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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.01 95.47 93.71 95.33 94.52 97.53 99.51


Total test records in report: 2938
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T1110 /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.890890657 Aug 11 08:05:12 PM PDT 24 Aug 11 09:12:08 PM PDT 24 15381769500 ps
T1111 /workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.4203039734 Aug 11 07:43:17 PM PDT 24 Aug 11 07:50:28 PM PDT 24 3741939192 ps
T333 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.1056655806 Aug 11 08:02:54 PM PDT 24 Aug 11 08:17:17 PM PDT 24 5141167382 ps
T891 /workspace/coverage/default/71.chip_sw_all_escalation_resets.45914226 Aug 11 08:24:30 PM PDT 24 Aug 11 08:35:40 PM PDT 24 4973643938 ps
T1112 /workspace/coverage/default/1.chip_sw_aon_timer_irq.4286570641 Aug 11 07:53:28 PM PDT 24 Aug 11 08:02:07 PM PDT 24 4419675414 ps
T844 /workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.447611010 Aug 11 08:21:04 PM PDT 24 Aug 11 08:27:41 PM PDT 24 3424756678 ps
T1113 /workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.1911057937 Aug 11 08:05:16 PM PDT 24 Aug 11 08:22:05 PM PDT 24 8267604360 ps
T1114 /workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.1419333142 Aug 11 07:41:09 PM PDT 24 Aug 11 07:49:30 PM PDT 24 4008159924 ps
T290 /workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.3625058609 Aug 11 07:58:35 PM PDT 24 Aug 11 08:02:19 PM PDT 24 2896330462 ps
T1115 /workspace/coverage/default/1.chip_sw_flash_crash_alert.2799355932 Aug 11 08:01:13 PM PDT 24 Aug 11 08:13:10 PM PDT 24 4250799624 ps
T1116 /workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.929841813 Aug 11 08:14:29 PM PDT 24 Aug 11 08:21:55 PM PDT 24 5972772704 ps
T1117 /workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.3841723414 Aug 11 07:58:41 PM PDT 24 Aug 11 08:07:10 PM PDT 24 4907743450 ps
T1118 /workspace/coverage/default/2.chip_sw_edn_auto_mode.2747768556 Aug 11 08:08:03 PM PDT 24 Aug 11 08:27:16 PM PDT 24 4491794004 ps
T1119 /workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.3375390869 Aug 11 08:08:54 PM PDT 24 Aug 11 08:28:08 PM PDT 24 5632902254 ps
T396 /workspace/coverage/default/2.chip_sw_kmac_app_rom.968650952 Aug 11 08:09:24 PM PDT 24 Aug 11 08:12:55 PM PDT 24 2270269280 ps
T1120 /workspace/coverage/default/2.chip_sw_aes_masking_off.2385419961 Aug 11 08:15:30 PM PDT 24 Aug 11 08:21:21 PM PDT 24 2886052783 ps
T237 /workspace/coverage/default/80.chip_sw_all_escalation_resets.1308195420 Aug 11 08:32:03 PM PDT 24 Aug 11 08:44:07 PM PDT 24 5439327128 ps
T1121 /workspace/coverage/default/2.chip_sw_kmac_smoketest.1455085782 Aug 11 08:13:34 PM PDT 24 Aug 11 08:18:28 PM PDT 24 3090838144 ps
T1122 /workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.996242386 Aug 11 08:03:54 PM PDT 24 Aug 11 08:11:52 PM PDT 24 3786385290 ps
T1123 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.3926251193 Aug 11 07:52:05 PM PDT 24 Aug 11 08:55:27 PM PDT 24 12012452824 ps
T1124 /workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.3478273908 Aug 11 07:39:59 PM PDT 24 Aug 11 07:49:29 PM PDT 24 4148131000 ps
T1125 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.778377605 Aug 11 07:54:23 PM PDT 24 Aug 11 09:00:08 PM PDT 24 17101703092 ps
T1126 /workspace/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.2765691831 Aug 11 07:37:58 PM PDT 24 Aug 11 07:40:56 PM PDT 24 2921126910 ps
T1127 /workspace/coverage/default/0.rom_keymgr_functest.2201308463 Aug 11 07:49:11 PM PDT 24 Aug 11 07:56:42 PM PDT 24 4486623668 ps
T252 /workspace/coverage/default/17.chip_sw_all_escalation_resets.4103270315 Aug 11 08:18:49 PM PDT 24 Aug 11 08:27:53 PM PDT 24 5188942228 ps
T1128 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2958950942 Aug 11 07:57:00 PM PDT 24 Aug 11 08:07:00 PM PDT 24 4714671264 ps
T1129 /workspace/coverage/default/8.chip_sw_lc_ctrl_transition.1909707690 Aug 11 08:17:29 PM PDT 24 Aug 11 08:27:52 PM PDT 24 7476345209 ps
T888 /workspace/coverage/default/26.chip_sw_all_escalation_resets.470273959 Aug 11 08:19:50 PM PDT 24 Aug 11 08:33:47 PM PDT 24 5830785934 ps
T1130 /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.1537418540 Aug 11 08:13:23 PM PDT 24 Aug 11 08:18:22 PM PDT 24 3653021366 ps
T543 /workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.3471899325 Aug 11 07:37:09 PM PDT 24 Aug 11 07:51:50 PM PDT 24 4375009404 ps
T364 /workspace/coverage/default/1.chip_sival_flash_info_access.3698509309 Aug 11 07:50:21 PM PDT 24 Aug 11 07:55:37 PM PDT 24 3494724100 ps
T1131 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.2616675943 Aug 11 07:56:18 PM PDT 24 Aug 11 09:51:07 PM PDT 24 23942867024 ps
T871 /workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.3679198833 Aug 11 08:16:30 PM PDT 24 Aug 11 08:23:27 PM PDT 24 4290185506 ps
T1132 /workspace/coverage/default/2.chip_sw_edn_sw_mode.3938984307 Aug 11 08:08:19 PM PDT 24 Aug 11 08:34:45 PM PDT 24 6392880576 ps
T1133 /workspace/coverage/default/57.chip_sw_all_escalation_resets.1851600503 Aug 11 08:24:12 PM PDT 24 Aug 11 08:35:06 PM PDT 24 5635173922 ps
T1134 /workspace/coverage/default/0.rom_e2e_asm_init_dev.2578355506 Aug 11 07:51:28 PM PDT 24 Aug 11 08:59:43 PM PDT 24 15608095044 ps
T1135 /workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.279676426 Aug 11 08:06:31 PM PDT 24 Aug 11 08:12:36 PM PDT 24 7373964692 ps
T223 /workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.11711241 Aug 11 08:02:34 PM PDT 24 Aug 11 08:10:26 PM PDT 24 3605298591 ps
T299 /workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.510695870 Aug 11 07:42:56 PM PDT 24 Aug 11 07:54:16 PM PDT 24 5157635666 ps
T803 /workspace/coverage/default/7.chip_sw_all_escalation_resets.3351577389 Aug 11 08:15:26 PM PDT 24 Aug 11 08:27:07 PM PDT 24 5882526728 ps
T213 /workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.178960076 Aug 11 08:09:17 PM PDT 24 Aug 11 08:34:58 PM PDT 24 7657660400 ps
T1136 /workspace/coverage/default/3.chip_sw_uart_tx_rx.1167310479 Aug 11 08:13:31 PM PDT 24 Aug 11 08:23:46 PM PDT 24 4488903720 ps
T1137 /workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.3339112950 Aug 11 07:54:00 PM PDT 24 Aug 11 08:10:21 PM PDT 24 7583592230 ps
T1138 /workspace/coverage/default/2.chip_sw_rv_timer_irq.3463165653 Aug 11 08:05:28 PM PDT 24 Aug 11 08:09:06 PM PDT 24 2399449608 ps
T1139 /workspace/coverage/default/2.chip_sw_otbn_smoketest.308927265 Aug 11 08:14:33 PM PDT 24 Aug 11 08:44:26 PM PDT 24 8314462336 ps
T1140 /workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.1515286476 Aug 11 08:01:57 PM PDT 24 Aug 11 08:11:34 PM PDT 24 4323749500 ps
T1141 /workspace/coverage/default/24.chip_sw_all_escalation_resets.3436762632 Aug 11 08:20:51 PM PDT 24 Aug 11 08:31:32 PM PDT 24 4382403624 ps
T224 /workspace/coverage/default/1.chip_sw_flash_init.31450434 Aug 11 07:50:14 PM PDT 24 Aug 11 08:30:56 PM PDT 24 22936054280 ps
T1142 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.400394425 Aug 11 07:36:23 PM PDT 24 Aug 11 07:45:10 PM PDT 24 5391300662 ps
T1143 /workspace/coverage/default/14.chip_sw_lc_ctrl_transition.2877875054 Aug 11 08:19:24 PM PDT 24 Aug 11 08:28:58 PM PDT 24 6725123940 ps
T1144 /workspace/coverage/default/15.chip_sw_uart_rand_baudrate.2924375382 Aug 11 08:19:07 PM PDT 24 Aug 11 08:28:54 PM PDT 24 4271124000 ps
T253 /workspace/coverage/default/30.chip_sw_all_escalation_resets.2313995249 Aug 11 08:20:24 PM PDT 24 Aug 11 08:29:20 PM PDT 24 4768534256 ps
T1145 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac.466481339 Aug 11 07:58:15 PM PDT 24 Aug 11 08:03:26 PM PDT 24 2954329656 ps
T866 /workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.310459472 Aug 11 08:17:15 PM PDT 24 Aug 11 08:24:44 PM PDT 24 4334447500 ps
T1146 /workspace/coverage/default/2.chip_sw_aes_smoketest.4205177948 Aug 11 08:15:05 PM PDT 24 Aug 11 08:19:05 PM PDT 24 3129854080 ps
T1147 /workspace/coverage/default/2.chip_sw_csrng_smoketest.1270029759 Aug 11 08:14:49 PM PDT 24 Aug 11 08:19:12 PM PDT 24 3061560412 ps
T1148 /workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.3002116026 Aug 11 08:10:01 PM PDT 24 Aug 11 08:19:32 PM PDT 24 5102043952 ps
T199 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.3783399961 Aug 11 07:53:04 PM PDT 24 Aug 11 08:53:35 PM PDT 24 20723854018 ps
T1149 /workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.3844936080 Aug 11 08:01:26 PM PDT 24 Aug 11 08:05:00 PM PDT 24 2998530284 ps
T1150 /workspace/coverage/default/19.chip_sw_uart_rand_baudrate.1852854740 Aug 11 08:18:49 PM PDT 24 Aug 11 08:44:42 PM PDT 24 8106127254 ps
T1151 /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.3157915123 Aug 11 07:41:34 PM PDT 24 Aug 11 07:55:18 PM PDT 24 9296564020 ps
T1152 /workspace/coverage/default/1.rom_keymgr_functest.1396813072 Aug 11 08:00:27 PM PDT 24 Aug 11 08:11:46 PM PDT 24 4382631976 ps
T353 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3276988568 Aug 11 08:11:34 PM PDT 24 Aug 11 08:23:42 PM PDT 24 5180482771 ps
T214 /workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.2626530117 Aug 11 07:38:26 PM PDT 24 Aug 11 08:05:34 PM PDT 24 8706226952 ps
T826 /workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.1018165759 Aug 11 08:17:50 PM PDT 24 Aug 11 08:24:01 PM PDT 24 3973744832 ps
T1153 /workspace/coverage/default/1.chip_sw_hmac_multistream.24638504 Aug 11 07:55:34 PM PDT 24 Aug 11 08:27:19 PM PDT 24 7446893396 ps
T1154 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.2664477297 Aug 11 07:50:11 PM PDT 24 Aug 11 09:08:07 PM PDT 24 15611101586 ps
T788 /workspace/coverage/default/0.rom_e2e_jtag_debug_rma.1373486069 Aug 11 07:48:33 PM PDT 24 Aug 11 08:27:47 PM PDT 24 11119202774 ps
T1155 /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2843035570 Aug 11 08:14:47 PM PDT 24 Aug 11 08:31:43 PM PDT 24 8449299242 ps
T1156 /workspace/coverage/default/1.chip_sw_aes_enc.3151046645 Aug 11 07:53:38 PM PDT 24 Aug 11 07:57:11 PM PDT 24 2884711800 ps
T1157 /workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.1790066040 Aug 11 08:14:57 PM PDT 24 Aug 11 09:07:33 PM PDT 24 12586401748 ps
T1158 /workspace/coverage/default/2.chip_sw_clkmgr_smoketest.1229291068 Aug 11 08:15:10 PM PDT 24 Aug 11 08:19:40 PM PDT 24 2844219980 ps
T895 /workspace/coverage/default/6.chip_sw_all_escalation_resets.1323832788 Aug 11 08:16:19 PM PDT 24 Aug 11 08:26:49 PM PDT 24 4915196816 ps
T1159 /workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.489646859 Aug 11 08:18:01 PM PDT 24 Aug 11 09:05:37 PM PDT 24 11485693697 ps
T1160 /workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.333427700 Aug 11 07:41:50 PM PDT 24 Aug 11 07:48:06 PM PDT 24 3851354664 ps
T1161 /workspace/coverage/default/0.chip_sw_rstmgr_sw_req.3655419266 Aug 11 07:35:53 PM PDT 24 Aug 11 07:45:02 PM PDT 24 5268565928 ps
T1162 /workspace/coverage/default/0.chip_sw_aes_enc.1795560988 Aug 11 07:38:00 PM PDT 24 Aug 11 07:41:38 PM PDT 24 2820113560 ps
T1163 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.224349998 Aug 11 07:42:12 PM PDT 24 Aug 11 07:54:53 PM PDT 24 4584793932 ps
T349 /workspace/coverage/default/1.chip_sw_pattgen_ios.480849557 Aug 11 07:50:03 PM PDT 24 Aug 11 07:53:30 PM PDT 24 2882944736 ps
T1164 /workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.1234667397 Aug 11 08:05:53 PM PDT 24 Aug 11 08:37:02 PM PDT 24 12257945370 ps
T1165 /workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.2350213405 Aug 11 07:37:59 PM PDT 24 Aug 11 07:43:30 PM PDT 24 3160393748 ps
T1166 /workspace/coverage/default/0.chip_sw_aes_masking_off.2909641914 Aug 11 07:38:00 PM PDT 24 Aug 11 07:42:03 PM PDT 24 2766611173 ps
T1167 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.1254287267 Aug 11 08:05:32 PM PDT 24 Aug 11 08:54:08 PM PDT 24 39289838660 ps
T1168 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.1863705203 Aug 11 07:53:17 PM PDT 24 Aug 11 07:57:27 PM PDT 24 3256160190 ps
T816 /workspace/coverage/default/18.chip_sw_all_escalation_resets.3134890459 Aug 11 08:18:01 PM PDT 24 Aug 11 08:25:36 PM PDT 24 5273535812 ps
T750 /workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.2279587909 Aug 11 08:03:23 PM PDT 24 Aug 11 08:06:05 PM PDT 24 4046424192 ps
T127 /workspace/coverage/default/0.chip_sw_ast_clk_rst_inputs.1849348512 Aug 11 07:45:56 PM PDT 24 Aug 11 08:58:07 PM PDT 24 23951155346 ps
T729 /workspace/coverage/default/2.chip_sw_edn_boot_mode.2638297961 Aug 11 08:08:41 PM PDT 24 Aug 11 08:17:09 PM PDT 24 2558761152 ps
T1169 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.604350347 Aug 11 07:58:34 PM PDT 24 Aug 11 08:20:59 PM PDT 24 13327601511 ps
T858 /workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.1220066427 Aug 11 08:22:51 PM PDT 24 Aug 11 08:28:02 PM PDT 24 3620835898 ps
T1170 /workspace/coverage/default/0.chip_sw_ast_clk_outputs.3728282137 Aug 11 07:46:19 PM PDT 24 Aug 11 07:59:34 PM PDT 24 6786756266 ps
T1171 /workspace/coverage/default/0.rom_e2e_smoke.1212469092 Aug 11 07:49:51 PM PDT 24 Aug 11 09:05:59 PM PDT 24 14639876576 ps
T238 /workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.2909050753 Aug 11 08:20:14 PM PDT 24 Aug 11 08:26:59 PM PDT 24 4328583860 ps
T1172 /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.1775245837 Aug 11 08:13:46 PM PDT 24 Aug 11 08:25:03 PM PDT 24 3982014604 ps
T298 /workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.268206542 Aug 11 08:10:09 PM PDT 24 Aug 11 08:25:15 PM PDT 24 8753610263 ps
T1173 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.1113707416 Aug 11 07:51:36 PM PDT 24 Aug 11 09:09:20 PM PDT 24 18258506515 ps
T1174 /workspace/coverage/default/0.chip_sw_aes_idle.607569982 Aug 11 07:38:12 PM PDT 24 Aug 11 07:41:05 PM PDT 24 2393134440 ps
T828 /workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.614187572 Aug 11 08:21:19 PM PDT 24 Aug 11 08:27:34 PM PDT 24 4166016600 ps
T1175 /workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.1997966998 Aug 11 07:43:56 PM PDT 24 Aug 11 08:29:21 PM PDT 24 23420850273 ps
T829 /workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.4190352720 Aug 11 08:20:42 PM PDT 24 Aug 11 08:26:34 PM PDT 24 3338945722 ps
T370 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.926147217 Aug 11 07:39:40 PM PDT 24 Aug 11 08:05:05 PM PDT 24 13576350008 ps
T1176 /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.2372643902 Aug 11 07:51:55 PM PDT 24 Aug 11 09:01:28 PM PDT 24 14742152368 ps
T26 /workspace/coverage/default/2.chip_sw_gpio.2909557412 Aug 11 08:02:15 PM PDT 24 Aug 11 08:09:48 PM PDT 24 4078476230 ps
T1177 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.1901315868 Aug 11 08:07:01 PM PDT 24 Aug 11 08:28:36 PM PDT 24 8972702740 ps
T368 /workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.217583023 Aug 11 07:43:42 PM PDT 24 Aug 11 07:48:39 PM PDT 24 5967179000 ps
T1178 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1365677166 Aug 11 07:36:05 PM PDT 24 Aug 11 07:55:10 PM PDT 24 10599168762 ps
T1179 /workspace/coverage/default/13.chip_sw_uart_rand_baudrate.1354494729 Aug 11 08:16:36 PM PDT 24 Aug 11 08:42:27 PM PDT 24 8553666648 ps
T271 /workspace/coverage/default/1.chip_sw_otbn_mem_scramble.4002049867 Aug 11 07:55:16 PM PDT 24 Aug 11 08:03:47 PM PDT 24 3381350280 ps
T1180 /workspace/coverage/default/0.chip_sw_flash_ctrl_access.1013072366 Aug 11 07:34:35 PM PDT 24 Aug 11 07:50:16 PM PDT 24 5749085134 ps
T1181 /workspace/coverage/default/1.chip_sw_ast_clk_outputs.3563944255 Aug 11 08:00:23 PM PDT 24 Aug 11 08:16:24 PM PDT 24 6414458824 ps
T840 /workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.3882841727 Aug 11 08:24:53 PM PDT 24 Aug 11 08:31:51 PM PDT 24 3388853718 ps
T1182 /workspace/coverage/default/1.chip_sw_uart_rand_baudrate.3999453759 Aug 11 07:50:45 PM PDT 24 Aug 11 08:23:25 PM PDT 24 8340378480 ps
T1183 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3374755380 Aug 11 07:53:57 PM PDT 24 Aug 11 08:03:04 PM PDT 24 6252642444 ps
T1184 /workspace/coverage/default/0.chip_sw_aes_smoketest.4281144829 Aug 11 07:49:42 PM PDT 24 Aug 11 07:53:51 PM PDT 24 2309192604 ps
T1185 /workspace/coverage/default/11.chip_sw_uart_rand_baudrate.2084892534 Aug 11 08:16:17 PM PDT 24 Aug 11 08:25:18 PM PDT 24 3761950472 ps
T1186 /workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.1869164954 Aug 11 07:52:22 PM PDT 24 Aug 11 08:01:26 PM PDT 24 4683136000 ps
T1187 /workspace/coverage/default/0.chip_sw_flash_ctrl_write_clear.323780767 Aug 11 07:44:23 PM PDT 24 Aug 11 07:50:10 PM PDT 24 3089062392 ps
T1188 /workspace/coverage/default/2.chip_sw_example_concurrency.170098888 Aug 11 08:04:48 PM PDT 24 Aug 11 08:09:56 PM PDT 24 2831849532 ps
T806 /workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.1899200364 Aug 11 08:22:10 PM PDT 24 Aug 11 08:29:20 PM PDT 24 3988626750 ps
T1189 /workspace/coverage/default/1.chip_sw_kmac_idle.2450988071 Aug 11 07:58:31 PM PDT 24 Aug 11 08:04:25 PM PDT 24 2500769914 ps
T824 /workspace/coverage/default/9.chip_sw_all_escalation_resets.1359375808 Aug 11 08:16:10 PM PDT 24 Aug 11 08:25:47 PM PDT 24 5555130448 ps
T149 /workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.3958002885 Aug 11 08:10:28 PM PDT 24 Aug 11 08:15:23 PM PDT 24 2612224818 ps
T884 /workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.854048136 Aug 11 08:19:51 PM PDT 24 Aug 11 08:26:12 PM PDT 24 3193501096 ps
T1190 /workspace/coverage/default/1.rom_e2e_self_hash.1021503428 Aug 11 08:05:29 PM PDT 24 Aug 11 09:51:34 PM PDT 24 26460383830 ps
T1191 /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2165508850 Aug 11 08:04:25 PM PDT 24 Aug 11 08:16:06 PM PDT 24 4217350356 ps
T835 /workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.356231566 Aug 11 08:18:06 PM PDT 24 Aug 11 08:27:29 PM PDT 24 3906678170 ps
T1192 /workspace/coverage/default/1.chip_sw_clkmgr_off_peri.2498502826 Aug 11 08:00:58 PM PDT 24 Aug 11 08:19:14 PM PDT 24 10535119800 ps
T41 /workspace/coverage/default/2.chip_sw_spi_device_tpm.368090715 Aug 11 08:03:43 PM PDT 24 Aug 11 08:10:01 PM PDT 24 3466881511 ps
T873 /workspace/coverage/default/23.chip_sw_all_escalation_resets.1898424320 Aug 11 08:20:32 PM PDT 24 Aug 11 08:31:50 PM PDT 24 6075406416 ps
T855 /workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.526662566 Aug 11 08:21:14 PM PDT 24 Aug 11 08:28:59 PM PDT 24 4077891156 ps
T62 /workspace/coverage/default/4.chip_tap_straps_testunlock0.2748976094 Aug 11 08:14:05 PM PDT 24 Aug 11 08:22:47 PM PDT 24 5472365447 ps
T1193 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.2383735293 Aug 11 07:51:36 PM PDT 24 Aug 11 08:03:03 PM PDT 24 4954421040 ps
T150 /workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.2427469640 Aug 11 07:35:59 PM PDT 24 Aug 11 07:39:13 PM PDT 24 2742260269 ps
T763 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.3862259047 Aug 11 07:37:15 PM PDT 24 Aug 11 07:42:19 PM PDT 24 3369336710 ps
T1194 /workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.1688892588 Aug 11 08:18:24 PM PDT 24 Aug 11 08:23:58 PM PDT 24 4231995434 ps
T1195 /workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.2429991375 Aug 11 07:54:30 PM PDT 24 Aug 11 08:04:17 PM PDT 24 5332976316 ps
T1196 /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.869056386 Aug 11 08:16:05 PM PDT 24 Aug 11 08:50:55 PM PDT 24 13163679133 ps
T1197 /workspace/coverage/default/0.chip_sw_rstmgr_smoketest.2097884457 Aug 11 07:51:16 PM PDT 24 Aug 11 07:55:25 PM PDT 24 3185739268 ps
T1198 /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2042324185 Aug 11 07:33:46 PM PDT 24 Aug 11 07:39:45 PM PDT 24 3710553634 ps
T1199 /workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.1441337292 Aug 11 07:33:57 PM PDT 24 Aug 11 07:54:18 PM PDT 24 9854097240 ps
T1200 /workspace/coverage/default/4.chip_tap_straps_prod.2621313343 Aug 11 08:13:58 PM PDT 24 Aug 11 08:26:23 PM PDT 24 8342665804 ps
T1201 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.963785952 Aug 11 07:54:56 PM PDT 24 Aug 11 08:17:40 PM PDT 24 9669198487 ps
T892 /workspace/coverage/default/97.chip_sw_all_escalation_resets.2231178303 Aug 11 08:25:12 PM PDT 24 Aug 11 08:36:41 PM PDT 24 5196248288 ps
T810 /workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.3801432600 Aug 11 08:24:53 PM PDT 24 Aug 11 08:30:49 PM PDT 24 3648475056 ps
T227 /workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.3254598881 Aug 11 08:03:07 PM PDT 24 Aug 11 09:30:11 PM PDT 24 49923807171 ps
T1202 /workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.2873068101 Aug 11 08:24:10 PM PDT 24 Aug 11 08:31:46 PM PDT 24 4478134830 ps
T337 /workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.195777389 Aug 11 07:42:15 PM PDT 24 Aug 11 07:49:44 PM PDT 24 4313980436 ps
T1203 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.1426542437 Aug 11 07:42:16 PM PDT 24 Aug 11 07:51:26 PM PDT 24 4641130164 ps
T1204 /workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.4101764941 Aug 11 08:18:24 PM PDT 24 Aug 11 09:05:36 PM PDT 24 11342170854 ps
T354 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops.751102799 Aug 11 07:50:18 PM PDT 24 Aug 11 07:59:52 PM PDT 24 3727553228 ps
T1205 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.3826305652 Aug 11 07:51:51 PM PDT 24 Aug 11 08:02:22 PM PDT 24 4134377940 ps
T1206 /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.2829999614 Aug 11 08:15:52 PM PDT 24 Aug 11 09:18:47 PM PDT 24 15218783832 ps
T96 /workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.123210562 Aug 11 07:43:52 PM PDT 24 Aug 11 07:50:20 PM PDT 24 4524238072 ps
T428 /workspace/coverage/default/0.chip_sw_edn_boot_mode.320002113 Aug 11 07:37:58 PM PDT 24 Aug 11 07:48:19 PM PDT 24 3391435490 ps
T429 /workspace/coverage/default/0.rom_volatile_raw_unlock.1351411236 Aug 11 07:51:18 PM PDT 24 Aug 11 07:53:14 PM PDT 24 2732635732 ps
T430 /workspace/coverage/default/0.chip_sw_clkmgr_smoketest.1310290410 Aug 11 07:48:57 PM PDT 24 Aug 11 07:52:25 PM PDT 24 2578468212 ps
T67 /workspace/coverage/default/0.chip_sw_usbdev_pincfg.1789483450 Aug 11 07:33:34 PM PDT 24 Aug 11 09:27:32 PM PDT 24 31259950072 ps
T431 /workspace/coverage/default/77.chip_sw_all_escalation_resets.2784514718 Aug 11 08:24:58 PM PDT 24 Aug 11 08:35:36 PM PDT 24 4968927080 ps
T432 /workspace/coverage/default/28.chip_sw_all_escalation_resets.2828961711 Aug 11 08:19:36 PM PDT 24 Aug 11 08:29:16 PM PDT 24 4578325392 ps
T433 /workspace/coverage/default/4.chip_sw_uart_rand_baudrate.2444250056 Aug 11 08:14:27 PM PDT 24 Aug 11 08:25:34 PM PDT 24 4494199040 ps
T434 /workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.2033391334 Aug 11 08:07:29 PM PDT 24 Aug 11 08:18:00 PM PDT 24 5291714640 ps
T435 /workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.2609143944 Aug 11 08:15:14 PM PDT 24 Aug 11 08:18:00 PM PDT 24 3195569396 ps
T1207 /workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.2736634829 Aug 11 07:51:58 PM PDT 24 Aug 11 07:57:07 PM PDT 24 3418972496 ps
T397 /workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.3818191516 Aug 11 07:39:53 PM PDT 24 Aug 11 07:48:53 PM PDT 24 9094330675 ps
T751 /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.1736830740 Aug 11 08:04:11 PM PDT 24 Aug 11 08:05:43 PM PDT 24 1739605350 ps
T1208 /workspace/coverage/default/1.chip_sw_entropy_src_smoketest.115383141 Aug 11 08:01:01 PM PDT 24 Aug 11 08:09:08 PM PDT 24 3726261810 ps
T1209 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1544279494 Aug 11 08:00:38 PM PDT 24 Aug 11 08:06:08 PM PDT 24 2982689332 ps
T865 /workspace/coverage/default/88.chip_sw_all_escalation_resets.521128346 Aug 11 08:25:42 PM PDT 24 Aug 11 08:37:35 PM PDT 24 5898009952 ps
T811 /workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.4001311859 Aug 11 08:23:22 PM PDT 24 Aug 11 08:30:17 PM PDT 24 4342448330 ps
T350 /workspace/coverage/default/0.chip_sw_pattgen_ios.2974812944 Aug 11 07:33:36 PM PDT 24 Aug 11 07:39:06 PM PDT 24 3195323512 ps
T1210 /workspace/coverage/default/0.chip_sw_usbdev_setuprx.1229490378 Aug 11 07:36:23 PM PDT 24 Aug 11 07:45:08 PM PDT 24 3191660430 ps
T1211 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.1295692974 Aug 11 07:49:48 PM PDT 24 Aug 11 09:02:08 PM PDT 24 14629742000 ps
T807 /workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.301642942 Aug 11 08:21:56 PM PDT 24 Aug 11 08:27:22 PM PDT 24 2943795560 ps
T1212 /workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.2693291316 Aug 11 07:46:01 PM PDT 24 Aug 11 08:03:49 PM PDT 24 5632683900 ps
T1213 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.1868093009 Aug 11 07:40:06 PM PDT 24 Aug 11 08:19:45 PM PDT 24 8492582696 ps
T1214 /workspace/coverage/default/1.chip_sw_example_rom.2473676557 Aug 11 07:49:51 PM PDT 24 Aug 11 07:52:07 PM PDT 24 2713439010 ps
T1215 /workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.1246723859 Aug 11 07:37:15 PM PDT 24 Aug 11 07:45:59 PM PDT 24 4419373390 ps
T1216 /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.1559910665 Aug 11 08:15:20 PM PDT 24 Aug 11 08:20:19 PM PDT 24 2605925285 ps
T200 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_outputs.554700915 Aug 11 07:36:56 PM PDT 24 Aug 11 07:43:21 PM PDT 24 3902341800 ps
T874 /workspace/coverage/default/49.chip_sw_all_escalation_resets.1176271964 Aug 11 08:23:01 PM PDT 24 Aug 11 08:34:07 PM PDT 24 4819148568 ps
T752 /workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.1068813685 Aug 11 07:53:27 PM PDT 24 Aug 11 07:58:35 PM PDT 24 3988524249 ps
T1217 /workspace/coverage/default/0.chip_sw_example_manufacturer.2395064907 Aug 11 07:34:20 PM PDT 24 Aug 11 07:36:59 PM PDT 24 2233013742 ps
T1218 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3249660330 Aug 11 07:34:29 PM PDT 24 Aug 11 07:43:47 PM PDT 24 4652516722 ps
T875 /workspace/coverage/default/11.chip_sw_all_escalation_resets.3789350561 Aug 11 08:17:40 PM PDT 24 Aug 11 08:27:07 PM PDT 24 6389347624 ps
T1219 /workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.1135260071 Aug 11 07:52:12 PM PDT 24 Aug 11 08:38:42 PM PDT 24 31038217660 ps
T76 /workspace/coverage/default/0.chip_jtag_csr_rw.103352071 Aug 11 07:35:45 PM PDT 24 Aug 11 07:41:39 PM PDT 24 4299435805 ps
T833 /workspace/coverage/default/66.chip_sw_all_escalation_resets.2600543306 Aug 11 08:23:31 PM PDT 24 Aug 11 08:35:13 PM PDT 24 6773995992 ps
T1220 /workspace/coverage/default/2.chip_sw_alert_handler_entropy.2904759628 Aug 11 08:07:45 PM PDT 24 Aug 11 08:12:57 PM PDT 24 3234363618 ps
T1221 /workspace/coverage/default/1.chip_sw_rv_timer_irq.3591521386 Aug 11 07:53:07 PM PDT 24 Aug 11 07:58:00 PM PDT 24 2758398820 ps
T1222 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.533200995 Aug 11 07:51:13 PM PDT 24 Aug 11 08:59:22 PM PDT 24 15272031326 ps
T1223 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.50038534 Aug 11 07:50:27 PM PDT 24 Aug 11 08:59:09 PM PDT 24 15800206440 ps
T37 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2766700895 Aug 11 08:07:02 PM PDT 24 Aug 11 08:13:31 PM PDT 24 5220332508 ps
T1224 /workspace/coverage/default/2.chip_sw_example_rom.2626333221 Aug 11 08:01:44 PM PDT 24 Aug 11 08:03:40 PM PDT 24 1950470882 ps
T254 /workspace/coverage/default/41.chip_sw_all_escalation_resets.58558810 Aug 11 08:20:37 PM PDT 24 Aug 11 08:30:32 PM PDT 24 5150402000 ps
T132 /workspace/coverage/default/1.chip_jtag_csr_rw.2629512199 Aug 11 07:50:35 PM PDT 24 Aug 11 07:55:08 PM PDT 24 4204088050 ps
T1225 /workspace/coverage/default/2.chip_sw_flash_ctrl_write_clear.99703091 Aug 11 08:12:14 PM PDT 24 Aug 11 08:18:54 PM PDT 24 3355328260 ps
T1226 /workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.3813546833 Aug 11 07:36:42 PM PDT 24 Aug 11 07:40:46 PM PDT 24 2730365564 ps
T1227 /workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.863179858 Aug 11 07:52:18 PM PDT 24 Aug 11 08:46:30 PM PDT 24 11883678344 ps
T1228 /workspace/coverage/default/0.chip_sw_kmac_smoketest.240929805 Aug 11 07:48:48 PM PDT 24 Aug 11 07:54:04 PM PDT 24 3318102660 ps
T880 /workspace/coverage/default/56.chip_sw_all_escalation_resets.2422121053 Aug 11 08:22:16 PM PDT 24 Aug 11 08:31:02 PM PDT 24 4664428010 ps
T1229 /workspace/coverage/default/2.rom_e2e_asm_init_prod_end.3052827788 Aug 11 08:16:05 PM PDT 24 Aug 11 09:20:58 PM PDT 24 14977561085 ps
T1230 /workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.3321851600 Aug 11 08:20:52 PM PDT 24 Aug 11 08:27:15 PM PDT 24 4176913200 ps
T869 /workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.697729134 Aug 11 08:17:50 PM PDT 24 Aug 11 08:25:16 PM PDT 24 3683821904 ps
T851 /workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.1669292680 Aug 11 08:33:43 PM PDT 24 Aug 11 08:39:50 PM PDT 24 3752976640 ps
T1231 /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.3977812012 Aug 11 08:13:01 PM PDT 24 Aug 11 08:17:34 PM PDT 24 3288497801 ps
T1232 /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.791568259 Aug 11 07:35:31 PM PDT 24 Aug 11 07:37:17 PM PDT 24 2477309586 ps
T1233 /workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.2639721157 Aug 11 07:39:59 PM PDT 24 Aug 11 08:08:07 PM PDT 24 11638135602 ps
T1234 /workspace/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.1220626178 Aug 11 08:03:24 PM PDT 24 Aug 11 08:08:03 PM PDT 24 2921658904 ps
T1235 /workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.3047985302 Aug 11 07:53:25 PM PDT 24 Aug 11 08:08:39 PM PDT 24 5196464084 ps
T1236 /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.1373735389 Aug 11 08:06:49 PM PDT 24 Aug 11 09:17:08 PM PDT 24 17050137732 ps
T1237 /workspace/coverage/default/64.chip_sw_all_escalation_resets.3591883244 Aug 11 08:23:28 PM PDT 24 Aug 11 08:33:35 PM PDT 24 5188676248 ps
T228 /workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.2369552835 Aug 11 07:34:59 PM PDT 24 Aug 11 07:41:34 PM PDT 24 4257190141 ps
T142 /workspace/coverage/default/2.chip_plic_all_irqs_10.1195766737 Aug 11 08:10:14 PM PDT 24 Aug 11 08:20:26 PM PDT 24 4233231320 ps
T1238 /workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.1770555169 Aug 11 08:14:45 PM PDT 24 Aug 11 08:20:07 PM PDT 24 5834587302 ps
T272 /workspace/coverage/default/2.chip_sw_otbn_mem_scramble.4131751684 Aug 11 08:07:00 PM PDT 24 Aug 11 08:15:13 PM PDT 24 3992094344 ps
T1239 /workspace/coverage/default/0.chip_sw_hmac_enc.3448741598 Aug 11 07:38:51 PM PDT 24 Aug 11 07:43:13 PM PDT 24 3102214040 ps
T1240 /workspace/coverage/default/1.chip_sw_example_manufacturer.3615880772 Aug 11 07:50:43 PM PDT 24 Aug 11 07:54:17 PM PDT 24 2979544664 ps
T225 /workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.1607732773 Aug 11 07:58:00 PM PDT 24 Aug 11 08:34:23 PM PDT 24 21773145423 ps
T119 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3483738634 Aug 11 07:57:00 PM PDT 24 Aug 11 08:04:59 PM PDT 24 5427822666 ps
T1241 /workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.2200475346 Aug 11 08:15:15 PM PDT 24 Aug 11 08:51:06 PM PDT 24 9389580408 ps
T1242 /workspace/coverage/default/2.chip_sw_lc_ctrl_transition.2162995111 Aug 11 08:04:36 PM PDT 24 Aug 11 08:11:10 PM PDT 24 4981216672 ps
T1243 /workspace/coverage/default/1.rom_e2e_shutdown_output.2074926927 Aug 11 08:07:13 PM PDT 24 Aug 11 09:12:07 PM PDT 24 25111042216 ps
T1244 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.549817373 Aug 11 07:38:58 PM PDT 24 Aug 11 07:58:32 PM PDT 24 8087493376 ps
T63 /workspace/coverage/default/3.chip_tap_straps_rma.3620439626 Aug 11 08:16:44 PM PDT 24 Aug 11 08:21:42 PM PDT 24 3904653579 ps
T1245 /workspace/coverage/default/0.rom_e2e_shutdown_exception_c.4053339679 Aug 11 07:49:19 PM PDT 24 Aug 11 08:53:24 PM PDT 24 14627730314 ps
T789 /workspace/coverage/default/0.rom_e2e_jtag_debug_dev.4121629416 Aug 11 07:49:12 PM PDT 24 Aug 11 08:22:16 PM PDT 24 11256609177 ps
T1246 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.1131123018 Aug 11 08:10:01 PM PDT 24 Aug 11 08:20:14 PM PDT 24 5779342942 ps
T879 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.2919661269 Aug 11 08:07:45 PM PDT 24 Aug 11 08:15:48 PM PDT 24 4393558104 ps
T1247 /workspace/coverage/default/0.chip_sw_example_flash.3911748031 Aug 11 07:33:38 PM PDT 24 Aug 11 07:37:48 PM PDT 24 2697875780 ps
T1248 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.720217641 Aug 11 08:11:31 PM PDT 24 Aug 11 08:26:47 PM PDT 24 5246966002 ps
T1249 /workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.98917528 Aug 11 08:06:33 PM PDT 24 Aug 11 08:23:32 PM PDT 24 5714193896 ps
T1250 /workspace/coverage/default/4.chip_tap_straps_dev.3417176034 Aug 11 08:15:32 PM PDT 24 Aug 11 08:19:18 PM PDT 24 3151463364 ps
T1251 /workspace/coverage/default/0.chip_sw_entropy_src_kat_test.1814153615 Aug 11 07:39:09 PM PDT 24 Aug 11 07:42:13 PM PDT 24 3444210880 ps
T837 /workspace/coverage/default/36.chip_sw_all_escalation_resets.2687218380 Aug 11 08:21:46 PM PDT 24 Aug 11 08:31:48 PM PDT 24 4815496284 ps
T1252 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.598569291 Aug 11 08:06:25 PM PDT 24 Aug 11 08:14:49 PM PDT 24 7507506860 ps
T1253 /workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.1885965746 Aug 11 08:10:35 PM PDT 24 Aug 11 08:17:59 PM PDT 24 3812858488 ps
T1254 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.3426433312 Aug 11 07:51:41 PM PDT 24 Aug 11 08:57:20 PM PDT 24 14626929057 ps
T889 /workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.1558025252 Aug 11 08:25:14 PM PDT 24 Aug 11 08:32:07 PM PDT 24 4212091850 ps
T273 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2401037583 Aug 11 08:12:25 PM PDT 24 Aug 11 08:24:35 PM PDT 24 4952360890 ps
T1255 /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.34366965 Aug 11 08:02:51 PM PDT 24 Aug 11 08:31:46 PM PDT 24 9383526902 ps
T1256 /workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.1263349995 Aug 11 08:01:46 PM PDT 24 Aug 11 08:26:12 PM PDT 24 9377918878 ps
T341 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.959596991 Aug 11 07:35:01 PM PDT 24 Aug 11 07:46:59 PM PDT 24 5099526165 ps
T51 /workspace/coverage/default/1.chip_sw_alert_test.1921172048 Aug 11 07:54:51 PM PDT 24 Aug 11 07:59:52 PM PDT 24 2904262932 ps
T279 /workspace/coverage/default/98.chip_sw_all_escalation_resets.339553505 Aug 11 08:25:45 PM PDT 24 Aug 11 08:36:49 PM PDT 24 4759511480 ps
T863 /workspace/coverage/default/1.chip_sw_all_escalation_resets.1260745085 Aug 11 07:50:02 PM PDT 24 Aug 11 08:04:14 PM PDT 24 6373431864 ps
T274 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.846576128 Aug 11 07:39:11 PM PDT 24 Aug 11 07:48:32 PM PDT 24 4205872048 ps
T1257 /workspace/coverage/default/2.chip_sw_entropy_src_smoketest.1464871176 Aug 11 08:12:45 PM PDT 24 Aug 11 08:21:14 PM PDT 24 4204791116 ps
T1258 /workspace/coverage/default/0.chip_sw_example_concurrency.1468025020 Aug 11 07:34:14 PM PDT 24 Aug 11 07:39:07 PM PDT 24 2768818308 ps
T124 /workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.2018118176 Aug 11 08:15:46 PM PDT 24 Aug 11 08:27:38 PM PDT 24 5058461930 ps
T845 /workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.451145706 Aug 11 08:20:28 PM PDT 24 Aug 11 08:27:20 PM PDT 24 4190886998 ps
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