Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_pwm_aon.u_reg.u_invert_cdc

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.08	100.00	92.31			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.22	100.00	96.88			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.26	99.77	97.26			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.88	90.91	84.62			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.38	94.00	87.50			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.26	99.77	97.26			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	93.79	93.33	81.82			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.08	100.00	92.31			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.22	100.00	96.88			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.26	99.77	97.26			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.08	100.00	92.31			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.22	100.00	96.88			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.26	99.77	97.26			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.88	90.91	84.62			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.38	94.00	87.50			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.26	99.77	97.26			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	93.79	93.33	81.82			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.08	100.00	92.31			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.22	100.00	96.88			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.26	99.77	97.26			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.88	90.91	84.62			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.38	94.00	87.50			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.26	99.77	97.26			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	93.79	93.33	81.82			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.88	90.91	84.62			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.38	94.00	87.50			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.26	99.77	97.26			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	93.79	93.33	81.82			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.26	99.77	97.26			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.26	99.77	97.26			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.26	99.77	97.26			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.26	99.77	97.26			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.26	99.77	97.26			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.26	99.77	97.26			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.26	99.77	97.26			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.26	99.77	97.26			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.26	99.77	97.26			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.26	99.77	97.26			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T15,T49,T99

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T15,T49,T99
1	1	Covered	T15,T49,T99

 LINE       123
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T15,T49,T99
1	-	Covered	T15,T49,T99

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T15,T49,T99

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T15,T49,T99
1	1	Covered	T15,T49,T99

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T15,T49,T99
0	0	1	Covered	T15,T49,T99
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T15,T49,T99
0	0	1	Covered	T15,T49,T99
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	156628801	99503	0	0
DstReqKnown_A	1898302	1671526	0	0
SrcAckBusyChk_A	156628801	252	0	0
SrcBusyKnown_A	156628801	155803222	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156628801	99503	0	0
T15	42699	735	0	0
T49	0	1780	0	0
T50	0	840	0	0
T51	0	951	0	0
T52	0	261	0	0
T53	0	1901	0	0
T54	0	2197	0	0
T99	0	911	0	0
T134	85000	0	0	0
T150	0	600	0	0
T151	0	617	0	0
T154	55223	0	0	0
T235	95175	0	0	0
T296	394225	0	0	0
T297	10842	0	0	0
T298	22652	0	0	0
T299	24928	0	0	0
T300	210746	0	0	0
T428	66990	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1898302	1671526	0	0
T1	762	589	0	0
T2	707	533	0	0
T3	730	556	0	0
T4	4635	3999	0	0
T5	647	475	0	0
T6	8871	8573	0	0
T43	2894	2720	0	0
T45	688	516	0	0
T61	734	559	0	0
T83	498	326	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156628801	252	0	0
T15	42699	2	0	0
T49	0	4	0	0
T50	0	2	0	0
T51	0	2	0	0
T52	0	1	0	0
T53	0	5	0	0
T54	0	5	0	0
T99	0	2	0	0
T134	85000	0	0	0
T150	0	2	0	0
T151	0	2	0	0
T154	55223	0	0	0
T235	95175	0	0	0
T296	394225	0	0	0
T297	10842	0	0	0
T298	22652	0	0	0
T299	24928	0	0	0
T300	210746	0	0	0
T428	66990	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156628801	155803222	0	0
T1	66806	65768	0	0
T2	54508	54070	0	0
T3	53256	52617	0	0
T4	303847	299192	0	0
T5	43099	42674	0	0
T6	995134	993382	0	0
T43	310032	309701	0	0
T45	62854	62002	0	0
T61	55723	54983	0	0
T83	35686	35049	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	20	90.91
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	0	0.00
CONT_ASSIGN	156	1	0	0.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	0	1
156	0	1
200	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc

	Total	Covered	Percent
Conditions	13	11	84.62
Logical	13	11	84.62
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T52,T429,T150

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T52,T150,T151
1	1	Covered	T52,T150,T151

 LINE       123
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T52,T150,T151
1	-	Not Covered

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T52,T150,T151

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T52,T150,T151
1	1	Covered	T52,T150,T151

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T52,T150,T151
0	0	1	Covered	T52,T150,T151
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T52,T150,T151
0	0	1	Covered	T52,T150,T151
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	156628801	95046	0	0
DstReqKnown_A	1898302	1671526	0	0
SrcAckBusyChk_A	156628801	240	0	0
SrcBusyKnown_A	156628801	155803222	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156628801	95046	0	0
T52	433960	266	0	0
T56	22304	0	0	0
T150	0	567	0	0
T151	0	622	0	0
T172	63162	0	0	0
T218	62222	0	0	0
T387	0	4047	0	0
T388	0	1219	0	0
T390	0	694	0	0
T391	0	295	0	0
T426	0	321	0	0
T427	0	381	0	0
T430	0	806	0	0
T431	14801	0	0	0
T432	18614	0	0	0
T433	112595	0	0	0
T434	56175	0	0	0
T435	54086	0	0	0
T436	42561	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1898302	1671526	0	0
T1	762	589	0	0
T2	707	533	0	0
T3	730	556	0	0
T4	4635	3999	0	0
T5	647	475	0	0
T6	8871	8573	0	0
T43	2894	2720	0	0
T45	688	516	0	0
T61	734	559	0	0
T83	498	326	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156628801	240	0	0
T52	433960	1	0	0
T56	22304	0	0	0
T150	0	2	0	0
T151	0	2	0	0
T172	63162	0	0	0
T218	62222	0	0	0
T387	0	9	0	0
T388	0	3	0	0
T390	0	2	0	0
T391	0	1	0	0
T426	0	1	0	0
T427	0	1	0	0
T430	0	2	0	0
T431	14801	0	0	0
T432	18614	0	0	0
T433	112595	0	0	0
T434	56175	0	0	0
T435	54086	0	0	0
T436	42561	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156628801	155803222	0	0
T1	66806	65768	0	0
T2	54508	54070	0	0
T3	53256	52617	0	0
T4	303847	299192	0	0
T5	43099	42674	0	0
T6	995134	993382	0	0
T43	310032	309701	0	0
T45	62854	62002	0	0
T61	55723	54983	0	0
T83	35686	35049	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T52,T55,T150

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T52,T55,T150
1	1	Covered	T52,T55,T150

 LINE       123
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T52,T55,T150
1	-	Covered	T55

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T52,T55,T150

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T52,T55,T150
1	1	Covered	T52,T55,T150

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T52,T55,T150
0	0	1	Covered	T52,T55,T150
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T52,T55,T150
0	0	1	Covered	T52,T55,T150
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	156628801	108202	0	0
DstReqKnown_A	1898302	1671526	0	0
SrcAckBusyChk_A	156628801	277	0	0
SrcBusyKnown_A	156628801	155803222	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156628801	108202	0	0
T52	433960	256	0	0
T55	0	827	0	0
T56	22304	0	0	0
T150	0	601	0	0
T151	0	623	0	0
T172	63162	0	0	0
T218	62222	0	0	0
T387	0	7079	0	0
T390	0	612	0	0
T391	0	325	0	0
T426	0	358	0	0
T427	0	467	0	0
T430	0	759	0	0
T431	14801	0	0	0
T432	18614	0	0	0
T433	112595	0	0	0
T434	56175	0	0	0
T435	54086	0	0	0
T436	42561	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1898302	1671526	0	0
T1	762	589	0	0
T2	707	533	0	0
T3	730	556	0	0
T4	4635	3999	0	0
T5	647	475	0	0
T6	8871	8573	0	0
T43	2894	2720	0	0
T45	688	516	0	0
T61	734	559	0	0
T83	498	326	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156628801	277	0	0
T52	433960	1	0	0
T55	0	2	0	0
T56	22304	0	0	0
T150	0	2	0	0
T151	0	2	0	0
T172	63162	0	0	0
T218	62222	0	0	0
T387	0	17	0	0
T390	0	2	0	0
T391	0	1	0	0
T426	0	1	0	0
T427	0	1	0	0
T430	0	2	0	0
T431	14801	0	0	0
T432	18614	0	0	0
T433	112595	0	0	0
T434	56175	0	0	0
T435	54086	0	0	0
T436	42561	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156628801	155803222	0	0
T1	66806	65768	0	0
T2	54508	54070	0	0
T3	53256	52617	0	0
T4	303847	299192	0	0
T5	43099	42674	0	0
T6	995134	993382	0	0
T43	310032	309701	0	0
T45	62854	62002	0	0
T61	55723	54983	0	0
T83	35686	35049	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T52,T56,T131

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T52,T56,T150
1	1	Covered	T52,T56,T150

 LINE       123
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T52,T56,T150
1	-	Covered	T56

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T52,T56,T150

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T52,T56,T150
1	1	Covered	T52,T56,T150

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T52,T56,T150
0	0	1	Covered	T52,T56,T150
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T52,T56,T150
0	0	1	Covered	T52,T56,T150
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	156628801	92803	0	0
DstReqKnown_A	1898302	1671526	0	0
SrcAckBusyChk_A	156628801	236	0	0
SrcBusyKnown_A	156628801	155803222	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156628801	92803	0	0
T52	433960	326	0	0
T56	22304	914	0	0
T150	0	529	0	0
T151	0	590	0	0
T172	63162	0	0	0
T218	62222	0	0	0
T387	0	4090	0	0
T390	0	640	0	0
T391	0	257	0	0
T426	0	270	0	0
T427	0	461	0	0
T430	0	925	0	0
T431	14801	0	0	0
T432	18614	0	0	0
T433	112595	0	0	0
T434	56175	0	0	0
T435	54086	0	0	0
T436	42561	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1898302	1671526	0	0
T1	762	589	0	0
T2	707	533	0	0
T3	730	556	0	0
T4	4635	3999	0	0
T5	647	475	0	0
T6	8871	8573	0	0
T43	2894	2720	0	0
T45	688	516	0	0
T61	734	559	0	0
T83	498	326	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156628801	236	0	0
T52	433960	1	0	0
T56	22304	2	0	0
T150	0	2	0	0
T151	0	2	0	0
T172	63162	0	0	0
T218	62222	0	0	0
T387	0	9	0	0
T390	0	2	0	0
T391	0	1	0	0
T426	0	1	0	0
T427	0	1	0	0
T430	0	2	0	0
T431	14801	0	0	0
T432	18614	0	0	0
T433	112595	0	0	0
T434	56175	0	0	0
T435	54086	0	0	0
T436	42561	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156628801	155803222	0	0
T1	66806	65768	0	0
T2	54508	54070	0	0
T3	53256	52617	0	0
T4	303847	299192	0	0
T5	43099	42674	0	0
T6	995134	993382	0	0
T43	310032	309701	0	0
T45	62854	62002	0	0
T61	55723	54983	0	0
T83	35686	35049	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	20	90.91
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	0	0.00
CONT_ASSIGN	156	1	0	0.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	0	1
156	0	1
200	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc

	Total	Covered	Percent
Conditions	13	11	84.62
Logical	13	11	84.62
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T52,T437,T150

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T52,T150,T151
1	1	Covered	T52,T150,T151

 LINE       123
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T52,T150,T151
1	-	Not Covered

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T52,T150,T151

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T52,T150,T151
1	1	Covered	T52,T150,T151

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T52,T150,T151
0	0	1	Covered	T52,T150,T151
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T52,T150,T151
0	0	1	Covered	T52,T150,T151
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	156628801	86889	0	0
DstReqKnown_A	1898302	1671526	0	0
SrcAckBusyChk_A	156628801	223	0	0
SrcBusyKnown_A	156628801	155803222	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156628801	86889	0	0
T52	433960	298	0	0
T56	22304	0	0	0
T150	0	675	0	0
T151	0	574	0	0
T172	63162	0	0	0
T218	62222	0	0	0
T387	0	5904	0	0
T388	0	1273	0	0
T390	0	602	0	0
T391	0	342	0	0
T426	0	289	0	0
T427	0	473	0	0
T430	0	801	0	0
T431	14801	0	0	0
T432	18614	0	0	0
T433	112595	0	0	0
T434	56175	0	0	0
T435	54086	0	0	0
T436	42561	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1898302	1671526	0	0
T1	762	589	0	0
T2	707	533	0	0
T3	730	556	0	0
T4	4635	3999	0	0
T5	647	475	0	0
T6	8871	8573	0	0
T43	2894	2720	0	0
T45	688	516	0	0
T61	734	559	0	0
T83	498	326	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156628801	223	0	0
T52	433960	1	0	0
T56	22304	0	0	0
T150	0	2	0	0
T151	0	2	0	0
T172	63162	0	0	0
T218	62222	0	0	0
T387	0	14	0	0
T388	0	3	0	0
T390	0	2	0	0
T391	0	1	0	0
T426	0	1	0	0
T427	0	1	0	0
T430	0	2	0	0
T431	14801	0	0	0
T432	18614	0	0	0
T433	112595	0	0	0
T434	56175	0	0	0
T435	54086	0	0	0
T436	42561	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156628801	155803222	0	0
T1	66806	65768	0	0
T2	54508	54070	0	0
T3	53256	52617	0	0
T4	303847	299192	0	0
T5	43099	42674	0	0
T6	995134	993382	0	0
T43	310032	309701	0	0
T45	62854	62002	0	0
T61	55723	54983	0	0
T83	35686	35049	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T18,T57,T58

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T18,T57,T58
1	1	Covered	T18,T57,T58

 LINE       123
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T18,T57,T58
1	-	Covered	T18,T57,T58

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T18,T57,T58

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T18,T57,T58
1	1	Covered	T18,T57,T58

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T18,T57,T58
0	0	1	Covered	T18,T57,T58
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T18,T57,T58
0	0	1	Covered	T18,T57,T58
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	156628801	107542	0	0
DstReqKnown_A	1898302	1671526	0	0
SrcAckBusyChk_A	156628801	274	0	0
SrcBusyKnown_A	156628801	155803222	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156628801	107542	0	0
T18	174119	757	0	0
T40	288773	0	0	0
T52	0	310	0	0
T57	0	756	0	0
T58	0	883	0	0
T60	10844	0	0	0
T78	124791	0	0	0
T97	0	752	0	0
T98	0	1680	0	0
T100	0	617	0	0
T101	0	864	0	0
T102	67801	0	0	0
T103	100139	0	0	0
T104	80780	0	0	0
T105	55716	0	0	0
T106	16047	0	0	0
T107	96981	0	0	0
T110	0	1309	0	0
T438	0	1409	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1898302	1671526	0	0
T1	762	589	0	0
T2	707	533	0	0
T3	730	556	0	0
T4	4635	3999	0	0
T5	647	475	0	0
T6	8871	8573	0	0
T43	2894	2720	0	0
T45	688	516	0	0
T61	734	559	0	0
T83	498	326	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156628801	274	0	0
T18	174119	2	0	0
T40	288773	0	0	0
T52	0	1	0	0
T57	0	2	0	0
T58	0	2	0	0
T60	10844	0	0	0
T78	124791	0	0	0
T97	0	2	0	0
T98	0	4	0	0
T100	0	2	0	0
T101	0	2	0	0
T102	67801	0	0	0
T103	100139	0	0	0
T104	80780	0	0	0
T105	55716	0	0	0
T106	16047	0	0	0
T107	96981	0	0	0
T110	0	4	0	0
T438	0	4	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156628801	155803222	0	0
T1	66806	65768	0	0
T2	54508	54070	0	0
T3	53256	52617	0	0
T4	303847	299192	0	0
T5	43099	42674	0	0
T6	995134	993382	0	0
T43	310032	309701	0	0
T45	62854	62002	0	0
T61	55723	54983	0	0
T83	35686	35049	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	20	90.91
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	0	0.00
CONT_ASSIGN	156	1	0	0.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	0	1
156	0	1
200	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc

	Total	Covered	Percent
Conditions	13	11	84.62
Logical	13	11	84.62
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T52,T150,T151

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T52,T150,T151
1	1	Covered	T52,T150,T151

 LINE       123
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T52,T150,T151
1	-	Not Covered

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T52,T150,T151

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T52,T150,T151
1	1	Covered	T52,T150,T151

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T52,T150,T151
0	0	1	Covered	T52,T150,T151
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T52,T150,T151
0	0	1	Covered	T52,T150,T151
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	156628801	87635	0	0
DstReqKnown_A	1898302	1671526	0	0
SrcAckBusyChk_A	156628801	227	0	0
SrcBusyKnown_A	156628801	155803222	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156628801	87635	0	0
T52	433960	276	0	0
T56	22304	0	0	0
T150	0	582	0	0
T151	0	580	0	0
T172	63162	0	0	0
T218	62222	0	0	0
T387	0	4418	0	0
T388	0	2443	0	0
T390	0	628	0	0
T391	0	340	0	0
T426	0	282	0	0
T427	0	480	0	0
T430	0	835	0	0
T431	14801	0	0	0
T432	18614	0	0	0
T433	112595	0	0	0
T434	56175	0	0	0
T435	54086	0	0	0
T436	42561	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1898302	1671526	0	0
T1	762	589	0	0
T2	707	533	0	0
T3	730	556	0	0
T4	4635	3999	0	0
T5	647	475	0	0
T6	8871	8573	0	0
T43	2894	2720	0	0
T45	688	516	0	0
T61	734	559	0	0
T83	498	326	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156628801	227	0	0
T52	433960	1	0	0
T56	22304	0	0	0
T150	0	2	0	0
T151	0	2	0	0
T172	63162	0	0	0
T218	62222	0	0	0
T387	0	10	0	0
T388	0	6	0	0
T390	0	2	0	0
T391	0	1	0	0
T426	0	1	0	0
T427	0	1	0	0
T430	0	2	0	0
T431	14801	0	0	0
T432	18614	0	0	0
T433	112595	0	0	0
T434	56175	0	0	0
T435	54086	0	0	0
T436	42561	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156628801	155803222	0	0
T1	66806	65768	0	0
T2	54508	54070	0	0
T3	53256	52617	0	0
T4	303847	299192	0	0
T5	43099	42674	0	0
T6	995134	993382	0	0
T43	310032	309701	0	0
T45	62854	62002	0	0
T61	55723	54983	0	0
T83	35686	35049	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	20	90.91
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	0	0.00
CONT_ASSIGN	156	1	0	0.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	0	1
156	0	1
200	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc

	Total	Covered	Percent
Conditions	13	11	84.62
Logical	13	11	84.62
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T52,T150,T439

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T52,T150,T151
1	1	Covered	T52,T150,T151

 LINE       123
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T52,T150,T151
1	-	Not Covered

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T52,T150,T151

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T52,T150,T151
1	1	Covered	T52,T150,T151

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T52,T150,T151
0	0	1	Covered	T52,T150,T151
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T52,T150,T151
0	0	1	Covered	T52,T150,T151
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	156628801	111970	0	0
DstReqKnown_A	1898302	1671526	0	0
SrcAckBusyChk_A	156628801	282	0	0
SrcBusyKnown_A	156628801	155803222	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156628801	111970	0	0
T52	433960	324	0	0
T56	22304	0	0	0
T150	0	592	0	0
T151	0	689	0	0
T172	63162	0	0	0
T218	62222	0	0	0
T387	0	2239	0	0
T388	0	2057	0	0
T390	0	717	0	0
T391	0	344	0	0
T426	0	254	0	0
T427	0	403	0	0
T430	0	808	0	0
T431	14801	0	0	0
T432	18614	0	0	0
T433	112595	0	0	0
T434	56175	0	0	0
T435	54086	0	0	0
T436	42561	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1898302	1671526	0	0
T1	762	589	0	0
T2	707	533	0	0
T3	730	556	0	0
T4	4635	3999	0	0
T5	647	475	0	0
T6	8871	8573	0	0
T43	2894	2720	0	0
T45	688	516	0	0
T61	734	559	0	0
T83	498	326	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156628801	282	0	0
T52	433960	1	0	0
T56	22304	0	0	0
T150	0	2	0	0
T151	0	2	0	0
T172	63162	0	0	0
T218	62222	0	0	0
T387	0	5	0	0
T388	0	5	0	0
T390	0	2	0	0
T391	0	1	0	0
T426	0	1	0	0
T427	0	1	0	0
T430	0	2	0	0
T431	14801	0	0	0
T432	18614	0	0	0
T433	112595	0	0	0
T434	56175	0	0	0
T435	54086	0	0	0
T436	42561	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156628801	155803222	0	0
T1	66806	65768	0	0
T2	54508	54070	0	0
T3	53256	52617	0	0
T4	303847	299192	0	0
T5	43099	42674	0	0
T6	995134	993382	0	0
T43	310032	309701	0	0
T45	62854	62002	0	0
T61	55723	54983	0	0
T83	35686	35049	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T15,T49,T99

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T15,T49,T99
1	1	Covered	T15,T49,T99

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T15,T49,T99

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T15,T49,T99
1	1	Covered	T15,T49,T99

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T15,T49,T99
0	0	1	Covered	T15,T49,T99
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T15,T49,T99
0	0	1	Covered	T15,T49,T99
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	156628801	112300	0	0
DstReqKnown_A	1898302	1671526	0	0
SrcAckBusyChk_A	156628801	285	0	0
SrcBusyKnown_A	156628801	155803222	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156628801	112300	0	0
T15	42699	358	0	0
T49	0	715	0	0
T50	0	344	0	0
T51	0	456	0	0
T52	0	270	0	0
T53	0	731	0	0
T54	0	903	0	0
T99	0	366	0	0
T134	85000	0	0	0
T150	0	608	0	0
T151	0	508	0	0
T154	55223	0	0	0
T235	95175	0	0	0
T296	394225	0	0	0
T297	10842	0	0	0
T298	22652	0	0	0
T299	24928	0	0	0
T300	210746	0	0	0
T428	66990	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1898302	1671526	0	0
T1	762	589	0	0
T2	707	533	0	0
T3	730	556	0	0
T4	4635	3999	0	0
T5	647	475	0	0
T6	8871	8573	0	0
T43	2894	2720	0	0
T45	688	516	0	0
T61	734	559	0	0
T83	498	326	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156628801	285	0	0
T15	42699	1	0	0
T49	0	2	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	2	0	0
T54	0	2	0	0
T99	0	1	0	0
T134	85000	0	0	0
T150	0	2	0	0
T151	0	2	0	0
T154	55223	0	0	0
T235	95175	0	0	0
T296	394225	0	0	0
T297	10842	0	0	0
T298	22652	0	0	0
T299	24928	0	0	0
T300	210746	0	0	0
T428	66990	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156628801	155803222	0	0
T1	66806	65768	0	0
T2	54508	54070	0	0
T3	53256	52617	0	0
T4	303847	299192	0	0
T5	43099	42674	0	0
T6	995134	993382	0	0
T43	310032	309701	0	0
T45	62854	62002	0	0
T61	55723	54983	0	0
T83	35686	35049	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T52,T150,T151

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T52,T150,T151
1	1	Covered	T52,T150,T151

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T52,T150,T151

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T52,T150,T151
1	1	Covered	T52,T150,T151

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T52,T150,T151
0	0	1	Covered	T52,T150,T151
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T52,T150,T151
0	0	1	Covered	T52,T150,T151
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	156628801	123910	0	0
DstReqKnown_A	1898302	1671526	0	0
SrcAckBusyChk_A	156628801	310	0	0
SrcBusyKnown_A	156628801	155803222	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156628801	123910	0	0
T52	433960	275	0	0
T56	22304	0	0	0
T150	0	624	0	0
T151	0	617	0	0
T172	63162	0	0	0
T218	62222	0	0	0
T387	0	5621	0	0
T388	0	2078	0	0
T390	0	671	0	0
T391	0	323	0	0
T426	0	291	0	0
T427	0	428	0	0
T430	0	816	0	0
T431	14801	0	0	0
T432	18614	0	0	0
T433	112595	0	0	0
T434	56175	0	0	0
T435	54086	0	0	0
T436	42561	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1898302	1671526	0	0
T1	762	589	0	0
T2	707	533	0	0
T3	730	556	0	0
T4	4635	3999	0	0
T5	647	475	0	0
T6	8871	8573	0	0
T43	2894	2720	0	0
T45	688	516	0	0
T61	734	559	0	0
T83	498	326	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156628801	310	0	0
T52	433960	1	0	0
T56	22304	0	0	0
T150	0	2	0	0
T151	0	2	0	0
T172	63162	0	0	0
T218	62222	0	0	0
T387	0	13	0	0
T388	0	5	0	0
T390	0	2	0	0
T391	0	1	0	0
T426	0	1	0	0
T427	0	1	0	0
T430	0	2	0	0
T431	14801	0	0	0
T432	18614	0	0	0
T433	112595	0	0	0
T434	56175	0	0	0
T435	54086	0	0	0
T436	42561	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156628801	155803222	0	0
T1	66806	65768	0	0
T2	54508	54070	0	0
T3	53256	52617	0	0
T4	303847	299192	0	0
T5	43099	42674	0	0
T6	995134	993382	0	0
T43	310032	309701	0	0
T45	62854	62002	0	0
T61	55723	54983	0	0
T83	35686	35049	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T52,T55,T150

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T52,T55,T150
1	1	Covered	T52,T55,T150

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T52,T55,T150

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T52,T55,T150
1	1	Covered	T52,T55,T150

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T52,T55,T150
0	0	1	Covered	T52,T55,T150
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T52,T55,T150
0	0	1	Covered	T52,T55,T150
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	156628801	109004	0	0
DstReqKnown_A	1898302	1671526	0	0
SrcAckBusyChk_A	156628801	278	0	0
SrcBusyKnown_A	156628801	155803222	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156628801	109004	0	0
T52	433960	358	0	0
T55	0	284	0	0
T56	22304	0	0	0
T150	0	655	0	0
T151	0	584	0	0
T172	63162	0	0	0
T218	62222	0	0	0
T387	0	3508	0	0
T390	0	606	0	0
T391	0	275	0	0
T426	0	306	0	0
T427	0	424	0	0
T430	0	826	0	0
T431	14801	0	0	0
T432	18614	0	0	0
T433	112595	0	0	0
T434	56175	0	0	0
T435	54086	0	0	0
T436	42561	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1898302	1671526	0	0
T1	762	589	0	0
T2	707	533	0	0
T3	730	556	0	0
T4	4635	3999	0	0
T5	647	475	0	0
T6	8871	8573	0	0
T43	2894	2720	0	0
T45	688	516	0	0
T61	734	559	0	0
T83	498	326	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156628801	278	0	0
T52	433960	1	0	0
T55	0	1	0	0
T56	22304	0	0	0
T150	0	2	0	0
T151	0	2	0	0
T172	63162	0	0	0
T218	62222	0	0	0
T387	0	8	0	0
T390	0	2	0	0
T391	0	1	0	0
T426	0	1	0	0
T427	0	1	0	0
T430	0	2	0	0
T431	14801	0	0	0
T432	18614	0	0	0
T433	112595	0	0	0
T434	56175	0	0	0
T435	54086	0	0	0
T436	42561	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156628801	155803222	0	0
T1	66806	65768	0	0
T2	54508	54070	0	0
T3	53256	52617	0	0
T4	303847	299192	0	0
T5	43099	42674	0	0
T6	995134	993382	0	0
T43	310032	309701	0	0
T45	62854	62002	0	0
T61	55723	54983	0	0
T83	35686	35049	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T52,T56,T429

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T52,T56,T150
1	1	Covered	T52,T56,T150

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T52,T56,T150

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T52,T56,T150
1	1	Covered	T52,T56,T150

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T52,T56,T150
0	0	1	Covered	T52,T56,T150
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T52,T56,T150
0	0	1	Covered	T52,T56,T150
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	156628801	97158	0	0
DstReqKnown_A	1898302	1671526	0	0
SrcAckBusyChk_A	156628801	248	0	0
SrcBusyKnown_A	156628801	155803222	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156628801	97158	0	0
T52	433960	303	0	0
T56	22304	370	0	0
T150	0	548	0	0
T151	0	563	0	0
T172	63162	0	0	0
T218	62222	0	0	0
T387	0	2677	0	0
T390	0	540	0	0
T391	0	247	0	0
T426	0	350	0	0
T427	0	427	0	0
T430	0	813	0	0
T431	14801	0	0	0
T432	18614	0	0	0
T433	112595	0	0	0
T434	56175	0	0	0
T435	54086	0	0	0
T436	42561	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1898302	1671526	0	0
T1	762	589	0	0
T2	707	533	0	0
T3	730	556	0	0
T4	4635	3999	0	0
T5	647	475	0	0
T6	8871	8573	0	0
T43	2894	2720	0	0
T45	688	516	0	0
T61	734	559	0	0
T83	498	326	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156628801	248	0	0
T52	433960	1	0	0
T56	22304	1	0	0
T150	0	2	0	0
T151	0	2	0	0
T172	63162	0	0	0
T218	62222	0	0	0
T387	0	6	0	0
T390	0	2	0	0
T391	0	1	0	0
T426	0	1	0	0
T427	0	1	0	0
T430	0	2	0	0
T431	14801	0	0	0
T432	18614	0	0	0
T433	112595	0	0	0
T434	56175	0	0	0
T435	54086	0	0	0
T436	42561	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156628801	155803222	0	0
T1	66806	65768	0	0
T2	54508	54070	0	0
T3	53256	52617	0	0
T4	303847	299192	0	0
T5	43099	42674	0	0
T6	995134	993382	0	0
T43	310032	309701	0	0
T45	62854	62002	0	0
T61	55723	54983	0	0
T83	35686	35049	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T52,T440,T150

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T52,T150,T151
1	1	Covered	T52,T150,T151

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T52,T150,T151

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T52,T150,T151
1	1	Covered	T52,T150,T151

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T52,T150,T151
0	0	1	Covered	T52,T150,T151
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T52,T150,T151
0	0	1	Covered	T52,T150,T151
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	156628801	104229	0	0
DstReqKnown_A	1898302	1671526	0	0
SrcAckBusyChk_A	156628801	267	0	0
SrcBusyKnown_A	156628801	155803222	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156628801	104229	0	0
T52	433960	353	0	0
T56	22304	0	0	0
T150	0	609	0	0
T151	0	703	0	0
T172	63162	0	0	0
T218	62222	0	0	0
T387	0	5928	0	0
T388	0	3555	0	0
T390	0	605	0	0
T391	0	325	0	0
T426	0	290	0	0
T427	0	379	0	0
T430	0	919	0	0
T431	14801	0	0	0
T432	18614	0	0	0
T433	112595	0	0	0
T434	56175	0	0	0
T435	54086	0	0	0
T436	42561	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1898302	1671526	0	0
T1	762	589	0	0
T2	707	533	0	0
T3	730	556	0	0
T4	4635	3999	0	0
T5	647	475	0	0
T6	8871	8573	0	0
T43	2894	2720	0	0
T45	688	516	0	0
T61	734	559	0	0
T83	498	326	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156628801	267	0	0
T52	433960	1	0	0
T56	22304	0	0	0
T150	0	2	0	0
T151	0	2	0	0
T172	63162	0	0	0
T218	62222	0	0	0
T387	0	14	0	0
T388	0	9	0	0
T390	0	2	0	0
T391	0	1	0	0
T426	0	1	0	0
T427	0	1	0	0
T430	0	2	0	0
T431	14801	0	0	0
T432	18614	0	0	0
T433	112595	0	0	0
T434	56175	0	0	0
T435	54086	0	0	0
T436	42561	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156628801	155803222	0	0
T1	66806	65768	0	0
T2	54508	54070	0	0
T3	53256	52617	0	0
T4	303847	299192	0	0
T5	43099	42674	0	0
T6	995134	993382	0	0
T43	310032	309701	0	0
T45	62854	62002	0	0
T61	55723	54983	0	0
T83	35686	35049	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T18,T57,T58

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T18,T57,T58
1	1	Covered	T18,T57,T58

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T18,T57,T58

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T18,T57,T58
1	1	Covered	T18,T57,T58

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T18,T57,T58
0	0	1	Covered	T18,T57,T58
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T18,T57,T58
0	0	1	Covered	T18,T57,T58
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	156628801	110866	0	0
DstReqKnown_A	1898302	1671526	0	0
SrcAckBusyChk_A	156628801	281	0	0
SrcBusyKnown_A	156628801	155803222	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156628801	110866	0	0
T18	174119	260	0	0
T40	288773	0	0	0
T52	0	326	0	0
T57	0	259	0	0
T58	0	387	0	0
T60	10844	0	0	0
T78	124791	0	0	0
T97	0	254	0	0
T98	0	692	0	0
T100	0	242	0	0
T101	0	369	0	0
T102	67801	0	0	0
T103	100139	0	0	0
T104	80780	0	0	0
T105	55716	0	0	0
T106	16047	0	0	0
T107	96981	0	0	0
T110	0	561	0	0
T438	0	782	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1898302	1671526	0	0
T1	762	589	0	0
T2	707	533	0	0
T3	730	556	0	0
T4	4635	3999	0	0
T5	647	475	0	0
T6	8871	8573	0	0
T43	2894	2720	0	0
T45	688	516	0	0
T61	734	559	0	0
T83	498	326	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156628801	281	0	0
T18	174119	1	0	0
T40	288773	0	0	0
T52	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T60	10844	0	0	0
T78	124791	0	0	0
T97	0	1	0	0
T98	0	2	0	0
T100	0	1	0	0
T101	0	1	0	0
T102	67801	0	0	0
T103	100139	0	0	0
T104	80780	0	0	0
T105	55716	0	0	0
T106	16047	0	0	0
T107	96981	0	0	0
T110	0	2	0	0
T438	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156628801	155803222	0	0
T1	66806	65768	0	0
T2	54508	54070	0	0
T3	53256	52617	0	0
T4	303847	299192	0	0
T5	43099	42674	0	0
T6	995134	993382	0	0
T43	310032	309701	0	0
T45	62854	62002	0	0
T61	55723	54983	0	0
T83	35686	35049	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T52,T150,T151

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T52,T150,T151
1	1	Covered	T52,T150,T151

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T52,T150,T151

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T52,T150,T151
1	1	Covered	T52,T150,T151

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T52,T150,T151
0	0	1	Covered	T52,T150,T151
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T52,T150,T151
0	0	1	Covered	T52,T150,T151
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	156628801	113059	0	0
DstReqKnown_A	1898302	1671526	0	0
SrcAckBusyChk_A	156628801	288	0	0
SrcBusyKnown_A	156628801	155803222	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156628801	113059	0	0
T52	433960	289	0	0
T56	22304	0	0	0
T150	0	580	0	0
T151	0	606	0	0
T172	63162	0	0	0
T218	62222	0	0	0
T387	0	7140	0	0
T388	0	818	0	0
T390	0	509	0	0
T391	0	309	0	0
T426	0	311	0	0
T427	0	392	0	0
T430	0	903	0	0
T431	14801	0	0	0
T432	18614	0	0	0
T433	112595	0	0	0
T434	56175	0	0	0
T435	54086	0	0	0
T436	42561	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1898302	1671526	0	0
T1	762	589	0	0
T2	707	533	0	0
T3	730	556	0	0
T4	4635	3999	0	0
T5	647	475	0	0
T6	8871	8573	0	0
T43	2894	2720	0	0
T45	688	516	0	0
T61	734	559	0	0
T83	498	326	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156628801	288	0	0
T52	433960	1	0	0
T56	22304	0	0	0
T150	0	2	0	0
T151	0	2	0	0
T172	63162	0	0	0
T218	62222	0	0	0
T387	0	17	0	0
T388	0	2	0	0
T390	0	2	0	0
T391	0	1	0	0
T426	0	1	0	0
T427	0	1	0	0
T430	0	2	0	0
T431	14801	0	0	0
T432	18614	0	0	0
T433	112595	0	0	0
T434	56175	0	0	0
T435	54086	0	0	0
T436	42561	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156628801	155803222	0	0
T1	66806	65768	0	0
T2	54508	54070	0	0
T3	53256	52617	0	0
T4	303847	299192	0	0
T5	43099	42674	0	0
T6	995134	993382	0	0
T43	310032	309701	0	0
T45	62854	62002	0	0
T61	55723	54983	0	0
T83	35686	35049	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T52,T150,T151

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T52,T150,T151
1	1	Covered	T52,T150,T151

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T52,T150,T151

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T52,T150,T151
1	1	Covered	T52,T150,T151

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T52,T150,T151
0	0	1	Covered	T52,T150,T151
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T52,T150,T151
0	0	1	Covered	T52,T150,T151
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	156628801	104820	0	0
DstReqKnown_A	1898302	1671526	0	0
SrcAckBusyChk_A	156628801	265	0	0
SrcBusyKnown_A	156628801	155803222	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156628801	104820	0	0
T52	433960	283	0	0
T56	22304	0	0	0
T150	0	582	0	0
T151	0	593	0	0
T172	63162	0	0	0
T218	62222	0	0	0
T387	0	5949	0	0
T388	0	1772	0	0
T390	0	610	0	0
T391	0	356	0	0
T426	0	342	0	0
T427	0	365	0	0
T430	0	922	0	0
T431	14801	0	0	0
T432	18614	0	0	0
T433	112595	0	0	0
T434	56175	0	0	0
T435	54086	0	0	0
T436	42561	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1898302	1671526	0	0
T1	762	589	0	0
T2	707	533	0	0
T3	730	556	0	0
T4	4635	3999	0	0
T5	647	475	0	0
T6	8871	8573	0	0
T43	2894	2720	0	0
T45	688	516	0	0
T61	734	559	0	0
T83	498	326	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156628801	265	0	0
T52	433960	1	0	0
T56	22304	0	0	0
T150	0	2	0	0
T151	0	2	0	0
T172	63162	0	0	0
T218	62222	0	0	0
T387	0	14	0	0
T388	0	4	0	0
T390	0	2	0	0
T391	0	1	0	0
T426	0	1	0	0
T427	0	1	0	0
T430	0	2	0	0
T431	14801	0	0	0
T432	18614	0	0	0
T433	112595	0	0	0
T434	56175	0	0	0
T435	54086	0	0	0
T436	42561	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156628801	155803222	0	0
T1	66806	65768	0	0
T2	54508	54070	0	0
T3	53256	52617	0	0
T4	303847	299192	0	0
T5	43099	42674	0	0
T6	995134	993382	0	0
T43	310032	309701	0	0
T45	62854	62002	0	0
T61	55723	54983	0	0
T83	35686	35049	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T52,T150,T151

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T52,T150,T151
1	1	Covered	T52,T150,T151

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T52,T150,T151

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T52,T150,T151
1	1	Covered	T52,T150,T151

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T52,T150,T151
0	0	1	Covered	T52,T150,T151
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T52,T150,T151
0	0	1	Covered	T52,T150,T151
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	156628801	97566	0	0
DstReqKnown_A	1898302	1671526	0	0
SrcAckBusyChk_A	156628801	250	0	0
SrcBusyKnown_A	156628801	155803222	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156628801	97566	0	0
T52	433960	314	0	0
T56	22304	0	0	0
T150	0	635	0	0
T151	0	573	0	0
T172	63162	0	0	0
T218	62222	0	0	0
T387	0	6673	0	0
T388	0	4736	0	0
T390	0	614	0	0
T391	0	245	0	0
T426	0	333	0	0
T427	0	420	0	0
T430	0	879	0	0
T431	14801	0	0	0
T432	18614	0	0	0
T433	112595	0	0	0
T434	56175	0	0	0
T435	54086	0	0	0
T436	42561	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1898302	1671526	0	0
T1	762	589	0	0
T2	707	533	0	0
T3	730	556	0	0
T4	4635	3999	0	0
T5	647	475	0	0
T6	8871	8573	0	0
T43	2894	2720	0	0
T45	688	516	0	0
T61	734	559	0	0
T83	498	326	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156628801	250	0	0
T52	433960	1	0	0
T56	22304	0	0	0
T150	0	2	0	0
T151	0	2	0	0
T172	63162	0	0	0
T218	62222	0	0	0
T387	0	16	0	0
T388	0	12	0	0
T390	0	2	0	0
T391	0	1	0	0
T426	0	1	0	0
T427	0	1	0	0
T430	0	2	0	0
T431	14801	0	0	0
T432	18614	0	0	0
T433	112595	0	0	0
T434	56175	0	0	0
T435	54086	0	0	0
T436	42561	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156628801	155803222	0	0
T1	66806	65768	0	0
T2	54508	54070	0	0
T3	53256	52617	0	0
T4	303847	299192	0	0
T5	43099	42674	0	0
T6	995134	993382	0	0
T43	310032	309701	0	0
T45	62854	62002	0	0
T61	55723	54983	0	0
T83	35686	35049	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T108,T52,T109

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T108,T52,T109
1	1	Covered	T108,T52,T109

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T108,T52,T109

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T108,T52,T109
1	1	Covered	T108,T52,T109

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T108,T52,T109
0	0	1	Covered	T108,T52,T109
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T108,T52,T109
0	0	1	Covered	T108,T52,T109
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	156628801	102691	0	0
DstReqKnown_A	1898302	1671526	0	0
SrcAckBusyChk_A	156628801	260	0	0
SrcBusyKnown_A	156628801	155803222	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156628801	102691	0	0
T16	45170	0	0	0
T52	0	307	0	0
T85	56579	0	0	0
T108	45313	419	0	0
T109	0	315	0	0
T150	0	525	0	0
T151	0	598	0	0
T183	449471	0	0	0
T205	105093	0	0	0
T216	22264	0	0	0
T323	57508	0	0	0
T369	55986	0	0	0
T390	0	626	0	0
T391	0	300	0	0
T426	0	274	0	0
T427	0	371	0	0
T441	0	449	0	0
T442	21638	0	0	0
T443	39278	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1898302	1671526	0	0
T1	762	589	0	0
T2	707	533	0	0
T3	730	556	0	0
T4	4635	3999	0	0
T5	647	475	0	0
T6	8871	8573	0	0
T43	2894	2720	0	0
T45	688	516	0	0
T61	734	559	0	0
T83	498	326	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156628801	260	0	0
T16	45170	0	0	0
T52	0	1	0	0
T85	56579	0	0	0
T108	45313	1	0	0
T109	0	1	0	0
T150	0	2	0	0
T151	0	2	0	0
T183	449471	0	0	0
T205	105093	0	0	0
T216	22264	0	0	0
T323	57508	0	0	0
T369	55986	0	0	0
T390	0	2	0	0
T391	0	1	0	0
T426	0	1	0	0
T427	0	1	0	0
T441	0	1	0	0
T442	21638	0	0	0
T443	39278	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156628801	155803222	0	0
T1	66806	65768	0	0
T2	54508	54070	0	0
T3	53256	52617	0	0
T4	303847	299192	0	0
T5	43099	42674	0	0
T6	995134	993382	0	0
T43	310032	309701	0	0
T45	62854	62002	0	0
T61	55723	54983	0	0
T83	35686	35049	0	0