Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo	75.00	50.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	191019825	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	10340	10340	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	191019825	0	0
T1	2582060	92341	0	0
T2	1964680	110187	0	0
T3	1241390	52462	0	0
T4	5627630	137685	0	0
T5	6445400	333753	0	0
T24	1998750	111217	0	0
T34	6396500	248259	0	0
T72	2164290	68715	0	0
T92	2778320	101697	0	0
T103	3675640	166251	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2582060	2580820	0	0
T2	1964680	1964060	0	0
T3	1241390	1240880	0	0
T4	5627630	5624680	0	0
T5	6445400	6444300	0	0
T24	1998750	1998170	0	0
T34	6396500	6395990	0	0
T72	2164290	2163780	0	0
T92	2778320	2777160	0	0
T103	3675640	3675130	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2582060	2580820	0	0
T2	1964680	1964060	0	0
T3	1241390	1240880	0	0
T4	5627630	5624680	0	0
T5	6445400	6444300	0	0
T24	1998750	1998170	0	0
T34	6396500	6395990	0	0
T72	2164290	2163780	0	0
T92	2778320	2777160	0	0
T103	3675640	3675130	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2582060	2580820	0	0
T2	1964680	1964060	0	0
T3	1241390	1240880	0	0
T4	5627630	5624680	0	0
T5	6445400	6444300	0	0
T24	1998750	1998170	0	0
T34	6396500	6395990	0	0
T72	2164290	2163780	0	0
T92	2778320	2777160	0	0
T103	3675640	3675130	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	10340	10340	0	0
T1	10	10	0	0
T2	10	10	0	0
T3	10	10	0	0
T4	10	10	0	0
T5	10	10	0	0
T24	10	10	0	0
T34	10	10	0	0
T72	10	10	0	0
T92	10	10	0	0
T103	10	10	0	0