Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	524555724	61171742	0	0
DepthKnown_A	524555724	524448377	0	0
RvalidKnown_A	524555724	524448377	0	0
WreadyKnown_A	524555724	524448377	0	0
gen_passthru_fifo.paramCheckPass	1034	1034	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524555724	61171742	0	0
T1	258206	33586	0	0
T2	196468	38069	0	0
T3	124139	15779	0	0
T4	562763	51828	0	0
T5	644540	90905	0	0
T24	199875	38126	0	0
T34	639650	57367	0	0
T72	216429	28229	0	0
T92	277832	36421	0	0
T103	367564	45364	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524555724	524448377	0	0
T1	258206	258082	0	0
T2	196468	196406	0	0
T3	124139	124088	0	0
T4	562763	562468	0	0
T5	644540	644430	0	0
T24	199875	199817	0	0
T34	639650	639599	0	0
T72	216429	216378	0	0
T92	277832	277716	0	0
T103	367564	367513	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524555724	524448377	0	0
T1	258206	258082	0	0
T2	196468	196406	0	0
T3	124139	124088	0	0
T4	562763	562468	0	0
T5	644540	644430	0	0
T24	199875	199817	0	0
T34	639650	639599	0	0
T72	216429	216378	0	0
T92	277832	277716	0	0
T103	367564	367513	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524555724	524448377	0	0
T1	258206	258082	0	0
T2	196468	196406	0	0
T3	124139	124088	0	0
T4	562763	562468	0	0
T5	644540	644430	0	0
T24	199875	199817	0	0
T34	639650	639599	0	0
T72	216429	216378	0	0
T92	277832	277716	0	0
T103	367564	367513	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1034	1034	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T24	1	1	0	0
T34	1	1	0	0
T72	1	1	0	0
T92	1	1	0	0
T103	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	524555724	47062376	0	0
DepthKnown_A	524555724	524448377	0	0
RvalidKnown_A	524555724	524448377	0	0
WreadyKnown_A	524555724	524448377	0	0
gen_passthru_fifo.paramCheckPass	1034	1034	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524555724	47062376	0	0
T1	258206	24084	0	0
T2	196468	27970	0	0
T3	124139	12640	0	0
T4	562763	38497	0	0
T5	644540	83994	0	0
T24	199875	28242	0	0
T34	639650	53213	0	0
T72	216429	25537	0	0
T92	277832	26812	0	0
T103	367564	35577	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524555724	524448377	0	0
T1	258206	258082	0	0
T2	196468	196406	0	0
T3	124139	124088	0	0
T4	562763	562468	0	0
T5	644540	644430	0	0
T24	199875	199817	0	0
T34	639650	639599	0	0
T72	216429	216378	0	0
T92	277832	277716	0	0
T103	367564	367513	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524555724	524448377	0	0
T1	258206	258082	0	0
T2	196468	196406	0	0
T3	124139	124088	0	0
T4	562763	562468	0	0
T5	644540	644430	0	0
T24	199875	199817	0	0
T34	639650	639599	0	0
T72	216429	216378	0	0
T92	277832	277716	0	0
T103	367564	367513	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524555724	524448377	0	0
T1	258206	258082	0	0
T2	196468	196406	0	0
T3	124139	124088	0	0
T4	562763	562468	0	0
T5	644540	644430	0	0
T24	199875	199817	0	0
T34	639650	639599	0	0
T72	216429	216378	0	0
T92	277832	277716	0	0
T103	367564	367513	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1034	1034	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T24	1	1	0	0
T34	1	1	0	0
T72	1	1	0	0
T92	1	1	0	0
T103	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	524555724	44674273	0	0
DepthKnown_A	524555724	524448377	0	0
RvalidKnown_A	524555724	524448377	0	0
WreadyKnown_A	524555724	524448377	0	0
gen_passthru_fifo.paramCheckPass	1034	1034	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524555724	44674273	0	0
T1	258206	17224	0	0
T2	196468	22310	0	0
T3	124139	11967	0	0
T4	562763	23706	0	0
T5	644540	79557	0	0
T24	199875	22665	0	0
T34	639650	68836	0	0
T72	216429	7423	0	0
T92	277832	19125	0	0
T103	367564	43931	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524555724	524448377	0	0
T1	258206	258082	0	0
T2	196468	196406	0	0
T3	124139	124088	0	0
T4	562763	562468	0	0
T5	644540	644430	0	0
T24	199875	199817	0	0
T34	639650	639599	0	0
T72	216429	216378	0	0
T92	277832	277716	0	0
T103	367564	367513	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524555724	524448377	0	0
T1	258206	258082	0	0
T2	196468	196406	0	0
T3	124139	124088	0	0
T4	562763	562468	0	0
T5	644540	644430	0	0
T24	199875	199817	0	0
T34	639650	639599	0	0
T72	216429	216378	0	0
T92	277832	277716	0	0
T103	367564	367513	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524555724	524448377	0	0
T1	258206	258082	0	0
T2	196468	196406	0	0
T3	124139	124088	0	0
T4	562763	562468	0	0
T5	644540	644430	0	0
T24	199875	199817	0	0
T34	639650	639599	0	0
T72	216429	216378	0	0
T92	277832	277716	0	0
T103	367564	367513	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1034	1034	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T24	1	1	0	0
T34	1	1	0	0
T72	1	1	0	0
T92	1	1	0	0
T103	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	524555724	37843138	0	0
DepthKnown_A	524555724	524448377	0	0
RvalidKnown_A	524555724	524448377	0	0
WreadyKnown_A	524555724	524448377	0	0
gen_passthru_fifo.paramCheckPass	1034	1034	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524555724	37843138	0	0
T1	258206	16843	0	0
T2	196468	21778	0	0
T3	124139	11804	0	0
T4	562763	22930	0	0
T5	644540	79141	0	0
T24	199875	22124	0	0
T34	639650	68619	0	0
T72	216429	7214	0	0
T92	277832	18735	0	0
T103	367564	41323	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524555724	524448377	0	0
T1	258206	258082	0	0
T2	196468	196406	0	0
T3	124139	124088	0	0
T4	562763	562468	0	0
T5	644540	644430	0	0
T24	199875	199817	0	0
T34	639650	639599	0	0
T72	216429	216378	0	0
T92	277832	277716	0	0
T103	367564	367513	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524555724	524448377	0	0
T1	258206	258082	0	0
T2	196468	196406	0	0
T3	124139	124088	0	0
T4	562763	562468	0	0
T5	644540	644430	0	0
T24	199875	199817	0	0
T34	639650	639599	0	0
T72	216429	216378	0	0
T92	277832	277716	0	0
T103	367564	367513	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524555724	524448377	0	0
T1	258206	258082	0	0
T2	196468	196406	0	0
T3	124139	124088	0	0
T4	562763	562468	0	0
T5	644540	644430	0	0
T24	199875	199817	0	0
T34	639650	639599	0	0
T72	216429	216378	0	0
T92	277832	277716	0	0
T103	367564	367513	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1034	1034	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T24	1	1	0	0
T34	1	1	0	0
T72	1	1	0	0
T92	1	1	0	0
T103	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	524555724	67074	0	0
DepthKnown_A	524555724	524448377	0	0
RvalidKnown_A	524555724	524448377	0	0
WreadyKnown_A	524555724	524448377	0	0
gen_passthru_fifo.paramCheckPass	1034	1034	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524555724	67074	0	0
T1	258206	151	0	0
T2	196468	15	0	0
T3	124139	68	0	0
T4	562763	181	0	0
T5	644540	39	0	0
T24	199875	15	0	0
T34	639650	56	0	0
T72	216429	78	0	0
T92	277832	151	0	0
T103	367564	14	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524555724	524448377	0	0
T1	258206	258082	0	0
T2	196468	196406	0	0
T3	124139	124088	0	0
T4	562763	562468	0	0
T5	644540	644430	0	0
T24	199875	199817	0	0
T34	639650	639599	0	0
T72	216429	216378	0	0
T92	277832	277716	0	0
T103	367564	367513	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524555724	524448377	0	0
T1	258206	258082	0	0
T2	196468	196406	0	0
T3	124139	124088	0	0
T4	562763	562468	0	0
T5	644540	644430	0	0
T24	199875	199817	0	0
T34	639650	639599	0	0
T72	216429	216378	0	0
T92	277832	277716	0	0
T103	367564	367513	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524555724	524448377	0	0
T1	258206	258082	0	0
T2	196468	196406	0	0
T3	124139	124088	0	0
T4	562763	562468	0	0
T5	644540	644430	0	0
T24	199875	199817	0	0
T34	639650	639599	0	0
T72	216429	216378	0	0
T92	277832	277716	0	0
T103	367564	367513	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1034	1034	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T24	1	1	0	0
T34	1	1	0	0
T72	1	1	0	0
T92	1	1	0	0
T103	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	524555724	67074	0	0
DepthKnown_A	524555724	524448377	0	0
RvalidKnown_A	524555724	524448377	0	0
WreadyKnown_A	524555724	524448377	0	0
gen_passthru_fifo.paramCheckPass	1034	1034	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524555724	67074	0	0
T1	258206	151	0	0
T2	196468	15	0	0
T3	124139	68	0	0
T4	562763	181	0	0
T5	644540	39	0	0
T24	199875	15	0	0
T34	639650	56	0	0
T72	216429	78	0	0
T92	277832	151	0	0
T103	367564	14	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524555724	524448377	0	0
T1	258206	258082	0	0
T2	196468	196406	0	0
T3	124139	124088	0	0
T4	562763	562468	0	0
T5	644540	644430	0	0
T24	199875	199817	0	0
T34	639650	639599	0	0
T72	216429	216378	0	0
T92	277832	277716	0	0
T103	367564	367513	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524555724	524448377	0	0
T1	258206	258082	0	0
T2	196468	196406	0	0
T3	124139	124088	0	0
T4	562763	562468	0	0
T5	644540	644430	0	0
T24	199875	199817	0	0
T34	639650	639599	0	0
T72	216429	216378	0	0
T92	277832	277716	0	0
T103	367564	367513	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524555724	524448377	0	0
T1	258206	258082	0	0
T2	196468	196406	0	0
T3	124139	124088	0	0
T4	562763	562468	0	0
T5	644540	644430	0	0
T24	199875	199817	0	0
T34	639650	639599	0	0
T72	216429	216378	0	0
T92	277832	277716	0	0
T103	367564	367513	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1034	1034	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T24	1	1	0	0
T34	1	1	0	0
T72	1	1	0	0
T92	1	1	0	0
T103	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	524555724	53203	0	0
DepthKnown_A	524555724	524448377	0	0
RvalidKnown_A	524555724	524448377	0	0
WreadyKnown_A	524555724	524448377	0	0
gen_passthru_fifo.paramCheckPass	1034	1034	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524555724	53203	0	0
T1	258206	95	0	0
T2	196468	12	0	0
T3	124139	67	0	0
T4	562763	176	0	0
T5	644540	37	0	0
T24	199875	12	0	0
T34	639650	55	0	0
T72	216429	77	0	0
T92	277832	95	0	0
T103	367564	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524555724	524448377	0	0
T1	258206	258082	0	0
T2	196468	196406	0	0
T3	124139	124088	0	0
T4	562763	562468	0	0
T5	644540	644430	0	0
T24	199875	199817	0	0
T34	639650	639599	0	0
T72	216429	216378	0	0
T92	277832	277716	0	0
T103	367564	367513	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524555724	524448377	0	0
T1	258206	258082	0	0
T2	196468	196406	0	0
T3	124139	124088	0	0
T4	562763	562468	0	0
T5	644540	644430	0	0
T24	199875	199817	0	0
T34	639650	639599	0	0
T72	216429	216378	0	0
T92	277832	277716	0	0
T103	367564	367513	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524555724	524448377	0	0
T1	258206	258082	0	0
T2	196468	196406	0	0
T3	124139	124088	0	0
T4	562763	562468	0	0
T5	644540	644430	0	0
T24	199875	199817	0	0
T34	639650	639599	0	0
T72	216429	216378	0	0
T92	277832	277716	0	0
T103	367564	367513	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1034	1034	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T24	1	1	0	0
T34	1	1	0	0
T72	1	1	0	0
T92	1	1	0	0
T103	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	524555724	53203	0	0
DepthKnown_A	524555724	524448377	0	0
RvalidKnown_A	524555724	524448377	0	0
WreadyKnown_A	524555724	524448377	0	0
gen_passthru_fifo.paramCheckPass	1034	1034	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524555724	53203	0	0
T1	258206	95	0	0
T2	196468	12	0	0
T3	124139	67	0	0
T4	562763	176	0	0
T5	644540	37	0	0
T24	199875	12	0	0
T34	639650	55	0	0
T72	216429	77	0	0
T92	277832	95	0	0
T103	367564	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524555724	524448377	0	0
T1	258206	258082	0	0
T2	196468	196406	0	0
T3	124139	124088	0	0
T4	562763	562468	0	0
T5	644540	644430	0	0
T24	199875	199817	0	0
T34	639650	639599	0	0
T72	216429	216378	0	0
T92	277832	277716	0	0
T103	367564	367513	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524555724	524448377	0	0
T1	258206	258082	0	0
T2	196468	196406	0	0
T3	124139	124088	0	0
T4	562763	562468	0	0
T5	644540	644430	0	0
T24	199875	199817	0	0
T34	639650	639599	0	0
T72	216429	216378	0	0
T92	277832	277716	0	0
T103	367564	367513	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524555724	524448377	0	0
T1	258206	258082	0	0
T2	196468	196406	0	0
T3	124139	124088	0	0
T4	562763	562468	0	0
T5	644540	644430	0	0
T24	199875	199817	0	0
T34	639650	639599	0	0
T72	216429	216378	0	0
T92	277832	277716	0	0
T103	367564	367513	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1034	1034	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T24	1	1	0	0
T34	1	1	0	0
T72	1	1	0	0
T92	1	1	0	0
T103	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	524555724	13871	0	0
DepthKnown_A	524555724	524448377	0	0
RvalidKnown_A	524555724	524448377	0	0
WreadyKnown_A	524555724	524448377	0	0
gen_passthru_fifo.paramCheckPass	1034	1034	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524555724	13871	0	0
T1	258206	56	0	0
T2	196468	3	0	0
T3	124139	1	0	0
T4	562763	5	0	0
T5	644540	2	0	0
T24	199875	3	0	0
T34	639650	1	0	0
T72	216429	1	0	0
T92	277832	56	0	0
T103	367564	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524555724	524448377	0	0
T1	258206	258082	0	0
T2	196468	196406	0	0
T3	124139	124088	0	0
T4	562763	562468	0	0
T5	644540	644430	0	0
T24	199875	199817	0	0
T34	639650	639599	0	0
T72	216429	216378	0	0
T92	277832	277716	0	0
T103	367564	367513	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524555724	524448377	0	0
T1	258206	258082	0	0
T2	196468	196406	0	0
T3	124139	124088	0	0
T4	562763	562468	0	0
T5	644540	644430	0	0
T24	199875	199817	0	0
T34	639650	639599	0	0
T72	216429	216378	0	0
T92	277832	277716	0	0
T103	367564	367513	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524555724	524448377	0	0
T1	258206	258082	0	0
T2	196468	196406	0	0
T3	124139	124088	0	0
T4	562763	562468	0	0
T5	644540	644430	0	0
T24	199875	199817	0	0
T34	639650	639599	0	0
T72	216429	216378	0	0
T92	277832	277716	0	0
T103	367564	367513	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1034	1034	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T24	1	1	0	0
T34	1	1	0	0
T72	1	1	0	0
T92	1	1	0	0
T103	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	524555724	13871	0	0
DepthKnown_A	524555724	524448377	0	0
RvalidKnown_A	524555724	524448377	0	0
WreadyKnown_A	524555724	524448377	0	0
gen_passthru_fifo.paramCheckPass	1034	1034	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524555724	13871	0	0
T1	258206	56	0	0
T2	196468	3	0	0
T3	124139	1	0	0
T4	562763	5	0	0
T5	644540	2	0	0
T24	199875	3	0	0
T34	639650	1	0	0
T72	216429	1	0	0
T92	277832	56	0	0
T103	367564	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524555724	524448377	0	0
T1	258206	258082	0	0
T2	196468	196406	0	0
T3	124139	124088	0	0
T4	562763	562468	0	0
T5	644540	644430	0	0
T24	199875	199817	0	0
T34	639650	639599	0	0
T72	216429	216378	0	0
T92	277832	277716	0	0
T103	367564	367513	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524555724	524448377	0	0
T1	258206	258082	0	0
T2	196468	196406	0	0
T3	124139	124088	0	0
T4	562763	562468	0	0
T5	644540	644430	0	0
T24	199875	199817	0	0
T34	639650	639599	0	0
T72	216429	216378	0	0
T92	277832	277716	0	0
T103	367564	367513	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524555724	524448377	0	0
T1	258206	258082	0	0
T2	196468	196406	0	0
T3	124139	124088	0	0
T4	562763	562468	0	0
T5	644540	644430	0	0
T24	199875	199817	0	0
T34	639650	639599	0	0
T72	216429	216378	0	0
T92	277832	277716	0	0
T103	367564	367513	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1034	1034	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T24	1	1	0	0
T34	1	1	0	0
T72	1	1	0	0
T92	1	1	0	0
T103	1	1	0	0