Unified Coverage Report :: Module :: prim_sync_reqack_data

Module : prim_sync_reqack_data

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data	100.00	100.00					100.00

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.67	100.00	66.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
87.73	94.12	89.29	87.06		100.00	68.18	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_sync_reqack	91.67	100.00	66.67			100.00	100.00

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.67	100.00	66.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	84.62			100.00	100.00	u_edn_if

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_sync_reqack	91.67	100.00	66.67			100.00	100.00

Line Coverage for Module : prim_sync_reqack_data

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	153	0	0
CONT_ASSIGN	156	0	0
ALWAYS	159	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
93	1	1
153		unreachable
156		unreachable
159		unreachable
160		unreachable
162		unreachable

---

Assert Coverage for Module : prim_sync_reqack_data

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA	1049111448	4451	0	0
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB	1049111448	4451	0	0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA

Name	Attempts	Real Successes	Failures	Incomplete
Total	1049111448	4451	0	0
T1	258206	4	0	0
T2	196468	2	0	0
T3	124139	1	0	0
T4	562763	5	0	0
T5	644540	2	0	0
T19	130600	0	0	0
T24	199875	2	0	0
T34	639650	1	0	0
T38	170898	0	0	0
T72	216429	1	0	0
T91	38790	0	0	0
T92	277832	4	0	0
T103	367564	1	0	0
T127	472923	0	0	0
T128	370327	0	0	0
T209	96150	0	0	0
T219	109470	8	0	0
T220	0	10	0	0
T221	0	9	0	0
T228	128061	0	0	0
T307	0	8	0	0
T308	0	6	0	0
T309	0	8	0	0
T310	143792	0	0	0
T311	74922	0	0	0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB

Name	Attempts	Real Successes	Failures	Incomplete
Total	1049111448	4451	0	0
T1	258206	4	0	0
T2	196468	2	0	0
T3	124139	1	0	0
T4	562763	5	0	0
T5	644540	2	0	0
T19	130600	0	0	0
T24	199875	2	0	0
T34	639650	1	0	0
T38	170898	0	0	0
T72	216429	1	0	0
T91	38790	0	0	0
T92	277832	4	0	0
T103	367564	1	0	0
T127	472923	0	0	0
T128	370327	0	0	0
T209	96150	0	0	0
T219	109470	8	0	0
T220	0	10	0	0
T221	0	9	0	0
T228	128061	0	0	0
T307	0	8	0	0
T308	0	6	0	0
T309	0	8	0	0
T310	143792	0	0	0
T311	74922	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	153	0	0
CONT_ASSIGN	156	0	0
ALWAYS	159	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
93	1	1
153		unreachable
156		unreachable
159		unreachable
160		unreachable
162		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA	524555724	49	0	0
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB	524555724	49	0	0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA

Name	Attempts	Real Successes	Failures	Incomplete
Total	524555724	49	0	0
T19	130600	0	0	0
T38	170898	0	0	0
T91	38790	0	0	0
T127	472923	0	0	0
T128	370327	0	0	0
T209	96150	0	0	0
T219	109470	8	0	0
T220	0	10	0	0
T221	0	9	0	0
T228	128061	0	0	0
T307	0	8	0	0
T308	0	6	0	0
T309	0	8	0	0
T310	143792	0	0	0
T311	74922	0	0	0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB

Name	Attempts	Real Successes	Failures	Incomplete
Total	524555724	49	0	0
T19	130600	0	0	0
T38	170898	0	0	0
T91	38790	0	0	0
T127	472923	0	0	0
T128	370327	0	0	0
T209	96150	0	0	0
T219	109470	8	0	0
T220	0	10	0	0
T221	0	9	0	0
T228	128061	0	0	0
T307	0	8	0	0
T308	0	6	0	0
T309	0	8	0	0
T310	143792	0	0	0
T311	74922	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	153	0	0
CONT_ASSIGN	156	0	0
ALWAYS	159	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
93	1	1
153		unreachable
156		unreachable
159		unreachable
160		unreachable
162		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA	524555724	4402	0	0
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB	524555724	4402	0	0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA

Name	Attempts	Real Successes	Failures	Incomplete
Total	524555724	4402	0	0
T1	258206	4	0	0
T2	196468	2	0	0
T3	124139	1	0	0
T4	562763	5	0	0
T5	644540	2	0	0
T24	199875	2	0	0
T34	639650	1	0	0
T72	216429	1	0	0
T92	277832	4	0	0
T103	367564	1	0	0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB

Name	Attempts	Real Successes	Failures	Incomplete
Total	524555724	4402	0	0
T1	258206	4	0	0
T2	196468	2	0	0
T3	124139	1	0	0
T4	562763	5	0	0
T5	644540	2	0	0
T24	199875	2	0	0
T34	639650	1	0	0
T72	216429	1	0	0
T92	277832	4	0	0
T103	367564	1	0	0