Unified Coverage Report :: Group :: tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	3770938	1			T72	492		T73	79		T74	4016
values[2]	752889	1			T72	138		T73	50		T74	799
values[3]	108403	1			T72	1		T73	1		T74	20
values[4]	58928	1			T455	65		T456	11		T520	13
values[5]	39434	1			T455	51		T456	11		T520	13
values[6]	28621	1			T455	25		T456	7		T520	13
values[7]	22464	1			T455	26		T456	8		T520	13
values[8]	18849	1			T455	28		T456	2		T520	13
values[9]	17166	1			T455	37		T520	13		T521	1
values[10]	15076	1			T455	39		T520	13		T521	1
values[11]	13772	1			T455	29		T520	13		T521	1
values[12]	13012	1			T455	18		T520	13		T525	3
values[13]	12284	1			T455	23		T520	13		T525	2
values[14]	11534	1			T455	30		T520	14		T525	1
values[15]	11138	1			T455	24		T520	13		T525	1
values[16]	10699	1			T455	35		T520	13		T525	2
values[17]	10312	1			T455	33		T520	13		T525	3
values[18]	10078	1			T455	25		T520	13		T525	2
values[19]	9557	1			T455	13		T520	13		T525	2
values[20]	9373	1			T455	15		T520	13		T525	2
values[21]	9222	1			T455	23		T520	13		T525	2
values[22]	8719	1			T455	28		T520	13		T525	1
values[23]	8326	1			T455	21		T520	13		T525	1
values[24]	8240	1			T455	19		T520	14		T525	3
values[25]	7817	1			T455	23		T520	13		T525	2
values[26]	7278	1			T455	10		T520	13		T525	2
values[27]	6782	1			T455	14		T520	13		T525	2
values[28]	6692	1			T455	10		T520	13		T525	2
values[29]	6421	1			T455	6		T520	13		T525	2
values[30]	5963	1			T455	7		T520	13		T525	2
values[31]	5571	1			T455	11		T520	13		T525	2
values[32]	5024	1			T455	11		T520	13		T525	2
values[33]	4794	1			T455	13		T520	14		T525	2
values[34]	4432	1			T455	2		T520	13		T525	2
values[35]	4131	1			T455	2		T520	13		T525	2
values[36]	3927	1			T455	3		T520	14		T525	2
values[37]	3737	1			T455	11		T520	13		T525	2
values[38]	3571	1			T455	2		T520	13		T525	2
values[39]	3322	1			T520	13		T525	2		T809	7
values[40]	3380	1			T520	15		T525	2		T809	15
values[41]	3233	1			T520	13		T525	2		T809	16
values[42]	3170	1			T520	13		T525	1		T809	11
values[43]	3195	1			T520	13		T809	16		T532	31
values[44]	2988	1			T520	13		T809	7		T532	23
values[45]	3042	1			T520	13		T809	4		T532	25
values[46]	3003	1			T520	13		T809	14		T532	22
values[47]	2898	1			T520	14		T809	4		T532	24
values[48]	2903	1			T520	13		T809	8		T532	21
values[49]	2792	1			T520	13		T809	4		T532	14
values[50]	2592	1			T520	13		T809	4		T532	11
values[51]	2692	1			T520	13		T809	4		T532	18
values[52]	2638	1			T520	14		T809	6		T532	12
values[53]	2594	1			T520	13		T809	5		T532	13
values[54]	2562	1			T520	13		T809	9		T532	6
values[55]	2529	1			T520	14		T809	16		T532	12
values[56]	2477	1			T520	13		T809	4		T532	19
values[57]	2474	1			T520	13		T809	1		T532	11
values[58]	2345	1			T520	14		T809	4		T532	13
values[59]	2396	1			T520	13		T809	6		T532	14
values[60]	2434	1			T520	13		T532	15		T438	2
values[61]	2607	1			T520	13		T532	11		T438	5
values[62]	4091	1			T520	13		T532	9		T438	15
values[63]	10778	1			T520	13		T532	19		T438	68
values[64]	233994	1			T520	2454		T532	203		T438	202

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	4792815	1			T72	439		T73	114		T74	5733
values[2]	808105	1			T72	127		T73	26		T74	990
values[3]	84333	1			T72	18		T73	4		T74	109
values[4]	14632	1			T72	1		T74	6		T455	6
values[5]	5326	1			T455	5		T520	24		T521	21
values[6]	3279	1			T455	4		T520	6		T521	7
values[7]	2550	1			T455	2		T520	1		T521	1
values[8]	2310	1			T455	3		T525	3		T420	2
values[9]	2014	1			T455	3		T525	5		T420	2
values[10]	1837	1			T455	5		T525	3		T420	2
values[11]	1713	1			T455	3		T525	1		T420	2
values[12]	1574	1			T455	2		T525	1		T420	2
values[13]	1360	1			T455	3		T420	2		T532	20
values[14]	1289	1			T455	3		T420	2		T532	1
values[15]	1145	1			T455	5		T420	3		T532	4
values[16]	1179	1			T455	5		T420	2		T532	2
values[17]	1138	1			T455	5		T420	2		T532	2
values[18]	1027	1			T455	6		T420	2		T532	6
values[19]	938	1			T455	3		T420	2		T532	3
values[20]	870	1			T455	3		T420	2		T532	3
values[21]	816	1			T455	2		T420	3		T438	16
values[22]	784	1			T455	1		T420	2		T438	15
values[23]	731	1			T455	1		T420	2		T438	18
values[24]	802	1			T455	3		T420	2		T438	11
values[25]	814	1			T455	2		T420	2		T438	1
values[26]	824	1			T455	2		T420	2		T438	1
values[27]	723	1			T455	2		T420	2		T438	1
values[28]	653	1			T455	2		T420	2		T438	2
values[29]	618	1			T455	2		T420	2		T438	2
values[30]	624	1			T455	2		T420	3		T438	6
values[31]	602	1			T455	2		T420	2		T438	3
values[32]	563	1			T455	2		T420	1		T438	2
values[33]	521	1			T455	2		T420	1		T438	1
values[34]	485	1			T455	3		T420	2		T438	1
values[35]	441	1			T455	1		T420	2		T438	1
values[36]	431	1			T455	1		T420	2		T438	1
values[37]	460	1			T455	2		T420	2		T438	1
values[38]	440	1			T455	2		T420	2		T438	3
values[39]	388	1			T455	2		T420	2		T438	3
values[40]	393	1			T455	2		T420	2		T438	3
values[41]	434	1			T455	2		T420	2		T438	4
values[42]	429	1			T455	2		T420	2		T438	5
values[43]	417	1			T455	2		T420	2		T438	4
values[44]	376	1			T455	2		T420	2		T438	2
values[45]	383	1			T455	2		T420	2		T438	1
values[46]	378	1			T455	3		T420	3		T438	1
values[47]	380	1			T455	2		T420	2		T438	1
values[48]	337	1			T455	2		T420	2		T438	2
values[49]	327	1			T455	2		T420	2		T438	1
values[50]	335	1			T455	2		T420	1		T438	2
values[51]	319	1			T455	2		T420	1		T438	3
values[52]	314	1			T455	2		T420	2		T438	4
values[53]	323	1			T455	2		T420	1		T438	1
values[54]	334	1			T455	2		T420	1		T438	1
values[55]	324	1			T455	2		T420	2		T438	3
values[56]	317	1			T455	2		T420	2		T438	1
values[57]	308	1			T455	2		T420	2		T438	1
values[58]	319	1			T455	2		T420	2		T438	2
values[59]	326	1			T455	2		T420	2		T438	4
values[60]	320	1			T455	2		T420	2		T438	1
values[61]	342	1			T455	1		T420	2		T438	5
values[62]	570	1			T455	1		T420	2		T438	4
values[63]	2003	1			T455	4		T420	4		T438	35
values[64]	24110	1			T455	36		T420	104		T438	86

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	589161	1			T72	4		T73	4		T74	295
values[2]	2661062	1			T72	437		T73	57		T74	3264
values[3]	1205364	1			T72	149		T73	48		T74	1516
values[4]	151028	1			T72	2		T73	1		T74	78
values[5]	76641	1			T74	18		T455	41		T456	6
values[6]	49419	1			T74	4		T455	28		T456	2
values[7]	36871	1			T74	1		T455	29		T520	13
values[8]	29019	1			T74	1		T455	37		T520	13
values[9]	23900	1			T455	36		T520	13		T521	73
values[10]	20978	1			T455	30		T520	13		T521	40
values[11]	18670	1			T455	37		T520	13		T521	69
values[12]	17406	1			T455	43		T520	13		T521	99
values[13]	15950	1			T455	30		T520	13		T521	60
values[14]	14431	1			T455	26		T520	14		T521	19
values[15]	13626	1			T455	40		T520	13		T521	8
values[16]	13076	1			T455	24		T520	13		T521	15
values[17]	12346	1			T455	19		T520	13		T521	13
values[18]	11825	1			T455	26		T520	13		T521	19
values[19]	10771	1			T455	36		T520	13		T521	23
values[20]	10520	1			T455	26		T520	13		T521	30
values[21]	10379	1			T455	23		T520	13		T521	35
values[22]	10377	1			T455	19		T520	13		T521	14
values[23]	9772	1			T455	29		T520	13		T521	5
values[24]	9324	1			T455	32		T520	13		T521	5
values[25]	8777	1			T455	11		T520	13		T521	4
values[26]	8406	1			T455	20		T520	13		T521	9
values[27]	7989	1			T455	11		T520	13		T521	9
values[28]	7648	1			T455	8		T520	13		T521	5
values[29]	7112	1			T455	20		T520	13		T809	30
values[30]	6760	1			T455	21		T520	14		T809	24
values[31]	6413	1			T455	21		T520	13		T809	30
values[32]	5753	1			T455	22		T520	13		T809	25
values[33]	5389	1			T455	20		T520	13		T809	17
values[34]	4764	1			T455	15		T520	13		T809	14
values[35]	4643	1			T455	12		T520	13		T809	33
values[36]	4636	1			T455	5		T520	13		T809	22
values[37]	4303	1			T455	4		T520	13		T809	15
values[38]	4206	1			T455	1		T520	13		T809	16
values[39]	3925	1			T455	2		T520	13		T809	14
values[40]	3864	1			T455	2		T520	14		T809	20
values[41]	3763	1			T455	1		T520	13		T809	6
values[42]	3546	1			T455	1		T520	14		T809	8
values[43]	3499	1			T455	4		T520	13		T809	6
values[44]	3453	1			T455	3		T520	13		T809	7
values[45]	3370	1			T455	2		T520	13		T809	2
values[46]	3408	1			T455	1		T520	13		T809	4
values[47]	3411	1			T455	1		T520	13		T809	1
values[48]	3342	1			T455	3		T520	13		T809	1
values[49]	3178	1			T455	2		T520	13		T809	4
values[50]	3163	1			T455	2		T520	13		T809	4
values[51]	3166	1			T455	1		T520	13		T809	3
values[52]	2987	1			T455	2		T520	14		T809	2
values[53]	2938	1			T520	13		T809	1		T532	7
values[54]	2868	1			T520	13		T809	1		T532	16
values[55]	2741	1			T520	13		T532	19		T438	6
values[56]	2806	1			T520	13		T532	6		T438	8
values[57]	2787	1			T520	13		T532	11		T438	5
values[58]	2648	1			T520	13		T532	14		T438	10
values[59]	2562	1			T520	13		T532	9		T438	9
values[60]	2616	1			T520	14		T532	10		T438	12
values[61]	2727	1			T520	13		T532	15		T438	13
values[62]	3567	1			T520	13		T532	16		T438	19
values[63]	8832	1			T520	13		T532	22		T438	87
values[64]	226735	1			T520	2280		T532	81		T438	236