Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2118399	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

37376160

1

T1

9936

T2

18584

T3

7303

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	27750453	1			T1	3818		T2	4493		T3	4336
values[0x0]	10321111	1			T1	6118		T2	14091		T3	2967
values[0x1]	1422995	1			T1	633		T2	282		T3	185

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	800102	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

38694457

1

T1

10569

T2

18866

T3

7488

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	18375592	1			T1	5285		T2	9435		T3	3744
valid_sources[0x01]	18374628	1			T1	5284		T2	9431		T3	3744
valid_sources[0x02]	44315	1			T65	1		T148	80		T149	236
valid_sources[0x03]	44319	1			T148	68		T149	220		T534	40
valid_sources[0x04]	43606	1			T65	3		T148	73		T149	261
valid_sources[0x05]	44485	1			T148	91		T149	268		T534	44
valid_sources[0x06]	46668	1			T201	1		T148	60		T149	230
valid_sources[0x07]	44468	1			T65	1		T200	3		T148	82
valid_sources[0x08]	44535	1			T65	2		T201	2		T148	65
valid_sources[0x09]	44229	1			T200	2		T148	99		T149	263
valid_sources[0x0a]	44637	1			T201	1		T148	69		T149	231
valid_sources[0x0b]	43688	1			T148	78		T149	237		T534	39
valid_sources[0x0c]	44742	1			T148	81		T149	284		T534	37
valid_sources[0x0d]	43681	1			T65	3		T148	68		T149	241
valid_sources[0x0e]	43327	1			T148	67		T149	251		T534	32
valid_sources[0x0f]	43839	1			T65	1		T148	112		T149	258
valid_sources[0x10]	44236	1			T148	61		T149	217		T534	42
valid_sources[0x11]	43737	1			T201	2		T148	94		T149	233
valid_sources[0x12]	44087	1			T65	1		T76	21		T201	2
valid_sources[0x13]	44233	1			T65	2		T201	1		T251	39
valid_sources[0x14]	44161	1			T65	1		T200	1		T148	112
valid_sources[0x15]	44031	1			T65	3		T148	92		T149	236
valid_sources[0x16]	44048	1			T65	1		T200	2		T148	104
valid_sources[0x17]	45257	1			T65	3		T200	1		T148	95
valid_sources[0x18]	43725	1			T200	4		T201	1		T148	82
valid_sources[0x19]	44328	1			T65	3		T148	78		T149	255
valid_sources[0x1a]	44421	1			T148	74		T149	242		T534	36
valid_sources[0x1b]	44577	1			T148	100		T149	258		T534	35
valid_sources[0x1c]	44612	1			T65	1		T201	1		T148	89
valid_sources[0x1d]	44089	1			T201	5		T148	93		T149	231
valid_sources[0x1e]	44123	1			T148	87		T149	241		T534	39
valid_sources[0x1f]	44761	1			T65	1		T200	4		T201	2
valid_sources[0x20]	44135	1			T65	1		T200	1		T201	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26848967

1

T1

3818

T2

4493

T3

4336

values[0x0]

all_enables

biggest_size

10262631

1

T1

6118

T2

14091

T3

2967

values[0x1]

all_enables

biggest_size

264562

1

T65

16

T75

19

T76

24

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2905994	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

460157

1

T72

2

T73

19

T74

682

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1140611	1			T72	12		T73	39		T74	1574
values[0x0]	1086987	1			T72	2		T73	46		T74	1588
values[0x1]	1138553	1			T72	7		T73	45		T74	1660

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2250414	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1115737

1

T72

6

T73

40

T74

1635

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	52652	1			T72	1		T73	4		T74	65
valid_sources[0x01]	52883	1			T73	1		T74	91		T77	28
valid_sources[0x02]	52218	1			T73	1		T74	79		T77	19
valid_sources[0x03]	52205	1			T73	2		T74	67		T77	29
valid_sources[0x04]	52369	1			T73	3		T74	97		T77	36
valid_sources[0x05]	52327	1			T72	1		T73	2		T74	65
valid_sources[0x06]	52204	1			T73	1		T74	68		T77	30
valid_sources[0x07]	54305	1			T74	74		T77	19		T454	2
valid_sources[0x08]	52143	1			T72	1		T73	6		T74	64
valid_sources[0x09]	52141	1			T72	2		T73	2		T74	80
valid_sources[0x0a]	51541	1			T72	1		T73	3		T74	69
valid_sources[0x0b]	52976	1			T73	1		T74	105		T77	8
valid_sources[0x0c]	53944	1			T73	3		T74	71		T77	26
valid_sources[0x0d]	53863	1			T73	1		T74	71		T77	7
valid_sources[0x0e]	53852	1			T74	65		T77	11		T221	6
valid_sources[0x0f]	52171	1			T73	1		T74	86		T77	11
valid_sources[0x10]	51804	1			T73	1		T74	65		T77	26
valid_sources[0x11]	52478	1			T74	66		T77	33		T221	9
valid_sources[0x12]	52870	1			T73	2		T74	91		T77	20
valid_sources[0x13]	52647	1			T73	4		T74	71		T77	32
valid_sources[0x14]	52987	1			T72	1		T73	1		T74	60
valid_sources[0x15]	53138	1			T73	1		T74	65		T77	27
valid_sources[0x16]	51617	1			T72	1		T73	3		T74	70
valid_sources[0x17]	52554	1			T74	89		T77	39		T221	6
valid_sources[0x18]	52716	1			T74	70		T77	26		T454	1
valid_sources[0x19]	53264	1			T72	1		T73	2		T74	77
valid_sources[0x1a]	52939	1			T74	79		T77	19		T454	1
valid_sources[0x1b]	52305	1			T73	4		T74	81		T77	12
valid_sources[0x1c]	53376	1			T72	1		T73	6		T74	72
valid_sources[0x1d]	53367	1			T73	2		T74	79		T77	26
valid_sources[0x1e]	53123	1			T72	1		T73	3		T74	70
valid_sources[0x1f]	53146	1			T73	2		T74	77		T77	15
valid_sources[0x20]	52682	1			T73	2		T74	59		T77	23

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

48405

1

T74

64

T77

22

T454

5

values[0x0]

all_enables

biggest_size

363590

1

T72

1

T73

17

T74

545

values[0x1]

all_enables

biggest_size

48162

1

T72

1

T73

2

T74

73

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3082615	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

502108

1

T72

6

T73

19

T74

951

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1226498	1			T72	15		T73	46		T74	2306
values[0x0]	1130512	1			T72	4		T73	56		T74	2235
values[0x1]	1227713	1			T72	14		T73	42		T74	2285

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2365498	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1219225

1

T72

12

T73

43

T74

2300

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	55272	1			T73	8		T74	98		T77	22
valid_sources[0x01]	56644	1			T72	1		T73	1		T74	117
valid_sources[0x02]	56384	1			T73	1		T74	111		T454	2
valid_sources[0x03]	56240	1			T73	3		T74	122		T77	39
valid_sources[0x04]	55626	1			T72	2		T73	5		T74	120
valid_sources[0x05]	56068	1			T72	1		T73	5		T74	102
valid_sources[0x06]	55802	1			T72	2		T73	1		T74	95
valid_sources[0x07]	56611	1			T72	1		T73	1		T74	98
valid_sources[0x08]	55864	1			T73	4		T74	111		T77	11
valid_sources[0x09]	57325	1			T72	1		T73	3		T74	114
valid_sources[0x0a]	54966	1			T74	137		T77	15		T221	8
valid_sources[0x0b]	55967	1			T74	93		T77	19		T221	4
valid_sources[0x0c]	55877	1			T72	1		T73	1		T74	118
valid_sources[0x0d]	56058	1			T74	105		T454	1		T455	6
valid_sources[0x0e]	57048	1			T74	100		T77	61		T221	3
valid_sources[0x0f]	55146	1			T72	1		T73	5		T74	99
valid_sources[0x10]	54510	1			T73	1		T74	108		T77	69
valid_sources[0x11]	56007	1			T73	2		T74	114		T77	78
valid_sources[0x12]	55493	1			T72	1		T73	4		T74	86
valid_sources[0x13]	56429	1			T72	1		T73	2		T74	92
valid_sources[0x14]	55395	1			T73	2		T74	114		T77	11
valid_sources[0x15]	55821	1			T73	1		T74	117		T77	7
valid_sources[0x16]	54467	1			T73	1		T74	89		T77	7
valid_sources[0x17]	56484	1			T72	2		T73	1		T74	140
valid_sources[0x18]	56080	1			T73	4		T74	117		T221	9
valid_sources[0x19]	57091	1			T72	1		T73	3		T74	85
valid_sources[0x1a]	55103	1			T73	1		T74	110		T77	2
valid_sources[0x1b]	55451	1			T73	4		T74	92		T454	4
valid_sources[0x1c]	57007	1			T73	2		T74	125		T77	24
valid_sources[0x1d]	56596	1			T72	1		T73	4		T74	123
valid_sources[0x1e]	55808	1			T73	3		T74	95		T77	12
valid_sources[0x1f]	56954	1			T73	3		T74	119		T77	41
valid_sources[0x20]	55816	1			T73	1		T74	103		T77	103

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

52753

1

T72

2

T73

2

T74

85

values[0x0]

all_enables

biggest_size

396710

1

T72

4

T73

15

T74

765

values[0x1]

all_enables

biggest_size

52645

1

T73

2

T74

101

T77

26

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2929512	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

464573

1

T72

2

T73

15

T74

709

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1149591	1			T72	6		T73	34		T74	1752
values[0x0]	1095620	1			T72	2		T73	34		T74	1711
values[0x1]	1148874	1			T72	13		T73	42		T74	1688

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2268256	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1125829

1

T72

5

T73

39

T74

1718

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	52679	1			T72	1		T73	1		T74	72
valid_sources[0x01]	53361	1			T73	1		T74	100		T77	23
valid_sources[0x02]	53537	1			T73	2		T74	96		T77	3
valid_sources[0x03]	52861	1			T73	3		T74	82		T77	10
valid_sources[0x04]	54776	1			T72	1		T73	3		T74	108
valid_sources[0x05]	52849	1			T73	1		T74	79		T77	22
valid_sources[0x06]	53149	1			T72	1		T73	1		T74	65
valid_sources[0x07]	52913	1			T73	1		T74	86		T77	3
valid_sources[0x08]	53063	1			T73	2		T74	72		T77	9
valid_sources[0x09]	53089	1			T73	2		T74	88		T77	13
valid_sources[0x0a]	52944	1			T73	1		T74	54		T77	35
valid_sources[0x0b]	53503	1			T73	1		T74	71		T77	18
valid_sources[0x0c]	53193	1			T73	2		T74	94		T77	43
valid_sources[0x0d]	53489	1			T73	1		T74	88		T77	18
valid_sources[0x0e]	53262	1			T73	5		T74	71		T77	1
valid_sources[0x0f]	53364	1			T73	2		T74	135		T77	5
valid_sources[0x10]	52784	1			T73	1		T74	67		T77	25
valid_sources[0x11]	52078	1			T73	1		T74	88		T77	7
valid_sources[0x12]	52682	1			T73	1		T74	56		T454	4
valid_sources[0x13]	52998	1			T72	2		T73	1		T74	84
valid_sources[0x14]	52748	1			T73	1		T74	82		T77	1
valid_sources[0x15]	53225	1			T73	2		T74	80		T77	62
valid_sources[0x16]	52661	1			T72	3		T73	3		T74	82
valid_sources[0x17]	53016	1			T73	1		T74	92		T77	19
valid_sources[0x18]	52190	1			T74	69		T77	9		T454	2
valid_sources[0x19]	53875	1			T73	2		T74	74		T77	41
valid_sources[0x1a]	53053	1			T72	1		T73	2		T74	67
valid_sources[0x1b]	52232	1			T73	2		T74	112		T77	17
valid_sources[0x1c]	52775	1			T73	2		T74	72		T77	26
valid_sources[0x1d]	53366	1			T72	3		T73	3		T74	127
valid_sources[0x1e]	52918	1			T73	3		T74	91		T77	21
valid_sources[0x1f]	53416	1			T73	2		T74	84		T77	1
valid_sources[0x20]	52791	1			T74	63		T77	6		T221	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

48785

1

T73

1

T74

65

T77

29

values[0x0]

all_enables

biggest_size

367247

1

T72

1

T73

13

T74

573

values[0x1]

all_enables

biggest_size

48541

1

T72

1

T73

1

T74

71