Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	529562655	61148478	0	0
DepthKnown_A	529562655	529456194	0	0
RvalidKnown_A	529562655	529456194	0	0
WreadyKnown_A	529562655	529456194	0	0
gen_passthru_fifo.paramCheckPass	1025	1025	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529562655	61148478	0	0
T1	169897	18248	0	0
T2	532660	54295	0	0
T3	397705	72245	0	0
T4	195678	20999	0	0
T5	278631	32039	0	0
T20	179152	120275	0	0
T43	861295	741470	0	0
T84	73178	7984	0	0
T85	81127	7662	0	0
T86	227567	27418	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529562655	529456194	0	0
T1	169897	169788	0	0
T2	532660	532301	0	0
T3	397705	397689	0	0
T4	195678	195566	0	0
T5	278631	278409	0	0
T20	179152	179141	0	0
T43	861295	861244	0	0
T84	73178	73127	0	0
T85	81127	81069	0	0
T86	227567	227447	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529562655	529456194	0	0
T1	169897	169788	0	0
T2	532660	532301	0	0
T3	397705	397689	0	0
T4	195678	195566	0	0
T5	278631	278409	0	0
T20	179152	179141	0	0
T43	861295	861244	0	0
T84	73178	73127	0	0
T85	81127	81069	0	0
T86	227567	227447	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529562655	529456194	0	0
T1	169897	169788	0	0
T2	532660	532301	0	0
T3	397705	397689	0	0
T4	195678	195566	0	0
T5	278631	278409	0	0
T20	179152	179141	0	0
T43	861295	861244	0	0
T84	73178	73127	0	0
T85	81127	81069	0	0
T86	227567	227447	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1025	1025	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T20	1	1	0	0
T43	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0
T86	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	529562655	47449343	0	0
DepthKnown_A	529562655	529456194	0	0
RvalidKnown_A	529562655	529456194	0	0
WreadyKnown_A	529562655	529456194	0	0
gen_passthru_fifo.paramCheckPass	1025	1025	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529562655	47449343	0	0
T1	169897	14240	0	0
T2	532660	36699	0	0
T3	397705	36780	0	0
T4	195678	16893	0	0
T5	278631	22440	0	0
T20	179152	115292	0	0
T43	861295	312073	0	0
T84	73178	5610	0	0
T85	81127	5465	0	0
T86	227567	21596	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529562655	529456194	0	0
T1	169897	169788	0	0
T2	532660	532301	0	0
T3	397705	397689	0	0
T4	195678	195566	0	0
T5	278631	278409	0	0
T20	179152	179141	0	0
T43	861295	861244	0	0
T84	73178	73127	0	0
T85	81127	81069	0	0
T86	227567	227447	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529562655	529456194	0	0
T1	169897	169788	0	0
T2	532660	532301	0	0
T3	397705	397689	0	0
T4	195678	195566	0	0
T5	278631	278409	0	0
T20	179152	179141	0	0
T43	861295	861244	0	0
T84	73178	73127	0	0
T85	81127	81069	0	0
T86	227567	227447	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529562655	529456194	0	0
T1	169897	169788	0	0
T2	532660	532301	0	0
T3	397705	397689	0	0
T4	195678	195566	0	0
T5	278631	278409	0	0
T20	179152	179141	0	0
T43	861295	861244	0	0
T84	73178	73127	0	0
T85	81127	81069	0	0
T86	227567	227447	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1025	1025	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T20	1	1	0	0
T43	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0
T86	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	529562655	43568159	0	0
DepthKnown_A	529562655	529456194	0	0
RvalidKnown_A	529562655	529456194	0	0
WreadyKnown_A	529562655	529456194	0	0
gen_passthru_fifo.paramCheckPass	1025	1025	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529562655	43568159	0	0
T1	169897	10824	0	0
T2	532660	19704	0	0
T3	397705	9138	0	0
T4	195678	12502	0	0
T5	278631	15999	0	0
T20	179152	111901	0	0
T43	861295	258608	0	0
T84	73178	3547	0	0
T85	81127	3751	0	0
T86	227567	16720	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529562655	529456194	0	0
T1	169897	169788	0	0
T2	532660	532301	0	0
T3	397705	397689	0	0
T4	195678	195566	0	0
T5	278631	278409	0	0
T20	179152	179141	0	0
T43	861295	861244	0	0
T84	73178	73127	0	0
T85	81127	81069	0	0
T86	227567	227447	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529562655	529456194	0	0
T1	169897	169788	0	0
T2	532660	532301	0	0
T3	397705	397689	0	0
T4	195678	195566	0	0
T5	278631	278409	0	0
T20	179152	179141	0	0
T43	861295	861244	0	0
T84	73178	73127	0	0
T85	81127	81069	0	0
T86	227567	227447	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529562655	529456194	0	0
T1	169897	169788	0	0
T2	532660	532301	0	0
T3	397705	397689	0	0
T4	195678	195566	0	0
T5	278631	278409	0	0
T20	179152	179141	0	0
T43	861295	861244	0	0
T84	73178	73127	0	0
T85	81127	81069	0	0
T86	227567	227447	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1025	1025	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T20	1	1	0	0
T43	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0
T86	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	529562655	36765969	0	0
DepthKnown_A	529562655	529456194	0	0
RvalidKnown_A	529562655	529456194	0	0
WreadyKnown_A	529562655	529456194	0	0
gen_passthru_fifo.paramCheckPass	1025	1025	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529562655	36765969	0	0
T1	169897	10569	0	0
T2	532660	18866	0	0
T3	397705	7488	0	0
T4	195678	12232	0	0
T5	278631	15412	0	0
T20	179152	111503	0	0
T43	861295	61563	0	0
T84	73178	3401	0	0
T85	81127	3611	0	0
T86	227567	16339	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529562655	529456194	0	0
T1	169897	169788	0	0
T2	532660	532301	0	0
T3	397705	397689	0	0
T4	195678	195566	0	0
T5	278631	278409	0	0
T20	179152	179141	0	0
T43	861295	861244	0	0
T84	73178	73127	0	0
T85	81127	81069	0	0
T86	227567	227447	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529562655	529456194	0	0
T1	169897	169788	0	0
T2	532660	532301	0	0
T3	397705	397689	0	0
T4	195678	195566	0	0
T5	278631	278409	0	0
T20	179152	179141	0	0
T43	861295	861244	0	0
T84	73178	73127	0	0
T85	81127	81069	0	0
T86	227567	227447	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529562655	529456194	0	0
T1	169897	169788	0	0
T2	532660	532301	0	0
T3	397705	397689	0	0
T4	195678	195566	0	0
T5	278631	278409	0	0
T20	179152	179141	0	0
T43	861295	861244	0	0
T84	73178	73127	0	0
T85	81127	81069	0	0
T86	227567	227447	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1025	1025	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T20	1	1	0	0
T43	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0
T86	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	621707365	98910	0	0
DepthKnown_A	621707365	621584936	0	0
RvalidKnown_A	621707365	621584936	0	0
WreadyKnown_A	621707365	621584936	0	0
gen_passthru_fifo.paramCheckPass	2936	2936	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	621707365	98910	0	0
T1	169897	28	0	0
T2	532660	112	0	0
T3	397705	35	0	0
T4	195678	27	0	0
T5	278631	72	0	0
T20	179152	61	0	0
T43	861295	2	0	0
T84	73178	13	0	0
T85	81127	19	0	0
T86	227567	104	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	621707365	621584936	0	0
T1	169897	169788	0	0
T2	532660	532301	0	0
T3	397705	397689	0	0
T4	195678	195566	0	0
T5	278631	278409	0	0
T20	179152	179141	0	0
T43	861295	861244	0	0
T84	73178	73127	0	0
T85	81127	81069	0	0
T86	227567	227447	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	621707365	621584936	0	0
T1	169897	169788	0	0
T2	532660	532301	0	0
T3	397705	397689	0	0
T4	195678	195566	0	0
T5	278631	278409	0	0
T20	179152	179141	0	0
T43	861295	861244	0	0
T84	73178	73127	0	0
T85	81127	81069	0	0
T86	227567	227447	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	621707365	621584936	0	0
T1	169897	169788	0	0
T2	532660	532301	0	0
T3	397705	397689	0	0
T4	195678	195566	0	0
T5	278631	278409	0	0
T20	179152	179141	0	0
T43	861295	861244	0	0
T84	73178	73127	0	0
T85	81127	81069	0	0
T86	227567	227447	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2936	2936	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T20	1	1	0	0
T43	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0
T86	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	621707365	101809	0	0
DepthKnown_A	621707365	621584936	0	0
RvalidKnown_A	621707365	621584936	0	0
WreadyKnown_A	621707365	621584936	0	0
gen_passthru_fifo.paramCheckPass	2936	2936	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	621707365	101809	0	0
T1	169897	28	0	0
T2	532660	112	0	0
T3	397705	35	0	0
T4	195678	27	0	0
T5	278631	72	0	0
T20	179152	61	0	0
T43	861295	2	0	0
T84	73178	13	0	0
T85	81127	19	0	0
T86	227567	104	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	621707365	621584936	0	0
T1	169897	169788	0	0
T2	532660	532301	0	0
T3	397705	397689	0	0
T4	195678	195566	0	0
T5	278631	278409	0	0
T20	179152	179141	0	0
T43	861295	861244	0	0
T84	73178	73127	0	0
T85	81127	81069	0	0
T86	227567	227447	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	621707365	621584936	0	0
T1	169897	169788	0	0
T2	532660	532301	0	0
T3	397705	397689	0	0
T4	195678	195566	0	0
T5	278631	278409	0	0
T20	179152	179141	0	0
T43	861295	861244	0	0
T84	73178	73127	0	0
T85	81127	81069	0	0
T86	227567	227447	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	621707365	621584936	0	0
T1	169897	169788	0	0
T2	532660	532301	0	0
T3	397705	397689	0	0
T4	195678	195566	0	0
T5	278631	278409	0	0
T20	179152	179141	0	0
T43	861295	861244	0	0
T84	73178	73127	0	0
T85	81127	81069	0	0
T86	227567	227447	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2936	2936	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T20	1	1	0	0
T43	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0
T86	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	621707365	51482	0	0
DepthKnown_A	621707365	621584936	0	0
RvalidKnown_A	621707365	621584936	0	0
WreadyKnown_A	621707365	621584936	0	0
gen_passthru_fifo.paramCheckPass	2936	2936	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	621707365	51482	0	0
T1	169897	26	0	0
T2	532660	97	0	0
T3	397705	35	0	0
T4	195678	25	0	0
T5	278631	68	0	0
T20	179152	59	0	0
T43	861295	1	0	0
T84	73178	12	0	0
T85	81127	18	0	0
T86	227567	98	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	621707365	621584936	0	0
T1	169897	169788	0	0
T2	532660	532301	0	0
T3	397705	397689	0	0
T4	195678	195566	0	0
T5	278631	278409	0	0
T20	179152	179141	0	0
T43	861295	861244	0	0
T84	73178	73127	0	0
T85	81127	81069	0	0
T86	227567	227447	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	621707365	621584936	0	0
T1	169897	169788	0	0
T2	532660	532301	0	0
T3	397705	397689	0	0
T4	195678	195566	0	0
T5	278631	278409	0	0
T20	179152	179141	0	0
T43	861295	861244	0	0
T84	73178	73127	0	0
T85	81127	81069	0	0
T86	227567	227447	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	621707365	621584936	0	0
T1	169897	169788	0	0
T2	532660	532301	0	0
T3	397705	397689	0	0
T4	195678	195566	0	0
T5	278631	278409	0	0
T20	179152	179141	0	0
T43	861295	861244	0	0
T84	73178	73127	0	0
T85	81127	81069	0	0
T86	227567	227447	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2936	2936	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T20	1	1	0	0
T43	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0
T86	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	621707365	51482	0	0
DepthKnown_A	621707365	621584936	0	0
RvalidKnown_A	621707365	621584936	0	0
WreadyKnown_A	621707365	621584936	0	0
gen_passthru_fifo.paramCheckPass	2936	2936	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	621707365	51482	0	0
T1	169897	26	0	0
T2	532660	97	0	0
T3	397705	35	0	0
T4	195678	25	0	0
T5	278631	68	0	0
T20	179152	59	0	0
T43	861295	1	0	0
T84	73178	12	0	0
T85	81127	18	0	0
T86	227567	98	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	621707365	621584936	0	0
T1	169897	169788	0	0
T2	532660	532301	0	0
T3	397705	397689	0	0
T4	195678	195566	0	0
T5	278631	278409	0	0
T20	179152	179141	0	0
T43	861295	861244	0	0
T84	73178	73127	0	0
T85	81127	81069	0	0
T86	227567	227447	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	621707365	621584936	0	0
T1	169897	169788	0	0
T2	532660	532301	0	0
T3	397705	397689	0	0
T4	195678	195566	0	0
T5	278631	278409	0	0
T20	179152	179141	0	0
T43	861295	861244	0	0
T84	73178	73127	0	0
T85	81127	81069	0	0
T86	227567	227447	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	621707365	621584936	0	0
T1	169897	169788	0	0
T2	532660	532301	0	0
T3	397705	397689	0	0
T4	195678	195566	0	0
T5	278631	278409	0	0
T20	179152	179141	0	0
T43	861295	861244	0	0
T84	73178	73127	0	0
T85	81127	81069	0	0
T86	227567	227447	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2936	2936	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T20	1	1	0	0
T43	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0
T86	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	621707365	47428	0	0
DepthKnown_A	621707365	621584936	0	0
RvalidKnown_A	621707365	621584936	0	0
WreadyKnown_A	621707365	621584936	0	0
gen_passthru_fifo.paramCheckPass	2936	2936	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	621707365	47428	0	0
T1	169897	2	0	0
T2	532660	15	0	0
T3	397705	0	0	0
T4	195678	2	0	0
T5	278631	4	0	0
T20	179152	2	0	0
T43	861295	1	0	0
T84	73178	1	0	0
T85	81127	1	0	0
T86	227567	6	0	0
T181	0	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	621707365	621584936	0	0
T1	169897	169788	0	0
T2	532660	532301	0	0
T3	397705	397689	0	0
T4	195678	195566	0	0
T5	278631	278409	0	0
T20	179152	179141	0	0
T43	861295	861244	0	0
T84	73178	73127	0	0
T85	81127	81069	0	0
T86	227567	227447	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	621707365	621584936	0	0
T1	169897	169788	0	0
T2	532660	532301	0	0
T3	397705	397689	0	0
T4	195678	195566	0	0
T5	278631	278409	0	0
T20	179152	179141	0	0
T43	861295	861244	0	0
T84	73178	73127	0	0
T85	81127	81069	0	0
T86	227567	227447	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	621707365	621584936	0	0
T1	169897	169788	0	0
T2	532660	532301	0	0
T3	397705	397689	0	0
T4	195678	195566	0	0
T5	278631	278409	0	0
T20	179152	179141	0	0
T43	861295	861244	0	0
T84	73178	73127	0	0
T85	81127	81069	0	0
T86	227567	227447	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2936	2936	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T20	1	1	0	0
T43	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0
T86	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	621707365	50327	0	0
DepthKnown_A	621707365	621584936	0	0
RvalidKnown_A	621707365	621584936	0	0
WreadyKnown_A	621707365	621584936	0	0
gen_passthru_fifo.paramCheckPass	2936	2936	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	621707365	50327	0	0
T1	169897	2	0	0
T2	532660	15	0	0
T3	397705	0	0	0
T4	195678	2	0	0
T5	278631	4	0	0
T20	179152	2	0	0
T43	861295	1	0	0
T84	73178	1	0	0
T85	81127	1	0	0
T86	227567	6	0	0
T181	0	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	621707365	621584936	0	0
T1	169897	169788	0	0
T2	532660	532301	0	0
T3	397705	397689	0	0
T4	195678	195566	0	0
T5	278631	278409	0	0
T20	179152	179141	0	0
T43	861295	861244	0	0
T84	73178	73127	0	0
T85	81127	81069	0	0
T86	227567	227447	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	621707365	621584936	0	0
T1	169897	169788	0	0
T2	532660	532301	0	0
T3	397705	397689	0	0
T4	195678	195566	0	0
T5	278631	278409	0	0
T20	179152	179141	0	0
T43	861295	861244	0	0
T84	73178	73127	0	0
T85	81127	81069	0	0
T86	227567	227447	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	621707365	621584936	0	0
T1	169897	169788	0	0
T2	532660	532301	0	0
T3	397705	397689	0	0
T4	195678	195566	0	0
T5	278631	278409	0	0
T20	179152	179141	0	0
T43	861295	861244	0	0
T84	73178	73127	0	0
T85	81127	81069	0	0
T86	227567	227447	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2936	2936	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T20	1	1	0	0
T43	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0
T86	1	1	0	0