Line Coverage for Module :
tlul_adapter_host ( parameter MAX_REQS=2,EnableDataIntgGen=1,EnableRspDataIntgCheck=0,WordSize=2,OutstandingReqCntW=2,g_multiple_reqs.ReqNumW=1 + MAX_REQS=2,EnableDataIntgGen=0,EnableRspDataIntgCheck=0,WordSize=2,OutstandingReqCntW=2,g_multiple_reqs.ReqNumW=1 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 23 | 21 | 91.30 |
ALWAYS | 70 | 3 | 3 | 100.00 |
ALWAYS | 78 | 5 | 5 | 100.00 |
CONT_ASSIGN | 89 | 1 | 1 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 119 | 1 | 1 | 100.00 |
CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
ALWAYS | 132 | 4 | 3 | 75.00 |
CONT_ASSIGN | 141 | 1 | 1 | 100.00 |
CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
CONT_ASSIGN | 149 | 1 | 0 | 0.00 |
CONT_ASSIGN | 153 | 1 | 1 | 100.00 |
ALWAYS | 168 | 0 | 0 | |
ALWAYS | 178 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' or '../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
70 |
1 |
1 |
71 |
1 |
1 |
73 |
1 |
1 |
78 |
1 |
1 |
80 |
1 |
1 |
81 |
1 |
1 |
82 |
1 |
1 |
84 |
1 |
1 |
|
|
|
MISSING_ELSE |
89 |
1 |
1 |
94 |
1 |
1 |
96 |
1 |
1 |
116 |
1 |
1 |
118 |
1 |
1 |
119 |
1 |
1 |
120 |
1 |
1 |
132 |
1 |
1 |
133 |
1 |
1 |
134 |
1 |
1 |
135 |
0 |
1 |
|
|
|
MISSING_ELSE |
141 |
1 |
1 |
145 |
1 |
1 |
149 |
0 |
1 |
153 |
1 |
1 |
168 |
|
unreachable |
170 |
|
unreachable |
171 |
|
unreachable |
172 |
|
unreachable |
173 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
178 |
|
unreachable |
179 |
|
unreachable |
181 |
|
unreachable |
Line Coverage for Module :
tlul_adapter_host ( parameter MAX_REQS=8,EnableDataIntgGen=0,EnableRspDataIntgCheck=0,WordSize=2,OutstandingReqCntW=4,g_multiple_reqs.ReqNumW=3 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 20 | 90.91 |
ALWAYS | 70 | 3 | 3 | 100.00 |
ALWAYS | 78 | 5 | 5 | 100.00 |
CONT_ASSIGN | 89 | 1 | 1 | 100.00 |
CONT_ASSIGN | 94 | 0 | 0 | |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 119 | 1 | 1 | 100.00 |
CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
ALWAYS | 132 | 4 | 3 | 75.00 |
CONT_ASSIGN | 141 | 1 | 1 | 100.00 |
CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
CONT_ASSIGN | 149 | 1 | 0 | 0.00 |
CONT_ASSIGN | 153 | 1 | 1 | 100.00 |
ALWAYS | 168 | 0 | 0 | |
ALWAYS | 178 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' or '../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
70 |
1 |
1 |
71 |
1 |
1 |
73 |
1 |
1 |
78 |
1 |
1 |
80 |
1 |
1 |
81 |
1 |
1 |
82 |
1 |
1 |
84 |
1 |
1 |
|
|
|
MISSING_ELSE |
89 |
1 |
1 |
94 |
|
unreachable |
96 |
1 |
1 |
116 |
1 |
1 |
118 |
1 |
1 |
119 |
1 |
1 |
120 |
1 |
1 |
132 |
1 |
1 |
133 |
1 |
1 |
134 |
1 |
1 |
135 |
0 |
1 |
|
|
|
MISSING_ELSE |
141 |
1 |
1 |
145 |
1 |
1 |
149 |
0 |
1 |
153 |
1 |
1 |
168 |
|
unreachable |
170 |
|
unreachable |
171 |
|
unreachable |
172 |
|
unreachable |
173 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
178 |
|
unreachable |
179 |
|
unreachable |
181 |
|
unreachable |
Cond Coverage for Module :
tlul_adapter_host ( parameter MAX_REQS=8,EnableDataIntgGen=0,EnableRspDataIntgCheck=0,WordSize=2,OutstandingReqCntW=4,g_multiple_reqs.ReqNumW=3 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 13 | 9 | 69.23 |
Logical | 13 | 9 | 69.23 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 80
EXPRESSION (req_i && gnt_o)
--1-- --2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 81
EXPRESSION (g_multiple_reqs.source_q == g_multiple_reqs.MaxSource[(g_multiple_reqs.ReqNumW - 1):0])
--------------------------------------------1-------------------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 94
EXPRESSION (((~we_i)) ? ({top_pkg::TL_DBW {1'b1}}) : be_i)
----1----
-1- | Status | Tests |
0 | Unreachable | |
1 | Covered | T1,T2,T3 |
LINE 96
EXPRESSION (((~we_i)) ? Get : (((&be_i)) ? PutFullData : PutPartialData))
----1----
-1- | Status | Tests |
0 | Unreachable | |
1 | Covered | T1,T2,T3 |
LINE 96
SUB-EXPRESSION (((&be_i)) ? PutFullData : PutPartialData)
----1----
-1- | Status | Tests |
0 | Unreachable | |
1 | Unreachable | |
LINE 141
EXPRESSION (tl_i.d_error | intg_err)
------1----- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Not Covered | |
1 | 0 | Covered | T5,T43,T61 |
LINE 145
EXPRESSION (intg_err_q | intg_err)
-----1---- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
Cond Coverage for Module :
tlul_adapter_host ( parameter MAX_REQS=2,EnableDataIntgGen=1,EnableRspDataIntgCheck=0,WordSize=2,OutstandingReqCntW=2,g_multiple_reqs.ReqNumW=1 + MAX_REQS=2,EnableDataIntgGen=0,EnableRspDataIntgCheck=0,WordSize=2,OutstandingReqCntW=2,g_multiple_reqs.ReqNumW=1 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 17 | 14 | 82.35 |
Logical | 17 | 14 | 82.35 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 80
EXPRESSION (req_i && gnt_o)
--1-- --2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T65,T75,T76 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 81
EXPRESSION (g_multiple_reqs.source_q == g_multiple_reqs.MaxSource[0])
-----------------------------1----------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 94
EXPRESSION (((~we_i)) ? ({top_pkg::TL_DBW {1'b1}}) : be_i)
----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 96
EXPRESSION (((~we_i)) ? Get : (((&be_i)) ? PutFullData : PutPartialData))
----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 96
SUB-EXPRESSION (((&be_i)) ? PutFullData : PutPartialData)
----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 141
EXPRESSION (tl_i.d_error | intg_err)
------1----- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Not Covered | |
1 | 0 | Covered | T2,T5,T43 |
LINE 145
EXPRESSION (intg_err_q | intg_err)
-----1---- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
Branch Coverage for Module :
tlul_adapter_host ( parameter MAX_REQS=2,EnableDataIntgGen=1,EnableRspDataIntgCheck=0,WordSize=2,OutstandingReqCntW=2,g_multiple_reqs.ReqNumW=1 + MAX_REQS=2,EnableDataIntgGen=0,EnableRspDataIntgCheck=0,WordSize=2,OutstandingReqCntW=2,g_multiple_reqs.ReqNumW=1 )
Branch Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
Branches |
|
10 |
9 |
90.00 |
TERNARY |
94 |
2 |
2 |
100.00 |
IF |
132 |
3 |
2 |
66.67 |
IF |
70 |
2 |
2 |
100.00 |
IF |
80 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' or '../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 94 ((~we_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 132 if ((!rst_ni))
-2-: 134 if (intg_err)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Not Covered |
|
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 70 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 80 if ((req_i && gnt_o))
-2-: 81 if ((g_multiple_reqs.source_q == g_multiple_reqs.MaxSource[0]))
Branches:
-1- | -2- | Status | Tests |
1 |
1 |
Covered |
T1,T2,T3 |
1 |
0 |
Covered |
T1,T2,T3 |
0 |
- |
Covered |
T1,T2,T3 |
Branch Coverage for Module :
tlul_adapter_host ( parameter MAX_REQS=8,EnableDataIntgGen=0,EnableRspDataIntgCheck=0,WordSize=2,OutstandingReqCntW=4,g_multiple_reqs.ReqNumW=3 )
Branch Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
Branches |
|
9 |
8 |
88.89 |
TERNARY |
94 |
1 |
1 |
100.00 |
IF |
132 |
3 |
2 |
66.67 |
IF |
70 |
2 |
2 |
100.00 |
IF |
80 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' or '../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 94 ((~we_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Unreachable |
|
LineNo. Expression
-1-: 132 if ((!rst_ni))
-2-: 134 if (intg_err)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Not Covered |
|
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 70 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 80 if ((req_i && gnt_o))
-2-: 81 if ((g_multiple_reqs.source_q == g_multiple_reqs.MaxSource[(g_multiple_reqs.ReqNumW - 1):0]))
Branches:
-1- | -2- | Status | Tests |
1 |
1 |
Covered |
T1,T2,T3 |
1 |
0 |
Covered |
T1,T2,T3 |
0 |
- |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
tlul_adapter_host
Assertion Details
DontExceeedMaxReqs
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1059125310 |
104674649 |
0 |
0 |
T1 |
339794 |
29072 |
0 |
0 |
T2 |
1065320 |
73999 |
0 |
0 |
T3 |
795410 |
81383 |
0 |
0 |
T4 |
391356 |
33501 |
0 |
0 |
T5 |
557262 |
48038 |
0 |
0 |
T20 |
358304 |
232176 |
0 |
0 |
T43 |
1722590 |
1000078 |
0 |
0 |
T84 |
146356 |
11531 |
0 |
0 |
T85 |
162254 |
11413 |
0 |
0 |
T86 |
455134 |
44138 |
0 |
0 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_i_ibex
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 20 | 90.91 |
ALWAYS | 70 | 3 | 3 | 100.00 |
ALWAYS | 78 | 5 | 5 | 100.00 |
CONT_ASSIGN | 89 | 1 | 1 | 100.00 |
CONT_ASSIGN | 94 | 0 | 0 | |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 119 | 1 | 1 | 100.00 |
CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
ALWAYS | 132 | 4 | 3 | 75.00 |
CONT_ASSIGN | 141 | 1 | 1 | 100.00 |
CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
CONT_ASSIGN | 149 | 1 | 0 | 0.00 |
CONT_ASSIGN | 153 | 1 | 1 | 100.00 |
ALWAYS | 168 | 0 | 0 | |
ALWAYS | 178 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' or '../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
70 |
1 |
1 |
71 |
1 |
1 |
73 |
1 |
1 |
78 |
1 |
1 |
80 |
1 |
1 |
81 |
1 |
1 |
82 |
1 |
1 |
84 |
1 |
1 |
|
|
|
MISSING_ELSE |
89 |
1 |
1 |
94 |
|
unreachable |
96 |
1 |
1 |
116 |
1 |
1 |
118 |
1 |
1 |
119 |
1 |
1 |
120 |
1 |
1 |
132 |
1 |
1 |
133 |
1 |
1 |
134 |
1 |
1 |
135 |
0 |
1 |
|
|
|
MISSING_ELSE |
141 |
1 |
1 |
145 |
1 |
1 |
149 |
0 |
1 |
153 |
1 |
1 |
168 |
|
unreachable |
170 |
|
unreachable |
171 |
|
unreachable |
172 |
|
unreachable |
173 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
178 |
|
unreachable |
179 |
|
unreachable |
181 |
|
unreachable |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_i_ibex
| Total | Covered | Percent |
Conditions | 13 | 9 | 69.23 |
Logical | 13 | 9 | 69.23 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 80
EXPRESSION (req_i && gnt_o)
--1-- --2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 81
EXPRESSION (g_multiple_reqs.source_q == g_multiple_reqs.MaxSource[(g_multiple_reqs.ReqNumW - 1):0])
--------------------------------------------1-------------------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 94
EXPRESSION (((~we_i)) ? ({top_pkg::TL_DBW {1'b1}}) : be_i)
----1----
-1- | Status | Tests |
0 | Unreachable | |
1 | Covered | T1,T2,T3 |
LINE 96
EXPRESSION (((~we_i)) ? Get : (((&be_i)) ? PutFullData : PutPartialData))
----1----
-1- | Status | Tests |
0 | Unreachable | |
1 | Covered | T1,T2,T3 |
LINE 96
SUB-EXPRESSION (((&be_i)) ? PutFullData : PutPartialData)
----1----
-1- | Status | Tests |
0 | Unreachable | |
1 | Unreachable | |
LINE 141
EXPRESSION (tl_i.d_error | intg_err)
------1----- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Not Covered | |
1 | 0 | Covered | T5,T43,T61 |
LINE 145
EXPRESSION (intg_err_q | intg_err)
-----1---- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_i_ibex
| Line No. | Total | Covered | Percent |
Branches |
|
9 |
8 |
88.89 |
TERNARY |
94 |
1 |
1 |
100.00 |
IF |
132 |
3 |
2 |
66.67 |
IF |
70 |
2 |
2 |
100.00 |
IF |
80 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' or '../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 94 ((~we_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Unreachable |
|
LineNo. Expression
-1-: 132 if ((!rst_ni))
-2-: 134 if (intg_err)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Not Covered |
|
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 70 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 80 if ((req_i && gnt_o))
-2-: 81 if ((g_multiple_reqs.source_q == g_multiple_reqs.MaxSource[(g_multiple_reqs.ReqNumW - 1):0]))
Branches:
-1- | -2- | Status | Tests |
1 |
1 |
Covered |
T1,T2,T3 |
1 |
0 |
Covered |
T1,T2,T3 |
0 |
- |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_i_ibex
Assertion Details
DontExceeedMaxReqs
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
529562655 |
61148478 |
0 |
0 |
T1 |
169897 |
18248 |
0 |
0 |
T2 |
532660 |
54295 |
0 |
0 |
T3 |
397705 |
72245 |
0 |
0 |
T4 |
195678 |
20999 |
0 |
0 |
T5 |
278631 |
32039 |
0 |
0 |
T20 |
179152 |
120275 |
0 |
0 |
T43 |
861295 |
741470 |
0 |
0 |
T84 |
73178 |
7984 |
0 |
0 |
T85 |
81127 |
7662 |
0 |
0 |
T86 |
227567 |
27418 |
0 |
0 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex
| Line No. | Total | Covered | Percent |
TOTAL | | 23 | 21 | 91.30 |
ALWAYS | 70 | 3 | 3 | 100.00 |
ALWAYS | 78 | 5 | 5 | 100.00 |
CONT_ASSIGN | 89 | 1 | 1 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 119 | 1 | 1 | 100.00 |
CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
ALWAYS | 132 | 4 | 3 | 75.00 |
CONT_ASSIGN | 141 | 1 | 1 | 100.00 |
CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
CONT_ASSIGN | 149 | 1 | 0 | 0.00 |
CONT_ASSIGN | 153 | 1 | 1 | 100.00 |
ALWAYS | 168 | 0 | 0 | |
ALWAYS | 178 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' or '../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
70 |
1 |
1 |
71 |
1 |
1 |
73 |
1 |
1 |
78 |
1 |
1 |
80 |
1 |
1 |
81 |
1 |
1 |
82 |
1 |
1 |
84 |
1 |
1 |
|
|
|
MISSING_ELSE |
89 |
1 |
1 |
94 |
1 |
1 |
96 |
1 |
1 |
116 |
1 |
1 |
118 |
1 |
1 |
119 |
1 |
1 |
120 |
1 |
1 |
132 |
1 |
1 |
133 |
1 |
1 |
134 |
1 |
1 |
135 |
0 |
1 |
|
|
|
MISSING_ELSE |
141 |
1 |
1 |
145 |
1 |
1 |
149 |
0 |
1 |
153 |
1 |
1 |
168 |
|
unreachable |
170 |
|
unreachable |
171 |
|
unreachable |
172 |
|
unreachable |
173 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
178 |
|
unreachable |
179 |
|
unreachable |
181 |
|
unreachable |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex
| Total | Covered | Percent |
Conditions | 17 | 14 | 82.35 |
Logical | 17 | 14 | 82.35 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 80
EXPRESSION (req_i && gnt_o)
--1-- --2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T65,T75,T76 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 81
EXPRESSION (g_multiple_reqs.source_q == g_multiple_reqs.MaxSource[0])
-----------------------------1----------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 94
EXPRESSION (((~we_i)) ? ({top_pkg::TL_DBW {1'b1}}) : be_i)
----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 96
EXPRESSION (((~we_i)) ? Get : (((&be_i)) ? PutFullData : PutPartialData))
----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 96
SUB-EXPRESSION (((&be_i)) ? PutFullData : PutPartialData)
----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 141
EXPRESSION (tl_i.d_error | intg_err)
------1----- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Not Covered | |
1 | 0 | Covered | T2,T5,T43 |
LINE 145
EXPRESSION (intg_err_q | intg_err)
-----1---- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex
| Line No. | Total | Covered | Percent |
Branches |
|
10 |
9 |
90.00 |
TERNARY |
94 |
2 |
2 |
100.00 |
IF |
132 |
3 |
2 |
66.67 |
IF |
70 |
2 |
2 |
100.00 |
IF |
80 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' or '../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 94 ((~we_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 132 if ((!rst_ni))
-2-: 134 if (intg_err)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Not Covered |
|
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 70 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 80 if ((req_i && gnt_o))
-2-: 81 if ((g_multiple_reqs.source_q == g_multiple_reqs.MaxSource[0]))
Branches:
-1- | -2- | Status | Tests |
1 |
1 |
Covered |
T1,T2,T3 |
1 |
0 |
Covered |
T1,T2,T3 |
0 |
- |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex
Assertion Details
DontExceeedMaxReqs
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
529562655 |
43526171 |
0 |
0 |
T1 |
169897 |
10824 |
0 |
0 |
T2 |
532660 |
19704 |
0 |
0 |
T3 |
397705 |
9138 |
0 |
0 |
T4 |
195678 |
12502 |
0 |
0 |
T5 |
278631 |
15999 |
0 |
0 |
T20 |
179152 |
111901 |
0 |
0 |
T43 |
861295 |
258608 |
0 |
0 |
T84 |
73178 |
3547 |
0 |
0 |
T85 |
81127 |
3751 |
0 |
0 |
T86 |
227567 |
16720 |
0 |
0 |