Unified Coverage Report :: Module :: uart

Module : uart

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_uart0	100.00			100.00
tb.dut.top_earlgrey.u_uart1	100.00			100.00
tb.dut.top_earlgrey.u_uart2	100.00			100.00
tb.dut.top_earlgrey.u_uart3	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_uart0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : uart

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	308	308	100.00
Total Bits 0->1	154	154	100.00
Total Bits 1->0	154	154	100.00

Ports	40	40	100.00
Port Bits	308	308	100.00
Port Bits 0->1	154	154	100.00
Port Bits 1->0	154	154	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T43,T44,T10	Yes	T43,T44,T10	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T43,T44,T10	Yes	T43,T44,T10	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T72,*T73,*T74	Yes	T72,T73,T74	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T43,*T65,*T75	Yes	T43,T65,T75	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T65,T75,T76	Yes	T65,T75,T76	INPUT
tl_i.a_valid	Yes	Yes	T43,T44,T10	Yes	T43,T44,T10	INPUT
tl_o.a_ready	Yes	Yes	T43,T44,T10	Yes	T43,T44,T10	OUTPUT
tl_o.d_error	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T44,T10,T45	Yes	T44,T10,T45	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T43,T44,T10	Yes	T43,T44,T10	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T43,T44,T10	Yes	T43,T44,T10	OUTPUT
tl_o.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T43,*T712,*T260	Yes	T43,T712,T260	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T43,*T44,*T10	Yes	T43,T44,T10	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T43,T44,T10	Yes	T43,T44,T10	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T102,T297,T79	Yes	T102,T297,T79	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T79,T716,T80	Yes	T79,T80,T82	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T79,T80,T82	Yes	T79,T716,T80	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T102,T297,T79	Yes	T102,T297,T79	OUTPUT
cio_rx_i	Yes	Yes	T2,T3,T20	Yes	T1,T2,T3	INPUT
cio_tx_o	Yes	Yes	T43,T44,T45	Yes	T43,T44,T45	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T151,T213,T214	Yes	T151,T213,T214	OUTPUT
intr_tx_empty_o	Yes	Yes	T151,T213,T214	Yes	T151,T213,T214	OUTPUT
intr_rx_watermark_o	Yes	Yes	T151,T213,T214	Yes	T151,T213,T214	OUTPUT
intr_tx_done_o	Yes	Yes	T151,T213,T214	Yes	T151,T213,T214	OUTPUT
intr_rx_overflow_o	Yes	Yes	T151,T213,T214	Yes	T151,T213,T214	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T324,T327,T325	Yes	T324,T327,T325	OUTPUT
intr_rx_break_err_o	Yes	Yes	T324,T327,T325	Yes	T324,T327,T325	OUTPUT
intr_rx_timeout_o	Yes	Yes	T324,T327,T325	Yes	T324,T327,T325	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T324,T327,T325	Yes	T324,T327,T325	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart0

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	304	304	100.00
Total Bits 0->1	152	152	100.00
Total Bits 1->0	152	152	100.00

Ports	40	40	100.00
Port Bits	304	304	100.00
Port Bits 0->1	152	152	100.00
Port Bits 1->0	152	152	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T43,T44,T45	Yes	T43,T44,T45	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T43,T44,T45	Yes	T43,T44,T45	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T72,*T73,*T74	Yes	T72,T73,T74	INPUT
tl_i.a_address[29:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T43,*T65,*T75	Yes	T43,T65,T75	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T65,T75,T76	Yes	T65,T75,T76	INPUT
tl_i.a_valid	Yes	Yes	T43,T44,T45	Yes	T43,T44,T45	INPUT
tl_o.a_ready	Yes	Yes	T43,T44,T45	Yes	T43,T44,T45	OUTPUT
tl_o.d_error	Yes	Yes	T72,T73,T74	Yes	T72,T74,T77	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T44,T45,T40	Yes	T44,T45,T40	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T43,T44,T45	Yes	T43,T44,T45	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T43,T44,T45	Yes	T43,T44,T45	OUTPUT
tl_o.d_sink	Yes	Yes	T72,T74,T77	Yes	T72,T74,T77	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T43,*T712,*T260	Yes	T43,T712,T260	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T74,T77	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T43,*T44,*T45	Yes	T43,T44,T45	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T43,T44,T45	Yes	T43,T44,T45	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T79,T358,T716	Yes	T79,T358,T716	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T79,T716,T80	Yes	T79,T80,T82	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T79,T80,T82	Yes	T79,T716,T80	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T79,T358,T716	Yes	T79,T358,T716	OUTPUT
cio_rx_i	Yes	Yes	T2,T3,T20	Yes	T1,T2,T3	INPUT
cio_tx_o	Yes	Yes	T43,T44,T45	Yes	T43,T44,T45	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T216,T314,T315	Yes	T216,T314,T315	OUTPUT
intr_tx_empty_o	Yes	Yes	T216,T315,T338	Yes	T216,T315,T338	OUTPUT
intr_rx_watermark_o	Yes	Yes	T216,T315,T338	Yes	T216,T315,T338	OUTPUT
intr_tx_done_o	Yes	Yes	T216,T315,T338	Yes	T216,T315,T338	OUTPUT
intr_rx_overflow_o	Yes	Yes	T216,T315,T338	Yes	T216,T315,T338	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T324,T327,T325	Yes	T324,T327,T325	OUTPUT
intr_rx_break_err_o	Yes	Yes	T324,T327,T325	Yes	T324,T327,T325	OUTPUT
intr_rx_timeout_o	Yes	Yes	T324,T327,T325	Yes	T324,T327,T325	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T324,T327,T325	Yes	T324,T327,T325	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart1

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	40	40	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T10,T213,T214	Yes	T10,T213,T214	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T10,T213,T214	Yes	T10,T213,T214	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T72,*T73,*T74	Yes	T72,T73,T74	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T43,*T65,*T75	Yes	T43,T65,T75	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T65,T75,T76	Yes	T65,T75,T76	INPUT
tl_i.a_valid	Yes	Yes	T10,T213,T214	Yes	T10,T213,T214	INPUT
tl_o.a_ready	Yes	Yes	T10,T213,T214	Yes	T10,T213,T214	OUTPUT
tl_o.d_error	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T10,T213,T214	Yes	T10,T213,T214	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T10,T213,T214	Yes	T10,T213,T214	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T10,T213,T214	Yes	T10,T213,T214	OUTPUT
tl_o.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T72,*T74,*T77	Yes	T72,T73,T74	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T74,T77	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T10,*T213,*T214	Yes	T10,T213,T214	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T10,T213,T214	Yes	T10,T213,T214	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T102,T79,T49	Yes	T102,T79,T49	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T102,T79,T49	Yes	T102,T79,T49	OUTPUT
cio_rx_i	Yes	Yes	T213,T214,T342	Yes	T213,T214,T342	INPUT
cio_tx_o	Yes	Yes	T213,T214,T342	Yes	T213,T214,T342	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T213,T214,T342	Yes	T213,T214,T342	OUTPUT
intr_tx_empty_o	Yes	Yes	T213,T214,T342	Yes	T213,T214,T342	OUTPUT
intr_rx_watermark_o	Yes	Yes	T213,T214,T342	Yes	T213,T214,T342	OUTPUT
intr_tx_done_o	Yes	Yes	T213,T214,T342	Yes	T213,T214,T342	OUTPUT
intr_rx_overflow_o	Yes	Yes	T213,T214,T342	Yes	T213,T214,T342	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T324,T327,T325	Yes	T324,T327,T325	OUTPUT
intr_rx_break_err_o	Yes	Yes	T324,T327,T325	Yes	T324,T327,T325	OUTPUT
intr_rx_timeout_o	Yes	Yes	T324,T327,T325	Yes	T324,T327,T325	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T324,T327,T325	Yes	T324,T327,T325	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart2

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	40	40	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T10,T151,T152	Yes	T10,T151,T152	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T10,T151,T152	Yes	T10,T151,T152	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T72,*T73,*T74	Yes	T72,T73,T74	INPUT
tl_i.a_address[16:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T43,*T65,*T75	Yes	T43,T65,T75	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T65,T75,T76	Yes	T65,T75,T76	INPUT
tl_i.a_valid	Yes	Yes	T10,T151,T152	Yes	T10,T151,T152	INPUT
tl_o.a_ready	Yes	Yes	T10,T151,T152	Yes	T10,T151,T152	OUTPUT
tl_o.d_error	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T10,T151,T152	Yes	T10,T151,T152	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T10,T151,T152	Yes	T10,T151,T152	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T10,T151,T152	Yes	T10,T151,T152	OUTPUT
tl_o.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T72,*T74,*T77	Yes	T72,T73,T74	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T72,T74,T77	Yes	T72,T73,T74	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T10,*T151,*T152	Yes	T10,T151,T152	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T10,T151,T152	Yes	T10,T151,T152	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T297,T79,T49	Yes	T297,T79,T49	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T297,T79,T49	Yes	T297,T79,T49	OUTPUT
cio_rx_i	Yes	Yes	T151,T152,T339	Yes	T151,T152,T339	INPUT
cio_tx_o	Yes	Yes	T151,T152,T339	Yes	T151,T152,T339	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T151,T152,T339	Yes	T151,T152,T339	OUTPUT
intr_tx_empty_o	Yes	Yes	T151,T152,T339	Yes	T151,T152,T339	OUTPUT
intr_rx_watermark_o	Yes	Yes	T151,T152,T339	Yes	T151,T152,T339	OUTPUT
intr_tx_done_o	Yes	Yes	T151,T152,T339	Yes	T151,T152,T339	OUTPUT
intr_rx_overflow_o	Yes	Yes	T151,T152,T339	Yes	T151,T152,T339	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T324,T327,T325	Yes	T324,T327,T325	OUTPUT
intr_rx_break_err_o	Yes	Yes	T324,T327,T325	Yes	T324,T327,T325	OUTPUT
intr_rx_timeout_o	Yes	Yes	T324,T327,T325	Yes	T324,T327,T325	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T324,T327,T325	Yes	T324,T327,T325	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart3

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	308	308	100.00
Total Bits 0->1	154	154	100.00
Total Bits 1->0	154	154	100.00

Ports	40	40	100.00
Port Bits	308	308	100.00
Port Bits 0->1	154	154	100.00
Port Bits 1->0	154	154	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T13,T10,T15	Yes	T13,T10,T15	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T13,T10,T15	Yes	T13,T10,T15	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T72,*T73,*T74	Yes	T72,T73,T74	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T43,*T65,*T75	Yes	T43,T65,T75	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T65,T75,T76	Yes	T65,T75,T76	INPUT
tl_i.a_valid	Yes	Yes	T13,T10,T15	Yes	T13,T10,T15	INPUT
tl_o.a_ready	Yes	Yes	T13,T10,T15	Yes	T13,T10,T15	OUTPUT
tl_o.d_error	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T13,T10,T15	Yes	T13,T10,T15	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T13,T10,T15	Yes	T13,T10,T15	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T13,T10,T15	Yes	T13,T10,T15	OUTPUT
tl_o.d_sink	Yes	Yes	T72,T74,T77	Yes	T72,T74,T77	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T72,*T74,*T77	Yes	T72,T74,T77	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T72,T74,T77	Yes	T72,T73,T74	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T13,*T10,*T15	Yes	T13,T10,T15	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T13,T10,T15	Yes	T13,T10,T15	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T79,T49,T80	Yes	T79,T49,T80	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T79,T49,T80	Yes	T79,T49,T80	OUTPUT
cio_rx_i	Yes	Yes	T13,T15,T95	Yes	T13,T15,T95	INPUT
cio_tx_o	Yes	Yes	T13,T15,T95	Yes	T13,T15,T95	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T13,T15,T95	Yes	T13,T15,T95	OUTPUT
intr_tx_empty_o	Yes	Yes	T13,T15,T95	Yes	T13,T15,T95	OUTPUT
intr_rx_watermark_o	Yes	Yes	T13,T15,T95	Yes	T13,T15,T95	OUTPUT
intr_tx_done_o	Yes	Yes	T13,T15,T95	Yes	T13,T15,T95	OUTPUT
intr_rx_overflow_o	Yes	Yes	T13,T15,T95	Yes	T13,T15,T95	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T324,T327,T325	Yes	T324,T327,T325	OUTPUT
intr_rx_break_err_o	Yes	Yes	T324,T327,T325	Yes	T324,T327,T325	OUTPUT
intr_rx_timeout_o	Yes	Yes	T324,T327,T325	Yes	T324,T327,T325	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T324,T327,T325	Yes	T324,T327,T325	OUTPUT

*Tests covering at least one bit in the range