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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.17 95.54 94.10 95.34 94.92 97.53 99.58


Total test records in report: 2934
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T341 /workspace/coverage/default/2.chip_sw_entropy_src_csrng.753421894 Aug 18 07:08:19 PM PDT 24 Aug 18 07:40:55 PM PDT 24 8771723442 ps
T282 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.2549786342 Aug 18 07:03:13 PM PDT 24 Aug 18 08:36:47 PM PDT 24 18282614632 ps
T938 /workspace/coverage/default/2.chip_sw_entropy_src_kat_test.4162988467 Aug 18 07:09:13 PM PDT 24 Aug 18 07:12:58 PM PDT 24 2840229824 ps
T939 /workspace/coverage/default/2.rom_keymgr_functest.4289394251 Aug 18 07:14:36 PM PDT 24 Aug 18 07:25:44 PM PDT 24 5155442236 ps
T719 /workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.3970137022 Aug 18 06:56:18 PM PDT 24 Aug 18 07:16:27 PM PDT 24 9030551006 ps
T750 /workspace/coverage/default/5.chip_sw_all_escalation_resets.346078190 Aug 18 07:14:04 PM PDT 24 Aug 18 07:22:48 PM PDT 24 4085091328 ps
T83 /workspace/coverage/default/0.rom_e2e_jtag_debug_rma.616510768 Aug 18 06:55:37 PM PDT 24 Aug 18 07:31:06 PM PDT 24 11956701648 ps
T79 /workspace/coverage/default/0.chip_jtag_csr_rw.4034489770 Aug 18 06:43:25 PM PDT 24 Aug 18 06:48:01 PM PDT 24 4658606978 ps
T940 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1828011441 Aug 18 07:11:57 PM PDT 24 Aug 18 07:17:19 PM PDT 24 2982821276 ps
T283 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.958356307 Aug 18 07:03:20 PM PDT 24 Aug 18 08:39:49 PM PDT 24 23667788131 ps
T717 /workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.3761426543 Aug 18 07:01:19 PM PDT 24 Aug 18 07:12:20 PM PDT 24 4946796616 ps
T941 /workspace/coverage/default/0.chip_sw_aes_masking_off.533857110 Aug 18 06:55:24 PM PDT 24 Aug 18 07:02:06 PM PDT 24 3416480389 ps
T942 /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.1909910801 Aug 18 07:17:12 PM PDT 24 Aug 18 08:11:46 PM PDT 24 14790753504 ps
T943 /workspace/coverage/default/0.chip_sw_edn_auto_mode.1863249131 Aug 18 06:56:25 PM PDT 24 Aug 18 07:17:19 PM PDT 24 6235812650 ps
T944 /workspace/coverage/default/1.chip_sw_example_flash.2293227083 Aug 18 06:54:01 PM PDT 24 Aug 18 06:58:31 PM PDT 24 3121830600 ps
T376 /workspace/coverage/default/2.chip_sw_flash_crash_alert.3463905602 Aug 18 07:10:21 PM PDT 24 Aug 18 07:21:45 PM PDT 24 5509328808 ps
T159 /workspace/coverage/default/2.chip_plic_all_irqs_10.1793198642 Aug 18 07:09:01 PM PDT 24 Aug 18 07:17:47 PM PDT 24 3728833624 ps
T945 /workspace/coverage/default/0.chip_sw_kmac_mode_cshake.1327428586 Aug 18 06:53:23 PM PDT 24 Aug 18 06:57:26 PM PDT 24 2731392672 ps
T946 /workspace/coverage/default/7.chip_sw_uart_rand_baudrate.1361263466 Aug 18 07:15:39 PM PDT 24 Aug 18 07:40:16 PM PDT 24 8106732180 ps
T947 /workspace/coverage/default/0.rom_e2e_smoke.2969474408 Aug 18 07:00:32 PM PDT 24 Aug 18 08:00:41 PM PDT 24 15635918366 ps
T948 /workspace/coverage/default/2.chip_sw_rv_dm_access_after_wakeup.611861562 Aug 18 07:10:39 PM PDT 24 Aug 18 07:21:43 PM PDT 24 5823343856 ps
T382 /workspace/coverage/default/1.chip_tap_straps_dev.1762923484 Aug 18 06:54:15 PM PDT 24 Aug 18 06:56:58 PM PDT 24 2794550444 ps
T212 /workspace/coverage/default/1.chip_sw_inject_scramble_seed.2327139128 Aug 18 06:56:18 PM PDT 24 Aug 18 10:16:07 PM PDT 24 64302325624 ps
T795 /workspace/coverage/default/21.chip_sw_all_escalation_resets.2500773592 Aug 18 07:16:27 PM PDT 24 Aug 18 07:29:15 PM PDT 24 5075308030 ps
T85 /workspace/coverage/default/0.chip_sw_alert_handler_entropy.1265360535 Aug 18 06:51:46 PM PDT 24 Aug 18 06:57:57 PM PDT 24 4292759039 ps
T180 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.1058737941 Aug 18 06:54:53 PM PDT 24 Aug 18 07:05:38 PM PDT 24 4971418076 ps
T949 /workspace/coverage/default/6.chip_sw_lc_ctrl_transition.2414409419 Aug 18 07:13:02 PM PDT 24 Aug 18 07:29:22 PM PDT 24 13198086256 ps
T373 /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2788729802 Aug 18 06:57:11 PM PDT 24 Aug 18 07:16:29 PM PDT 24 8690238327 ps
T779 /workspace/coverage/default/33.chip_sw_all_escalation_resets.1724584250 Aug 18 07:17:05 PM PDT 24 Aug 18 07:25:21 PM PDT 24 4510176536 ps
T950 /workspace/coverage/default/1.chip_sw_hmac_enc_idle.2704470968 Aug 18 06:56:04 PM PDT 24 Aug 18 07:00:34 PM PDT 24 3040165610 ps
T76 /workspace/coverage/default/1.chip_tap_straps_testunlock0.2335926601 Aug 18 06:53:55 PM PDT 24 Aug 18 06:58:53 PM PDT 24 4164460952 ps
T765 /workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.1254702873 Aug 18 07:18:34 PM PDT 24 Aug 18 07:25:42 PM PDT 24 4202790200 ps
T156 /workspace/coverage/default/1.rom_raw_unlock.2910129858 Aug 18 06:57:23 PM PDT 24 Aug 18 07:00:48 PM PDT 24 4066226347 ps
T951 /workspace/coverage/default/2.chip_sw_ast_clk_outputs.4183709494 Aug 18 07:09:45 PM PDT 24 Aug 18 07:25:29 PM PDT 24 7025020368 ps
T232 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.3208193854 Aug 18 07:08:08 PM PDT 24 Aug 18 07:50:22 PM PDT 24 13103220361 ps
T141 /workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.3641199375 Aug 18 06:52:56 PM PDT 24 Aug 18 07:06:13 PM PDT 24 7369518968 ps
T952 /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.1982558374 Aug 18 07:14:21 PM PDT 24 Aug 18 07:27:49 PM PDT 24 8431357960 ps
T953 /workspace/coverage/default/0.chip_sw_example_manufacturer.2682551939 Aug 18 06:54:54 PM PDT 24 Aug 18 06:59:04 PM PDT 24 3081738912 ps
T21 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.2304307621 Aug 18 06:53:09 PM PDT 24 Aug 18 07:53:46 PM PDT 24 20272935069 ps
T25 /workspace/coverage/default/0.chip_sw_gpio.3609987889 Aug 18 06:51:21 PM PDT 24 Aug 18 06:59:01 PM PDT 24 3978637060 ps
T741 /workspace/coverage/default/68.chip_sw_all_escalation_resets.319138824 Aug 18 07:19:47 PM PDT 24 Aug 18 07:27:54 PM PDT 24 5186856070 ps
T954 /workspace/coverage/default/1.chip_sw_kmac_smoketest.372169483 Aug 18 07:02:00 PM PDT 24 Aug 18 07:07:15 PM PDT 24 2828577384 ps
T336 /workspace/coverage/default/0.chip_plic_all_irqs_20.3101105639 Aug 18 06:55:50 PM PDT 24 Aug 18 07:09:53 PM PDT 24 4861048408 ps
T807 /workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.1813486946 Aug 18 07:14:38 PM PDT 24 Aug 18 07:20:28 PM PDT 24 3564732786 ps
T955 /workspace/coverage/default/1.rom_e2e_self_hash.3685205054 Aug 18 07:07:57 PM PDT 24 Aug 18 08:50:08 PM PDT 24 25817383028 ps
T18 /workspace/coverage/default/0.chip_sw_usbdev_pincfg.4228843246 Aug 18 06:52:17 PM PDT 24 Aug 18 08:47:33 PM PDT 24 31968646024 ps
T956 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3327820916 Aug 18 06:58:14 PM PDT 24 Aug 18 07:09:33 PM PDT 24 4480391668 ps
T957 /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.1380582051 Aug 18 07:10:57 PM PDT 24 Aug 18 07:14:54 PM PDT 24 3050096484 ps
T242 /workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.3035040750 Aug 18 06:55:29 PM PDT 24 Aug 18 08:30:05 PM PDT 24 52077598372 ps
T735 /workspace/coverage/default/61.chip_sw_all_escalation_resets.956264579 Aug 18 07:18:52 PM PDT 24 Aug 18 07:29:40 PM PDT 24 5570793976 ps
T958 /workspace/coverage/default/2.rom_e2e_asm_init_prod.733028513 Aug 18 07:16:07 PM PDT 24 Aug 18 08:21:38 PM PDT 24 15854451857 ps
T233 /workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.3869155650 Aug 18 06:56:03 PM PDT 24 Aug 18 07:30:54 PM PDT 24 9247927640 ps
T745 /workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.3902038787 Aug 18 06:52:51 PM PDT 24 Aug 18 07:03:00 PM PDT 24 4573336820 ps
T188 /workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.1902899928 Aug 18 07:13:53 PM PDT 24 Aug 18 07:27:54 PM PDT 24 7693231668 ps
T959 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.874952269 Aug 18 06:56:30 PM PDT 24 Aug 18 07:06:19 PM PDT 24 4603141262 ps
T960 /workspace/coverage/default/6.chip_sw_uart_rand_baudrate.2548774407 Aug 18 07:13:20 PM PDT 24 Aug 18 07:43:50 PM PDT 24 7876891868 ps
T746 /workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.2505738047 Aug 18 07:21:16 PM PDT 24 Aug 18 07:27:58 PM PDT 24 3704273172 ps
T177 /workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.4254149829 Aug 18 07:03:22 PM PDT 24 Aug 18 07:05:56 PM PDT 24 2652041326 ps
T835 /workspace/coverage/default/17.chip_sw_all_escalation_resets.2432046901 Aug 18 07:15:42 PM PDT 24 Aug 18 07:26:13 PM PDT 24 6294055326 ps
T961 /workspace/coverage/default/0.chip_sw_flash_ctrl_access.2501192312 Aug 18 07:00:21 PM PDT 24 Aug 18 07:18:52 PM PDT 24 5194814080 ps
T962 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2091278716 Aug 18 06:59:35 PM PDT 24 Aug 18 07:10:34 PM PDT 24 5321981200 ps
T377 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.954724887 Aug 18 06:54:10 PM PDT 24 Aug 18 07:31:54 PM PDT 24 22087255820 ps
T751 /workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.1564114527 Aug 18 07:16:19 PM PDT 24 Aug 18 07:22:44 PM PDT 24 4256402010 ps
T339 /workspace/coverage/default/0.chip_sw_rstmgr_alert_info.4257498122 Aug 18 06:55:15 PM PDT 24 Aug 18 07:23:58 PM PDT 24 9499401982 ps
T234 /workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.577702098 Aug 18 06:57:46 PM PDT 24 Aug 18 07:39:56 PM PDT 24 11790033500 ps
T963 /workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.733045756 Aug 18 07:14:35 PM PDT 24 Aug 18 08:35:49 PM PDT 24 20936415848 ps
T964 /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.4199664321 Aug 18 07:02:16 PM PDT 24 Aug 18 08:11:55 PM PDT 24 15722221094 ps
T375 /workspace/coverage/default/19.chip_sw_all_escalation_resets.1058500083 Aug 18 07:15:20 PM PDT 24 Aug 18 07:25:50 PM PDT 24 4382694656 ps
T965 /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.3986669202 Aug 18 07:02:56 PM PDT 24 Aug 18 07:20:41 PM PDT 24 5608007182 ps
T966 /workspace/coverage/default/0.rom_e2e_asm_init_prod.1004385651 Aug 18 06:59:16 PM PDT 24 Aug 18 08:02:11 PM PDT 24 15484277801 ps
T413 /workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.1424231728 Aug 18 06:54:50 PM PDT 24 Aug 18 07:02:51 PM PDT 24 9306049503 ps
T967 /workspace/coverage/default/2.chip_sw_example_concurrency.3564037083 Aug 18 07:01:14 PM PDT 24 Aug 18 07:05:18 PM PDT 24 2856393928 ps
T968 /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.3494602539 Aug 18 06:52:38 PM PDT 24 Aug 18 06:57:21 PM PDT 24 2644969220 ps
T250 /workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.359345483 Aug 18 07:07:47 PM PDT 24 Aug 18 07:21:39 PM PDT 24 5828726280 ps
T969 /workspace/coverage/default/1.chip_sw_ast_clk_outputs.816129560 Aug 18 06:57:37 PM PDT 24 Aug 18 07:12:32 PM PDT 24 8155429304 ps
T970 /workspace/coverage/default/1.chip_sw_alert_handler_ping_ok.500842871 Aug 18 06:58:41 PM PDT 24 Aug 18 07:21:36 PM PDT 24 7646513800 ps
T526 /workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.3170954120 Aug 18 07:06:37 PM PDT 24 Aug 18 07:19:29 PM PDT 24 4609257224 ps
T12 /workspace/coverage/default/0.chip_sw_spi_device_pass_through.644122640 Aug 18 06:51:54 PM PDT 24 Aug 18 07:06:21 PM PDT 24 6927324860 ps
T235 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.2560729030 Aug 18 07:05:05 PM PDT 24 Aug 18 07:20:14 PM PDT 24 6550836103 ps
T971 /workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.753099016 Aug 18 06:56:04 PM PDT 24 Aug 18 07:18:17 PM PDT 24 6217321240 ps
T972 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.783180480 Aug 18 06:59:31 PM PDT 24 Aug 18 08:14:51 PM PDT 24 15613363064 ps
T809 /workspace/coverage/default/25.chip_sw_all_escalation_resets.3876622705 Aug 18 07:16:34 PM PDT 24 Aug 18 07:26:40 PM PDT 24 5814239324 ps
T222 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.57513237 Aug 18 07:10:19 PM PDT 24 Aug 18 07:31:10 PM PDT 24 7045477416 ps
T973 /workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.183443174 Aug 18 07:04:46 PM PDT 24 Aug 18 07:12:47 PM PDT 24 4523903489 ps
T34 /workspace/coverage/default/1.chip_sw_spi_host_tx_rx.2152555704 Aug 18 06:54:04 PM PDT 24 Aug 18 06:59:55 PM PDT 24 2612127476 ps
T974 /workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.3020522979 Aug 18 06:55:07 PM PDT 24 Aug 18 07:03:57 PM PDT 24 7421982908 ps
T975 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac.1443332749 Aug 18 06:53:24 PM PDT 24 Aug 18 06:57:59 PM PDT 24 3230134532 ps
T243 /workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.3924573462 Aug 18 07:03:52 PM PDT 24 Aug 18 08:44:43 PM PDT 24 51773861707 ps
T976 /workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.706020132 Aug 18 07:06:35 PM PDT 24 Aug 18 07:16:25 PM PDT 24 3846140750 ps
T778 /workspace/coverage/default/72.chip_sw_all_escalation_resets.3757013922 Aug 18 07:20:12 PM PDT 24 Aug 18 07:31:01 PM PDT 24 4972216540 ps
T977 /workspace/coverage/default/2.chip_tap_straps_prod.1504948982 Aug 18 07:10:01 PM PDT 24 Aug 18 07:22:56 PM PDT 24 6275704707 ps
T747 /workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.3803080871 Aug 18 07:15:50 PM PDT 24 Aug 18 07:22:59 PM PDT 24 4544883096 ps
T978 /workspace/coverage/default/1.rom_e2e_asm_init_rma.2733296317 Aug 18 07:05:34 PM PDT 24 Aug 18 08:19:17 PM PDT 24 14146523185 ps
T979 /workspace/coverage/default/2.chip_sw_hmac_smoketest.2111155390 Aug 18 07:12:25 PM PDT 24 Aug 18 07:19:09 PM PDT 24 3063904830 ps
T980 /workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.1236694120 Aug 18 07:02:38 PM PDT 24 Aug 18 07:06:59 PM PDT 24 3123385254 ps
T981 /workspace/coverage/default/1.chip_sw_entropy_src_smoketest.2386854352 Aug 18 07:00:31 PM PDT 24 Aug 18 07:08:45 PM PDT 24 3586390800 ps
T166 /workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.1129391316 Aug 18 06:53:30 PM PDT 24 Aug 18 06:55:35 PM PDT 24 2261865367 ps
T190 /workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.3907329544 Aug 18 07:09:45 PM PDT 24 Aug 18 07:19:06 PM PDT 24 5017063550 ps
T86 /workspace/coverage/default/2.chip_sw_alert_handler_entropy.2485322236 Aug 18 07:07:05 PM PDT 24 Aug 18 07:12:41 PM PDT 24 3392204737 ps
T239 /workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.3546473877 Aug 18 06:53:44 PM PDT 24 Aug 18 08:37:17 PM PDT 24 48450096588 ps
T982 /workspace/coverage/default/1.chip_sw_aes_entropy.3269839074 Aug 18 07:01:11 PM PDT 24 Aug 18 07:05:10 PM PDT 24 2702286024 ps
T983 /workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.3090246178 Aug 18 07:05:02 PM PDT 24 Aug 18 07:09:10 PM PDT 24 2366597950 ps
T690 /workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.4093191197 Aug 18 06:58:06 PM PDT 24 Aug 18 07:08:32 PM PDT 24 6226949384 ps
T984 /workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.3516123870 Aug 18 07:05:14 PM PDT 24 Aug 18 07:19:11 PM PDT 24 9918591440 ps
T985 /workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.3845684016 Aug 18 07:08:23 PM PDT 24 Aug 18 07:12:40 PM PDT 24 2753029082 ps
T115 /workspace/coverage/default/2.chip_sw_ast_clk_rst_inputs.3679246018 Aug 18 07:12:58 PM PDT 24 Aug 18 07:49:33 PM PDT 24 17234458816 ps
T986 /workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.87503175 Aug 18 07:12:49 PM PDT 24 Aug 18 07:20:42 PM PDT 24 6865883096 ps
T439 /workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.2290817848 Aug 18 06:56:53 PM PDT 24 Aug 18 07:16:45 PM PDT 24 6662722551 ps
T987 /workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.2802291059 Aug 18 07:00:22 PM PDT 24 Aug 18 07:06:42 PM PDT 24 4521312952 ps
T780 /workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.1809247873 Aug 18 07:17:37 PM PDT 24 Aug 18 07:24:18 PM PDT 24 4333292968 ps
T988 /workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.26986634 Aug 18 07:14:25 PM PDT 24 Aug 18 07:20:34 PM PDT 24 5141224120 ps
T191 /workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.3914692335 Aug 18 07:00:01 PM PDT 24 Aug 18 07:05:58 PM PDT 24 3517822768 ps
T183 /workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.2595829520 Aug 18 06:59:32 PM PDT 24 Aug 18 07:03:33 PM PDT 24 3020127784 ps
T353 /workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.3428120088 Aug 18 06:51:58 PM PDT 24 Aug 18 06:57:30 PM PDT 24 3770481800 ps
T172 /workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.2012344504 Aug 18 06:54:29 PM PDT 24 Aug 18 07:02:12 PM PDT 24 5207202260 ps
T64 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.2594477668 Aug 18 06:54:23 PM PDT 24 Aug 18 07:16:55 PM PDT 24 21250212680 ps
T989 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1926964043 Aug 18 06:55:14 PM PDT 24 Aug 18 07:02:52 PM PDT 24 7259820424 ps
T40 /workspace/coverage/default/0.chip_sw_spi_device_tpm.1566163198 Aug 18 06:53:33 PM PDT 24 Aug 18 07:00:28 PM PDT 24 3745341975 ps
T269 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.2922342459 Aug 18 06:55:54 PM PDT 24 Aug 18 07:17:34 PM PDT 24 10729186142 ps
T748 /workspace/coverage/default/56.chip_sw_all_escalation_resets.2999720559 Aug 18 07:21:56 PM PDT 24 Aug 18 07:34:00 PM PDT 24 4513176830 ps
T402 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.805322511 Aug 18 07:00:36 PM PDT 24 Aug 18 08:43:12 PM PDT 24 24470356824 ps
T990 /workspace/coverage/default/1.chip_sw_example_manufacturer.1962928909 Aug 18 06:57:29 PM PDT 24 Aug 18 07:02:37 PM PDT 24 2232174480 ps
T378 /workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.1244011122 Aug 18 07:04:27 PM PDT 24 Aug 18 07:23:00 PM PDT 24 8930315581 ps
T991 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.468692643 Aug 18 07:00:41 PM PDT 24 Aug 18 07:50:39 PM PDT 24 11721895200 ps
T992 /workspace/coverage/default/1.chip_sw_lc_ctrl_transition.3420094365 Aug 18 06:59:11 PM PDT 24 Aug 18 07:10:34 PM PDT 24 10506293420 ps
T993 /workspace/coverage/default/1.rom_e2e_static_critical.429252439 Aug 18 07:03:08 PM PDT 24 Aug 18 08:14:57 PM PDT 24 16879243040 ps
T236 /workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.55709246 Aug 18 07:09:14 PM PDT 24 Aug 18 08:37:17 PM PDT 24 16664105750 ps
T87 /workspace/coverage/default/0.chip_sw_usbdev_vbus.2716173920 Aug 18 06:52:57 PM PDT 24 Aug 18 06:58:07 PM PDT 24 2367662536 ps
T270 /workspace/coverage/default/35.chip_sw_all_escalation_resets.1991548682 Aug 18 07:16:05 PM PDT 24 Aug 18 07:27:40 PM PDT 24 5184822888 ps
T994 /workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.4032003120 Aug 18 06:57:45 PM PDT 24 Aug 18 07:07:40 PM PDT 24 5168880530 ps
T149 /workspace/coverage/default/0.chip_sw_sensor_ctrl_status.3251002761 Aug 18 07:01:22 PM PDT 24 Aug 18 07:04:48 PM PDT 24 2423697016 ps
T306 /workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.2467767567 Aug 18 06:58:46 PM PDT 24 Aug 18 07:03:24 PM PDT 24 3631200051 ps
T691 /workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.2312717202 Aug 18 07:11:25 PM PDT 24 Aug 18 07:20:20 PM PDT 24 4312280065 ps
T157 /workspace/coverage/default/0.rom_raw_unlock.3322118908 Aug 18 06:58:06 PM PDT 24 Aug 18 07:02:16 PM PDT 24 6006235472 ps
T798 /workspace/coverage/default/9.chip_sw_all_escalation_resets.1202117767 Aug 18 07:14:01 PM PDT 24 Aug 18 07:23:50 PM PDT 24 4507433092 ps
T257 /workspace/coverage/default/0.chip_sw_plic_sw_irq.1093696300 Aug 18 06:58:43 PM PDT 24 Aug 18 07:03:39 PM PDT 24 2488962754 ps
T403 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.3284521012 Aug 18 07:00:30 PM PDT 24 Aug 18 08:30:59 PM PDT 24 24729724406 ps
T995 /workspace/coverage/default/2.rom_e2e_smoke.1732407750 Aug 18 07:15:50 PM PDT 24 Aug 18 08:16:09 PM PDT 24 14758001096 ps
T288 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.2345730146 Aug 18 07:08:58 PM PDT 24 Aug 18 07:18:23 PM PDT 24 4588355546 ps
T996 /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.3262404586 Aug 18 06:58:36 PM PDT 24 Aug 18 08:15:13 PM PDT 24 20988928786 ps
T997 /workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.1473667666 Aug 18 07:12:58 PM PDT 24 Aug 18 07:21:27 PM PDT 24 6538052198 ps
T37 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3491789541 Aug 18 06:56:55 PM PDT 24 Aug 18 07:05:40 PM PDT 24 6429087920 ps
T316 /workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.1769311302 Aug 18 07:00:03 PM PDT 24 Aug 18 07:14:02 PM PDT 24 9264794607 ps
T822 /workspace/coverage/default/79.chip_sw_all_escalation_resets.935643586 Aug 18 07:20:20 PM PDT 24 Aug 18 07:32:44 PM PDT 24 5281153560 ps
T998 /workspace/coverage/default/2.chip_sw_aon_timer_irq.1321529502 Aug 18 07:05:45 PM PDT 24 Aug 18 07:12:38 PM PDT 24 3946481470 ps
T784 /workspace/coverage/default/1.chip_sw_all_escalation_resets.250677321 Aug 18 06:56:18 PM PDT 24 Aug 18 07:06:19 PM PDT 24 5768365376 ps
T999 /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.388250587 Aug 18 07:01:14 PM PDT 24 Aug 18 07:05:41 PM PDT 24 2736708720 ps
T1000 /workspace/coverage/default/0.chip_sw_uart_smoketest.3861745558 Aug 18 06:55:23 PM PDT 24 Aug 18 06:59:53 PM PDT 24 3294416044 ps
T65 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3524029375 Aug 18 07:10:58 PM PDT 24 Aug 18 07:32:47 PM PDT 24 22591770280 ps
T699 /workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.1371152636 Aug 18 06:56:38 PM PDT 24 Aug 18 07:11:28 PM PDT 24 5164062976 ps
T1001 /workspace/coverage/default/14.chip_sw_uart_rand_baudrate.574081875 Aug 18 07:15:06 PM PDT 24 Aug 18 07:24:27 PM PDT 24 3792501400 ps
T1002 /workspace/coverage/default/1.rom_e2e_asm_init_prod.3300218794 Aug 18 07:00:04 PM PDT 24 Aug 18 08:07:15 PM PDT 24 15558814115 ps
T1003 /workspace/coverage/default/2.chip_sw_power_idle_load.344014027 Aug 18 07:11:49 PM PDT 24 Aug 18 07:25:11 PM PDT 24 4857476276 ps
T1004 /workspace/coverage/default/0.chip_sw_rv_dm_access_after_wakeup.956566993 Aug 18 06:56:55 PM PDT 24 Aug 18 07:04:58 PM PDT 24 6197550520 ps
T1005 /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.1341268002 Aug 18 06:54:58 PM PDT 24 Aug 18 07:16:00 PM PDT 24 5972310307 ps
T1006 /workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.2458768504 Aug 18 07:02:29 PM PDT 24 Aug 18 07:20:49 PM PDT 24 5214516992 ps
T1007 /workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.2389461428 Aug 18 06:54:01 PM PDT 24 Aug 18 07:01:40 PM PDT 24 4478395000 ps
T1008 /workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.383079624 Aug 18 07:13:20 PM PDT 24 Aug 18 08:51:47 PM PDT 24 23907198160 ps
T90 /workspace/coverage/default/59.chip_sw_all_escalation_resets.1639749272 Aug 18 07:21:03 PM PDT 24 Aug 18 07:34:22 PM PDT 24 5840510752 ps
T93 /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3458589782 Aug 18 07:10:54 PM PDT 24 Aug 18 07:32:03 PM PDT 24 7990488362 ps
T94 /workspace/coverage/default/60.chip_sw_all_escalation_resets.75379669 Aug 18 07:19:05 PM PDT 24 Aug 18 07:28:10 PM PDT 24 5889345184 ps
T95 /workspace/coverage/default/3.chip_sw_all_escalation_resets.188701106 Aug 18 07:11:52 PM PDT 24 Aug 18 07:21:03 PM PDT 24 4850727174 ps
T96 /workspace/coverage/default/80.chip_sw_all_escalation_resets.1303308089 Aug 18 07:20:49 PM PDT 24 Aug 18 07:31:09 PM PDT 24 5698087550 ps
T97 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.385554838 Aug 18 06:59:49 PM PDT 24 Aug 18 08:14:49 PM PDT 24 24809515274 ps
T98 /workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.2609610866 Aug 18 07:08:53 PM PDT 24 Aug 18 07:42:33 PM PDT 24 11114932016 ps
T99 /workspace/coverage/default/54.chip_sw_all_escalation_resets.3417868211 Aug 18 07:20:14 PM PDT 24 Aug 18 07:32:51 PM PDT 24 4194240912 ps
T100 /workspace/coverage/default/0.chip_plic_all_irqs_0.2149295502 Aug 18 06:57:39 PM PDT 24 Aug 18 07:16:44 PM PDT 24 5941197808 ps
T101 /workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.1370794140 Aug 18 06:52:44 PM PDT 24 Aug 18 07:04:28 PM PDT 24 7277893000 ps
T363 /workspace/coverage/default/1.chip_sival_flash_info_access.1691324870 Aug 18 06:56:43 PM PDT 24 Aug 18 07:02:37 PM PDT 24 3472814532 ps
T1009 /workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.488032617 Aug 18 06:51:32 PM PDT 24 Aug 18 06:57:57 PM PDT 24 6781693460 ps
T416 /workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.1428896083 Aug 18 06:52:27 PM PDT 24 Aug 18 06:57:05 PM PDT 24 3000534142 ps
T1010 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.3952363607 Aug 18 07:05:53 PM PDT 24 Aug 18 07:14:45 PM PDT 24 6727096812 ps
T1011 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.1132897138 Aug 18 06:52:25 PM PDT 24 Aug 18 06:59:40 PM PDT 24 6923591690 ps
T1012 /workspace/coverage/default/2.chip_sw_aes_enc.3973330866 Aug 18 07:06:16 PM PDT 24 Aug 18 07:12:27 PM PDT 24 3701810024 ps
T265 /workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.831475140 Aug 18 06:56:03 PM PDT 24 Aug 18 07:06:53 PM PDT 24 4897261836 ps
T768 /workspace/coverage/default/15.chip_sw_all_escalation_resets.407239860 Aug 18 07:14:53 PM PDT 24 Aug 18 07:26:06 PM PDT 24 5278448748 ps
T694 /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.989928731 Aug 18 06:54:31 PM PDT 24 Aug 18 06:56:29 PM PDT 24 1991638524 ps
T360 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops.2152725464 Aug 18 06:54:32 PM PDT 24 Aug 18 07:05:18 PM PDT 24 3680600254 ps
T337 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.920284716 Aug 18 07:00:16 PM PDT 24 Aug 18 07:17:04 PM PDT 24 5168501024 ps
T289 /workspace/coverage/default/2.chip_sw_otbn_mem_scramble.3850490700 Aug 18 07:06:42 PM PDT 24 Aug 18 07:16:26 PM PDT 24 3902542780 ps
T440 /workspace/coverage/default/0.chip_sw_edn_entropy_reqs.2277591963 Aug 18 06:52:20 PM PDT 24 Aug 18 07:07:56 PM PDT 24 6233380602 ps
T1013 /workspace/coverage/default/4.chip_sw_uart_rand_baudrate.2199056073 Aug 18 07:14:18 PM PDT 24 Aug 18 07:40:01 PM PDT 24 8288144576 ps
T1014 /workspace/coverage/default/1.chip_sw_aes_idle.2436454560 Aug 18 06:56:07 PM PDT 24 Aug 18 07:01:08 PM PDT 24 3170069740 ps
T1015 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.2027394091 Aug 18 07:00:33 PM PDT 24 Aug 18 07:05:03 PM PDT 24 2468759607 ps
T826 /workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.1862922357 Aug 18 07:20:04 PM PDT 24 Aug 18 07:27:07 PM PDT 24 3524225318 ps
T1016 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.2046979573 Aug 18 06:57:52 PM PDT 24 Aug 18 07:09:24 PM PDT 24 4333388182 ps
T381 /workspace/coverage/default/0.chip_sw_hmac_enc.2443317418 Aug 18 06:57:02 PM PDT 24 Aug 18 07:01:31 PM PDT 24 3375173032 ps
T53 /workspace/coverage/default/0.chip_sw_alert_test.3884291927 Aug 18 06:57:40 PM PDT 24 Aug 18 07:03:44 PM PDT 24 3385351888 ps
T1017 /workspace/coverage/default/1.chip_sw_power_idle_load.3716329151 Aug 18 06:57:08 PM PDT 24 Aug 18 07:07:41 PM PDT 24 4107299168 ps
T1018 /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.294077350 Aug 18 06:57:38 PM PDT 24 Aug 18 08:02:29 PM PDT 24 16149523504 ps
T237 /workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.3197342109 Aug 18 06:56:05 PM PDT 24 Aug 18 08:02:58 PM PDT 24 14714475928 ps
T1019 /workspace/coverage/default/1.chip_sw_kmac_entropy.322093625 Aug 18 07:00:37 PM PDT 24 Aug 18 07:04:21 PM PDT 24 2635560712 ps
T1020 /workspace/coverage/default/2.chip_sw_clkmgr_jitter.2510920031 Aug 18 07:09:37 PM PDT 24 Aug 18 07:13:43 PM PDT 24 2716635279 ps
T1021 /workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.3885629289 Aug 18 07:02:35 PM PDT 24 Aug 18 07:27:41 PM PDT 24 9853459482 ps
T1022 /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.862256115 Aug 18 06:55:53 PM PDT 24 Aug 18 06:59:25 PM PDT 24 3467204149 ps
T1023 /workspace/coverage/default/4.chip_tap_straps_dev.1179989880 Aug 18 07:12:51 PM PDT 24 Aug 18 07:33:04 PM PDT 24 11652701534 ps
T1024 /workspace/coverage/default/7.chip_sw_lc_ctrl_transition.2943846766 Aug 18 07:15:36 PM PDT 24 Aug 18 07:23:06 PM PDT 24 4656493337 ps
T727 /workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.2028827956 Aug 18 06:58:54 PM PDT 24 Aug 18 07:12:51 PM PDT 24 4821192200 ps
T1025 /workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.399310437 Aug 18 06:58:22 PM PDT 24 Aug 18 07:13:12 PM PDT 24 5663647576 ps
T1026 /workspace/coverage/default/0.chip_sw_otp_ctrl_dai_lock.3958887586 Aug 18 06:54:54 PM PDT 24 Aug 18 08:22:58 PM PDT 24 27382679348 ps
T1027 /workspace/coverage/default/2.chip_sw_kmac_mode_cshake.566603080 Aug 18 07:09:21 PM PDT 24 Aug 18 07:13:44 PM PDT 24 2318515844 ps
T1028 /workspace/coverage/default/1.chip_sw_rv_plic_smoketest.1311728223 Aug 18 07:00:30 PM PDT 24 Aug 18 07:03:37 PM PDT 24 2446309428 ps
T1029 /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.1873669976 Aug 18 07:11:49 PM PDT 24 Aug 18 08:11:56 PM PDT 24 24728370811 ps
T344 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.2241884085 Aug 18 06:53:55 PM PDT 24 Aug 18 07:10:09 PM PDT 24 5539718656 ps
T258 /workspace/coverage/default/1.chip_sw_power_sleep_load.1453986162 Aug 18 06:59:11 PM PDT 24 Aug 18 07:04:50 PM PDT 24 4023292124 ps
T1030 /workspace/coverage/default/0.rom_e2e_shutdown_output.3612795263 Aug 18 07:00:54 PM PDT 24 Aug 18 08:00:50 PM PDT 24 27229768600 ps
T1031 /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1593949412 Aug 18 06:54:41 PM PDT 24 Aug 18 07:25:20 PM PDT 24 13398799615 ps
T1032 /workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.1217450608 Aug 18 06:55:14 PM PDT 24 Aug 18 07:02:16 PM PDT 24 3435475634 ps
T1033 /workspace/coverage/default/2.chip_sw_example_manufacturer.895875041 Aug 18 07:01:30 PM PDT 24 Aug 18 07:04:41 PM PDT 24 2730719700 ps
T1034 /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.1308615255 Aug 18 07:13:58 PM PDT 24 Aug 18 07:27:39 PM PDT 24 8738795326 ps
T1035 /workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.4234990892 Aug 18 06:58:27 PM PDT 24 Aug 18 10:35:27 PM PDT 24 254602303368 ps
T77 /workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.2209996205 Aug 18 06:56:16 PM PDT 24 Aug 18 07:03:19 PM PDT 24 3161609198 ps
T414 /workspace/coverage/default/85.chip_sw_all_escalation_resets.3723788962 Aug 18 07:20:08 PM PDT 24 Aug 18 07:30:45 PM PDT 24 5697041354 ps
T761 /workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.3047839184 Aug 18 07:13:14 PM PDT 24 Aug 18 07:20:04 PM PDT 24 4292330736 ps
T266 /workspace/coverage/default/0.rom_e2e_jtag_debug_dev.156908260 Aug 18 06:59:47 PM PDT 24 Aug 18 07:35:21 PM PDT 24 10768319803 ps
T1036 /workspace/coverage/default/0.chip_sw_flash_crash_alert.939675916 Aug 18 06:58:46 PM PDT 24 Aug 18 07:11:49 PM PDT 24 6108174456 ps
T1037 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.18727624 Aug 18 06:58:03 PM PDT 24 Aug 18 07:29:51 PM PDT 24 8653132472 ps
T1038 /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.51247541 Aug 18 06:58:37 PM PDT 24 Aug 18 07:02:30 PM PDT 24 2332319086 ps
T1039 /workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.4212418414 Aug 18 06:49:21 PM PDT 24 Aug 18 07:20:54 PM PDT 24 12000465400 ps
T1040 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.1816062176 Aug 18 06:54:16 PM PDT 24 Aug 18 07:20:08 PM PDT 24 8432371550 ps
T773 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.2673763034 Aug 18 07:07:58 PM PDT 24 Aug 18 07:13:42 PM PDT 24 3349433304 ps
T1041 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.2987014504 Aug 18 07:00:46 PM PDT 24 Aug 18 07:12:35 PM PDT 24 4300262104 ps
T348 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.1582481595 Aug 18 06:54:47 PM PDT 24 Aug 18 07:06:44 PM PDT 24 4184718724 ps
T1042 /workspace/coverage/default/1.chip_sw_clkmgr_jitter.3012503712 Aug 18 07:01:17 PM PDT 24 Aug 18 07:04:52 PM PDT 24 2910117634 ps
T1043 /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.3749466719 Aug 18 06:55:30 PM PDT 24 Aug 18 07:06:50 PM PDT 24 7728980320 ps
T1044 /workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.3650319378 Aug 18 06:53:05 PM PDT 24 Aug 18 07:00:16 PM PDT 24 6067801300 ps
T1045 /workspace/coverage/default/0.chip_sw_otbn_randomness.1246299982 Aug 18 06:57:16 PM PDT 24 Aug 18 07:14:47 PM PDT 24 6567877674 ps
T164 /workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.3185214598 Aug 18 07:03:37 PM PDT 24 Aug 18 07:07:49 PM PDT 24 2226853539 ps
T114 /workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.1825391025 Aug 18 06:56:01 PM PDT 24 Aug 18 07:00:28 PM PDT 24 4158393416 ps
T1046 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.657158617 Aug 18 06:58:53 PM PDT 24 Aug 18 07:30:17 PM PDT 24 18115185250 ps
T285 /workspace/coverage/default/1.chip_sw_data_integrity_escalation.425306173 Aug 18 06:57:57 PM PDT 24 Aug 18 07:14:35 PM PDT 24 5802603000 ps
T1047 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.555564705 Aug 18 06:59:58 PM PDT 24 Aug 18 08:50:10 PM PDT 24 23152392450 ps
T1048 /workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.3498016231 Aug 18 06:56:45 PM PDT 24 Aug 18 07:02:13 PM PDT 24 3450085528 ps
T1049 /workspace/coverage/default/0.chip_sw_entropy_src_smoketest.3571741566 Aug 18 06:53:49 PM PDT 24 Aug 18 07:03:16 PM PDT 24 3503308784 ps
T1050 /workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.2793021054 Aug 18 07:08:28 PM PDT 24 Aug 18 07:19:33 PM PDT 24 9444698137 ps
T736 /workspace/coverage/default/10.chip_sw_all_escalation_resets.1734970996 Aug 18 07:14:49 PM PDT 24 Aug 18 07:26:09 PM PDT 24 5728638684 ps
T1051 /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.1389972002 Aug 18 07:18:10 PM PDT 24 Aug 18 08:11:35 PM PDT 24 14841735360 ps
T1052 /workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.3558148528 Aug 18 06:59:51 PM PDT 24 Aug 18 07:05:39 PM PDT 24 3963299140 ps
T75 /workspace/coverage/default/3.chip_tap_straps_testunlock0.2653054465 Aug 18 07:11:17 PM PDT 24 Aug 18 07:17:25 PM PDT 24 4015476073 ps
T1053 /workspace/coverage/default/2.chip_sw_flash_ctrl_access.2489301621 Aug 18 07:02:31 PM PDT 24 Aug 18 07:21:13 PM PDT 24 5736316450 ps
T1054 /workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.3939130972 Aug 18 06:55:01 PM PDT 24 Aug 18 07:03:52 PM PDT 24 4531649528 ps
T753 /workspace/coverage/default/84.chip_sw_all_escalation_resets.3453285218 Aug 18 07:20:40 PM PDT 24 Aug 18 07:32:20 PM PDT 24 5450427090 ps
T1055 /workspace/coverage/default/0.chip_sw_flash_ctrl_write_clear.588548792 Aug 18 06:59:13 PM PDT 24 Aug 18 07:04:16 PM PDT 24 2684722120 ps
T837 /workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.1016767204 Aug 18 07:20:05 PM PDT 24 Aug 18 07:26:05 PM PDT 24 3810007052 ps
T1056 /workspace/coverage/default/1.chip_sw_kmac_app_rom.3827721169 Aug 18 06:58:53 PM PDT 24 Aug 18 07:02:22 PM PDT 24 2753857192 ps
T307 /workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.1429466879 Aug 18 06:56:36 PM PDT 24 Aug 18 07:02:45 PM PDT 24 2699289144 ps
T357 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.1501809161 Aug 18 06:54:31 PM PDT 24 Aug 18 07:07:38 PM PDT 24 3928747632 ps
T1057 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.2361160229 Aug 18 07:02:37 PM PDT 24 Aug 18 08:45:58 PM PDT 24 23129704500 ps
T776 /workspace/coverage/default/44.chip_sw_all_escalation_resets.621565894 Aug 18 07:17:25 PM PDT 24 Aug 18 07:29:38 PM PDT 24 4729825128 ps
T754 /workspace/coverage/default/74.chip_sw_all_escalation_resets.910802774 Aug 18 07:20:16 PM PDT 24 Aug 18 07:34:18 PM PDT 24 6332390370 ps
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