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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.17 95.54 94.10 95.34 94.92 97.53 99.58


Total test records in report: 2934
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T733 /workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.3955786363 Aug 18 07:18:39 PM PDT 24 Aug 18 07:24:57 PM PDT 24 3300056600 ps
T762 /workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.1752639111 Aug 18 07:19:28 PM PDT 24 Aug 18 07:26:48 PM PDT 24 3589717680 ps
T1058 /workspace/coverage/default/1.chip_sw_entropy_src_kat_test.1322640659 Aug 18 06:59:38 PM PDT 24 Aug 18 07:03:24 PM PDT 24 2881948158 ps
T216 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_outputs.707303796 Aug 18 06:56:58 PM PDT 24 Aug 18 07:03:25 PM PDT 24 4067735452 ps
T808 /workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.2127609463 Aug 18 07:21:09 PM PDT 24 Aug 18 07:29:19 PM PDT 24 3877805736 ps
T1059 /workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.3332547134 Aug 18 06:55:02 PM PDT 24 Aug 18 07:02:54 PM PDT 24 4714450160 ps
T1060 /workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.1643193708 Aug 18 06:56:13 PM PDT 24 Aug 18 07:10:17 PM PDT 24 10049018866 ps
T1061 /workspace/coverage/default/4.chip_sw_uart_tx_rx.2580335039 Aug 18 07:16:44 PM PDT 24 Aug 18 07:25:48 PM PDT 24 4427876728 ps
T1062 /workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.912697731 Aug 18 07:05:08 PM PDT 24 Aug 18 07:26:21 PM PDT 24 8793361512 ps
T802 /workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.3461458758 Aug 18 07:21:07 PM PDT 24 Aug 18 07:28:02 PM PDT 24 3154710160 ps
T1063 /workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.2965316052 Aug 18 06:56:56 PM PDT 24 Aug 18 07:00:48 PM PDT 24 2588881579 ps
T1064 /workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.3487032244 Aug 18 06:53:29 PM PDT 24 Aug 18 07:02:53 PM PDT 24 4540988920 ps
T1065 /workspace/coverage/default/1.chip_sw_csrng_kat_test.221255194 Aug 18 06:58:56 PM PDT 24 Aug 18 07:03:33 PM PDT 24 3259698968 ps
T358 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2534415147 Aug 18 07:17:27 PM PDT 24 Aug 18 07:29:27 PM PDT 24 4381294969 ps
T1066 /workspace/coverage/default/0.chip_sw_coremark.1184382428 Aug 18 06:55:43 PM PDT 24 Aug 18 10:44:34 PM PDT 24 70865319320 ps
T203 /workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.3967638329 Aug 18 06:56:56 PM PDT 24 Aug 18 07:05:29 PM PDT 24 4934461060 ps
T1067 /workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.1837860243 Aug 18 07:12:09 PM PDT 24 Aug 18 07:33:25 PM PDT 24 7777248624 ps
T367 /workspace/coverage/default/1.chip_sw_pattgen_ios.3573063485 Aug 18 06:56:35 PM PDT 24 Aug 18 06:59:30 PM PDT 24 2513595062 ps
T117 /workspace/coverage/default/0.chip_sw_ast_clk_rst_inputs.1281537909 Aug 18 06:55:03 PM PDT 24 Aug 18 07:32:28 PM PDT 24 15597734079 ps
T1068 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.3625256377 Aug 18 06:58:16 PM PDT 24 Aug 18 07:10:39 PM PDT 24 4113954100 ps
T1069 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.1724016044 Aug 18 07:07:47 PM PDT 24 Aug 18 07:31:00 PM PDT 24 6686746850 ps
T1070 /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.425071646 Aug 18 07:14:08 PM PDT 24 Aug 18 07:24:40 PM PDT 24 4684780196 ps
T1071 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.1617423943 Aug 18 07:03:10 PM PDT 24 Aug 18 07:54:28 PM PDT 24 11502753800 ps
T1072 /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.373291940 Aug 18 07:11:31 PM PDT 24 Aug 18 08:43:50 PM PDT 24 28763871198 ps
T173 /workspace/coverage/default/1.chip_sw_lc_ctrl_program_error.2358756011 Aug 18 06:57:39 PM PDT 24 Aug 18 07:08:57 PM PDT 24 5840953944 ps
T240 /workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.152097189 Aug 18 06:59:42 PM PDT 24 Aug 18 07:39:57 PM PDT 24 25996929993 ps
T150 /workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.3160357248 Aug 18 06:54:22 PM PDT 24 Aug 18 07:04:32 PM PDT 24 8951955291 ps
T833 /workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.750773242 Aug 18 07:15:47 PM PDT 24 Aug 18 07:23:30 PM PDT 24 4393666374 ps
T1073 /workspace/coverage/default/16.chip_sw_uart_rand_baudrate.4051817832 Aug 18 07:15:57 PM PDT 24 Aug 18 07:25:11 PM PDT 24 3512403248 ps
T1074 /workspace/coverage/default/0.chip_tap_straps_dev.543942280 Aug 18 06:55:11 PM PDT 24 Aug 18 07:22:11 PM PDT 24 13493337827 ps
T217 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.263257801 Aug 18 07:05:44 PM PDT 24 Aug 18 07:17:10 PM PDT 24 4825785451 ps
T213 /workspace/coverage/default/2.chip_sw_inject_scramble_seed.20597317 Aug 18 07:02:36 PM PDT 24 Aug 18 10:19:26 PM PDT 24 65091702490 ps
T799 /workspace/coverage/default/14.chip_sw_all_escalation_resets.3550891018 Aug 18 07:15:28 PM PDT 24 Aug 18 07:28:16 PM PDT 24 5431797612 ps
T820 /workspace/coverage/default/7.chip_sw_all_escalation_resets.75017104 Aug 18 07:14:16 PM PDT 24 Aug 18 07:24:22 PM PDT 24 5063330904 ps
T770 /workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.1720136077 Aug 18 07:14:11 PM PDT 24 Aug 18 07:22:37 PM PDT 24 4079282290 ps
T791 /workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.2352669663 Aug 18 07:16:07 PM PDT 24 Aug 18 07:22:04 PM PDT 24 3323090438 ps
T1075 /workspace/coverage/default/88.chip_sw_all_escalation_resets.2907729522 Aug 18 07:21:07 PM PDT 24 Aug 18 07:31:56 PM PDT 24 5788519420 ps
T1076 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.2537416448 Aug 18 07:08:32 PM PDT 24 Aug 18 07:15:57 PM PDT 24 2868256307 ps
T71 /workspace/coverage/default/2.chip_tap_straps_rma.2167890632 Aug 18 07:09:23 PM PDT 24 Aug 18 07:20:12 PM PDT 24 8712425944 ps
T1077 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.804935625 Aug 18 06:56:20 PM PDT 24 Aug 18 07:20:52 PM PDT 24 6949130104 ps
T812 /workspace/coverage/default/20.chip_sw_all_escalation_resets.3747812415 Aug 18 07:15:42 PM PDT 24 Aug 18 07:30:19 PM PDT 24 5172212300 ps
T1078 /workspace/coverage/default/2.rom_e2e_shutdown_exception_c.4086613392 Aug 18 07:14:14 PM PDT 24 Aug 18 08:02:52 PM PDT 24 14109487056 ps
T1079 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.1741811335 Aug 18 07:14:28 PM PDT 24 Aug 18 07:22:50 PM PDT 24 3923512900 ps
T1080 /workspace/coverage/default/1.chip_sw_rv_timer_smoketest.3311803642 Aug 18 06:59:52 PM PDT 24 Aug 18 07:03:59 PM PDT 24 2667756016 ps
T1081 /workspace/coverage/default/2.chip_sw_sensor_ctrl_status.1290316651 Aug 18 07:08:33 PM PDT 24 Aug 18 07:12:31 PM PDT 24 2687199958 ps
T1082 /workspace/coverage/default/2.rom_e2e_self_hash.4287531989 Aug 18 07:16:41 PM PDT 24 Aug 18 08:54:21 PM PDT 24 25948257086 ps
T1083 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.794132036 Aug 18 07:10:44 PM PDT 24 Aug 18 07:21:09 PM PDT 24 3719291748 ps
T1084 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.2271225417 Aug 18 07:05:10 PM PDT 24 Aug 18 08:07:12 PM PDT 24 14796468134 ps
T821 /workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.2029685248 Aug 18 07:13:54 PM PDT 24 Aug 18 07:21:26 PM PDT 24 4675420166 ps
T1085 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.885061929 Aug 18 06:56:26 PM PDT 24 Aug 18 07:07:34 PM PDT 24 4544329720 ps
T1086 /workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.2184805097 Aug 18 07:12:05 PM PDT 24 Aug 18 07:18:56 PM PDT 24 7060545688 ps
T1087 /workspace/coverage/default/11.chip_sw_lc_ctrl_transition.3080196707 Aug 18 07:13:26 PM PDT 24 Aug 18 07:25:41 PM PDT 24 7430479089 ps
T1088 /workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.3047102341 Aug 18 06:57:53 PM PDT 24 Aug 18 07:01:24 PM PDT 24 3364693640 ps
T1089 /workspace/coverage/default/2.chip_sw_edn_auto_mode.3641198872 Aug 18 07:10:05 PM PDT 24 Aug 18 07:32:22 PM PDT 24 5401508548 ps
T178 /workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.428252971 Aug 18 06:53:38 PM PDT 24 Aug 18 06:56:18 PM PDT 24 4107521242 ps
T1090 /workspace/coverage/default/11.chip_sw_uart_rand_baudrate.666026902 Aug 18 07:14:39 PM PDT 24 Aug 18 07:22:39 PM PDT 24 3850478364 ps
T41 /workspace/coverage/default/2.chip_sw_spi_device_tpm.2497675039 Aug 18 07:02:15 PM PDT 24 Aug 18 07:07:52 PM PDT 24 3300316310 ps
T804 /workspace/coverage/default/30.chip_sw_all_escalation_resets.2594038256 Aug 18 07:16:42 PM PDT 24 Aug 18 07:28:35 PM PDT 24 4898939496 ps
T379 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.12130469 Aug 18 06:59:35 PM PDT 24 Aug 18 07:10:21 PM PDT 24 4720484359 ps
T431 /workspace/coverage/default/0.rom_e2e_jtag_inject_dev.4168589370 Aug 18 06:58:23 PM PDT 24 Aug 18 07:50:47 PM PDT 24 23864494750 ps
T290 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.3565270776 Aug 18 06:59:54 PM PDT 24 Aug 18 07:09:20 PM PDT 24 4844557306 ps
T1091 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2068568674 Aug 18 06:55:34 PM PDT 24 Aug 18 06:59:30 PM PDT 24 3231316592 ps
T1092 /workspace/coverage/default/2.chip_sw_entropy_src_smoketest.2392212874 Aug 18 07:14:03 PM PDT 24 Aug 18 07:23:03 PM PDT 24 3364273260 ps
T1093 /workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.1983232964 Aug 18 07:08:13 PM PDT 24 Aug 18 07:17:19 PM PDT 24 5319495746 ps
T322 /workspace/coverage/default/82.chip_sw_all_escalation_resets.428556658 Aug 18 07:22:43 PM PDT 24 Aug 18 07:32:48 PM PDT 24 4090613094 ps
T324 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.724476864 Aug 18 07:02:01 PM PDT 24 Aug 18 08:04:52 PM PDT 24 14722766096 ps
T325 /workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.597097897 Aug 18 07:16:10 PM PDT 24 Aug 18 07:22:12 PM PDT 24 3711040530 ps
T326 /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.4075608704 Aug 18 07:00:16 PM PDT 24 Aug 18 07:16:12 PM PDT 24 9100361000 ps
T327 /workspace/coverage/default/1.rom_keymgr_functest.3747383152 Aug 18 06:59:46 PM PDT 24 Aug 18 07:08:50 PM PDT 24 5233929692 ps
T57 /workspace/coverage/default/2.chip_jtag_csr_rw.1407131888 Aug 18 07:02:44 PM PDT 24 Aug 18 07:26:18 PM PDT 24 12040607412 ps
T328 /workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.3936229320 Aug 18 07:20:31 PM PDT 24 Aug 18 07:27:10 PM PDT 24 4276109422 ps
T329 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.977347558 Aug 18 06:59:47 PM PDT 24 Aug 18 08:03:52 PM PDT 24 17282946002 ps
T330 /workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.482795883 Aug 18 07:16:43 PM PDT 24 Aug 18 07:24:01 PM PDT 24 4359914204 ps
T331 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.476948332 Aug 18 07:05:30 PM PDT 24 Aug 18 08:05:31 PM PDT 24 20875207395 ps
T420 /workspace/coverage/default/1.chip_sw_hmac_smoketest.1472711976 Aug 18 06:59:26 PM PDT 24 Aug 18 07:06:11 PM PDT 24 3196711800 ps
T421 /workspace/coverage/default/0.chip_sw_all_escalation_resets.1215464126 Aug 18 06:50:53 PM PDT 24 Aug 18 07:03:32 PM PDT 24 5886630628 ps
T333 /workspace/coverage/default/1.chip_plic_all_irqs_20.818976901 Aug 18 07:01:42 PM PDT 24 Aug 18 07:14:12 PM PDT 24 4749437344 ps
T422 /workspace/coverage/default/1.chip_sw_otbn_randomness.3511656523 Aug 18 06:55:51 PM PDT 24 Aug 18 07:12:50 PM PDT 24 5603493588 ps
T423 /workspace/coverage/default/0.chip_sw_clkmgr_smoketest.1318530394 Aug 18 06:58:00 PM PDT 24 Aug 18 07:02:18 PM PDT 24 2883691096 ps
T1094 /workspace/coverage/default/19.chip_sw_uart_rand_baudrate.3654876908 Aug 18 07:15:05 PM PDT 24 Aug 18 07:45:02 PM PDT 24 9018732776 ps
T271 /workspace/coverage/default/83.chip_sw_all_escalation_resets.3902552192 Aug 18 07:19:44 PM PDT 24 Aug 18 07:28:21 PM PDT 24 5773920036 ps
T1095 /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.3238240727 Aug 18 06:53:56 PM PDT 24 Aug 18 06:58:19 PM PDT 24 3658822523 ps
T1096 /workspace/coverage/default/0.chip_sw_gpio_smoketest.485577890 Aug 18 06:57:55 PM PDT 24 Aug 18 07:02:18 PM PDT 24 3521720809 ps
T1097 /workspace/coverage/default/0.rom_e2e_asm_init_dev.2782075515 Aug 18 07:00:39 PM PDT 24 Aug 18 08:15:11 PM PDT 24 15680066780 ps
T291 /workspace/coverage/default/0.chip_sw_data_integrity_escalation.4110965969 Aug 18 06:56:16 PM PDT 24 Aug 18 07:10:29 PM PDT 24 5512895224 ps
T1098 /workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.1752908165 Aug 18 06:54:02 PM PDT 24 Aug 18 07:04:25 PM PDT 24 8269234326 ps
T695 /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1519711022 Aug 18 06:58:21 PM PDT 24 Aug 18 07:00:34 PM PDT 24 2779087212 ps
T787 /workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.138750758 Aug 18 07:17:10 PM PDT 24 Aug 18 07:24:02 PM PDT 24 3435459008 ps
T1099 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.457220933 Aug 18 06:59:15 PM PDT 24 Aug 18 07:50:53 PM PDT 24 10679585490 ps
T1100 /workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.1937711749 Aug 18 07:00:18 PM PDT 24 Aug 18 07:39:48 PM PDT 24 34128898982 ps
T1101 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.1695800716 Aug 18 07:00:17 PM PDT 24 Aug 18 08:53:46 PM PDT 24 23821129162 ps
T404 /workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.1750230310 Aug 18 06:54:13 PM PDT 24 Aug 18 06:56:52 PM PDT 24 2578885882 ps
T1102 /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.2556964291 Aug 18 07:01:29 PM PDT 24 Aug 18 08:04:19 PM PDT 24 15051968360 ps
T818 /workspace/coverage/default/40.chip_sw_all_escalation_resets.4130076770 Aug 18 07:17:26 PM PDT 24 Aug 18 07:28:32 PM PDT 24 5426939800 ps
T1103 /workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.1430619311 Aug 18 07:04:28 PM PDT 24 Aug 18 07:41:31 PM PDT 24 21777741926 ps
T1104 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.385613107 Aug 18 07:03:12 PM PDT 24 Aug 18 08:13:10 PM PDT 24 15142785720 ps
T1105 /workspace/coverage/default/1.chip_sw_example_rom.80015806 Aug 18 06:52:14 PM PDT 24 Aug 18 06:54:34 PM PDT 24 2618723100 ps
T55 /workspace/coverage/default/0.chip_sw_sleep_pin_retention.234024200 Aug 18 06:53:43 PM PDT 24 Aug 18 06:59:56 PM PDT 24 4792305320 ps
T789 /workspace/coverage/default/29.chip_sw_all_escalation_resets.1745809128 Aug 18 07:16:16 PM PDT 24 Aug 18 07:26:18 PM PDT 24 4288166612 ps
T1106 /workspace/coverage/default/3.chip_tap_straps_prod.1327699406 Aug 18 07:13:43 PM PDT 24 Aug 18 07:16:48 PM PDT 24 3328404360 ps
T819 /workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.2685905778 Aug 18 07:18:31 PM PDT 24 Aug 18 07:24:47 PM PDT 24 4205648472 ps
T317 /workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2063811038 Aug 18 06:56:03 PM PDT 24 Aug 18 07:01:22 PM PDT 24 3635836108 ps
T147 /workspace/coverage/default/1.chip_sw_ast_clk_rst_inputs.7991110 Aug 18 06:59:41 PM PDT 24 Aug 18 08:15:04 PM PDT 24 26492059962 ps
T1107 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops.2902549064 Aug 18 07:04:04 PM PDT 24 Aug 18 07:13:11 PM PDT 24 4305534778 ps
T259 /workspace/coverage/default/2.chip_sw_power_sleep_load.2082224484 Aug 18 07:11:48 PM PDT 24 Aug 18 07:19:31 PM PDT 24 4058370488 ps
T1108 /workspace/coverage/default/3.chip_sw_csrng_edn_concurrency.2453576797 Aug 18 07:13:04 PM PDT 24 Aug 18 08:16:17 PM PDT 24 15203895800 ps
T211 /workspace/coverage/default/0.chip_jtag_mem_access.3263428022 Aug 18 06:43:26 PM PDT 24 Aug 18 07:04:53 PM PDT 24 13878190118 ps
T1109 /workspace/coverage/default/0.chip_sw_example_flash.1137691845 Aug 18 06:53:25 PM PDT 24 Aug 18 06:57:13 PM PDT 24 2752095828 ps
T1110 /workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.1269069117 Aug 18 07:00:29 PM PDT 24 Aug 18 07:05:05 PM PDT 24 3300502360 ps
T696 /workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.3862084516 Aug 18 06:51:27 PM PDT 24 Aug 18 06:55:14 PM PDT 24 4294522139 ps
T1111 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.2157938993 Aug 18 06:59:50 PM PDT 24 Aug 18 08:01:31 PM PDT 24 15715145040 ps
T1112 /workspace/coverage/default/2.chip_sw_aes_smoketest.2455171052 Aug 18 07:12:08 PM PDT 24 Aug 18 07:16:27 PM PDT 24 2693145240 ps
T1113 /workspace/coverage/default/0.chip_sw_hmac_oneshot.1248670852 Aug 18 06:53:14 PM PDT 24 Aug 18 06:59:56 PM PDT 24 3477389896 ps
T54 /workspace/coverage/default/1.chip_sw_alert_test.1135488358 Aug 18 07:00:12 PM PDT 24 Aug 18 07:06:13 PM PDT 24 3146945824 ps
T1114 /workspace/coverage/default/0.chip_tap_straps_prod.1893264312 Aug 18 06:53:53 PM PDT 24 Aug 18 07:19:06 PM PDT 24 13869317807 ps
T185 /workspace/coverage/default/2.chip_sw_flash_rma_unlocked.829323211 Aug 18 07:01:50 PM PDT 24 Aug 18 08:16:09 PM PDT 24 44287377693 ps
T803 /workspace/coverage/default/51.chip_sw_all_escalation_resets.2337619044 Aug 18 07:18:23 PM PDT 24 Aug 18 07:33:35 PM PDT 24 6741118592 ps
T1115 /workspace/coverage/default/9.chip_sw_uart_rand_baudrate.329386697 Aug 18 07:14:32 PM PDT 24 Aug 18 07:58:47 PM PDT 24 13234615420 ps
T1116 /workspace/coverage/default/0.chip_sw_rstmgr_sw_req.751408513 Aug 18 06:51:53 PM PDT 24 Aug 18 06:56:48 PM PDT 24 3556224872 ps
T1117 /workspace/coverage/default/1.chip_sw_rv_dm_access_after_wakeup.4134449489 Aug 18 06:55:36 PM PDT 24 Aug 18 07:00:35 PM PDT 24 5970295814 ps
T349 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.3672933433 Aug 18 06:54:49 PM PDT 24 Aug 18 07:07:48 PM PDT 24 4362373288 ps
T1118 /workspace/coverage/default/0.chip_sw_uart_tx_rx.1285946294 Aug 18 06:54:00 PM PDT 24 Aug 18 07:03:23 PM PDT 24 3955777160 ps
T1119 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.1170677896 Aug 18 06:57:49 PM PDT 24 Aug 18 08:13:04 PM PDT 24 15079853776 ps
T1120 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation.2778573588 Aug 18 06:56:12 PM PDT 24 Aug 18 07:39:15 PM PDT 24 11052132828 ps
T1121 /workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.3507925736 Aug 18 06:56:42 PM PDT 24 Aug 18 07:05:21 PM PDT 24 4051304165 ps
T1122 /workspace/coverage/default/1.chip_sw_aes_smoketest.2714997030 Aug 18 06:59:49 PM PDT 24 Aug 18 07:05:30 PM PDT 24 2954136612 ps
T790 /workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.2413754705 Aug 18 07:15:22 PM PDT 24 Aug 18 07:20:57 PM PDT 24 3512967912 ps
T351 /workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.745213156 Aug 18 07:03:55 PM PDT 24 Aug 18 07:12:47 PM PDT 24 3390642432 ps
T774 /workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.2719269241 Aug 18 07:16:19 PM PDT 24 Aug 18 07:22:14 PM PDT 24 3700478418 ps
T286 /workspace/coverage/default/4.chip_sw_data_integrity_escalation.1159852517 Aug 18 07:12:41 PM PDT 24 Aug 18 07:29:15 PM PDT 24 5621374976 ps
T342 /workspace/coverage/default/1.chip_sw_entropy_src_csrng.275485672 Aug 18 06:54:46 PM PDT 24 Aug 18 07:22:19 PM PDT 24 6929393880 ps
T38 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.4065522408 Aug 18 07:01:26 PM PDT 24 Aug 18 07:13:06 PM PDT 24 7001348348 ps
T813 /workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.3337782859 Aug 18 07:14:55 PM PDT 24 Aug 18 07:22:03 PM PDT 24 3313969796 ps
T755 /workspace/coverage/default/34.chip_sw_all_escalation_resets.948695750 Aug 18 07:19:36 PM PDT 24 Aug 18 07:35:25 PM PDT 24 6177123248 ps
T1123 /workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.3744718988 Aug 18 06:55:38 PM PDT 24 Aug 18 07:05:14 PM PDT 24 5603440200 ps
T793 /workspace/coverage/default/37.chip_sw_all_escalation_resets.2484971556 Aug 18 07:17:12 PM PDT 24 Aug 18 07:27:37 PM PDT 24 4708873616 ps
T1124 /workspace/coverage/default/8.chip_sw_uart_rand_baudrate.2329646528 Aug 18 07:17:09 PM PDT 24 Aug 18 07:25:15 PM PDT 24 3979761636 ps
T1125 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.1565669374 Aug 18 07:02:07 PM PDT 24 Aug 18 07:13:22 PM PDT 24 5011335242 ps
T1126 /workspace/coverage/default/0.chip_tap_straps_rma.450272606 Aug 18 06:55:54 PM PDT 24 Aug 18 06:59:46 PM PDT 24 3745049522 ps
T78 /workspace/coverage/default/0.chip_sw_usbdev_pullup.1182753865 Aug 18 06:50:02 PM PDT 24 Aug 18 06:55:58 PM PDT 24 3045782896 ps
T334 /workspace/coverage/default/1.chip_plic_all_irqs_0.501868947 Aug 18 07:02:37 PM PDT 24 Aug 18 07:24:08 PM PDT 24 6675632128 ps
T1127 /workspace/coverage/default/0.chip_sw_example_concurrency.50876965 Aug 18 06:56:48 PM PDT 24 Aug 18 07:02:54 PM PDT 24 2950201932 ps
T1128 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2944859376 Aug 18 07:00:29 PM PDT 24 Aug 18 07:12:01 PM PDT 24 3846610300 ps
T272 /workspace/coverage/default/86.chip_sw_all_escalation_resets.3922280969 Aug 18 07:23:09 PM PDT 24 Aug 18 07:36:12 PM PDT 24 6383395560 ps
T1129 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.46184781 Aug 18 06:52:04 PM PDT 24 Aug 18 07:10:17 PM PDT 24 6852789480 ps
T214 /workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.2502365656 Aug 18 07:05:29 PM PDT 24 Aug 18 11:11:03 PM PDT 24 79108754004 ps
T1130 /workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.2314440000 Aug 18 06:55:27 PM PDT 24 Aug 18 07:09:25 PM PDT 24 7039850974 ps
T1131 /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.3287650238 Aug 18 07:01:25 PM PDT 24 Aug 18 07:13:03 PM PDT 24 6248228592 ps
T1132 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.3110764665 Aug 18 06:55:09 PM PDT 24 Aug 18 07:14:31 PM PDT 24 7237656256 ps
T730 /workspace/coverage/default/13.chip_sw_all_escalation_resets.1451986949 Aug 18 07:15:17 PM PDT 24 Aug 18 07:25:57 PM PDT 24 4328274824 ps
T142 /workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.3599243454 Aug 18 07:12:56 PM PDT 24 Aug 18 07:30:29 PM PDT 24 9704351016 ps
T1133 /workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.2145545117 Aug 18 07:18:17 PM PDT 24 Aug 18 08:19:07 PM PDT 24 11096737100 ps
T56 /workspace/coverage/default/2.chip_sw_sleep_pin_retention.3335177857 Aug 18 06:59:31 PM PDT 24 Aug 18 07:04:14 PM PDT 24 2613970040 ps
T350 /workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.254647252 Aug 18 06:58:45 PM PDT 24 Aug 18 07:12:11 PM PDT 24 4124198740 ps
T102 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3989616717 Aug 18 06:55:43 PM PDT 24 Aug 18 07:28:29 PM PDT 24 26164502846 ps
T1134 /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.4215965277 Aug 18 07:13:02 PM PDT 24 Aug 18 07:43:42 PM PDT 24 9003278187 ps
T785 /workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.3735560735 Aug 18 07:18:59 PM PDT 24 Aug 18 07:27:01 PM PDT 24 3895557610 ps
T1135 /workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.1615267465 Aug 18 07:15:47 PM PDT 24 Aug 18 07:21:28 PM PDT 24 3376446418 ps
T204 /workspace/coverage/default/2.chip_sw_spi_device_pass_through.2798546799 Aug 18 07:03:28 PM PDT 24 Aug 18 07:11:44 PM PDT 24 5206240005 ps
T1136 /workspace/coverage/default/1.chip_sw_flash_init.2088547885 Aug 18 06:56:41 PM PDT 24 Aug 18 07:31:46 PM PDT 24 22523085600 ps
T766 /workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.669851452 Aug 18 07:17:08 PM PDT 24 Aug 18 07:24:51 PM PDT 24 3380727240 ps
T703 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.2382406160 Aug 18 07:05:26 PM PDT 24 Aug 18 07:09:34 PM PDT 24 3537362930 ps
T815 /workspace/coverage/default/98.chip_sw_all_escalation_resets.3372345355 Aug 18 07:21:59 PM PDT 24 Aug 18 07:33:21 PM PDT 24 5930132390 ps
T1137 /workspace/coverage/default/0.rom_keymgr_functest.31897269 Aug 18 06:54:54 PM PDT 24 Aug 18 07:05:52 PM PDT 24 4063544658 ps
T292 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3257430850 Aug 18 07:10:49 PM PDT 24 Aug 18 07:22:32 PM PDT 24 4777591656 ps
T1138 /workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.3805986671 Aug 18 07:00:32 PM PDT 24 Aug 18 07:10:15 PM PDT 24 5747850614 ps
T1139 /workspace/coverage/default/0.rom_e2e_self_hash.1461271282 Aug 18 07:03:05 PM PDT 24 Aug 18 08:49:04 PM PDT 24 25922324216 ps
T293 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.2363321924 Aug 18 07:00:14 PM PDT 24 Aug 18 07:07:57 PM PDT 24 4106691978 ps
T1140 /workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.1093444474 Aug 18 07:07:58 PM PDT 24 Aug 18 07:13:37 PM PDT 24 3498126984 ps
T1141 /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.3658621673 Aug 18 07:01:26 PM PDT 24 Aug 18 07:13:58 PM PDT 24 7227846000 ps
T1142 /workspace/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.1187125810 Aug 18 06:53:07 PM PDT 24 Aug 18 06:57:53 PM PDT 24 2447383612 ps
T1143 /workspace/coverage/default/1.chip_sw_kmac_mode_cshake.3481180959 Aug 18 06:53:12 PM PDT 24 Aug 18 06:56:16 PM PDT 24 2861601304 ps
T1144 /workspace/coverage/default/0.chip_sw_ast_clk_outputs.2916308116 Aug 18 06:54:37 PM PDT 24 Aug 18 07:14:11 PM PDT 24 8181489640 ps
T1145 /workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.4223279151 Aug 18 06:54:00 PM PDT 24 Aug 18 06:59:00 PM PDT 24 3081154235 ps
T1146 /workspace/coverage/default/0.rom_e2e_asm_init_prod_end.2958374934 Aug 18 06:57:31 PM PDT 24 Aug 18 08:02:37 PM PDT 24 15774355703 ps
T273 /workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.1925474398 Aug 18 07:01:19 PM PDT 24 Aug 18 07:14:39 PM PDT 24 6042723974 ps
T1147 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.1385469590 Aug 18 07:09:12 PM PDT 24 Aug 18 07:22:45 PM PDT 24 8739583593 ps
T1148 /workspace/coverage/default/2.rom_e2e_asm_init_rma.1897427358 Aug 18 07:16:14 PM PDT 24 Aug 18 08:22:49 PM PDT 24 14376672666 ps
T1149 /workspace/coverage/default/0.chip_sw_aes_enc.2655518892 Aug 18 06:53:53 PM PDT 24 Aug 18 06:58:33 PM PDT 24 2308938200 ps
T59 /workspace/coverage/default/2.chip_sw_spi_device_pinmux_sleep_retention.2525771641 Aug 18 07:00:09 PM PDT 24 Aug 18 07:04:43 PM PDT 24 3809775828 ps
T797 /workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.2405906180 Aug 18 07:22:50 PM PDT 24 Aug 18 07:30:17 PM PDT 24 4424550576 ps
T1150 /workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.1739584876 Aug 18 07:06:24 PM PDT 24 Aug 18 07:23:54 PM PDT 24 4958164760 ps
T1151 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.345767902 Aug 18 06:56:14 PM PDT 24 Aug 18 07:19:38 PM PDT 24 5990704512 ps
T42 /workspace/coverage/default/1.chip_sw_spi_device_tpm.414137901 Aug 18 06:57:03 PM PDT 24 Aug 18 07:02:02 PM PDT 24 3707154033 ps
T758 /workspace/coverage/default/71.chip_sw_all_escalation_resets.3181860770 Aug 18 07:20:20 PM PDT 24 Aug 18 07:30:09 PM PDT 24 4790950188 ps
T771 /workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.567890072 Aug 18 07:21:13 PM PDT 24 Aug 18 07:27:34 PM PDT 24 4136124668 ps
T218 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.88621222 Aug 18 06:59:05 PM PDT 24 Aug 18 07:32:44 PM PDT 24 23451246034 ps
T238 /workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.3644801711 Aug 18 06:52:38 PM PDT 24 Aug 18 07:55:38 PM PDT 24 18174132024 ps
T1152 /workspace/coverage/default/2.chip_sw_flash_ctrl_write_clear.1456548630 Aug 18 07:09:52 PM PDT 24 Aug 18 07:14:06 PM PDT 24 3590194358 ps
T1153 /workspace/coverage/default/67.chip_sw_all_escalation_resets.2429306155 Aug 18 07:19:17 PM PDT 24 Aug 18 07:31:54 PM PDT 24 4916644916 ps
T385 /workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.4156214654 Aug 18 07:16:22 PM PDT 24 Aug 18 07:24:40 PM PDT 24 3950468800 ps
T777 /workspace/coverage/default/78.chip_sw_all_escalation_resets.1850907307 Aug 18 07:22:35 PM PDT 24 Aug 18 07:31:45 PM PDT 24 5395727390 ps
T35 /workspace/coverage/default/2.chip_sw_spi_host_tx_rx.2246384855 Aug 18 07:01:21 PM PDT 24 Aug 18 07:04:46 PM PDT 24 2063794340 ps
T1154 /workspace/coverage/default/8.chip_sw_all_escalation_resets.1709484062 Aug 18 07:13:25 PM PDT 24 Aug 18 07:25:18 PM PDT 24 5530175040 ps
T1155 /workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.279485354 Aug 18 07:13:20 PM PDT 24 Aug 18 07:42:07 PM PDT 24 20783535156 ps
T1156 /workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.1081846514 Aug 18 07:05:43 PM PDT 24 Aug 18 07:14:02 PM PDT 24 7708656864 ps
T318 /workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1816107616 Aug 18 07:11:19 PM PDT 24 Aug 18 07:18:50 PM PDT 24 3630724656 ps
T380 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops.2938735875 Aug 18 06:57:42 PM PDT 24 Aug 18 07:08:58 PM PDT 24 3956663760 ps
T1157 /workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.62973359 Aug 18 07:06:45 PM PDT 24 Aug 18 07:18:14 PM PDT 24 18289673694 ps
T1158 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.1181621208 Aug 18 07:00:11 PM PDT 24 Aug 18 07:10:56 PM PDT 24 4168298088 ps
T827 /workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.3174787503 Aug 18 07:15:27 PM PDT 24 Aug 18 07:23:09 PM PDT 24 4093948500 ps
T398 /workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.215729650 Aug 18 06:53:04 PM PDT 24 Aug 18 07:00:48 PM PDT 24 5639907288 ps
T781 /workspace/coverage/default/22.chip_sw_all_escalation_resets.2588747483 Aug 18 07:17:09 PM PDT 24 Aug 18 07:28:05 PM PDT 24 5255499636 ps
T1159 /workspace/coverage/default/1.rom_e2e_shutdown_exception_c.1210689438 Aug 18 07:00:21 PM PDT 24 Aug 18 08:02:58 PM PDT 24 14664886156 ps
T775 /workspace/coverage/default/73.chip_sw_all_escalation_resets.3552676468 Aug 18 07:20:26 PM PDT 24 Aug 18 07:31:15 PM PDT 24 5602963336 ps
T1160 /workspace/coverage/default/2.chip_tap_straps_testunlock0.2708708412 Aug 18 07:10:38 PM PDT 24 Aug 18 07:18:55 PM PDT 24 4589854640 ps
T786 /workspace/coverage/default/45.chip_sw_all_escalation_resets.3024054369 Aug 18 07:18:05 PM PDT 24 Aug 18 07:27:41 PM PDT 24 4245439478 ps
T1161 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.1037483622 Aug 18 07:13:16 PM PDT 24 Aug 18 07:26:20 PM PDT 24 4097225850 ps
T1162 /workspace/coverage/default/0.chip_sw_rv_timer_irq.4216619620 Aug 18 06:55:09 PM PDT 24 Aug 18 06:59:31 PM PDT 24 2386119890 ps
T174 /workspace/coverage/default/2.chip_sw_lc_ctrl_program_error.449561380 Aug 18 07:09:49 PM PDT 24 Aug 18 07:21:11 PM PDT 24 3895040040 ps
T1163 /workspace/coverage/default/0.chip_sw_inject_scramble_seed.1148667399 Aug 18 06:51:59 PM PDT 24 Aug 18 10:06:47 PM PDT 24 65415948260 ps
T1164 /workspace/coverage/default/1.chip_sw_otbn_mem_scramble.2227245155 Aug 18 06:53:34 PM PDT 24 Aug 18 07:01:21 PM PDT 24 3910071810 ps
T1165 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.608916765 Aug 18 06:55:02 PM PDT 24 Aug 18 07:13:05 PM PDT 24 12120791618 ps
T1166 /workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.1770765442 Aug 18 07:15:36 PM PDT 24 Aug 18 07:19:55 PM PDT 24 2577468700 ps
T1167 /workspace/coverage/default/0.chip_sw_alert_handler_escalation.3262875496 Aug 18 06:51:48 PM PDT 24 Aug 18 06:58:58 PM PDT 24 4561467800 ps
T1168 /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.2163058641 Aug 18 06:54:41 PM PDT 24 Aug 18 07:42:53 PM PDT 24 13010132089 ps
T1169 /workspace/coverage/default/0.chip_sw_aon_timer_irq.20893390 Aug 18 06:55:12 PM PDT 24 Aug 18 07:03:01 PM PDT 24 3872875652 ps
T1170 /workspace/coverage/default/1.rom_e2e_smoke.3463585220 Aug 18 07:02:06 PM PDT 24 Aug 18 08:06:25 PM PDT 24 14472190076 ps
T1171 /workspace/coverage/default/1.chip_sw_flash_crash_alert.2645800398 Aug 18 06:59:15 PM PDT 24 Aug 18 07:10:43 PM PDT 24 6090076396 ps
T36 /workspace/coverage/default/0.chip_sw_spi_host_tx_rx.3715845500 Aug 18 06:52:30 PM PDT 24 Aug 18 06:57:58 PM PDT 24 2816639444 ps
T1172 /workspace/coverage/default/31.chip_sw_all_escalation_resets.4061261226 Aug 18 07:15:28 PM PDT 24 Aug 18 07:26:16 PM PDT 24 5351736396 ps
T1173 /workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.2447096091 Aug 18 07:01:39 PM PDT 24 Aug 18 07:09:00 PM PDT 24 4175699928 ps
T1174 /workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.1015962617 Aug 18 07:19:36 PM PDT 24 Aug 18 07:27:35 PM PDT 24 3574807796 ps
T1175 /workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.1809479284 Aug 18 07:04:54 PM PDT 24 Aug 18 07:14:37 PM PDT 24 7850951788 ps
T168 /workspace/coverage/default/50.chip_sw_all_escalation_resets.2151732482 Aug 18 07:17:47 PM PDT 24 Aug 18 07:29:16 PM PDT 24 5255034552 ps
T1176 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.2551263997 Aug 18 06:59:44 PM PDT 24 Aug 18 08:06:10 PM PDT 24 14777355496 ps
T1177 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.2945508381 Aug 18 06:56:30 PM PDT 24 Aug 18 07:04:00 PM PDT 24 5096291750 ps
T1178 /workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.3396125618 Aug 18 07:01:10 PM PDT 24 Aug 18 07:05:17 PM PDT 24 3004127204 ps
T205 /workspace/coverage/default/0.chip_sw_power_virus.3076089196 Aug 18 06:59:13 PM PDT 24 Aug 18 07:24:31 PM PDT 24 5562365324 ps
T335 /workspace/coverage/default/2.chip_plic_all_irqs_0.1519043065 Aug 18 07:09:35 PM PDT 24 Aug 18 07:33:53 PM PDT 24 5869568576 ps
T1179 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.301737351 Aug 18 06:53:27 PM PDT 24 Aug 18 07:12:13 PM PDT 24 6944477940 ps
T810 /workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.2933402669 Aug 18 07:21:40 PM PDT 24 Aug 18 07:28:06 PM PDT 24 3511234972 ps
T219 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.3836580346 Aug 18 07:05:27 PM PDT 24 Aug 18 07:34:01 PM PDT 24 24718978510 ps
T1180 /workspace/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.1442543532 Aug 18 07:03:13 PM PDT 24 Aug 18 07:07:21 PM PDT 24 2895848713 ps
T1181 /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.1517420524 Aug 18 07:06:39 PM PDT 24 Aug 18 08:25:02 PM PDT 24 19063816761 ps
T1182 /workspace/coverage/default/0.chip_sw_aes_smoketest.3039431443 Aug 18 06:56:48 PM PDT 24 Aug 18 07:00:52 PM PDT 24 3021276824 ps
T354 /workspace/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.2148554755 Aug 18 07:09:45 PM PDT 24 Aug 18 07:17:35 PM PDT 24 3989194440 ps
T697 /workspace/coverage/default/0.rom_volatile_raw_unlock.391715182 Aug 18 06:57:38 PM PDT 24 Aug 18 06:59:31 PM PDT 24 2498899064 ps
T698 /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.4268164014 Aug 18 07:05:17 PM PDT 24 Aug 18 07:06:52 PM PDT 24 2284991382 ps
T103 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2381591051 Aug 18 07:10:05 PM PDT 24 Aug 18 07:17:39 PM PDT 24 7539140100 ps
T1183 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.3412757085 Aug 18 06:53:54 PM PDT 24 Aug 18 07:04:24 PM PDT 24 3966064660 ps
T1184 /workspace/coverage/default/2.rom_e2e_static_critical.4180689734 Aug 18 07:16:13 PM PDT 24 Aug 18 08:21:12 PM PDT 24 16862067904 ps
T528 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.1463514873 Aug 18 07:00:33 PM PDT 24 Aug 18 07:12:25 PM PDT 24 4762962200 ps
T1185 /workspace/coverage/default/0.chip_sw_kmac_app_rom.3092084033 Aug 18 06:56:35 PM PDT 24 Aug 18 06:59:40 PM PDT 24 2540116934 ps
T1186 /workspace/coverage/default/2.chip_sw_alert_handler_escalation.834001292 Aug 18 07:06:48 PM PDT 24 Aug 18 07:15:05 PM PDT 24 5287160030 ps
T831 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.3960795702 Aug 18 06:58:54 PM PDT 24 Aug 18 07:05:38 PM PDT 24 3597438246 ps
T160 /workspace/coverage/default/1.chip_plic_all_irqs_10.2026793410 Aug 18 06:55:37 PM PDT 24 Aug 18 07:04:44 PM PDT 24 3911660286 ps
T1187 /workspace/coverage/default/2.chip_sw_example_rom.2276080518 Aug 18 07:01:56 PM PDT 24 Aug 18 07:04:08 PM PDT 24 2682159880 ps
T1188 /workspace/coverage/default/17.chip_sw_uart_rand_baudrate.1742708557 Aug 18 07:16:05 PM PDT 24 Aug 18 07:25:33 PM PDT 24 4433719752 ps
T1189 /workspace/coverage/default/13.chip_sw_uart_rand_baudrate.1761180848 Aug 18 07:15:04 PM PDT 24 Aug 18 07:26:21 PM PDT 24 4556648440 ps
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