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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.17 95.54 94.10 95.34 94.92 97.53 99.58


Total test records in report: 2934
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T1190 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.3118598178 Aug 18 06:59:43 PM PDT 24 Aug 18 07:11:30 PM PDT 24 4596993090 ps
T1191 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.91502701 Aug 18 06:54:21 PM PDT 24 Aug 18 07:22:32 PM PDT 24 9476803195 ps
T1192 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.2255052483 Aug 18 06:58:39 PM PDT 24 Aug 18 07:24:07 PM PDT 24 6726135000 ps
T39 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3270584097 Aug 18 07:08:18 PM PDT 24 Aug 18 07:15:50 PM PDT 24 6384085408 ps
T8 /workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.3065995426 Aug 18 06:53:53 PM PDT 24 Aug 18 06:59:18 PM PDT 24 3260804151 ps
T1193 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation.2828944576 Aug 18 06:56:12 PM PDT 24 Aug 18 07:17:17 PM PDT 24 7376253874 ps
T1194 /workspace/coverage/default/0.chip_sw_clkmgr_off_peri.3782123217 Aug 18 06:57:16 PM PDT 24 Aug 18 07:23:50 PM PDT 24 9265951724 ps
T1195 /workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.2097358610 Aug 18 07:01:46 PM PDT 24 Aug 18 07:41:11 PM PDT 24 26786459390 ps
T1196 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.2171460059 Aug 18 06:57:00 PM PDT 24 Aug 18 07:06:28 PM PDT 24 4472934055 ps
T1197 /workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.410082466 Aug 18 06:55:26 PM PDT 24 Aug 18 10:41:23 PM PDT 24 78797725261 ps
T1198 /workspace/coverage/default/52.chip_sw_all_escalation_resets.531294116 Aug 18 07:17:59 PM PDT 24 Aug 18 07:29:12 PM PDT 24 4879387390 ps
T1199 /workspace/coverage/default/10.chip_sw_lc_ctrl_transition.1035857737 Aug 18 07:13:48 PM PDT 24 Aug 18 07:20:25 PM PDT 24 4995593553 ps
T1200 /workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.3535691322 Aug 18 06:53:28 PM PDT 24 Aug 18 06:58:49 PM PDT 24 3798816694 ps
T1201 /workspace/coverage/default/1.chip_sw_alert_handler_entropy.2263852644 Aug 18 06:54:46 PM PDT 24 Aug 18 07:00:10 PM PDT 24 3654096751 ps
T1202 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.1991652841 Aug 18 07:12:06 PM PDT 24 Aug 18 07:48:53 PM PDT 24 13946292200 ps
T165 /workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.3568941839 Aug 18 06:55:21 PM PDT 24 Aug 18 06:56:56 PM PDT 24 1812626056 ps
T829 /workspace/coverage/default/95.chip_sw_all_escalation_resets.2696529673 Aug 18 07:20:46 PM PDT 24 Aug 18 07:35:12 PM PDT 24 5998367148 ps
T1203 /workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.4002094474 Aug 18 06:55:02 PM PDT 24 Aug 18 06:59:27 PM PDT 24 2590750932 ps
T759 /workspace/coverage/default/16.chip_sw_all_escalation_resets.3788805286 Aug 18 07:16:06 PM PDT 24 Aug 18 07:29:32 PM PDT 24 6528771776 ps
T1204 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.1725686263 Aug 18 06:58:07 PM PDT 24 Aug 18 08:03:58 PM PDT 24 14617497162 ps
T731 /workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.930428384 Aug 18 07:22:16 PM PDT 24 Aug 18 07:29:58 PM PDT 24 3516062472 ps
T1205 /workspace/coverage/default/0.chip_sw_hmac_smoketest.1663849529 Aug 18 06:57:25 PM PDT 24 Aug 18 07:03:23 PM PDT 24 3005406008 ps
T1206 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.192474642 Aug 18 06:52:20 PM PDT 24 Aug 18 07:02:11 PM PDT 24 7906158200 ps
T1207 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2714742444 Aug 18 07:08:13 PM PDT 24 Aug 18 07:34:00 PM PDT 24 13269015819 ps
T1208 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.276612940 Aug 18 06:52:44 PM PDT 24 Aug 18 08:04:14 PM PDT 24 18308559778 ps
T1209 /workspace/coverage/default/1.chip_sw_rstmgr_smoketest.2476296848 Aug 18 07:02:14 PM PDT 24 Aug 18 07:04:55 PM PDT 24 2581077448 ps
T811 /workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.3389482275 Aug 18 07:20:21 PM PDT 24 Aug 18 07:30:13 PM PDT 24 3732580296 ps
T1210 /workspace/coverage/default/2.chip_sw_hmac_enc.1199412955 Aug 18 07:07:32 PM PDT 24 Aug 18 07:11:22 PM PDT 24 3127629944 ps
T137 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3092432744 Aug 18 06:54:25 PM PDT 24 Aug 18 07:02:26 PM PDT 24 5425583776 ps
T1211 /workspace/coverage/default/2.chip_sw_aes_idle.3559838948 Aug 18 07:08:01 PM PDT 24 Aug 18 07:12:01 PM PDT 24 2719471600 ps
T1212 /workspace/coverage/default/1.chip_sw_clkmgr_smoketest.121233483 Aug 18 07:00:11 PM PDT 24 Aug 18 07:03:41 PM PDT 24 2510703000 ps
T1213 /workspace/coverage/default/0.chip_sw_clkmgr_jitter.402236340 Aug 18 06:54:35 PM PDT 24 Aug 18 06:58:18 PM PDT 24 3033616003 ps
T1214 /workspace/coverage/default/1.chip_sw_hmac_multistream.104138618 Aug 18 06:53:41 PM PDT 24 Aug 18 07:23:10 PM PDT 24 8639448340 ps
T340 /workspace/coverage/default/1.chip_sw_rstmgr_alert_info.563591396 Aug 18 06:54:35 PM PDT 24 Aug 18 07:19:19 PM PDT 24 8937844048 ps
T1215 /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.4121687734 Aug 18 06:51:43 PM PDT 24 Aug 18 06:55:48 PM PDT 24 2639564907 ps
T1216 /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.2045982360 Aug 18 06:53:54 PM PDT 24 Aug 18 07:43:19 PM PDT 24 13655851774 ps
T757 /workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.2392570779 Aug 18 07:17:58 PM PDT 24 Aug 18 07:26:08 PM PDT 24 4163722108 ps
T1217 /workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.1694556272 Aug 18 06:58:41 PM PDT 24 Aug 18 07:10:27 PM PDT 24 4627365692 ps
T1218 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.2011764161 Aug 18 06:59:49 PM PDT 24 Aug 18 08:28:15 PM PDT 24 18228126440 ps
T91 /workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.2043935392 Aug 18 07:17:30 PM PDT 24 Aug 18 07:25:05 PM PDT 24 3987139270 ps
T1219 /workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.3738928815 Aug 18 06:55:07 PM PDT 24 Aug 18 07:01:44 PM PDT 24 5111838664 ps
T1220 /workspace/coverage/default/0.chip_sw_edn_sw_mode.515090436 Aug 18 06:56:29 PM PDT 24 Aug 18 07:16:52 PM PDT 24 6395573030 ps
T206 /workspace/coverage/default/1.chip_sw_spi_device_pass_through.778853814 Aug 18 06:59:51 PM PDT 24 Aug 18 07:15:19 PM PDT 24 6767626012 ps
T104 /workspace/coverage/default/0.chip_sw_sleep_pin_wake.3202066706 Aug 18 06:54:24 PM PDT 24 Aug 18 06:58:59 PM PDT 24 2806073680 ps
T1221 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2051988183 Aug 18 07:16:00 PM PDT 24 Aug 18 07:27:52 PM PDT 24 5324829840 ps
T1222 /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3793412055 Aug 18 07:13:16 PM PDT 24 Aug 18 07:20:36 PM PDT 24 3696065170 ps
T1223 /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.1028613257 Aug 18 07:12:09 PM PDT 24 Aug 18 07:22:01 PM PDT 24 4439829460 ps
T1224 /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.1349433104 Aug 18 07:01:31 PM PDT 24 Aug 18 08:09:33 PM PDT 24 15478484700 ps
T1225 /workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.2789148216 Aug 18 06:54:43 PM PDT 24 Aug 18 08:20:14 PM PDT 24 46797162688 ps
T1226 /workspace/coverage/default/0.rom_e2e_static_critical.2138112532 Aug 18 07:03:44 PM PDT 24 Aug 18 08:20:16 PM PDT 24 17084936888 ps
T1227 /workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.944749120 Aug 18 06:57:04 PM PDT 24 Aug 18 08:23:06 PM PDT 24 47928037730 ps
T1228 /workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.1800987602 Aug 18 07:17:05 PM PDT 24 Aug 18 07:24:35 PM PDT 24 3769701550 ps
T1229 /workspace/coverage/default/1.chip_sw_aon_timer_irq.2361588184 Aug 18 06:53:03 PM PDT 24 Aug 18 07:00:04 PM PDT 24 4646952652 ps
T832 /workspace/coverage/default/57.chip_sw_all_escalation_resets.2023121046 Aug 18 07:19:12 PM PDT 24 Aug 18 07:28:56 PM PDT 24 5183327036 ps
T1230 /workspace/coverage/default/2.rom_e2e_asm_init_dev.2600406559 Aug 18 07:18:03 PM PDT 24 Aug 18 08:28:09 PM PDT 24 16096837517 ps
T1231 /workspace/coverage/default/3.chip_sw_lc_ctrl_transition.1981968176 Aug 18 07:12:57 PM PDT 24 Aug 18 07:23:25 PM PDT 24 11935898578 ps
T1232 /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3439038280 Aug 18 07:03:30 PM PDT 24 Aug 18 07:05:42 PM PDT 24 3110380798 ps
T1233 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.3648710955 Aug 18 06:51:39 PM PDT 24 Aug 18 07:09:54 PM PDT 24 9443787762 ps
T830 /workspace/coverage/default/36.chip_sw_all_escalation_resets.1562863116 Aug 18 07:15:47 PM PDT 24 Aug 18 07:24:18 PM PDT 24 6122495688 ps
T1234 /workspace/coverage/default/66.chip_sw_all_escalation_resets.1210988545 Aug 18 07:18:07 PM PDT 24 Aug 18 07:30:06 PM PDT 24 5342475820 ps
T1235 /workspace/coverage/default/0.chip_sw_edn_kat.2223669953 Aug 18 06:56:35 PM PDT 24 Aug 18 07:07:40 PM PDT 24 3567604480 ps
T805 /workspace/coverage/default/93.chip_sw_all_escalation_resets.2540419909 Aug 18 07:23:34 PM PDT 24 Aug 18 07:36:08 PM PDT 24 5800917496 ps
T1236 /workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.3392799320 Aug 18 07:15:21 PM PDT 24 Aug 18 07:21:18 PM PDT 24 3272137304 ps
T1237 /workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.916827681 Aug 18 06:53:35 PM PDT 24 Aug 18 07:10:40 PM PDT 24 5478511474 ps
T22 /workspace/coverage/default/0.chip_sw_usbdev_dpi.337143391 Aug 18 06:56:17 PM PDT 24 Aug 18 07:47:33 PM PDT 24 12179771040 ps
T1238 /workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.2505326409 Aug 18 07:07:10 PM PDT 24 Aug 18 07:19:28 PM PDT 24 5751967576 ps
T1239 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.345896622 Aug 18 06:57:41 PM PDT 24 Aug 18 08:00:36 PM PDT 24 13733775635 ps
T732 /workspace/coverage/default/55.chip_sw_all_escalation_resets.2328977627 Aug 18 07:20:28 PM PDT 24 Aug 18 07:28:40 PM PDT 24 4948298330 ps
T1240 /workspace/coverage/default/2.chip_sw_kmac_idle.4240791651 Aug 18 07:08:39 PM PDT 24 Aug 18 07:12:53 PM PDT 24 2966954444 ps
T1241 /workspace/coverage/default/0.chip_sw_kmac_idle.3267606002 Aug 18 06:52:33 PM PDT 24 Aug 18 06:56:33 PM PDT 24 2777843480 ps
T1242 /workspace/coverage/default/3.chip_tap_straps_dev.2692268670 Aug 18 07:11:26 PM PDT 24 Aug 18 07:17:31 PM PDT 24 4527343163 ps
T1243 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2683940829 Aug 18 06:58:34 PM PDT 24 Aug 18 07:20:23 PM PDT 24 9804861851 ps
T734 /workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.2020187488 Aug 18 07:17:35 PM PDT 24 Aug 18 07:24:39 PM PDT 24 3659281802 ps
T1244 /workspace/coverage/default/1.chip_sw_kmac_idle.3654537949 Aug 18 06:58:36 PM PDT 24 Aug 18 07:04:31 PM PDT 24 2883484970 ps
T1245 /workspace/coverage/default/2.chip_sw_clkmgr_off_peri.904612276 Aug 18 07:08:34 PM PDT 24 Aug 18 07:31:19 PM PDT 24 11193220570 ps
T838 /workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.1817900882 Aug 18 07:17:39 PM PDT 24 Aug 18 07:26:28 PM PDT 24 4145214120 ps
T1246 /workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.3044530714 Aug 18 06:57:50 PM PDT 24 Aug 18 07:14:43 PM PDT 24 11310714488 ps
T1247 /workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.4041695288 Aug 18 06:54:18 PM PDT 24 Aug 18 07:05:43 PM PDT 24 19896852290 ps
T1248 /workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.2557261802 Aug 18 06:55:17 PM PDT 24 Aug 18 07:03:01 PM PDT 24 3572826156 ps
T1249 /workspace/coverage/default/1.chip_tap_straps_prod.3539732085 Aug 18 06:55:16 PM PDT 24 Aug 18 06:58:10 PM PDT 24 2828510483 ps
T1250 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.15022449 Aug 18 07:02:11 PM PDT 24 Aug 18 07:52:30 PM PDT 24 11531187176 ps
T823 /workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.4037562954 Aug 18 07:17:51 PM PDT 24 Aug 18 07:25:29 PM PDT 24 3641437096 ps
T1251 /workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.653032403 Aug 18 06:53:48 PM PDT 24 Aug 18 07:17:39 PM PDT 24 10582643660 ps
T1252 /workspace/coverage/default/4.chip_tap_straps_testunlock0.3519578415 Aug 18 07:13:16 PM PDT 24 Aug 18 07:20:25 PM PDT 24 4819748782 ps
T1253 /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2045422613 Aug 18 06:57:45 PM PDT 24 Aug 18 07:19:18 PM PDT 24 7499406759 ps
T1254 /workspace/coverage/default/75.chip_sw_all_escalation_resets.2601780597 Aug 18 07:20:22 PM PDT 24 Aug 18 07:31:13 PM PDT 24 4734951720 ps
T1255 /workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.3013196448 Aug 18 07:19:23 PM PDT 24 Aug 18 07:25:55 PM PDT 24 3707163228 ps
T1256 /workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.2578139840 Aug 18 06:59:58 PM PDT 24 Aug 18 07:05:28 PM PDT 24 5573505308 ps
T1257 /workspace/coverage/default/1.chip_sw_rstmgr_sw_req.4192156017 Aug 18 06:59:31 PM PDT 24 Aug 18 07:05:11 PM PDT 24 3734312172 ps
T816 /workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.750061370 Aug 18 07:18:51 PM PDT 24 Aug 18 07:27:07 PM PDT 24 4195681990 ps
T1258 /workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.669791463 Aug 18 06:55:18 PM PDT 24 Aug 18 07:15:01 PM PDT 24 6920774980 ps
T814 /workspace/coverage/default/53.chip_sw_all_escalation_resets.3676044464 Aug 18 07:18:53 PM PDT 24 Aug 18 07:31:44 PM PDT 24 4707864192 ps
T1259 /workspace/coverage/default/1.chip_sw_edn_auto_mode.3114437468 Aug 18 06:57:24 PM PDT 24 Aug 18 07:27:07 PM PDT 24 6459062852 ps
T1260 /workspace/coverage/default/1.chip_sw_clkmgr_off_peri.791068023 Aug 18 06:59:49 PM PDT 24 Aug 18 07:28:07 PM PDT 24 10717973988 ps
T783 /workspace/coverage/default/43.chip_sw_all_escalation_resets.3952303990 Aug 18 07:17:05 PM PDT 24 Aug 18 07:28:07 PM PDT 24 5317690340 ps
T60 /workspace/coverage/default/1.chip_sw_spi_device_pinmux_sleep_retention.1696663417 Aug 18 06:58:10 PM PDT 24 Aug 18 07:03:32 PM PDT 24 3093685801 ps
T274 /workspace/coverage/default/11.chip_sw_all_escalation_resets.1804692675 Aug 18 07:14:43 PM PDT 24 Aug 18 07:28:50 PM PDT 24 5032830258 ps
T1261 /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2578415217 Aug 18 06:57:17 PM PDT 24 Aug 18 07:17:25 PM PDT 24 7759421937 ps
T245 /workspace/coverage/default/0.chip_sw_flash_init.2442200949 Aug 18 06:55:04 PM PDT 24 Aug 18 07:39:43 PM PDT 24 21791006724 ps
T1262 /workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.447904665 Aug 18 07:16:27 PM PDT 24 Aug 18 07:23:52 PM PDT 24 3914840400 ps
T287 /workspace/coverage/default/5.chip_sw_data_integrity_escalation.3916868607 Aug 18 07:13:02 PM PDT 24 Aug 18 07:26:23 PM PDT 24 5282990324 ps
T1263 /workspace/coverage/default/2.chip_sw_uart_smoketest.2501899333 Aug 18 07:13:40 PM PDT 24 Aug 18 07:17:56 PM PDT 24 2431774970 ps
T23 /workspace/coverage/default/0.chip_sw_usbdev_setuprx.3197394740 Aug 18 06:52:21 PM PDT 24 Aug 18 07:00:27 PM PDT 24 3612316752 ps
T1264 /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.1508234647 Aug 18 07:12:48 PM PDT 24 Aug 18 07:23:16 PM PDT 24 4394034440 ps
T704 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.3011639010 Aug 18 06:54:55 PM PDT 24 Aug 18 07:00:36 PM PDT 24 2783000160 ps
T424 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.3714265531 Aug 18 07:10:43 PM PDT 24 Aug 18 07:28:56 PM PDT 24 20489295224 ps
T706 /workspace/coverage/default/2.chip_sw_plic_sw_irq.523610855 Aug 18 07:09:40 PM PDT 24 Aug 18 07:14:04 PM PDT 24 2856122268 ps
T1265 /workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1869731068 Aug 18 07:01:21 PM PDT 24 Aug 18 07:13:41 PM PDT 24 18448472664 ps
T763 /workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.2941720225 Aug 18 07:20:50 PM PDT 24 Aug 18 07:29:29 PM PDT 24 4387905810 ps
T1266 /workspace/coverage/default/0.chip_sival_flash_info_access.2265125114 Aug 18 06:54:59 PM PDT 24 Aug 18 07:00:29 PM PDT 24 2967345850 ps
T1267 /workspace/coverage/default/2.chip_sw_kmac_entropy.2226095535 Aug 18 07:02:35 PM PDT 24 Aug 18 07:08:07 PM PDT 24 2585220868 ps
T1268 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.4041310615 Aug 18 06:55:49 PM PDT 24 Aug 18 07:06:06 PM PDT 24 4538117336 ps
T1269 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2482057008 Aug 18 07:05:26 PM PDT 24 Aug 18 07:29:23 PM PDT 24 11590803107 ps
T1270 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.3909969688 Aug 18 06:54:02 PM PDT 24 Aug 18 07:05:39 PM PDT 24 4828565356 ps
T1271 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.3940152439 Aug 18 07:13:37 PM PDT 24 Aug 18 07:23:47 PM PDT 24 4085677808 ps
T209 /workspace/coverage/default/2.chip_jtag_mem_access.222143877 Aug 18 07:02:47 PM PDT 24 Aug 18 07:25:30 PM PDT 24 13486877504 ps
T1272 /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.2142894033 Aug 18 07:01:38 PM PDT 24 Aug 18 07:59:17 PM PDT 24 14743955168 ps
T1273 /workspace/coverage/default/1.chip_sw_uart_tx_rx.285951479 Aug 18 06:53:43 PM PDT 24 Aug 18 07:04:12 PM PDT 24 4336730712 ps
T705 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.848162600 Aug 18 06:55:34 PM PDT 24 Aug 18 06:59:44 PM PDT 24 3051212344 ps
T1274 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2080027667 Aug 18 07:03:24 PM PDT 24 Aug 18 07:13:37 PM PDT 24 4663848688 ps
T323 /workspace/coverage/default/27.chip_sw_all_escalation_resets.2910032663 Aug 18 07:18:27 PM PDT 24 Aug 18 07:33:02 PM PDT 24 5654735000 ps
T207 /workspace/coverage/default/2.chip_sw_power_virus.1349918377 Aug 18 07:14:38 PM PDT 24 Aug 18 07:43:16 PM PDT 24 5448738548 ps
T308 /workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.873691563 Aug 18 06:57:34 PM PDT 24 Aug 18 07:02:19 PM PDT 24 3388392820 ps
T26 /workspace/coverage/default/2.chip_sw_gpio.3879338536 Aug 18 07:00:16 PM PDT 24 Aug 18 07:08:53 PM PDT 24 3572869316 ps
T1275 /workspace/coverage/default/2.chip_sw_example_flash.3706788208 Aug 18 06:59:38 PM PDT 24 Aug 18 07:04:28 PM PDT 24 3583529098 ps
T828 /workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.1601124901 Aug 18 07:16:05 PM PDT 24 Aug 18 07:23:03 PM PDT 24 3932007680 ps
T1276 /workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.232530537 Aug 18 07:22:11 PM PDT 24 Aug 18 07:28:00 PM PDT 24 3605061392 ps
T1277 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.2166882542 Aug 18 07:03:00 PM PDT 24 Aug 18 07:25:45 PM PDT 24 8213138256 ps
T1278 /workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.728247264 Aug 18 06:54:36 PM PDT 24 Aug 18 07:03:41 PM PDT 24 4985053590 ps
T1279 /workspace/coverage/default/3.chip_sw_uart_rand_baudrate.3821884207 Aug 18 07:12:54 PM PDT 24 Aug 18 07:22:24 PM PDT 24 4136590140 ps
T1280 /workspace/coverage/default/2.chip_sw_otbn_randomness.968723949 Aug 18 07:06:45 PM PDT 24 Aug 18 07:24:30 PM PDT 24 5783644504 ps
T410 /workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.3302750803 Aug 18 06:57:46 PM PDT 24 Aug 18 07:03:58 PM PDT 24 2940627042 ps
T1281 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.229899946 Aug 18 06:56:48 PM PDT 24 Aug 18 07:02:25 PM PDT 24 3453868476 ps
T1282 /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_no_meas.1657218426 Aug 18 07:05:22 PM PDT 24 Aug 18 08:13:35 PM PDT 24 14949541024 ps
T800 /workspace/coverage/default/32.chip_sw_all_escalation_resets.2028686480 Aug 18 07:17:31 PM PDT 24 Aug 18 07:29:53 PM PDT 24 4297983760 ps
T428 /workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.3313852694 Aug 18 06:53:03 PM PDT 24 Aug 18 07:00:54 PM PDT 24 5108789184 ps
T1283 /workspace/coverage/default/18.chip_sw_uart_rand_baudrate.3062307713 Aug 18 07:15:54 PM PDT 24 Aug 18 07:43:30 PM PDT 24 9254486276 ps
T411 /workspace/coverage/default/0.chip_sw_usbdev_config_host.503208135 Aug 18 06:53:50 PM PDT 24 Aug 18 07:30:15 PM PDT 24 8553467422 ps
T1284 /workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.29435225 Aug 18 06:51:48 PM PDT 24 Aug 18 11:10:55 PM PDT 24 77711569598 ps
T1285 /workspace/coverage/default/2.chip_sw_uart_rand_baudrate.3742187787 Aug 18 06:58:20 PM PDT 24 Aug 18 07:50:04 PM PDT 24 13158802530 ps
T1286 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2939830611 Aug 18 07:07:53 PM PDT 24 Aug 18 08:05:11 PM PDT 24 27029446368 ps
T1287 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.3049178598 Aug 18 07:02:37 PM PDT 24 Aug 18 07:23:16 PM PDT 24 8228122682 ps
T1288 /workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.4293598043 Aug 18 07:11:28 PM PDT 24 Aug 18 07:15:16 PM PDT 24 2699963747 ps
T1289 /workspace/coverage/default/0.chip_tap_straps_testunlock0.3776977878 Aug 18 06:54:33 PM PDT 24 Aug 18 07:09:11 PM PDT 24 8347868610 ps
T1290 /workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.3921805242 Aug 18 06:52:29 PM PDT 24 Aug 18 07:26:53 PM PDT 24 12384346827 ps
T343 /workspace/coverage/default/0.chip_sw_entropy_src_csrng.3165155279 Aug 18 06:56:16 PM PDT 24 Aug 18 07:26:00 PM PDT 24 7101218108 ps
T806 /workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.3843936576 Aug 18 07:21:12 PM PDT 24 Aug 18 07:29:19 PM PDT 24 3674556724 ps
T769 /workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.951088042 Aug 18 07:19:09 PM PDT 24 Aug 18 07:29:14 PM PDT 24 3805527584 ps
T161 /workspace/coverage/default/0.chip_plic_all_irqs_10.375225383 Aug 18 06:58:30 PM PDT 24 Aug 18 07:08:20 PM PDT 24 3886641530 ps
T1291 /workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.1189242595 Aug 18 07:17:50 PM PDT 24 Aug 18 07:27:11 PM PDT 24 3578854620 ps
T1292 /workspace/coverage/default/65.chip_sw_all_escalation_resets.4270947536 Aug 18 07:19:03 PM PDT 24 Aug 18 07:29:04 PM PDT 24 5120814528 ps
T1293 /workspace/coverage/default/0.chip_sw_entropy_src_kat_test.1002376352 Aug 18 06:57:13 PM PDT 24 Aug 18 07:00:35 PM PDT 24 2960028084 ps
T1294 /workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.2663117402 Aug 18 07:15:22 PM PDT 24 Aug 18 07:21:18 PM PDT 24 4074648208 ps
T1295 /workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.3683859698 Aug 18 06:59:27 PM PDT 24 Aug 18 07:08:16 PM PDT 24 4500942610 ps
T772 /workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.1469003233 Aug 18 07:15:56 PM PDT 24 Aug 18 07:24:18 PM PDT 24 4369336784 ps
T1296 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2041820573 Aug 18 06:55:03 PM PDT 24 Aug 18 07:06:45 PM PDT 24 3923210568 ps
T1297 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.720312142 Aug 18 06:57:38 PM PDT 24 Aug 18 07:17:09 PM PDT 24 9448662144 ps
T788 /workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.2696600522 Aug 18 07:17:05 PM PDT 24 Aug 18 07:24:58 PM PDT 24 3771776156 ps
T1298 /workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.2082068204 Aug 18 07:01:32 PM PDT 24 Aug 18 07:09:57 PM PDT 24 3871381244 ps
T1299 /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.456061186 Aug 18 06:59:44 PM PDT 24 Aug 18 08:27:42 PM PDT 24 33435954141 ps
T1300 /workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.3926178164 Aug 18 07:11:26 PM PDT 24 Aug 18 07:17:25 PM PDT 24 7093977546 ps
T1301 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.1822563693 Aug 18 06:57:40 PM PDT 24 Aug 18 07:08:47 PM PDT 24 4838334144 ps
T1302 /workspace/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.2456581380 Aug 18 06:55:34 PM PDT 24 Aug 18 06:59:45 PM PDT 24 3088917790 ps
T425 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.1581974377 Aug 18 06:56:42 PM PDT 24 Aug 18 07:19:12 PM PDT 24 21810169112 ps
T1303 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3284750376 Aug 18 06:56:38 PM PDT 24 Aug 18 07:05:59 PM PDT 24 4354731668 ps
T434 /workspace/coverage/default/0.rom_e2e_jtag_debug_test_unlocked0.2687913426 Aug 18 06:52:39 PM PDT 24 Aug 18 07:26:49 PM PDT 24 11709367239 ps
T9 /workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.3957682584 Aug 18 07:00:49 PM PDT 24 Aug 18 07:06:15 PM PDT 24 3458231802 ps
T1304 /workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.1048832151 Aug 18 07:13:36 PM PDT 24 Aug 18 08:05:35 PM PDT 24 11909979914 ps
T61 /workspace/coverage/default/0.chip_sw_spi_device_pinmux_sleep_retention.389258292 Aug 18 06:59:18 PM PDT 24 Aug 18 07:03:06 PM PDT 24 3400279194 ps
T1305 /workspace/coverage/default/1.rom_volatile_raw_unlock.1159880431 Aug 18 07:02:34 PM PDT 24 Aug 18 07:04:21 PM PDT 24 2689002969 ps
T1306 /workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.3681073428 Aug 18 06:56:08 PM PDT 24 Aug 18 07:32:18 PM PDT 24 23770094572 ps
T767 /workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.1627112723 Aug 18 07:14:52 PM PDT 24 Aug 18 07:24:15 PM PDT 24 3912467944 ps
T143 /workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.3928204155 Aug 18 06:55:41 PM PDT 24 Aug 18 07:03:17 PM PDT 24 4937170080 ps
T715 /workspace/coverage/default/0.chip_sw_power_sleep_load.1049171974 Aug 18 06:58:14 PM PDT 24 Aug 18 07:04:29 PM PDT 24 4102279156 ps
T1307 /workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.16748211 Aug 18 07:10:18 PM PDT 24 Aug 18 07:19:06 PM PDT 24 4096540320 ps
T1308 /workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.2607541699 Aug 18 07:17:32 PM PDT 24 Aug 18 07:23:52 PM PDT 24 4037377460 ps
T1309 /workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.2894651120 Aug 18 07:00:32 PM PDT 24 Aug 18 07:14:33 PM PDT 24 7578398320 ps
T1310 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.1254534737 Aug 18 07:11:37 PM PDT 24 Aug 18 07:22:13 PM PDT 24 3615907793 ps
T186 /workspace/coverage/default/0.chip_sw_flash_rma_unlocked.3288488730 Aug 18 06:52:43 PM PDT 24 Aug 18 08:25:12 PM PDT 24 43631871184 ps
T1311 /workspace/coverage/default/0.chip_sw_alert_handler_ping_ok.1145452789 Aug 18 06:58:13 PM PDT 24 Aug 18 07:21:30 PM PDT 24 7699598700 ps
T1312 /workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.3924630977 Aug 18 07:12:48 PM PDT 24 Aug 18 07:17:09 PM PDT 24 3039945982 ps
T1313 /workspace/coverage/default/3.chip_tap_straps_rma.925583396 Aug 18 07:11:57 PM PDT 24 Aug 18 07:21:44 PM PDT 24 4861280161 ps
T1314 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.455712493 Aug 18 06:53:39 PM PDT 24 Aug 18 07:04:20 PM PDT 24 4778166632 ps
T707 /workspace/coverage/default/1.chip_sw_plic_sw_irq.1072380582 Aug 18 07:00:38 PM PDT 24 Aug 18 07:04:39 PM PDT 24 2489637352 ps
T1315 /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.1007088935 Aug 18 07:19:21 PM PDT 24 Aug 18 08:22:01 PM PDT 24 15004062744 ps
T1316 /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.3845377312 Aug 18 07:13:22 PM PDT 24 Aug 18 07:23:22 PM PDT 24 3624438883 ps
T146 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2515451134 Aug 18 06:59:35 PM PDT 24 Aug 18 07:06:54 PM PDT 24 4794763478 ps
T1317 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.546830134 Aug 18 06:58:49 PM PDT 24 Aug 18 07:33:27 PM PDT 24 9449451670 ps
T1318 /workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.2561546817 Aug 18 07:00:52 PM PDT 24 Aug 18 07:10:42 PM PDT 24 4675651042 ps
T432 /workspace/coverage/default/0.rom_e2e_jtag_inject_test_unlocked0.1905817663 Aug 18 06:55:58 PM PDT 24 Aug 18 07:45:24 PM PDT 24 30053908328 ps
T187 /workspace/coverage/default/1.chip_sw_flash_rma_unlocked.308796882 Aug 18 06:57:46 PM PDT 24 Aug 18 08:20:45 PM PDT 24 42933929941 ps
T836 /workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.4053197060 Aug 18 07:20:29 PM PDT 24 Aug 18 07:26:53 PM PDT 24 3587569232 ps
T1319 /workspace/coverage/default/2.chip_sw_hmac_oneshot.4264422374 Aug 18 07:07:27 PM PDT 24 Aug 18 07:12:16 PM PDT 24 2231490148 ps
T1320 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3837569758 Aug 18 07:09:15 PM PDT 24 Aug 18 07:19:10 PM PDT 24 4674603750 ps
T210 /workspace/coverage/default/1.chip_jtag_mem_access.3825654381 Aug 18 06:45:08 PM PDT 24 Aug 18 07:11:19 PM PDT 24 14044278910 ps
T1321 /workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.2617311446 Aug 18 06:53:22 PM PDT 24 Aug 18 09:56:43 PM PDT 24 59461913015 ps
T737 /workspace/coverage/default/92.chip_sw_all_escalation_resets.4235993104 Aug 18 07:24:19 PM PDT 24 Aug 18 07:32:02 PM PDT 24 4781604144 ps
T1322 /workspace/coverage/default/47.chip_sw_all_escalation_resets.3349845531 Aug 18 07:17:40 PM PDT 24 Aug 18 07:29:00 PM PDT 24 6050716300 ps
T169 /workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.2923761642 Aug 18 06:53:45 PM PDT 24 Aug 18 07:02:16 PM PDT 24 4994037184 ps
T426 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.423848650 Aug 18 06:57:51 PM PDT 24 Aug 18 07:05:58 PM PDT 24 7065939960 ps
T1323 /workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1667449795 Aug 18 07:00:25 PM PDT 24 Aug 18 10:41:42 PM PDT 24 254881045108 ps
T1324 /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.1212719016 Aug 18 06:57:30 PM PDT 24 Aug 18 07:03:45 PM PDT 24 7241770480 ps
T1325 /workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.3428120092 Aug 18 06:56:54 PM PDT 24 Aug 18 07:10:23 PM PDT 24 8157648960 ps
T1326 /workspace/coverage/default/1.chip_sw_aes_enc.3652451525 Aug 18 06:59:03 PM PDT 24 Aug 18 07:03:21 PM PDT 24 2971280160 ps
T1327 /workspace/coverage/default/1.chip_sw_edn_entropy_reqs.3194568977 Aug 18 06:54:35 PM PDT 24 Aug 18 07:17:46 PM PDT 24 7170405080 ps
T693 /workspace/coverage/default/2.chip_tap_straps_dev.2622316766 Aug 18 07:09:20 PM PDT 24 Aug 18 07:29:19 PM PDT 24 10177050044 ps
T1328 /workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.1440178734 Aug 18 06:57:00 PM PDT 24 Aug 18 07:00:17 PM PDT 24 3847761979 ps
T1329 /workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.2323697946 Aug 18 06:59:08 PM PDT 24 Aug 18 07:01:40 PM PDT 24 3583064121 ps
T1330 /workspace/coverage/default/69.chip_sw_all_escalation_resets.977635860 Aug 18 07:18:43 PM PDT 24 Aug 18 07:33:25 PM PDT 24 6321003640 ps
T1331 /workspace/coverage/default/0.chip_sw_csrng_smoketest.698472026 Aug 18 06:58:03 PM PDT 24 Aug 18 07:01:38 PM PDT 24 3046752476 ps
T1332 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_outputs.3523784391 Aug 18 07:00:43 PM PDT 24 Aug 18 07:07:37 PM PDT 24 3949838744 ps
T1333 /workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.3559044440 Aug 18 06:59:26 PM PDT 24 Aug 18 08:36:06 PM PDT 24 50614338606 ps
T1334 /workspace/coverage/default/0.chip_sw_usbdev_stream.3266678582 Aug 18 06:56:22 PM PDT 24 Aug 18 08:15:40 PM PDT 24 19079082730 ps
T1335 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.3637026047 Aug 18 06:55:35 PM PDT 24 Aug 18 07:34:34 PM PDT 24 10724031000 ps
T1336 /workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.755266705 Aug 18 07:07:31 PM PDT 24 Aug 18 10:11:10 PM PDT 24 255410235768 ps
T1337 /workspace/coverage/default/1.chip_sw_uart_smoketest.1666049165 Aug 18 06:59:58 PM PDT 24 Aug 18 07:03:35 PM PDT 24 2626201850 ps
T1338 /workspace/coverage/default/0.chip_sw_kmac_smoketest.1259462839 Aug 18 06:57:01 PM PDT 24 Aug 18 07:01:48 PM PDT 24 2825888764 ps
T1339 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.3632067441 Aug 18 06:59:08 PM PDT 24 Aug 18 08:05:57 PM PDT 24 16102987892 ps
T1340 /workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.990919502 Aug 18 07:13:40 PM PDT 24 Aug 18 08:14:54 PM PDT 24 18000669224 ps
T1341 /workspace/coverage/default/1.chip_sw_rv_timer_irq.2324096560 Aug 18 06:59:43 PM PDT 24 Aug 18 07:05:09 PM PDT 24 2511644840 ps
T1342 /workspace/coverage/default/0.chip_sw_aes_entropy.2135886486 Aug 18 06:58:20 PM PDT 24 Aug 18 07:03:47 PM PDT 24 2963135770 ps
T1343 /workspace/coverage/default/1.chip_sw_flash_ctrl_access.1754607275 Aug 18 07:00:24 PM PDT 24 Aug 18 07:15:45 PM PDT 24 5109385328 ps
T1344 /workspace/coverage/default/2.rom_e2e_asm_init_prod_end.3480550615 Aug 18 07:16:46 PM PDT 24 Aug 18 08:16:51 PM PDT 24 14954064380 ps
T1345 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.603583531 Aug 18 06:59:49 PM PDT 24 Aug 18 07:58:06 PM PDT 24 14279222243 ps
T1346 /workspace/coverage/default/90.chip_sw_all_escalation_resets.3458041792 Aug 18 07:23:36 PM PDT 24 Aug 18 07:32:30 PM PDT 24 5574463072 ps
T170 /workspace/coverage/default/26.chip_sw_all_escalation_resets.4106538737 Aug 18 07:18:31 PM PDT 24 Aug 18 07:29:49 PM PDT 24 5214939912 ps
T1347 /workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.1088268978 Aug 18 06:55:37 PM PDT 24 Aug 18 07:52:49 PM PDT 24 33892093664 ps
T1348 /workspace/coverage/default/1.chip_sw_flash_ctrl_write_clear.1379160840 Aug 18 06:55:25 PM PDT 24 Aug 18 07:00:55 PM PDT 24 3648999800 ps
T1349 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3638514478 Aug 18 06:56:56 PM PDT 24 Aug 18 07:31:14 PM PDT 24 21433315095 ps
T399 /workspace/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.2033717631 Aug 18 07:10:21 PM PDT 24 Aug 18 07:16:57 PM PDT 24 5637259428 ps
T1350 /workspace/coverage/default/1.chip_sw_gpio_smoketest.2447203932 Aug 18 07:00:43 PM PDT 24 Aug 18 07:04:59 PM PDT 24 3076979034 ps
T1351 /workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.2424709719 Aug 18 06:53:27 PM PDT 24 Aug 18 07:14:46 PM PDT 24 5085487242 ps
T760 /workspace/coverage/default/91.chip_sw_all_escalation_resets.4105834123 Aug 18 07:21:31 PM PDT 24 Aug 18 07:32:12 PM PDT 24 4341414920 ps
T1352 /workspace/coverage/default/4.chip_tap_straps_prod.2955563370 Aug 18 07:12:27 PM PDT 24 Aug 18 07:32:13 PM PDT 24 11351980804 ps
T355 /workspace/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.3315059453 Aug 18 06:57:38 PM PDT 24 Aug 18 07:05:00 PM PDT 24 3491046792 ps
T1353 /workspace/coverage/default/2.rom_volatile_raw_unlock.515765730 Aug 18 07:12:18 PM PDT 24 Aug 18 07:14:20 PM PDT 24 2153004654 ps
T58 /workspace/coverage/default/1.chip_sw_sleep_pin_retention.3529111516 Aug 18 06:52:29 PM PDT 24 Aug 18 06:59:02 PM PDT 24 4204427092 ps
T1354 /workspace/coverage/default/1.rom_e2e_asm_init_dev.3542084956 Aug 18 07:02:15 PM PDT 24 Aug 18 08:19:30 PM PDT 24 15189933430 ps
T817 /workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.4203242329 Aug 18 07:20:31 PM PDT 24 Aug 18 07:27:23 PM PDT 24 4400373848 ps
T1355 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation.3677624423 Aug 18 07:07:46 PM PDT 24 Aug 18 07:36:43 PM PDT 24 9593552798 ps
T1356 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.229903811 Aug 18 06:56:32 PM PDT 24 Aug 18 07:06:07 PM PDT 24 3937066472 ps
T1357 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.4052700152 Aug 18 07:03:25 PM PDT 24 Aug 18 08:54:48 PM PDT 24 23304496896 ps
T1358 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.4035341345 Aug 18 07:10:25 PM PDT 24 Aug 18 07:23:12 PM PDT 24 3366478132 ps
T1359 /workspace/coverage/default/4.chip_sw_lc_ctrl_transition.3509326050 Aug 18 07:13:43 PM PDT 24 Aug 18 07:21:45 PM PDT 24 6831468340 ps
T62 /workspace/coverage/default/1.chip_sw_sleep_pin_wake.2858371925 Aug 18 06:58:20 PM PDT 24 Aug 18 07:03:15 PM PDT 24 2898921834 ps
T400 /workspace/coverage/default/48.chip_sw_all_escalation_resets.3225737329 Aug 18 07:18:01 PM PDT 24 Aug 18 07:27:21 PM PDT 24 4890680540 ps
T1360 /workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.3609669096 Aug 18 06:59:41 PM PDT 24 Aug 18 07:06:56 PM PDT 24 5481566336 ps
T1361 /workspace/coverage/default/2.rom_raw_unlock.1633485490 Aug 18 07:12:25 PM PDT 24 Aug 18 07:18:00 PM PDT 24 6518249020 ps
T1362 /workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.2478772936 Aug 18 06:58:05 PM PDT 24 Aug 18 07:33:45 PM PDT 24 18661274414 ps
T1363 /workspace/coverage/default/2.chip_sw_clkmgr_smoketest.3413605146 Aug 18 07:11:39 PM PDT 24 Aug 18 07:15:18 PM PDT 24 2652834604 ps
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