Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : chip_earlgrey_asic
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.90 80.00 100.00 95.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut 92.83 80.00 100.00 98.48



Module Instance : tb.dut

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.83 80.00 100.00 98.48


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.02 90.80 80.18 90.27 92.19 81.66


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
tb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
top_earlgrey 85.82 90.62 78.59 90.17 91.87 77.87
u_ast 87.36 87.36
u_padring 99.04 99.21 99.81 96.57 99.60 100.00
u_prim_usb_diff_rx 96.30 100.00 88.89 100.00

Line Coverage for Module : chip_earlgrey_asic
Line No.TotalCoveredPercent
TOTAL252080.00
CONT_ASSIGN28211100.00
CONT_ASSIGN28311100.00
CONT_ASSIGN857100.00
CONT_ASSIGN870100.00
CONT_ASSIGN899100.00
CONT_ASSIGN907100.00
CONT_ASSIGN91411100.00
CONT_ASSIGN91711100.00
CONT_ASSIGN92311100.00
CONT_ASSIGN92511100.00
CONT_ASSIGN929100.00
CONT_ASSIGN93211100.00
CONT_ASSIGN109711100.00
CONT_ASSIGN109811100.00
CONT_ASSIGN109911100.00
CONT_ASSIGN110011100.00
CONT_ASSIGN110711100.00
CONT_ASSIGN112411100.00
CONT_ASSIGN112511100.00
CONT_ASSIGN112611100.00
CONT_ASSIGN112711100.00
CONT_ASSIGN113111100.00
CONT_ASSIGN113211100.00
CONT_ASSIGN113311100.00
CONT_ASSIGN113411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv' or '../src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
282 1 1
283 1 1
857 0 1
870 0 1
899 0 1
907 0 1
914 1 1
917 1 1
923 1 1
925 1 1
929 0 1
932 1 1
1097 1 1
1098 1 1
1099 1 1
1100 1 1
1107 1 1
1124 1 1
1125 1 1
1126 1 1
1127 1 1
1131 1 1
1132 1 1
1133 1 1
1134 1 1


Cond Coverage for Module : chip_earlgrey_asic
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       79
 EXPRESSION (tb.dut.top_earlgrey.u_pwrmgr_aon.pwr_rst_o.reset_cause == LowPwrEntry)
            -----------------------------------1-----------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T8,T266

Toggle Coverage for Module : chip_earlgrey_asic
TotalCoveredPercent
Totals 70 64 91.43
Total Bits 140 134 95.71
Total Bits 0->1 70 70 100.00
Total Bits 1->0 70 64 91.43

Ports 70 64 91.43
Port Bits 140 134 95.71
Port Bits 0->1 70 70 100.00
Port Bits 1->0 70 64 91.43

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
POR_N Yes Yes T5,T6,T7 Yes T1,T2,T3 INOUT
USB_P Yes Yes T32,T92,T23 Yes T32,T33,T35 INOUT
USB_N Yes Yes T32,T33,T35 Yes T32,T33,T35 INOUT
CC1 No No Yes T23,T24,T25 INOUT
CC2 No No Yes T23,T24,T25 INOUT
FLASH_TEST_VOLT No No Yes T23,T24,T25 INOUT
FLASH_TEST_MODE0 No No Yes T23,T24,T25 INOUT
FLASH_TEST_MODE1 No No Yes T23,T24,T25 INOUT
OTP_EXT_VOLT No No Yes T23,T24,T25 INOUT
SPI_HOST_D0 Yes Yes T26,T27,T28 Yes T26,T27,T28 INOUT
SPI_HOST_D1 Yes Yes T26,T27,T28 Yes T26,T27,T28 INOUT
SPI_HOST_D2 Yes Yes T26,T27,T28 Yes T26,T73,T27 INOUT
SPI_HOST_D3 Yes Yes T26,T27,T28 Yes T26,T27,T28 INOUT
SPI_HOST_CLK Yes Yes T26,T27,T28 Yes T26,T27,T28 INOUT
SPI_HOST_CS_L Yes Yes T26,T27,T28 Yes T26,T27,T28 INOUT
SPI_DEV_D0 Yes Yes T67,T26,T27 Yes T67,T26,T27 INOUT
SPI_DEV_D1 Yes Yes T67,T26,T27 Yes T67,T26,T27 INOUT
SPI_DEV_D2 Yes Yes T67,T26,T27 Yes T67,T26,T27 INOUT
SPI_DEV_D3 Yes Yes T67,T26,T27 Yes T67,T26,T27 INOUT
SPI_DEV_CLK Yes Yes T67,T26,T27 Yes T67,T26,T27 INOUT
SPI_DEV_CS_L Yes Yes T67,T26,T73 Yes T67,T26,T27 INOUT
IOR8 Yes Yes T36,T246,T37 Yes T36,T73,T246 INOUT
IOR9 Yes Yes T36,T14,T246 Yes T8,T36,T73 INOUT
IOA0 Yes Yes T29,T30,T31 Yes T29,T30,T31 INOUT
IOA1 Yes Yes T29,T30,T31 Yes T29,T30,T31 INOUT
IOA2 Yes Yes T29,T105,T40 Yes T29,T105,T40 INOUT
IOA3 Yes Yes T29,T40,T41 Yes T29,T40,T23 INOUT
IOA4 Yes Yes T135,T29,T40 Yes T135,T29,T40 INOUT
IOA5 Yes Yes T135,T29,T40 Yes T135,T29,T40 INOUT
IOA6 Yes Yes T29,T40,T41 Yes T29,T40,T41 INOUT
IOA7 Yes Yes T218,T29,T27 Yes T218,T29,T27 INOUT
IOA8 Yes Yes T218,T29,T67 Yes T218,T29,T67 INOUT
IOB0 Yes Yes T27,T28,T57 Yes T27,T28,T57 INOUT
IOB1 Yes Yes T27,T28,T57 Yes T27,T28,T23 INOUT
IOB2 Yes Yes T27,T28,T57 Yes T27,T28,T23 INOUT
IOB3 Yes Yes T36,T27,T246 Yes T27,T246,T28 INOUT
IOB4 Yes Yes T3,T93,T311 Yes T3,T93,T311 INOUT
IOB5 Yes Yes T3,T93,T311 Yes T3,T93,T311 INOUT
IOB6 Yes Yes T36,T246,T37 Yes T246,T40,T247 INOUT
IOB7 Yes Yes T40,T34,T75 Yes T8,T36,T37 INOUT
IOB8 Yes Yes T27,T246,T40 Yes T27,T246,T40 INOUT
IOB9 Yes Yes T36,T27,T312 Yes T36,T27,T312 INOUT
IOB10 Yes Yes T105,T27,T308 Yes T105,T27,T308 INOUT
IOB11 Yes Yes T105,T219,T27 Yes T105,T219,T27 INOUT
IOB12 Yes Yes T105,T219,T27 Yes T105,T219,T27 INOUT
IOC0 Yes Yes T59,T5,T7 Yes T279,T244,T24 INOUT
IOC1 Yes Yes T244,T245,T187 Yes T23,T244,T24 INOUT
IOC2 Yes Yes T244,T245,T187 Yes T23,T244,T24 INOUT
IOC3 Yes Yes T295,T117,T313 Yes T295,T117,T313 INOUT
IOC4 Yes Yes T59,T5,T7 Yes T59,T5,T7 INOUT
IOC5 Yes Yes T314,T82,T84 Yes T314,T13,T23 INOUT
IOC6 Yes Yes T6,T93,T62 Yes T6,T93,T62 INOUT
IOC7 Yes Yes T246,T247,T39 Yes T32,T92,T36 INOUT
IOC8 Yes Yes T314,T84,T186 Yes T314,T23,T82 INOUT
IOC9 Yes Yes T8,T40,T51 Yes T8,T36,T37 INOUT
IOC10 Yes Yes T105,T308,T40 Yes T105,T308,T40 INOUT
IOC11 Yes Yes T105,T308,T40 Yes T105,T308,T40 INOUT
IOC12 Yes Yes T105,T308,T40 Yes T105,T308,T40 INOUT
IOR0 Yes Yes T6,T60,T76 Yes T6,T60,T76 INOUT
IOR1 Yes Yes T6,T60,T76 Yes T6,T60,T76 INOUT
IOR2 Yes Yes T6,T60,T76 Yes T6,T60,T76 INOUT
IOR3 Yes Yes T6,T60,T76 Yes T6,T60,T76 INOUT
IOR4 Yes Yes T6,T60,T61 Yes T6,T62,T60 INOUT
IOR5 Yes Yes T36,T27,T37 Yes T36,T27,T37 INOUT
IOR6 Yes Yes T27,T40,T28 Yes T36,T27,T37 INOUT
IOR7 Yes Yes T27,T40,T28 Yes T27,T40,T28 INOUT
IOR10 Yes Yes T27,T40,T28 Yes T27,T40,T28 INOUT
IOR11 Yes Yes T27,T40,T28 Yes T27,T40,T28 INOUT
IOR12 Yes Yes T40,T41,T315 Yes T40,T23,T41 INOUT
IOR13 Yes Yes T13,T316,T353 Yes T13,T316,T353 INOUT

Line Coverage for Instance : tb.dut
Line No.TotalCoveredPercent
TOTAL252080.00
CONT_ASSIGN28211100.00
CONT_ASSIGN28311100.00
CONT_ASSIGN857100.00
CONT_ASSIGN870100.00
CONT_ASSIGN899100.00
CONT_ASSIGN907100.00
CONT_ASSIGN91411100.00
CONT_ASSIGN91711100.00
CONT_ASSIGN92311100.00
CONT_ASSIGN92511100.00
CONT_ASSIGN929100.00
CONT_ASSIGN93211100.00
CONT_ASSIGN109711100.00
CONT_ASSIGN109811100.00
CONT_ASSIGN109911100.00
CONT_ASSIGN110011100.00
CONT_ASSIGN110711100.00
CONT_ASSIGN112411100.00
CONT_ASSIGN112511100.00
CONT_ASSIGN112611100.00
CONT_ASSIGN112711100.00
CONT_ASSIGN113111100.00
CONT_ASSIGN113211100.00
CONT_ASSIGN113311100.00
CONT_ASSIGN113411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv' or '../src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
282 1 1
283 1 1
857 0 1
870 0 1
899 0 1
907 0 1
914 1 1
917 1 1
923 1 1
925 1 1
929 0 1
932 1 1
1097 1 1
1098 1 1
1099 1 1
1100 1 1
1107 1 1
1124 1 1
1125 1 1
1126 1 1
1127 1 1
1131 1 1
1132 1 1
1133 1 1
1134 1 1


Cond Coverage for Instance : tb.dut
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       79
 EXPRESSION (tb.dut.top_earlgrey.u_pwrmgr_aon.pwr_rst_o.reset_cause == LowPwrEntry)
            -----------------------------------1-----------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T8,T266

Toggle Coverage for Instance : tb.dut
TotalCoveredPercent
Totals 66 64 96.97
Total Bits 132 130 98.48
Total Bits 0->1 66 66 100.00
Total Bits 1->0 66 64 96.97

Ports 66 64 96.97
Port Bits 132 130 98.48
Port Bits 0->1 66 66 100.00
Port Bits 1->0 66 64 96.97

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
POR_N Yes Yes T5,T6,T7 Yes T1,T2,T3 INOUT
USB_P Yes Yes T32,T92,T23 Yes T32,T33,T35 INOUT
USB_N Yes Yes T32,T33,T35 Yes T32,T33,T35 INOUT
CC1 No No Yes T23,T24,T25 INOUT
CC2 No No Yes T23,T24,T25 INOUT
FLASH_TEST_VOLT[0:0] Excluded Excluded Excluded INOUT [LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and flash. Must be covered in vendor closed source DV.
FLASH_TEST_MODE0[0:0] Excluded Excluded Excluded INOUT [LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and flash. Must be covered in vendor closed source DV.
FLASH_TEST_MODE1[0:0] Excluded Excluded Excluded INOUT [LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and flash. Must be covered in vendor closed source DV.
OTP_EXT_VOLT[0:0] Excluded Excluded Excluded INOUT [LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and OTP. Must be covered in vendor closed source DV.
SPI_HOST_D0 Yes Yes T26,T27,T28 Yes T26,T27,T28 INOUT
SPI_HOST_D1 Yes Yes T26,T27,T28 Yes T26,T27,T28 INOUT
SPI_HOST_D2 Yes Yes T26,T27,T28 Yes T26,T73,T27 INOUT
SPI_HOST_D3 Yes Yes T26,T27,T28 Yes T26,T27,T28 INOUT
SPI_HOST_CLK Yes Yes T26,T27,T28 Yes T26,T27,T28 INOUT
SPI_HOST_CS_L Yes Yes T26,T27,T28 Yes T26,T27,T28 INOUT
SPI_DEV_D0 Yes Yes T67,T26,T27 Yes T67,T26,T27 INOUT
SPI_DEV_D1 Yes Yes T67,T26,T27 Yes T67,T26,T27 INOUT
SPI_DEV_D2 Yes Yes T67,T26,T27 Yes T67,T26,T27 INOUT
SPI_DEV_D3 Yes Yes T67,T26,T27 Yes T67,T26,T27 INOUT
SPI_DEV_CLK Yes Yes T67,T26,T27 Yes T67,T26,T27 INOUT
SPI_DEV_CS_L Yes Yes T67,T26,T73 Yes T67,T26,T27 INOUT
IOR8 Yes Yes T36,T246,T37 Yes T36,T73,T246 INOUT
IOR9 Yes Yes T36,T14,T246 Yes T8,T36,T73 INOUT
IOA0 Yes Yes T29,T30,T31 Yes T29,T30,T31 INOUT
IOA1 Yes Yes T29,T30,T31 Yes T29,T30,T31 INOUT
IOA2 Yes Yes T29,T105,T40 Yes T29,T105,T40 INOUT
IOA3 Yes Yes T29,T40,T41 Yes T29,T40,T23 INOUT
IOA4 Yes Yes T135,T29,T40 Yes T135,T29,T40 INOUT
IOA5 Yes Yes T135,T29,T40 Yes T135,T29,T40 INOUT
IOA6 Yes Yes T29,T40,T41 Yes T29,T40,T41 INOUT
IOA7 Yes Yes T218,T29,T27 Yes T218,T29,T27 INOUT
IOA8 Yes Yes T218,T29,T67 Yes T218,T29,T67 INOUT
IOB0 Yes Yes T27,T28,T57 Yes T27,T28,T57 INOUT
IOB1 Yes Yes T27,T28,T57 Yes T27,T28,T23 INOUT
IOB2 Yes Yes T27,T28,T57 Yes T27,T28,T23 INOUT
IOB3 Yes Yes T36,T27,T246 Yes T27,T246,T28 INOUT
IOB4 Yes Yes T3,T93,T311 Yes T3,T93,T311 INOUT
IOB5 Yes Yes T3,T93,T311 Yes T3,T93,T311 INOUT
IOB6 Yes Yes T36,T246,T37 Yes T246,T40,T247 INOUT
IOB7 Yes Yes T40,T34,T75 Yes T8,T36,T37 INOUT
IOB8 Yes Yes T27,T246,T40 Yes T27,T246,T40 INOUT
IOB9 Yes Yes T36,T27,T312 Yes T36,T27,T312 INOUT
IOB10 Yes Yes T105,T27,T308 Yes T105,T27,T308 INOUT
IOB11 Yes Yes T105,T219,T27 Yes T105,T219,T27 INOUT
IOB12 Yes Yes T105,T219,T27 Yes T105,T219,T27 INOUT
IOC0 Yes Yes T59,T5,T7 Yes T279,T244,T24 INOUT
IOC1 Yes Yes T244,T245,T187 Yes T23,T244,T24 INOUT
IOC2 Yes Yes T244,T245,T187 Yes T23,T244,T24 INOUT
IOC3 Yes Yes T295,T117,T313 Yes T295,T117,T313 INOUT
IOC4 Yes Yes T59,T5,T7 Yes T59,T5,T7 INOUT
IOC5 Yes Yes T314,T82,T84 Yes T314,T13,T23 INOUT
IOC6 Yes Yes T6,T93,T62 Yes T6,T93,T62 INOUT
IOC7 Yes Yes T246,T247,T39 Yes T32,T92,T36 INOUT
IOC8 Yes Yes T314,T84,T186 Yes T314,T23,T82 INOUT
IOC9 Yes Yes T8,T40,T51 Yes T8,T36,T37 INOUT
IOC10 Yes Yes T105,T308,T40 Yes T105,T308,T40 INOUT
IOC11 Yes Yes T105,T308,T40 Yes T105,T308,T40 INOUT
IOC12 Yes Yes T105,T308,T40 Yes T105,T308,T40 INOUT
IOR0 Yes Yes T6,T60,T76 Yes T6,T60,T76 INOUT
IOR1 Yes Yes T6,T60,T76 Yes T6,T60,T76 INOUT
IOR2 Yes Yes T6,T60,T76 Yes T6,T60,T76 INOUT
IOR3 Yes Yes T6,T60,T76 Yes T6,T60,T76 INOUT
IOR4 Yes Yes T6,T60,T61 Yes T6,T62,T60 INOUT
IOR5 Yes Yes T36,T27,T37 Yes T36,T27,T37 INOUT
IOR6 Yes Yes T27,T40,T28 Yes T36,T27,T37 INOUT
IOR7 Yes Yes T27,T40,T28 Yes T27,T40,T28 INOUT
IOR10 Yes Yes T27,T40,T28 Yes T27,T40,T28 INOUT
IOR11 Yes Yes T27,T40,T28 Yes T27,T40,T28 INOUT
IOR12 Yes Yes T40,T41,T315 Yes T40,T23,T41 INOUT
IOR13 Yes Yes T13,T316,T353 Yes T13,T316,T353 INOUT

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