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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
86.66 90.80 80.18 90.27 92.19 81.66 84.87


Total test records in report: 1023
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T714 /workspace/coverage/default/1.chip_sw_aes_smoketest.621859500 Aug 19 06:40:22 PM PDT 24 Aug 19 06:43:47 PM PDT 24 2816756120 ps
T715 /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.947523215 Aug 19 06:53:00 PM PDT 24 Aug 19 07:03:17 PM PDT 24 4008503282 ps
T716 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2968900675 Aug 19 06:35:42 PM PDT 24 Aug 19 06:42:43 PM PDT 24 7569177000 ps
T534 /workspace/coverage/default/12.chip_sw_all_escalation_resets.1080978315 Aug 19 06:58:21 PM PDT 24 Aug 19 07:11:01 PM PDT 24 6799478394 ps
T717 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.2280307461 Aug 19 06:37:22 PM PDT 24 Aug 19 06:50:14 PM PDT 24 4136149560 ps
T718 /workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.4239353437 Aug 19 06:36:01 PM PDT 24 Aug 19 06:43:39 PM PDT 24 4345460352 ps
T83 /workspace/coverage/default/1.chip_tap_straps_rma.75941936 Aug 19 06:35:39 PM PDT 24 Aug 19 06:38:49 PM PDT 24 3252383269 ps
T455 /workspace/coverage/default/4.chip_tap_straps_dev.2507783693 Aug 19 06:56:56 PM PDT 24 Aug 19 07:15:38 PM PDT 24 10137056184 ps
T533 /workspace/coverage/default/25.chip_sw_all_escalation_resets.2895300589 Aug 19 06:55:47 PM PDT 24 Aug 19 07:08:05 PM PDT 24 5452195940 ps
T358 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.2542188481 Aug 19 06:36:06 PM PDT 24 Aug 19 06:43:04 PM PDT 24 4556757398 ps
T719 /workspace/coverage/default/1.chip_sw_kmac_idle.1011228280 Aug 19 06:36:56 PM PDT 24 Aug 19 06:40:38 PM PDT 24 3291395902 ps
T457 /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.1354700945 Aug 19 06:35:23 PM PDT 24 Aug 19 06:37:28 PM PDT 24 2808893712 ps
T249 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.64332356 Aug 19 06:40:03 PM PDT 24 Aug 19 06:45:38 PM PDT 24 3143693632 ps
T720 /workspace/coverage/default/1.chip_sw_aon_timer_smoketest.3891395162 Aug 19 06:40:15 PM PDT 24 Aug 19 06:44:55 PM PDT 24 3442976680 ps
T332 /workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.27532750 Aug 19 06:38:41 PM PDT 24 Aug 19 06:49:13 PM PDT 24 5032347206 ps
T386 /workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.3942087853 Aug 19 06:55:35 PM PDT 24 Aug 19 07:02:55 PM PDT 24 4037328074 ps
T372 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.2870610128 Aug 19 06:37:49 PM PDT 24 Aug 19 06:48:16 PM PDT 24 3890081451 ps
T721 /workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.3589219049 Aug 19 06:51:23 PM PDT 24 Aug 19 07:09:31 PM PDT 24 5509379152 ps
T52 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.4077210937 Aug 19 06:34:39 PM PDT 24 Aug 19 06:41:34 PM PDT 24 5753525448 ps
T722 /workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.1934870405 Aug 19 06:52:38 PM PDT 24 Aug 19 06:59:22 PM PDT 24 6689417800 ps
T304 /workspace/coverage/default/2.chip_sw_all_escalation_resets.4136226928 Aug 19 06:40:45 PM PDT 24 Aug 19 06:50:04 PM PDT 24 4507074640 ps
T723 /workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.2899818502 Aug 19 06:53:36 PM PDT 24 Aug 19 07:00:26 PM PDT 24 6597502644 ps
T250 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.4145091874 Aug 19 06:36:16 PM PDT 24 Aug 19 07:05:16 PM PDT 24 24525618812 ps
T724 /workspace/coverage/default/3.chip_tap_straps_testunlock0.3222142837 Aug 19 06:53:05 PM PDT 24 Aug 19 07:00:42 PM PDT 24 5718330942 ps
T512 /workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.1060209416 Aug 19 06:59:04 PM PDT 24 Aug 19 07:05:13 PM PDT 24 3571533160 ps
T725 /workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.2564684731 Aug 19 06:32:55 PM PDT 24 Aug 19 06:40:42 PM PDT 24 6245837264 ps
T726 /workspace/coverage/default/2.chip_sw_aes_enc.702915916 Aug 19 06:47:00 PM PDT 24 Aug 19 06:51:45 PM PDT 24 3426301186 ps
T727 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1567308386 Aug 19 06:43:28 PM PDT 24 Aug 19 07:07:21 PM PDT 24 12819532074 ps
T527 /workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.143200089 Aug 19 06:55:13 PM PDT 24 Aug 19 07:02:06 PM PDT 24 4391090766 ps
T728 /workspace/coverage/default/3.chip_tap_straps_dev.1600439350 Aug 19 06:51:28 PM PDT 24 Aug 19 07:18:52 PM PDT 24 15842681355 ps
T729 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.248188516 Aug 19 06:34:54 PM PDT 24 Aug 19 06:41:44 PM PDT 24 5290622690 ps
T391 /workspace/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.2819836437 Aug 19 06:50:12 PM PDT 24 Aug 19 06:56:33 PM PDT 24 4802868604 ps
T730 /workspace/coverage/default/15.chip_sw_uart_rand_baudrate.2043099887 Aug 19 06:54:56 PM PDT 24 Aug 19 07:31:12 PM PDT 24 13169541384 ps
T505 /workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.3265331938 Aug 19 06:58:46 PM PDT 24 Aug 19 07:05:53 PM PDT 24 3768012364 ps
T731 /workspace/coverage/default/0.chip_sw_otbn_smoketest.2992505263 Aug 19 06:34:10 PM PDT 24 Aug 19 06:50:58 PM PDT 24 5509000234 ps
T732 /workspace/coverage/default/2.chip_sw_otbn_randomness.3607616229 Aug 19 06:46:01 PM PDT 24 Aug 19 07:01:46 PM PDT 24 6072199144 ps
T733 /workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.2206339514 Aug 19 06:44:25 PM PDT 24 Aug 19 06:51:09 PM PDT 24 2597655186 ps
T549 /workspace/coverage/default/54.chip_sw_all_escalation_resets.3478811165 Aug 19 06:59:08 PM PDT 24 Aug 19 07:06:10 PM PDT 24 4207822690 ps
T734 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.2088918822 Aug 19 06:37:13 PM PDT 24 Aug 19 07:05:50 PM PDT 24 9306450160 ps
T735 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.2414249241 Aug 19 06:38:10 PM PDT 24 Aug 19 07:43:28 PM PDT 24 15462967120 ps
T736 /workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.302589508 Aug 19 06:35:01 PM PDT 24 Aug 19 06:43:53 PM PDT 24 5014193998 ps
T737 /workspace/coverage/default/2.chip_sw_alert_handler_escalation.3663757280 Aug 19 06:46:59 PM PDT 24 Aug 19 06:54:59 PM PDT 24 5410774604 ps
T738 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.2351861722 Aug 19 06:43:56 PM PDT 24 Aug 19 07:38:19 PM PDT 24 15362003808 ps
T559 /workspace/coverage/default/93.chip_sw_all_escalation_resets.612677556 Aug 19 07:01:24 PM PDT 24 Aug 19 07:11:02 PM PDT 24 5665261316 ps
T739 /workspace/coverage/default/0.rom_e2e_self_hash.934013189 Aug 19 06:47:05 PM PDT 24 Aug 19 08:35:04 PM PDT 24 26432927628 ps
T300 /workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.4187456376 Aug 19 06:50:30 PM PDT 24 Aug 19 06:55:07 PM PDT 24 2813995230 ps
T740 /workspace/coverage/default/1.chip_sw_kmac_entropy.2353399697 Aug 19 06:35:54 PM PDT 24 Aug 19 06:40:14 PM PDT 24 3145532400 ps
T456 /workspace/coverage/default/2.chip_tap_straps_dev.3078742356 Aug 19 06:52:48 PM PDT 24 Aug 19 07:07:31 PM PDT 24 8602576557 ps
T741 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.690252214 Aug 19 06:55:53 PM PDT 24 Aug 19 07:06:59 PM PDT 24 4524848712 ps
T475 /workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.1953669666 Aug 19 06:57:57 PM PDT 24 Aug 19 07:04:30 PM PDT 24 3399231618 ps
T41 /workspace/coverage/default/1.chip_sw_gpio_smoketest.3102689289 Aug 19 06:37:13 PM PDT 24 Aug 19 06:42:52 PM PDT 24 3533538745 ps
T742 /workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.949623969 Aug 19 06:38:46 PM PDT 24 Aug 19 06:57:12 PM PDT 24 7560923786 ps
T743 /workspace/coverage/default/11.chip_sw_uart_rand_baudrate.2755156569 Aug 19 06:53:34 PM PDT 24 Aug 19 07:01:55 PM PDT 24 4187223132 ps
T744 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac.1583264273 Aug 19 06:38:16 PM PDT 24 Aug 19 06:44:53 PM PDT 24 2875888092 ps
T554 /workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.1312535691 Aug 19 06:56:48 PM PDT 24 Aug 19 07:03:50 PM PDT 24 4649975624 ps
T519 /workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.502656762 Aug 19 06:59:26 PM PDT 24 Aug 19 07:05:24 PM PDT 24 3498672440 ps
T745 /workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.3880769154 Aug 19 06:36:01 PM PDT 24 Aug 19 06:40:22 PM PDT 24 3594021616 ps
T70 /workspace/coverage/default/1.chip_sw_sleep_pin_retention.4288616891 Aug 19 06:36:57 PM PDT 24 Aug 19 06:42:22 PM PDT 24 2878765638 ps
T458 /workspace/coverage/default/2.rom_volatile_raw_unlock.2287193502 Aug 19 06:54:09 PM PDT 24 Aug 19 06:56:21 PM PDT 24 2406811848 ps
T459 /workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.3685448577 Aug 19 06:33:03 PM PDT 24 Aug 19 06:35:40 PM PDT 24 3462861665 ps
T113 /workspace/coverage/default/0.chip_sw_sensor_ctrl_status.3655702930 Aug 19 06:39:31 PM PDT 24 Aug 19 06:45:44 PM PDT 24 3062297250 ps
T746 /workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.2600824262 Aug 19 06:58:46 PM PDT 24 Aug 19 07:05:09 PM PDT 24 4632575496 ps
T188 /workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.1346363844 Aug 19 06:37:15 PM PDT 24 Aug 19 09:21:14 PM PDT 24 59540840016 ps
T747 /workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.2655589598 Aug 19 06:36:30 PM PDT 24 Aug 19 06:43:59 PM PDT 24 3928293400 ps
T748 /workspace/coverage/default/1.chip_sw_rv_dm_access_after_wakeup.303253081 Aug 19 06:41:05 PM PDT 24 Aug 19 06:49:47 PM PDT 24 6035948648 ps
T506 /workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.1821432512 Aug 19 06:58:15 PM PDT 24 Aug 19 07:06:41 PM PDT 24 3313287726 ps
T528 /workspace/coverage/default/99.chip_sw_all_escalation_resets.2679906308 Aug 19 07:01:07 PM PDT 24 Aug 19 07:11:47 PM PDT 24 5010700424 ps
T149 /workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.230581700 Aug 19 06:41:22 PM PDT 24 Aug 19 06:51:48 PM PDT 24 8779767801 ps
T749 /workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.2151144537 Aug 19 06:44:53 PM PDT 24 Aug 19 06:49:59 PM PDT 24 3110625848 ps
T131 /workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.3008979822 Aug 19 06:49:00 PM PDT 24 Aug 19 07:01:07 PM PDT 24 6169661180 ps
T750 /workspace/coverage/default/2.rom_e2e_asm_init_prod_end.748971622 Aug 19 06:58:38 PM PDT 24 Aug 19 08:04:03 PM PDT 24 15311693457 ps
T751 /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.2445239789 Aug 19 06:37:15 PM PDT 24 Aug 19 06:41:26 PM PDT 24 3016987652 ps
T532 /workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.2572974853 Aug 19 06:57:19 PM PDT 24 Aug 19 07:03:36 PM PDT 24 3507257798 ps
T503 /workspace/coverage/default/42.chip_sw_all_escalation_resets.3557164242 Aug 19 06:58:07 PM PDT 24 Aug 19 07:05:30 PM PDT 24 4470098690 ps
T87 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2904588413 Aug 19 06:51:59 PM PDT 24 Aug 19 07:16:24 PM PDT 24 24816958216 ps
T752 /workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.2513032242 Aug 19 06:39:49 PM PDT 24 Aug 19 06:45:55 PM PDT 24 3271950644 ps
T753 /workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.2111274331 Aug 19 06:54:28 PM PDT 24 Aug 19 08:04:13 PM PDT 24 19707632446 ps
T214 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.1123281413 Aug 19 06:40:12 PM PDT 24 Aug 19 07:07:07 PM PDT 24 13171252712 ps
T146 /workspace/coverage/default/1.chip_plic_all_irqs_10.1265156647 Aug 19 06:40:59 PM PDT 24 Aug 19 06:54:06 PM PDT 24 4348291624 ps
T10 /workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.712046895 Aug 19 06:50:34 PM PDT 24 Aug 19 06:56:52 PM PDT 24 3710480286 ps
T196 /workspace/coverage/default/64.chip_sw_all_escalation_resets.57153582 Aug 19 07:00:50 PM PDT 24 Aug 19 07:13:18 PM PDT 24 5228195024 ps
T55 /workspace/coverage/default/0.chip_sw_spi_device_tpm.3422917392 Aug 19 06:32:43 PM PDT 24 Aug 19 06:39:33 PM PDT 24 3399407935 ps
T447 /workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.918263694 Aug 19 06:35:41 PM PDT 24 Aug 19 06:45:30 PM PDT 24 5791886198 ps
T357 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.3570165635 Aug 19 06:48:01 PM PDT 24 Aug 19 07:00:07 PM PDT 24 5433307354 ps
T69 /workspace/coverage/default/0.chip_sw_sleep_pin_retention.828422607 Aug 19 06:31:09 PM PDT 24 Aug 19 06:35:17 PM PDT 24 3598136090 ps
T448 /workspace/coverage/default/2.chip_sw_aon_timer_smoketest.3014102398 Aug 19 06:52:02 PM PDT 24 Aug 19 06:57:48 PM PDT 24 3816440550 ps
T449 /workspace/coverage/default/27.chip_sw_all_escalation_resets.2876089785 Aug 19 06:56:35 PM PDT 24 Aug 19 07:04:53 PM PDT 24 4628214400 ps
T450 /workspace/coverage/default/1.chip_sw_all_escalation_resets.1682664530 Aug 19 06:39:01 PM PDT 24 Aug 19 06:51:48 PM PDT 24 4687645216 ps
T451 /workspace/coverage/default/0.chip_sw_inject_scramble_seed.4192285836 Aug 19 06:33:59 PM PDT 24 Aug 19 09:50:37 PM PDT 24 65543442379 ps
T754 /workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.104725390 Aug 19 06:49:22 PM PDT 24 Aug 19 07:00:36 PM PDT 24 5444872952 ps
T755 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3854807425 Aug 19 06:38:25 PM PDT 24 Aug 19 07:01:38 PM PDT 24 17438353466 ps
T387 /workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.1406699506 Aug 19 06:54:49 PM PDT 24 Aug 19 07:00:51 PM PDT 24 3454460988 ps
T756 /workspace/coverage/default/2.chip_sw_otbn_smoketest.879273097 Aug 19 06:54:07 PM PDT 24 Aug 19 07:25:20 PM PDT 24 10540737176 ps
T757 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.3268075412 Aug 19 06:39:54 PM PDT 24 Aug 19 07:47:36 PM PDT 24 14725717880 ps
T758 /workspace/coverage/default/1.chip_sw_rv_timer_smoketest.701243681 Aug 19 06:42:43 PM PDT 24 Aug 19 06:47:24 PM PDT 24 3404516380 ps
T151 /workspace/coverage/default/38.chip_sw_all_escalation_resets.698011939 Aug 19 06:56:31 PM PDT 24 Aug 19 07:05:53 PM PDT 24 4827539736 ps
T759 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1176521654 Aug 19 06:40:46 PM PDT 24 Aug 19 06:53:53 PM PDT 24 4034884080 ps
T760 /workspace/coverage/default/0.rom_keymgr_functest.4270568862 Aug 19 06:33:47 PM PDT 24 Aug 19 06:42:38 PM PDT 24 4974080680 ps
T761 /workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.3629054524 Aug 19 06:59:23 PM PDT 24 Aug 19 07:06:55 PM PDT 24 3864196900 ps
T56 /workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.3397263825 Aug 19 06:37:28 PM PDT 24 Aug 19 06:47:41 PM PDT 24 4747693344 ps
T762 /workspace/coverage/default/2.chip_sw_edn_sw_mode.1074925144 Aug 19 06:47:28 PM PDT 24 Aug 19 07:31:28 PM PDT 24 10476168440 ps
T557 /workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.1345692559 Aug 19 06:57:47 PM PDT 24 Aug 19 07:04:22 PM PDT 24 3362987976 ps
T763 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.851775569 Aug 19 06:39:02 PM PDT 24 Aug 19 06:49:33 PM PDT 24 3809974800 ps
T764 /workspace/coverage/default/2.chip_sw_rv_plic_smoketest.4138732908 Aug 19 06:52:32 PM PDT 24 Aug 19 06:56:23 PM PDT 24 3009329272 ps
T71 /workspace/coverage/default/0.chip_sw_spi_device_pinmux_sleep_retention.1603106719 Aug 19 06:34:30 PM PDT 24 Aug 19 06:39:36 PM PDT 24 3228400236 ps
T765 /workspace/coverage/default/2.chip_tap_straps_prod.1203126921 Aug 19 06:49:11 PM PDT 24 Aug 19 07:12:04 PM PDT 24 12370466524 ps
T766 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.2593982894 Aug 19 06:39:31 PM PDT 24 Aug 19 06:49:06 PM PDT 24 4150095050 ps
T767 /workspace/coverage/default/0.chip_sw_hmac_enc.565929178 Aug 19 06:31:30 PM PDT 24 Aug 19 06:34:33 PM PDT 24 2666664676 ps
T768 /workspace/coverage/default/0.rom_e2e_asm_init_dev.668844589 Aug 19 06:38:22 PM PDT 24 Aug 19 07:43:04 PM PDT 24 15572288140 ps
T769 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.1170532121 Aug 19 06:36:51 PM PDT 24 Aug 19 07:38:57 PM PDT 24 16913853304 ps
T558 /workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.1473584259 Aug 19 07:00:25 PM PDT 24 Aug 19 07:05:21 PM PDT 24 3786657400 ps
T165 /workspace/coverage/default/0.chip_jtag_mem_access.2597970045 Aug 19 06:24:04 PM PDT 24 Aug 19 06:47:15 PM PDT 24 13799599287 ps
T770 /workspace/coverage/default/9.chip_sw_uart_rand_baudrate.1619983546 Aug 19 06:56:27 PM PDT 24 Aug 19 07:18:14 PM PDT 24 8006711000 ps
T771 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.2885080603 Aug 19 06:36:35 PM PDT 24 Aug 19 06:46:57 PM PDT 24 4278931772 ps
T772 /workspace/coverage/default/2.chip_sw_edn_auto_mode.354138377 Aug 19 06:48:39 PM PDT 24 Aug 19 07:05:30 PM PDT 24 4332418328 ps
T524 /workspace/coverage/default/22.chip_sw_all_escalation_resets.3525945218 Aug 19 06:56:49 PM PDT 24 Aug 19 07:05:40 PM PDT 24 4464986092 ps
T773 /workspace/coverage/default/1.chip_sw_hmac_multistream.3565408142 Aug 19 06:37:13 PM PDT 24 Aug 19 07:10:55 PM PDT 24 7840853000 ps
T774 /workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.1018323986 Aug 19 06:43:10 PM PDT 24 Aug 19 06:52:49 PM PDT 24 7776764725 ps
T775 /workspace/coverage/default/2.chip_sw_clkmgr_off_peri.626398855 Aug 19 06:48:58 PM PDT 24 Aug 19 07:07:09 PM PDT 24 11867578516 ps
T776 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2069492982 Aug 19 06:35:58 PM PDT 24 Aug 19 06:50:44 PM PDT 24 4688014440 ps
T568 /workspace/coverage/default/44.chip_sw_all_escalation_resets.889232857 Aug 19 06:58:32 PM PDT 24 Aug 19 07:05:27 PM PDT 24 4055175808 ps
T777 /workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.3154821662 Aug 19 06:56:31 PM PDT 24 Aug 19 08:15:42 PM PDT 24 20942859604 ps
T778 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2029633472 Aug 19 06:39:58 PM PDT 24 Aug 19 07:16:57 PM PDT 24 23850490285 ps
T471 /workspace/coverage/default/66.chip_sw_all_escalation_resets.2773702556 Aug 19 06:58:36 PM PDT 24 Aug 19 07:08:22 PM PDT 24 4526524600 ps
T779 /workspace/coverage/default/0.rom_e2e_static_critical.2639803181 Aug 19 06:46:24 PM PDT 24 Aug 19 08:01:04 PM PDT 24 16725557030 ps
T780 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac.2887897010 Aug 19 06:47:55 PM PDT 24 Aug 19 06:53:24 PM PDT 24 2854391824 ps
T781 /workspace/coverage/default/1.chip_sw_aes_entropy.4100808115 Aug 19 06:36:42 PM PDT 24 Aug 19 06:40:05 PM PDT 24 2289012500 ps
T95 /workspace/coverage/default/26.chip_sw_all_escalation_resets.3277773886 Aug 19 06:56:29 PM PDT 24 Aug 19 07:07:52 PM PDT 24 5051327560 ps
T782 /workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.3906706168 Aug 19 06:56:38 PM PDT 24 Aug 19 07:04:25 PM PDT 24 3447883240 ps
T366 /workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.1252637825 Aug 19 06:33:21 PM PDT 24 Aug 19 06:39:55 PM PDT 24 3717568760 ps
T783 /workspace/coverage/default/63.chip_sw_all_escalation_resets.3419523798 Aug 19 06:59:35 PM PDT 24 Aug 19 07:07:58 PM PDT 24 5240170240 ps
T784 /workspace/coverage/default/2.chip_sw_data_integrity_escalation.874022672 Aug 19 06:44:01 PM PDT 24 Aug 19 06:58:02 PM PDT 24 6953703416 ps
T785 /workspace/coverage/default/0.chip_sw_clkmgr_jitter.1532842868 Aug 19 06:35:54 PM PDT 24 Aug 19 06:41:40 PM PDT 24 2976996649 ps
T786 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.1671485203 Aug 19 06:41:40 PM PDT 24 Aug 19 07:36:57 PM PDT 24 15074074644 ps
T787 /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.931802327 Aug 19 06:39:22 PM PDT 24 Aug 19 06:43:05 PM PDT 24 2630658746 ps
T788 /workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.4208795613 Aug 19 06:54:25 PM PDT 24 Aug 19 07:02:56 PM PDT 24 5971310040 ps
T789 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.1954639914 Aug 19 06:38:44 PM PDT 24 Aug 19 07:04:24 PM PDT 24 8507143974 ps
T199 /workspace/coverage/default/2.chip_sw_lc_ctrl_program_error.1596093105 Aug 19 06:49:42 PM PDT 24 Aug 19 06:58:40 PM PDT 24 5411663804 ps
T360 /workspace/coverage/default/2.chip_sw_entropy_src_csrng.3868183764 Aug 19 06:50:41 PM PDT 24 Aug 19 07:15:39 PM PDT 24 6278656630 ps
T790 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.146138158 Aug 19 06:40:21 PM PDT 24 Aug 19 06:52:29 PM PDT 24 4785691498 ps
T791 /workspace/coverage/default/2.chip_sw_flash_init.800746267 Aug 19 06:39:34 PM PDT 24 Aug 19 07:14:58 PM PDT 24 22729971600 ps
T296 /workspace/coverage/default/55.chip_sw_all_escalation_resets.1883162784 Aug 19 06:57:32 PM PDT 24 Aug 19 07:05:46 PM PDT 24 5218888700 ps
T792 /workspace/coverage/default/0.chip_sw_kmac_idle.1408374300 Aug 19 06:37:37 PM PDT 24 Aug 19 06:43:05 PM PDT 24 2951613546 ps
T565 /workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.3629505646 Aug 19 06:56:45 PM PDT 24 Aug 19 07:02:31 PM PDT 24 3673153762 ps
T793 /workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.1415300301 Aug 19 06:37:46 PM PDT 24 Aug 19 08:11:09 PM PDT 24 52051130842 ps
T794 /workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.367895929 Aug 19 06:34:42 PM PDT 24 Aug 19 06:45:47 PM PDT 24 4794340024 ps
T544 /workspace/coverage/default/30.chip_sw_all_escalation_resets.359304538 Aug 19 06:55:45 PM PDT 24 Aug 19 07:09:14 PM PDT 24 6016631048 ps
T215 /workspace/coverage/default/0.chip_plic_all_irqs_0.528134877 Aug 19 06:30:32 PM PDT 24 Aug 19 06:43:45 PM PDT 24 5961403486 ps
T795 /workspace/coverage/default/2.chip_sw_edn_kat.3313456500 Aug 19 06:47:33 PM PDT 24 Aug 19 06:59:55 PM PDT 24 3352173382 ps
T796 /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.3390189627 Aug 19 06:35:01 PM PDT 24 Aug 19 06:40:11 PM PDT 24 2790518900 ps
T324 /workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.4183243077 Aug 19 06:38:41 PM PDT 24 Aug 19 07:19:24 PM PDT 24 10320054888 ps
T797 /workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.3662641350 Aug 19 06:48:47 PM PDT 24 Aug 19 06:56:30 PM PDT 24 4196682696 ps
T181 /workspace/coverage/default/1.chip_plic_all_irqs_20.51140201 Aug 19 06:39:53 PM PDT 24 Aug 19 06:52:02 PM PDT 24 4524384416 ps
T251 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.450753652 Aug 19 06:38:08 PM PDT 24 Aug 19 07:12:26 PM PDT 24 24104188026 ps
T260 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.129036420 Aug 19 06:39:05 PM PDT 24 Aug 19 08:11:08 PM PDT 24 24348488014 ps
T134 /workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.2486363509 Aug 19 06:38:43 PM PDT 24 Aug 19 06:59:52 PM PDT 24 9762220168 ps
T798 /workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.2076702702 Aug 19 06:55:22 PM PDT 24 Aug 19 07:03:34 PM PDT 24 4974950128 ps
T48 /workspace/coverage/default/1.chip_sw_spi_host_tx_rx.2306333588 Aug 19 06:34:51 PM PDT 24 Aug 19 06:39:49 PM PDT 24 2935604928 ps
T80 /workspace/coverage/default/4.chip_tap_straps_rma.527232893 Aug 19 06:53:15 PM PDT 24 Aug 19 07:00:54 PM PDT 24 5086412414 ps
T799 /workspace/coverage/default/1.rom_e2e_self_hash.3253980654 Aug 19 06:41:57 PM PDT 24 Aug 19 08:09:04 PM PDT 24 25887154798 ps
T800 /workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.1480250208 Aug 19 06:40:31 PM PDT 24 Aug 19 06:50:23 PM PDT 24 4787281112 ps
T801 /workspace/coverage/default/3.chip_sw_uart_rand_baudrate.3964108337 Aug 19 06:53:00 PM PDT 24 Aug 19 07:14:51 PM PDT 24 8262262392 ps
T802 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.3109376429 Aug 19 06:34:19 PM PDT 24 Aug 19 07:25:45 PM PDT 24 14929484330 ps
T803 /workspace/coverage/default/0.chip_sw_clkmgr_smoketest.1620618581 Aug 19 06:35:38 PM PDT 24 Aug 19 06:40:06 PM PDT 24 3300848640 ps
T804 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.3635654085 Aug 19 06:35:18 PM PDT 24 Aug 19 06:39:13 PM PDT 24 2956725314 ps
T530 /workspace/coverage/default/48.chip_sw_all_escalation_resets.3557477383 Aug 19 06:59:49 PM PDT 24 Aug 19 07:14:49 PM PDT 24 5525998360 ps
T805 /workspace/coverage/default/2.chip_sw_lc_ctrl_transition.859556809 Aug 19 06:40:50 PM PDT 24 Aug 19 06:49:19 PM PDT 24 5177218488 ps
T806 /workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.3964233205 Aug 19 06:39:12 PM PDT 24 Aug 19 06:50:51 PM PDT 24 5563301256 ps
T807 /workspace/coverage/default/1.rom_e2e_static_critical.1654788587 Aug 19 06:42:19 PM PDT 24 Aug 19 07:45:04 PM PDT 24 17829634376 ps
T808 /workspace/coverage/default/0.chip_sw_flash_crash_alert.1636116882 Aug 19 06:33:23 PM PDT 24 Aug 19 06:43:37 PM PDT 24 5933975510 ps
T809 /workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.2211344117 Aug 19 06:40:06 PM PDT 24 Aug 19 06:43:33 PM PDT 24 2808514928 ps
T526 /workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.836283374 Aug 19 06:55:26 PM PDT 24 Aug 19 07:01:44 PM PDT 24 4216657660 ps
T810 /workspace/coverage/default/2.chip_sw_rv_timer_smoketest.2981739971 Aug 19 06:54:34 PM PDT 24 Aug 19 06:58:33 PM PDT 24 2607159336 ps
T811 /workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.2021110602 Aug 19 06:34:46 PM PDT 24 Aug 19 07:07:18 PM PDT 24 24179954687 ps
T812 /workspace/coverage/default/1.chip_sw_aes_enc.1552535595 Aug 19 06:34:04 PM PDT 24 Aug 19 06:37:49 PM PDT 24 2732432696 ps
T132 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3746097313 Aug 19 06:36:15 PM PDT 24 Aug 19 06:44:13 PM PDT 24 5746614594 ps
T200 /workspace/coverage/default/1.chip_sw_lc_ctrl_program_error.3263341803 Aug 19 06:40:42 PM PDT 24 Aug 19 06:49:02 PM PDT 24 5021260496 ps
T375 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops.609982012 Aug 19 06:36:30 PM PDT 24 Aug 19 06:48:23 PM PDT 24 4750095810 ps
T566 /workspace/coverage/default/85.chip_sw_all_escalation_resets.2919091152 Aug 19 07:00:41 PM PDT 24 Aug 19 07:08:38 PM PDT 24 4870938868 ps
T518 /workspace/coverage/default/39.chip_sw_all_escalation_resets.2766832058 Aug 19 06:55:34 PM PDT 24 Aug 19 07:02:44 PM PDT 24 4640053216 ps
T485 /workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.1619489408 Aug 19 06:31:00 PM PDT 24 Aug 19 06:40:10 PM PDT 24 5364638548 ps
T813 /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.2864813957 Aug 19 06:37:13 PM PDT 24 Aug 19 06:51:47 PM PDT 24 8995267680 ps
T814 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.3698918405 Aug 19 06:43:05 PM PDT 24 Aug 19 08:22:13 PM PDT 24 23514409268 ps
T815 /workspace/coverage/default/1.chip_sw_alert_handler_entropy.1050218279 Aug 19 06:36:57 PM PDT 24 Aug 19 06:42:29 PM PDT 24 3211286036 ps
T816 /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.1182084738 Aug 19 06:50:03 PM PDT 24 Aug 19 08:04:14 PM PDT 24 15237277348 ps
T817 /workspace/coverage/default/0.chip_sw_example_rom.4035310789 Aug 19 06:32:09 PM PDT 24 Aug 19 06:34:50 PM PDT 24 2743498676 ps
T818 /workspace/coverage/default/1.rom_e2e_asm_init_prod_end.2070093074 Aug 19 06:43:25 PM PDT 24 Aug 19 07:58:28 PM PDT 24 15670927591 ps
T819 /workspace/coverage/default/2.chip_sw_ast_clk_outputs.1975157399 Aug 19 06:50:16 PM PDT 24 Aug 19 07:09:27 PM PDT 24 8418806046 ps
T820 /workspace/coverage/default/1.chip_sw_alert_handler_ping_ok.3707845224 Aug 19 06:36:37 PM PDT 24 Aug 19 06:58:35 PM PDT 24 8147995970 ps
T821 /workspace/coverage/default/1.chip_sw_csrng_smoketest.432524183 Aug 19 06:37:43 PM PDT 24 Aug 19 06:41:36 PM PDT 24 2378013514 ps
T822 /workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.1312608191 Aug 19 06:35:17 PM PDT 24 Aug 19 06:38:43 PM PDT 24 2360352376 ps
T254 /workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.2117442181 Aug 19 06:45:03 PM PDT 24 Aug 19 06:56:25 PM PDT 24 5785928584 ps
T823 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.1442652249 Aug 19 06:35:50 PM PDT 24 Aug 19 06:47:14 PM PDT 24 4343382472 ps
T824 /workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.1444765363 Aug 19 06:38:41 PM PDT 24 Aug 19 06:48:49 PM PDT 24 5179888552 ps
T381 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.670926591 Aug 19 06:36:52 PM PDT 24 Aug 19 06:48:33 PM PDT 24 4532755542 ps
T178 /workspace/coverage/default/1.chip_sw_sleep_pin_wake.2617875383 Aug 19 06:37:47 PM PDT 24 Aug 19 06:44:17 PM PDT 24 5696340532 ps
T429 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.2666819404 Aug 19 06:41:24 PM PDT 24 Aug 19 07:47:58 PM PDT 24 16137295750 ps
T430 /workspace/coverage/default/2.rom_keymgr_functest.4002662856 Aug 19 06:53:49 PM PDT 24 Aug 19 07:02:21 PM PDT 24 4427055888 ps
T431 /workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.1594579111 Aug 19 06:36:12 PM PDT 24 Aug 19 06:46:09 PM PDT 24 5641557424 ps
T432 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.2716083077 Aug 19 06:38:29 PM PDT 24 Aug 19 07:02:09 PM PDT 24 10948275592 ps
T433 /workspace/coverage/default/1.chip_sw_uart_rand_baudrate.2211684298 Aug 19 06:38:27 PM PDT 24 Aug 19 07:05:16 PM PDT 24 8031426440 ps
T337 /workspace/coverage/default/0.rom_raw_unlock.323546016 Aug 19 06:39:02 PM PDT 24 Aug 19 06:43:25 PM PDT 24 5181236548 ps
T434 /workspace/coverage/default/96.chip_sw_all_escalation_resets.1610811197 Aug 19 07:01:10 PM PDT 24 Aug 19 07:09:18 PM PDT 24 4951874850 ps
T435 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_outputs.2739776872 Aug 19 06:47:22 PM PDT 24 Aug 19 06:53:52 PM PDT 24 3860056248 ps
T436 /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.3498058960 Aug 19 06:36:41 PM PDT 24 Aug 19 06:58:50 PM PDT 24 6362702487 ps
T825 /workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.3264195300 Aug 19 06:52:09 PM PDT 24 Aug 19 07:18:58 PM PDT 24 22928487256 ps
T826 /workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.1427564167 Aug 19 06:32:39 PM PDT 24 Aug 19 06:41:13 PM PDT 24 3489374652 ps
T255 /workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.2358387418 Aug 19 06:34:31 PM PDT 24 Aug 19 06:43:41 PM PDT 24 6008657000 ps
T827 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.3580427366 Aug 19 06:40:55 PM PDT 24 Aug 19 07:00:50 PM PDT 24 5427956120 ps
T828 /workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.3848203788 Aug 19 06:40:56 PM PDT 24 Aug 19 06:48:48 PM PDT 24 4114531604 ps
T829 /workspace/coverage/default/1.chip_sw_example_flash.3898257160 Aug 19 06:36:05 PM PDT 24 Aug 19 06:40:12 PM PDT 24 2622374456 ps
T830 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.312852924 Aug 19 06:35:47 PM PDT 24 Aug 19 06:45:11 PM PDT 24 4164360740 ps
T522 /workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.1488619117 Aug 19 07:03:58 PM PDT 24 Aug 19 07:10:32 PM PDT 24 3915639596 ps
T831 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.2129730954 Aug 19 06:43:21 PM PDT 24 Aug 19 08:29:54 PM PDT 24 24884529788 ps
T832 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.3909339386 Aug 19 06:48:56 PM PDT 24 Aug 19 07:11:50 PM PDT 24 23243137228 ps
T11 /workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.736759974 Aug 19 06:40:47 PM PDT 24 Aug 19 06:47:46 PM PDT 24 4132772440 ps
T150 /workspace/coverage/default/0.chip_sw_kmac_app_rom.4077613576 Aug 19 06:36:49 PM PDT 24 Aug 19 06:40:30 PM PDT 24 2962675662 ps
T833 /workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.2388290031 Aug 19 06:48:24 PM PDT 24 Aug 19 06:52:11 PM PDT 24 3342224144 ps
T523 /workspace/coverage/default/32.chip_sw_all_escalation_resets.3540583635 Aug 19 06:57:11 PM PDT 24 Aug 19 07:06:59 PM PDT 24 5565479848 ps
T338 /workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.852727883 Aug 19 06:50:31 PM PDT 24 Aug 19 06:58:47 PM PDT 24 3682266068 ps
T834 /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.3781415538 Aug 19 06:49:54 PM PDT 24 Aug 19 06:54:33 PM PDT 24 2788085456 ps
T225 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.26119907 Aug 19 06:40:03 PM PDT 24 Aug 19 06:51:45 PM PDT 24 5199668648 ps
T835 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.58851512 Aug 19 06:36:41 PM PDT 24 Aug 19 06:50:43 PM PDT 24 7506791212 ps
T836 /workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.405269054 Aug 19 06:54:16 PM PDT 24 Aug 19 07:33:02 PM PDT 24 11893985946 ps
T837 /workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.1969195313 Aug 19 06:54:35 PM PDT 24 Aug 19 06:58:01 PM PDT 24 3285523991 ps
T838 /workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.2408629467 Aug 19 06:46:31 PM PDT 24 Aug 19 06:54:11 PM PDT 24 7814420520 ps
T839 /workspace/coverage/default/2.chip_sw_edn_entropy_reqs.4169067061 Aug 19 06:47:43 PM PDT 24 Aug 19 07:09:07 PM PDT 24 5612809980 ps
T411 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.1444573582 Aug 19 06:38:55 PM PDT 24 Aug 19 07:31:46 PM PDT 24 24522985978 ps
T297 /workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.2768504308 Aug 19 06:58:43 PM PDT 24 Aug 19 07:05:26 PM PDT 24 4179542622 ps
T63 /workspace/coverage/default/2.chip_jtag_csr_rw.779156682 Aug 19 06:42:41 PM PDT 24 Aug 19 06:59:04 PM PDT 24 9659162718 ps
T840 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.2807387155 Aug 19 06:47:15 PM PDT 24 Aug 19 06:57:41 PM PDT 24 8012697282 ps
T841 /workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.970095614 Aug 19 06:40:12 PM PDT 24 Aug 19 07:00:14 PM PDT 24 5726078960 ps
T842 /workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.3985624063 Aug 19 06:36:21 PM PDT 24 Aug 19 06:40:04 PM PDT 24 2749302952 ps
T182 /workspace/coverage/default/0.chip_plic_all_irqs_20.2113343764 Aug 19 06:40:29 PM PDT 24 Aug 19 06:53:20 PM PDT 24 4831718716 ps
T843 /workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.2570249344 Aug 19 06:38:00 PM PDT 24 Aug 19 07:15:47 PM PDT 24 28412939929 ps
T844 /workspace/coverage/default/35.chip_sw_all_escalation_resets.1382487279 Aug 19 06:57:11 PM PDT 24 Aug 19 07:06:53 PM PDT 24 6564329940 ps
T845 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.3668393356 Aug 19 06:37:47 PM PDT 24 Aug 19 07:01:42 PM PDT 24 7549170472 ps
T846 /workspace/coverage/default/0.rom_e2e_jtag_inject_test_unlocked0.3582405095 Aug 19 06:39:38 PM PDT 24 Aug 19 07:15:35 PM PDT 24 34649162206 ps
T847 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.4164696970 Aug 19 06:36:10 PM PDT 24 Aug 19 06:47:39 PM PDT 24 4468852656 ps
T397 /workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.3102687331 Aug 19 06:59:19 PM PDT 24 Aug 19 07:05:28 PM PDT 24 3881898032 ps
T848 /workspace/coverage/default/0.chip_sw_kmac_smoketest.1057091227 Aug 19 06:33:57 PM PDT 24 Aug 19 06:38:38 PM PDT 24 2864330736 ps
T228 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.1564184560 Aug 19 06:33:36 PM PDT 24 Aug 19 06:47:33 PM PDT 24 4094215504 ps
T177 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.2608812294 Aug 19 06:50:43 PM PDT 24 Aug 19 07:13:22 PM PDT 24 22655857704 ps
T424 /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2166599241 Aug 19 06:36:03 PM PDT 24 Aug 19 06:43:14 PM PDT 24 6755563752 ps
T849 /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.3801871127 Aug 19 06:41:16 PM PDT 24 Aug 19 07:02:15 PM PDT 24 5518427098 ps
T850 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2859560505 Aug 19 06:47:06 PM PDT 24 Aug 19 07:24:10 PM PDT 24 24477143609 ps
T460 /workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.3126163609 Aug 19 06:37:02 PM PDT 24 Aug 19 06:40:01 PM PDT 24 2520044503 ps
T851 /workspace/coverage/default/0.rom_e2e_asm_init_prod_end.2423387215 Aug 19 06:39:34 PM PDT 24 Aug 19 07:36:54 PM PDT 24 15383758057 ps
T852 /workspace/coverage/default/5.chip_sw_data_integrity_escalation.1495494707 Aug 19 06:54:57 PM PDT 24 Aug 19 07:07:50 PM PDT 24 6283477544 ps
T853 /workspace/coverage/default/0.chip_sw_flash_init.2554613022 Aug 19 06:31:22 PM PDT 24 Aug 19 07:14:33 PM PDT 24 26345126632 ps
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