Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_rv_plic.gen_target[0].u_target.u_prim_max_tree

Module Instance : tb.dut.top_earlgrey.u_rv_plic.gen_target[0].u_target.u_prim_max_tree

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.46	89.27	76.58			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.46	89.27	76.58			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		gen_target[0].u_target

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.gen_target[0].u_target.u_prim_max_tree

	Line No.	Total	Covered	Percent
TOTAL		1258	1123	89.27
CONT_ASSIGN	72	1	0	0.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
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CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
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CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
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CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
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CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
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CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
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CONT_ASSIGN	74	1	1	100.00
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CONT_ASSIGN	85	0	0
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CONT_ASSIGN	85	1	1	100.00
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CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	0	0
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CONT_ASSIGN	85	0	0
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CONT_ASSIGN	85	0	0
CONT_ASSIGN	85	0	0
CONT_ASSIGN	85	0	0
CONT_ASSIGN	85	0	0
CONT_ASSIGN	85	0	0
CONT_ASSIGN	85	0	0
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CONT_ASSIGN	85	0	0
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CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ROUTINE	114	0	0
ROUTINE	125	0	0
CONT_ASSIGN	138	0	0
CONT_ASSIGN	139	0	0

Click here to see the source line report.

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.gen_target[0].u_target.u_prim_max_tree

	Total	Covered	Percent
Conditions	3313	2537	76.58
Logical	3313	2537	76.58
Non-Logical	0	0
Event	0	0

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.

Line numbers	Percent
85	63.64
85	62.80
85	60.44
85	57.78
85	55.37
85-90	72.40
90	100.00
90-91	100.00
91	100.00
91-92	100.00
92	100.00
92	100.00

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.gen_target[0].u_target.u_prim_max_tree

	Line No.	Total	Covered	Percent
Branches		1320	1320	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	1	1	100.00
TERNARY	91	1	1	100.00
TERNARY	92	1	1	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	1	1	100.00
TERNARY	91	1	1	100.00
TERNARY	92	1	1	100.00
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TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	1	1	100.00
TERNARY	91	1	1	100.00
TERNARY	92	1	1	100.00
TERNARY	90	1	1	100.00
TERNARY	91	1	1	100.00
TERNARY	92	1	1	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
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TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
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TERNARY	90	2	2	100.00
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TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
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TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
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TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
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TERNARY	90	2	2	100.00
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TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	1	1	100.00
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TERNARY	92	1	1	100.00
TERNARY	90	1	1	100.00
TERNARY	91	1	1	100.00
TERNARY	92	1	1	100.00
TERNARY	90	1	1	100.00
TERNARY	91	1	1	100.00
TERNARY	92	1	1	100.00
TERNARY	90	1	1	100.00
TERNARY	91	1	1	100.00
TERNARY	92	1	1	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
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TERNARY	90	2	2	100.00
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TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
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TERNARY	91	1	1	100.00
TERNARY	92	1	1	100.00
TERNARY	90	1	1	100.00
TERNARY	91	1	1	100.00
TERNARY	92	1	1	100.00
TERNARY	90	1	1	100.00
TERNARY	91	1	1	100.00
TERNARY	92	1	1	100.00
TERNARY	90	1	1	100.00
TERNARY	91	1	1	100.00
TERNARY	92	1	1	100.00
TERNARY	90	1	1	100.00
TERNARY	91	1	1	100.00
TERNARY	92	1	1	100.00
TERNARY	90	1	1	100.00
TERNARY	91	1	1	100.00
TERNARY	92	1	1	100.00
TERNARY	90	1	1	100.00
TERNARY	91	1	1	100.00
TERNARY	92	1	1	100.00
TERNARY	90	1	1	100.00
TERNARY	91	1	1	100.00
TERNARY	92	1	1	100.00
TERNARY	90	1	1	100.00
TERNARY	91	1	1	100.00
TERNARY	92	1	1	100.00
TERNARY	90	1	1	100.00
TERNARY	91	1	1	100.00
TERNARY	92	1	1	100.00
TERNARY	90	1	1	100.00
TERNARY	91	1	1	100.00
TERNARY	92	1	1	100.00
TERNARY	90	1	1	100.00
TERNARY	91	1	1	100.00
TERNARY	92	1	1	100.00
TERNARY	90	1	1	100.00
TERNARY	91	1	1	100.00
TERNARY	92	1	1	100.00
TERNARY	90	1	1	100.00
TERNARY	91	1	1	100.00
TERNARY	92	1	1	100.00

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T22,T178
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T22,T178
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T22,T178
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T39
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T39
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T39
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T311,T34
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T311,T34
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T311,T34
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T39,T27,T58
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T39,T27,T58
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T39,T27,T58
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T178,T147,T316
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T178,T147,T316
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T178,T147,T316
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T24,T23,T122
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T24,T23,T122
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T24,T23,T122
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T311,T320
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T311,T320
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T311,T320
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T53,T54,T56
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T53,T54,T56
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T53,T54,T56
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T39,T27,T58
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T39,T27,T58
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T39,T27,T58
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T22,T19
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T22,T19
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T22,T19
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T316,T311,T320
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T316,T311,T320
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T316,T311,T320
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T24,T120,T121
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T24,T120,T121
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T24,T120,T121
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T23,T34,T61
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T23,T34,T61
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T23,T34,T61
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T311,T320
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T311,T320
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T311,T320
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T311,T320
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T311,T320
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T311,T320
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T11,T54,T311
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T11,T54,T311
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T11,T54,T311
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T56,T311,T57
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T56,T311,T57
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T56,T311,T57
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T58,T311,T59
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T58,T311,T59
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T58,T311,T59
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T39,T27,T172
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T39,T27,T172
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T39,T27,T172
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T318,T319
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T318,T319
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T318,T319
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T22,T19
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T22,T19
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T22,T19
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T147,T316,T163
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T147,T316,T163
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T147,T316,T163
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T316,T311,T320
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T316,T311,T320
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T316,T311,T320
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T120,T121,T317
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T120,T121,T317
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T120,T121,T317
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T24,T122,T123
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T24,T122,T123
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T24,T122,T123
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T23,T60,T318
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T23,T60,T318
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T23,T60,T318
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T34,T61,T318
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T34,T61,T318
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T34,T61,T318
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T311,T34
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T311,T34
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T311,T34
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T311,T320
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T311,T320
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T311,T320
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T311,T320
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T311,T320
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T311,T320
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T311,T320
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T311,T320
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T311,T320
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T311
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T311
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T311
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T54,T311,T55
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T54,T311,T55
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T54,T311,T55
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T53,T54,T311
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T53,T54,T311
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T53,T54,T311
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T56,T311,T57
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T56,T311,T57
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T56,T311,T57
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T56,T311,T57
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T56,T311,T57
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T56,T311,T57
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T58,T311,T59
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T58,T311,T59
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T58,T311,T59
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T58,T311,T59
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T58,T311,T59
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T58,T311,T59
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T39,T172,T65
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T39,T172,T65
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T39,T172,T65
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T168,T318,T319
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T168,T318,T319
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T168,T318,T319
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T318,T319
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T318,T319
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T318,T319
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T318,T319
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T318,T319
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T318,T319
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T172,T65,T245
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T172,T65,T245
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T172,T65,T245
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T178,T314,T311
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T178,T314,T311
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T178,T314,T311
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T147,T316,T163
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T147,T316,T163
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T147,T316,T163
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T316,T311,T320
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T316,T311,T320
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T316,T311,T320
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T120,T121,T317
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T120,T121,T317
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T120,T121,T317
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T318,T319
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T318,T319
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T318,T319
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T24,T122,T123
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T24,T122,T123
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T24,T122,T123
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T318,T319
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T318,T319
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T318,T319
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T24,T23,T122
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T24,T23,T122
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T24,T23,T122
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T23,T60,T318
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T23,T60,T318
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T23,T60,T318
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T23,T60,T318
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T23,T60,T318
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T23,T60,T318
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T34,T61,T318
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T34,T61,T318
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T34,T61,T318
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T318,T319
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T318,T319
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T318,T319
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T311,T320
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T311,T320
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T311,T320
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T311,T320
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T311,T320
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T311,T320
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T311,T320
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T311,T320
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T311,T320
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T311,T320
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T311,T320
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T311,T320
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T311,T320
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T311,T320
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T311,T320
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T311,T320
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T311,T320
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T311,T320
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T311,T320
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T311,T320
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T311,T320
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T311,T320
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T311,T320
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T311,T320
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T168,T169
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T168,T169
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T168,T169
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T11,T168,T43
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T11,T168,T43
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T11,T168,T43
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T54,T311,T55
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T54,T311,T55
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T54,T311,T55
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T320,T321
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T320,T321
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T320,T321
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T53,T54,T311
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T53,T54,T311
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T53,T54,T311
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T320,T321
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T320,T321
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T320,T321
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T320,T321
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T320,T321
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T320,T321
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T320,T321
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T320,T321
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T320,T321
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T320,T321
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T320,T321
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T320,T321
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T58,T311,T59
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T58,T311,T59
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T58,T311,T59
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T320,T321
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T320,T321
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T320,T321
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T320,T321
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T320,T321
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T320,T321
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T320,T321
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T320,T321
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T320,T321
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T27,T126,T168
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T27,T126,T168
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T27,T126,T168
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T39,T172,T65
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T39,T172,T65
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T39,T172,T65
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T75,T172,T311
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T75,T172,T311
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T75,T172,T311
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T168,T318,T319
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T168,T318,T319
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T168,T318,T319
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T318,T319
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T318,T319
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T318,T319
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T318,T319
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T318,T319
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T318,T319
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T318,T319
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T318,T319
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T318,T319
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T318,T319
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T318,T319
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T318,T319
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T63,T311,T129
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T63,T311,T129
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T63,T311,T129
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T161,T162,T168
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T161,T162,T168
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T161,T162,T168
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T323,T320
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T323,T320
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T323,T320
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T314,T311,T315
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T314,T311,T315
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T314,T311,T315
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T168,T169
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T168,T169
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T168,T169
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T316,T311,T320
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T316,T311,T320
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T316,T311,T320
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T320,T321
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T320,T321
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T320,T321
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T316,T311,T320
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T316,T311,T320
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T316,T311,T320
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T120,T121,T317
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T120,T121,T317
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T120,T121,T317
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T120,T121,T317
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T120,T121,T317
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T120,T121,T317
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T318,T319
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T318,T319
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T318,T319
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T318,T319
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T318,T319
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T318,T319
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T120,T121,T317
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T120,T121,T317
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T120,T121,T317
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T24,T122,T123
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T24,T122,T123
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T24,T122,T123
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T24,T122,T123
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T24,T122,T123
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T24,T122,T123
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T318,T319
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T318,T319
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T318,T319
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T318,T319
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T318,T319
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T318,T319
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T23,T60,T318
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T23,T60,T318
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T23,T60,T318
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T23,T60,T318
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T23,T60,T318
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T23,T60,T318
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T318,T319
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T318,T319
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T318,T319
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T318,T319
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T318,T319
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T318,T319
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T23,T60,T318
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T23,T60,T318
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T23,T60,T318
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T34,T61,T318
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T34,T61,T318
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T34,T61,T318
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T34,T61,T318
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T34,T61,T318
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T34,T61,T318
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T318,T319
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T318,T319
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T318,T319
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T318,T319
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T318,T319
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T318,T319
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T311,T320
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T311,T320
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T311,T320
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T311,T320
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T311,T320
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T311,T320
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T311,T320
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T311,T320
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T311,T320
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T311,T320
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T311,T320
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T311,T320
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T311,T320
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T311,T320
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T311,T320
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T311,T320
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T311,T320
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T311,T320
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T311,T320
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T311,T320
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T311,T320
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T311,T320
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T311,T320
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T311,T320
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T311,T320
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T311,T320
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T311,T320
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T311,T320
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T311,T320
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T311,T320
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T311,T320
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T311,T320
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T311,T320
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T311,T320
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T311,T320
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T311,T320
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T311,T320
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T311,T320
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T311,T320
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T311,T320
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T311,T320
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T311,T320
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T311,T320
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T311,T320
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T311,T320
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T311,T320
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T311,T320
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T311,T320
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T3,T205,T168
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T3,T205,T168
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T3,T205,T168
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T168,T169
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T168,T169
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T168,T169
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T168,T169
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T168,T169
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T168,T169
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T168,T169
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T168,T169
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T168,T169
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T54,T311,T55
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T54,T311,T55
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T54,T311,T55
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T320,T321
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T320,T321
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T320,T321
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T320,T321
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T320,T321
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T320,T321
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T320,T321
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T320,T321
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T320,T321
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T320,T321
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T320,T321
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T320,T321
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T320,T321
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T320,T321
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T320,T321
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T320,T321
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T320,T321
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T320,T321
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T320,T321
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T320,T321
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T320,T321
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T56,T311,T57
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T56,T311,T57
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T56,T311,T57
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T320,T321
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T320,T321
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T320,T321
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T320,T321
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T320,T321
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T320,T321
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T320,T321
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T320,T321
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T320,T321
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T56,T311,T57
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T56,T311,T57
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T56,T311,T57
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T320,T321
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T320,T321
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T320,T321
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T320,T321
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T320,T321
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T320,T321
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T58,T311,T59
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T58,T311,T59
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T58,T311,T59
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T320,T321
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T320,T321
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T320,T321
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T320,T321
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T320,T321
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T320,T321
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T320,T321
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T320,T321
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T320,T321
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T320,T321
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T320,T321
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T320,T321
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T320,T321
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T320,T321
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T320,T321
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T320,T321
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T320,T321
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T320,T321
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T320,T321
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T320,T321
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T320,T321
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T168,T169
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T168,T169
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T168,T169
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T168,T169
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T168,T169
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T168,T169
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T39,T172,T65
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T39,T172,T65
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T39,T172,T65
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T76,T311,T320
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T76,T311,T320
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T76,T311,T320
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T168,T169
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T168,T169
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T168,T169
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T168,T169
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T168,T169
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T168,T169
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T318,T319
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T318,T319
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T318,T319
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T318,T319
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T318,T319
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T318,T319
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T318,T319
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T318,T319
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T318,T319
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T318,T319
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T318,T319
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T318,T319
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T318,T319
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T318,T319
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T318,T319
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T318,T319
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T318,T319
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T318,T319
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T318,T319
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T318,T319
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T318,T319
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T318,T319
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T318,T319
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T318,T319
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T318,T319
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T318,T319
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T318,T319
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T22,T19
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T22,T19
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T22,T19
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T129,T320
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T129,T320
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T129,T320
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T172,T65,T245
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T172,T65,T245
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T172,T65,T245
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T168,T169
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T168,T169
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T168,T169
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T178,T311,T313
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T178,T311,T313
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T178,T311,T313
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T323,T320
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T323,T320
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T323,T320
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T320,T321
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T320,T321
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T320,T321
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T320,T321
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T320,T321
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T320,T321
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T168,T169
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T168,T169
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T168,T169
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T168,T169
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T168,T169
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T168,T169
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T168,T169
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T168,T169
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T168,T169
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T316,T311,T320
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T316,T311,T320
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T316,T311,T320
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T320,T321
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T320,T321
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T320,T321
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T320,T321
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T320,T321
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T320,T321
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T320,T321
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T320,T321
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T320,T321
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T320,T321
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T320,T321
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T320,T321
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T320,T321
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T320,T321
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T311,T320,T321
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.gen_target[0].u_target.u_prim_max_tree

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
MaxComputationInvalid_A	414974052	413335638	0	0
MaxComputation_A	414974052	1557612	0	0
MaxIndexComputationInvalid_A	414974052	413335638	0	0
MaxIndexComputation_A	414974052	1557612	0	0
NumSources_A	777	777	0	0
ValidInImpliesValidOut_A	414974052	414893250	0	0

MaxComputationInvalid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414974052	413335638	0	0
T1	103166	101172	0	0
T2	68779	68728	0	0
T3	212795	211171	0	0
T4	180992	175680	0	0
T11	130451	122225	0	0
T22	115208	114267	0	0
T24	219043	217622	0	0
T31	97041	96935	0	0
T39	225028	163806	0	0
T97	78718	78656	0	0

MaxComputation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414974052	1557612	0	0
T1	103166	1939	0	0
T2	68779	0	0	0
T3	212795	1573	0	0
T4	180992	5250	0	0
T11	130451	8171	0	0
T22	115208	886	0	0
T23	0	1252	0	0
T24	219043	1366	0	0
T27	0	150	0	0
T31	97041	0	0	0
T39	225028	61105	0	0
T97	78718	0	0	0
T178	0	1543	0	0

MaxIndexComputationInvalid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414974052	413335638	0	0
T1	103166	101172	0	0
T2	68779	68728	0	0
T3	212795	211171	0	0
T4	180992	175680	0	0
T11	130451	122225	0	0
T22	115208	114267	0	0
T24	219043	217622	0	0
T31	97041	96935	0	0
T39	225028	163806	0	0
T97	78718	78656	0	0

MaxIndexComputation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414974052	1557612	0	0
T1	103166	1939	0	0
T2	68779	0	0	0
T3	212795	1573	0	0
T4	180992	5250	0	0
T11	130451	8171	0	0
T22	115208	886	0	0
T23	0	1252	0	0
T24	219043	1366	0	0
T27	0	150	0	0
T31	97041	0	0	0
T39	225028	61105	0	0
T97	78718	0	0	0
T178	0	1543	0	0

NumSources_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	777	777	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T11	1	1	0	0
T22	1	1	0	0
T24	1	1	0	0
T31	1	1	0	0
T39	1	1	0	0
T97	1	1	0	0

ValidInImpliesValidOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414974052	414893250	0	0
T1	103166	103111	0	0
T2	68779	68728	0	0
T3	212795	212744	0	0
T4	180992	180930	0	0
T11	130451	130396	0	0
T22	115208	115153	0	0
T24	219043	218988	0	0
T31	97041	96935	0	0
T39	225028	224911	0	0
T97	78718	78656	0	0