Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_spi_device.u_reg.u_socket.fifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00		100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	75.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.27	94.12	89.29	99.75		100.00	68.18	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
reqfifo	100.00	100.00					100.00
rspfifo	75.00	50.00					100.00

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00		100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.27	94.12	89.29	99.75		100.00	68.18	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
reqfifo	100.00	100.00					100.00
rspfifo	100.00	100.00					100.00

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00		100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.64	94.64	93.18			94.74	100.00	u_socket

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
reqfifo	100.00	100.00					100.00
rspfifo	100.00	100.00					100.00

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00		100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.64	94.64	93.18			94.74	100.00	u_socket

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
reqfifo	100.00	100.00					100.00
rspfifo	100.00	100.00					100.00

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00		100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.64	94.64	93.18			94.74	100.00	u_socket

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
reqfifo	100.00	100.00					100.00
rspfifo	100.00	100.00					100.00

Go back
Module Instances:
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i

	Total	Covered	Percent
Conditions	4	4	100.00
Logical	4	4	100.00
Non-Logical	0	0
Event	0	0

 LINE       66
 SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
                 -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       66
 SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
                -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	66	2	2	100.00



66           prim_fifo_sync #(.Width(RSPFIFO_WIDTH), .Pass(RspPass), .Depth(RspDepth)) rspfifo (
                                                                                                
67             .clk_i,
                      
68             .rst_ni,
                       
69             .clr_i         (1'b0          ),
                                               
70             .wvalid_i      (tl_d_i.d_valid),
                                               
71             .wready_o      (tl_d_o.d_ready),
                                               
72             .wdata_i       ({tl_d_i.d_opcode,
                                                
73                              tl_d_i.d_param ,
                                                
74                              tl_d_i.d_size  ,
                                                
75                              tl_d_i.d_source,
                                                
76                              tl_d_i.d_sink  ,
                                                
77                              (tl_d_i.d_opcode == tlul_pkg::AccessAckData) ? tl_d_i.d_data :
                                                                             -1-  
                                                                             ==>  
                                                                             ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d

	Total	Covered	Percent
Conditions	4	4	100.00
Logical	4	4	100.00
Non-Logical	0	0
Event	0	0

 LINE       66
 SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
                 -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       66
 SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
                -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	66	2	2	100.00



66           prim_fifo_sync #(.Width(RSPFIFO_WIDTH), .Pass(RspPass), .Depth(RspDepth)) rspfifo (
                                                                                                
67             .clk_i,
                      
68             .rst_ni,
                       
69             .clr_i         (1'b0          ),
                                               
70             .wvalid_i      (tl_d_i.d_valid),
                                               
71             .wready_o      (tl_d_o.d_ready),
                                               
72             .wdata_i       ({tl_d_i.d_opcode,
                                                
73                              tl_d_i.d_param ,
                                                
74                              tl_d_i.d_size  ,
                                                
75                              tl_d_i.d_source,
                                                
76                              tl_d_i.d_sink  ,
                                                
77                              (tl_d_i.d_opcode == tlul_pkg::AccessAckData) ? tl_d_i.d_data :
                                                                             -1-  
                                                                             ==>  
                                                                             ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h

	Total	Covered	Percent
Conditions	4	4	100.00
Logical	4	4	100.00
Non-Logical	0	0
Event	0	0

 LINE       66
 SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
                 -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       66
 SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
                -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	66	2	2	100.00



66           prim_fifo_sync #(.Width(RSPFIFO_WIDTH), .Pass(RspPass), .Depth(RspDepth)) rspfifo (
                                                                                                
67             .clk_i,
                      
68             .rst_ni,
                       
69             .clr_i         (1'b0          ),
                                               
70             .wvalid_i      (tl_d_i.d_valid),
                                               
71             .wready_o      (tl_d_o.d_ready),
                                               
72             .wdata_i       ({tl_d_i.d_opcode,
                                                
73                              tl_d_i.d_param ,
                                                
74                              tl_d_i.d_size  ,
                                                
75                              tl_d_i.d_source,
                                                
76                              tl_d_i.d_sink  ,
                                                
77                              (tl_d_i.d_opcode == tlul_pkg::AccessAckData) ? tl_d_i.d_data :
                                                                             -1-  
                                                                             ==>  
                                                                             ==>

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d

	Total	Covered	Percent
Conditions	4	4	100.00
Logical	4	4	100.00
Non-Logical	0	0
Event	0	0

 LINE       66
 SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
                 -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T39,T95,T96

 LINE       66
 SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
                -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T39,T95,T96

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	66	2	2	100.00



66           prim_fifo_sync #(.Width(RSPFIFO_WIDTH), .Pass(RspPass), .Depth(RspDepth)) rspfifo (
                                                                                                
67             .clk_i,
                      
68             .rst_ni,
                       
69             .clr_i         (1'b0          ),
                                               
70             .wvalid_i      (tl_d_i.d_valid),
                                               
71             .wready_o      (tl_d_o.d_ready),
                                               
72             .wdata_i       ({tl_d_i.d_opcode,
                                                
73                              tl_d_i.d_param ,
                                                
74                              tl_d_i.d_size  ,
                                                
75                              tl_d_i.d_source,
                                                
76                              tl_d_i.d_sink  ,
                                                
77                              (tl_d_i.d_opcode == tlul_pkg::AccessAckData) ? tl_d_i.d_data :
                                                                             -1-  
                                                                             ==>  
                                                                             ==>

Branches:

-1-	Status	Tests
1	Covered	T39,T95,T96
0	Covered	T1,T2,T3

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d

	Total	Covered	Percent
Conditions	4	4	100.00
Logical	4	4	100.00
Non-Logical	0	0
Event	0	0

 LINE       66
 SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
                 -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       66
 SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
                -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	66	2	2	100.00



66           prim_fifo_sync #(.Width(RSPFIFO_WIDTH), .Pass(RspPass), .Depth(RspDepth)) rspfifo (
                                                                                                
67             .clk_i,
                      
68             .rst_ni,
                       
69             .clr_i         (1'b0          ),
                                               
70             .wvalid_i      (tl_d_i.d_valid),
                                               
71             .wready_o      (tl_d_o.d_ready),
                                               
72             .wdata_i       ({tl_d_i.d_opcode,
                                                
73                              tl_d_i.d_param ,
                                                
74                              tl_d_i.d_size  ,
                                                
75                              tl_d_i.d_source,
                                                
76                              tl_d_i.d_sink  ,
                                                
77                              (tl_d_i.d_opcode == tlul_pkg::AccessAckData) ? tl_d_i.d_data :
                                                                             -1-  
                                                                             ==>  
                                                                             ==>

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3