Unified Coverage Report :: Group :: tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	3698858	1			T91	118		T92	107		T93	1935
values[2]	743296	1			T91	49		T92	39		T93	442
values[3]	114124	1			T93	1		T409	22		T475	3
values[4]	61273	1			T409	23		T473	54		T850	57
values[5]	40435	1			T409	29		T473	42		T850	17
values[6]	29928	1			T409	15		T473	45		T850	9
values[7]	23858	1			T409	8		T473	34		T850	8
values[8]	20173	1			T409	28		T473	45		T850	1
values[9]	17705	1			T409	24		T473	43		T827	2
values[10]	15807	1			T409	17		T473	51		T827	1
values[11]	14321	1			T409	16		T473	40		T827	2
values[12]	13842	1			T409	33		T473	35		T827	2
values[13]	13087	1			T409	35		T473	40		T827	1
values[14]	12382	1			T409	27		T473	41		T827	3
values[15]	11987	1			T409	22		T473	51		T827	7
values[16]	11523	1			T409	28		T473	43		T827	5
values[17]	11065	1			T409	34		T473	50		T827	7
values[18]	10822	1			T409	19		T473	25		T827	10
values[19]	10323	1			T409	29		T473	37		T827	1
values[20]	10116	1			T409	22		T473	37		T827	2
values[21]	9880	1			T409	15		T473	42		T827	8
values[22]	9430	1			T409	14		T473	50		T827	11
values[23]	9028	1			T409	18		T473	28		T827	5
values[24]	8618	1			T409	19		T473	21		T827	4
values[25]	8457	1			T409	8		T473	25		T827	6
values[26]	8095	1			T409	18		T473	22		T827	12
values[27]	7812	1			T409	11		T473	14		T827	4
values[28]	7435	1			T409	5		T473	13		T827	4
values[29]	6969	1			T409	2		T473	21		T827	2
values[30]	6295	1			T409	7		T473	16		T827	4
values[31]	5962	1			T409	5		T473	15		T827	3
values[32]	5531	1			T409	5		T473	14		T827	5
values[33]	5310	1			T409	7		T473	15		T827	4
values[34]	4912	1			T409	7		T473	19		T827	7
values[35]	4468	1			T409	18		T473	28		T827	7
values[36]	4268	1			T409	19		T473	19		T690	1
values[37]	4050	1			T409	5		T473	16		T690	1
values[38]	3834	1			T409	1		T473	6		T690	1
values[39]	3654	1			T409	7		T473	7		T690	1
values[40]	3505	1			T409	1		T473	3		T690	2
values[41]	3418	1			T409	1		T473	2		T690	1
values[42]	3359	1			T409	2		T473	2		T690	1
values[43]	3352	1			T409	2		T473	4		T690	1
values[44]	3323	1			T409	2		T473	3		T690	3
values[45]	3145	1			T409	2		T473	2		T690	2
values[46]	3164	1			T409	7		T473	3		T690	4
values[47]	3092	1			T409	3		T473	1		T690	10
values[48]	3013	1			T409	1		T473	5		T690	4
values[49]	2938	1			T409	2		T473	2		T690	7
values[50]	2826	1			T409	5		T473	5		T690	6
values[51]	2850	1			T409	4		T473	4		T690	3
values[52]	2783	1			T409	2		T473	12		T690	5
values[53]	2725	1			T409	6		T473	6		T690	2
values[54]	2640	1			T409	3		T690	2		T461	2
values[55]	2559	1			T409	2		T690	2		T461	2
values[56]	2516	1			T690	1		T461	2		T488	4
values[57]	2437	1			T690	1		T461	2		T488	5
values[58]	2479	1			T690	2		T461	2		T488	4
values[59]	2544	1			T690	3		T461	2		T488	3
values[60]	2485	1			T690	2		T461	2		T488	6
values[61]	2912	1			T690	2		T461	2		T488	6
values[62]	4317	1			T690	3		T461	2		T488	7
values[63]	11744	1			T690	28		T461	2		T488	17
values[64]	218898	1			T690	81		T461	164		T488	86

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	4772351	1			T91	95		T92	142		T93	1753
values[2]	813352	1			T91	23		T92	38		T93	419
values[3]	85792	1			T91	2		T92	2		T93	8
values[4]	15143	1			T93	1		T445	2		T475	1
values[5]	5970	1			T567	2		T574	1		T690	2
values[6]	3434	1			T690	1		T461	2		T488	4
values[7]	2597	1			T690	4		T461	2		T488	7
values[8]	2213	1			T690	2		T461	2		T488	7
values[9]	1982	1			T690	1		T461	2		T488	16
values[10]	1675	1			T690	1		T461	2		T488	16
values[11]	1567	1			T690	1		T461	2		T488	3
values[12]	1472	1			T690	1		T461	2		T488	1
values[13]	1398	1			T690	3		T461	2		T488	2
values[14]	1312	1			T690	1		T461	2		T488	4
values[15]	1204	1			T690	1		T461	2		T488	5
values[16]	1173	1			T690	1		T461	2		T488	6
values[17]	1103	1			T690	1		T461	2		T488	7
values[18]	1146	1			T690	1		T461	2		T488	8
values[19]	1117	1			T690	5		T461	2		T488	3
values[20]	977	1			T690	13		T461	2		T488	6
values[21]	1004	1			T690	3		T461	3		T488	5
values[22]	952	1			T690	1		T461	2		T488	1
values[23]	872	1			T690	4		T461	2		T488	1
values[24]	771	1			T690	1		T461	2		T488	2
values[25]	739	1			T690	1		T461	2		T488	6
values[26]	710	1			T690	1		T461	2		T488	8
values[27]	684	1			T690	2		T461	2		T488	7
values[28]	582	1			T690	5		T461	2		T488	7
values[29]	597	1			T690	1		T461	2		T488	18
values[30]	556	1			T690	1		T461	2		T488	6
values[31]	541	1			T690	1		T461	3		T488	4
values[32]	548	1			T690	1		T461	2		T636	1
values[33]	531	1			T690	4		T461	2		T636	2
values[34]	500	1			T690	4		T461	2		T636	2
values[35]	507	1			T690	2		T461	2		T636	2
values[36]	487	1			T690	1		T461	2		T636	4
values[37]	516	1			T690	1		T461	2		T636	2
values[38]	510	1			T690	1		T461	2		T636	2
values[39]	440	1			T690	1		T461	2		T636	3
values[40]	436	1			T690	1		T461	2		T636	2
values[41]	448	1			T690	1		T461	2		T636	2
values[42]	436	1			T690	1		T461	2		T636	2
values[43]	454	1			T690	2		T461	2		T636	1
values[44]	449	1			T690	2		T461	2		T636	1
values[45]	445	1			T690	1		T461	2		T636	2
values[46]	429	1			T690	1		T461	2		T636	1
values[47]	407	1			T690	1		T461	2		T636	1
values[48]	425	1			T690	1		T461	2		T636	1
values[49]	413	1			T690	2		T461	2		T636	3
values[50]	378	1			T690	1		T461	2		T636	1
values[51]	417	1			T690	1		T461	2		T636	3
values[52]	380	1			T690	1		T461	1		T636	3
values[53]	366	1			T690	2		T461	1		T636	3
values[54]	367	1			T690	1		T461	2		T636	3
values[55]	386	1			T690	3		T461	2		T636	5
values[56]	377	1			T690	1		T461	2		T636	7
values[57]	378	1			T690	1		T461	2		T636	3
values[58]	334	1			T690	1		T461	2		T636	2
values[59]	330	1			T690	1		T461	2		T636	2
values[60]	335	1			T690	1		T461	2		T636	6
values[61]	371	1			T690	1		T461	2		T636	3
values[62]	618	1			T690	9		T461	2		T636	6
values[63]	2423	1			T690	26		T461	3		T636	42
values[64]	24480	1			T690	64		T461	88		T636	80

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	555092	1			T91	1		T92	1		T93	15
values[2]	2645706	1			T91	92		T92	102		T93	1879
values[3]	1187442	1			T91	44		T92	25		T93	494
values[4]	155043	1			T409	18		T475	1		T274	7
values[5]	80029	1			T409	20		T473	32		T560	1
values[6]	52144	1			T409	25		T473	43		T850	30
values[7]	37954	1			T409	33		T473	70		T850	24
values[8]	29855	1			T409	35		T473	45		T850	42
values[9]	25338	1			T409	33		T473	23		T850	16
values[10]	22123	1			T409	17		T473	46		T850	14
values[11]	19980	1			T409	19		T473	50		T850	19
values[12]	18216	1			T409	14		T473	38		T850	3
values[13]	16628	1			T409	21		T473	30		T850	7
values[14]	15400	1			T409	14		T473	50		T850	6
values[15]	14566	1			T409	21		T473	52		T850	3
values[16]	13926	1			T409	35		T473	52		T850	1
values[17]	13391	1			T409	31		T473	34		T827	5
values[18]	12796	1			T409	16		T473	37		T827	6
values[19]	12128	1			T409	7		T473	31		T827	2
values[20]	11652	1			T409	27		T473	37		T827	1
values[21]	11347	1			T409	32		T473	29		T827	1
values[22]	10885	1			T409	15		T473	45		T827	1
values[23]	10476	1			T409	13		T473	34		T827	5
values[24]	10277	1			T409	22		T473	53		T827	2
values[25]	9638	1			T409	21		T473	50		T827	3
values[26]	9411	1			T409	13		T473	29		T827	1
values[27]	8806	1			T409	14		T473	46		T827	2
values[28]	8054	1			T409	8		T473	43		T827	5
values[29]	7617	1			T409	20		T473	30		T827	14
values[30]	7053	1			T409	34		T473	19		T827	10
values[31]	6620	1			T409	36		T473	19		T827	18
values[32]	6101	1			T409	11		T473	13		T827	19
values[33]	5698	1			T409	6		T473	8		T827	10
values[34]	5525	1			T409	2		T473	12		T827	3
values[35]	5052	1			T409	7		T473	16		T690	2
values[36]	4791	1			T409	6		T473	3		T690	1
values[37]	4524	1			T409	4		T473	7		T690	1
values[38]	4286	1			T409	7		T473	10		T690	1
values[39]	4168	1			T409	8		T473	11		T690	3
values[40]	4081	1			T409	7		T473	8		T690	1
values[41]	3847	1			T409	6		T473	3		T690	3
values[42]	3753	1			T409	1		T473	7		T690	3
values[43]	3683	1			T409	3		T473	9		T690	1
values[44]	3601	1			T473	10		T690	2		T488	4
values[45]	3483	1			T473	10		T690	1		T488	2
values[46]	3482	1			T473	4		T690	2		T488	2
values[47]	3423	1			T473	10		T690	1		T488	3
values[48]	3300	1			T473	2		T690	1		T488	10
values[49]	3233	1			T473	5		T690	1		T488	11
values[50]	3271	1			T473	1		T690	1		T488	9
values[51]	3121	1			T690	1		T488	8		T499	8
values[52]	3134	1			T690	2		T488	4		T499	10
values[53]	3073	1			T690	4		T499	5		T809	1
values[54]	2980	1			T690	3		T499	3		T809	1
values[55]	2955	1			T690	2		T499	1		T809	1
values[56]	2923	1			T690	1		T499	1		T809	1
values[57]	2913	1			T690	3		T499	1		T809	1
values[58]	2831	1			T690	4		T809	1		T636	12
values[59]	2733	1			T690	3		T809	1		T636	18
values[60]	2753	1			T690	1		T809	1		T636	22
values[61]	2860	1			T690	1		T809	1		T636	19
values[62]	3705	1			T690	2		T809	1		T636	20
values[63]	9102	1			T690	20		T809	2		T636	77
values[64]	208863	1			T690	67		T809	197		T636	312