Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2045908	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

37197224

1

T1

350

T2

8310

T3

12121

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	26983766	1			T1	175		T2	3623		T3	6948
values[0x0]	10747785	1			T1	175		T2	4687		T3	5173
values[0x1]	1511581	1			T1	3		T2	499		T3	1378

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	680135	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

38562997

1

T1

353

T2

8809

T3

13499

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	18427337	1			T1	177		T2	4405		T3	6750
valid_sources[0x01]	18426145	1			T1	176		T2	4404		T3	6749
valid_sources[0x02]	41932	1			T163	75		T900	19		T901	25
valid_sources[0x03]	38190	1			T96	1		T415	41		T163	83
valid_sources[0x04]	38148	1			T96	1		T163	106		T900	13
valid_sources[0x05]	39088	1			T163	47		T900	5		T164	75
valid_sources[0x06]	36827	1			T227	1		T163	89		T900	34
valid_sources[0x07]	40748	1			T226	3		T163	106		T900	8
valid_sources[0x08]	38359	1			T96	1		T415	1		T163	87
valid_sources[0x09]	38555	1			T96	4		T163	80		T900	6
valid_sources[0x0a]	38486	1			T227	2		T163	64		T164	66
valid_sources[0x0b]	38365	1			T226	8		T227	3		T163	108
valid_sources[0x0c]	42903	1			T163	99		T900	3		T164	69
valid_sources[0x0d]	38772	1			T163	60		T900	4		T901	14
valid_sources[0x0e]	38714	1			T227	2		T163	38		T900	8
valid_sources[0x0f]	38944	1			T96	2		T163	88		T900	23
valid_sources[0x10]	38628	1			T96	1		T163	78		T900	19
valid_sources[0x11]	38387	1			T95	39		T227	1		T415	1
valid_sources[0x12]	38547	1			T415	2		T163	71		T900	7
valid_sources[0x13]	38711	1			T163	65		T900	13		T901	11
valid_sources[0x14]	38336	1			T226	1		T227	2		T163	92
valid_sources[0x15]	38111	1			T226	4		T227	2		T415	3
valid_sources[0x16]	37939	1			T36	11		T163	65		T900	11
valid_sources[0x17]	38612	1			T163	89		T900	3		T164	84
valid_sources[0x18]	38484	1			T227	1		T415	1		T163	77
valid_sources[0x19]	38478	1			T226	17		T163	77		T900	18
valid_sources[0x1a]	38303	1			T415	2		T163	100		T900	4
valid_sources[0x1b]	38168	1			T96	1		T226	3		T163	86
valid_sources[0x1c]	38297	1			T96	4		T227	1		T415	3
valid_sources[0x1d]	38973	1			T227	4		T415	3		T163	106
valid_sources[0x1e]	37898	1			T163	78		T900	3		T901	2
valid_sources[0x1f]	38044	1			T227	1		T163	63		T901	8
valid_sources[0x20]	38374	1			T415	1		T163	74		T900	11

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26247204

1

T1

175

T2

3623

T3

6948

values[0x0]

all_enables

biggest_size

10687332

1

T1

175

T2

4687

T3

5173

values[0x1]

all_enables

biggest_size

262688

1

T36

19

T95

19

T96

22

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2692419	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

424071

1

T91

27

T92

18

T93

336

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1057204	1			T91	47		T92	58		T93	774
values[0x0]	1001624	1			T91	60		T92	45		T93	822
values[0x1]	1057662	1			T91	60		T92	43		T93	782

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2083881	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1032609

1

T91

56

T92

50

T93

780

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	48937	1			T91	2		T93	20		T97	8
valid_sources[0x01]	48538	1			T91	3		T92	1		T93	39
valid_sources[0x02]	48200	1			T91	10		T92	4		T93	61
valid_sources[0x03]	48116	1			T91	1		T92	2		T93	38
valid_sources[0x04]	47400	1			T91	4		T92	2		T93	64
valid_sources[0x05]	49151	1			T91	3		T92	2		T93	44
valid_sources[0x06]	48537	1			T92	2		T93	29		T409	15
valid_sources[0x07]	48840	1			T91	1		T92	3		T93	46
valid_sources[0x08]	49235	1			T91	3		T93	40		T97	2
valid_sources[0x09]	49403	1			T91	5		T92	2		T93	58
valid_sources[0x0a]	47881	1			T91	2		T92	3		T93	28
valid_sources[0x0b]	48579	1			T91	11		T92	1		T93	31
valid_sources[0x0c]	49144	1			T91	1		T93	40		T97	7
valid_sources[0x0d]	48607	1			T91	3		T92	1		T93	50
valid_sources[0x0e]	48758	1			T91	2		T92	3		T93	58
valid_sources[0x0f]	49307	1			T91	3		T92	2		T93	23
valid_sources[0x10]	48115	1			T91	16		T92	1		T93	10
valid_sources[0x11]	48190	1			T92	1		T93	46		T97	10
valid_sources[0x12]	49211	1			T92	4		T93	27		T97	2
valid_sources[0x13]	48479	1			T92	2		T93	39		T97	5
valid_sources[0x14]	49284	1			T92	3		T93	6		T97	11
valid_sources[0x15]	48918	1			T91	1		T92	1		T93	41
valid_sources[0x16]	48739	1			T91	1		T92	1		T93	85
valid_sources[0x17]	49203	1			T92	4		T93	38		T409	14
valid_sources[0x18]	47865	1			T92	5		T93	44		T180	1
valid_sources[0x19]	49734	1			T91	4		T92	1		T93	32
valid_sources[0x1a]	49307	1			T91	1		T93	24		T97	1
valid_sources[0x1b]	49220	1			T91	6		T92	1		T93	7
valid_sources[0x1c]	49704	1			T91	1		T92	4		T93	40
valid_sources[0x1d]	48820	1			T92	3		T93	20		T97	5
valid_sources[0x1e]	47978	1			T91	1		T92	2		T93	14
valid_sources[0x1f]	48623	1			T92	2		T93	34		T97	5
valid_sources[0x20]	48840	1			T92	4		T93	47		T97	11

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

44776

1

T91

4

T92

3

T93

31

values[0x0]

all_enables

biggest_size

334313

1

T91

16

T92

13

T93

277

values[0x1]

all_enables

biggest_size

44982

1

T91

7

T92

2

T93

28

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2889642	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

469934

1

T91

12

T92

17

T93

293

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1151245	1			T91	42		T92	59		T93	763
values[0x0]	1056317	1			T91	36		T92	58		T93	684
values[0x1]	1152014	1			T91	42		T92	65		T93	734

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2216526	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1143050

1

T91

32

T92

50

T93

748

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	52927	1			T92	14		T93	38		T97	8
valid_sources[0x01]	52610	1			T91	6		T93	34		T97	5
valid_sources[0x02]	53135	1			T91	1		T93	19		T97	11
valid_sources[0x03]	53005	1			T91	3		T92	8		T93	26
valid_sources[0x04]	52637	1			T91	1		T92	4		T93	39
valid_sources[0x05]	53857	1			T91	2		T92	2		T93	32
valid_sources[0x06]	52176	1			T91	3		T92	4		T93	30
valid_sources[0x07]	52553	1			T92	10		T93	33		T97	2
valid_sources[0x08]	52614	1			T91	2		T93	24		T97	2
valid_sources[0x09]	53123	1			T93	41		T97	12		T180	3
valid_sources[0x0a]	51898	1			T91	4		T93	36		T97	2
valid_sources[0x0b]	53187	1			T91	2		T92	7		T93	38
valid_sources[0x0c]	53844	1			T91	1		T93	33		T97	9
valid_sources[0x0d]	52033	1			T93	36		T97	2		T180	2
valid_sources[0x0e]	51511	1			T91	2		T92	7		T93	30
valid_sources[0x0f]	53286	1			T91	6		T92	6		T93	31
valid_sources[0x10]	52137	1			T91	1		T93	27		T97	8
valid_sources[0x11]	52788	1			T91	7		T92	3		T93	36
valid_sources[0x12]	51745	1			T91	1		T93	43		T180	7
valid_sources[0x13]	52317	1			T91	3		T93	28		T97	4
valid_sources[0x14]	52709	1			T91	2		T92	8		T93	31
valid_sources[0x15]	52617	1			T93	29		T97	2		T180	4
valid_sources[0x16]	53336	1			T91	2		T92	11		T93	27
valid_sources[0x17]	52079	1			T91	2		T92	2		T93	36
valid_sources[0x18]	52090	1			T92	2		T93	41		T97	3
valid_sources[0x19]	52403	1			T91	1		T93	31		T97	4
valid_sources[0x1a]	52392	1			T91	1		T93	41		T97	4
valid_sources[0x1b]	52119	1			T93	31		T97	2		T180	7
valid_sources[0x1c]	52285	1			T91	1		T93	26		T97	4
valid_sources[0x1d]	52424	1			T91	2		T92	15		T93	27
valid_sources[0x1e]	52358	1			T91	2		T93	26		T97	5
valid_sources[0x1f]	52384	1			T93	32		T97	4		T180	4
valid_sources[0x20]	52303	1			T91	2		T93	33		T97	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

49337

1

T91

2

T92

2

T93

28

values[0x0]

all_enables

biggest_size

371095

1

T91

9

T92

13

T93

228

values[0x1]

all_enables

biggest_size

49502

1

T91

1

T92

2

T93

37

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2720538	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

429248

1

T91

23

T92

17

T93

321

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1069131	1			T91	45		T92	46		T93	807
values[0x0]	1013232	1			T91	43		T92	39		T93	764
values[0x1]	1067423	1			T91	49		T92	43		T93	817

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2105408	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1044378

1

T91

47

T92

42

T93

762

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	50119	1			T91	16		T93	38		T97	6
valid_sources[0x01]	48904	1			T92	2		T93	37		T97	1
valid_sources[0x02]	48228	1			T92	1		T93	47		T180	1
valid_sources[0x03]	49840	1			T92	2		T93	37		T97	25
valid_sources[0x04]	49444	1			T93	40		T180	3		T175	2
valid_sources[0x05]	50214	1			T91	16		T93	44		T97	9
valid_sources[0x06]	48812	1			T92	4		T93	56		T180	6
valid_sources[0x07]	49406	1			T93	48		T97	4		T180	3
valid_sources[0x08]	49462	1			T93	45		T97	1		T180	2
valid_sources[0x09]	49745	1			T91	3		T92	1		T93	35
valid_sources[0x0a]	48529	1			T91	4		T93	28		T175	5
valid_sources[0x0b]	49859	1			T92	8		T93	48		T180	3
valid_sources[0x0c]	49705	1			T91	1		T93	31		T180	4
valid_sources[0x0d]	48452	1			T92	2		T93	40		T97	6
valid_sources[0x0e]	47995	1			T92	8		T93	38		T97	4
valid_sources[0x0f]	49091	1			T93	44		T97	6		T180	1
valid_sources[0x10]	48960	1			T93	38		T180	2		T175	1
valid_sources[0x11]	49872	1			T93	38		T97	10		T180	3
valid_sources[0x12]	48410	1			T91	10		T92	3		T93	52
valid_sources[0x13]	48968	1			T93	36		T97	1		T180	1
valid_sources[0x14]	49306	1			T91	2		T93	45		T97	2
valid_sources[0x15]	48692	1			T92	4		T93	34		T175	4
valid_sources[0x16]	49368	1			T91	10		T93	34		T97	8
valid_sources[0x17]	49071	1			T91	4		T92	3		T93	43
valid_sources[0x18]	49792	1			T91	2		T92	4		T93	33
valid_sources[0x19]	49079	1			T92	1		T93	39		T180	5
valid_sources[0x1a]	49067	1			T91	14		T92	5		T93	38
valid_sources[0x1b]	49778	1			T93	35		T97	25		T180	1
valid_sources[0x1c]	50782	1			T92	4		T93	35		T97	10
valid_sources[0x1d]	48635	1			T91	3		T92	4		T93	29
valid_sources[0x1e]	49353	1			T93	31		T97	1		T175	2
valid_sources[0x1f]	48812	1			T92	1		T93	32		T97	6
valid_sources[0x20]	49030	1			T93	36		T97	14		T180	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

45237

1

T91

7

T92

2

T93

39

values[0x0]

all_enables

biggest_size

338609

1

T91

11

T92

11

T93

248

values[0x1]

all_enables

biggest_size

45402

1

T91

5

T92

4

T93

34