Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	514105209	62400993	0	0
DataKnown_AKnownEnable	514105209	513999283	0	0
DepthKnown_A	514105209	513999283	0	0
RvalidKnown_A	514105209	513999283	0	0
WreadyKnown_A	514105209	513999283	0	0
gen_passthru_fifo.paramCheckPass	1021	1021	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514105209	62400993	0	0
T1	42217	3485	0	0
T2	107343	12100	0	0
T3	196310	22526	0	0
T4	80296	9699	0	0
T5	81563	11322	0	0
T6	90509	11139	0	0
T8	108887	12510	0	0
T65	87507	9843	0	0
T103	73424	7369	0	0
T104	59868	5604	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	514105209	513999283	0	0
T1	42217	42155	0	0
T2	107343	107288	0	0
T3	196310	196252	0	0
T4	80296	80245	0	0
T5	81563	81508	0	0
T6	90509	90447	0	0
T8	108887	108829	0	0
T65	87507	87445	0	0
T103	73424	73362	0	0
T104	59868	59806	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514105209	513999283	0	0
T1	42217	42155	0	0
T2	107343	107288	0	0
T3	196310	196252	0	0
T4	80296	80245	0	0
T5	81563	81508	0	0
T6	90509	90447	0	0
T8	108887	108829	0	0
T65	87507	87445	0	0
T103	73424	73362	0	0
T104	59868	59806	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514105209	513999283	0	0
T1	42217	42155	0	0
T2	107343	107288	0	0
T3	196310	196252	0	0
T4	80296	80245	0	0
T5	81563	81508	0	0
T6	90509	90447	0	0
T8	108887	108829	0	0
T65	87507	87445	0	0
T103	73424	73362	0	0
T104	59868	59806	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514105209	513999283	0	0
T1	42217	42155	0	0
T2	107343	107288	0	0
T3	196310	196252	0	0
T4	80296	80245	0	0
T5	81563	81508	0	0
T6	90509	90447	0	0
T8	108887	108829	0	0
T65	87507	87445	0	0
T103	73424	73362	0	0
T104	59868	59806	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1021	1021	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T65	1	1	0	0
T103	1	1	0	0
T104	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         0/1     ==>      assign wready_o = rready_i;
49         0/1     ==>      assign full_o = rready_i;
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	514105209	47303506	0	0
DataKnown_AKnownEnable	514105209	513999283	0	0
DepthKnown_A	514105209	513999283	0	0
RvalidKnown_A	514105209	513999283	0	0
WreadyKnown_A	514105209	513999283	0	0
gen_passthru_fifo.paramCheckPass	1021	1021	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514105209	47303506	0	0
T1	42217	1880	0	0
T2	107343	9444	0	0
T3	196310	19660	0	0
T4	80296	6960	0	0
T5	81563	7080	0	0
T6	90509	8330	0	0
T8	108887	10089	0	0
T65	87507	7713	0	0
T103	73424	5699	0	0
T104	59868	3929	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	514105209	513999283	0	0
T1	42217	42155	0	0
T2	107343	107288	0	0
T3	196310	196252	0	0
T4	80296	80245	0	0
T5	81563	81508	0	0
T6	90509	90447	0	0
T8	108887	108829	0	0
T65	87507	87445	0	0
T103	73424	73362	0	0
T104	59868	59806	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514105209	513999283	0	0
T1	42217	42155	0	0
T2	107343	107288	0	0
T3	196310	196252	0	0
T4	80296	80245	0	0
T5	81563	81508	0	0
T6	90509	90447	0	0
T8	108887	108829	0	0
T65	87507	87445	0	0
T103	73424	73362	0	0
T104	59868	59806	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514105209	513999283	0	0
T1	42217	42155	0	0
T2	107343	107288	0	0
T3	196310	196252	0	0
T4	80296	80245	0	0
T5	81563	81508	0	0
T6	90509	90447	0	0
T8	108887	108829	0	0
T65	87507	87445	0	0
T103	73424	73362	0	0
T104	59868	59806	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514105209	513999283	0	0
T1	42217	42155	0	0
T2	107343	107288	0	0
T3	196310	196252	0	0
T4	80296	80245	0	0
T5	81563	81508	0	0
T6	90509	90447	0	0
T8	108887	108829	0	0
T65	87507	87445	0	0
T103	73424	73362	0	0
T104	59868	59806	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1021	1021	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T65	1	1	0	0
T103	1	1	0	0
T104	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	514105209	44088107	0	0
DataKnown_AKnownEnable	514105209	513999283	0	0
DepthKnown_A	514105209	513999283	0	0
RvalidKnown_A	514105209	513999283	0	0
WreadyKnown_A	514105209	513999283	0	0
gen_passthru_fifo.paramCheckPass	1021	1021	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514105209	44088107	0	0
T1	42217	461	0	0
T2	107343	9268	0	0
T3	196310	13629	0	0
T4	80296	6794	0	0
T5	81563	4583	0	0
T6	90509	5930	0	0
T8	108887	6522	0	0
T65	87507	5658	0	0
T103	73424	4524	0	0
T104	59868	3235	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	514105209	513999283	0	0
T1	42217	42155	0	0
T2	107343	107288	0	0
T3	196310	196252	0	0
T4	80296	80245	0	0
T5	81563	81508	0	0
T6	90509	90447	0	0
T8	108887	108829	0	0
T65	87507	87445	0	0
T103	73424	73362	0	0
T104	59868	59806	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514105209	513999283	0	0
T1	42217	42155	0	0
T2	107343	107288	0	0
T3	196310	196252	0	0
T4	80296	80245	0	0
T5	81563	81508	0	0
T6	90509	90447	0	0
T8	108887	108829	0	0
T65	87507	87445	0	0
T103	73424	73362	0	0
T104	59868	59806	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514105209	513999283	0	0
T1	42217	42155	0	0
T2	107343	107288	0	0
T3	196310	196252	0	0
T4	80296	80245	0	0
T5	81563	81508	0	0
T6	90509	90447	0	0
T8	108887	108829	0	0
T65	87507	87445	0	0
T103	73424	73362	0	0
T104	59868	59806	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514105209	513999283	0	0
T1	42217	42155	0	0
T2	107343	107288	0	0
T3	196310	196252	0	0
T4	80296	80245	0	0
T5	81563	81508	0	0
T6	90509	90447	0	0
T8	108887	108829	0	0
T65	87507	87445	0	0
T103	73424	73362	0	0
T104	59868	59806	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1021	1021	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T65	1	1	0	0
T103	1	1	0	0
T104	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T36 T95 T96 
49         1/1              assign full_o = rready_i;
           Tests:       T36 T95 T96 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	514105209	36869525	0	0
DataKnown_AKnownEnable	514105209	513999283	0	0
DepthKnown_A	514105209	513999283	0	0
RvalidKnown_A	514105209	513999283	0	0
WreadyKnown_A	514105209	513999283	0	0
gen_passthru_fifo.paramCheckPass	1021	1021	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514105209	36869525	0	0
T1	42217	353	0	0
T2	107343	8809	0	0
T3	196310	13499	0	0
T4	80296	6198	0	0
T5	81563	4333	0	0
T6	90509	5758	0	0
T8	108887	6388	0	0
T65	87507	5531	0	0
T103	73424	4410	0	0
T104	59868	3122	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	514105209	513999283	0	0
T1	42217	42155	0	0
T2	107343	107288	0	0
T3	196310	196252	0	0
T4	80296	80245	0	0
T5	81563	81508	0	0
T6	90509	90447	0	0
T8	108887	108829	0	0
T65	87507	87445	0	0
T103	73424	73362	0	0
T104	59868	59806	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514105209	513999283	0	0
T1	42217	42155	0	0
T2	107343	107288	0	0
T3	196310	196252	0	0
T4	80296	80245	0	0
T5	81563	81508	0	0
T6	90509	90447	0	0
T8	108887	108829	0	0
T65	87507	87445	0	0
T103	73424	73362	0	0
T104	59868	59806	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514105209	513999283	0	0
T1	42217	42155	0	0
T2	107343	107288	0	0
T3	196310	196252	0	0
T4	80296	80245	0	0
T5	81563	81508	0	0
T6	90509	90447	0	0
T8	108887	108829	0	0
T65	87507	87445	0	0
T103	73424	73362	0	0
T104	59868	59806	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514105209	513999283	0	0
T1	42217	42155	0	0
T2	107343	107288	0	0
T3	196310	196252	0	0
T4	80296	80245	0	0
T5	81563	81508	0	0
T6	90509	90447	0	0
T8	108887	108829	0	0
T65	87507	87445	0	0
T103	73424	73362	0	0
T104	59868	59806	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1021	1021	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T65	1	1	0	0
T103	1	1	0	0
T104	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	602190799	80778	0	0
DataKnown_AKnownEnable	602190799	602068654	0	0
DepthKnown_A	602190799	602068654	0	0
RvalidKnown_A	602190799	602068654	0	0
WreadyKnown_A	602190799	602068654	0	0
gen_passthru_fifo.paramCheckPass	2931	2931	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	602190799	80778	0	0
T1	42217	8	0	0
T2	107343	208	0	0
T3	196310	13	0	0
T4	80296	34	0	0
T5	81563	25	0	0
T6	90509	24	0	0
T8	108887	13	0	0
T65	87507	13	0	0
T103	73424	13	0	0
T104	59868	13	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	602190799	602068654	0	0
T1	42217	42155	0	0
T2	107343	107288	0	0
T3	196310	196252	0	0
T4	80296	80245	0	0
T5	81563	81508	0	0
T6	90509	90447	0	0
T8	108887	108829	0	0
T65	87507	87445	0	0
T103	73424	73362	0	0
T104	59868	59806	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	602190799	602068654	0	0
T1	42217	42155	0	0
T2	107343	107288	0	0
T3	196310	196252	0	0
T4	80296	80245	0	0
T5	81563	81508	0	0
T6	90509	90447	0	0
T8	108887	108829	0	0
T65	87507	87445	0	0
T103	73424	73362	0	0
T104	59868	59806	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	602190799	602068654	0	0
T1	42217	42155	0	0
T2	107343	107288	0	0
T3	196310	196252	0	0
T4	80296	80245	0	0
T5	81563	81508	0	0
T6	90509	90447	0	0
T8	108887	108829	0	0
T65	87507	87445	0	0
T103	73424	73362	0	0
T104	59868	59806	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	602190799	602068654	0	0
T1	42217	42155	0	0
T2	107343	107288	0	0
T3	196310	196252	0	0
T4	80296	80245	0	0
T5	81563	81508	0	0
T6	90509	90447	0	0
T8	108887	108829	0	0
T65	87507	87445	0	0
T103	73424	73362	0	0
T104	59868	59806	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2931	2931	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T65	1	1	0	0
T103	1	1	0	0
T104	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	602190799	82331	0	0
DataKnown_AKnownEnable	602190799	602068654	0	0
DepthKnown_A	602190799	602068654	0	0
RvalidKnown_A	602190799	602068654	0	0
WreadyKnown_A	602190799	602068654	0	0
gen_passthru_fifo.paramCheckPass	2931	2931	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	602190799	82331	0	0
T1	42217	8	0	0
T2	107343	208	0	0
T3	196310	13	0	0
T4	80296	34	0	0
T5	81563	25	0	0
T6	90509	24	0	0
T8	108887	13	0	0
T65	87507	13	0	0
T103	73424	13	0	0
T104	59868	13	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	602190799	602068654	0	0
T1	42217	42155	0	0
T2	107343	107288	0	0
T3	196310	196252	0	0
T4	80296	80245	0	0
T5	81563	81508	0	0
T6	90509	90447	0	0
T8	108887	108829	0	0
T65	87507	87445	0	0
T103	73424	73362	0	0
T104	59868	59806	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	602190799	602068654	0	0
T1	42217	42155	0	0
T2	107343	107288	0	0
T3	196310	196252	0	0
T4	80296	80245	0	0
T5	81563	81508	0	0
T6	90509	90447	0	0
T8	108887	108829	0	0
T65	87507	87445	0	0
T103	73424	73362	0	0
T104	59868	59806	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	602190799	602068654	0	0
T1	42217	42155	0	0
T2	107343	107288	0	0
T3	196310	196252	0	0
T4	80296	80245	0	0
T5	81563	81508	0	0
T6	90509	90447	0	0
T8	108887	108829	0	0
T65	87507	87445	0	0
T103	73424	73362	0	0
T104	59868	59806	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	602190799	602068654	0	0
T1	42217	42155	0	0
T2	107343	107288	0	0
T3	196310	196252	0	0
T4	80296	80245	0	0
T5	81563	81508	0	0
T6	90509	90447	0	0
T8	108887	108829	0	0
T65	87507	87445	0	0
T103	73424	73362	0	0
T104	59868	59806	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2931	2931	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T65	1	1	0	0
T103	1	1	0	0
T104	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	602190799	50945	0	0
DataKnown_AKnownEnable	602190799	602068654	0	0
DepthKnown_A	602190799	602068654	0	0
RvalidKnown_A	602190799	602068654	0	0
WreadyKnown_A	602190799	602068654	0	0
gen_passthru_fifo.paramCheckPass	2931	2931	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	602190799	50945	0	0
T1	42217	8	0	0
T2	107343	205	0	0
T3	196310	12	0	0
T4	80296	33	0	0
T5	81563	22	0	0
T6	90509	21	0	0
T8	108887	12	0	0
T65	87507	12	0	0
T103	73424	12	0	0
T104	59868	12	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	602190799	602068654	0	0
T1	42217	42155	0	0
T2	107343	107288	0	0
T3	196310	196252	0	0
T4	80296	80245	0	0
T5	81563	81508	0	0
T6	90509	90447	0	0
T8	108887	108829	0	0
T65	87507	87445	0	0
T103	73424	73362	0	0
T104	59868	59806	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	602190799	602068654	0	0
T1	42217	42155	0	0
T2	107343	107288	0	0
T3	196310	196252	0	0
T4	80296	80245	0	0
T5	81563	81508	0	0
T6	90509	90447	0	0
T8	108887	108829	0	0
T65	87507	87445	0	0
T103	73424	73362	0	0
T104	59868	59806	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	602190799	602068654	0	0
T1	42217	42155	0	0
T2	107343	107288	0	0
T3	196310	196252	0	0
T4	80296	80245	0	0
T5	81563	81508	0	0
T6	90509	90447	0	0
T8	108887	108829	0	0
T65	87507	87445	0	0
T103	73424	73362	0	0
T104	59868	59806	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	602190799	602068654	0	0
T1	42217	42155	0	0
T2	107343	107288	0	0
T3	196310	196252	0	0
T4	80296	80245	0	0
T5	81563	81508	0	0
T6	90509	90447	0	0
T8	108887	108829	0	0
T65	87507	87445	0	0
T103	73424	73362	0	0
T104	59868	59806	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2931	2931	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T65	1	1	0	0
T103	1	1	0	0
T104	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	602190799	50943	0	0
DataKnown_AKnownEnable	602190799	602068654	0	0
DepthKnown_A	602190799	602068654	0	0
RvalidKnown_A	602190799	602068654	0	0
WreadyKnown_A	602190799	602068654	0	0
gen_passthru_fifo.paramCheckPass	2931	2931	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	602190799	50943	0	0
T1	42217	8	0	0
T2	107343	205	0	0
T3	196310	12	0	0
T4	80296	33	0	0
T5	81563	22	0	0
T6	90509	21	0	0
T8	108887	12	0	0
T65	87507	12	0	0
T103	73424	12	0	0
T104	59868	12	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	602190799	602068654	0	0
T1	42217	42155	0	0
T2	107343	107288	0	0
T3	196310	196252	0	0
T4	80296	80245	0	0
T5	81563	81508	0	0
T6	90509	90447	0	0
T8	108887	108829	0	0
T65	87507	87445	0	0
T103	73424	73362	0	0
T104	59868	59806	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	602190799	602068654	0	0
T1	42217	42155	0	0
T2	107343	107288	0	0
T3	196310	196252	0	0
T4	80296	80245	0	0
T5	81563	81508	0	0
T6	90509	90447	0	0
T8	108887	108829	0	0
T65	87507	87445	0	0
T103	73424	73362	0	0
T104	59868	59806	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	602190799	602068654	0	0
T1	42217	42155	0	0
T2	107343	107288	0	0
T3	196310	196252	0	0
T4	80296	80245	0	0
T5	81563	81508	0	0
T6	90509	90447	0	0
T8	108887	108829	0	0
T65	87507	87445	0	0
T103	73424	73362	0	0
T104	59868	59806	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	602190799	602068654	0	0
T1	42217	42155	0	0
T2	107343	107288	0	0
T3	196310	196252	0	0
T4	80296	80245	0	0
T5	81563	81508	0	0
T6	90509	90447	0	0
T8	108887	108829	0	0
T65	87507	87445	0	0
T103	73424	73362	0	0
T104	59868	59806	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2931	2931	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T65	1	1	0	0
T103	1	1	0	0
T104	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T2 T3 T4 
49         1/1              assign full_o = rready_i;
           Tests:       T2 T3 T4 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	602190799	29833	0	0
DataKnown_AKnownEnable	602190799	602068654	0	0
DepthKnown_A	602190799	602068654	0	0
RvalidKnown_A	602190799	602068654	0	0
WreadyKnown_A	602190799	602068654	0	0
gen_passthru_fifo.paramCheckPass	2931	2931	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	602190799	29833	0	0
T2	107343	3	0	0
T3	196310	1	0	0
T4	80296	1	0	0
T5	81563	3	0	0
T6	90509	3	0	0
T8	108887	1	0	0
T29	91829	3	0	0
T65	87507	1	0	0
T103	73424	1	0	0
T104	59868	1	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	602190799	602068654	0	0
T1	42217	42155	0	0
T2	107343	107288	0	0
T3	196310	196252	0	0
T4	80296	80245	0	0
T5	81563	81508	0	0
T6	90509	90447	0	0
T8	108887	108829	0	0
T65	87507	87445	0	0
T103	73424	73362	0	0
T104	59868	59806	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	602190799	602068654	0	0
T1	42217	42155	0	0
T2	107343	107288	0	0
T3	196310	196252	0	0
T4	80296	80245	0	0
T5	81563	81508	0	0
T6	90509	90447	0	0
T8	108887	108829	0	0
T65	87507	87445	0	0
T103	73424	73362	0	0
T104	59868	59806	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	602190799	602068654	0	0
T1	42217	42155	0	0
T2	107343	107288	0	0
T3	196310	196252	0	0
T4	80296	80245	0	0
T5	81563	81508	0	0
T6	90509	90447	0	0
T8	108887	108829	0	0
T65	87507	87445	0	0
T103	73424	73362	0	0
T104	59868	59806	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	602190799	602068654	0	0
T1	42217	42155	0	0
T2	107343	107288	0	0
T3	196310	196252	0	0
T4	80296	80245	0	0
T5	81563	81508	0	0
T6	90509	90447	0	0
T8	108887	108829	0	0
T65	87507	87445	0	0
T103	73424	73362	0	0
T104	59868	59806	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2931	2931	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T65	1	1	0	0
T103	1	1	0	0
T104	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T2 T3 T4 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T2 T3 T4 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	602190799	31388	0	0
DataKnown_AKnownEnable	602190799	602068654	0	0
DepthKnown_A	602190799	602068654	0	0
RvalidKnown_A	602190799	602068654	0	0
WreadyKnown_A	602190799	602068654	0	0
gen_passthru_fifo.paramCheckPass	2931	2931	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	602190799	31388	0	0
T2	107343	3	0	0
T3	196310	1	0	0
T4	80296	1	0	0
T5	81563	3	0	0
T6	90509	3	0	0
T8	108887	1	0	0
T29	91829	3	0	0
T65	87507	1	0	0
T103	73424	1	0	0
T104	59868	1	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	602190799	602068654	0	0
T1	42217	42155	0	0
T2	107343	107288	0	0
T3	196310	196252	0	0
T4	80296	80245	0	0
T5	81563	81508	0	0
T6	90509	90447	0	0
T8	108887	108829	0	0
T65	87507	87445	0	0
T103	73424	73362	0	0
T104	59868	59806	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	602190799	602068654	0	0
T1	42217	42155	0	0
T2	107343	107288	0	0
T3	196310	196252	0	0
T4	80296	80245	0	0
T5	81563	81508	0	0
T6	90509	90447	0	0
T8	108887	108829	0	0
T65	87507	87445	0	0
T103	73424	73362	0	0
T104	59868	59806	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	602190799	602068654	0	0
T1	42217	42155	0	0
T2	107343	107288	0	0
T3	196310	196252	0	0
T4	80296	80245	0	0
T5	81563	81508	0	0
T6	90509	90447	0	0
T8	108887	108829	0	0
T65	87507	87445	0	0
T103	73424	73362	0	0
T104	59868	59806	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	602190799	602068654	0	0
T1	42217	42155	0	0
T2	107343	107288	0	0
T3	196310	196252	0	0
T4	80296	80245	0	0
T5	81563	81508	0	0
T6	90509	90447	0	0
T8	108887	108829	0	0
T65	87507	87445	0	0
T103	73424	73362	0	0
T104	59868	59806	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2931	2931	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T65	1	1	0	0
T103	1	1	0	0
T104	1	1	0	0