Unified Coverage Report :: Module :: uart

Module : uart

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_uart0	100.00			100.00
tb.dut.top_earlgrey.u_uart1	100.00			100.00
tb.dut.top_earlgrey.u_uart2	100.00			100.00
tb.dut.top_earlgrey.u_uart3	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_uart0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : uart

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	308	308	100.00
Total Bits 0->1	154	154	100.00
Total Bits 1->0	154	154	100.00

Ports	40	40	100.00
Port Bits	308	308	100.00
Port Bits 0->1	154	154	100.00
Port Bits 1->0	154	154	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T37,T24,T32	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T66,T127,T59	Yes	T66,T127,T59	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T66,T127,T59	Yes	T66,T127,T59	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T91,*T92,*T93	Yes	T91,T92,T93	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T36,*T94,*T95	Yes	T36,T94,T95	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T36,T95,T96	Yes	T36,T95,T96	INPUT
tl_i.a_valid	Yes	Yes	T66,T127,T59	Yes	T66,T127,T59	INPUT
tl_o.a_ready	Yes	Yes	T66,T127,T59	Yes	T66,T127,T59	OUTPUT
tl_o.d_error	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T66,T127,T59	Yes	T66,T127,T59	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T66,T127,T59	Yes	T66,T127,T59	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T66,T127,T59	Yes	T66,T127,T59	OUTPUT
tl_o.d_sink	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T36,*T54,*T280	Yes	T36,T54,T280	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T66,*T127,*T59	Yes	T66,T127,T59	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T66,T127,T59	Yes	T66,T127,T59	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T74,T99,T101	Yes	T74,T99,T101	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T99,T101,T102	Yes	T99,T101,T102	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T99,T101,T102	Yes	T99,T101,T102	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T74,T99,T101	Yes	T74,T99,T101	OUTPUT
cio_rx_i	Yes	Yes	T2,T29,T66	Yes	T1,T2,T3	INPUT
cio_tx_o	Yes	Yes	T66,T127,T59	Yes	T66,T127,T59	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T66,T127,T59	Yes	T66,T127,T59	OUTPUT
intr_tx_empty_o	Yes	Yes	T66,T127,T59	Yes	T66,T127,T59	OUTPUT
intr_rx_watermark_o	Yes	Yes	T66,T127,T59	Yes	T66,T127,T59	OUTPUT
intr_tx_done_o	Yes	Yes	T66,T127,T59	Yes	T66,T127,T59	OUTPUT
intr_rx_overflow_o	Yes	Yes	T66,T127,T59	Yes	T66,T127,T59	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T329,T338,T339	Yes	T329,T338,T339	OUTPUT
intr_rx_break_err_o	Yes	Yes	T329,T338,T339	Yes	T329,T338,T339	OUTPUT
intr_rx_timeout_o	Yes	Yes	T329,T338,T339	Yes	T329,T338,T339	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T329,T338,T339	Yes	T329,T338,T339	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart0

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	304	304	100.00
Total Bits 0->1	152	152	100.00
Total Bits 1->0	152	152	100.00

Ports	40	40	100.00
Port Bits	304	304	100.00
Port Bits 0->1	152	152	100.00
Port Bits 1->0	152	152	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T37,T24,T32	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T127,T219,T36	Yes	T127,T219,T36	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T127,T219,T36	Yes	T127,T219,T36	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T91,*T92,*T93	Yes	T91,T92,T93	INPUT
tl_i.a_address[29:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T36,*T94,*T95	Yes	T36,T94,T95	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T36,T95,T96	Yes	T36,T95,T96	INPUT
tl_i.a_valid	Yes	Yes	T127,T74,T219	Yes	T127,T74,T219	INPUT
tl_o.a_ready	Yes	Yes	T127,T74,T270	Yes	T127,T74,T270	OUTPUT
tl_o.d_error	Yes	Yes	T92,T93,T180	Yes	T92,T93,T180	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T127,T36,T329	Yes	T127,T36,T329	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T127,T270,T36	Yes	T127,T74,T270	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T127,T270,T36	Yes	T127,T74,T270	OUTPUT
tl_o.d_sink	Yes	Yes	T91,T92,T93	Yes	T92,T93,T97	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T36,*T54,*T280	Yes	T36,T54,T280	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T92,T93,T97	Yes	T92,T93,T97	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T127,*T36,*T329	Yes	T127,T36,T329	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T127,T74,T270	Yes	T127,T74,T270	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T74,T99,T101	Yes	T74,T99,T101	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T99,T101,T102	Yes	T99,T101,T102	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T99,T101,T102	Yes	T99,T101,T102	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T74,T99,T101	Yes	T74,T99,T101	OUTPUT
cio_rx_i	Yes	Yes	T2,T37,T127	Yes	T1,T2,T3	INPUT
cio_tx_o	Yes	Yes	T127,T54,T51	Yes	T127,T54,T51	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T127,T329,T335	Yes	T127,T329,T335	OUTPUT
intr_tx_empty_o	Yes	Yes	T127,T36,T329	Yes	T127,T36,T329	OUTPUT
intr_rx_watermark_o	Yes	Yes	T127,T329,T336	Yes	T127,T329,T336	OUTPUT
intr_tx_done_o	Yes	Yes	T127,T329,T337	Yes	T127,T329,T337	OUTPUT
intr_rx_overflow_o	Yes	Yes	T127,T329,T337	Yes	T127,T329,T337	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T329,T338,T339	Yes	T329,T338,T339	OUTPUT
intr_rx_break_err_o	Yes	Yes	T329,T338,T339	Yes	T329,T338,T339	OUTPUT
intr_rx_timeout_o	Yes	Yes	T329,T338,T339	Yes	T329,T338,T339	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T329,T338,T339	Yes	T329,T338,T339	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart1

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	40	40	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T37,T24,T32	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T66,T128,T129	Yes	T66,T128,T129	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T66,T128,T129	Yes	T66,T128,T129	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T91,*T92,*T93	Yes	T91,T92,T93	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T36,*T94,*T95	Yes	T36,T94,T95	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T36,T95,T96	Yes	T36,T95,T96	INPUT
tl_i.a_valid	Yes	Yes	T66,T128,T129	Yes	T66,T128,T129	INPUT
tl_o.a_ready	Yes	Yes	T66,T128,T129	Yes	T66,T128,T129	OUTPUT
tl_o.d_error	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T66,T128,T129	Yes	T66,T128,T129	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T66,T128,T129	Yes	T66,T128,T129	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T66,T128,T129	Yes	T66,T128,T129	OUTPUT
tl_o.d_sink	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T36,*T96,*T69	Yes	T36,T96,T69	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T66,*T128,*T129	Yes	T66,T128,T129	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T66,T128,T129	Yes	T66,T128,T129	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T74,T99,T101	Yes	T74,T99,T101	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T99,T101,T102	Yes	T99,T101,T102	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T99,T101,T102	Yes	T99,T101,T102	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T74,T99,T101	Yes	T74,T99,T101	OUTPUT
cio_rx_i	Yes	Yes	T29,T66,T128	Yes	T2,T29,T66	INPUT
cio_tx_o	Yes	Yes	T66,T128,T129	Yes	T66,T128,T129	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T66,T128,T129	Yes	T66,T128,T129	OUTPUT
intr_tx_empty_o	Yes	Yes	T66,T128,T129	Yes	T66,T128,T129	OUTPUT
intr_rx_watermark_o	Yes	Yes	T66,T128,T129	Yes	T66,T128,T129	OUTPUT
intr_tx_done_o	Yes	Yes	T66,T128,T129	Yes	T66,T128,T129	OUTPUT
intr_rx_overflow_o	Yes	Yes	T66,T128,T129	Yes	T66,T128,T129	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T329,T338,T339	Yes	T329,T338,T339	OUTPUT
intr_rx_break_err_o	Yes	Yes	T329,T338,T339	Yes	T329,T338,T339	OUTPUT
intr_rx_timeout_o	Yes	Yes	T329,T338,T339	Yes	T329,T338,T339	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T329,T338,T339	Yes	T329,T338,T339	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart2

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	40	40	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T37,T24,T32	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T59,T36,T329	Yes	T59,T36,T329	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T59,T36,T329	Yes	T59,T36,T329	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T91,*T92,*T93	Yes	T91,T92,T93	INPUT
tl_i.a_address[16:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T36,*T94,*T95	Yes	T36,T94,T95	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T36,T95,T96	Yes	T36,T95,T96	INPUT
tl_i.a_valid	Yes	Yes	T59,T74,T270	Yes	T59,T74,T270	INPUT
tl_o.a_ready	Yes	Yes	T59,T74,T270	Yes	T59,T74,T270	OUTPUT
tl_o.d_error	Yes	Yes	T91,T92,T409	Yes	T91,T92,T175	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T59,T36,T329	Yes	T59,T36,T329	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T59,T270,T36	Yes	T59,T74,T270	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T59,T270,T36	Yes	T59,T74,T270	OUTPUT
tl_o.d_sink	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T36,*T96,*T69	Yes	T36,T96,T69	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T59,*T36,*T329	Yes	T59,T36,T329	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T59,T74,T270	Yes	T59,T74,T270	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T74,T99,T101	Yes	T74,T99,T101	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T99,T101,T102	Yes	T99,T101,T102	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T99,T101,T102	Yes	T99,T101,T102	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T74,T99,T101	Yes	T74,T99,T101	OUTPUT
cio_rx_i	Yes	Yes	T59,T60,T362	Yes	T59,T60,T362	INPUT
cio_tx_o	Yes	Yes	T59,T60,T96	Yes	T59,T60,T96	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T59,T329,T60	Yes	T59,T329,T60	OUTPUT
intr_tx_empty_o	Yes	Yes	T59,T329,T60	Yes	T59,T329,T60	OUTPUT
intr_rx_watermark_o	Yes	Yes	T59,T329,T60	Yes	T59,T329,T60	OUTPUT
intr_tx_done_o	Yes	Yes	T59,T329,T60	Yes	T59,T329,T60	OUTPUT
intr_rx_overflow_o	Yes	Yes	T59,T329,T60	Yes	T59,T329,T60	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T329,T338,T339	Yes	T329,T338,T339	OUTPUT
intr_rx_break_err_o	Yes	Yes	T329,T338,T339	Yes	T329,T338,T339	OUTPUT
intr_rx_timeout_o	Yes	Yes	T329,T338,T339	Yes	T329,T338,T339	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T329,T338,T339	Yes	T329,T338,T339	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart3

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	308	308	100.00
Total Bits 0->1	154	154	100.00
Total Bits 1->0	154	154	100.00

Ports	40	40	100.00
Port Bits	308	308	100.00
Port Bits 0->1	154	154	100.00
Port Bits 1->0	154	154	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T37,T24,T32	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T40,T36,T329	Yes	T40,T36,T329	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T40,T36,T329	Yes	T40,T36,T329	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T91,*T92,*T93	Yes	T91,T92,T93	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T36,*T94,*T95	Yes	T36,T94,T95	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T36,T95,T96	Yes	T36,T95,T96	INPUT
tl_i.a_valid	Yes	Yes	T40,T74,T270	Yes	T40,T74,T270	INPUT
tl_o.a_ready	Yes	Yes	T40,T74,T270	Yes	T40,T74,T270	OUTPUT
tl_o.d_error	Yes	Yes	T91,T93,T180	Yes	T91,T93,T180	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T40,T36,T329	Yes	T40,T36,T329	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T40,T270,T36	Yes	T40,T74,T270	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T40,T270,T36	Yes	T40,T74,T270	OUTPUT
tl_o.d_sink	Yes	Yes	T91,T93,T97	Yes	T91,T92,T93	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T36,*T96,*T69	Yes	T36,T96,T69	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T91,T93,T97	Yes	T91,T93,T97	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T40,*T36,*T329	Yes	T40,T36,T329	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T40,T74,T270	Yes	T40,T74,T270	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T74,T99,T101	Yes	T74,T99,T101	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T99,T101,T102	Yes	T99,T101,T102	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T99,T101,T102	Yes	T99,T101,T102	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T74,T99,T101	Yes	T74,T99,T101	OUTPUT
cio_rx_i	Yes	Yes	T40,T61,T373	Yes	T40,T61,T373	INPUT
cio_tx_o	Yes	Yes	T40,T61,T96	Yes	T40,T61,T96	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T40,T36,T329	Yes	T40,T36,T329	OUTPUT
intr_tx_empty_o	Yes	Yes	T40,T329,T61	Yes	T40,T329,T61	OUTPUT
intr_rx_watermark_o	Yes	Yes	T40,T329,T61	Yes	T40,T329,T61	OUTPUT
intr_tx_done_o	Yes	Yes	T40,T329,T61	Yes	T40,T329,T61	OUTPUT
intr_rx_overflow_o	Yes	Yes	T40,T329,T61	Yes	T40,T329,T61	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T329,T338,T339	Yes	T329,T338,T339	OUTPUT
intr_rx_break_err_o	Yes	Yes	T329,T338,T339	Yes	T329,T338,T339	OUTPUT
intr_rx_timeout_o	Yes	Yes	T329,T338,T339	Yes	T329,T338,T339	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T329,T338,T339	Yes	T329,T338,T339	OUTPUT

*Tests covering at least one bit in the range