Unified Coverage Report :: Module :: xbar_main

Module : xbar_main

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_main_0.1/rtl/autogen/xbar_main.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_main	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_main

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_main

	Total	Covered	Percent
Totals	550	550	100.00
Total Bits	6824	6824	100.00
Total Bits 0->1	3412	3412	100.00
Total Bits 1->0	3412	3412	100.00

Ports	550	550	100.00
Port Bits	6824	6824	100.00
Port Bits 0->1	3412	3412	100.00
Port Bits 1->0	3412	3412	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_main_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_fixed_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_usb_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_spi_host0_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_spi_host1_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_main_ni	Yes	Yes	T37,T24,T32	Yes	T1,T2,T3	INPUT
rst_fixed_ni	Yes	Yes	T37,T24,T32	Yes	T1,T2,T3	INPUT
rst_usb_ni	Yes	Yes	T37,T24,T32	Yes	T1,T2,T3	INPUT
rst_spi_host0_ni	Yes	Yes	T37,T24,T32	Yes	T1,T2,T3	INPUT
rst_spi_host1_ni	Yes	Yes	T37,T24,T32	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.d_ready	Yes	Yes	T98,T274,T275	Yes	T91,T92,T93	INPUT
tl_rv_core_ibex__corei_i.a_user.data_intg[6:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	INPUT
tl_rv_core_ibex__corei_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.a_user.instr_type[3:0]	Yes	Yes	T91,T97,T276	Yes	T91,T97,T276	INPUT
tl_rv_core_ibex__corei_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_data[31:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	INPUT
tl_rv_core_ibex__corei_i.a_mask[3:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	INPUT
tl_rv_core_ibex__corei_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_size[1:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	INPUT
tl_rv_core_ibex__corei_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_opcode[2:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	INPUT
tl_rv_core_ibex__corei_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_error	Yes	Yes	T236,T201,T94	Yes	T236,T201,T94	OUTPUT
tl_rv_core_ibex__corei_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[6:0]	Yes	Yes	T81,T236,T201	Yes	T81,T236,T201	OUTPUT
tl_rv_core_ibex__corei_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_sink	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_rv_core_ibex__corei_o.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_size[1:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_rv_core_ibex__corei_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_i.d_ready	Yes	Yes	T36,T95,T96	Yes	T36,T95,T96	INPUT
tl_rv_core_ibex__cored_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_user.instr_type[3:0]	Yes	Yes	T96,T97,T180	Yes	T96,T97,T180	INPUT
tl_rv_core_ibex__cored_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_size[1:0]	Yes	Yes	T96,T91,T92	Yes	T96,T91,T92	INPUT
tl_rv_core_ibex__cored_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_error	Yes	Yes	T44,T80,T183	Yes	T44,T80,T183	OUTPUT
tl_rv_core_ibex__cored_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_sink	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_rv_core_ibex__cored_o.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_size[1:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_rv_core_ibex__cored_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_i.d_ready	Yes	Yes	T37,T38,T44	Yes	T1,T3,T4	INPUT
tl_rv_dm__sba_i.a_user.data_intg[6:0]	Yes	Yes	T36,T94,T87	Yes	T36,T94,T87	INPUT
tl_rv_dm__sba_i.a_user.cmd_intg[6:0]	Yes	Yes	T37,T38,T44	Yes	T1,T3,T4	INPUT
tl_rv_dm__sba_i.a_user.instr_type[3:0]	Yes	Yes	T37,T38,T44	Yes	T1,T3,T4	INPUT
tl_rv_dm__sba_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_data[31:0]	Yes	Yes	T36,T94,T87	Yes	T36,T94,T87	INPUT
tl_rv_dm__sba_i.a_mask[3:0]	Yes	Yes	T37,T38,T44	Yes	T1,T3,T4	INPUT
tl_rv_dm__sba_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_source[5:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	INPUT
tl_rv_dm__sba_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_size[1:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	INPUT
tl_rv_dm__sba_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_opcode[2:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	INPUT
tl_rv_dm__sba_i.a_valid	Yes	Yes	T36,T94,T87	Yes	T36,T94,T87	INPUT
tl_rv_dm__sba_o.a_ready	Yes	Yes	T37,T24,T32	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_o.d_error	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_rv_dm__sba_o.d_user.data_intg[6:0]	Yes	Yes	T36,T94,T87	Yes	T36,T94,T87	OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[6:0]	Yes	Yes	T36,T87,T95	Yes	T36,T87,T95	OUTPUT
tl_rv_dm__sba_o.d_data[31:0]	Yes	Yes	T36,T94,T87	Yes	T36,T94,T87	OUTPUT
tl_rv_dm__sba_o.d_sink	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_rv_dm__sba_o.d_source[5:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_rv_dm__sba_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_size[1:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_rv_dm__sba_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_opcode[0]	Yes	Yes	*T36,*T94,*T87	Yes	T36,T94,T87	OUTPUT
tl_rv_dm__sba_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_valid	Yes	Yes	T36,T94,T87	Yes	T36,T94,T87	OUTPUT
tl_rv_dm__regs_o.d_ready	Yes	Yes	T37,T24,T32	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__regs_o.a_user.data_intg[6:0]	Yes	Yes	T69,T91,T92	Yes	T69,T91,T92	OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T69,T91,T92	Yes	T69,T91,T92	OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[3:0]	Yes	Yes	T69,T91,T92	Yes	T69,T91,T92	OUTPUT
tl_rv_dm__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_data[31:0]	Yes	Yes	T69,T91,T92	Yes	T69,T91,T92	OUTPUT
tl_rv_dm__regs_o.a_mask[3:0]	Yes	Yes	T69,T91,T93	Yes	T69,T91,T93	OUTPUT
tl_rv_dm__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_source[5:0]	Yes	Yes	*T69,T91,T92	Yes	T69,T91,T92	OUTPUT
tl_rv_dm__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_size[1:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_rv_dm__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_opcode[2:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_rv_dm__regs_o.a_valid	Yes	Yes	T69,T91,T92	Yes	T69,T91,T92	OUTPUT
tl_rv_dm__regs_i.a_ready	Yes	Yes	T69,T98,T274	Yes	T69,T91,T92	INPUT
tl_rv_dm__regs_i.d_error	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	INPUT
tl_rv_dm__regs_i.d_user.data_intg[6:0]	Yes	Yes	T69,T91,T92	Yes	T69,T91,T92	INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T69,T91,T92	Yes	T69,T91,T92	INPUT
tl_rv_dm__regs_i.d_data[31:0]	Yes	Yes	T69,T91,T93	Yes	T69,T91,T92	INPUT
tl_rv_dm__regs_i.d_sink	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	INPUT
tl_rv_dm__regs_i.d_source[5:0]	Yes	Yes	*T69,T91,T93	Yes	T69,T91,T92	INPUT
tl_rv_dm__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_size[1:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	INPUT
tl_rv_dm__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_opcode[0]	Yes	Yes	*T69,*T91,*T93	Yes	T69,T91,T92	INPUT
tl_rv_dm__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_valid	Yes	Yes	T69,T91,T92	Yes	T69,T91,T92	INPUT
tl_rv_dm__mem_o.d_ready	Yes	Yes	T37,T24,T32	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__mem_o.a_user.data_intg[6:0]	Yes	Yes	T94,T54,T280	Yes	T94,T54,T280	OUTPUT
tl_rv_dm__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T94,T54,T280	Yes	T94,T54,T280	OUTPUT
tl_rv_dm__mem_o.a_user.instr_type[3:0]	Yes	Yes	T94,T54,T280	Yes	T94,T54,T280	OUTPUT
tl_rv_dm__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_data[31:0]	Yes	Yes	T94,T54,T280	Yes	T94,T54,T280	OUTPUT
tl_rv_dm__mem_o.a_mask[3:0]	Yes	Yes	T94,T54,T280	Yes	T94,T54,T280	OUTPUT
tl_rv_dm__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_source[5:0]	Yes	Yes	*T94,*T54,*T280	Yes	T94,T54,T280	OUTPUT
tl_rv_dm__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_size[1:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_rv_dm__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_opcode[2:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_rv_dm__mem_o.a_valid	Yes	Yes	T94,T54,T280	Yes	T94,T54,T280	OUTPUT
tl_rv_dm__mem_i.a_ready	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
tl_rv_dm__mem_i.d_error	Yes	Yes	T1,T3,T4	Yes	T37,T38,T44	INPUT
tl_rv_dm__mem_i.d_user.data_intg[6:0]	Yes	Yes	T94,T54,T280	Yes	T94,T54,T280	INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T94,T54,T280	Yes	T94,T54,T280	INPUT
tl_rv_dm__mem_i.d_data[31:0]	Yes	Yes	T1,T3,T4	Yes	T37,T38,T44	INPUT
tl_rv_dm__mem_i.d_sink	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	INPUT
tl_rv_dm__mem_i.d_source[5:0]	Yes	Yes	*T94,*T54,*T280	Yes	T94,T54,T280	INPUT
tl_rv_dm__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_size[1:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	INPUT
tl_rv_dm__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_opcode[0]	Yes	Yes	*T1,*T3,*T4	Yes	T37,T38,T44	INPUT
tl_rv_dm__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_valid	Yes	Yes	T94,T54,T280	Yes	T94,T54,T280	INPUT
tl_rom_ctrl__rom_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.data_intg[6:0]	Yes	Yes	T1,T195,T235	Yes	T1,T195,T235	OUTPUT
tl_rom_ctrl__rom_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_data[31:0]	Yes	Yes	T195,T427,T95	Yes	T195,T427,T95	OUTPUT
tl_rom_ctrl__rom_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_size[1:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_rom_ctrl__rom_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_opcode[2:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_rom_ctrl__rom_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_error	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	INPUT
tl_rom_ctrl__rom_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_sink	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	INPUT
tl_rom_ctrl__rom_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_size[1:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	INPUT
tl_rom_ctrl__rom_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_opcode[0]	Yes	Yes	*T91,*T92,*T93	Yes	T91,T92,T93	INPUT
tl_rom_ctrl__rom_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__regs_o.d_ready	Yes	Yes	T37,T24,T32	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[6:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_rom_ctrl__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T74,T428,T293	Yes	T74,T428,T293	OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[3:0]	Yes	Yes	T74,T428,T293	Yes	T74,T428,T293	OUTPUT
tl_rom_ctrl__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_data[31:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_rom_ctrl__regs_o.a_mask[3:0]	Yes	Yes	T74,T428,T293	Yes	T74,T428,T293	OUTPUT
tl_rom_ctrl__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_source[5:0]	Yes	Yes	*T69,T91,T92	Yes	T69,T91,T92	OUTPUT
tl_rom_ctrl__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_size[1:0]	Yes	Yes	T91,T93,T97	Yes	T91,T93,T97	OUTPUT
tl_rom_ctrl__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_opcode[2:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_rom_ctrl__regs_o.a_valid	Yes	Yes	T74,T428,T293	Yes	T74,T428,T293	OUTPUT
tl_rom_ctrl__regs_i.a_ready	Yes	Yes	T74,T428,T293	Yes	T74,T428,T293	INPUT
tl_rom_ctrl__regs_i.d_error	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	INPUT
tl_rom_ctrl__regs_i.d_user.data_intg[6:0]	Yes	Yes	T428,T293,T429	Yes	T428,T293,T429	INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T69,T91,T92	Yes	T74,T75,T76	INPUT
tl_rom_ctrl__regs_i.d_data[31:0]	Yes	Yes	T428,T293,T429	Yes	T74,T428,T293	INPUT
tl_rom_ctrl__regs_i.d_sink	Yes	Yes	T91,T93,T97	Yes	T91,T93,T97	INPUT
tl_rom_ctrl__regs_i.d_source[5:0]	Yes	Yes	*T69,T93,T97	Yes	T69,T91,T92	INPUT
tl_rom_ctrl__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_size[1:0]	Yes	Yes	T91,T93,T97	Yes	T91,T93,T97	INPUT
tl_rom_ctrl__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_opcode[0]	Yes	Yes	*T293,*T430,*T431	Yes	T428,T293,T429	INPUT
tl_rom_ctrl__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_valid	Yes	Yes	T74,T428,T293	Yes	T74,T428,T293	INPUT
tl_peri_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_source[5:0]	Yes	Yes	*T36,*T94,*T95	Yes	T36,T94,T95	OUTPUT
tl_peri_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_size[1:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_peri_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_opcode[2:0]	Yes	Yes	T36,T95,T96	Yes	T36,T95,T96	OUTPUT
tl_peri_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_error	Yes	Yes	T378,T675,T295	Yes	T378,T675,T295	INPUT
tl_peri_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_sink	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	INPUT
tl_peri_i.d_source[5:0]	Yes	Yes	*T36,*T94,*T95	Yes	T36,T94,T95	INPUT
tl_peri_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_size[1:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	INPUT
tl_peri_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_spi_host0_o.d_ready	Yes	Yes	T10,T11,T402	Yes	T10,T11,T402	OUTPUT
tl_spi_host0_o.a_user.data_intg[6:0]	Yes	Yes	T10,T11,T402	Yes	T10,T11,T402	OUTPUT
tl_spi_host0_o.a_user.cmd_intg[6:0]	Yes	Yes	T10,T11,T402	Yes	T10,T11,T402	OUTPUT
tl_spi_host0_o.a_user.instr_type[3:0]	Yes	Yes	T10,T11,T402	Yes	T10,T11,T402	OUTPUT
tl_spi_host0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_data[31:0]	Yes	Yes	T10,T11,T402	Yes	T10,T11,T402	OUTPUT
tl_spi_host0_o.a_mask[3:0]	Yes	Yes	T10,T11,T402	Yes	T10,T11,T402	OUTPUT
tl_spi_host0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_source[5:0]	Yes	Yes	*T91,*T92,*T93	Yes	T91,T92,T93	OUTPUT
tl_spi_host0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_size[1:0]	Yes	Yes	T92,T93,T97	Yes	T92,T93,T97	OUTPUT
tl_spi_host0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_opcode[2:0]	Yes	Yes	T10,T222,T225	Yes	T10,T222,T225	OUTPUT
tl_spi_host0_o.a_valid	Yes	Yes	T10,T11,T402	Yes	T10,T11,T402	OUTPUT
tl_spi_host0_i.a_ready	Yes	Yes	T10,T11,T402	Yes	T10,T11,T402	INPUT
tl_spi_host0_i.d_error	Yes	Yes	T91,T92,T93	Yes	T92,T93,T97	INPUT
tl_spi_host0_i.d_user.data_intg[6:0]	Yes	Yes	T10,T11,T402	Yes	T10,T11,T402	INPUT
tl_spi_host0_i.d_user.rsp_intg[6:0]	Yes	Yes	T10,T11,T402	Yes	T10,T11,T402	INPUT
tl_spi_host0_i.d_data[31:0]	Yes	Yes	T10,T11,T402	Yes	T10,T11,T402	INPUT
tl_spi_host0_i.d_sink	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	INPUT
tl_spi_host0_i.d_source[5:0]	Yes	Yes	*T93,*T97,*T276	Yes	T91,T92,T93	INPUT
tl_spi_host0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_size[1:0]	Yes	Yes	T92,T93,T97	Yes	T92,T93,T97	INPUT
tl_spi_host0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_opcode[0]	Yes	Yes	*T10,*T11,*T402	Yes	T10,T11,T402	INPUT
tl_spi_host0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_valid	Yes	Yes	T10,T11,T402	Yes	T10,T11,T402	INPUT
tl_spi_host1_o.d_ready	Yes	Yes	T29,T402,T74	Yes	T29,T402,T74	OUTPUT
tl_spi_host1_o.a_user.data_intg[6:0]	Yes	Yes	T29,T402,T74	Yes	T29,T402,T74	OUTPUT
tl_spi_host1_o.a_user.cmd_intg[6:0]	Yes	Yes	T29,T402,T74	Yes	T29,T402,T74	OUTPUT
tl_spi_host1_o.a_user.instr_type[3:0]	Yes	Yes	T29,T402,T74	Yes	T29,T402,T74	OUTPUT
tl_spi_host1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_data[31:0]	Yes	Yes	T29,T402,T74	Yes	T29,T402,T74	OUTPUT
tl_spi_host1_o.a_mask[3:0]	Yes	Yes	T29,T402,T74	Yes	T29,T402,T74	OUTPUT
tl_spi_host1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_source[5:0]	Yes	Yes	*T91,*T92,*T93	Yes	T91,T92,T93	OUTPUT
tl_spi_host1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_size[1:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_spi_host1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_opcode[2:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_spi_host1_o.a_valid	Yes	Yes	T29,T402,T74	Yes	T29,T402,T74	OUTPUT
tl_spi_host1_i.a_ready	Yes	Yes	T29,T402,T74	Yes	T29,T402,T74	INPUT
tl_spi_host1_i.d_error	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	INPUT
tl_spi_host1_i.d_user.data_intg[6:0]	Yes	Yes	T29,T402,T124	Yes	T29,T402,T124	INPUT
tl_spi_host1_i.d_user.rsp_intg[6:0]	Yes	Yes	T29,T402,T124	Yes	T29,T402,T74	INPUT
tl_spi_host1_i.d_data[31:0]	Yes	Yes	T29,T402,T124	Yes	T29,T402,T124	INPUT
tl_spi_host1_i.d_sink	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	INPUT
tl_spi_host1_i.d_source[5:0]	Yes	Yes	*T92,*T93,*T97	Yes	T91,T92,T93	INPUT
tl_spi_host1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_size[1:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	INPUT
tl_spi_host1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_opcode[0]	Yes	Yes	*T29,*T402,*T124	Yes	T29,T402,T124	INPUT
tl_spi_host1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_valid	Yes	Yes	T29,T402,T74	Yes	T29,T402,T74	INPUT
tl_usbdev_o.d_ready	Yes	Yes	T3,T8,T65	Yes	T3,T8,T65	OUTPUT
tl_usbdev_o.a_user.data_intg[6:0]	Yes	Yes	T3,T8,T9	Yes	T3,T8,T9	OUTPUT
tl_usbdev_o.a_user.cmd_intg[6:0]	Yes	Yes	T3,T8,T65	Yes	T3,T8,T65	OUTPUT
tl_usbdev_o.a_user.instr_type[3:0]	Yes	Yes	T3,T8,T65	Yes	T3,T8,T65	OUTPUT
tl_usbdev_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_data[31:0]	Yes	Yes	T3,T8,T9	Yes	T3,T8,T9	OUTPUT
tl_usbdev_o.a_mask[3:0]	Yes	Yes	T3,T8,T65	Yes	T3,T8,T65	OUTPUT
tl_usbdev_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_source[5:0]	Yes	Yes	*T36,*T96,*T69	Yes	T36,T96,T69	OUTPUT
tl_usbdev_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_size[1:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_usbdev_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_opcode[2:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_usbdev_o.a_valid	Yes	Yes	T3,T8,T65	Yes	T3,T8,T65	OUTPUT
tl_usbdev_i.a_ready	Yes	Yes	T3,T8,T65	Yes	T3,T8,T65	INPUT
tl_usbdev_i.d_error	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	INPUT
tl_usbdev_i.d_user.data_intg[6:0]	Yes	Yes	T3,T8,T9	Yes	T3,T8,T65	INPUT
tl_usbdev_i.d_user.rsp_intg[6:0]	Yes	Yes	T3,T8,T65	Yes	T3,T8,T9	INPUT
tl_usbdev_i.d_data[31:0]	Yes	Yes	T3,T8,T65	Yes	T3,T8,T9	INPUT
tl_usbdev_i.d_sink	Yes	Yes	T92,T93,T97	Yes	T92,T93,T97	INPUT
tl_usbdev_i.d_source[5:0]	Yes	Yes	*T36,*T96,*T69	Yes	T36,T96,T69	INPUT
tl_usbdev_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_size[1:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	INPUT
tl_usbdev_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_opcode[0]	Yes	Yes	*T3,*T8,*T9	Yes	T3,T8,T9	INPUT
tl_usbdev_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_valid	Yes	Yes	T3,T8,T65	Yes	T3,T8,T65	INPUT
tl_flash_ctrl__core_o.d_ready	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_data[31:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__core_o.a_mask[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_source[5:0]	Yes	Yes	*T91,*T92,*T93	Yes	T91,T92,T93	OUTPUT
tl_flash_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_size[1:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_flash_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_flash_ctrl__core_o.a_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__core_i.a_ready	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_flash_ctrl__core_i.d_error	Yes	Yes	T1,T2,T3	Yes	T37,T24,T32	INPUT
tl_flash_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_data[31:0]	Yes	Yes	T2,T3,T4	Yes	T7,T37,T221	INPUT
tl_flash_ctrl__core_i.d_sink	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	INPUT
tl_flash_ctrl__core_i.d_source[5:0]	Yes	Yes	*T93,*T97,*T180	Yes	T91,T92,T93	INPUT
tl_flash_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_size[1:0]	Yes	Yes	T92,T93,T97	Yes	T91,T93,T97	INPUT
tl_flash_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_opcode[0]	Yes	Yes	*T2,*T3,*T4	Yes	T2,T3,T4	INPUT
tl_flash_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_flash_ctrl__prim_o.d_ready	Yes	Yes	T37,T24,T32	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_flash_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_flash_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_flash_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_data[31:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_flash_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_flash_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_source[5:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_flash_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_size[1:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_flash_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_flash_ctrl__prim_o.a_valid	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_flash_ctrl__prim_i.a_ready	Yes	Yes	T98,T274,T275	Yes	T91,T92,T93	INPUT
tl_flash_ctrl__prim_i.d_error	Yes	Yes	T92,T93,T97	Yes	T92,T93,T97	INPUT
tl_flash_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T91,T92,T93	Yes	T91,T93,T97	INPUT
tl_flash_ctrl__prim_i.d_data[31:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	INPUT
tl_flash_ctrl__prim_i.d_sink	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	INPUT
tl_flash_ctrl__prim_i.d_source[5:0]	Yes	Yes	T93,T97,T180	Yes	T91,T92,T93	INPUT
tl_flash_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_size[1:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	INPUT
tl_flash_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T91,*T92,*T93	Yes	T91,T92,T93	INPUT
tl_flash_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_valid	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	INPUT
tl_flash_ctrl__mem_o.d_ready	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.data_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__mem_o.a_user.instr_type[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_data[31:0]	Yes	Yes	T2,T4,T104	Yes	T2,T4,T104	OUTPUT
tl_flash_ctrl__mem_o.a_mask[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_source[5:0]	Yes	Yes	*T2,*T3,*T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_size[1:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_flash_ctrl__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_opcode[2:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_flash_ctrl__mem_o.a_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__mem_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T2,T3,T4	INPUT
tl_flash_ctrl__mem_i.d_error	Yes	Yes	T1,T2,T3	Yes	T37,T24,T32	INPUT
tl_flash_ctrl__mem_i.d_user.data_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_data[31:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_flash_ctrl__mem_i.d_sink	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	INPUT
tl_flash_ctrl__mem_i.d_source[5:0]	Yes	Yes	*T2,*T3,*T4	Yes	T2,T3,T4	INPUT
tl_flash_ctrl__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_size[1:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	INPUT
tl_flash_ctrl__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_opcode[0]	Yes	Yes	*T91,*T92,*T93	Yes	T91,T92,T93	INPUT
tl_flash_ctrl__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_hmac_o.d_ready	Yes	Yes	T37,T24,T32	Yes	T1,T2,T3	OUTPUT
tl_hmac_o.a_user.data_intg[6:0]	Yes	Yes	T74,T115,T671	Yes	T74,T115,T671	OUTPUT
tl_hmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T74,T115,T671	Yes	T74,T115,T671	OUTPUT
tl_hmac_o.a_user.instr_type[3:0]	Yes	Yes	T74,T115,T671	Yes	T74,T115,T671	OUTPUT
tl_hmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_data[31:0]	Yes	Yes	T74,T115,T671	Yes	T74,T115,T671	OUTPUT
tl_hmac_o.a_mask[3:0]	Yes	Yes	T74,T115,T671	Yes	T74,T115,T671	OUTPUT
tl_hmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_source[5:0]	Yes	Yes	*T91,*T92,*T93	Yes	T91,T92,T93	OUTPUT
tl_hmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_size[1:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_hmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_opcode[2:0]	Yes	Yes	T115,T671,T334	Yes	T115,T671,T334	OUTPUT
tl_hmac_o.a_valid	Yes	Yes	T74,T115,T671	Yes	T74,T115,T671	OUTPUT
tl_hmac_i.a_ready	Yes	Yes	T74,T115,T671	Yes	T74,T115,T671	INPUT
tl_hmac_i.d_error	Yes	Yes	T91,T93,T97	Yes	T91,T93,T97	INPUT
tl_hmac_i.d_user.data_intg[6:0]	Yes	Yes	T115,T671,T334	Yes	T115,T671,T334	INPUT
tl_hmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T115,T671,T334	Yes	T115,T671,T334	INPUT
tl_hmac_i.d_data[31:0]	Yes	Yes	T74,T115,T671	Yes	T115,T671,T334	INPUT
tl_hmac_i.d_sink	Yes	Yes	T91,T92,T93	Yes	T92,T93,T97	INPUT
tl_hmac_i.d_source[5:0]	Yes	Yes	*T93,*T97,*T175	Yes	T91,T93,T97	INPUT
tl_hmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_size[1:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	INPUT
tl_hmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_opcode[0]	Yes	Yes	*T74,*T115,*T671	Yes	T115,T671,T334	INPUT
tl_hmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_valid	Yes	Yes	T74,T115,T671	Yes	T74,T115,T671	INPUT
tl_kmac_o.d_ready	Yes	Yes	T4,T37,T24	Yes	T1,T2,T3	OUTPUT
tl_kmac_o.a_user.data_intg[6:0]	Yes	Yes	T4,T74,T467	Yes	T4,T74,T467	OUTPUT
tl_kmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T37,T189	Yes	T4,T37,T189	OUTPUT
tl_kmac_o.a_user.instr_type[3:0]	Yes	Yes	T4,T37,T189	Yes	T4,T37,T189	OUTPUT
tl_kmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_data[31:0]	Yes	Yes	T4,T74,T467	Yes	T4,T74,T467	OUTPUT
tl_kmac_o.a_mask[3:0]	Yes	Yes	T4,T37,T189	Yes	T4,T37,T189	OUTPUT
tl_kmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_source[5:0]	Yes	Yes	*T92,*T93,*T97	Yes	T92,T93,T97	OUTPUT
tl_kmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_size[1:0]	Yes	Yes	T92,T93,T97	Yes	T92,T93,T97	OUTPUT
tl_kmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_opcode[2:0]	Yes	Yes	T4,T467,T468	Yes	T4,T467,T468	OUTPUT
tl_kmac_o.a_valid	Yes	Yes	T4,T37,T189	Yes	T4,T37,T189	OUTPUT
tl_kmac_i.a_ready	Yes	Yes	T4,T37,T189	Yes	T4,T37,T189	INPUT
tl_kmac_i.d_error	Yes	Yes	T91,T93,T97	Yes	T91,T92,T93	INPUT
tl_kmac_i.d_user.data_intg[6:0]	Yes	Yes	T4,T37,T189	Yes	T4,T37,T189	INPUT
tl_kmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T37,T189	Yes	T4,T37,T189	INPUT
tl_kmac_i.d_data[31:0]	Yes	Yes	T4,T37,T189	Yes	T4,T37,T191	INPUT
tl_kmac_i.d_sink	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	INPUT
tl_kmac_i.d_source[5:0]	Yes	Yes	*T93,*T97,*T175	Yes	T92,T93,T97	INPUT
tl_kmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_size[1:0]	Yes	Yes	T92,T93,T97	Yes	T92,T93,T97	INPUT
tl_kmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_opcode[0]	Yes	Yes	*T4,*T37,*T189	Yes	T4,T37,T191	INPUT
tl_kmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_valid	Yes	Yes	T4,T37,T189	Yes	T4,T37,T189	INPUT
tl_aes_o.d_ready	Yes	Yes	T37,T24,T32	Yes	T1,T2,T3	OUTPUT
tl_aes_o.a_user.data_intg[6:0]	Yes	Yes	T422,T669,T670	Yes	T422,T669,T670	OUTPUT
tl_aes_o.a_user.cmd_intg[6:0]	Yes	Yes	T422,T669,T670	Yes	T422,T669,T670	OUTPUT
tl_aes_o.a_user.instr_type[3:0]	Yes	Yes	T422,T669,T670	Yes	T422,T669,T670	OUTPUT
tl_aes_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_data[31:0]	Yes	Yes	T422,T669,T670	Yes	T422,T669,T670	OUTPUT
tl_aes_o.a_mask[3:0]	Yes	Yes	T422,T669,T670	Yes	T422,T669,T670	OUTPUT
tl_aes_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_source[5:0]	Yes	Yes	*T91,*T92,*T93	Yes	T91,T92,T93	OUTPUT
tl_aes_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_size[1:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_aes_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_opcode[2:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_aes_o.a_valid	Yes	Yes	T422,T669,T670	Yes	T422,T669,T670	OUTPUT
tl_aes_i.a_ready	Yes	Yes	T422,T669,T670	Yes	T422,T669,T670	INPUT
tl_aes_i.d_error	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	INPUT
tl_aes_i.d_user.data_intg[6:0]	Yes	Yes	T422,T669,T670	Yes	T422,T669,T670	INPUT
tl_aes_i.d_user.rsp_intg[6:0]	Yes	Yes	T422,T669,T670	Yes	T422,T669,T670	INPUT
tl_aes_i.d_data[31:0]	Yes	Yes	T422,T669,T670	Yes	T422,T669,T670	INPUT
tl_aes_i.d_sink	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	INPUT
tl_aes_i.d_source[5:0]	Yes	Yes	*T92,*T93,*T97	Yes	T91,T92,T93	INPUT
tl_aes_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_size[1:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	INPUT
tl_aes_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_opcode[0]	Yes	Yes	*T422,*T669,*T670	Yes	T422,T669,T670	INPUT
tl_aes_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_valid	Yes	Yes	T422,T669,T670	Yes	T422,T669,T670	INPUT
tl_entropy_src_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_source[5:0]	Yes	Yes	*T91,*T92,*T93	Yes	T91,T92,T93	OUTPUT
tl_entropy_src_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_size[1:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_entropy_src_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_opcode[2:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_entropy_src_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_error	Yes	Yes	T93,T97,T180	Yes	T92,T93,T97	INPUT
tl_entropy_src_i.d_user.data_intg[6:0]	Yes	Yes	T152,T155,T113	Yes	T152,T155,T113	INPUT
tl_entropy_src_i.d_user.rsp_intg[6:0]	Yes	Yes	T37,T24,T38	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_data[31:0]	Yes	Yes	T37,T24,T38	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_sink	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	INPUT
tl_entropy_src_i.d_source[5:0]	Yes	Yes	*T93,*T97,*T276	Yes	T91,T92,T93	INPUT
tl_entropy_src_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_size[1:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	INPUT
tl_entropy_src_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_opcode[0]	Yes	Yes	*T152,*T155,*T113	Yes	T152,T155,T113	INPUT
tl_entropy_src_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_csrng_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_data[31:0]	Yes	Yes	T152,T290,T74	Yes	T152,T290,T74	OUTPUT
tl_csrng_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_source[5:0]	Yes	Yes	*T91,*T92,*T93	Yes	T91,T92,T93	OUTPUT
tl_csrng_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_size[1:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_csrng_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_opcode[2:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_csrng_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_error	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	INPUT
tl_csrng_i.d_user.data_intg[6:0]	Yes	Yes	T152,T290,T155	Yes	T152,T290,T155	INPUT
tl_csrng_i.d_user.rsp_intg[6:0]	Yes	Yes	T37,T24,T38	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_data[31:0]	Yes	Yes	T37,T24,T38	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_sink	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	INPUT
tl_csrng_i.d_source[5:0]	Yes	Yes	*T92,*T93,*T97	Yes	T91,T92,T93	INPUT
tl_csrng_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_size[1:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	INPUT
tl_csrng_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_opcode[0]	Yes	Yes	*T152,*T290,*T155	Yes	T152,T290,T155	INPUT
tl_csrng_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn0_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.data_intg[6:0]	Yes	Yes	T152,T290,T74	Yes	T152,T290,T74	OUTPUT
tl_edn0_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_data[31:0]	Yes	Yes	T152,T290,T74	Yes	T152,T290,T74	OUTPUT
tl_edn0_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_source[5:0]	Yes	Yes	*T91,*T93,*T97	Yes	T91,T93,T97	OUTPUT
tl_edn0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_size[1:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_edn0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_opcode[2:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_edn0_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_error	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	INPUT
tl_edn0_i.d_user.data_intg[6:0]	Yes	Yes	T152,T290,T155	Yes	T152,T290,T155	INPUT
tl_edn0_i.d_user.rsp_intg[6:0]	Yes	Yes	T37,T24,T38	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_data[31:0]	Yes	Yes	T37,T24,T38	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_sink	Yes	Yes	T91,T92,T93	Yes	T91,T93,T98	INPUT
tl_edn0_i.d_source[5:0]	Yes	Yes	*T93,*T97,*T276	Yes	T91,T93,T175	INPUT
tl_edn0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_size[1:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	INPUT
tl_edn0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_opcode[0]	Yes	Yes	*T152,*T290,*T155	Yes	T152,T290,T155	INPUT
tl_edn0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn1_o.d_ready	Yes	Yes	T37,T24,T32	Yes	T1,T2,T3	OUTPUT
tl_edn1_o.a_user.data_intg[6:0]	Yes	Yes	T152,T74,T155	Yes	T152,T74,T155	OUTPUT
tl_edn1_o.a_user.cmd_intg[6:0]	Yes	Yes	T152,T74,T155	Yes	T152,T74,T155	OUTPUT
tl_edn1_o.a_user.instr_type[3:0]	Yes	Yes	T152,T74,T155	Yes	T152,T74,T155	OUTPUT
tl_edn1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_data[31:0]	Yes	Yes	T152,T74,T155	Yes	T152,T74,T155	OUTPUT
tl_edn1_o.a_mask[3:0]	Yes	Yes	T152,T74,T155	Yes	T152,T74,T155	OUTPUT
tl_edn1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_source[5:0]	Yes	Yes	*T91,*T93,*T97	Yes	T91,T93,T97	OUTPUT
tl_edn1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_size[1:0]	Yes	Yes	T91,T93,T97	Yes	T91,T93,T97	OUTPUT
tl_edn1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_opcode[2:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_edn1_o.a_valid	Yes	Yes	T152,T74,T155	Yes	T152,T74,T155	OUTPUT
tl_edn1_i.a_ready	Yes	Yes	T152,T74,T155	Yes	T152,T74,T155	INPUT
tl_edn1_i.d_error	Yes	Yes	T92,T93,T97	Yes	T92,T93,T97	INPUT
tl_edn1_i.d_user.data_intg[6:0]	Yes	Yes	T152,T155,T116	Yes	T152,T155,T116	INPUT
tl_edn1_i.d_user.rsp_intg[6:0]	Yes	Yes	T152,T116,T153	Yes	T152,T74,T155	INPUT
tl_edn1_i.d_data[31:0]	Yes	Yes	T152,T116,T153	Yes	T152,T74,T155	INPUT
tl_edn1_i.d_sink	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	INPUT
tl_edn1_i.d_source[5:0]	Yes	Yes	*T93,*T97,*T276	Yes	T91,T93,T97	INPUT
tl_edn1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_size[1:0]	Yes	Yes	T91,T93,T97	Yes	T93,T276,T445	INPUT
tl_edn1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_opcode[0]	Yes	Yes	*T152,*T155,*T116	Yes	T152,T155,T116	INPUT
tl_edn1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_valid	Yes	Yes	T152,T74,T155	Yes	T152,T74,T155	INPUT
tl_rv_plic_o.d_ready	Yes	Yes	T2,T5,T6	Yes	T1,T2,T3	OUTPUT
tl_rv_plic_o.a_user.data_intg[6:0]	Yes	Yes	T2,T5,T6	Yes	T2,T5,T6	OUTPUT
tl_rv_plic_o.a_user.cmd_intg[6:0]	Yes	Yes	T2,T5,T6	Yes	T2,T5,T6	OUTPUT
tl_rv_plic_o.a_user.instr_type[3:0]	Yes	Yes	T2,T5,T6	Yes	T2,T5,T6	OUTPUT
tl_rv_plic_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_data[31:0]	Yes	Yes	T2,T5,T6	Yes	T2,T5,T6	OUTPUT
tl_rv_plic_o.a_mask[3:0]	Yes	Yes	T2,T5,T6	Yes	T2,T5,T6	OUTPUT
tl_rv_plic_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_source[5:0]	Yes	Yes	*T91,*T92,*T93	Yes	T91,T92,T93	OUTPUT
tl_rv_plic_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_size[1:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_rv_plic_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_opcode[2:0]	Yes	Yes	T91,T93,T97	Yes	T91,T93,T97	OUTPUT
tl_rv_plic_o.a_valid	Yes	Yes	T2,T5,T6	Yes	T2,T5,T6	OUTPUT
tl_rv_plic_i.a_ready	Yes	Yes	T2,T5,T6	Yes	T2,T5,T6	INPUT
tl_rv_plic_i.d_error	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	INPUT
tl_rv_plic_i.d_user.data_intg[6:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_rv_plic_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T5,T6	Yes	T2,T5,T6	INPUT
tl_rv_plic_i.d_data[31:0]	Yes	Yes	T2,T5,T6	Yes	T2,T5,T6	INPUT
tl_rv_plic_i.d_sink	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	INPUT
tl_rv_plic_i.d_source[5:0]	Yes	Yes	*T91,*T93,*T97	Yes	T91,T92,T93	INPUT
tl_rv_plic_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_size[1:0]	Yes	Yes	T91,T92,T93	Yes	T91,T93,T97	INPUT
tl_rv_plic_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_opcode[0]	Yes	Yes	*T2,*T5,*T6	Yes	T2,T5,T6	INPUT
tl_rv_plic_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_valid	Yes	Yes	T2,T5,T6	Yes	T2,T5,T6	INPUT
tl_otbn_o.d_ready	Yes	Yes	T37,T24,T32	Yes	T1,T2,T3	OUTPUT
tl_otbn_o.a_user.data_intg[6:0]	Yes	Yes	T74,T205,T116	Yes	T74,T205,T116	OUTPUT
tl_otbn_o.a_user.cmd_intg[6:0]	Yes	Yes	T74,T205,T116	Yes	T74,T205,T116	OUTPUT
tl_otbn_o.a_user.instr_type[3:0]	Yes	Yes	T74,T205,T116	Yes	T74,T205,T116	OUTPUT
tl_otbn_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_data[31:0]	Yes	Yes	T74,T205,T116	Yes	T74,T205,T116	OUTPUT
tl_otbn_o.a_mask[3:0]	Yes	Yes	T74,T205,T116	Yes	T74,T205,T116	OUTPUT
tl_otbn_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_source[5:0]	Yes	Yes	*T95,*T226,*T227	Yes	T95,T226,T227	OUTPUT
tl_otbn_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_size[1:0]	Yes	Yes	T92,T93,T180	Yes	T92,T93,T180	OUTPUT
tl_otbn_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_opcode[2:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_otbn_o.a_valid	Yes	Yes	T74,T205,T116	Yes	T74,T205,T116	OUTPUT
tl_otbn_i.a_ready	Yes	Yes	T74,T205,T116	Yes	T74,T205,T116	INPUT
tl_otbn_i.d_error	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	INPUT
tl_otbn_i.d_user.data_intg[6:0]	Yes	Yes	T205,T116,T153	Yes	T205,T116,T153	INPUT
tl_otbn_i.d_user.rsp_intg[6:0]	Yes	Yes	T205,T116,T153	Yes	T205,T116,T153	INPUT
tl_otbn_i.d_data[31:0]	Yes	Yes	T74,T205,T116	Yes	T205,T116,T153	INPUT
tl_otbn_i.d_sink	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	INPUT
tl_otbn_i.d_source[5:0]	Yes	Yes	*T95,*T226,*T227	Yes	T95,T226,T227	INPUT
tl_otbn_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_size[1:0]	Yes	Yes	T92,T93,T180	Yes	T92,T93,T175	INPUT
tl_otbn_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_opcode[0]	Yes	Yes	*T74,*T205,*T116	Yes	T205,T116,T153	INPUT
tl_otbn_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_valid	Yes	Yes	T74,T205,T116	Yes	T74,T205,T116	INPUT
tl_keymgr_o.d_ready	Yes	Yes	T37,T24,T32	Yes	T1,T2,T3	OUTPUT
tl_keymgr_o.a_user.data_intg[6:0]	Yes	Yes	T37,T191,T74	Yes	T37,T191,T74	OUTPUT
tl_keymgr_o.a_user.cmd_intg[6:0]	Yes	Yes	T37,T189,T191	Yes	T37,T189,T191	OUTPUT
tl_keymgr_o.a_user.instr_type[3:0]	Yes	Yes	T37,T189,T191	Yes	T37,T189,T191	OUTPUT
tl_keymgr_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_data[31:0]	Yes	Yes	T37,T191,T74	Yes	T37,T191,T74	OUTPUT
tl_keymgr_o.a_mask[3:0]	Yes	Yes	T37,T189,T191	Yes	T37,T189,T191	OUTPUT
tl_keymgr_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_source[5:0]	Yes	Yes	*T91,*T92,*T93	Yes	T91,T92,T93	OUTPUT
tl_keymgr_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_size[1:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_keymgr_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_opcode[2:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_keymgr_o.a_valid	Yes	Yes	T37,T189,T191	Yes	T37,T189,T191	OUTPUT
tl_keymgr_i.a_ready	Yes	Yes	T37,T189,T191	Yes	T37,T189,T191	INPUT
tl_keymgr_i.d_error	Yes	Yes	T91,T93,T97	Yes	T91,T93,T97	INPUT
tl_keymgr_i.d_user.data_intg[6:0]	Yes	Yes	T37,T191,T237	Yes	T37,T191,T237	INPUT
tl_keymgr_i.d_user.rsp_intg[6:0]	Yes	Yes	T37,T191,T237	Yes	T37,T191,T74	INPUT
tl_keymgr_i.d_data[31:0]	Yes	Yes	T37,T191,T237	Yes	T37,T191,T74	INPUT
tl_keymgr_i.d_sink	Yes	Yes	T92,T93,T97	Yes	T91,T93,T175	INPUT
tl_keymgr_i.d_source[5:0]	Yes	Yes	*T93,*T97,*T175	Yes	T91,T92,T93	INPUT
tl_keymgr_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_size[1:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	INPUT
tl_keymgr_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_opcode[0]	Yes	Yes	*T37,*T191,*T237	Yes	T37,T189,T191	INPUT
tl_keymgr_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_valid	Yes	Yes	T37,T189,T191	Yes	T37,T189,T191	INPUT
tl_rv_core_ibex__cfg_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_source[5:0]	Yes	Yes	*T54,*T280,*T281	Yes	T54,T280,T281	OUTPUT
tl_rv_core_ibex__cfg_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_size[1:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_rv_core_ibex__cfg_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_opcode[2:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_rv_core_ibex__cfg_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_error	Yes	Yes	T69,T91,T92	Yes	T69,T92,T93	INPUT
tl_rv_core_ibex__cfg_i.d_user.data_intg[6:0]	Yes	Yes	T2,T5,T6	Yes	T2,T5,T6	INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_data[31:0]	Yes	Yes	T2,T5,T6	Yes	T2,T5,T6	INPUT
tl_rv_core_ibex__cfg_i.d_sink	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	INPUT
tl_rv_core_ibex__cfg_i.d_source[5:0]	Yes	Yes	*T69,*T93,*T97	Yes	T54,T280,T281	INPUT
tl_rv_core_ibex__cfg_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_size[1:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	INPUT
tl_rv_core_ibex__cfg_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_opcode[0]	Yes	Yes	*T2,*T3,*T4	Yes	T2,T3,T4	INPUT
tl_rv_core_ibex__cfg_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__regs_o.d_ready	Yes	Yes	T37,T24,T32	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.data_intg[6:0]	Yes	Yes	T74,T146,T198	Yes	T74,T146,T198	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T74,T146,T198	Yes	T74,T146,T198	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[3:0]	Yes	Yes	T74,T146,T198	Yes	T74,T146,T198	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_data[31:0]	Yes	Yes	T74,T146,T198	Yes	T74,T146,T198	OUTPUT
tl_sram_ctrl_main__regs_o.a_mask[3:0]	Yes	Yes	T74,T146,T198	Yes	T74,T146,T198	OUTPUT
tl_sram_ctrl_main__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_source[5:0]	Yes	Yes	*T462,*T463,*T91	Yes	T462,T463,T91	OUTPUT
tl_sram_ctrl_main__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_size[1:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_sram_ctrl_main__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_opcode[2:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_sram_ctrl_main__regs_o.a_valid	Yes	Yes	T74,T146,T198	Yes	T74,T146,T198	OUTPUT
tl_sram_ctrl_main__regs_i.a_ready	Yes	Yes	T74,T146,T198	Yes	T74,T146,T198	INPUT
tl_sram_ctrl_main__regs_i.d_error	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	INPUT
tl_sram_ctrl_main__regs_i.d_user.data_intg[6:0]	Yes	Yes	T201,T326,T327	Yes	T201,T326,T327	INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T146,T198,T201	Yes	T74,T146,T198	INPUT
tl_sram_ctrl_main__regs_i.d_data[31:0]	Yes	Yes	T146,T198,T201	Yes	T74,T146,T198	INPUT
tl_sram_ctrl_main__regs_i.d_sink	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	INPUT
tl_sram_ctrl_main__regs_i.d_source[5:0]	Yes	Yes	*T92,*T93,*T97	Yes	T462,T463,T91	INPUT
tl_sram_ctrl_main__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_size[1:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	INPUT
tl_sram_ctrl_main__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_opcode[0]	Yes	Yes	*T146,*T198,*T201	Yes	T146,T198,T201	INPUT
tl_sram_ctrl_main__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_valid	Yes	Yes	T74,T146,T198	Yes	T74,T146,T198	INPUT
tl_sram_ctrl_main__ram_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_size[1:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_sram_ctrl_main__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_error	Yes	Yes	T1,T2,T3	Yes	T37,T24,T32	INPUT
tl_sram_ctrl_main__ram_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_sink	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	INPUT
tl_sram_ctrl_main__ram_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_size[1:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	INPUT
tl_sram_ctrl_main__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range