Unified Coverage Report :: Module Instance :: tb.dut.u_padring.gen_dio_pads[22].u_dio_pad.gen_generic.u_impl_generic

Module Instance : tb.dut.u_padring.gen_dio_pads[22].u_dio_pad.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_dio_pads[22].u_dio_pad

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_padring.gen_mio_pads[0].u_mio_pad.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[0].u_mio_pad

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_padring.gen_mio_pads[1].u_mio_pad.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[1].u_mio_pad

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_padring.gen_mio_pads[2].u_mio_pad.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[2].u_mio_pad

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_padring.gen_mio_pads[3].u_mio_pad.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[3].u_mio_pad

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_padring.gen_mio_pads[4].u_mio_pad.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[4].u_mio_pad

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_padring.gen_mio_pads[5].u_mio_pad.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[5].u_mio_pad

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_padring.gen_mio_pads[6].u_mio_pad.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[6].u_mio_pad

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_padring.gen_mio_pads[7].u_mio_pad.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[7].u_mio_pad

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_padring.gen_mio_pads[8].u_mio_pad.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[8].u_mio_pad

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_padring.gen_mio_pads[9].u_mio_pad.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[9].u_mio_pad

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_padring.gen_mio_pads[10].u_mio_pad.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[10].u_mio_pad

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_padring.gen_mio_pads[11].u_mio_pad.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[11].u_mio_pad

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_padring.gen_mio_pads[12].u_mio_pad.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[12].u_mio_pad

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_padring.gen_mio_pads[13].u_mio_pad.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[13].u_mio_pad

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_padring.gen_mio_pads[14].u_mio_pad.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[14].u_mio_pad

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_padring.gen_mio_pads[15].u_mio_pad.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[15].u_mio_pad

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_padring.gen_mio_pads[16].u_mio_pad.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[16].u_mio_pad

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_padring.gen_mio_pads[17].u_mio_pad.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[17].u_mio_pad

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_padring.gen_mio_pads[18].u_mio_pad.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[18].u_mio_pad

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_padring.gen_mio_pads[19].u_mio_pad.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[19].u_mio_pad

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_padring.gen_mio_pads[20].u_mio_pad.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[20].u_mio_pad

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[22].u_dio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	95	1	1	100.00

38                        logic unused_sigs;
39         unreachable    assign unused_sigs = ^{attr_i.slew_rate,
40                                               attr_i.drive_strength[3:1],
41                                               attr_i.od_en,
42                                               attr_i.schmitt_en,
43                                               attr_i.keep_en,
44                                               scanmode_i,
45                                               pok_i};
46                        //VCS coverage on
47                        // pragma coverage on
48                      
49                        // Input enable (active-high)
50                        logic ie;
51         1/1            assign ie = ie_i & ~attr_i.input_disable;
           Tests:       T21 T22 T23 
52                      
53                        if (PadType == InputStd) begin : gen_input_only
54                          //VCS coverage off
55                          // pragma coverage off
56                          logic unused_in_sigs;
57                          assign unused_in_sigs = ^{out_i,
58                                                    oe_i,
59                                                    attr_i.virt_od_en,
60                                                    attr_i.drive_strength};
61                          //VCS coverage on
62                          // pragma coverage on
63                      
64                          assign in_raw_o = ie ? inout_io : 1'bz;
65                          // input inversion
66                          assign in_o = attr_i.invert ^ in_raw_o;
67                      
68                        // pulls are not supported by verilator
69                        `ifndef VERILATOR
70                          // pullup / pulldown termination
71                          assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72                        `endif
73                        end else if (PadType == BidirTol ||
74                                     PadType == DualBidirTol ||
75                                     PadType == BidirOd ||
76                                     PadType == BidirStd) begin : gen_bidir
77                      
78         1/1              assign in_raw_o = ie ? inout_io : 1'bz;
           Tests:       T24 T17 T14 
79                          // input inversion
80         1/1              assign in_o = attr_i.invert ^ in_raw_o;
           Tests:       T24 T17 T14 
81                      
82                          // virtual open drain emulation
83                          logic oe, out;
84         1/1              assign out = out_i ^ attr_i.invert;
           Tests:       T17 T14 T15 
85         1/1              assign oe  = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
           Tests:       T24 T17 T14 
86                      
87                        // drive strength attributes are not supported by verilator
88                        `ifdef VERILATOR
89                          assign inout_io = (oe)   ? out : 1'bz;
90                        `else
91                          // different driver types
92         1/1              assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T24 T17 T14 
93         1/1              assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T24 T17 T14 
94                          // pullup / pulldown termination
95         1/1              assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
           Tests:       T21 T22 T23 

---

Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[22].u_dio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T21,T22,T23
1	1	Covered	T1,T2,T3

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1

-1-	Status	Tests
0	Covered	T21,T22,T23
1	Covered	T1,T2,T3

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T24,T17,T14
1	0	Covered	T21,T22,T23
1	1	Covered	T21,T22,T23

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T21,T22,T23
1	0	Covered	T17,T14,T15
1	1	Covered	T21,T22,T23

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T24,T25,T26
1	0	Covered	T17,T47,T48
1	1	Covered	T1,T2,T3

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T17,T47,T48
0	1	Covered	T1,T2,T3
1	0	Covered	T17,T47,T48

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T17,T47,T48
1	1	Covered	T17,T47,T48

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T21,T22,T23

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T21,T22,T23
1	0	Covered	T1,T2,T3
1	1	Covered	T21,T22,T23

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T24,T17,T25
1	Covered	T1,T2,T3

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T24,T17,T25
1	0	Covered	T21,T22,T23
1	1	Covered	T1,T2,T3

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T21,T22,T23

---

Branch Coverage for Instance : tb.dut.u_padring.gen_dio_pads[22].u_dio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	78	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	93	2	2	100.00
TERNARY	95	2	2	100.00

78             assign in_raw_o = ie ? inout_io : 1'bz;
                                    -1-  
                                    ==>  
                                    ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T21,T22,T23

92             assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                     -1-  
                                                                                     ==>  
                                                                                     ==>  

Branches:

-1-	Status	Tests
1	Covered	T21,T22,T23
0	Covered	T1,T2,T3

93             assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                      -1-  
                                                                                      ==>  
                                                                                      ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T24,T17,T25

95             assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
                                                                   -1-  
                                                                   ==>  
                                                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T21,T22,T23
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[22].u_dio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	1021	1021	0	0

AnalogNoScan_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1021	1021	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T65	1	1	0	0
T103	1	1	0	0
T104	1	1	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[0].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	95	1	1	100.00

38                        logic unused_sigs;
39         unreachable    assign unused_sigs = ^{attr_i.slew_rate,
40                                               attr_i.drive_strength[3:1],
41                                               attr_i.od_en,
42                                               attr_i.schmitt_en,
43                                               attr_i.keep_en,
44                                               scanmode_i,
45                                               pok_i};
46                        //VCS coverage on
47                        // pragma coverage on
48                      
49                        // Input enable (active-high)
50                        logic ie;
51         1/1            assign ie = ie_i & ~attr_i.input_disable;
           Tests:       T21 T22 T23 
52                      
53                        if (PadType == InputStd) begin : gen_input_only
54                          //VCS coverage off
55                          // pragma coverage off
56                          logic unused_in_sigs;
57                          assign unused_in_sigs = ^{out_i,
58                                                    oe_i,
59                                                    attr_i.virt_od_en,
60                                                    attr_i.drive_strength};
61                          //VCS coverage on
62                          // pragma coverage on
63                      
64                          assign in_raw_o = ie ? inout_io : 1'bz;
65                          // input inversion
66                          assign in_o = attr_i.invert ^ in_raw_o;
67                      
68                        // pulls are not supported by verilator
69                        `ifndef VERILATOR
70                          // pullup / pulldown termination
71                          assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72                        `endif
73                        end else if (PadType == BidirTol ||
74                                     PadType == DualBidirTol ||
75                                     PadType == BidirOd ||
76                                     PadType == BidirStd) begin : gen_bidir
77                      
78         1/1              assign in_raw_o = ie ? inout_io : 1'bz;
           Tests:       T2 T27 T28 
79                          // input inversion
80         1/1              assign in_o = attr_i.invert ^ in_raw_o;
           Tests:       T2 T27 T28 
81                      
82                          // virtual open drain emulation
83                          logic oe, out;
84         1/1              assign out = out_i ^ attr_i.invert;
           Tests:       T27 T28 T41 
85         1/1              assign oe  = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
           Tests:       T27 T28 T41 
86                      
87                        // drive strength attributes are not supported by verilator
88                        `ifdef VERILATOR
89                          assign inout_io = (oe)   ? out : 1'bz;
90                        `else
91                          // different driver types
92         1/1              assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T27 T28 T41 
93         1/1              assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T27 T28 T41 
94                          // pullup / pulldown termination
95         1/1              assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
           Tests:       T21 T22 T23 

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[0].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T21,T22,T23
1	1	Covered	T1,T2,T3

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1

-1-	Status	Tests
0	Covered	T21,T22,T23
1	Covered	T1,T2,T3

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T2,T27,T28
0	1	Covered	T2,T27,T28
1	0	Covered	T21,T22,T23
1	1	Covered	T21,T22,T23

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T21,T22,T23
1	0	Covered	T27,T28,T41
1	1	Covered	T21,T22,T23

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T22,T23
1	1	Covered	T27,T28,T41

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T21,T22,T23
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T22,T23

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T22,T23
1	1	Covered	T21,T22,T23

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T21,T22,T23

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T21,T22,T23
1	0	Covered	T27,T28,T41
1	1	Covered	T21,T22,T23

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T27,T28,T41

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T22,T23
1	1	Covered	T27,T28,T41

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T21,T22,T23

---

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[0].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	78	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	93	2	2	100.00
TERNARY	95	2	2	100.00

78             assign in_raw_o = ie ? inout_io : 1'bz;
                                    -1-  
                                    ==>  
                                    ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T21,T22,T23

92             assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                     -1-  
                                                                                     ==>  
                                                                                     ==>  

Branches:

-1-	Status	Tests
1	Covered	T21,T22,T23
0	Covered	T1,T2,T3

93             assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                      -1-  
                                                                                      ==>  
                                                                                      ==>  

Branches:

-1-	Status	Tests
1	Covered	T27,T28,T41
0	Covered	T1,T2,T3

95             assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
                                                                   -1-  
                                                                   ==>  
                                                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T21,T22,T23
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[0].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	1021	1021	0	0

AnalogNoScan_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1021	1021	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T65	1	1	0	0
T103	1	1	0	0
T104	1	1	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[1].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	95	1	1	100.00

38                        logic unused_sigs;
39         unreachable    assign unused_sigs = ^{attr_i.slew_rate,
40                                               attr_i.drive_strength[3:1],
41                                               attr_i.od_en,
42                                               attr_i.schmitt_en,
43                                               attr_i.keep_en,
44                                               scanmode_i,
45                                               pok_i};
46                        //VCS coverage on
47                        // pragma coverage on
48                      
49                        // Input enable (active-high)
50                        logic ie;
51         1/1            assign ie = ie_i & ~attr_i.input_disable;
           Tests:       T21 T22 T23 
52                      
53                        if (PadType == InputStd) begin : gen_input_only
54                          //VCS coverage off
55                          // pragma coverage off
56                          logic unused_in_sigs;
57                          assign unused_in_sigs = ^{out_i,
58                                                    oe_i,
59                                                    attr_i.virt_od_en,
60                                                    attr_i.drive_strength};
61                          //VCS coverage on
62                          // pragma coverage on
63                      
64                          assign in_raw_o = ie ? inout_io : 1'bz;
65                          // input inversion
66                          assign in_o = attr_i.invert ^ in_raw_o;
67                      
68                        // pulls are not supported by verilator
69                        `ifndef VERILATOR
70                          // pullup / pulldown termination
71                          assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72                        `endif
73                        end else if (PadType == BidirTol ||
74                                     PadType == DualBidirTol ||
75                                     PadType == BidirOd ||
76                                     PadType == BidirStd) begin : gen_bidir
77                      
78         1/1              assign in_raw_o = ie ? inout_io : 1'bz;
           Tests:       T2 T27 T28 
79                          // input inversion
80         1/1              assign in_o = attr_i.invert ^ in_raw_o;
           Tests:       T2 T27 T28 
81                      
82                          // virtual open drain emulation
83                          logic oe, out;
84         1/1              assign out = out_i ^ attr_i.invert;
           Tests:       T27 T28 T40 
85         1/1              assign oe  = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
           Tests:       T2 T27 T28 
86                      
87                        // drive strength attributes are not supported by verilator
88                        `ifdef VERILATOR
89                          assign inout_io = (oe)   ? out : 1'bz;
90                        `else
91                          // different driver types
92         1/1              assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T2 T27 T28 
93         1/1              assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T2 T27 T28 
94                          // pullup / pulldown termination
95         1/1              assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
           Tests:       T21 T22 T23 

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[1].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T21,T22,T23
1	1	Covered	T1,T2,T3

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1

-1-	Status	Tests
0	Covered	T21,T22,T23
1	Covered	T1,T2,T3

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T2,T27,T28
0	1	Covered	T27,T28,T40
1	0	Covered	T21,T22,T23
1	1	Covered	T21,T22,T212

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T21,T22,T23
1	0	Covered	T27,T28,T40
1	1	Covered	T21,T22,T23

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T22,T23
1	1	Covered	T2,T27,T28

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T21,T22,T23
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T22,T23

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T22,T23
1	1	Covered	T21,T22,T23

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T21,T22,T23

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T21,T22,T23
1	0	Covered	T2,T27,T28
1	1	Covered	T21,T22,T23

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T27,T28

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T22,T23
1	1	Covered	T2,T27,T28

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T21,T22,T23

---

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[1].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	78	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	93	2	2	100.00
TERNARY	95	2	2	100.00

78             assign in_raw_o = ie ? inout_io : 1'bz;
                                    -1-  
                                    ==>  
                                    ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T21,T22,T23

92             assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                     -1-  
                                                                                     ==>  
                                                                                     ==>  

Branches:

-1-	Status	Tests
1	Covered	T21,T22,T23
0	Covered	T1,T2,T3

93             assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                      -1-  
                                                                                      ==>  
                                                                                      ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T27,T28
0	Covered	T1,T2,T3

95             assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
                                                                   -1-  
                                                                   ==>  
                                                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T21,T22,T23
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[1].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	1021	1021	0	0

AnalogNoScan_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1021	1021	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T65	1	1	0	0
T103	1	1	0	0
T104	1	1	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[2].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	95	1	1	100.00

38                        logic unused_sigs;
39         unreachable    assign unused_sigs = ^{attr_i.slew_rate,
40                                               attr_i.drive_strength[3:1],
41                                               attr_i.od_en,
42                                               attr_i.schmitt_en,
43                                               attr_i.keep_en,
44                                               scanmode_i,
45                                               pok_i};
46                        //VCS coverage on
47                        // pragma coverage on
48                      
49                        // Input enable (active-high)
50                        logic ie;
51         1/1            assign ie = ie_i & ~attr_i.input_disable;
           Tests:       T21 T22 T23 
52                      
53                        if (PadType == InputStd) begin : gen_input_only
54                          //VCS coverage off
55                          // pragma coverage off
56                          logic unused_in_sigs;
57                          assign unused_in_sigs = ^{out_i,
58                                                    oe_i,
59                                                    attr_i.virt_od_en,
60                                                    attr_i.drive_strength};
61                          //VCS coverage on
62                          // pragma coverage on
63                      
64                          assign in_raw_o = ie ? inout_io : 1'bz;
65                          // input inversion
66                          assign in_o = attr_i.invert ^ in_raw_o;
67                      
68                        // pulls are not supported by verilator
69                        `ifndef VERILATOR
70                          // pullup / pulldown termination
71                          assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72                        `endif
73                        end else if (PadType == BidirTol ||
74                                     PadType == DualBidirTol ||
75                                     PadType == BidirOd ||
76                                     PadType == BidirStd) begin : gen_bidir
77                      
78         1/1              assign in_raw_o = ie ? inout_io : 1'bz;
           Tests:       T2 T29 T27 
79                          // input inversion
80         1/1              assign in_o = attr_i.invert ^ in_raw_o;
           Tests:       T2 T29 T27 
81                      
82                          // virtual open drain emulation
83                          logic oe, out;
84         1/1              assign out = out_i ^ attr_i.invert;
           Tests:       T27 T28 T67 
85         1/1              assign oe  = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
           Tests:       T27 T28 T67 
86                      
87                        // drive strength attributes are not supported by verilator
88                        `ifdef VERILATOR
89                          assign inout_io = (oe)   ? out : 1'bz;
90                        `else
91                          // different driver types
92         1/1              assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T27 T28 T67 
93         1/1              assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T27 T28 T67 
94                          // pullup / pulldown termination
95         1/1              assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
           Tests:       T29 T45 T46 

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[2].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T21,T22,T23
1	1	Covered	T1,T2,T3

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1

-1-	Status	Tests
0	Covered	T21,T22,T23
1	Covered	T1,T2,T3

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T2,T27,T28
0	1	Covered	T2,T29,T27
1	0	Covered	T21,T22,T23
1	1	Covered	T21,T22,T23

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T21,T22,T23
1	0	Covered	T27,T28,T67
1	1	Covered	T21,T22,T23

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T22,T23
1	1	Covered	T27,T28,T67

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T21,T22,T23
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T22,T23

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T22,T23
1	1	Covered	T21,T22,T23

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T21,T22,T23

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T21,T22,T23
1	0	Covered	T27,T28,T67
1	1	Covered	T21,T22,T23

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T27,T28,T67

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T22,T23
1	1	Covered	T27,T28,T67

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T29,T45,T46

---

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[2].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	78	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	93	2	2	100.00
TERNARY	95	2	2	100.00

78             assign in_raw_o = ie ? inout_io : 1'bz;
                                    -1-  
                                    ==>  
                                    ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T21,T22,T23

92             assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                     -1-  
                                                                                     ==>  
                                                                                     ==>  

Branches:

-1-	Status	Tests
1	Covered	T21,T22,T23
0	Covered	T1,T2,T3

93             assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                      -1-  
                                                                                      ==>  
                                                                                      ==>  

Branches:

-1-	Status	Tests
1	Covered	T27,T28,T67
0	Covered	T1,T2,T3

95             assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
                                                                   -1-  
                                                                   ==>  
                                                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T29,T45,T46
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[2].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	1021	1021	0	0

AnalogNoScan_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1021	1021	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T65	1	1	0	0
T103	1	1	0	0
T104	1	1	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[3].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	95	1	1	100.00

38                        logic unused_sigs;
39         unreachable    assign unused_sigs = ^{attr_i.slew_rate,
40                                               attr_i.drive_strength[3:1],
41                                               attr_i.od_en,
42                                               attr_i.schmitt_en,
43                                               attr_i.keep_en,
44                                               scanmode_i,
45                                               pok_i};
46                        //VCS coverage on
47                        // pragma coverage on
48                      
49                        // Input enable (active-high)
50                        logic ie;
51         1/1            assign ie = ie_i & ~attr_i.input_disable;
           Tests:       T21 T22 T23 
52                      
53                        if (PadType == InputStd) begin : gen_input_only
54                          //VCS coverage off
55                          // pragma coverage off
56                          logic unused_in_sigs;
57                          assign unused_in_sigs = ^{out_i,
58                                                    oe_i,
59                                                    attr_i.virt_od_en,
60                                                    attr_i.drive_strength};
61                          //VCS coverage on
62                          // pragma coverage on
63                      
64                          assign in_raw_o = ie ? inout_io : 1'bz;
65                          // input inversion
66                          assign in_o = attr_i.invert ^ in_raw_o;
67                      
68                        // pulls are not supported by verilator
69                        `ifndef VERILATOR
70                          // pullup / pulldown termination
71                          assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72                        `endif
73                        end else if (PadType == BidirTol ||
74                                     PadType == DualBidirTol ||
75                                     PadType == BidirOd ||
76                                     PadType == BidirStd) begin : gen_bidir
77                      
78         1/1              assign in_raw_o = ie ? inout_io : 1'bz;
           Tests:       T2 T27 T28 
79                          // input inversion
80         1/1              assign in_o = attr_i.invert ^ in_raw_o;
           Tests:       T2 T27 T28 
81                      
82                          // virtual open drain emulation
83                          logic oe, out;
84         1/1              assign out = out_i ^ attr_i.invert;
           Tests:       T27 T28 T41 
85         1/1              assign oe  = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
           Tests:       T2 T27 T28 
86                      
87                        // drive strength attributes are not supported by verilator
88                        `ifdef VERILATOR
89                          assign inout_io = (oe)   ? out : 1'bz;
90                        `else
91                          // different driver types
92         1/1              assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T2 T27 T28 
93         1/1              assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T2 T27 T28 
94                          // pullup / pulldown termination
95         1/1              assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
           Tests:       T21 T22 T23 

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[3].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T21,T22,T23
1	1	Covered	T1,T2,T3

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1

-1-	Status	Tests
0	Covered	T21,T22,T23
1	Covered	T1,T2,T3

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T2,T27,T28
0	1	Covered	T27,T28,T41
1	0	Covered	T21,T22,T23
1	1	Covered	T21,T22,T23

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T21,T22,T23
1	0	Covered	T27,T28,T41
1	1	Covered	T21,T22,T23

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T22,T23
1	1	Covered	T2,T27,T28

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T21,T22,T23
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T22,T23

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T22,T23
1	1	Covered	T21,T22,T23

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T21,T22,T23

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T21,T22,T23
1	0	Covered	T2,T27,T28
1	1	Covered	T21,T22,T23

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T27,T28

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T22,T23
1	1	Covered	T2,T27,T28

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T21,T22,T23

---

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[3].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	78	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	93	2	2	100.00
TERNARY	95	2	2	100.00

78             assign in_raw_o = ie ? inout_io : 1'bz;
                                    -1-  
                                    ==>  
                                    ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T21,T22,T23

92             assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                     -1-  
                                                                                     ==>  
                                                                                     ==>  

Branches:

-1-	Status	Tests
1	Covered	T21,T22,T23
0	Covered	T1,T2,T3

93             assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                      -1-  
                                                                                      ==>  
                                                                                      ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T27,T28
0	Covered	T1,T2,T3

95             assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
                                                                   -1-  
                                                                   ==>  
                                                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T21,T22,T23
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[3].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	1021	1021	0	0

AnalogNoScan_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1021	1021	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T65	1	1	0	0
T103	1	1	0	0
T104	1	1	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[4].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	95	1	1	100.00

38                        logic unused_sigs;
39         unreachable    assign unused_sigs = ^{attr_i.slew_rate,
40                                               attr_i.drive_strength[3:1],
41                                               attr_i.od_en,
42                                               attr_i.schmitt_en,
43                                               attr_i.keep_en,
44                                               scanmode_i,
45                                               pok_i};
46                        //VCS coverage on
47                        // pragma coverage on
48                      
49                        // Input enable (active-high)
50                        logic ie;
51         1/1            assign ie = ie_i & ~attr_i.input_disable;
           Tests:       T21 T22 T23 
52                      
53                        if (PadType == InputStd) begin : gen_input_only
54                          //VCS coverage off
55                          // pragma coverage off
56                          logic unused_in_sigs;
57                          assign unused_in_sigs = ^{out_i,
58                                                    oe_i,
59                                                    attr_i.virt_od_en,
60                                                    attr_i.drive_strength};
61                          //VCS coverage on
62                          // pragma coverage on
63                      
64                          assign in_raw_o = ie ? inout_io : 1'bz;
65                          // input inversion
66                          assign in_o = attr_i.invert ^ in_raw_o;
67                      
68                        // pulls are not supported by verilator
69                        `ifndef VERILATOR
70                          // pullup / pulldown termination
71                          assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72                        `endif
73                        end else if (PadType == BidirTol ||
74                                     PadType == DualBidirTol ||
75                                     PadType == BidirOd ||
76                                     PadType == BidirStd) begin : gen_bidir
77                      
78         1/1              assign in_raw_o = ie ? inout_io : 1'bz;
           Tests:       T2 T27 T28 
79                          // input inversion
80         1/1              assign in_o = attr_i.invert ^ in_raw_o;
           Tests:       T2 T27 T28 
81                      
82                          // virtual open drain emulation
83                          logic oe, out;
84         1/1              assign out = out_i ^ attr_i.invert;
           Tests:       T27 T28 T41 
85         1/1              assign oe  = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
           Tests:       T27 T28 T41 
86                      
87                        // drive strength attributes are not supported by verilator
88                        `ifdef VERILATOR
89                          assign inout_io = (oe)   ? out : 1'bz;
90                        `else
91                          // different driver types
92         1/1              assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T27 T28 T41 
93         1/1              assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T27 T28 T41 
94                          // pullup / pulldown termination
95         1/1              assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
           Tests:       T21 T22 T23 

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[4].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T21,T22,T23
1	1	Covered	T1,T2,T3

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1

-1-	Status	Tests
0	Covered	T21,T22,T23
1	Covered	T1,T2,T3

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T2,T27,T28
0	1	Covered	T2,T27,T28
1	0	Covered	T21,T22,T23
1	1	Covered	T21,T22,T23

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T21,T22,T23
1	0	Covered	T27,T28,T41
1	1	Covered	T21,T22,T23

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T22,T23
1	1	Covered	T27,T28,T41

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T21,T22,T23
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T22,T23

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T22,T23
1	1	Covered	T21,T22,T23

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T21,T22,T23

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T21,T22,T23
1	0	Covered	T27,T28,T41
1	1	Covered	T21,T22,T23

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T27,T28,T41

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T22,T23
1	1	Covered	T27,T28,T41

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T21,T22,T23

---

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[4].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	78	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	93	2	2	100.00
TERNARY	95	2	2	100.00

78             assign in_raw_o = ie ? inout_io : 1'bz;
                                    -1-  
                                    ==>  
                                    ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T21,T22,T23

92             assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                     -1-  
                                                                                     ==>  
                                                                                     ==>  

Branches:

-1-	Status	Tests
1	Covered	T21,T22,T23
0	Covered	T1,T2,T3

93             assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                      -1-  
                                                                                      ==>  
                                                                                      ==>  

Branches:

-1-	Status	Tests
1	Covered	T27,T28,T41
0	Covered	T1,T2,T3

95             assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
                                                                   -1-  
                                                                   ==>  
                                                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T21,T22,T23
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[4].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	1021	1021	0	0

AnalogNoScan_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1021	1021	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T65	1	1	0	0
T103	1	1	0	0
T104	1	1	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[5].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	95	1	1	100.00

38                        logic unused_sigs;
39         unreachable    assign unused_sigs = ^{attr_i.slew_rate,
40                                               attr_i.drive_strength[3:1],
41                                               attr_i.od_en,
42                                               attr_i.schmitt_en,
43                                               attr_i.keep_en,
44                                               scanmode_i,
45                                               pok_i};
46                        //VCS coverage on
47                        // pragma coverage on
48                      
49                        // Input enable (active-high)
50                        logic ie;
51         1/1            assign ie = ie_i & ~attr_i.input_disable;
           Tests:       T21 T22 T23 
52                      
53                        if (PadType == InputStd) begin : gen_input_only
54                          //VCS coverage off
55                          // pragma coverage off
56                          logic unused_in_sigs;
57                          assign unused_in_sigs = ^{out_i,
58                                                    oe_i,
59                                                    attr_i.virt_od_en,
60                                                    attr_i.drive_strength};
61                          //VCS coverage on
62                          // pragma coverage on
63                      
64                          assign in_raw_o = ie ? inout_io : 1'bz;
65                          // input inversion
66                          assign in_o = attr_i.invert ^ in_raw_o;
67                      
68                        // pulls are not supported by verilator
69                        `ifndef VERILATOR
70                          // pullup / pulldown termination
71                          assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72                        `endif
73                        end else if (PadType == BidirTol ||
74                                     PadType == DualBidirTol ||
75                                     PadType == BidirOd ||
76                                     PadType == BidirStd) begin : gen_bidir
77                      
78         1/1              assign in_raw_o = ie ? inout_io : 1'bz;
           Tests:       T2 T27 T28 
79                          // input inversion
80         1/1              assign in_o = attr_i.invert ^ in_raw_o;
           Tests:       T2 T27 T28 
81                      
82                          // virtual open drain emulation
83                          logic oe, out;
84         1/1              assign out = out_i ^ attr_i.invert;
           Tests:       T2 T27 T28 
85         1/1              assign oe  = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
           Tests:       T2 T27 T28 
86                      
87                        // drive strength attributes are not supported by verilator
88                        `ifdef VERILATOR
89                          assign inout_io = (oe)   ? out : 1'bz;
90                        `else
91                          // different driver types
92         1/1              assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T2 T27 T28 
93         1/1              assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T2 T27 T28 
94                          // pullup / pulldown termination
95         1/1              assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
           Tests:       T21 T22 T23 

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[5].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T21,T22,T23
1	1	Covered	T1,T2,T3

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1

-1-	Status	Tests
0	Covered	T21,T22,T23
1	Covered	T1,T2,T3

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T27,T28,T59
0	1	Covered	T2,T27,T28
1	0	Covered	T21,T22,T23
1	1	Covered	T21,T22,T23

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T21,T22,T23
1	0	Covered	T2,T27,T28
1	1	Covered	T21,T22,T23

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T22,T23
1	1	Covered	T2,T27,T28

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T21,T22,T23
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T22,T23

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T22,T23
1	1	Covered	T21,T22,T23

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T21,T22,T23

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T21,T22,T23
1	0	Covered	T2,T27,T28
1	1	Covered	T21,T22,T23

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T27,T28

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T22,T23
1	1	Covered	T2,T27,T28

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T21,T22,T23

---

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[5].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	78	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	93	2	2	100.00
TERNARY	95	2	2	100.00

78             assign in_raw_o = ie ? inout_io : 1'bz;
                                    -1-  
                                    ==>  
                                    ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T21,T22,T23

92             assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                     -1-  
                                                                                     ==>  
                                                                                     ==>  

Branches:

-1-	Status	Tests
1	Covered	T21,T22,T23
0	Covered	T1,T2,T3

93             assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                      -1-  
                                                                                      ==>  
                                                                                      ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T27,T28
0	Covered	T1,T2,T3

95             assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
                                                                   -1-  
                                                                   ==>  
                                                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T21,T22,T23
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[5].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	1021	1021	0	0

AnalogNoScan_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1021	1021	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T65	1	1	0	0
T103	1	1	0	0
T104	1	1	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[6].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	95	1	1	100.00

38                        logic unused_sigs;
39         unreachable    assign unused_sigs = ^{attr_i.slew_rate,
40                                               attr_i.drive_strength[3:1],
41                                               attr_i.od_en,
42                                               attr_i.schmitt_en,
43                                               attr_i.keep_en,
44                                               scanmode_i,
45                                               pok_i};
46                        //VCS coverage on
47                        // pragma coverage on
48                      
49                        // Input enable (active-high)
50                        logic ie;
51         1/1            assign ie = ie_i & ~attr_i.input_disable;
           Tests:       T21 T22 T23 
52                      
53                        if (PadType == InputStd) begin : gen_input_only
54                          //VCS coverage off
55                          // pragma coverage off
56                          logic unused_in_sigs;
57                          assign unused_in_sigs = ^{out_i,
58                                                    oe_i,
59                                                    attr_i.virt_od_en,
60                                                    attr_i.drive_strength};
61                          //VCS coverage on
62                          // pragma coverage on
63                      
64                          assign in_raw_o = ie ? inout_io : 1'bz;
65                          // input inversion
66                          assign in_o = attr_i.invert ^ in_raw_o;
67                      
68                        // pulls are not supported by verilator
69                        `ifndef VERILATOR
70                          // pullup / pulldown termination
71                          assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72                        `endif
73                        end else if (PadType == BidirTol ||
74                                     PadType == DualBidirTol ||
75                                     PadType == BidirOd ||
76                                     PadType == BidirStd) begin : gen_bidir
77                      
78         1/1              assign in_raw_o = ie ? inout_io : 1'bz;
           Tests:       T2 T27 T28 
79                          // input inversion
80         1/1              assign in_o = attr_i.invert ^ in_raw_o;
           Tests:       T2 T27 T28 
81                      
82                          // virtual open drain emulation
83                          logic oe, out;
84         1/1              assign out = out_i ^ attr_i.invert;
           Tests:       T27 T28 T41 
85         1/1              assign oe  = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
           Tests:       T27 T28 T41 
86                      
87                        // drive strength attributes are not supported by verilator
88                        `ifdef VERILATOR
89                          assign inout_io = (oe)   ? out : 1'bz;
90                        `else
91                          // different driver types
92         1/1              assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T27 T28 T41 
93         1/1              assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T27 T28 T41 
94                          // pullup / pulldown termination
95         1/1              assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
           Tests:       T21 T22 T23 

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[6].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T21,T22,T23
1	1	Covered	T1,T2,T3

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1

-1-	Status	Tests
0	Covered	T21,T22,T23
1	Covered	T1,T2,T3

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T2,T27,T28
0	1	Covered	T2,T27,T28
1	0	Covered	T21,T22,T23
1	1	Covered	T21,T22,T23

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T21,T22,T23
1	0	Covered	T27,T28,T41
1	1	Covered	T21,T22,T23

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T23,T212
1	1	Covered	T27,T28,T41

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T21,T22,T23
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T22,T23

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T22,T23
1	1	Covered	T21,T22,T23

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T21,T22,T23

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T21,T22,T23
1	0	Covered	T27,T28,T41
1	1	Covered	T21,T22,T23

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T27,T28,T41

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T22,T23
1	1	Covered	T27,T28,T41

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T21,T22,T23

---

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[6].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	78	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	93	2	2	100.00
TERNARY	95	2	2	100.00

78             assign in_raw_o = ie ? inout_io : 1'bz;
                                    -1-  
                                    ==>  
                                    ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T21,T22,T23

92             assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                     -1-  
                                                                                     ==>  
                                                                                     ==>  

Branches:

-1-	Status	Tests
1	Covered	T21,T22,T23
0	Covered	T1,T2,T3

93             assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                      -1-  
                                                                                      ==>  
                                                                                      ==>  

Branches:

-1-	Status	Tests
1	Covered	T27,T28,T41
0	Covered	T1,T2,T3

95             assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
                                                                   -1-  
                                                                   ==>  
                                                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T21,T22,T23
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[6].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	1021	1021	0	0

AnalogNoScan_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1021	1021	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T65	1	1	0	0
T103	1	1	0	0
T104	1	1	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[7].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	95	1	1	100.00

38                        logic unused_sigs;
39         unreachable    assign unused_sigs = ^{attr_i.slew_rate,
40                                               attr_i.drive_strength[3:1],
41                                               attr_i.od_en,
42                                               attr_i.schmitt_en,
43                                               attr_i.keep_en,
44                                               scanmode_i,
45                                               pok_i};
46                        //VCS coverage on
47                        // pragma coverage on
48                      
49                        // Input enable (active-high)
50                        logic ie;
51         1/1            assign ie = ie_i & ~attr_i.input_disable;
           Tests:       T21 T22 T23 
52                      
53                        if (PadType == InputStd) begin : gen_input_only
54                          //VCS coverage off
55                          // pragma coverage off
56                          logic unused_in_sigs;
57                          assign unused_in_sigs = ^{out_i,
58                                                    oe_i,
59                                                    attr_i.virt_od_en,
60                                                    attr_i.drive_strength};
61                          //VCS coverage on
62                          // pragma coverage on
63                      
64                          assign in_raw_o = ie ? inout_io : 1'bz;
65                          // input inversion
66                          assign in_o = attr_i.invert ^ in_raw_o;
67                      
68                        // pulls are not supported by verilator
69                        `ifndef VERILATOR
70                          // pullup / pulldown termination
71                          assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72                        `endif
73                        end else if (PadType == BidirTol ||
74                                     PadType == DualBidirTol ||
75                                     PadType == BidirOd ||
76                                     PadType == BidirStd) begin : gen_bidir
77                      
78         1/1              assign in_raw_o = ie ? inout_io : 1'bz;
           Tests:       T2 T5 T27 
79                          // input inversion
80         1/1              assign in_o = attr_i.invert ^ in_raw_o;
           Tests:       T2 T5 T27 
81                      
82                          // virtual open drain emulation
83                          logic oe, out;
84         1/1              assign out = out_i ^ attr_i.invert;
           Tests:       T2 T27 T28 
85         1/1              assign oe  = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
           Tests:       T2 T5 T27 
86                      
87                        // drive strength attributes are not supported by verilator
88                        `ifdef VERILATOR
89                          assign inout_io = (oe)   ? out : 1'bz;
90                        `else
91                          // different driver types
92         1/1              assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T2 T5 T27 
93         1/1              assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T2 T5 T27 
94                          // pullup / pulldown termination
95         1/1              assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
           Tests:       T13 T49 T50 

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[7].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T21,T22,T23
1	1	Covered	T1,T2,T3

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1

-1-	Status	Tests
0	Covered	T21,T22,T23
1	Covered	T1,T2,T3

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T27,T55
0	1	Covered	T2,T27,T55
1	0	Covered	T21,T22,T23
1	1	Covered	T21,T22,T23

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T21,T22,T23
1	0	Covered	T2,T27,T28
1	1	Covered	T21,T22,T23

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T22,T23
1	1	Covered	T2,T5,T27

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T21,T22,T23
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T22,T23

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T22,T23
1	1	Covered	T21,T22,T23

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T21,T22,T23

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T21,T22,T23
1	0	Covered	T2,T5,T27
1	1	Covered	T21,T22,T23

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T27

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T22,T23
1	1	Covered	T2,T5,T27

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T49,T50

---

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[7].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	78	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	93	2	2	100.00
TERNARY	95	2	2	100.00

78             assign in_raw_o = ie ? inout_io : 1'bz;
                                    -1-  
                                    ==>  
                                    ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T21,T22,T23

92             assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                     -1-  
                                                                                     ==>  
                                                                                     ==>  

Branches:

-1-	Status	Tests
1	Covered	T21,T22,T23
0	Covered	T1,T2,T3

93             assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                      -1-  
                                                                                      ==>  
                                                                                      ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T5,T27
0	Covered	T1,T2,T3

95             assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
                                                                   -1-  
                                                                   ==>  
                                                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T13,T49,T50
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[7].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	1021	1021	0	0

AnalogNoScan_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1021	1021	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T65	1	1	0	0
T103	1	1	0	0
T104	1	1	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[8].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	95	1	1	100.00

38                        logic unused_sigs;
39         unreachable    assign unused_sigs = ^{attr_i.slew_rate,
40                                               attr_i.drive_strength[3:1],
41                                               attr_i.od_en,
42                                               attr_i.schmitt_en,
43                                               attr_i.keep_en,
44                                               scanmode_i,
45                                               pok_i};
46                        //VCS coverage on
47                        // pragma coverage on
48                      
49                        // Input enable (active-high)
50                        logic ie;
51         1/1            assign ie = ie_i & ~attr_i.input_disable;
           Tests:       T21 T22 T23 
52                      
53                        if (PadType == InputStd) begin : gen_input_only
54                          //VCS coverage off
55                          // pragma coverage off
56                          logic unused_in_sigs;
57                          assign unused_in_sigs = ^{out_i,
58                                                    oe_i,
59                                                    attr_i.virt_od_en,
60                                                    attr_i.drive_strength};
61                          //VCS coverage on
62                          // pragma coverage on
63                      
64                          assign in_raw_o = ie ? inout_io : 1'bz;
65                          // input inversion
66                          assign in_o = attr_i.invert ^ in_raw_o;
67                      
68                        // pulls are not supported by verilator
69                        `ifndef VERILATOR
70                          // pullup / pulldown termination
71                          assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72                        `endif
73                        end else if (PadType == BidirTol ||
74                                     PadType == DualBidirTol ||
75                                     PadType == BidirOd ||
76                                     PadType == BidirStd) begin : gen_bidir
77                      
78         1/1              assign in_raw_o = ie ? inout_io : 1'bz;
           Tests:       T2 T5 T27 
79                          // input inversion
80         1/1              assign in_o = attr_i.invert ^ in_raw_o;
           Tests:       T2 T5 T27 
81                      
82                          // virtual open drain emulation
83                          logic oe, out;
84         1/1              assign out = out_i ^ attr_i.invert;
           Tests:       T2 T28 T41 
85         1/1              assign oe  = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
           Tests:       T2 T55 T28 
86                      
87                        // drive strength attributes are not supported by verilator
88                        `ifdef VERILATOR
89                          assign inout_io = (oe)   ? out : 1'bz;
90                        `else
91                          // different driver types
92         1/1              assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T2 T55 T28 
93         1/1              assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T2 T55 T28 
94                          // pullup / pulldown termination
95         1/1              assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
           Tests:       T21 T22 T23 

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[8].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T21,T22,T23
1	1	Covered	T1,T2,T3

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1

-1-	Status	Tests
0	Covered	T21,T22,T23
1	Covered	T1,T2,T3

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T27,T55
0	1	Covered	T2,T5,T27
1	0	Covered	T22,T23,T212
1	1	Covered	T22,T23,T212

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T21,T22,T23
1	0	Covered	T2,T28,T41
1	1	Covered	T21,T22,T23

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T22,T23
1	1	Covered	T2,T55,T28

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T21,T22,T23
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T22,T23

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T22,T23
1	1	Covered	T21,T22,T23

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T21,T22,T23

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T21,T22,T23
1	0	Covered	T2,T55,T28
1	1	Covered	T21,T22,T23

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T55,T28

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T22,T23
1	1	Covered	T2,T55,T28

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T21,T22,T23

---

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[8].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	78	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	93	2	2	100.00
TERNARY	95	2	2	100.00

78             assign in_raw_o = ie ? inout_io : 1'bz;
                                    -1-  
                                    ==>  
                                    ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T21,T22,T23

92             assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                     -1-  
                                                                                     ==>  
                                                                                     ==>  

Branches:

-1-	Status	Tests
1	Covered	T21,T22,T23
0	Covered	T1,T2,T3

93             assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                      -1-  
                                                                                      ==>  
                                                                                      ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T55,T28
0	Covered	T1,T2,T3

95             assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
                                                                   -1-  
                                                                   ==>  
                                                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T21,T22,T23
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[8].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	1021	1021	0	0

AnalogNoScan_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1021	1021	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T65	1	1	0	0
T103	1	1	0	0
T104	1	1	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	95	1	1	100.00

38                        logic unused_sigs;
39         unreachable    assign unused_sigs = ^{attr_i.slew_rate,
40                                               attr_i.drive_strength[3:1],
41                                               attr_i.od_en,
42                                               attr_i.schmitt_en,
43                                               attr_i.keep_en,
44                                               scanmode_i,
45                                               pok_i};
46                        //VCS coverage on
47                        // pragma coverage on
48                      
49                        // Input enable (active-high)
50                        logic ie;
51         1/1            assign ie = ie_i & ~attr_i.input_disable;
           Tests:       T21 T22 T23 
52                      
53                        if (PadType == InputStd) begin : gen_input_only
54                          //VCS coverage off
55                          // pragma coverage off
56                          logic unused_in_sigs;
57                          assign unused_in_sigs = ^{out_i,
58                                                    oe_i,
59                                                    attr_i.virt_od_en,
60                                                    attr_i.drive_strength};
61                          //VCS coverage on
62                          // pragma coverage on
63                      
64                          assign in_raw_o = ie ? inout_io : 1'bz;
65                          // input inversion
66                          assign in_o = attr_i.invert ^ in_raw_o;
67                      
68                        // pulls are not supported by verilator
69                        `ifndef VERILATOR
70                          // pullup / pulldown termination
71                          assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72                        `endif
73                        end else if (PadType == BidirTol ||
74                                     PadType == DualBidirTol ||
75                                     PadType == BidirOd ||
76                                     PadType == BidirStd) begin : gen_bidir
77                      
78         1/1              assign in_raw_o = ie ? inout_io : 1'bz;
           Tests:       T2 T29 T36 
79                          // input inversion
80         1/1              assign in_o = attr_i.invert ^ in_raw_o;
           Tests:       T2 T29 T36 
81                      
82                          // virtual open drain emulation
83                          logic oe, out;
84         1/1              assign out = out_i ^ attr_i.invert;
           Tests:       T29 T10 T11 
85         1/1              assign oe  = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
           Tests:       T2 T29 T10 
86                      
87                        // drive strength attributes are not supported by verilator
88                        `ifdef VERILATOR
89                          assign inout_io = (oe)   ? out : 1'bz;
90                        `else
91                          // different driver types
92         1/1              assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T2 T29 T10 
93         1/1              assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T2 T29 T10 
94                          // pullup / pulldown termination
95         1/1              assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
           Tests:       T29 T45 T46 

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T21,T22,T23
1	1	Covered	T1,T2,T3

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1

-1-	Status	Tests
0	Covered	T21,T22,T23
1	Covered	T1,T2,T3

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T2,T29,T36
0	1	Covered	T29,T12,T39
1	0	Covered	T21,T22,T23
1	1	Covered	T21,T22,T23

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T21,T22,T23
1	0	Covered	T29,T10,T11
1	1	Covered	T21,T22,T23

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T22,T23
1	1	Covered	T2,T29,T12

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T21,T22,T23
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T22,T23

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T22,T23
1	1	Covered	T21,T22,T23

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T21,T22,T23

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T21,T22,T23
1	0	Covered	T2,T29,T12
1	1	Covered	T21,T22,T23

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T29,T12

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T22,T23
1	1	Covered	T2,T29,T12

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T29,T45,T46

---

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	78	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	93	2	2	100.00
TERNARY	95	2	2	100.00

78             assign in_raw_o = ie ? inout_io : 1'bz;
                                    -1-  
                                    ==>  
                                    ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T21,T22,T23

92             assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                     -1-  
                                                                                     ==>  
                                                                                     ==>  

Branches:

-1-	Status	Tests
1	Covered	T21,T22,T23
0	Covered	T1,T2,T3

93             assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                      -1-  
                                                                                      ==>  
                                                                                      ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T29,T12
0	Covered	T1,T2,T3

95             assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
                                                                   -1-  
                                                                   ==>  
                                                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T29,T45,T46
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	1021	1021	0	0

AnalogNoScan_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1021	1021	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T65	1	1	0	0
T103	1	1	0	0
T104	1	1	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	95	1	1	100.00

38                        logic unused_sigs;
39         unreachable    assign unused_sigs = ^{attr_i.slew_rate,
40                                               attr_i.drive_strength[3:1],
41                                               attr_i.od_en,
42                                               attr_i.schmitt_en,
43                                               attr_i.keep_en,
44                                               scanmode_i,
45                                               pok_i};
46                        //VCS coverage on
47                        // pragma coverage on
48                      
49                        // Input enable (active-high)
50                        logic ie;
51         1/1            assign ie = ie_i & ~attr_i.input_disable;
           Tests:       T21 T22 T23 
52                      
53                        if (PadType == InputStd) begin : gen_input_only
54                          //VCS coverage off
55                          // pragma coverage off
56                          logic unused_in_sigs;
57                          assign unused_in_sigs = ^{out_i,
58                                                    oe_i,
59                                                    attr_i.virt_od_en,
60                                                    attr_i.drive_strength};
61                          //VCS coverage on
62                          // pragma coverage on
63                      
64                          assign in_raw_o = ie ? inout_io : 1'bz;
65                          // input inversion
66                          assign in_o = attr_i.invert ^ in_raw_o;
67                      
68                        // pulls are not supported by verilator
69                        `ifndef VERILATOR
70                          // pullup / pulldown termination
71                          assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72                        `endif
73                        end else if (PadType == BidirTol ||
74                                     PadType == DualBidirTol ||
75                                     PadType == BidirOd ||
76                                     PadType == BidirStd) begin : gen_bidir
77                      
78         1/1              assign in_raw_o = ie ? inout_io : 1'bz;
           Tests:       T2 T29 T10 
79                          // input inversion
80         1/1              assign in_o = attr_i.invert ^ in_raw_o;
           Tests:       T2 T29 T10 
81                      
82                          // virtual open drain emulation
83                          logic oe, out;
84         1/1              assign out = out_i ^ attr_i.invert;
           Tests:       T29 T12 T45 
85         1/1              assign oe  = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
           Tests:       T2 T29 T12 
86                      
87                        // drive strength attributes are not supported by verilator
88                        `ifdef VERILATOR
89                          assign inout_io = (oe)   ? out : 1'bz;
90                        `else
91                          // different driver types
92         1/1              assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T2 T29 T12 
93         1/1              assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T2 T29 T12 
94                          // pullup / pulldown termination
95         1/1              assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
           Tests:       T29 T10 T11 

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T21,T22,T23
1	1	Covered	T1,T2,T3

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1

-1-	Status	Tests
0	Covered	T21,T22,T23
1	Covered	T1,T2,T3

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T2,T29,T36
0	1	Covered	T29,T10,T11
1	0	Covered	T21,T22,T23
1	1	Covered	T21,T22,T23

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T21,T22,T23
1	0	Covered	T29,T12,T45
1	1	Covered	T21,T22,T23

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T22,T23
1	1	Covered	T2,T29,T12

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T21,T22,T23
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T22,T23

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T22,T23
1	1	Covered	T21,T22,T23

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T21,T22,T23

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T21,T22,T23
1	0	Covered	T2,T29,T12
1	1	Covered	T21,T22,T23

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T29,T12

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T22,T23
1	1	Covered	T2,T29,T12

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T29,T10,T11

---

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	78	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	93	2	2	100.00
TERNARY	95	2	2	100.00

78             assign in_raw_o = ie ? inout_io : 1'bz;
                                    -1-  
                                    ==>  
                                    ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T21,T22,T23

92             assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                     -1-  
                                                                                     ==>  
                                                                                     ==>  

Branches:

-1-	Status	Tests
1	Covered	T21,T22,T23
0	Covered	T1,T2,T3

93             assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                      -1-  
                                                                                      ==>  
                                                                                      ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T29,T12
0	Covered	T1,T2,T3

95             assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
                                                                   -1-  
                                                                   ==>  
                                                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T29,T10,T11
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	1021	1021	0	0

AnalogNoScan_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1021	1021	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T65	1	1	0	0
T103	1	1	0	0
T104	1	1	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	95	1	1	100.00

38                        logic unused_sigs;
39         unreachable    assign unused_sigs = ^{attr_i.slew_rate,
40                                               attr_i.drive_strength[3:1],
41                                               attr_i.od_en,
42                                               attr_i.schmitt_en,
43                                               attr_i.keep_en,
44                                               scanmode_i,
45                                               pok_i};
46                        //VCS coverage on
47                        // pragma coverage on
48                      
49                        // Input enable (active-high)
50                        logic ie;
51         1/1            assign ie = ie_i & ~attr_i.input_disable;
           Tests:       T21 T22 T23 
52                      
53                        if (PadType == InputStd) begin : gen_input_only
54                          //VCS coverage off
55                          // pragma coverage off
56                          logic unused_in_sigs;
57                          assign unused_in_sigs = ^{out_i,
58                                                    oe_i,
59                                                    attr_i.virt_od_en,
60                                                    attr_i.drive_strength};
61                          //VCS coverage on
62                          // pragma coverage on
63                      
64                          assign in_raw_o = ie ? inout_io : 1'bz;
65                          // input inversion
66                          assign in_o = attr_i.invert ^ in_raw_o;
67                      
68                        // pulls are not supported by verilator
69                        `ifndef VERILATOR
70                          // pullup / pulldown termination
71                          assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72                        `endif
73                        end else if (PadType == BidirTol ||
74                                     PadType == DualBidirTol ||
75                                     PadType == BidirOd ||
76                                     PadType == BidirStd) begin : gen_bidir
77                      
78         1/1              assign in_raw_o = ie ? inout_io : 1'bz;
           Tests:       T2 T5 T36 
79                          // input inversion
80         1/1              assign in_o = attr_i.invert ^ in_raw_o;
           Tests:       T2 T5 T36 
81                      
82                          // virtual open drain emulation
83                          logic oe, out;
84         1/1              assign out = out_i ^ attr_i.invert;
           Tests:       T12 T68 T126 
85         1/1              assign oe  = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
           Tests:       T12 T20 T68 
86                      
87                        // drive strength attributes are not supported by verilator
88                        `ifdef VERILATOR
89                          assign inout_io = (oe)   ? out : 1'bz;
90                        `else
91                          // different driver types
92         1/1              assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T12 T20 T68 
93         1/1              assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T12 T20 T68 
94                          // pullup / pulldown termination
95         1/1              assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
           Tests:       T21 T22 T23 

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T21,T22,T23
1	1	Covered	T1,T2,T3

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1

-1-	Status	Tests
0	Covered	T21,T22,T23
1	Covered	T1,T2,T3

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T2,T5,T36
0	1	Covered	T2,T12,T39
1	0	Covered	T21,T22,T23
1	1	Covered	T21,T22,T23

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T21,T22,T23
1	0	Covered	T12,T68,T126
1	1	Covered	T21,T22,T23

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T22,T23
1	1	Covered	T12,T20,T68

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T21,T22,T23
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T22,T23

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T22,T23
1	1	Covered	T21,T22,T23

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T21,T22,T23

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T21,T22,T23
1	0	Covered	T12,T20,T68
1	1	Covered	T21,T22,T23

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T12,T20,T68

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T22,T23
1	1	Covered	T12,T20,T68

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T21,T22,T23

---

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	78	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	93	2	2	100.00
TERNARY	95	2	2	100.00

78             assign in_raw_o = ie ? inout_io : 1'bz;
                                    -1-  
                                    ==>  
                                    ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T21,T22,T23

92             assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                     -1-  
                                                                                     ==>  
                                                                                     ==>  

Branches:

-1-	Status	Tests
1	Covered	T21,T22,T23
0	Covered	T1,T2,T3

93             assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                      -1-  
                                                                                      ==>  
                                                                                      ==>  

Branches:

-1-	Status	Tests
1	Covered	T12,T20,T68
0	Covered	T1,T2,T3

95             assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
                                                                   -1-  
                                                                   ==>  
                                                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T21,T22,T23
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	1021	1021	0	0

AnalogNoScan_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1021	1021	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T65	1	1	0	0
T103	1	1	0	0
T104	1	1	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	95	1	1	100.00

38                        logic unused_sigs;
39         unreachable    assign unused_sigs = ^{attr_i.slew_rate,
40                                               attr_i.drive_strength[3:1],
41                                               attr_i.od_en,
42                                               attr_i.schmitt_en,
43                                               attr_i.keep_en,
44                                               scanmode_i,
45                                               pok_i};
46                        //VCS coverage on
47                        // pragma coverage on
48                      
49                        // Input enable (active-high)
50                        logic ie;
51         1/1            assign ie = ie_i & ~attr_i.input_disable;
           Tests:       T21 T22 T23 
52                      
53                        if (PadType == InputStd) begin : gen_input_only
54                          //VCS coverage off
55                          // pragma coverage off
56                          logic unused_in_sigs;
57                          assign unused_in_sigs = ^{out_i,
58                                                    oe_i,
59                                                    attr_i.virt_od_en,
60                                                    attr_i.drive_strength};
61                          //VCS coverage on
62                          // pragma coverage on
63                      
64                          assign in_raw_o = ie ? inout_io : 1'bz;
65                          // input inversion
66                          assign in_o = attr_i.invert ^ in_raw_o;
67                      
68                        // pulls are not supported by verilator
69                        `ifndef VERILATOR
70                          // pullup / pulldown termination
71                          assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72                        `endif
73                        end else if (PadType == BidirTol ||
74                                     PadType == DualBidirTol ||
75                                     PadType == BidirOd ||
76                                     PadType == BidirStd) begin : gen_bidir
77                      
78         1/1              assign in_raw_o = ie ? inout_io : 1'bz;
           Tests:       T2 T29 T10 
79                          // input inversion
80         1/1              assign in_o = attr_i.invert ^ in_raw_o;
           Tests:       T2 T29 T10 
81                      
82                          // virtual open drain emulation
83                          logic oe, out;
84         1/1              assign out = out_i ^ attr_i.invert;
           Tests:       T2 T29 T39 
85         1/1              assign oe  = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
           Tests:       T2 T29 T12 
86                      
87                        // drive strength attributes are not supported by verilator
88                        `ifdef VERILATOR
89                          assign inout_io = (oe)   ? out : 1'bz;
90                        `else
91                          // different driver types
92         1/1              assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T2 T29 T12 
93         1/1              assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T2 T29 T12 
94                          // pullup / pulldown termination
95         1/1              assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
           Tests:       T29 T10 T11 

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T21,T22,T23
1	1	Covered	T1,T2,T3

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1

-1-	Status	Tests
0	Covered	T21,T22,T23
1	Covered	T1,T2,T3

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T29,T14,T62
0	1	Covered	T2,T29,T10
1	0	Covered	T21,T22,T23
1	1	Covered	T21,T22,T23

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T21,T22,T23
1	0	Covered	T2,T29,T39
1	1	Covered	T21,T22,T23

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T22,T23
1	1	Covered	T2,T29,T12

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T21,T22,T23
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T22,T23

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T22,T23
1	1	Covered	T21,T22,T23

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T21,T22,T23

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T21,T22,T23
1	0	Covered	T2,T29,T12
1	1	Covered	T21,T22,T23

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T29,T12

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T22,T23
1	1	Covered	T2,T29,T12

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T29,T10,T11

---

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	78	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	93	2	2	100.00
TERNARY	95	2	2	100.00

78             assign in_raw_o = ie ? inout_io : 1'bz;
                                    -1-  
                                    ==>  
                                    ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T21,T22,T23

92             assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                     -1-  
                                                                                     ==>  
                                                                                     ==>  

Branches:

-1-	Status	Tests
1	Covered	T21,T22,T23
0	Covered	T1,T2,T3

93             assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                      -1-  
                                                                                      ==>  
                                                                                      ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T29,T12
0	Covered	T1,T2,T3

95             assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
                                                                   -1-  
                                                                   ==>  
                                                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T29,T10,T11
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	1021	1021	0	0

AnalogNoScan_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1021	1021	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T65	1	1	0	0
T103	1	1	0	0
T104	1	1	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[13].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	95	1	1	100.00

38                        logic unused_sigs;
39         unreachable    assign unused_sigs = ^{attr_i.slew_rate,
40                                               attr_i.drive_strength[3:1],
41                                               attr_i.od_en,
42                                               attr_i.schmitt_en,
43                                               attr_i.keep_en,
44                                               scanmode_i,
45                                               pok_i};
46                        //VCS coverage on
47                        // pragma coverage on
48                      
49                        // Input enable (active-high)
50                        logic ie;
51         1/1            assign ie = ie_i & ~attr_i.input_disable;
           Tests:       T21 T22 T23 
52                      
53                        if (PadType == InputStd) begin : gen_input_only
54                          //VCS coverage off
55                          // pragma coverage off
56                          logic unused_in_sigs;
57                          assign unused_in_sigs = ^{out_i,
58                                                    oe_i,
59                                                    attr_i.virt_od_en,
60                                                    attr_i.drive_strength};
61                          //VCS coverage on
62                          // pragma coverage on
63                      
64                          assign in_raw_o = ie ? inout_io : 1'bz;
65                          // input inversion
66                          assign in_o = attr_i.invert ^ in_raw_o;
67                      
68                        // pulls are not supported by verilator
69                        `ifndef VERILATOR
70                          // pullup / pulldown termination
71                          assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72                        `endif
73                        end else if (PadType == BidirTol ||
74                                     PadType == DualBidirTol ||
75                                     PadType == BidirOd ||
76                                     PadType == BidirStd) begin : gen_bidir
77                      
78         1/1              assign in_raw_o = ie ? inout_io : 1'bz;
           Tests:       T2 T5 T29 
79                          // input inversion
80         1/1              assign in_o = attr_i.invert ^ in_raw_o;
           Tests:       T2 T5 T29 
81                      
82                          // virtual open drain emulation
83                          logic oe, out;
84         1/1              assign out = out_i ^ attr_i.invert;
           Tests:       T12 T39 T68 
85         1/1              assign oe  = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
           Tests:       T12 T39 T20 
86                      
87                        // drive strength attributes are not supported by verilator
88                        `ifdef VERILATOR
89                          assign inout_io = (oe)   ? out : 1'bz;
90                        `else
91                          // different driver types
92         1/1              assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T12 T39 T20 
93         1/1              assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T12 T39 T20 
94                          // pullup / pulldown termination
95         1/1              assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
           Tests:       T29 T12 T45 

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[13].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T21,T22,T23
1	1	Covered	T1,T2,T3

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1

-1-	Status	Tests
0	Covered	T21,T22,T23
1	Covered	T1,T2,T3

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T2,T5,T29
0	1	Covered	T2,T29,T66
1	0	Covered	T21,T22,T23
1	1	Covered	T21,T22,T23

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T21,T22,T23
1	0	Covered	T12,T39,T68
1	1	Covered	T21,T22,T23

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T22,T23
1	1	Covered	T12,T39,T20

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T21,T22,T23
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T22,T23

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T22,T23
1	1	Covered	T21,T22,T23

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T21,T22,T23

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T21,T22,T23
1	0	Covered	T12,T39,T20
1	1	Covered	T21,T22,T23

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T12,T39,T20

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T22,T23
1	1	Covered	T12,T39,T20

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T29,T12,T45

---

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[13].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	78	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	93	2	2	100.00
TERNARY	95	2	2	100.00

78             assign in_raw_o = ie ? inout_io : 1'bz;
                                    -1-  
                                    ==>  
                                    ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T21,T22,T23

92             assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                     -1-  
                                                                                     ==>  
                                                                                     ==>  

Branches:

-1-	Status	Tests
1	Covered	T21,T22,T23
0	Covered	T1,T2,T3

93             assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                      -1-  
                                                                                      ==>  
                                                                                      ==>  

Branches:

-1-	Status	Tests
1	Covered	T12,T39,T20
0	Covered	T1,T2,T3

95             assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
                                                                   -1-  
                                                                   ==>  
                                                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T29,T12,T45
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[13].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	1021	1021	0	0

AnalogNoScan_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1021	1021	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T65	1	1	0	0
T103	1	1	0	0
T104	1	1	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[14].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	95	1	1	100.00

38                        logic unused_sigs;
39         unreachable    assign unused_sigs = ^{attr_i.slew_rate,
40                                               attr_i.drive_strength[3:1],
41                                               attr_i.od_en,
42                                               attr_i.schmitt_en,
43                                               attr_i.keep_en,
44                                               scanmode_i,
45                                               pok_i};
46                        //VCS coverage on
47                        // pragma coverage on
48                      
49                        // Input enable (active-high)
50                        logic ie;
51         1/1            assign ie = ie_i & ~attr_i.input_disable;
           Tests:       T21 T22 T23 
52                      
53                        if (PadType == InputStd) begin : gen_input_only
54                          //VCS coverage off
55                          // pragma coverage off
56                          logic unused_in_sigs;
57                          assign unused_in_sigs = ^{out_i,
58                                                    oe_i,
59                                                    attr_i.virt_od_en,
60                                                    attr_i.drive_strength};
61                          //VCS coverage on
62                          // pragma coverage on
63                      
64                          assign in_raw_o = ie ? inout_io : 1'bz;
65                          // input inversion
66                          assign in_o = attr_i.invert ^ in_raw_o;
67                      
68                        // pulls are not supported by verilator
69                        `ifndef VERILATOR
70                          // pullup / pulldown termination
71                          assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72                        `endif
73                        end else if (PadType == BidirTol ||
74                                     PadType == DualBidirTol ||
75                                     PadType == BidirOd ||
76                                     PadType == BidirStd) begin : gen_bidir
77                      
78         1/1              assign in_raw_o = ie ? inout_io : 1'bz;
           Tests:       T1 T2 T3 
79                          // input inversion
80         1/1              assign in_o = attr_i.invert ^ in_raw_o;
           Tests:       T1 T2 T3 
81                      
82                          // virtual open drain emulation
83                          logic oe, out;
84         1/1              assign out = out_i ^ attr_i.invert;
           Tests:       T1 T2 T3 
85         1/1              assign oe  = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
           Tests:       T1 T2 T3 
86                      
87                        // drive strength attributes are not supported by verilator
88                        `ifdef VERILATOR
89                          assign inout_io = (oe)   ? out : 1'bz;
90                        `else
91                          // different driver types
92         1/1              assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T1 T2 T3 
93         1/1              assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T1 T2 T3 
94                          // pullup / pulldown termination
95         1/1              assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
           Tests:       T29 T12 T45 

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[14].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T21,T22,T23
1	1	Covered	T1,T2,T3

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1

-1-	Status	Tests
0	Covered	T21,T22,T23
1	Covered	T1,T2,T3

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T66,T128,T129
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T22,T23
1	1	Covered	T21,T22,T23

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T21,T22,T23
1	0	Covered	T1,T2,T3
1	1	Covered	T21,T22,T23

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T22,T23
1	1	Covered	T1,T2,T3

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T21,T22,T23
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T22,T23

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T22,T23
1	1	Covered	T21,T22,T23

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T21,T22,T23

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T21,T22,T23
1	0	Covered	T1,T2,T3
1	1	Covered	T21,T22,T23

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T22,T23
1	1	Covered	T1,T2,T3

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T29,T12,T45

---

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[14].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	78	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	93	2	2	100.00
TERNARY	95	2	2	100.00

78             assign in_raw_o = ie ? inout_io : 1'bz;
                                    -1-  
                                    ==>  
                                    ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T21,T22,T23

92             assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                     -1-  
                                                                                     ==>  
                                                                                     ==>  

Branches:

-1-	Status	Tests
1	Covered	T21,T22,T23
0	Covered	T1,T2,T3

93             assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                      -1-  
                                                                                      ==>  
                                                                                      ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

95             assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
                                                                   -1-  
                                                                   ==>  
                                                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T29,T12,T45
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[14].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	1021	1021	0	0

AnalogNoScan_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1021	1021	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T65	1	1	0	0
T103	1	1	0	0
T104	1	1	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[15].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	95	1	1	100.00

38                        logic unused_sigs;
39         unreachable    assign unused_sigs = ^{attr_i.slew_rate,
40                                               attr_i.drive_strength[3:1],
41                                               attr_i.od_en,
42                                               attr_i.schmitt_en,
43                                               attr_i.keep_en,
44                                               scanmode_i,
45                                               pok_i};
46                        //VCS coverage on
47                        // pragma coverage on
48                      
49                        // Input enable (active-high)
50                        logic ie;
51         1/1            assign ie = ie_i & ~attr_i.input_disable;
           Tests:       T21 T22 T23 
52                      
53                        if (PadType == InputStd) begin : gen_input_only
54                          //VCS coverage off
55                          // pragma coverage off
56                          logic unused_in_sigs;
57                          assign unused_in_sigs = ^{out_i,
58                                                    oe_i,
59                                                    attr_i.virt_od_en,
60                                                    attr_i.drive_strength};
61                          //VCS coverage on
62                          // pragma coverage on
63                      
64                          assign in_raw_o = ie ? inout_io : 1'bz;
65                          // input inversion
66                          assign in_o = attr_i.invert ^ in_raw_o;
67                      
68                        // pulls are not supported by verilator
69                        `ifndef VERILATOR
70                          // pullup / pulldown termination
71                          assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72                        `endif
73                        end else if (PadType == BidirTol ||
74                                     PadType == DualBidirTol ||
75                                     PadType == BidirOd ||
76                                     PadType == BidirStd) begin : gen_bidir
77                      
78         1/1              assign in_raw_o = ie ? inout_io : 1'bz;
           Tests:       T2 T29 T28 
79                          // input inversion
80         1/1              assign in_o = attr_i.invert ^ in_raw_o;
           Tests:       T2 T29 T28 
81                      
82                          // virtual open drain emulation
83                          logic oe, out;
84         1/1              assign out = out_i ^ attr_i.invert;
           Tests:       T2 T28 T12 
85         1/1              assign oe  = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
           Tests:       T2 T28 T12 
86                      
87                        // drive strength attributes are not supported by verilator
88                        `ifdef VERILATOR
89                          assign inout_io = (oe)   ? out : 1'bz;
90                        `else
91                          // different driver types
92         1/1              assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T2 T28 T12 
93         1/1              assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T2 T28 T12 
94                          // pullup / pulldown termination
95         1/1              assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
           Tests:       T29 T12 T45 

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[15].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T21,T22,T23
1	1	Covered	T1,T2,T3

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1

-1-	Status	Tests
0	Covered	T21,T22,T23
1	Covered	T1,T2,T3

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T28,T14,T62
0	1	Covered	T2,T29,T28
1	0	Covered	T21,T22,T23
1	1	Covered	T21,T22,T23

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T21,T22,T23
1	0	Covered	T2,T28,T12
1	1	Covered	T21,T22,T23

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T22,T23
1	1	Covered	T2,T28,T12

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T21,T22,T23
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T22,T23

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T22,T23
1	1	Covered	T21,T22,T23

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T21,T22,T23

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T21,T22,T23
1	0	Covered	T2,T28,T12
1	1	Covered	T21,T22,T23

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T28,T12

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T22,T23
1	1	Covered	T2,T28,T12

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T29,T12,T45

---

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[15].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	78	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	93	2	2	100.00
TERNARY	95	2	2	100.00

78             assign in_raw_o = ie ? inout_io : 1'bz;
                                    -1-  
                                    ==>  
                                    ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T21,T22,T23

92             assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                     -1-  
                                                                                     ==>  
                                                                                     ==>  

Branches:

-1-	Status	Tests
1	Covered	T21,T22,T23
0	Covered	T1,T2,T3

93             assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                      -1-  
                                                                                      ==>  
                                                                                      ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T28,T12
0	Covered	T1,T2,T3

95             assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
                                                                   -1-  
                                                                   ==>  
                                                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T29,T12,T45
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[15].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	1021	1021	0	0

AnalogNoScan_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1021	1021	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T65	1	1	0	0
T103	1	1	0	0
T104	1	1	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[16].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	95	1	1	100.00

38                        logic unused_sigs;
39         unreachable    assign unused_sigs = ^{attr_i.slew_rate,
40                                               attr_i.drive_strength[3:1],
41                                               attr_i.od_en,
42                                               attr_i.schmitt_en,
43                                               attr_i.keep_en,
44                                               scanmode_i,
45                                               pok_i};
46                        //VCS coverage on
47                        // pragma coverage on
48                      
49                        // Input enable (active-high)
50                        logic ie;
51         1/1            assign ie = ie_i & ~attr_i.input_disable;
           Tests:       T21 T22 T23 
52                      
53                        if (PadType == InputStd) begin : gen_input_only
54                          //VCS coverage off
55                          // pragma coverage off
56                          logic unused_in_sigs;
57                          assign unused_in_sigs = ^{out_i,
58                                                    oe_i,
59                                                    attr_i.virt_od_en,
60                                                    attr_i.drive_strength};
61                          //VCS coverage on
62                          // pragma coverage on
63                      
64                          assign in_raw_o = ie ? inout_io : 1'bz;
65                          // input inversion
66                          assign in_o = attr_i.invert ^ in_raw_o;
67                      
68                        // pulls are not supported by verilator
69                        `ifndef VERILATOR
70                          // pullup / pulldown termination
71                          assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72                        `endif
73                        end else if (PadType == BidirTol ||
74                                     PadType == DualBidirTol ||
75                                     PadType == BidirOd ||
76                                     PadType == BidirStd) begin : gen_bidir
77                      
78         1/1              assign in_raw_o = ie ? inout_io : 1'bz;
           Tests:       T2 T28 T17 
79                          // input inversion
80         1/1              assign in_o = attr_i.invert ^ in_raw_o;
           Tests:       T2 T28 T17 
81                      
82                          // virtual open drain emulation
83                          logic oe, out;
84         1/1              assign out = out_i ^ attr_i.invert;
           Tests:       T2 T28 T17 
85         1/1              assign oe  = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
           Tests:       T2 T28 T17 
86                      
87                        // drive strength attributes are not supported by verilator
88                        `ifdef VERILATOR
89                          assign inout_io = (oe)   ? out : 1'bz;
90                        `else
91                          // different driver types
92         1/1              assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T2 T28 T17 
93         1/1              assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T2 T28 T17 
94                          // pullup / pulldown termination
95         1/1              assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
           Tests:       T21 T22 T23 

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[16].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T21,T22,T23
1	1	Covered	T1,T2,T3

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1

-1-	Status	Tests
0	Covered	T21,T22,T23
1	Covered	T1,T2,T3

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T28,T17,T14
0	1	Covered	T2,T28,T17
1	0	Covered	T21,T22,T23
1	1	Covered	T21,T22,T23

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T21,T22,T23
1	0	Covered	T2,T28,T17
1	1	Covered	T22,T23,T212

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T22,T23
1	1	Covered	T2,T28,T17

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T21,T22,T23
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T22,T23

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T22,T23
1	1	Covered	T21,T22,T23

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T21,T22,T23

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T21,T22,T23
1	0	Covered	T2,T28,T17
1	1	Covered	T21,T22,T23

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T28,T17

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T22,T23
1	1	Covered	T2,T28,T17

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T21,T22,T23

---

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[16].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	78	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	93	2	2	100.00
TERNARY	95	2	2	100.00

78             assign in_raw_o = ie ? inout_io : 1'bz;
                                    -1-  
                                    ==>  
                                    ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T21,T22,T23

92             assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                     -1-  
                                                                                     ==>  
                                                                                     ==>  

Branches:

-1-	Status	Tests
1	Covered	T21,T22,T23
0	Covered	T1,T2,T3

93             assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                      -1-  
                                                                                      ==>  
                                                                                      ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T28,T17
0	Covered	T1,T2,T3

95             assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
                                                                   -1-  
                                                                   ==>  
                                                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T21,T22,T23
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[16].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	1021	1021	0	0

AnalogNoScan_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1021	1021	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T65	1	1	0	0
T103	1	1	0	0
T104	1	1	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[17].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	95	1	1	100.00

38                        logic unused_sigs;
39         unreachable    assign unused_sigs = ^{attr_i.slew_rate,
40                                               attr_i.drive_strength[3:1],
41                                               attr_i.od_en,
42                                               attr_i.schmitt_en,
43                                               attr_i.keep_en,
44                                               scanmode_i,
45                                               pok_i};
46                        //VCS coverage on
47                        // pragma coverage on
48                      
49                        // Input enable (active-high)
50                        logic ie;
51         1/1            assign ie = ie_i & ~attr_i.input_disable;
           Tests:       T21 T22 T23 
52                      
53                        if (PadType == InputStd) begin : gen_input_only
54                          //VCS coverage off
55                          // pragma coverage off
56                          logic unused_in_sigs;
57                          assign unused_in_sigs = ^{out_i,
58                                                    oe_i,
59                                                    attr_i.virt_od_en,
60                                                    attr_i.drive_strength};
61                          //VCS coverage on
62                          // pragma coverage on
63                      
64                          assign in_raw_o = ie ? inout_io : 1'bz;
65                          // input inversion
66                          assign in_o = attr_i.invert ^ in_raw_o;
67                      
68                        // pulls are not supported by verilator
69                        `ifndef VERILATOR
70                          // pullup / pulldown termination
71                          assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72                        `endif
73                        end else if (PadType == BidirTol ||
74                                     PadType == DualBidirTol ||
75                                     PadType == BidirOd ||
76                                     PadType == BidirStd) begin : gen_bidir
77                      
78         1/1              assign in_raw_o = ie ? inout_io : 1'bz;
           Tests:       T2 T28 T14 
79                          // input inversion
80         1/1              assign in_o = attr_i.invert ^ in_raw_o;
           Tests:       T2 T28 T14 
81                      
82                          // virtual open drain emulation
83                          logic oe, out;
84         1/1              assign out = out_i ^ attr_i.invert;
           Tests:       T28 T12 T41 
85         1/1              assign oe  = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
           Tests:       T28 T12 T41 
86                      
87                        // drive strength attributes are not supported by verilator
88                        `ifdef VERILATOR
89                          assign inout_io = (oe)   ? out : 1'bz;
90                        `else
91                          // different driver types
92         1/1              assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T28 T12 T41 
93         1/1              assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T28 T12 T41 
94                          // pullup / pulldown termination
95         1/1              assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
           Tests:       T21 T22 T23 

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[17].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T21,T22,T23
1	1	Covered	T1,T2,T3

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1

-1-	Status	Tests
0	Covered	T21,T22,T23
1	Covered	T1,T2,T3

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T2,T28,T14
0	1	Covered	T2,T28,T14
1	0	Covered	T21,T22,T23
1	1	Covered	T21,T22,T23

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T21,T22,T23
1	0	Covered	T28,T12,T41
1	1	Covered	T21,T22,T23

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T22,T23
1	1	Covered	T28,T12,T41

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T21,T22,T23
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T22,T23

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T22,T23
1	1	Covered	T21,T22,T23

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T21,T22,T23

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T21,T22,T23
1	0	Covered	T28,T12,T41
1	1	Covered	T21,T22,T23

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T28,T12,T41

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T22,T23
1	1	Covered	T28,T12,T41

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T21,T22,T23

---

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[17].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	78	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	93	2	2	100.00
TERNARY	95	2	2	100.00

78             assign in_raw_o = ie ? inout_io : 1'bz;
                                    -1-  
                                    ==>  
                                    ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T21,T22,T23

92             assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                     -1-  
                                                                                     ==>  
                                                                                     ==>  

Branches:

-1-	Status	Tests
1	Covered	T21,T22,T23
0	Covered	T1,T2,T3

93             assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                      -1-  
                                                                                      ==>  
                                                                                      ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T12,T41
0	Covered	T1,T2,T3

95             assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
                                                                   -1-  
                                                                   ==>  
                                                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T21,T22,T23
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[17].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	1021	1021	0	0

AnalogNoScan_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1021	1021	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T65	1	1	0	0
T103	1	1	0	0
T104	1	1	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[18].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	95	1	1	100.00

38                        logic unused_sigs;
39         unreachable    assign unused_sigs = ^{attr_i.slew_rate,
40                                               attr_i.drive_strength[3:1],
41                                               attr_i.od_en,
42                                               attr_i.schmitt_en,
43                                               attr_i.keep_en,
44                                               scanmode_i,
45                                               pok_i};
46                        //VCS coverage on
47                        // pragma coverage on
48                      
49                        // Input enable (active-high)
50                        logic ie;
51         1/1            assign ie = ie_i & ~attr_i.input_disable;
           Tests:       T21 T22 T23 
52                      
53                        if (PadType == InputStd) begin : gen_input_only
54                          //VCS coverage off
55                          // pragma coverage off
56                          logic unused_in_sigs;
57                          assign unused_in_sigs = ^{out_i,
58                                                    oe_i,
59                                                    attr_i.virt_od_en,
60                                                    attr_i.drive_strength};
61                          //VCS coverage on
62                          // pragma coverage on
63                      
64                          assign in_raw_o = ie ? inout_io : 1'bz;
65                          // input inversion
66                          assign in_o = attr_i.invert ^ in_raw_o;
67                      
68                        // pulls are not supported by verilator
69                        `ifndef VERILATOR
70                          // pullup / pulldown termination
71                          assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72                        `endif
73                        end else if (PadType == BidirTol ||
74                                     PadType == DualBidirTol ||
75                                     PadType == BidirOd ||
76                                     PadType == BidirStd) begin : gen_bidir
77                      
78         1/1              assign in_raw_o = ie ? inout_io : 1'bz;
           Tests:       T2 T6 T30 
79                          // input inversion
80         1/1              assign in_o = attr_i.invert ^ in_raw_o;
           Tests:       T2 T6 T30 
81                      
82                          // virtual open drain emulation
83                          logic oe, out;
84         1/1              assign out = out_i ^ attr_i.invert;
           Tests:       T2 T28 T14 
85         1/1              assign oe  = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
           Tests:       T2 T6 T30 
86                      
87                        // drive strength attributes are not supported by verilator
88                        `ifdef VERILATOR
89                          assign inout_io = (oe)   ? out : 1'bz;
90                        `else
91                          // different driver types
92         1/1              assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T2 T6 T30 
93         1/1              assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T2 T6 T30 
94                          // pullup / pulldown termination
95         1/1              assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
           Tests:       T21 T22 T23 

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[18].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T21,T22,T23
1	1	Covered	T1,T2,T3

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1

-1-	Status	Tests
0	Covered	T21,T22,T23
1	Covered	T1,T2,T3

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T30,T28
0	1	Covered	T2,T30,T28
1	0	Covered	T21,T22,T23
1	1	Covered	T21,T22,T23

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T21,T22,T23
1	0	Covered	T2,T28,T14
1	1	Covered	T21,T22,T23

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T22,T23
1	1	Covered	T2,T6,T30

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T21,T22,T23
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T22,T23

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T22,T23
1	1	Covered	T21,T22,T23

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T21,T22,T23

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T21,T22,T23
1	0	Covered	T2,T6,T30
1	1	Covered	T21,T22,T23

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T6,T30

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T22,T23
1	1	Covered	T2,T6,T30

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T21,T22,T23

---

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[18].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	78	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	93	2	2	100.00
TERNARY	95	2	2	100.00

78             assign in_raw_o = ie ? inout_io : 1'bz;
                                    -1-  
                                    ==>  
                                    ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T21,T22,T23

92             assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                     -1-  
                                                                                     ==>  
                                                                                     ==>  

Branches:

-1-	Status	Tests
1	Covered	T21,T22,T23
0	Covered	T1,T2,T3

93             assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                      -1-  
                                                                                      ==>  
                                                                                      ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T30
0	Covered	T1,T2,T3

95             assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
                                                                   -1-  
                                                                   ==>  
                                                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T21,T22,T23
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[18].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	1021	1021	0	0

AnalogNoScan_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1021	1021	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T65	1	1	0	0
T103	1	1	0	0
T104	1	1	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[19].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	95	1	1	100.00

38                        logic unused_sigs;
39         unreachable    assign unused_sigs = ^{attr_i.slew_rate,
40                                               attr_i.drive_strength[3:1],
41                                               attr_i.od_en,
42                                               attr_i.schmitt_en,
43                                               attr_i.keep_en,
44                                               scanmode_i,
45                                               pok_i};
46                        //VCS coverage on
47                        // pragma coverage on
48                      
49                        // Input enable (active-high)
50                        logic ie;
51         1/1            assign ie = ie_i & ~attr_i.input_disable;
           Tests:       T21 T22 T23 
52                      
53                        if (PadType == InputStd) begin : gen_input_only
54                          //VCS coverage off
55                          // pragma coverage off
56                          logic unused_in_sigs;
57                          assign unused_in_sigs = ^{out_i,
58                                                    oe_i,
59                                                    attr_i.virt_od_en,
60                                                    attr_i.drive_strength};
61                          //VCS coverage on
62                          // pragma coverage on
63                      
64                          assign in_raw_o = ie ? inout_io : 1'bz;
65                          // input inversion
66                          assign in_o = attr_i.invert ^ in_raw_o;
67                      
68                        // pulls are not supported by verilator
69                        `ifndef VERILATOR
70                          // pullup / pulldown termination
71                          assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72                        `endif
73                        end else if (PadType == BidirTol ||
74                                     PadType == DualBidirTol ||
75                                     PadType == BidirOd ||
76                                     PadType == BidirStd) begin : gen_bidir
77                      
78         1/1              assign in_raw_o = ie ? inout_io : 1'bz;
           Tests:       T2 T6 T30 
79                          // input inversion
80         1/1              assign in_o = attr_i.invert ^ in_raw_o;
           Tests:       T2 T6 T30 
81                      
82                          // virtual open drain emulation
83                          logic oe, out;
84         1/1              assign out = out_i ^ attr_i.invert;
           Tests:       T2 T28 T34 
85         1/1              assign oe  = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
           Tests:       T2 T6 T30 
86                      
87                        // drive strength attributes are not supported by verilator
88                        `ifdef VERILATOR
89                          assign inout_io = (oe)   ? out : 1'bz;
90                        `else
91                          // different driver types
92         1/1              assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T2 T6 T30 
93         1/1              assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T2 T6 T30 
94                          // pullup / pulldown termination
95         1/1              assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
           Tests:       T21 T22 T23 

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[19].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T21,T22,T23
1	1	Covered	T1,T2,T3

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1

-1-	Status	Tests
0	Covered	T21,T22,T23
1	Covered	T1,T2,T3

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T30,T28
0	1	Covered	T2,T30,T28
1	0	Covered	T21,T22,T23
1	1	Covered	T21,T22,T23

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T21,T22,T23
1	0	Covered	T2,T28,T34
1	1	Covered	T21,T22,T23

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T22,T23
1	1	Covered	T2,T6,T30

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T21,T22,T23
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T22,T23

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T22,T23
1	1	Covered	T21,T22,T23

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T21,T22,T23

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T21,T22,T23
1	0	Covered	T2,T6,T30
1	1	Covered	T21,T22,T23

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T6,T30

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T22,T23
1	1	Covered	T2,T6,T30

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T21,T22,T23

---

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[19].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	78	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	93	2	2	100.00
TERNARY	95	2	2	100.00

78             assign in_raw_o = ie ? inout_io : 1'bz;
                                    -1-  
                                    ==>  
                                    ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T21,T22,T23

92             assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                     -1-  
                                                                                     ==>  
                                                                                     ==>  

Branches:

-1-	Status	Tests
1	Covered	T21,T22,T23
0	Covered	T1,T2,T3

93             assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                      -1-  
                                                                                      ==>  
                                                                                      ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T30
0	Covered	T1,T2,T3

95             assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
                                                                   -1-  
                                                                   ==>  
                                                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T21,T22,T23
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[19].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	1021	1021	0	0

AnalogNoScan_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1021	1021	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T65	1	1	0	0
T103	1	1	0	0
T104	1	1	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[20].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	95	1	1	100.00

38                        logic unused_sigs;
39         unreachable    assign unused_sigs = ^{attr_i.slew_rate,
40                                               attr_i.drive_strength[3:1],
41                                               attr_i.od_en,
42                                               attr_i.schmitt_en,
43                                               attr_i.keep_en,
44                                               scanmode_i,
45                                               pok_i};
46                        //VCS coverage on
47                        // pragma coverage on
48                      
49                        // Input enable (active-high)
50                        logic ie;
51         1/1            assign ie = ie_i & ~attr_i.input_disable;
           Tests:       T21 T22 T23 
52                      
53                        if (PadType == InputStd) begin : gen_input_only
54                          //VCS coverage off
55                          // pragma coverage off
56                          logic unused_in_sigs;
57                          assign unused_in_sigs = ^{out_i,
58                                                    oe_i,
59                                                    attr_i.virt_od_en,
60                                                    attr_i.drive_strength};
61                          //VCS coverage on
62                          // pragma coverage on
63                      
64                          assign in_raw_o = ie ? inout_io : 1'bz;
65                          // input inversion
66                          assign in_o = attr_i.invert ^ in_raw_o;
67                      
68                        // pulls are not supported by verilator
69                        `ifndef VERILATOR
70                          // pullup / pulldown termination
71                          assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72                        `endif
73                        end else if (PadType == BidirTol ||
74                                     PadType == DualBidirTol ||
75                                     PadType == BidirOd ||
76                                     PadType == BidirStd) begin : gen_bidir
77                      
78         1/1              assign in_raw_o = ie ? inout_io : 1'bz;
           Tests:       T2 T6 T31 
79                          // input inversion
80         1/1              assign in_o = attr_i.invert ^ in_raw_o;
           Tests:       T2 T6 T31 
81                      
82                          // virtual open drain emulation
83                          logic oe, out;
84         1/1              assign out = out_i ^ attr_i.invert;
           Tests:       T2 T6 T28 
85         1/1              assign oe  = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
           Tests:       T2 T6 T31 
86                      
87                        // drive strength attributes are not supported by verilator
88                        `ifdef VERILATOR
89                          assign inout_io = (oe)   ? out : 1'bz;
90                        `else
91                          // different driver types
92         1/1              assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T2 T6 T31 
93         1/1              assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T2 T6 T31 
94                          // pullup / pulldown termination
95         1/1              assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
           Tests:       T21 T22 T23 

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[20].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T21,T22,T23
1	1	Covered	T1,T2,T3

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1

-1-	Status	Tests
0	Covered	T21,T22,T23
1	Covered	T1,T2,T3

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T31,T28
0	1	Covered	T2,T6,T31
1	0	Covered	T21,T22,T23
1	1	Covered	T21,T22,T23

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T21,T22,T23
1	0	Covered	T2,T6,T28
1	1	Covered	T21,T22,T23

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T22,T23
1	1	Covered	T2,T6,T31

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T21,T22,T23
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T22,T23

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T22,T23
1	1	Covered	T21,T22,T23

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T21,T22,T23

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T21,T22,T23
1	0	Covered	T2,T6,T31
1	1	Covered	T21,T22,T23

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T6,T31

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T22,T23
1	1	Covered	T2,T6,T31

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T21,T22,T23

---

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[20].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	78	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	93	2	2	100.00
TERNARY	95	2	2	100.00

78             assign in_raw_o = ie ? inout_io : 1'bz;
                                    -1-  
                                    ==>  
                                    ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T21,T22,T23

92             assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                     -1-  
                                                                                     ==>  
                                                                                     ==>  

Branches:

-1-	Status	Tests
1	Covered	T21,T22,T23
0	Covered	T1,T2,T3

93             assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                      -1-  
                                                                                      ==>  
                                                                                      ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T31
0	Covered	T1,T2,T3

95             assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
                                                                   -1-  
                                                                   ==>  
                                                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T21,T22,T23
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[20].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	1021	1021	0	0

AnalogNoScan_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1021	1021	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T65	1	1	0	0
T103	1	1	0	0
T104	1	1	0	0