Unified Coverage Report :: Module :: pinmux_wkup

Module : pinmux_wkup

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.33	78.95	92.31			72.73

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux_wkup.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[6].u_pinmux_wkup	25.56	26.32	23.08			27.27
tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[1].u_pinmux_wkup	45.52	52.63	38.46			45.45
tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[3].u_pinmux_wkup	45.52	52.63	38.46			45.45
tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[7].u_pinmux_wkup	59.28	63.16	69.23			45.45
tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[2].u_pinmux_wkup	61.50	68.42	61.54			54.55
tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[4].u_pinmux_wkup	64.07	68.42	69.23			54.55
tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[5].u_pinmux_wkup	64.07	68.42	69.23			54.55
tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[0].u_pinmux_wkup	81.33	78.95	92.31			72.73

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[6].u_pinmux_wkup

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
25.56	26.32	23.08			27.27

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
45.45	50.00	31.82			54.55

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.51	99.13	85.84	98.84		81.75	92.00	u_pinmux_aon

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_filter	67.58	76.47	44.44			81.82

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[1].u_pinmux_wkup

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
45.52	52.63	38.46			45.45

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
56.14	63.89	40.91			63.64

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.51	99.13	85.84	98.84		81.75	92.00	u_pinmux_aon

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_filter	67.58	76.47	44.44			81.82

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[3].u_pinmux_wkup

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
45.52	52.63	38.46			45.45

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
56.14	63.89	40.91			63.64

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.51	99.13	85.84	98.84		81.75	92.00	u_pinmux_aon

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_filter	67.58	76.47	44.44			81.82

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[7].u_pinmux_wkup

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
59.28	63.16	69.23			45.45

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
78.37	80.56	81.82			72.73

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.51	99.13	85.84	98.84		81.75	92.00	u_pinmux_aon

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_filter	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[2].u_pinmux_wkup

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
61.50	68.42	61.54			54.55

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.29	83.33	77.27			77.27

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.51	99.13	85.84	98.84		81.75	92.00	u_pinmux_aon

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_filter	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[4].u_pinmux_wkup

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
64.07	68.42	69.23			54.55

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
77.78	83.33	77.27			72.73

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.51	99.13	85.84	98.84		81.75	92.00	u_pinmux_aon

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_filter	93.27	100.00	88.89			90.91

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[5].u_pinmux_wkup

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
64.07	68.42	69.23			54.55

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
77.78	83.33	77.27			72.73

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.51	99.13	85.84	98.84		81.75	92.00	u_pinmux_aon

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_filter	93.27	100.00	88.89			90.91

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[0].u_pinmux_wkup

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.33	78.95	92.31			72.73

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.21	88.89	90.91			81.82

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.51	99.13	85.84	98.84		81.75	92.00	u_pinmux_aon

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_filter	93.27	100.00	88.89			90.91

Line Coverage for Module : pinmux_wkup

	Line No.	Total	Covered	Percent
TOTAL		19	15	78.95
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	46	1	1	100.00
CONT_ASSIGN	50	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
ALWAYS	55	10	6	60.00
ALWAYS	82	5	5	100.00

44                        logic rising, falling;
45         1/1            assign falling = ~filter_out_d & filter_out_q;
           Tests:       T6 T25 T29 
46         1/1            assign rising  = filter_out_d & ~filter_out_q;
           Tests:       T6 T25 T29 
47                      
48                        logic cnt_en, cnt_eq_th;
49                        logic [WkupCntWidth-1:0] cnt_d, cnt_q;
50         1/1            assign cnt_d     = (cnt_eq_th) ? '0 : (cnt_en) ? cnt_q + 1'b1 : '0;
           Tests:       T90 T128 T74 
51                      
52         1/1            assign cnt_eq_th = (cnt_q >= wkup_cnt_th_i);
           Tests:       T90 T128 T74 
53                      
54                        always_comb begin : p_mode
55         1/1              aon_wkup_pulse_o = 1'b0;
           Tests:       T6 T25 T29 
56         1/1              cnt_en           = 1'b0;
           Tests:       T6 T25 T29 
57         1/1              if (wkup_en_i) begin
           Tests:       T6 T25 T29 
58         1/1                unique case (wkup_mode_i)
           Tests:       T6 T25 T29 
59                              Negedge: begin
60         1/1                    aon_wkup_pulse_o = falling;
           Tests:       T6 T84 T85 
61                              end
62                              Edge: begin
63         1/1                    aon_wkup_pulse_o = rising | falling;
           Tests:       T6 T84 T85 
64                              end
65                              HighTimed: begin
66         0/1     ==>            cnt_en = filter_out_d;
67         0/1     ==>            aon_wkup_pulse_o = cnt_eq_th;
68                              end
69                              LowTimed: begin
70         0/1     ==>            cnt_en = ~filter_out_d;
71         0/1     ==>            aon_wkup_pulse_o = cnt_eq_th;
72                              end
73                              // Default to rising
74                              default: begin
75                                aon_wkup_pulse_o = rising;
76                              end
77                            endcase
78                          end
                        MISSING_ELSE
79                        end
80                      
81                        always_ff @(posedge clk_i or negedge rst_ni) begin : p_aon_pattern
82         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
83         1/1                filter_out_q <= 1'b0;
           Tests:       T1 T2 T3 
84         1/1                cnt_q        <= '0;
           Tests:       T1 T2 T3 
85                          end else begin
86         1/1                filter_out_q <= filter_out_d;
           Tests:       T1 T2 T3 
87         1/1                cnt_q        <= cnt_d;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : pinmux_wkup

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       45
 EXPRESSION (((~filter_out_d)) & filter_out_q)
             --------1--------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T25,T29
1	0	Covered	T1,T2,T3
1	1	Covered	T6,T29,T77

 LINE       46
 EXPRESSION (filter_out_d & ((~filter_out_q)))
             ------1-----   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T25,T29
1	1	Covered	T6,T25,T29

 LINE       50
 EXPRESSION (cnt_eq_th ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : '0))
             ----1----

-1-	Status	Tests
0	Covered	T90,T128,T74
1	Covered	T1,T2,T3

 LINE       50
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : '0)
                 ---1--

-1-	Status	Tests
0	Covered	T90,T128,T74
1	Not Covered

 LINE       63
 EXPRESSION (rising | falling)
             ---1--   ---2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T84,T85
0	1	Covered	T6,T84,T85
1	0	Covered	T6,T84,T85

---

Branch Coverage for Module : pinmux_wkup

	Line No.	Total	Covered	Percent
Branches		11	8	72.73
TERNARY	50	3	2	66.67
IF	57	6	4	66.67
IF	82	2	2	100.00

50           assign cnt_d     = (cnt_eq_th) ? '0 : (cnt_en) ? cnt_q + 1'b1 : '0;
                                            -1-             -2-   
                                            ==>             ==>   
                                                            ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T90,T128,T74

57             if (wkup_en_i) begin
               -1-  
58               unique case (wkup_mode_i)
                        -2-  
59                 Negedge: begin
60                   aon_wkup_pulse_o = falling;
                     ==>
61                 end
62                 Edge: begin
63                   aon_wkup_pulse_o = rising | falling;
                     ==>
64                 end
65                 HighTimed: begin
66                   cnt_en = filter_out_d;
                     ==>
67                   aon_wkup_pulse_o = cnt_eq_th;
68                 end
69                 LowTimed: begin
70                   cnt_en = ~filter_out_d;
                     ==>
71                   aon_wkup_pulse_o = cnt_eq_th;
72                 end
73                 // Default to rising
74                 default: begin
75                   aon_wkup_pulse_o = rising;
                     ==>
76                 end
77               endcase
78             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	Negedge	Covered	T6,T84,T85
1	Edge	Covered	T6,T84,T85
1	HighTimed	Not Covered
1	LowTimed	Not Covered
1	default	Covered	T25,T29,T77
0	-	Covered	T6,T90,T78

82             if (!rst_ni) begin
               -1-  
83               filter_out_q <= 1'b0;
                 ==>
84               cnt_q        <= '0;
85             end else begin
86               filter_out_q <= filter_out_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[6].u_pinmux_wkup

	Line No.	Total	Covered	Percent
TOTAL		19	5	26.32
CONT_ASSIGN	45	1	0	0.00
CONT_ASSIGN	46	1	0	0.00
CONT_ASSIGN	50	1	0	0.00
CONT_ASSIGN	52	1	0	0.00
ALWAYS	55	10	0	0.00
ALWAYS	82	5	5	100.00

44                        logic rising, falling;
45         0/1     ==>    assign falling = ~filter_out_d & filter_out_q;
46         0/1     ==>    assign rising  = filter_out_d & ~filter_out_q;
47                      
48                        logic cnt_en, cnt_eq_th;
49                        logic [WkupCntWidth-1:0] cnt_d, cnt_q;
50         0/1     ==>    assign cnt_d     = (cnt_eq_th) ? '0 : (cnt_en) ? cnt_q + 1'b1 : '0;
51                      
52         0/1     ==>    assign cnt_eq_th = (cnt_q >= wkup_cnt_th_i);
53                      
54                        always_comb begin : p_mode
55         0/1     ==>      aon_wkup_pulse_o = 1'b0;
56         0/1     ==>      cnt_en           = 1'b0;
57         0/1     ==>      if (wkup_en_i) begin
58         0/1     ==>        unique case (wkup_mode_i)
59                              Negedge: begin
60         0/1     ==>            aon_wkup_pulse_o = falling;
61                              end
62                              Edge: begin
63         0/1     ==>            aon_wkup_pulse_o = rising | falling;
64                              end
65                              HighTimed: begin
66         0/1     ==>            cnt_en = filter_out_d;
67         0/1     ==>            aon_wkup_pulse_o = cnt_eq_th;
68                              end
69                              LowTimed: begin
70         0/1     ==>            cnt_en = ~filter_out_d;
71         0/1     ==>            aon_wkup_pulse_o = cnt_eq_th;
72                              end
73                              // Default to rising
74                              default: begin
75                                aon_wkup_pulse_o = rising;
76                              end
77                            endcase
78                          end
                   ==>  MISSING_ELSE
79                        end
80                      
81                        always_ff @(posedge clk_i or negedge rst_ni) begin : p_aon_pattern
82         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
83         1/1                filter_out_q <= 1'b0;
           Tests:       T1 T2 T3 
84         1/1                cnt_q        <= '0;
           Tests:       T1 T2 T3 
85                          end else begin
86         1/1                filter_out_q <= filter_out_d;
           Tests:       T1 T2 T3 
87         1/1                cnt_q        <= cnt_d;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[6].u_pinmux_wkup

	Total	Covered	Percent
Conditions	13	3	23.08
Logical	13	3	23.08
Non-Logical	0	0
Event	0	0

 LINE       45
 EXPRESSION (((~filter_out_d)) & filter_out_q)
             --------1--------   ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       46
 EXPRESSION (filter_out_d & ((~filter_out_q)))
             ------1-----   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       50
 EXPRESSION (cnt_eq_th ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : '0))
             ----1----

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       50
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : '0)
                 ---1--

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       63
 EXPRESSION (rising | falling)
             ---1--   ---2---

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[6].u_pinmux_wkup

	Line No.	Total	Covered	Percent
Branches		11	3	27.27
TERNARY	50	3	1	33.33
IF	57	6	0	0.00
IF	82	2	2	100.00

50           assign cnt_d     = (cnt_eq_th) ? '0 : (cnt_en) ? cnt_q + 1'b1 : '0;
                                            -1-             -2-   
                                            ==>             ==>   
                                                            ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Not Covered

57             if (wkup_en_i) begin
               -1-  
58               unique case (wkup_mode_i)
                        -2-  
59                 Negedge: begin
60                   aon_wkup_pulse_o = falling;
                     ==>
61                 end
62                 Edge: begin
63                   aon_wkup_pulse_o = rising | falling;
                     ==>
64                 end
65                 HighTimed: begin
66                   cnt_en = filter_out_d;
                     ==>
67                   aon_wkup_pulse_o = cnt_eq_th;
68                 end
69                 LowTimed: begin
70                   cnt_en = ~filter_out_d;
                     ==>
71                   aon_wkup_pulse_o = cnt_eq_th;
72                 end
73                 // Default to rising
74                 default: begin
75                   aon_wkup_pulse_o = rising;
                     ==>
76                 end
77               endcase
78             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	Negedge	Not Covered
1	Edge	Not Covered
1	HighTimed	Not Covered
1	LowTimed	Not Covered
1	default	Not Covered
0	-	Not Covered

82             if (!rst_ni) begin
               -1-  
83               filter_out_q <= 1'b0;
                 ==>
84               cnt_q        <= '0;
85             end else begin
86               filter_out_q <= filter_out_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[1].u_pinmux_wkup

	Line No.	Total	Covered	Percent
TOTAL		19	10	52.63
CONT_ASSIGN	45	1	0	0.00
CONT_ASSIGN	46	1	0	0.00
CONT_ASSIGN	50	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
ALWAYS	55	10	3	30.00
ALWAYS	82	5	5	100.00

44                        logic rising, falling;
45         0/1     ==>    assign falling = ~filter_out_d & filter_out_q;
46         0/1     ==>    assign rising  = filter_out_d & ~filter_out_q;
47                      
48                        logic cnt_en, cnt_eq_th;
49                        logic [WkupCntWidth-1:0] cnt_d, cnt_q;
50         1/1            assign cnt_d     = (cnt_eq_th) ? '0 : (cnt_en) ? cnt_q + 1'b1 : '0;
           Tests:       T90 T128 T74 
51                      
52         1/1            assign cnt_eq_th = (cnt_q >= wkup_cnt_th_i);
           Tests:       T90 T128 T74 
53                      
54                        always_comb begin : p_mode
55         1/1              aon_wkup_pulse_o = 1'b0;
           Tests:       T90 T128 T74 
56         1/1              cnt_en           = 1'b0;
           Tests:       T90 T128 T74 
57         1/1              if (wkup_en_i) begin
           Tests:       T90 T128 T74 
58         0/1     ==>        unique case (wkup_mode_i)
59                              Negedge: begin
60         0/1     ==>            aon_wkup_pulse_o = falling;
61                              end
62                              Edge: begin
63         0/1     ==>            aon_wkup_pulse_o = rising | falling;
64                              end
65                              HighTimed: begin
66         0/1     ==>            cnt_en = filter_out_d;
67         0/1     ==>            aon_wkup_pulse_o = cnt_eq_th;
68                              end
69                              LowTimed: begin
70         0/1     ==>            cnt_en = ~filter_out_d;
71         0/1     ==>            aon_wkup_pulse_o = cnt_eq_th;
72                              end
73                              // Default to rising
74                              default: begin
75                                aon_wkup_pulse_o = rising;
76                              end
77                            endcase
78                          end
                        MISSING_ELSE
79                        end
80                      
81                        always_ff @(posedge clk_i or negedge rst_ni) begin : p_aon_pattern
82         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
83         1/1                filter_out_q <= 1'b0;
           Tests:       T1 T2 T3 
84         1/1                cnt_q        <= '0;
           Tests:       T1 T2 T3 
85                          end else begin
86         1/1                filter_out_q <= filter_out_d;
           Tests:       T1 T2 T3 
87         1/1                cnt_q        <= cnt_d;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[1].u_pinmux_wkup

	Total	Covered	Percent
Conditions	13	5	38.46
Logical	13	5	38.46
Non-Logical	0	0
Event	0	0

 LINE       45
 EXPRESSION (((~filter_out_d)) & filter_out_q)
             --------1--------   ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       46
 EXPRESSION (filter_out_d & ((~filter_out_q)))
             ------1-----   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       50
 EXPRESSION (cnt_eq_th ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : '0))
             ----1----

-1-	Status	Tests
0	Covered	T90,T128,T74
1	Covered	T1,T2,T3

 LINE       50
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : '0)
                 ---1--

-1-	Status	Tests
0	Covered	T90,T128,T74
1	Not Covered

 LINE       63
 EXPRESSION (rising | falling)
             ---1--   ---2---

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[1].u_pinmux_wkup

	Line No.	Total	Covered	Percent
Branches		11	5	45.45
TERNARY	50	3	2	66.67
IF	57	6	1	16.67
IF	82	2	2	100.00

50           assign cnt_d     = (cnt_eq_th) ? '0 : (cnt_en) ? cnt_q + 1'b1 : '0;
                                            -1-             -2-   
                                            ==>             ==>   
                                                            ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T90,T128,T74

57             if (wkup_en_i) begin
               -1-  
58               unique case (wkup_mode_i)
                        -2-  
59                 Negedge: begin
60                   aon_wkup_pulse_o = falling;
                     ==>
61                 end
62                 Edge: begin
63                   aon_wkup_pulse_o = rising | falling;
                     ==>
64                 end
65                 HighTimed: begin
66                   cnt_en = filter_out_d;
                     ==>
67                   aon_wkup_pulse_o = cnt_eq_th;
68                 end
69                 LowTimed: begin
70                   cnt_en = ~filter_out_d;
                     ==>
71                   aon_wkup_pulse_o = cnt_eq_th;
72                 end
73                 // Default to rising
74                 default: begin
75                   aon_wkup_pulse_o = rising;
                     ==>
76                 end
77               endcase
78             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	Negedge	Not Covered
1	Edge	Not Covered
1	HighTimed	Not Covered
1	LowTimed	Not Covered
1	default	Not Covered
0	-	Covered	T90,T128,T74

82             if (!rst_ni) begin
               -1-  
83               filter_out_q <= 1'b0;
                 ==>
84               cnt_q        <= '0;
85             end else begin
86               filter_out_q <= filter_out_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[3].u_pinmux_wkup

	Line No.	Total	Covered	Percent
TOTAL		19	10	52.63
CONT_ASSIGN	45	1	0	0.00
CONT_ASSIGN	46	1	0	0.00
CONT_ASSIGN	50	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
ALWAYS	55	10	3	30.00
ALWAYS	82	5	5	100.00

44                        logic rising, falling;
45         0/1     ==>    assign falling = ~filter_out_d & filter_out_q;
46         0/1     ==>    assign rising  = filter_out_d & ~filter_out_q;
47                      
48                        logic cnt_en, cnt_eq_th;
49                        logic [WkupCntWidth-1:0] cnt_d, cnt_q;
50         1/1            assign cnt_d     = (cnt_eq_th) ? '0 : (cnt_en) ? cnt_q + 1'b1 : '0;
           Tests:       T74 
51                      
52         1/1            assign cnt_eq_th = (cnt_q >= wkup_cnt_th_i);
           Tests:       T74 
53                      
54                        always_comb begin : p_mode
55         1/1              aon_wkup_pulse_o = 1'b0;
           Tests:       T74 
56         1/1              cnt_en           = 1'b0;
           Tests:       T74 
57         1/1              if (wkup_en_i) begin
           Tests:       T74 
58         0/1     ==>        unique case (wkup_mode_i)
59                              Negedge: begin
60         0/1     ==>            aon_wkup_pulse_o = falling;
61                              end
62                              Edge: begin
63         0/1     ==>            aon_wkup_pulse_o = rising | falling;
64                              end
65                              HighTimed: begin
66         0/1     ==>            cnt_en = filter_out_d;
67         0/1     ==>            aon_wkup_pulse_o = cnt_eq_th;
68                              end
69                              LowTimed: begin
70         0/1     ==>            cnt_en = ~filter_out_d;
71         0/1     ==>            aon_wkup_pulse_o = cnt_eq_th;
72                              end
73                              // Default to rising
74                              default: begin
75                                aon_wkup_pulse_o = rising;
76                              end
77                            endcase
78                          end
                        MISSING_ELSE
79                        end
80                      
81                        always_ff @(posedge clk_i or negedge rst_ni) begin : p_aon_pattern
82         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
83         1/1                filter_out_q <= 1'b0;
           Tests:       T1 T2 T3 
84         1/1                cnt_q        <= '0;
           Tests:       T1 T2 T3 
85                          end else begin
86         1/1                filter_out_q <= filter_out_d;
           Tests:       T1 T2 T3 
87         1/1                cnt_q        <= cnt_d;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[3].u_pinmux_wkup

	Total	Covered	Percent
Conditions	13	5	38.46
Logical	13	5	38.46
Non-Logical	0	0
Event	0	0

 LINE       45
 EXPRESSION (((~filter_out_d)) & filter_out_q)
             --------1--------   ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       46
 EXPRESSION (filter_out_d & ((~filter_out_q)))
             ------1-----   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       50
 EXPRESSION (cnt_eq_th ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : '0))
             ----1----

-1-	Status	Tests
0	Covered	T74
1	Covered	T1,T2,T3

 LINE       50
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : '0)
                 ---1--

-1-	Status	Tests
0	Covered	T74
1	Not Covered

 LINE       63
 EXPRESSION (rising | falling)
             ---1--   ---2---

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[3].u_pinmux_wkup

	Line No.	Total	Covered	Percent
Branches		11	5	45.45
TERNARY	50	3	2	66.67
IF	57	6	1	16.67
IF	82	2	2	100.00

50           assign cnt_d     = (cnt_eq_th) ? '0 : (cnt_en) ? cnt_q + 1'b1 : '0;
                                            -1-             -2-   
                                            ==>             ==>   
                                                            ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T74

57             if (wkup_en_i) begin
               -1-  
58               unique case (wkup_mode_i)
                        -2-  
59                 Negedge: begin
60                   aon_wkup_pulse_o = falling;
                     ==>
61                 end
62                 Edge: begin
63                   aon_wkup_pulse_o = rising | falling;
                     ==>
64                 end
65                 HighTimed: begin
66                   cnt_en = filter_out_d;
                     ==>
67                   aon_wkup_pulse_o = cnt_eq_th;
68                 end
69                 LowTimed: begin
70                   cnt_en = ~filter_out_d;
                     ==>
71                   aon_wkup_pulse_o = cnt_eq_th;
72                 end
73                 // Default to rising
74                 default: begin
75                   aon_wkup_pulse_o = rising;
                     ==>
76                 end
77               endcase
78             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	Negedge	Not Covered
1	Edge	Not Covered
1	HighTimed	Not Covered
1	LowTimed	Not Covered
1	default	Not Covered
0	-	Covered	T74

82             if (!rst_ni) begin
               -1-  
83               filter_out_q <= 1'b0;
                 ==>
84               cnt_q        <= '0;
85             end else begin
86               filter_out_q <= filter_out_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[7].u_pinmux_wkup

	Line No.	Total	Covered	Percent
TOTAL		19	12	63.16
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	46	1	1	100.00
CONT_ASSIGN	50	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
ALWAYS	55	10	3	30.00
ALWAYS	82	5	5	100.00

44                        logic rising, falling;
45         1/1            assign falling = ~filter_out_d & filter_out_q;
           Tests:       T74 
46         1/1            assign rising  = filter_out_d & ~filter_out_q;
           Tests:       T74 
47                      
48                        logic cnt_en, cnt_eq_th;
49                        logic [WkupCntWidth-1:0] cnt_d, cnt_q;
50         1/1            assign cnt_d     = (cnt_eq_th) ? '0 : (cnt_en) ? cnt_q + 1'b1 : '0;
           Tests:       T74 
51                      
52         1/1            assign cnt_eq_th = (cnt_q >= wkup_cnt_th_i);
           Tests:       T74 
53                      
54                        always_comb begin : p_mode
55         1/1              aon_wkup_pulse_o = 1'b0;
           Tests:       T74 
56         1/1              cnt_en           = 1'b0;
           Tests:       T74 
57         1/1              if (wkup_en_i) begin
           Tests:       T74 
58         0/1     ==>        unique case (wkup_mode_i)
59                              Negedge: begin
60         0/1     ==>            aon_wkup_pulse_o = falling;
61                              end
62                              Edge: begin
63         0/1     ==>            aon_wkup_pulse_o = rising | falling;
64                              end
65                              HighTimed: begin
66         0/1     ==>            cnt_en = filter_out_d;
67         0/1     ==>            aon_wkup_pulse_o = cnt_eq_th;
68                              end
69                              LowTimed: begin
70         0/1     ==>            cnt_en = ~filter_out_d;
71         0/1     ==>            aon_wkup_pulse_o = cnt_eq_th;
72                              end
73                              // Default to rising
74                              default: begin
75                                aon_wkup_pulse_o = rising;
76                              end
77                            endcase
78                          end
                        MISSING_ELSE
79                        end
80                      
81                        always_ff @(posedge clk_i or negedge rst_ni) begin : p_aon_pattern
82         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
83         1/1                filter_out_q <= 1'b0;
           Tests:       T1 T2 T3 
84         1/1                cnt_q        <= '0;
           Tests:       T1 T2 T3 
85                          end else begin
86         1/1                filter_out_q <= filter_out_d;
           Tests:       T1 T2 T3 
87         1/1                cnt_q        <= cnt_d;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[7].u_pinmux_wkup

	Total	Covered	Percent
Conditions	13	9	69.23
Logical	13	9	69.23
Non-Logical	0	0
Event	0	0

 LINE       45
 EXPRESSION (((~filter_out_d)) & filter_out_q)
             --------1--------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T74
1	0	Covered	T1,T2,T3
1	1	Covered	T74

 LINE       46
 EXPRESSION (filter_out_d & ((~filter_out_q)))
             ------1-----   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T74
1	1	Covered	T74

 LINE       50
 EXPRESSION (cnt_eq_th ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : '0))
             ----1----

-1-	Status	Tests
0	Covered	T74
1	Covered	T1,T2,T3

 LINE       50
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : '0)
                 ---1--

-1-	Status	Tests
0	Covered	T74
1	Not Covered

 LINE       63
 EXPRESSION (rising | falling)
             ---1--   ---2---

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[7].u_pinmux_wkup

	Line No.	Total	Covered	Percent
Branches		11	5	45.45
TERNARY	50	3	2	66.67
IF	57	6	1	16.67
IF	82	2	2	100.00

50           assign cnt_d     = (cnt_eq_th) ? '0 : (cnt_en) ? cnt_q + 1'b1 : '0;
                                            -1-             -2-   
                                            ==>             ==>   
                                                            ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T74

57             if (wkup_en_i) begin
               -1-  
58               unique case (wkup_mode_i)
                        -2-  
59                 Negedge: begin
60                   aon_wkup_pulse_o = falling;
                     ==>
61                 end
62                 Edge: begin
63                   aon_wkup_pulse_o = rising | falling;
                     ==>
64                 end
65                 HighTimed: begin
66                   cnt_en = filter_out_d;
                     ==>
67                   aon_wkup_pulse_o = cnt_eq_th;
68                 end
69                 LowTimed: begin
70                   cnt_en = ~filter_out_d;
                     ==>
71                   aon_wkup_pulse_o = cnt_eq_th;
72                 end
73                 // Default to rising
74                 default: begin
75                   aon_wkup_pulse_o = rising;
                     ==>
76                 end
77               endcase
78             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	Negedge	Not Covered
1	Edge	Not Covered
1	HighTimed	Not Covered
1	LowTimed	Not Covered
1	default	Not Covered
0	-	Covered	T74

82             if (!rst_ni) begin
               -1-  
83               filter_out_q <= 1'b0;
                 ==>
84               cnt_q        <= '0;
85             end else begin
86               filter_out_q <= filter_out_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[2].u_pinmux_wkup

	Line No.	Total	Covered	Percent
TOTAL		19	13	68.42
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	46	1	1	100.00
CONT_ASSIGN	50	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
ALWAYS	55	10	4	40.00
ALWAYS	82	5	5	100.00

44                        logic rising, falling;
45         1/1            assign falling = ~filter_out_d & filter_out_q;
           Tests:       T26 
46         1/1            assign rising  = filter_out_d & ~filter_out_q;
           Tests:       T26 
47                      
48                        logic cnt_en, cnt_eq_th;
49                        logic [WkupCntWidth-1:0] cnt_d, cnt_q;
50         1/1            assign cnt_d     = (cnt_eq_th) ? '0 : (cnt_en) ? cnt_q + 1'b1 : '0;
           Tests:       T74 
51                      
52         1/1            assign cnt_eq_th = (cnt_q >= wkup_cnt_th_i);
           Tests:       T74 
53                      
54                        always_comb begin : p_mode
55         1/1              aon_wkup_pulse_o = 1'b0;
           Tests:       T26 T74 
56         1/1              cnt_en           = 1'b0;
           Tests:       T26 T74 
57         1/1              if (wkup_en_i) begin
           Tests:       T26 T74 
58         1/1                unique case (wkup_mode_i)
           Tests:       T26 
59                              Negedge: begin
60         0/1     ==>            aon_wkup_pulse_o = falling;
61                              end
62                              Edge: begin
63         0/1     ==>            aon_wkup_pulse_o = rising | falling;
64                              end
65                              HighTimed: begin
66         0/1     ==>            cnt_en = filter_out_d;
67         0/1     ==>            aon_wkup_pulse_o = cnt_eq_th;
68                              end
69                              LowTimed: begin
70         0/1     ==>            cnt_en = ~filter_out_d;
71         0/1     ==>            aon_wkup_pulse_o = cnt_eq_th;
72                              end
73                              // Default to rising
74                              default: begin
75                                aon_wkup_pulse_o = rising;
76                              end
77                            endcase
78                          end
                        MISSING_ELSE
79                        end
80                      
81                        always_ff @(posedge clk_i or negedge rst_ni) begin : p_aon_pattern
82         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
83         1/1                filter_out_q <= 1'b0;
           Tests:       T1 T2 T3 
84         1/1                cnt_q        <= '0;
           Tests:       T1 T2 T3 
85                          end else begin
86         1/1                filter_out_q <= filter_out_d;
           Tests:       T1 T2 T3 
87         1/1                cnt_q        <= cnt_d;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[2].u_pinmux_wkup

	Total	Covered	Percent
Conditions	13	8	61.54
Logical	13	8	61.54
Non-Logical	0	0
Event	0	0

 LINE       45
 EXPRESSION (((~filter_out_d)) & filter_out_q)
             --------1--------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T26
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       46
 EXPRESSION (filter_out_d & ((~filter_out_q)))
             ------1-----   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T26
1	1	Covered	T26

 LINE       50
 EXPRESSION (cnt_eq_th ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : '0))
             ----1----

-1-	Status	Tests
0	Covered	T74
1	Covered	T1,T2,T3

 LINE       50
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : '0)
                 ---1--

-1-	Status	Tests
0	Covered	T74
1	Not Covered

 LINE       63
 EXPRESSION (rising | falling)
             ---1--   ---2---

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[2].u_pinmux_wkup

	Line No.	Total	Covered	Percent
Branches		11	6	54.55
TERNARY	50	3	2	66.67
IF	57	6	2	33.33
IF	82	2	2	100.00

50           assign cnt_d     = (cnt_eq_th) ? '0 : (cnt_en) ? cnt_q + 1'b1 : '0;
                                            -1-             -2-   
                                            ==>             ==>   
                                                            ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T74

57             if (wkup_en_i) begin
               -1-  
58               unique case (wkup_mode_i)
                        -2-  
59                 Negedge: begin
60                   aon_wkup_pulse_o = falling;
                     ==>
61                 end
62                 Edge: begin
63                   aon_wkup_pulse_o = rising | falling;
                     ==>
64                 end
65                 HighTimed: begin
66                   cnt_en = filter_out_d;
                     ==>
67                   aon_wkup_pulse_o = cnt_eq_th;
68                 end
69                 LowTimed: begin
70                   cnt_en = ~filter_out_d;
                     ==>
71                   aon_wkup_pulse_o = cnt_eq_th;
72                 end
73                 // Default to rising
74                 default: begin
75                   aon_wkup_pulse_o = rising;
                     ==>
76                 end
77               endcase
78             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	Negedge	Not Covered
1	Edge	Not Covered
1	HighTimed	Not Covered
1	LowTimed	Not Covered
1	default	Covered	T26
0	-	Covered	T26,T74

82             if (!rst_ni) begin
               -1-  
83               filter_out_q <= 1'b0;
                 ==>
84               cnt_q        <= '0;
85             end else begin
86               filter_out_q <= filter_out_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[4].u_pinmux_wkup

	Line No.	Total	Covered	Percent
TOTAL		19	13	68.42
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	46	1	1	100.00
CONT_ASSIGN	50	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
ALWAYS	55	10	4	40.00
ALWAYS	82	5	5	100.00

44                        logic rising, falling;
45         1/1            assign falling = ~filter_out_d & filter_out_q;
           Tests:       T74 T27 
46         1/1            assign rising  = filter_out_d & ~filter_out_q;
           Tests:       T74 T27 
47                      
48                        logic cnt_en, cnt_eq_th;
49                        logic [WkupCntWidth-1:0] cnt_d, cnt_q;
50         1/1            assign cnt_d     = (cnt_eq_th) ? '0 : (cnt_en) ? cnt_q + 1'b1 : '0;
           Tests:       T74 
51                      
52         1/1            assign cnt_eq_th = (cnt_q >= wkup_cnt_th_i);
           Tests:       T74 
53                      
54                        always_comb begin : p_mode
55         1/1              aon_wkup_pulse_o = 1'b0;
           Tests:       T74 T27 
56         1/1              cnt_en           = 1'b0;
           Tests:       T74 T27 
57         1/1              if (wkup_en_i) begin
           Tests:       T74 T27 
58         1/1                unique case (wkup_mode_i)
           Tests:       T27 
59                              Negedge: begin
60         0/1     ==>            aon_wkup_pulse_o = falling;
61                              end
62                              Edge: begin
63         0/1     ==>            aon_wkup_pulse_o = rising | falling;
64                              end
65                              HighTimed: begin
66         0/1     ==>            cnt_en = filter_out_d;
67         0/1     ==>            aon_wkup_pulse_o = cnt_eq_th;
68                              end
69                              LowTimed: begin
70         0/1     ==>            cnt_en = ~filter_out_d;
71         0/1     ==>            aon_wkup_pulse_o = cnt_eq_th;
72                              end
73                              // Default to rising
74                              default: begin
75                                aon_wkup_pulse_o = rising;
76                              end
77                            endcase
78                          end
                        MISSING_ELSE
79                        end
80                      
81                        always_ff @(posedge clk_i or negedge rst_ni) begin : p_aon_pattern
82         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
83         1/1                filter_out_q <= 1'b0;
           Tests:       T1 T2 T3 
84         1/1                cnt_q        <= '0;
           Tests:       T1 T2 T3 
85                          end else begin
86         1/1                filter_out_q <= filter_out_d;
           Tests:       T1 T2 T3 
87         1/1                cnt_q        <= cnt_d;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[4].u_pinmux_wkup

	Total	Covered	Percent
Conditions	13	9	69.23
Logical	13	9	69.23
Non-Logical	0	0
Event	0	0

 LINE       45
 EXPRESSION (((~filter_out_d)) & filter_out_q)
             --------1--------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T74,T27
1	0	Covered	T1,T2,T3
1	1	Covered	T74,T27

 LINE       46
 EXPRESSION (filter_out_d & ((~filter_out_q)))
             ------1-----   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T74,T27
1	1	Covered	T74,T27

 LINE       50
 EXPRESSION (cnt_eq_th ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : '0))
             ----1----

-1-	Status	Tests
0	Covered	T74
1	Covered	T1,T2,T3

 LINE       50
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : '0)
                 ---1--

-1-	Status	Tests
0	Covered	T74
1	Not Covered

 LINE       63
 EXPRESSION (rising | falling)
             ---1--   ---2---

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[4].u_pinmux_wkup

	Line No.	Total	Covered	Percent
Branches		11	6	54.55
TERNARY	50	3	2	66.67
IF	57	6	2	33.33
IF	82	2	2	100.00

50           assign cnt_d     = (cnt_eq_th) ? '0 : (cnt_en) ? cnt_q + 1'b1 : '0;
                                            -1-             -2-   
                                            ==>             ==>   
                                                            ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T74

57             if (wkup_en_i) begin
               -1-  
58               unique case (wkup_mode_i)
                        -2-  
59                 Negedge: begin
60                   aon_wkup_pulse_o = falling;
                     ==>
61                 end
62                 Edge: begin
63                   aon_wkup_pulse_o = rising | falling;
                     ==>
64                 end
65                 HighTimed: begin
66                   cnt_en = filter_out_d;
                     ==>
67                   aon_wkup_pulse_o = cnt_eq_th;
68                 end
69                 LowTimed: begin
70                   cnt_en = ~filter_out_d;
                     ==>
71                   aon_wkup_pulse_o = cnt_eq_th;
72                 end
73                 // Default to rising
74                 default: begin
75                   aon_wkup_pulse_o = rising;
                     ==>
76                 end
77               endcase
78             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	Negedge	Not Covered
1	Edge	Not Covered
1	HighTimed	Not Covered
1	LowTimed	Not Covered
1	default	Covered	T27
0	-	Covered	T74,T27

82             if (!rst_ni) begin
               -1-  
83               filter_out_q <= 1'b0;
                 ==>
84               cnt_q        <= '0;
85             end else begin
86               filter_out_q <= filter_out_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[5].u_pinmux_wkup

	Line No.	Total	Covered	Percent
TOTAL		19	13	68.42
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	46	1	1	100.00
CONT_ASSIGN	50	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
ALWAYS	55	10	4	40.00
ALWAYS	82	5	5	100.00

44                        logic rising, falling;
45         1/1            assign falling = ~filter_out_d & filter_out_q;
           Tests:       T77 T78 T79 
46         1/1            assign rising  = filter_out_d & ~filter_out_q;
           Tests:       T77 T78 T79 
47                      
48                        logic cnt_en, cnt_eq_th;
49                        logic [WkupCntWidth-1:0] cnt_d, cnt_q;
50         1/1            assign cnt_d     = (cnt_eq_th) ? '0 : (cnt_en) ? cnt_q + 1'b1 : '0;
           Tests:       T74 
51                      
52         1/1            assign cnt_eq_th = (cnt_q >= wkup_cnt_th_i);
           Tests:       T74 
53                      
54                        always_comb begin : p_mode
55         1/1              aon_wkup_pulse_o = 1'b0;
           Tests:       T77 T78 T79 
56         1/1              cnt_en           = 1'b0;
           Tests:       T77 T78 T79 
57         1/1              if (wkup_en_i) begin
           Tests:       T77 T78 T79 
58         1/1                unique case (wkup_mode_i)
           Tests:       T77 T78 T79 
59                              Negedge: begin
60         0/1     ==>            aon_wkup_pulse_o = falling;
61                              end
62                              Edge: begin
63         0/1     ==>            aon_wkup_pulse_o = rising | falling;
64                              end
65                              HighTimed: begin
66         0/1     ==>            cnt_en = filter_out_d;
67         0/1     ==>            aon_wkup_pulse_o = cnt_eq_th;
68                              end
69                              LowTimed: begin
70         0/1     ==>            cnt_en = ~filter_out_d;
71         0/1     ==>            aon_wkup_pulse_o = cnt_eq_th;
72                              end
73                              // Default to rising
74                              default: begin
75                                aon_wkup_pulse_o = rising;
76                              end
77                            endcase
78                          end
                        MISSING_ELSE
79                        end
80                      
81                        always_ff @(posedge clk_i or negedge rst_ni) begin : p_aon_pattern
82         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
83         1/1                filter_out_q <= 1'b0;
           Tests:       T1 T2 T3 
84         1/1                cnt_q        <= '0;
           Tests:       T1 T2 T3 
85                          end else begin
86         1/1                filter_out_q <= filter_out_d;
           Tests:       T1 T2 T3 
87         1/1                cnt_q        <= cnt_d;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[5].u_pinmux_wkup

	Total	Covered	Percent
Conditions	13	9	69.23
Logical	13	9	69.23
Non-Logical	0	0
Event	0	0

 LINE       45
 EXPRESSION (((~filter_out_d)) & filter_out_q)
             --------1--------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T77,T78,T79
1	0	Covered	T1,T2,T3
1	1	Covered	T77,T78,T79

 LINE       46
 EXPRESSION (filter_out_d & ((~filter_out_q)))
             ------1-----   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T77,T78,T79
1	1	Covered	T77,T78,T79

 LINE       50
 EXPRESSION (cnt_eq_th ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : '0))
             ----1----

-1-	Status	Tests
0	Covered	T74
1	Covered	T1,T2,T3

 LINE       50
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : '0)
                 ---1--

-1-	Status	Tests
0	Covered	T74
1	Not Covered

 LINE       63
 EXPRESSION (rising | falling)
             ---1--   ---2---

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[5].u_pinmux_wkup

	Line No.	Total	Covered	Percent
Branches		11	6	54.55
TERNARY	50	3	2	66.67
IF	57	6	2	33.33
IF	82	2	2	100.00

50           assign cnt_d     = (cnt_eq_th) ? '0 : (cnt_en) ? cnt_q + 1'b1 : '0;
                                            -1-             -2-   
                                            ==>             ==>   
                                                            ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T74

57             if (wkup_en_i) begin
               -1-  
58               unique case (wkup_mode_i)
                        -2-  
59                 Negedge: begin
60                   aon_wkup_pulse_o = falling;
                     ==>
61                 end
62                 Edge: begin
63                   aon_wkup_pulse_o = rising | falling;
                     ==>
64                 end
65                 HighTimed: begin
66                   cnt_en = filter_out_d;
                     ==>
67                   aon_wkup_pulse_o = cnt_eq_th;
68                 end
69                 LowTimed: begin
70                   cnt_en = ~filter_out_d;
                     ==>
71                   aon_wkup_pulse_o = cnt_eq_th;
72                 end
73                 // Default to rising
74                 default: begin
75                   aon_wkup_pulse_o = rising;
                     ==>
76                 end
77               endcase
78             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	Negedge	Not Covered
1	Edge	Not Covered
1	HighTimed	Not Covered
1	LowTimed	Not Covered
1	default	Covered	T77,T78,T79
0	-	Covered	T78,T74,T129

82             if (!rst_ni) begin
               -1-  
83               filter_out_q <= 1'b0;
                 ==>
84               cnt_q        <= '0;
85             end else begin
86               filter_out_q <= filter_out_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[0].u_pinmux_wkup

	Line No.	Total	Covered	Percent
TOTAL		19	15	78.95
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	46	1	1	100.00
CONT_ASSIGN	50	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
ALWAYS	55	10	6	60.00
ALWAYS	82	5	5	100.00

44                        logic rising, falling;
45         1/1            assign falling = ~filter_out_d & filter_out_q;
           Tests:       T6 T25 T29 
46         1/1            assign rising  = filter_out_d & ~filter_out_q;
           Tests:       T6 T25 T29 
47                      
48                        logic cnt_en, cnt_eq_th;
49                        logic [WkupCntWidth-1:0] cnt_d, cnt_q;
50         1/1            assign cnt_d     = (cnt_eq_th) ? '0 : (cnt_en) ? cnt_q + 1'b1 : '0;
           Tests:       T74 
51                      
52         1/1            assign cnt_eq_th = (cnt_q >= wkup_cnt_th_i);
           Tests:       T74 
53                      
54                        always_comb begin : p_mode
55         1/1              aon_wkup_pulse_o = 1'b0;
           Tests:       T6 T25 T29 
56         1/1              cnt_en           = 1'b0;
           Tests:       T6 T25 T29 
57         1/1              if (wkup_en_i) begin
           Tests:       T6 T25 T29 
58         1/1                unique case (wkup_mode_i)
           Tests:       T6 T25 T29 
59                              Negedge: begin
60         1/1                    aon_wkup_pulse_o = falling;
           Tests:       T6 T84 T85 
61                              end
62                              Edge: begin
63         1/1                    aon_wkup_pulse_o = rising | falling;
           Tests:       T6 T84 T85 
64                              end
65                              HighTimed: begin
66         0/1     ==>            cnt_en = filter_out_d;
67         0/1     ==>            aon_wkup_pulse_o = cnt_eq_th;
68                              end
69                              LowTimed: begin
70         0/1     ==>            cnt_en = ~filter_out_d;
71         0/1     ==>            aon_wkup_pulse_o = cnt_eq_th;
72                              end
73                              // Default to rising
74                              default: begin
75                                aon_wkup_pulse_o = rising;
76                              end
77                            endcase
78                          end
                        MISSING_ELSE
79                        end
80                      
81                        always_ff @(posedge clk_i or negedge rst_ni) begin : p_aon_pattern
82         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
83         1/1                filter_out_q <= 1'b0;
           Tests:       T1 T2 T3 
84         1/1                cnt_q        <= '0;
           Tests:       T1 T2 T3 
85                          end else begin
86         1/1                filter_out_q <= filter_out_d;
           Tests:       T1 T2 T3 
87         1/1                cnt_q        <= cnt_d;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[0].u_pinmux_wkup

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       45
 EXPRESSION (((~filter_out_d)) & filter_out_q)
             --------1--------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T25,T29
1	0	Covered	T1,T2,T3
1	1	Covered	T6,T29,T76

 LINE       46
 EXPRESSION (filter_out_d & ((~filter_out_q)))
             ------1-----   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T25,T29
1	1	Covered	T6,T25,T29

 LINE       50
 EXPRESSION (cnt_eq_th ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : '0))
             ----1----

-1-	Status	Tests
0	Covered	T74
1	Covered	T1,T2,T3

 LINE       50
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : '0)
                 ---1--

-1-	Status	Tests
0	Covered	T74
1	Not Covered

 LINE       63
 EXPRESSION (rising | falling)
             ---1--   ---2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T84,T85
0	1	Covered	T6,T84,T85
1	0	Covered	T6,T84,T85

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[0].u_pinmux_wkup

	Line No.	Total	Covered	Percent
Branches		11	8	72.73
TERNARY	50	3	2	66.67
IF	57	6	4	66.67
IF	82	2	2	100.00

50           assign cnt_d     = (cnt_eq_th) ? '0 : (cnt_en) ? cnt_q + 1'b1 : '0;
                                            -1-             -2-   
                                            ==>             ==>   
                                                            ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T74

57             if (wkup_en_i) begin
               -1-  
58               unique case (wkup_mode_i)
                        -2-  
59                 Negedge: begin
60                   aon_wkup_pulse_o = falling;
                     ==>
61                 end
62                 Edge: begin
63                   aon_wkup_pulse_o = rising | falling;
                     ==>
64                 end
65                 HighTimed: begin
66                   cnt_en = filter_out_d;
                     ==>
67                   aon_wkup_pulse_o = cnt_eq_th;
68                 end
69                 LowTimed: begin
70                   cnt_en = ~filter_out_d;
                     ==>
71                   aon_wkup_pulse_o = cnt_eq_th;
72                 end
73                 // Default to rising
74                 default: begin
75                   aon_wkup_pulse_o = rising;
                     ==>
76                 end
77               endcase
78             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	Negedge	Covered	T6,T84,T85
1	Edge	Covered	T6,T84,T85
1	HighTimed	Not Covered
1	LowTimed	Not Covered
1	default	Covered	T25,T29,T76
0	-	Covered	T6,T84,T74

82             if (!rst_ni) begin
               -1-  
83               filter_out_q <= 1'b0;
                 ==>
84               cnt_q        <= '0;
85             end else begin
86               filter_out_q <= filter_out_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3