Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Line Coverage for Module : pinmux
Line No.TotalCoveredPercent
TOTAL1282102179.64
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CONT_ASSIGN48911100.00
CONT_ASSIGN48911100.00
CONT_ASSIGN48911100.00
CONT_ASSIGN48911100.00
CONT_ASSIGN48911100.00
CONT_ASSIGN48911100.00
CONT_ASSIGN48911100.00
CONT_ASSIGN48911100.00
CONT_ASSIGN48911100.00
CONT_ASSIGN48911100.00
CONT_ASSIGN48911100.00
CONT_ASSIGN48911100.00
CONT_ASSIGN48911100.00
CONT_ASSIGN48911100.00
CONT_ASSIGN48911100.00
CONT_ASSIGN48911100.00
CONT_ASSIGN48911100.00
CONT_ASSIGN48911100.00
CONT_ASSIGN48911100.00
CONT_ASSIGN48911100.00
CONT_ASSIGN48911100.00
CONT_ASSIGN48911100.00
CONT_ASSIGN48911100.00
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CONT_ASSIGN48911100.00
CONT_ASSIGN48911100.00
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CONT_ASSIGN48911100.00
CONT_ASSIGN48911100.00
CONT_ASSIGN48911100.00
CONT_ASSIGN48911100.00
CONT_ASSIGN48911100.00
CONT_ASSIGN48911100.00
CONT_ASSIGN48911100.00
CONT_ASSIGN48911100.00
CONT_ASSIGN48911100.00
CONT_ASSIGN48911100.00
CONT_ASSIGN48911100.00
CONT_ASSIGN48911100.00
CONT_ASSIGN48911100.00
CONT_ASSIGN48911100.00
CONT_ASSIGN48911100.00
CONT_ASSIGN49311100.00
CONT_ASSIGN49311100.00
CONT_ASSIGN49311100.00
CONT_ASSIGN49311100.00
CONT_ASSIGN49311100.00
CONT_ASSIGN49311100.00
CONT_ASSIGN49311100.00
CONT_ASSIGN49311100.00
CONT_ASSIGN49311100.00
CONT_ASSIGN49311100.00
CONT_ASSIGN49311100.00
CONT_ASSIGN49311100.00
CONT_ASSIGN49311100.00
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CONT_ASSIGN49311100.00
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CONT_ASSIGN49311100.00
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CONT_ASSIGN49311100.00
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CONT_ASSIGN49311100.00
CONT_ASSIGN49311100.00
CONT_ASSIGN49311100.00
CONT_ASSIGN49311100.00
CONT_ASSIGN49311100.00
CONT_ASSIGN49311100.00
CONT_ASSIGN49311100.00
CONT_ASSIGN50211100.00
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CONT_ASSIGN50211100.00
CONT_ASSIGN50211100.00
CONT_ASSIGN50211100.00
CONT_ASSIGN50211100.00
CONT_ASSIGN50211100.00
CONT_ASSIGN50211100.00
CONT_ASSIGN50211100.00
CONT_ASSIGN50211100.00
CONT_ASSIGN50211100.00
CONT_ASSIGN50211100.00
CONT_ASSIGN50211100.00
CONT_ASSIGN50211100.00
CONT_ASSIGN50211100.00
CONT_ASSIGN50211100.00
CONT_ASSIGN50211100.00
CONT_ASSIGN50211100.00
CONT_ASSIGN50211100.00
CONT_ASSIGN50211100.00
CONT_ASSIGN50211100.00
CONT_ASSIGN50211100.00
CONT_ASSIGN50211100.00
CONT_ASSIGN50211100.00
CONT_ASSIGN50211100.00
CONT_ASSIGN50211100.00
CONT_ASSIGN50211100.00
CONT_ASSIGN50211100.00
CONT_ASSIGN50211100.00
CONT_ASSIGN50211100.00
CONT_ASSIGN50211100.00
CONT_ASSIGN50211100.00
CONT_ASSIGN50211100.00
CONT_ASSIGN50211100.00
CONT_ASSIGN50211100.00
CONT_ASSIGN50211100.00
CONT_ASSIGN50211100.00
CONT_ASSIGN50211100.00
CONT_ASSIGN50211100.00
CONT_ASSIGN50211100.00
CONT_ASSIGN50611100.00
CONT_ASSIGN50611100.00
CONT_ASSIGN50611100.00
CONT_ASSIGN50611100.00
CONT_ASSIGN50611100.00
CONT_ASSIGN50611100.00
CONT_ASSIGN50611100.00
CONT_ASSIGN50611100.00
CONT_ASSIGN50611100.00
CONT_ASSIGN50611100.00
CONT_ASSIGN50611100.00
CONT_ASSIGN50611100.00
CONT_ASSIGN50611100.00
CONT_ASSIGN50611100.00
CONT_ASSIGN50611100.00
CONT_ASSIGN50611100.00
CONT_ASSIGN50611100.00
CONT_ASSIGN50611100.00
CONT_ASSIGN50611100.00
CONT_ASSIGN50611100.00
CONT_ASSIGN50611100.00
CONT_ASSIGN50611100.00
CONT_ASSIGN50611100.00
CONT_ASSIGN50611100.00
CONT_ASSIGN50611100.00
CONT_ASSIGN50611100.00
CONT_ASSIGN50611100.00
CONT_ASSIGN50611100.00
CONT_ASSIGN50611100.00
CONT_ASSIGN50611100.00
CONT_ASSIGN50611100.00
CONT_ASSIGN50611100.00
CONT_ASSIGN50611100.00
CONT_ASSIGN50611100.00
CONT_ASSIGN50611100.00
CONT_ASSIGN50611100.00
CONT_ASSIGN50611100.00
CONT_ASSIGN50611100.00
CONT_ASSIGN50611100.00
CONT_ASSIGN50611100.00
CONT_ASSIGN50611100.00
CONT_ASSIGN50611100.00
CONT_ASSIGN50611100.00
CONT_ASSIGN50611100.00
CONT_ASSIGN50611100.00
CONT_ASSIGN50611100.00
CONT_ASSIGN50611100.00
CONT_ASSIGN51111100.00
CONT_ASSIGN51111100.00
CONT_ASSIGN51111100.00
CONT_ASSIGN51111100.00
CONT_ASSIGN51111100.00
CONT_ASSIGN51111100.00
CONT_ASSIGN51111100.00
CONT_ASSIGN51111100.00
CONT_ASSIGN51111100.00
CONT_ASSIGN51111100.00
CONT_ASSIGN51111100.00
CONT_ASSIGN51111100.00
CONT_ASSIGN51111100.00
CONT_ASSIGN51111100.00
CONT_ASSIGN51111100.00
CONT_ASSIGN51111100.00
CONT_ASSIGN51111100.00
CONT_ASSIGN51111100.00
CONT_ASSIGN51111100.00
CONT_ASSIGN51111100.00
CONT_ASSIGN51111100.00
CONT_ASSIGN51111100.00
CONT_ASSIGN51111100.00
CONT_ASSIGN51111100.00
CONT_ASSIGN51111100.00
CONT_ASSIGN51111100.00
CONT_ASSIGN51111100.00
CONT_ASSIGN51111100.00
CONT_ASSIGN51111100.00
CONT_ASSIGN51111100.00
CONT_ASSIGN51111100.00
CONT_ASSIGN51111100.00
CONT_ASSIGN51111100.00
CONT_ASSIGN51111100.00
CONT_ASSIGN51111100.00
CONT_ASSIGN51111100.00
CONT_ASSIGN51111100.00
CONT_ASSIGN51111100.00
CONT_ASSIGN51111100.00
CONT_ASSIGN51111100.00
CONT_ASSIGN51111100.00
CONT_ASSIGN51111100.00
CONT_ASSIGN51111100.00
CONT_ASSIGN51111100.00
CONT_ASSIGN51111100.00
CONT_ASSIGN51111100.00
CONT_ASSIGN51111100.00
CONT_ASSIGN51311100.00
CONT_ASSIGN51311100.00
CONT_ASSIGN51311100.00
CONT_ASSIGN51311100.00
CONT_ASSIGN51311100.00
CONT_ASSIGN51311100.00
CONT_ASSIGN51311100.00
CONT_ASSIGN51311100.00
CONT_ASSIGN51311100.00
CONT_ASSIGN51311100.00
CONT_ASSIGN51311100.00
CONT_ASSIGN51311100.00
CONT_ASSIGN51311100.00
CONT_ASSIGN51311100.00
CONT_ASSIGN51311100.00
CONT_ASSIGN51311100.00
CONT_ASSIGN51311100.00
CONT_ASSIGN51311100.00
CONT_ASSIGN51311100.00
CONT_ASSIGN51311100.00
CONT_ASSIGN51311100.00
CONT_ASSIGN51311100.00
CONT_ASSIGN51311100.00
CONT_ASSIGN51311100.00
CONT_ASSIGN51311100.00
CONT_ASSIGN51311100.00
CONT_ASSIGN51311100.00
CONT_ASSIGN51311100.00
CONT_ASSIGN51311100.00
CONT_ASSIGN51311100.00
CONT_ASSIGN51311100.00
CONT_ASSIGN51311100.00
CONT_ASSIGN51311100.00
CONT_ASSIGN51311100.00
CONT_ASSIGN51311100.00
CONT_ASSIGN51311100.00
CONT_ASSIGN51311100.00
CONT_ASSIGN51311100.00
CONT_ASSIGN51311100.00
CONT_ASSIGN51311100.00
CONT_ASSIGN51311100.00
CONT_ASSIGN51311100.00
CONT_ASSIGN51311100.00
CONT_ASSIGN51311100.00
CONT_ASSIGN51311100.00
CONT_ASSIGN51311100.00
CONT_ASSIGN51311100.00
CONT_ASSIGN52111100.00
CONT_ASSIGN52511100.00
CONT_ASSIGN52511100.00
CONT_ASSIGN52511100.00
CONT_ASSIGN52511100.00
CONT_ASSIGN52511100.00
CONT_ASSIGN52511100.00
CONT_ASSIGN52511100.00
CONT_ASSIGN52511100.00
CONT_ASSIGN52511100.00
CONT_ASSIGN52511100.00
CONT_ASSIGN52511100.00
CONT_ASSIGN52511100.00
CONT_ASSIGN52511100.00
CONT_ASSIGN52511100.00
CONT_ASSIGN52511100.00
CONT_ASSIGN52511100.00
CONT_ASSIGN52911100.00
CONT_ASSIGN52911100.00
CONT_ASSIGN52911100.00
CONT_ASSIGN52911100.00
CONT_ASSIGN52911100.00
CONT_ASSIGN52911100.00
CONT_ASSIGN52911100.00
CONT_ASSIGN52911100.00
CONT_ASSIGN52911100.00
CONT_ASSIGN52911100.00
CONT_ASSIGN52911100.00
CONT_ASSIGN52911100.00
CONT_ASSIGN52911100.00
CONT_ASSIGN52911100.00
CONT_ASSIGN52911100.00
CONT_ASSIGN52911100.00
CONT_ASSIGN53811100.00
CONT_ASSIGN53811100.00
CONT_ASSIGN53811100.00
CONT_ASSIGN53811100.00
CONT_ASSIGN53811100.00
CONT_ASSIGN53811100.00
CONT_ASSIGN53811100.00
CONT_ASSIGN53811100.00
CONT_ASSIGN53811100.00
CONT_ASSIGN53811100.00
CONT_ASSIGN53811100.00
CONT_ASSIGN53811100.00
CONT_ASSIGN53811100.00
CONT_ASSIGN53811100.00
CONT_ASSIGN53811100.00
CONT_ASSIGN53811100.00
CONT_ASSIGN54211100.00
CONT_ASSIGN54211100.00
CONT_ASSIGN54211100.00
CONT_ASSIGN54211100.00
CONT_ASSIGN54211100.00
CONT_ASSIGN54211100.00
CONT_ASSIGN54211100.00
CONT_ASSIGN54211100.00
CONT_ASSIGN54211100.00
CONT_ASSIGN54211100.00
CONT_ASSIGN54211100.00
CONT_ASSIGN54211100.00
CONT_ASSIGN54211100.00
CONT_ASSIGN54211100.00
CONT_ASSIGN54211100.00
CONT_ASSIGN54211100.00
CONT_ASSIGN54711100.00
CONT_ASSIGN54711100.00
CONT_ASSIGN54711100.00
CONT_ASSIGN54711100.00
CONT_ASSIGN54711100.00
CONT_ASSIGN54711100.00
CONT_ASSIGN54711100.00
CONT_ASSIGN54711100.00
CONT_ASSIGN54711100.00
CONT_ASSIGN54711100.00
CONT_ASSIGN54711100.00
CONT_ASSIGN54711100.00
CONT_ASSIGN54711100.00
CONT_ASSIGN54711100.00
CONT_ASSIGN54711100.00
CONT_ASSIGN54711100.00
CONT_ASSIGN54911100.00
CONT_ASSIGN54911100.00
CONT_ASSIGN54911100.00
CONT_ASSIGN54911100.00
CONT_ASSIGN54911100.00
CONT_ASSIGN54911100.00
CONT_ASSIGN54911100.00
CONT_ASSIGN54911100.00
CONT_ASSIGN54911100.00
CONT_ASSIGN54911100.00
CONT_ASSIGN54911100.00
CONT_ASSIGN54911100.00
CONT_ASSIGN54911100.00
CONT_ASSIGN54911100.00
CONT_ASSIGN54911100.00
CONT_ASSIGN54911100.00
ALWAYS5623266.67
CONT_ASSIGN56811100.00
CONT_ASSIGN56811100.00
CONT_ASSIGN56811100.00
CONT_ASSIGN56811100.00
CONT_ASSIGN56811100.00
CONT_ASSIGN56811100.00
CONT_ASSIGN56811100.00
CONT_ASSIGN56811100.00
CONT_ASSIGN56811100.00
CONT_ASSIGN56811100.00
CONT_ASSIGN56811100.00
CONT_ASSIGN56811100.00
CONT_ASSIGN56811100.00
CONT_ASSIGN56811100.00
CONT_ASSIGN56811100.00
CONT_ASSIGN58211100.00
CONT_ASSIGN58211100.00
CONT_ASSIGN58211100.00
CONT_ASSIGN58211100.00
CONT_ASSIGN58211100.00
CONT_ASSIGN58211100.00
CONT_ASSIGN58211100.00
CONT_ASSIGN58211100.00
CONT_ASSIGN58211100.00
CONT_ASSIGN58211100.00
CONT_ASSIGN58211100.00
CONT_ASSIGN58211100.00
CONT_ASSIGN58211100.00
CONT_ASSIGN58211100.00
CONT_ASSIGN58211100.00
CONT_ASSIGN58211100.00
CONT_ASSIGN58211100.00
CONT_ASSIGN58211100.00
CONT_ASSIGN58211100.00
CONT_ASSIGN58211100.00
CONT_ASSIGN58211100.00
CONT_ASSIGN58211100.00
CONT_ASSIGN58211100.00
CONT_ASSIGN58211100.00
CONT_ASSIGN58211100.00
CONT_ASSIGN58211100.00
CONT_ASSIGN58211100.00
CONT_ASSIGN58211100.00
CONT_ASSIGN58211100.00
CONT_ASSIGN58211100.00
CONT_ASSIGN58211100.00
CONT_ASSIGN58211100.00
CONT_ASSIGN58211100.00
CONT_ASSIGN58211100.00
CONT_ASSIGN58211100.00
CONT_ASSIGN58211100.00
CONT_ASSIGN58211100.00
CONT_ASSIGN58211100.00
CONT_ASSIGN58211100.00
CONT_ASSIGN58211100.00
CONT_ASSIGN58211100.00
CONT_ASSIGN58211100.00
CONT_ASSIGN58211100.00
CONT_ASSIGN58211100.00
CONT_ASSIGN58211100.00
CONT_ASSIGN58211100.00
CONT_ASSIGN58211100.00
CONT_ASSIGN59111100.00
CONT_ASSIGN59611100.00
CONT_ASSIGN60111100.00
CONT_ASSIGN60111100.00
CONT_ASSIGN60111100.00
CONT_ASSIGN60111100.00
CONT_ASSIGN60111100.00
CONT_ASSIGN60111100.00
CONT_ASSIGN60111100.00
CONT_ASSIGN60111100.00
CONT_ASSIGN62211100.00
CONT_ASSIGN622100.00
CONT_ASSIGN62211100.00
CONT_ASSIGN622100.00
CONT_ASSIGN62211100.00
CONT_ASSIGN62211100.00
CONT_ASSIGN622100.00
CONT_ASSIGN622100.00
CONT_ASSIGN62611100.00

Click here to see the source line report.

Cond Coverage for Module : pinmux
TotalCoveredPercent
Conditions1977169785.84
Logical1977169785.84
Non-Logical00
Event00

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.
Line numbersPercent
133-50294.76
50282.68
502-50683.72
506-51182.07
511-53892.76
538-60181.40

Toggle Coverage for Module : pinmux
TotalCoveredPercent
Totals 713 395 55.40
Total Bits 3068 2046 66.69
Total Bits 0->1 1534 1024 66.75
Total Bits 1->0 1534 1022 66.62

Ports 713 395 55.40
Port Bits 3068 2046 66.69
Port Bits 0->1 1534 1024 66.75
Port Bits 1->0 1534 1022 66.62

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T46,T41,T34 Yes T1,T2,T3 INPUT
rst_sys_ni Yes Yes T46,T41,T34 Yes T1,T2,T3 INPUT
scanmode_i[3:0] Unreachable Unreachable Unreachable INPUT
clk_aon_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_aon_ni Yes Yes T46,T41,T34 Yes T1,T2,T3 INPUT
pin_wkup_req_o Yes Yes T6,T29,T77 Yes T6,T25,T29 OUTPUT
usb_wkup_req_o Yes Yes T8,T77,T78 Yes T8,T77,T78 OUTPUT
sleep_en_i Yes Yes T1,T2,T3 Yes T7,T6,T25 INPUT
strap_en_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
strap_en_override_i Unreachable Unreachable Unreachable INPUT
lc_dft_en_i[3:0] Yes Yes T46,T47,T59 Yes T1,T2,T3 INPUT
lc_hw_debug_en_i[3:0] Yes Yes T46,T41,T47 Yes T1,T2,T3 INPUT
lc_check_byp_en_i[3:0] Yes Yes T34,T42,T59 Yes T34,T42,T86 INPUT
lc_escalate_en_i[3:0] Yes Yes T46,T47,T87 Yes T46,T34,T47 INPUT
pinmux_hw_debug_en_o[3:0] Yes Yes T46,T41,T47 Yes T1,T2,T3 OUTPUT
dft_strap_test_o.straps[1:0] No No Yes T38,T88,T89 OUTPUT
dft_strap_test_o.valid Yes Yes T46,T47,T59 Yes T1,T2,T3 OUTPUT
dft_hold_tap_sel_i Unreachable Unreachable Unreachable INPUT
lc_jtag_o.tdi Yes Yes T34,T42,T60 Yes T34,T42,T60 OUTPUT
lc_jtag_o.trst_n Yes Yes T34,T42,T59 Yes T34,T42,T60 OUTPUT
lc_jtag_o.tms Yes Yes T34,T42,T60 Yes T34,T42,T60 OUTPUT
lc_jtag_o.tck Yes Yes T34,T42,T60 Yes T34,T42,T60 OUTPUT
lc_jtag_i.tdo_oe Yes Yes T34,T42,T60 Yes T34,T42,T60 INPUT
lc_jtag_i.tdo Yes Yes T34,T42,T60 Yes T34,T42,T60 INPUT
rv_jtag_o.tdi Yes Yes T38,T90,T91 Yes T38,T90,T91 OUTPUT
rv_jtag_o.trst_n Yes Yes T38,T91,T92 Yes T38,T90,T91 OUTPUT
rv_jtag_o.tms Yes Yes T38,T90,T91 Yes T38,T90,T91 OUTPUT
rv_jtag_o.tck Yes Yes T38,T90,T91 Yes T38,T90,T91 OUTPUT
rv_jtag_i.tdo_oe Yes Yes T38,T90,T91 Yes T38,T90,T91 INPUT
rv_jtag_i.tdo Yes Yes T38,T90,T91 Yes T38,T90,T91 INPUT
dft_jtag_o.tdi Yes Yes T38,T93,T94 Yes T38,T93,T94 OUTPUT
dft_jtag_o.trst_n Yes Yes T38,T93,T94 Yes T38,T93,T94 OUTPUT
dft_jtag_o.tms Yes Yes T38,T93,T94 Yes T38,T93,T94 OUTPUT
dft_jtag_o.tck Yes Yes T38,T93,T94 Yes T38,T93,T94 OUTPUT
dft_jtag_i.tdo_oe Yes Yes T38,T93,T94 Yes T38,T93,T94 INPUT
dft_jtag_i.tdo Yes Yes T38,T93,T94 Yes T38,T93,T94 INPUT
usbdev_dppullup_en_i Yes Yes T4,T8,T9 Yes T4,T8,T9 INPUT
usbdev_dnpullup_en_i Yes Yes T4,T8,T95 Yes T4,T8,T95 INPUT
usb_dppullup_en_o Yes Yes T4,T8,T9 Yes T4,T8,T9 OUTPUT
usb_dnpullup_en_o Yes Yes T4,T8,T95 Yes T4,T8,T95 OUTPUT
usbdev_suspend_req_i Yes Yes T8,T77,T78 Yes T8,T77,T78 INPUT
usbdev_wake_ack_i Yes Yes T8,T77,T96 Yes T8,T77,T96 INPUT
usbdev_bus_not_idle_o Yes Yes T77,T78,T79 Yes T77,T78,T79 OUTPUT
usbdev_bus_reset_o Yes Yes T8 Yes T8 OUTPUT
usbdev_sense_lost_o Yes Yes T77,T78,T79 Yes T77,T78,T79 OUTPUT
usbdev_wake_detect_active_o Yes Yes T8,T77,T78 Yes T8,T77,T78 OUTPUT
tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[11:0] Yes Yes *T97,*T98,*T99 Yes T97,T98,T99 INPUT
tl_i.a_address[16:12] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[18:17] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[21:19] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[22] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[29:23] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T100,*T40,*T96 Yes T100,T40,T96 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T97,T98,T99 Yes T97,T98,T99 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T40,T96,T101 Yes T40,T96,T101 INPUT
tl_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_error Yes Yes T97,T102,T103 Yes T97,T98,T102 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_sink Yes Yes T102,T104,T105 Yes T98,T104,T105 OUTPUT
tl_o.d_source[5:0] Yes Yes *T74,*T69,*T103 Yes T74,T69,T97 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T97,T104,T105 Yes T97,T98,T105 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T80,T106,T107 Yes T80,T106,T107 INPUT
alert_rx_i[0].ping_n Yes Yes T106,T107,T108 Yes T106,T107,T108 INPUT
alert_rx_i[0].ping_p Yes Yes T106,T107,T108 Yes T106,T107,T108 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T80,T106,T107 Yes T80,T106,T107 OUTPUT
periph_to_mio_i[74:0] Yes Yes T31,T96,T12 Yes T29,T31,T96 INPUT
periph_to_mio_oe_i[74:0] Yes Yes T31,T44,T45 Yes T6,T29,T31 INPUT
mio_to_periph_o[56:0] Yes Yes T6,T31,T43 Yes T6,T31,T43 OUTPUT
periph_to_dio_i[11:0] Yes Yes *T4,*T8,*T9 Yes T9,T18,T19 INPUT
periph_to_dio_i[13:12] No No No INPUT
periph_to_dio_i[15:14] Yes Yes T10,T11,T12 Yes T10,T11,T12 INPUT
periph_to_dio_oe_i[15:0] Yes Yes T9,T18,T19 Yes T9,T18,T19 INPUT
dio_to_periph_o[15:0] Yes Yes T4,T7,T35 Yes T4,T7,T8 OUTPUT
mio_attr_o[0].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[0].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[0].pull_en Yes Yes T22,T23,T24 Yes T28,T50,T51 OUTPUT
mio_attr_o[0].pull_select Yes Yes T22,T23,T24 Yes T28,T50,T51 OUTPUT
mio_attr_o[0].keep_en No No No OUTPUT
mio_attr_o[0].schmitt_en No No No OUTPUT
mio_attr_o[0].od_en No No No OUTPUT
mio_attr_o[0].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[0].slew_rate[1:0] No No No OUTPUT
mio_attr_o[0].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T28,T50,T51 OUTPUT
mio_attr_o[0].drive_strength[3:1] No No No OUTPUT
mio_attr_o[1].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[1].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[1].pull_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[1].pull_select Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[1].keep_en No No No OUTPUT
mio_attr_o[1].schmitt_en No No No OUTPUT
mio_attr_o[1].od_en No No No OUTPUT
mio_attr_o[1].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[1].slew_rate[1:0] No No No OUTPUT
mio_attr_o[1].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[1].drive_strength[3:1] No No No OUTPUT
mio_attr_o[2].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[2].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[2].pull_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[2].pull_select Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[2].keep_en No No No OUTPUT
mio_attr_o[2].schmitt_en No No No OUTPUT
mio_attr_o[2].od_en No No No OUTPUT
mio_attr_o[2].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[2].slew_rate[1:0] No No No OUTPUT
mio_attr_o[2].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[2].drive_strength[3:1] No No No OUTPUT
mio_attr_o[3].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[3].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[3].pull_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[3].pull_select Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[3].keep_en No No No OUTPUT
mio_attr_o[3].schmitt_en No No No OUTPUT
mio_attr_o[3].od_en No No No OUTPUT
mio_attr_o[3].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[3].slew_rate[1:0] No No No OUTPUT
mio_attr_o[3].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[3].drive_strength[3:1] No No No OUTPUT
mio_attr_o[4].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[4].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[4].pull_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[4].pull_select Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[4].keep_en No No No OUTPUT
mio_attr_o[4].schmitt_en No No No OUTPUT
mio_attr_o[4].od_en No No No OUTPUT
mio_attr_o[4].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[4].slew_rate[1:0] No No No OUTPUT
mio_attr_o[4].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[4].drive_strength[3:1] No No No OUTPUT
mio_attr_o[5].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[5].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[5].pull_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[5].pull_select Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[5].keep_en No No No OUTPUT
mio_attr_o[5].schmitt_en No No No OUTPUT
mio_attr_o[5].od_en No No No OUTPUT
mio_attr_o[5].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[5].slew_rate[1:0] No No No OUTPUT
mio_attr_o[5].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[5].drive_strength[3:1] No No No OUTPUT
mio_attr_o[6].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[6].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[6].pull_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[6].pull_select Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[6].keep_en No No No OUTPUT
mio_attr_o[6].schmitt_en No No No OUTPUT
mio_attr_o[6].od_en No No No OUTPUT
mio_attr_o[6].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[6].slew_rate[1:0] No No No OUTPUT
mio_attr_o[6].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[6].drive_strength[3:1] No No No OUTPUT
mio_attr_o[7].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[7].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[7].pull_en Yes Yes T22,T23,T24 Yes T13,T52,T53 OUTPUT
mio_attr_o[7].pull_select Yes Yes T22,T23,T24 Yes T13,T52,T53 OUTPUT
mio_attr_o[7].keep_en No No No OUTPUT
mio_attr_o[7].schmitt_en No No No OUTPUT
mio_attr_o[7].od_en No No No OUTPUT
mio_attr_o[7].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[7].slew_rate[1:0] No No No OUTPUT
mio_attr_o[7].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[7].drive_strength[3:1] No No No OUTPUT
mio_attr_o[8].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[8].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[8].pull_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[8].pull_select Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[8].keep_en No No No OUTPUT
mio_attr_o[8].schmitt_en No No No OUTPUT
mio_attr_o[8].od_en No No No OUTPUT
mio_attr_o[8].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[8].slew_rate[1:0] No No No OUTPUT
mio_attr_o[8].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[8].drive_strength[3:1] No No No OUTPUT
mio_attr_o[9].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[9].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[9].pull_en Yes Yes T22,T23,T24 Yes T28,T50,T51 OUTPUT
mio_attr_o[9].pull_select Yes Yes T22,T23,T24 Yes T28,T50,T51 OUTPUT
mio_attr_o[9].keep_en No No No OUTPUT
mio_attr_o[9].schmitt_en No No No OUTPUT
mio_attr_o[9].od_en No No No OUTPUT
mio_attr_o[9].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[9].slew_rate[1:0] No No No OUTPUT
mio_attr_o[9].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T28,T50,T51 OUTPUT
mio_attr_o[9].drive_strength[3:1] No No No OUTPUT
mio_attr_o[10].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[10].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[10].pull_en Yes Yes T22,T23,T24 Yes T28,T10,T11 OUTPUT
mio_attr_o[10].pull_select Yes Yes T22,T23,T24 Yes T28,T10,T11 OUTPUT
mio_attr_o[10].keep_en No No No OUTPUT
mio_attr_o[10].schmitt_en No No No OUTPUT
mio_attr_o[10].od_en No No No OUTPUT
mio_attr_o[10].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[10].slew_rate[1:0] No No No OUTPUT
mio_attr_o[10].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T28,T50,T51 OUTPUT
mio_attr_o[10].drive_strength[3:1] No No No OUTPUT
mio_attr_o[11].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[11].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[11].pull_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[11].pull_select Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[11].keep_en No No No OUTPUT
mio_attr_o[11].schmitt_en No No No OUTPUT
mio_attr_o[11].od_en No No No OUTPUT
mio_attr_o[11].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[11].slew_rate[1:0] No No No OUTPUT
mio_attr_o[11].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[11].drive_strength[3:1] No No No OUTPUT
mio_attr_o[12].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[12].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[12].pull_en Yes Yes T22,T23,T24 Yes T28,T10,T11 OUTPUT
mio_attr_o[12].pull_select Yes Yes T22,T23,T24 Yes T28,T10,T11 OUTPUT
mio_attr_o[12].keep_en No No No OUTPUT
mio_attr_o[12].schmitt_en No No No OUTPUT
mio_attr_o[12].od_en No No No OUTPUT
mio_attr_o[12].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[12].slew_rate[1:0] No No No OUTPUT
mio_attr_o[12].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T28,T50,T51 OUTPUT
mio_attr_o[12].drive_strength[3:1] No No No OUTPUT
mio_attr_o[13].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[13].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[13].pull_en Yes Yes T22,T23,T24 Yes T28,T12,T50 OUTPUT
mio_attr_o[13].pull_select Yes Yes T22,T23,T24 Yes T28,T12,T50 OUTPUT
mio_attr_o[13].keep_en No No No OUTPUT
mio_attr_o[13].schmitt_en No No No OUTPUT
mio_attr_o[13].od_en No No No OUTPUT
mio_attr_o[13].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[13].slew_rate[1:0] No No No OUTPUT
mio_attr_o[13].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T28,T50,T51 OUTPUT
mio_attr_o[13].drive_strength[3:1] No No No OUTPUT
mio_attr_o[14].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[14].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[14].pull_en Yes Yes T22,T23,T24 Yes T28,T12,T50 OUTPUT
mio_attr_o[14].pull_select Yes Yes T22,T23,T24 Yes T28,T12,T50 OUTPUT
mio_attr_o[14].keep_en No No No OUTPUT
mio_attr_o[14].schmitt_en No No No OUTPUT
mio_attr_o[14].od_en No No No OUTPUT
mio_attr_o[14].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[14].slew_rate[1:0] No No No OUTPUT
mio_attr_o[14].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T28,T50,T51 OUTPUT
mio_attr_o[14].drive_strength[3:1] No No No OUTPUT
mio_attr_o[15].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[15].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[15].pull_en Yes Yes T22,T23,T24 Yes T28,T12,T50 OUTPUT
mio_attr_o[15].pull_select Yes Yes T22,T23,T24 Yes T28,T12,T50 OUTPUT
mio_attr_o[15].keep_en No No No OUTPUT
mio_attr_o[15].schmitt_en No No No OUTPUT
mio_attr_o[15].od_en No No No OUTPUT
mio_attr_o[15].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[15].slew_rate[1:0] No No No OUTPUT
mio_attr_o[15].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T28,T50,T51 OUTPUT
mio_attr_o[15].drive_strength[3:1] No No No OUTPUT
mio_attr_o[16].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[16].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[16].pull_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[16].pull_select Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[16].keep_en No No No OUTPUT
mio_attr_o[16].schmitt_en No No No OUTPUT
mio_attr_o[16].od_en No No No OUTPUT
mio_attr_o[16].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[16].slew_rate[1:0] No No No OUTPUT
mio_attr_o[16].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[16].drive_strength[3:1] No No No OUTPUT
mio_attr_o[17].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[17].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[17].pull_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[17].pull_select Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[17].keep_en No No No OUTPUT
mio_attr_o[17].schmitt_en No No No OUTPUT
mio_attr_o[17].od_en No No No OUTPUT
mio_attr_o[17].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[17].slew_rate[1:0] No No No OUTPUT
mio_attr_o[17].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[17].drive_strength[3:1] No No No OUTPUT
mio_attr_o[18].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[18].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[18].pull_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[18].pull_select Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[18].keep_en No No No OUTPUT
mio_attr_o[18].schmitt_en No No No OUTPUT
mio_attr_o[18].od_en No No No OUTPUT
mio_attr_o[18].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[18].slew_rate[1:0] No No No OUTPUT
mio_attr_o[18].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[18].drive_strength[3:1] No No No OUTPUT
mio_attr_o[19].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[19].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[19].pull_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[19].pull_select Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[19].keep_en No No No OUTPUT
mio_attr_o[19].schmitt_en No No No OUTPUT
mio_attr_o[19].od_en No No No OUTPUT
mio_attr_o[19].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[19].slew_rate[1:0] No No No OUTPUT
mio_attr_o[19].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[19].drive_strength[3:1] No No No OUTPUT
mio_attr_o[20].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[20].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[20].pull_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[20].pull_select Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[20].keep_en No No No OUTPUT
mio_attr_o[20].schmitt_en No No No OUTPUT
mio_attr_o[20].od_en No No No OUTPUT
mio_attr_o[20].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[20].slew_rate[1:0] No No No OUTPUT
mio_attr_o[20].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[20].drive_strength[3:1] No No No OUTPUT
mio_attr_o[21].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[21].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[21].pull_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[21].pull_select Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[21].keep_en No No No OUTPUT
mio_attr_o[21].schmitt_en No No No OUTPUT
mio_attr_o[21].od_en No No No OUTPUT
mio_attr_o[21].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[21].slew_rate[1:0] No No No OUTPUT
mio_attr_o[21].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[21].drive_strength[3:1] No No No OUTPUT
mio_attr_o[22].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[22].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[22].pull_en Yes Yes T54,T55,T56 Yes T57,T58,T54 OUTPUT
mio_attr_o[22].pull_select Yes Yes T57,T58,T54 Yes T57,T58,T54 OUTPUT
mio_attr_o[22].keep_en No No No OUTPUT
mio_attr_o[22].schmitt_en No No No OUTPUT
mio_attr_o[22].od_en No No No OUTPUT
mio_attr_o[22].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[22].slew_rate[1:0] No No No OUTPUT
mio_attr_o[22].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[22].drive_strength[3:1] No No No OUTPUT
mio_attr_o[23].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[23].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[23].pull_en Yes Yes T54,T55,T56 Yes T57,T58,T54 OUTPUT
mio_attr_o[23].pull_select Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[23].keep_en No No No OUTPUT
mio_attr_o[23].schmitt_en No No No OUTPUT
mio_attr_o[23].od_en No No No OUTPUT
mio_attr_o[23].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[23].slew_rate[1:0] No No No OUTPUT
mio_attr_o[23].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[23].drive_strength[3:1] No No No OUTPUT
mio_attr_o[24].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[24].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[24].pull_en Yes Yes T54,T55,T56 Yes T57,T58,T54 OUTPUT
mio_attr_o[24].pull_select Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[24].keep_en No No No OUTPUT
mio_attr_o[24].schmitt_en No No No OUTPUT
mio_attr_o[24].od_en No No No OUTPUT
mio_attr_o[24].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[24].slew_rate[1:0] No No No OUTPUT
mio_attr_o[24].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[24].drive_strength[3:1] No No No OUTPUT
mio_attr_o[25].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[25].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[25].pull_en Yes Yes T7,T46,T25 Yes T1,T2,T3 OUTPUT
mio_attr_o[25].pull_select Yes Yes T7,T46,T25 Yes T1,T2,T3 OUTPUT
mio_attr_o[25].keep_en No No No OUTPUT
mio_attr_o[25].schmitt_en No No No OUTPUT
mio_attr_o[25].od_en No No No OUTPUT
mio_attr_o[25].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[25].slew_rate[1:0] No No No OUTPUT
mio_attr_o[25].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[25].drive_strength[3:1] No No No OUTPUT
mio_attr_o[26].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[26].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[26].pull_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[26].pull_select Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[26].keep_en No No No OUTPUT
mio_attr_o[26].schmitt_en No No No OUTPUT
mio_attr_o[26].od_en No No No OUTPUT
mio_attr_o[26].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[26].slew_rate[1:0] No No No OUTPUT
mio_attr_o[26].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[26].drive_strength[3:1] No No No OUTPUT
mio_attr_o[27].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[27].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[27].pull_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[27].pull_select Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[27].keep_en No No No OUTPUT
mio_attr_o[27].schmitt_en No No No OUTPUT
mio_attr_o[27].od_en No No No OUTPUT
mio_attr_o[27].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[27].slew_rate[1:0] No No No OUTPUT
mio_attr_o[27].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[27].drive_strength[3:1] No No No OUTPUT
mio_attr_o[28].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[28].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[28].pull_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[28].pull_select Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[28].keep_en No No No OUTPUT
mio_attr_o[28].schmitt_en No No No OUTPUT
mio_attr_o[28].od_en No No No OUTPUT
mio_attr_o[28].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[28].slew_rate[1:0] No No No OUTPUT
mio_attr_o[28].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[28].drive_strength[3:1] No No No OUTPUT
mio_attr_o[29].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[29].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[29].pull_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[29].pull_select Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[29].keep_en No No No OUTPUT
mio_attr_o[29].schmitt_en No No No OUTPUT
mio_attr_o[29].od_en No No No OUTPUT
mio_attr_o[29].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[29].slew_rate[1:0] No No No OUTPUT
mio_attr_o[29].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[29].drive_strength[3:1] No No No OUTPUT
mio_attr_o[30].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[30].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[30].pull_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[30].pull_select Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[30].keep_en No No No OUTPUT
mio_attr_o[30].schmitt_en No No No OUTPUT
mio_attr_o[30].od_en No No No OUTPUT
mio_attr_o[30].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[30].slew_rate[1:0] No No No OUTPUT
mio_attr_o[30].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[30].drive_strength[3:1] No No No OUTPUT
mio_attr_o[31].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[31].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[31].pull_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[31].pull_select Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[31].keep_en No No No OUTPUT
mio_attr_o[31].schmitt_en No No No OUTPUT
mio_attr_o[31].od_en No No No OUTPUT
mio_attr_o[31].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[31].slew_rate[1:0] No No No OUTPUT
mio_attr_o[31].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[31].drive_strength[3:1] No No No OUTPUT
mio_attr_o[32].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[32].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[32].pull_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[32].pull_select Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[32].keep_en No No No OUTPUT
mio_attr_o[32].schmitt_en No No No OUTPUT
mio_attr_o[32].od_en No No No OUTPUT
mio_attr_o[32].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[32].slew_rate[1:0] No No No OUTPUT
mio_attr_o[32].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[32].drive_strength[3:1] No No No OUTPUT
mio_attr_o[33].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[33].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[33].pull_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[33].pull_select Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[33].keep_en No No No OUTPUT
mio_attr_o[33].schmitt_en No No No OUTPUT
mio_attr_o[33].od_en No No No OUTPUT
mio_attr_o[33].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[33].slew_rate[1:0] No No No OUTPUT
mio_attr_o[33].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[33].drive_strength[3:1] No No No OUTPUT
mio_attr_o[34].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[34].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[34].pull_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[34].pull_select Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[34].keep_en No No No OUTPUT
mio_attr_o[34].schmitt_en No No No OUTPUT
mio_attr_o[34].od_en No No No OUTPUT
mio_attr_o[34].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[34].slew_rate[1:0] No No No OUTPUT
mio_attr_o[34].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[34].drive_strength[3:1] No No No OUTPUT
mio_attr_o[35].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[35].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[35].pull_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[35].pull_select Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[35].keep_en No No No OUTPUT
mio_attr_o[35].schmitt_en No No No OUTPUT
mio_attr_o[35].od_en No No No OUTPUT
mio_attr_o[35].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[35].slew_rate[1:0] No No No OUTPUT
mio_attr_o[35].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[35].drive_strength[3:1] No No No OUTPUT
mio_attr_o[36].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[36].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[36].pull_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[36].pull_select Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[36].keep_en No No No OUTPUT
mio_attr_o[36].schmitt_en No No No OUTPUT
mio_attr_o[36].od_en No No No OUTPUT
mio_attr_o[36].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[36].slew_rate[1:0] No No No OUTPUT
mio_attr_o[36].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[36].drive_strength[3:1] No No No OUTPUT
mio_attr_o[37].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[37].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[37].pull_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[37].pull_select Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[37].keep_en No No No OUTPUT
mio_attr_o[37].schmitt_en No No No OUTPUT
mio_attr_o[37].od_en No No No OUTPUT
mio_attr_o[37].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[37].slew_rate[1:0] No No No OUTPUT
mio_attr_o[37].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[37].drive_strength[3:1] No No No OUTPUT
mio_attr_o[38].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[38].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[38].pull_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[38].pull_select Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[38].keep_en No No No OUTPUT
mio_attr_o[38].schmitt_en Yes Yes T34,T42,T59 Yes T34,T42,T60 OUTPUT
mio_attr_o[38].od_en No No No OUTPUT
mio_attr_o[38].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[38].slew_rate[1:0] No No No OUTPUT
mio_attr_o[38].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[38].drive_strength[3:1] No No No OUTPUT
mio_attr_o[39].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[39].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[39].pull_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[39].pull_select Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[39].keep_en No No No OUTPUT
mio_attr_o[39].schmitt_en Yes Yes T34,T42,T59 Yes T34,T42,T60 OUTPUT
mio_attr_o[39].od_en No No No OUTPUT
mio_attr_o[39].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[39].slew_rate[1:0] No No No OUTPUT
mio_attr_o[39].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[39].drive_strength[3:1] No No No OUTPUT
mio_attr_o[40].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[40].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[40].pull_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[40].pull_select Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[40].keep_en No No No OUTPUT
mio_attr_o[40].schmitt_en No No No OUTPUT
mio_attr_o[40].od_en No No No OUTPUT
mio_attr_o[40].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[40].slew_rate[1:0] No No No OUTPUT
mio_attr_o[40].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[40].drive_strength[3:1] No No No OUTPUT
mio_attr_o[41].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[41].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[41].pull_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[41].pull_select Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[41].keep_en No No No OUTPUT
mio_attr_o[41].schmitt_en No No No OUTPUT
mio_attr_o[41].od_en No No No OUTPUT
mio_attr_o[41].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[41].slew_rate[1:0] No No No OUTPUT
mio_attr_o[41].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[41].drive_strength[3:1] No No No OUTPUT
mio_attr_o[42].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[42].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[42].pull_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[42].pull_select Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[42].keep_en No No No OUTPUT
mio_attr_o[42].schmitt_en No No No OUTPUT
mio_attr_o[42].od_en No No No OUTPUT
mio_attr_o[42].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[42].slew_rate[1:0] No No No OUTPUT
mio_attr_o[42].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[42].drive_strength[3:1] No No No OUTPUT
mio_attr_o[43].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[43].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[43].pull_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[43].pull_select Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[43].keep_en No No No OUTPUT
mio_attr_o[43].schmitt_en No No No OUTPUT
mio_attr_o[43].od_en No No No OUTPUT
mio_attr_o[43].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[43].slew_rate[1:0] No No No OUTPUT
mio_attr_o[43].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[43].drive_strength[3:1] No No No OUTPUT
mio_attr_o[44].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[44].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[44].pull_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[44].pull_select Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[44].keep_en No No No OUTPUT
mio_attr_o[44].schmitt_en No No No OUTPUT
mio_attr_o[44].od_en No No No OUTPUT
mio_attr_o[44].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[44].slew_rate[1:0] No No No OUTPUT
mio_attr_o[44].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[44].drive_strength[3:1] No No No OUTPUT
mio_attr_o[45].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[45].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[45].pull_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[45].pull_select Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[45].keep_en No No No OUTPUT
mio_attr_o[45].schmitt_en No No No OUTPUT
mio_attr_o[45].od_en No No No OUTPUT
mio_attr_o[45].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[45].slew_rate[1:0] No No No OUTPUT
mio_attr_o[45].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[45].drive_strength[3:1] No No No OUTPUT
mio_attr_o[46].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[46].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[46].pull_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[46].pull_select Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[46].keep_en No No No OUTPUT
mio_attr_o[46].schmitt_en No No No OUTPUT
mio_attr_o[46].od_en No No No OUTPUT
mio_attr_o[46].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[46].slew_rate[1:0] No No No OUTPUT
mio_attr_o[46].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T22,T23,T24 OUTPUT
mio_attr_o[46].drive_strength[3:1] No No No OUTPUT
mio_out_o[46:0] Yes Yes T29,T31,T43 Yes T29,T31,T43 OUTPUT
mio_oe_o[46:0] Yes Yes T31,T44,T45 Yes T29,T31,T43 OUTPUT
mio_in_i[46:0] Yes Yes T29,T30,T31 Yes T7,T29,T30 INPUT
dio_attr_o[0].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[0].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[0].pull_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[0].pull_select Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[0].keep_en No No No OUTPUT
dio_attr_o[0].schmitt_en No No No OUTPUT
dio_attr_o[0].od_en No No No OUTPUT
dio_attr_o[0].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[0].slew_rate[1:0] No No No OUTPUT
dio_attr_o[0].drive_strength[0] Yes Yes *T46,*T41,*T47 Yes T1,T2,T3 OUTPUT
dio_attr_o[0].drive_strength[3:1] No No No OUTPUT
dio_attr_o[1].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[1].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[1].pull_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[1].pull_select Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[1].keep_en No No No OUTPUT
dio_attr_o[1].schmitt_en No No No OUTPUT
dio_attr_o[1].od_en No No No OUTPUT
dio_attr_o[1].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[1].slew_rate[1:0] No No No OUTPUT
dio_attr_o[1].drive_strength[0] Yes Yes *T46,*T41,*T47 Yes T1,T2,T3 OUTPUT
dio_attr_o[1].drive_strength[3:1] No No No OUTPUT
dio_attr_o[2].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[2].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[2].pull_en Yes Yes T22,T23,T24 Yes T28,T10,T11 OUTPUT
dio_attr_o[2].pull_select Yes Yes T22,T23,T24 Yes T28,T10,T11 OUTPUT
dio_attr_o[2].keep_en No No No OUTPUT
dio_attr_o[2].schmitt_en No No No OUTPUT
dio_attr_o[2].od_en No No No OUTPUT
dio_attr_o[2].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[2].slew_rate[1:0] No No No OUTPUT
dio_attr_o[2].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T28,T10,T11 OUTPUT
dio_attr_o[2].drive_strength[3:1] No No No OUTPUT
dio_attr_o[3].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[3].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[3].pull_en Yes Yes T22,T23,T24 Yes T28,T10,T11 OUTPUT
dio_attr_o[3].pull_select Yes Yes T22,T23,T24 Yes T28,T10,T11 OUTPUT
dio_attr_o[3].keep_en No No No OUTPUT
dio_attr_o[3].schmitt_en No No No OUTPUT
dio_attr_o[3].od_en No No No OUTPUT
dio_attr_o[3].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[3].slew_rate[1:0] No No No OUTPUT
dio_attr_o[3].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T28,T10,T11 OUTPUT
dio_attr_o[3].drive_strength[3:1] No No No OUTPUT
dio_attr_o[4].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[4].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[4].pull_en Yes Yes T22,T23,T24 Yes T28,T10,T11 OUTPUT
dio_attr_o[4].pull_select Yes Yes T22,T23,T24 Yes T28,T10,T11 OUTPUT
dio_attr_o[4].keep_en No No No OUTPUT
dio_attr_o[4].schmitt_en No No No OUTPUT
dio_attr_o[4].od_en No No No OUTPUT
dio_attr_o[4].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[4].slew_rate[1:0] No No No OUTPUT
dio_attr_o[4].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T28,T10,T11 OUTPUT
dio_attr_o[4].drive_strength[3:1] No No No OUTPUT
dio_attr_o[5].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[5].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[5].pull_en Yes Yes T22,T23,T24 Yes T28,T10,T11 OUTPUT
dio_attr_o[5].pull_select Yes Yes T22,T23,T24 Yes T28,T10,T11 OUTPUT
dio_attr_o[5].keep_en No No No OUTPUT
dio_attr_o[5].schmitt_en No No No OUTPUT
dio_attr_o[5].od_en No No No OUTPUT
dio_attr_o[5].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[5].slew_rate[1:0] No No No OUTPUT
dio_attr_o[5].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T28,T10,T11 OUTPUT
dio_attr_o[5].drive_strength[3:1] No No No OUTPUT
dio_attr_o[6].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[6].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[6].pull_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[6].pull_select Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[6].keep_en No No No OUTPUT
dio_attr_o[6].schmitt_en No No No OUTPUT
dio_attr_o[6].od_en No No No OUTPUT
dio_attr_o[6].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[6].slew_rate[1:0] No No No OUTPUT
dio_attr_o[6].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T10,T11,T12 OUTPUT
dio_attr_o[6].drive_strength[3:1] No No No OUTPUT
dio_attr_o[7].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[7].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[7].pull_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[7].pull_select Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[7].keep_en No No No OUTPUT
dio_attr_o[7].schmitt_en No No No OUTPUT
dio_attr_o[7].od_en No No No OUTPUT
dio_attr_o[7].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[7].slew_rate[1:0] No No No OUTPUT
dio_attr_o[7].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T10,T11,T12 OUTPUT
dio_attr_o[7].drive_strength[3:1] No No No OUTPUT
dio_attr_o[8].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[8].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[8].pull_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[8].pull_select Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[8].keep_en No No No OUTPUT
dio_attr_o[8].schmitt_en No No No OUTPUT
dio_attr_o[8].od_en No No No OUTPUT
dio_attr_o[8].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[8].slew_rate[1:0] No No No OUTPUT
dio_attr_o[8].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T10,T11,T12 OUTPUT
dio_attr_o[8].drive_strength[3:1] No No No OUTPUT
dio_attr_o[9].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[9].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[9].pull_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[9].pull_select Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[9].keep_en No No No OUTPUT
dio_attr_o[9].schmitt_en No No No OUTPUT
dio_attr_o[9].od_en No No No OUTPUT
dio_attr_o[9].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[9].slew_rate[1:0] No No No OUTPUT
dio_attr_o[9].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T10,T11,T12 OUTPUT
dio_attr_o[9].drive_strength[3:1] No No No OUTPUT
dio_attr_o[10].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[10].virt_od_en Yes Yes T22,T23,T24 Yes T17,T48,T49 OUTPUT
dio_attr_o[10].pull_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[10].pull_select Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[10].keep_en No No No OUTPUT
dio_attr_o[10].schmitt_en No No No OUTPUT
dio_attr_o[10].od_en No No No OUTPUT
dio_attr_o[10].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[10].slew_rate[1:0] No No No OUTPUT
dio_attr_o[10].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[10].drive_strength[3:1] No No No OUTPUT
dio_attr_o[11].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[11].virt_od_en Yes Yes T22,T23,T24 Yes T17,T48,T49 OUTPUT
dio_attr_o[11].pull_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[11].pull_select Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[11].keep_en No No No OUTPUT
dio_attr_o[11].schmitt_en No No No OUTPUT
dio_attr_o[11].od_en No No No OUTPUT
dio_attr_o[11].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[11].slew_rate[1:0] No No No OUTPUT
dio_attr_o[11].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[11].drive_strength[3:1] No No No OUTPUT
dio_attr_o[12].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[12].virt_od_en No No No OUTPUT
dio_attr_o[12].pull_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[12].pull_select Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[12].keep_en No No No OUTPUT
dio_attr_o[12].schmitt_en No No No OUTPUT
dio_attr_o[12].od_en No No No OUTPUT
dio_attr_o[12].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[12].slew_rate[1:0] No No No OUTPUT
dio_attr_o[12].drive_strength[3:0] No No No OUTPUT
dio_attr_o[13].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[13].virt_od_en No No No OUTPUT
dio_attr_o[13].pull_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[13].pull_select Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[13].keep_en No No No OUTPUT
dio_attr_o[13].schmitt_en No No No OUTPUT
dio_attr_o[13].od_en No No No OUTPUT
dio_attr_o[13].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[13].slew_rate[1:0] No No No OUTPUT
dio_attr_o[13].drive_strength[3:0] No No No OUTPUT
dio_attr_o[14].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[14].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[14].pull_en Yes Yes T22,T23,T24 Yes T28,T10,T11 OUTPUT
dio_attr_o[14].pull_select Yes Yes T22,T23,T24 Yes T28,T10,T11 OUTPUT
dio_attr_o[14].keep_en No No No OUTPUT
dio_attr_o[14].schmitt_en No No No OUTPUT
dio_attr_o[14].od_en No No No OUTPUT
dio_attr_o[14].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[14].slew_rate[1:0] No No No OUTPUT
dio_attr_o[14].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T28,T10,T11 OUTPUT
dio_attr_o[14].drive_strength[3:1] No No No OUTPUT
dio_attr_o[15].invert Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[15].virt_od_en Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[15].pull_en Yes Yes T22,T23,T24 Yes T28,T10,T11 OUTPUT
dio_attr_o[15].pull_select Yes Yes T22,T23,T24 Yes T28,T10,T11 OUTPUT
dio_attr_o[15].keep_en No No No OUTPUT
dio_attr_o[15].schmitt_en No No No OUTPUT
dio_attr_o[15].od_en No No No OUTPUT
dio_attr_o[15].input_disable Yes Yes T22,T23,T24 Yes T22,T23,T24 OUTPUT
dio_attr_o[15].slew_rate[1:0] No No No OUTPUT
dio_attr_o[15].drive_strength[0] Yes Yes *T22,*T23,*T24 Yes T28,T10,T11 OUTPUT
dio_attr_o[15].drive_strength[3:1] No No No OUTPUT
dio_out_o[11:0] Yes Yes *T4,*T7,*T8 Yes T9,T18,T19 OUTPUT
dio_out_o[13:12] No No No OUTPUT
dio_out_o[15:14] Yes Yes T10,T11,T12 Yes T7,T10,T11 OUTPUT
dio_oe_o[15:0] Yes Yes T9,T18,T19 Yes T9,T18,T19 OUTPUT
dio_in_i[15:0] Yes Yes T4,T7,T35 Yes T4,T7,T8 INPUT

*Tests covering at least one bit in the range

Branch Coverage for Module : pinmux
Line No.TotalCoveredPercent
Branches 778 636 81.75
TERNARY 489 2 2 100.00
TERNARY 493 2 2 100.00
TERNARY 502 4 3 75.00
TERNARY 506 4 3 75.00
TERNARY 489 2 2 100.00
TERNARY 493 2 2 100.00
TERNARY 502 4 3 75.00
TERNARY 506 4 3 75.00
TERNARY 489 2 2 100.00
TERNARY 493 2 2 100.00
TERNARY 502 4 3 75.00
TERNARY 506 4 3 75.00
TERNARY 489 2 2 100.00
TERNARY 493 2 2 100.00
TERNARY 502 4 3 75.00
TERNARY 506 4 3 75.00
TERNARY 489 2 2 100.00
TERNARY 493 2 2 100.00
TERNARY 502 4 3 75.00
TERNARY 506 4 3 75.00
TERNARY 489 2 2 100.00
TERNARY 493 2 2 100.00
TERNARY 502 4 3 75.00
TERNARY 506 4 3 75.00
TERNARY 489 2 2 100.00
TERNARY 493 2 2 100.00
TERNARY 502 4 3 75.00
TERNARY 506 4 3 75.00
TERNARY 489 2 2 100.00
TERNARY 493 2 2 100.00
TERNARY 502 4 4 100.00
TERNARY 506 4 4 100.00
TERNARY 489 2 2 100.00
TERNARY 493 2 2 100.00
TERNARY 502 4 4 100.00
TERNARY 506 4 4 100.00
TERNARY 489 2 2 100.00
TERNARY 493 2 2 100.00
TERNARY 502 4 3 75.00
TERNARY 506 4 3 75.00
TERNARY 489 2 2 100.00
TERNARY 493 2 2 100.00
TERNARY 502 4 3 75.00
TERNARY 506 4 3 75.00
TERNARY 489 2 2 100.00
TERNARY 493 2 2 100.00
TERNARY 502 4 3 75.00
TERNARY 506 4 3 75.00
TERNARY 489 2 2 100.00
TERNARY 493 2 2 100.00
TERNARY 502 4 3 75.00
TERNARY 506 4 3 75.00
TERNARY 489 2 2 100.00
TERNARY 493 2 2 100.00
TERNARY 502 4 3 75.00
TERNARY 506 4 3 75.00
TERNARY 489 2 2 100.00
TERNARY 493 2 2 100.00
TERNARY 502 4 3 75.00
TERNARY 506 4 3 75.00
TERNARY 489 2 2 100.00
TERNARY 493 2 2 100.00
TERNARY 502 4 2 50.00
TERNARY 506 4 2 50.00
TERNARY 489 2 2 100.00
TERNARY 493 2 2 100.00
TERNARY 502 4 3 75.00
TERNARY 506 4 3 75.00
TERNARY 489 2 2 100.00
TERNARY 493 2 2 100.00
TERNARY 502 4 3 75.00
TERNARY 506 4 3 75.00
TERNARY 489 2 2 100.00
TERNARY 493 2 2 100.00
TERNARY 502 4 4 100.00
TERNARY 506 4 4 100.00
TERNARY 489 2 2 100.00
TERNARY 493 2 2 100.00
TERNARY 502 4 3 75.00
TERNARY 506 4 3 75.00
TERNARY 489 2 2 100.00
TERNARY 493 2 2 100.00
TERNARY 502 4 3 75.00
TERNARY 506 4 3 75.00
TERNARY 489 2 2 100.00
TERNARY 493 2 2 100.00
TERNARY 502 4 4 100.00
TERNARY 506 4 4 100.00
TERNARY 489 2 2 100.00
TERNARY 493 2 2 100.00
TERNARY 502 4 3 75.00
TERNARY 506 4 3 75.00
TERNARY 489 2 2 100.00
TERNARY 493 2 2 100.00
TERNARY 502 4 2 50.00
TERNARY 506 4 2 50.00
TERNARY 489 2 2 100.00
TERNARY 493 2 2 100.00
TERNARY 502 4 2 50.00
TERNARY 506 4 2 50.00
TERNARY 489 2 2 100.00
TERNARY 493 2 2 100.00
TERNARY 502 4 3 75.00
TERNARY 506 4 3 75.00
TERNARY 489 2 2 100.00
TERNARY 493 2 2 100.00
TERNARY 502 4 4 100.00
TERNARY 506 4 4 100.00
TERNARY 489 2 2 100.00
TERNARY 493 2 2 100.00
TERNARY 502 4 3 75.00
TERNARY 506 4 3 75.00
TERNARY 489 2 2 100.00
TERNARY 493 2 2 100.00
TERNARY 502 4 3 75.00
TERNARY 506 4 3 75.00
TERNARY 489 2 2 100.00
TERNARY 493 2 2 100.00
TERNARY 502 4 2 50.00
TERNARY 506 4 2 50.00
TERNARY 489 2 2 100.00
TERNARY 493 2 2 100.00
TERNARY 502 4 3 75.00
TERNARY 506 4 3 75.00
TERNARY 489 2 2 100.00
TERNARY 493 2 2 100.00
TERNARY 502 4 2 50.00
TERNARY 506 4 2 50.00
TERNARY 489 2 2 100.00
TERNARY 493 2 2 100.00
TERNARY 502 4 3 75.00
TERNARY 506 4 3 75.00
TERNARY 489 2 2 100.00
TERNARY 493 2 2 100.00
TERNARY 502 4 2 50.00
TERNARY 506 4 2 50.00
TERNARY 489 2 2 100.00
TERNARY 493 2 2 100.00
TERNARY 502 4 3 75.00
TERNARY 506 4 3 75.00
TERNARY 489 2 2 100.00
TERNARY 493 2 2 100.00
TERNARY 502 4 3 75.00
TERNARY 506 4 3 75.00
TERNARY 489 2 2 100.00
TERNARY 493 2 2 100.00
TERNARY 502 4 3 75.00
TERNARY 506 4 3 75.00
TERNARY 489 2 2 100.00
TERNARY 493 2 2 100.00
TERNARY 502 4 3 75.00
TERNARY 506 4 3 75.00
TERNARY 489 2 2 100.00
TERNARY 493 2 2 100.00
TERNARY 502 4 2 50.00
TERNARY 506 4 2 50.00
TERNARY 489 2 2 100.00
TERNARY 493 2 2 100.00
TERNARY 502 4 4 100.00
TERNARY 506 4 4 100.00
TERNARY 489 2 2 100.00
TERNARY 493 2 2 100.00
TERNARY 502 4 3 75.00
TERNARY 506 4 3 75.00
TERNARY 489 2 2 100.00
TERNARY 493 2 2 100.00
TERNARY 502 4 3 75.00
TERNARY 506 4 3 75.00
TERNARY 489 2 2 100.00
TERNARY 493 2 2 100.00
TERNARY 502 4 3 75.00
TERNARY 506 4 3 75.00
TERNARY 489 2 2 100.00
TERNARY 493 2 2 100.00
TERNARY 502 4 2 50.00
TERNARY 506 4 2 50.00
TERNARY 489 2 2 100.00
TERNARY 493 2 2 100.00
TERNARY 502 4 4 100.00
TERNARY 506 4 4 100.00
TERNARY 489 2 2 100.00
TERNARY 493 2 2 100.00
TERNARY 502 4 3 75.00
TERNARY 506 4 3 75.00
TERNARY 489 2 2 100.00
TERNARY 493 2 2 100.00
TERNARY 502 4 2 50.00
TERNARY 506 4 2 50.00
TERNARY 525 2 2 100.00
TERNARY 529 2 2 100.00
TERNARY 538 4 3 75.00
TERNARY 542 4 3 75.00
TERNARY 525 2 2 100.00
TERNARY 529 2 2 100.00
TERNARY 538 4 3 75.00
TERNARY 542 4 3 75.00
TERNARY 525 2 2 100.00
TERNARY 529 2 2 100.00
TERNARY 538 4 2 50.00
TERNARY 542 4 2 50.00
TERNARY 525 2 2 100.00
TERNARY 529 2 2 100.00
TERNARY 538 4 3 75.00
TERNARY 542 4 3 75.00
TERNARY 525 2 2 100.00
TERNARY 529 2 2 100.00
TERNARY 538 4 3 75.00
TERNARY 542 4 3 75.00
TERNARY 525 2 2 100.00
TERNARY 529 2 2 100.00
TERNARY 538 4 3 75.00
TERNARY 542 4 3 75.00
TERNARY 525 2 2 100.00
TERNARY 529 2 2 100.00
TERNARY 538 4 3 75.00
TERNARY 542 4 3 75.00
TERNARY 525 2 2 100.00
TERNARY 529 2 2 100.00
TERNARY 538 4 3 75.00
TERNARY 542 4 3 75.00
TERNARY 525 2 2 100.00
TERNARY 529 2 2 100.00
TERNARY 538 4 3 75.00
TERNARY 542 4 3 75.00
TERNARY 525 2 2 100.00
TERNARY 529 2 2 100.00
TERNARY 538 4 3 75.00
TERNARY 542 4 3 75.00
TERNARY 525 2 2 100.00
TERNARY 529 2 2 100.00
TERNARY 538 4 3 75.00
TERNARY 542 4 3 75.00
TERNARY 525 2 2 100.00
TERNARY 529 2 2 100.00
TERNARY 538 4 3 75.00
TERNARY 542 4 3 75.00
TERNARY 525 2 2 100.00
TERNARY 529 2 2 100.00
TERNARY 538 4 2 50.00
TERNARY 542 4 2 50.00
TERNARY 525 2 2 100.00
TERNARY 529 2 2 100.00
TERNARY 538 4 2 50.00
TERNARY 542 4 2 50.00
TERNARY 525 2 2 100.00
TERNARY 529 2 2 100.00
TERNARY 538 4 3 75.00
TERNARY 542 4 3 75.00
TERNARY 525 2 2 100.00
TERNARY 529 2 2 100.00
TERNARY 538 4 2 50.00
TERNARY 542 4 2 50.00
TERNARY 601 2 2 100.00
TERNARY 601 2 1 50.00
TERNARY 601 2 2 100.00
TERNARY 601 2 1 50.00
TERNARY 601 2 2 100.00
TERNARY 601 2 2 100.00
TERNARY 601 2 1 50.00
TERNARY 601 2 2 100.00
IF 162 2 2 100.00
IF 433 2 2 100.00
IF 563 2 1 50.00


489 assign mio_out[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T29,T76
0 Covered T1,T2,T3


493 assign mio_oe[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T29,T76
0 Covered T1,T2,T3


502 assign mio_out_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 503 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 504 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T29,T76,T83
0 1 - Covered T29,T76,T83
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


506 assign mio_oe_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 507 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 508 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T29,T76,T83
0 1 - Covered T29,T76,T83
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


489 assign mio_out[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T29,T76
0 Covered T1,T2,T3


493 assign mio_oe[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T29,T76
0 Covered T1,T2,T3


502 assign mio_out_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 503 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 504 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T7,T29,T76
0 1 - Covered T29,T76,T74
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


506 assign mio_oe_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 507 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 508 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T7,T29,T76
0 1 - Covered T29,T76,T74
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


489 assign mio_out[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T29,T76
0 Covered T1,T2,T3


493 assign mio_oe[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T29,T76
0 Covered T1,T2,T3


502 assign mio_out_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 503 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 504 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T29,T76,T83
0 1 - Covered T7,T29,T76
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


506 assign mio_oe_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 507 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 508 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T29,T76,T83
0 1 - Covered T7,T29,T76
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


489 assign mio_out[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T29,T76
0 Covered T1,T2,T3


493 assign mio_oe[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T29,T76
0 Covered T1,T2,T3


502 assign mio_out_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 503 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 504 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T29,T76,T20
0 1 - Covered T29,T76,T21
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


506 assign mio_oe_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 507 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 508 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T29,T76,T20
0 1 - Covered T29,T76,T21
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


489 assign mio_out[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T29,T76
0 Covered T1,T2,T3


493 assign mio_oe[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T29,T76
0 Covered T1,T2,T3


502 assign mio_out_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 503 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 504 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T29,T76,T20
0 1 - Covered T7,T29,T76
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


506 assign mio_oe_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 507 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 508 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T29,T76,T20
0 1 - Covered T7,T29,T76
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


489 assign mio_out[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T29,T76
0 Covered T1,T2,T3


493 assign mio_oe[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T29,T76
0 Covered T1,T2,T3


502 assign mio_out_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 503 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 504 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T29,T76,T83
0 1 - Covered T29,T76,T74
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


506 assign mio_oe_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 507 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 508 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T29,T76,T83
0 1 - Covered T29,T76,T74
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


489 assign mio_out[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T29,T76
0 Covered T1,T2,T3


493 assign mio_oe[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T29,T76
0 Covered T1,T2,T3


502 assign mio_out_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 503 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 504 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T7,T29,T76
0 1 - Covered T29,T76,T20
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


506 assign mio_oe_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 507 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 508 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T7,T29,T76
0 1 - Covered T29,T76,T20
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


489 assign mio_out[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T6,T29
0 Covered T1,T2,T3


493 assign mio_oe[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T6,T29
0 Covered T1,T2,T3


502 assign mio_out_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 503 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 504 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T7,T6,T29
0 1 - Covered T29,T76,T21
0 0 1 Covered T1,T2,T3
0 0 0 Covered T74


506 assign mio_oe_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 507 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 508 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T7,T6,T29
0 1 - Covered T29,T76,T21
0 0 1 Covered T1,T2,T3
0 0 0 Covered T74


489 assign mio_out[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T20,T21
0 Covered T1,T2,T3


493 assign mio_oe[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T20,T21
0 Covered T1,T2,T3


502 assign mio_out_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 503 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 504 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T7,T20
0 1 - Covered T21
0 0 1 Covered T1,T2,T3
0 0 0 Covered T74


506 assign mio_oe_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 507 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 508 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T7,T20
0 1 - Covered T21
0 0 1 Covered T1,T2,T3
0 0 0 Covered T74


489 assign mio_out[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T20,T21
0 Covered T1,T2,T3


493 assign mio_oe[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T20,T21
0 Covered T1,T2,T3


502 assign mio_out_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 503 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 504 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T20,T74
0 1 - Covered T21
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


506 assign mio_oe_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 507 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 508 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T20,T74
0 1 - Covered T21
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


489 assign mio_out[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T20,T21
0 Covered T1,T2,T3


493 assign mio_oe[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T20,T21
0 Covered T1,T2,T3


502 assign mio_out_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 503 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 504 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T21
0 1 - Covered T7
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


506 assign mio_oe_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 507 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 508 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T21
0 1 - Covered T7
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


489 assign mio_out[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T20,T21
0 Covered T1,T2,T3


493 assign mio_oe[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T20,T21
0 Covered T1,T2,T3


502 assign mio_out_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 503 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 504 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T20
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Covered T74


506 assign mio_oe_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 507 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 508 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T20
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Covered T74


489 assign mio_out[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T20,T21
0 Covered T1,T2,T3


493 assign mio_oe[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T20,T21
0 Covered T1,T2,T3


502 assign mio_out_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 503 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 504 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T74
0 1 - Covered T21
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


506 assign mio_oe_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 507 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 508 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T74
0 1 - Covered T21
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


489 assign mio_out[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T20,T21
0 Covered T1,T2,T3


493 assign mio_oe[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T20,T21
0 Covered T1,T2,T3


502 assign mio_out_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 503 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 504 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T20
0 1 - Covered T7,T21
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


506 assign mio_oe_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 507 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 508 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T20
0 1 - Covered T7,T21
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


489 assign mio_out[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T20,T21
0 Covered T1,T2,T3


493 assign mio_oe[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T20,T21
0 Covered T1,T2,T3


502 assign mio_out_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 503 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 504 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T74
0 1 - Covered T7,T20
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


506 assign mio_oe_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 507 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 508 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T74
0 1 - Covered T7,T20
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


489 assign mio_out[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T20,T21
0 Covered T1,T2,T3


493 assign mio_oe[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T20,T21
0 Covered T1,T2,T3


502 assign mio_out_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 503 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 504 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T74,T21
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


506 assign mio_oe_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 507 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 508 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T74,T21
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


489 assign mio_out[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T20,T21
0 Covered T1,T2,T3


493 assign mio_oe[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T20,T21
0 Covered T1,T2,T3


502 assign mio_out_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 503 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 504 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T21
0 1 - Covered T20
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


506 assign mio_oe_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 507 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 508 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T21
0 1 - Covered T20
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


489 assign mio_out[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T20,T21
0 Covered T1,T2,T3


493 assign mio_oe[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T20,T21
0 Covered T1,T2,T3


502 assign mio_out_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 503 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 504 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T20
0 1 - Covered T7,T21
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


506 assign mio_oe_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 507 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 508 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T20
0 1 - Covered T7,T21
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


489 assign mio_out[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T20,T21
0 Covered T1,T2,T3


493 assign mio_oe[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T20,T21
0 Covered T1,T2,T3


502 assign mio_out_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 503 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 504 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T21
0 1 - Covered T7,T20
0 0 1 Covered T1,T2,T3
0 0 0 Covered T74


506 assign mio_oe_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 507 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 508 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T21
0 1 - Covered T7,T20
0 0 1 Covered T1,T2,T3
0 0 0 Covered T74


489 assign mio_out[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T20,T21
0 Covered T1,T2,T3


493 assign mio_oe[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T20,T21
0 Covered T1,T2,T3


502 assign mio_out_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 503 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 504 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T7,T20,T74
0 1 - Covered T21
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


506 assign mio_oe_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 507 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 508 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T7,T20,T74
0 1 - Covered T21
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


489 assign mio_out[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T20,T21
0 Covered T1,T2,T3


493 assign mio_oe[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T20,T21
0 Covered T1,T2,T3


502 assign mio_out_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 503 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 504 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T7,T74
0 1 - Covered T21
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


506 assign mio_oe_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 507 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 508 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T7,T74
0 1 - Covered T21
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


489 assign mio_out[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T20,T21
0 Covered T1,T2,T3


493 assign mio_oe[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T20,T21
0 Covered T1,T2,T3


502 assign mio_out_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 503 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 504 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T7,T21
0 1 - Covered T20
0 0 1 Covered T1,T2,T3
0 0 0 Covered T74


506 assign mio_oe_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 507 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 508 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T7,T21
0 1 - Covered T20
0 0 1 Covered T1,T2,T3
0 0 0 Covered T74


489 assign mio_out[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T20,T21
0 Covered T1,T2,T3


493 assign mio_oe[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T20,T21
0 Covered T1,T2,T3


502 assign mio_out_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 503 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 504 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T7,T20,T74
0 1 - Covered T21
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


506 assign mio_oe_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 507 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 508 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T7,T20,T74
0 1 - Covered T21
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


489 assign mio_out[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T20,T21
0 Covered T1,T2,T3


493 assign mio_oe[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T20,T21
0 Covered T1,T2,T3


502 assign mio_out_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 503 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 504 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T21
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


506 assign mio_oe_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 507 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 508 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T21
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


489 assign mio_out[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T20,T21
0 Covered T1,T2,T3


493 assign mio_oe[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T20,T21
0 Covered T1,T2,T3


502 assign mio_out_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 503 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 504 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T20
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


506 assign mio_oe_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 507 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 508 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T20
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


489 assign mio_out[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T20,T21
0 Covered T1,T2,T3


493 assign mio_oe[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T20,T21
0 Covered T1,T2,T3


502 assign mio_out_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 503 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 504 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T21
0 1 - Covered T7
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


506 assign mio_oe_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 507 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 508 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T21
0 1 - Covered T7
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


489 assign mio_out[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T20,T21
0 Covered T1,T2,T3


493 assign mio_oe[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T20,T21
0 Covered T1,T2,T3


502 assign mio_out_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 503 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 504 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T7
0 1 - Covered T21
0 0 1 Covered T1,T2,T3
0 0 0 Covered T74


506 assign mio_oe_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 507 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 508 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T7
0 1 - Covered T21
0 0 1 Covered T1,T2,T3
0 0 0 Covered T74


489 assign mio_out[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T20,T21
0 Covered T1,T2,T3


493 assign mio_oe[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T20,T21
0 Covered T1,T2,T3


502 assign mio_out_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 503 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 504 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T74
0 1 - Covered T20
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


506 assign mio_oe_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 507 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 508 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T74
0 1 - Covered T20
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


489 assign mio_out[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T20,T21
0 Covered T1,T2,T3


493 assign mio_oe[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T20,T21
0 Covered T1,T2,T3


502 assign mio_out_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 503 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 504 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T74,T21
0 1 - Covered T7,T20
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


506 assign mio_oe_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 507 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 508 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T74,T21
0 1 - Covered T7,T20
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


489 assign mio_out[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T20,T21
0 Covered T1,T2,T3


493 assign mio_oe[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T20,T21
0 Covered T1,T2,T3


502 assign mio_out_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 503 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 504 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Not Covered
0 1 - Covered T7,T74
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


506 assign mio_oe_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 507 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 508 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Not Covered
0 1 - Covered T7,T74
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


489 assign mio_out[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T20,T21
0 Covered T1,T2,T3


493 assign mio_oe[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T20,T21
0 Covered T1,T2,T3


502 assign mio_out_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 503 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 504 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T7,T74
0 1 - Covered T20,T21
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


506 assign mio_oe_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 507 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 508 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T7,T74
0 1 - Covered T20,T21
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


489 assign mio_out[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T20,T21
0 Covered T1,T2,T3


493 assign mio_oe[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T20,T21
0 Covered T1,T2,T3


502 assign mio_out_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 503 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 504 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T21
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


506 assign mio_oe_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 507 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 508 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T21
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


489 assign mio_out[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T20,T21
0 Covered T1,T2,T3


493 assign mio_oe[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T20,T21
0 Covered T1,T2,T3


502 assign mio_out_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 503 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 504 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T21
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Covered T74


506 assign mio_oe_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 507 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 508 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T21
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Covered T74


489 assign mio_out[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T20,T21
0 Covered T1,T2,T3


493 assign mio_oe[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T20,T21
0 Covered T1,T2,T3


502 assign mio_out_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 503 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 504 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T7
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


506 assign mio_oe_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 507 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 508 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T7
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


489 assign mio_out[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T20,T21
0 Covered T1,T2,T3


493 assign mio_oe[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T20,T21
0 Covered T1,T2,T3


502 assign mio_out_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 503 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 504 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T7
0 1 - Covered T20
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


506 assign mio_oe_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 507 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 508 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T7
0 1 - Covered T20
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


489 assign mio_out[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T20,T21
0 Covered T1,T2,T3


493 assign mio_oe[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T20,T21
0 Covered T1,T2,T3


502 assign mio_out_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 503 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 504 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T20
0 1 - Covered T7
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


506 assign mio_oe_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 507 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 508 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T20
0 1 - Covered T7
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


489 assign mio_out[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T20,T21
0 Covered T1,T2,T3


493 assign mio_oe[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T20,T21
0 Covered T1,T2,T3


502 assign mio_out_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 503 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 504 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T7,T74
0 1 - Covered T20,T21
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


506 assign mio_oe_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 507 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 508 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T7,T74
0 1 - Covered T20,T21
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


489 assign mio_out[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T20,T21
0 Covered T1,T2,T3


493 assign mio_oe[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T20,T21
0 Covered T1,T2,T3


502 assign mio_out_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 503 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 504 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T20,T21
0 1 - Covered T7
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


506 assign mio_oe_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 507 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 508 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T20,T21
0 1 - Covered T7
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


489 assign mio_out[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T20,T21
0 Covered T1,T2,T3


493 assign mio_oe[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T20,T21
0 Covered T1,T2,T3


502 assign mio_out_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 503 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 504 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Not Covered
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Covered T74


506 assign mio_oe_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 507 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 508 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Not Covered
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Covered T74


489 assign mio_out[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T20,T21
0 Covered T1,T2,T3


493 assign mio_oe[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T20,T21
0 Covered T1,T2,T3


502 assign mio_out_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 503 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 504 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T21
0 1 - Covered T7
0 0 1 Covered T1,T2,T3
0 0 0 Covered T74


506 assign mio_oe_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 507 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 508 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T21
0 1 - Covered T7
0 0 1 Covered T1,T2,T3
0 0 0 Covered T74


489 assign mio_out[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T20,T21
0 Covered T1,T2,T3


493 assign mio_oe[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T20,T21
0 Covered T1,T2,T3


502 assign mio_out_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 503 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 504 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T74
0 1 - Covered T21
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


506 assign mio_oe_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 507 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 508 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T74
0 1 - Covered T21
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


489 assign mio_out[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T20,T21
0 Covered T1,T2,T3


493 assign mio_oe[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T20,T21
0 Covered T1,T2,T3


502 assign mio_out_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 503 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 504 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Not Covered
0 1 - Covered T20
0 0 1 Covered T1,T2,T3
0 0 0 Covered T74


506 assign mio_oe_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 507 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 508 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Not Covered
0 1 - Covered T20
0 0 1 Covered T1,T2,T3
0 0 0 Covered T74


489 assign mio_out[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T20,T21
0 Covered T1,T2,T3


493 assign mio_oe[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T20,T21
0 Covered T1,T2,T3


502 assign mio_out_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 503 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 504 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T74,T21
0 1 - Covered T7,T20
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


506 assign mio_oe_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 507 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 508 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T74,T21
0 1 - Covered T7,T20
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


489 assign mio_out[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T20,T21
0 Covered T1,T2,T3


493 assign mio_oe[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T20,T21
0 Covered T1,T2,T3


502 assign mio_out_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 503 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 504 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Not Covered
0 1 - Covered T7,T74
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


506 assign mio_oe_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 507 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 508 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Not Covered
0 1 - Covered T7,T74
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


489 assign mio_out[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T20,T21
0 Covered T1,T2,T3


493 assign mio_oe[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T20,T21
0 Covered T1,T2,T3


502 assign mio_out_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 503 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 504 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T20
0 1 - Covered T7,T21
0 0 1 Covered T1,T2,T3
0 0 0 Covered T74


506 assign mio_oe_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 507 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 508 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T20
0 1 - Covered T7,T21
0 0 1 Covered T1,T2,T3
0 0 0 Covered T74


489 assign mio_out[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T20,T21
0 Covered T1,T2,T3


493 assign mio_oe[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T20,T21
0 Covered T1,T2,T3


502 assign mio_out_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 503 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 504 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T21
0 1 - Covered T74
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


506 assign mio_oe_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 507 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 508 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T21
0 1 - Covered T74
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


489 assign mio_out[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T20,T21
0 Covered T1,T2,T3


493 assign mio_oe[k] = reg2hw.mio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T20,T21
0 Covered T1,T2,T3


502 assign mio_out_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 503 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 504 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T20,T21
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


506 assign mio_oe_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 507 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 508 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T20,T21
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


525 assign dio_out[k] = reg2hw.dio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T20,T21
0 Covered T1,T2,T3


529 assign dio_oe[k] = reg2hw.dio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T20,T21
0 Covered T1,T2,T3


538 assign dio_out_retreg_d[k] = (reg2hw.dio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 539 (reg2hw.dio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 540 (reg2hw.dio_pad_sleep_mode[k].q == 2) ? 1'b0 : dio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Not Covered
0 1 - Covered T20,T21
0 0 1 Covered T1,T2,T3
0 0 0 Covered T74


542 assign dio_oe_retreg_d[k] = (reg2hw.dio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 543 (reg2hw.dio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 544 (reg2hw.dio_pad_sleep_mode[k].q == 2) ? 1'b0 : dio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Not Covered
0 1 - Covered T20,T21
0 0 1 Covered T1,T2,T3
0 0 0 Covered T74


525 assign dio_out[k] = reg2hw.dio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T20,T21
0 Covered T1,T2,T3


529 assign dio_oe[k] = reg2hw.dio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T20,T21
0 Covered T1,T2,T3


538 assign dio_out_retreg_d[k] = (reg2hw.dio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 539 (reg2hw.dio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 540 (reg2hw.dio_pad_sleep_mode[k].q == 2) ? 1'b0 : dio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T7
0 1 - Covered T21
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


542 assign dio_oe_retreg_d[k] = (reg2hw.dio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 543 (reg2hw.dio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 544 (reg2hw.dio_pad_sleep_mode[k].q == 2) ? 1'b0 : dio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T7
0 1 - Covered T21
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


525 assign dio_out[k] = reg2hw.dio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T20,T21
0 Covered T1,T2,T3


529 assign dio_oe[k] = reg2hw.dio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T20,T21
0 Covered T1,T2,T3


538 assign dio_out_retreg_d[k] = (reg2hw.dio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 539 (reg2hw.dio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 540 (reg2hw.dio_pad_sleep_mode[k].q == 2) ? 1'b0 : dio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Not Covered
0 1 - Covered T7,T21
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


542 assign dio_oe_retreg_d[k] = (reg2hw.dio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 543 (reg2hw.dio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 544 (reg2hw.dio_pad_sleep_mode[k].q == 2) ? 1'b0 : dio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Not Covered
0 1 - Covered T7,T21
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


525 assign dio_out[k] = reg2hw.dio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T20,T21
0 Covered T1,T2,T3


529 assign dio_oe[k] = reg2hw.dio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T20,T21
0 Covered T1,T2,T3


538 assign dio_out_retreg_d[k] = (reg2hw.dio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 539 (reg2hw.dio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 540 (reg2hw.dio_pad_sleep_mode[k].q == 2) ? 1'b0 : dio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T20
0 1 - Covered T7,T21
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


542 assign dio_oe_retreg_d[k] = (reg2hw.dio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 543 (reg2hw.dio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 544 (reg2hw.dio_pad_sleep_mode[k].q == 2) ? 1'b0 : dio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T20
0 1 - Covered T7,T21
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


525 assign dio_out[k] = reg2hw.dio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T20,T21
0 Covered T1,T2,T3


529 assign dio_oe[k] = reg2hw.dio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T20,T21
0 Covered T1,T2,T3


538 assign dio_out_retreg_d[k] = (reg2hw.dio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 539 (reg2hw.dio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 540 (reg2hw.dio_pad_sleep_mode[k].q == 2) ? 1'b0 : dio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T7,T20
0 1 - Covered T74,T21
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


542 assign dio_oe_retreg_d[k] = (reg2hw.dio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 543 (reg2hw.dio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 544 (reg2hw.dio_pad_sleep_mode[k].q == 2) ? 1'b0 : dio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T7,T20
0 1 - Covered T74,T21
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


525 assign dio_out[k] = reg2hw.dio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T20,T21
0 Covered T1,T2,T3


529 assign dio_oe[k] = reg2hw.dio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T20,T21
0 Covered T1,T2,T3


538 assign dio_out_retreg_d[k] = (reg2hw.dio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 539 (reg2hw.dio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 540 (reg2hw.dio_pad_sleep_mode[k].q == 2) ? 1'b0 : dio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T7
0 1 - Covered T74
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


542 assign dio_oe_retreg_d[k] = (reg2hw.dio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 543 (reg2hw.dio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 544 (reg2hw.dio_pad_sleep_mode[k].q == 2) ? 1'b0 : dio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T7
0 1 - Covered T74
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


525 assign dio_out[k] = reg2hw.dio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T6,T20
0 Covered T1,T2,T3


529 assign dio_oe[k] = reg2hw.dio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T6,T20
0 Covered T1,T2,T3


538 assign dio_out_retreg_d[k] = (reg2hw.dio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 539 (reg2hw.dio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 540 (reg2hw.dio_pad_sleep_mode[k].q == 2) ? 1'b0 : dio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T7,T6,T20
0 1 - Covered T6,T84,T74
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


542 assign dio_oe_retreg_d[k] = (reg2hw.dio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 543 (reg2hw.dio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 544 (reg2hw.dio_pad_sleep_mode[k].q == 2) ? 1'b0 : dio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T7,T6,T20
0 1 - Covered T6,T84,T74
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


525 assign dio_out[k] = reg2hw.dio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T6,T20
0 Covered T1,T2,T3


529 assign dio_oe[k] = reg2hw.dio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T6,T20
0 Covered T1,T2,T3


538 assign dio_out_retreg_d[k] = (reg2hw.dio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 539 (reg2hw.dio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 540 (reg2hw.dio_pad_sleep_mode[k].q == 2) ? 1'b0 : dio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T6,T20,T84
0 1 - Covered T7,T6,T84
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


542 assign dio_oe_retreg_d[k] = (reg2hw.dio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 543 (reg2hw.dio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 544 (reg2hw.dio_pad_sleep_mode[k].q == 2) ? 1'b0 : dio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T6,T20,T84
0 1 - Covered T7,T6,T84
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


525 assign dio_out[k] = reg2hw.dio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T6,T20
0 Covered T1,T2,T3


529 assign dio_oe[k] = reg2hw.dio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T6,T20
0 Covered T1,T2,T3


538 assign dio_out_retreg_d[k] = (reg2hw.dio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 539 (reg2hw.dio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 540 (reg2hw.dio_pad_sleep_mode[k].q == 2) ? 1'b0 : dio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T6,T20,T84
0 1 - Covered T7,T6,T84
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


542 assign dio_oe_retreg_d[k] = (reg2hw.dio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 543 (reg2hw.dio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 544 (reg2hw.dio_pad_sleep_mode[k].q == 2) ? 1'b0 : dio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T6,T20,T84
0 1 - Covered T7,T6,T84
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


525 assign dio_out[k] = reg2hw.dio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T6,T20
0 Covered T1,T2,T3


529 assign dio_oe[k] = reg2hw.dio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T6,T20
0 Covered T1,T2,T3


538 assign dio_out_retreg_d[k] = (reg2hw.dio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 539 (reg2hw.dio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 540 (reg2hw.dio_pad_sleep_mode[k].q == 2) ? 1'b0 : dio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T7,T6,T84
0 1 - Covered T6,T84,T85
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


542 assign dio_oe_retreg_d[k] = (reg2hw.dio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 543 (reg2hw.dio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 544 (reg2hw.dio_pad_sleep_mode[k].q == 2) ? 1'b0 : dio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T7,T6,T84
0 1 - Covered T6,T84,T85
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


525 assign dio_out[k] = reg2hw.dio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T20,T21
0 Covered T1,T2,T3


529 assign dio_oe[k] = reg2hw.dio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T20,T21
0 Covered T1,T2,T3


538 assign dio_out_retreg_d[k] = (reg2hw.dio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 539 (reg2hw.dio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 540 (reg2hw.dio_pad_sleep_mode[k].q == 2) ? 1'b0 : dio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T7,T20,T74
0 1 - Covered T21
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


542 assign dio_oe_retreg_d[k] = (reg2hw.dio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 543 (reg2hw.dio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 544 (reg2hw.dio_pad_sleep_mode[k].q == 2) ? 1'b0 : dio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T7,T20,T74
0 1 - Covered T21
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


525 assign dio_out[k] = reg2hw.dio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T20,T21
0 Covered T1,T2,T3


529 assign dio_oe[k] = reg2hw.dio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T20,T21
0 Covered T1,T2,T3


538 assign dio_out_retreg_d[k] = (reg2hw.dio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 539 (reg2hw.dio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 540 (reg2hw.dio_pad_sleep_mode[k].q == 2) ? 1'b0 : dio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T7,T74
0 1 - Covered T20,T21
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


542 assign dio_oe_retreg_d[k] = (reg2hw.dio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 543 (reg2hw.dio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 544 (reg2hw.dio_pad_sleep_mode[k].q == 2) ? 1'b0 : dio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T7,T74
0 1 - Covered T20,T21
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


525 assign dio_out[k] = reg2hw.dio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T20,T21
0 Covered T1,T2,T3


529 assign dio_oe[k] = reg2hw.dio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T20,T21
0 Covered T1,T2,T3


538 assign dio_out_retreg_d[k] = (reg2hw.dio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 539 (reg2hw.dio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 540 (reg2hw.dio_pad_sleep_mode[k].q == 2) ? 1'b0 : dio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T74
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


542 assign dio_oe_retreg_d[k] = (reg2hw.dio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 543 (reg2hw.dio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 544 (reg2hw.dio_pad_sleep_mode[k].q == 2) ? 1'b0 : dio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T74
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


525 assign dio_out[k] = reg2hw.dio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T20,T21
0 Covered T1,T2,T3


529 assign dio_oe[k] = reg2hw.dio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T20,T21
0 Covered T1,T2,T3


538 assign dio_out_retreg_d[k] = (reg2hw.dio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 539 (reg2hw.dio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 540 (reg2hw.dio_pad_sleep_mode[k].q == 2) ? 1'b0 : dio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Not Covered
0 1 - Covered T74
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


542 assign dio_oe_retreg_d[k] = (reg2hw.dio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 543 (reg2hw.dio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 544 (reg2hw.dio_pad_sleep_mode[k].q == 2) ? 1'b0 : dio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Not Covered
0 1 - Covered T74
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


525 assign dio_out[k] = reg2hw.dio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T20,T21
0 Covered T1,T2,T3


529 assign dio_oe[k] = reg2hw.dio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T20,T21
0 Covered T1,T2,T3


538 assign dio_out_retreg_d[k] = (reg2hw.dio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 539 (reg2hw.dio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 540 (reg2hw.dio_pad_sleep_mode[k].q == 2) ? 1'b0 : dio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T20
0 1 - Covered T7
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


542 assign dio_oe_retreg_d[k] = (reg2hw.dio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 543 (reg2hw.dio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 544 (reg2hw.dio_pad_sleep_mode[k].q == 2) ? 1'b0 : dio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T20
0 1 - Covered T7
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


525 assign dio_out[k] = reg2hw.dio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T20,T21
0 Covered T1,T2,T3


529 assign dio_oe[k] = reg2hw.dio_pad_sleep_status[k].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T7,T20,T21
0 Covered T1,T2,T3


538 assign dio_out_retreg_d[k] = (reg2hw.dio_pad_sleep_mode[k].q == 0) ? 1'b0 : -1- ==> 539 (reg2hw.dio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 540 (reg2hw.dio_pad_sleep_mode[k].q == 2) ? 1'b0 : dio_out[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Not Covered
0 1 - Covered T7,T74
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


542 assign dio_oe_retreg_d[k] = (reg2hw.dio_pad_sleep_mode[k].q == 0) ? 1'b1 : -1- ==> 543 (reg2hw.dio_pad_sleep_mode[k].q == 1) ? 1'b1 : -2- ==> 544 (reg2hw.dio_pad_sleep_mode[k].q == 2) ? 1'b0 : dio_oe[k]; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Not Covered
0 1 - Covered T7,T74
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


601 assign pin_value = (reg2hw.wkup_detector[k].miodio.q) ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T6,T84,T85
0 Covered T1,T2,T3


601 assign pin_value = (reg2hw.wkup_detector[k].miodio.q) ? -1- ==> ==>

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


601 assign pin_value = (reg2hw.wkup_detector[k].miodio.q) ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T26,T74
0 Covered T1,T2,T3


601 assign pin_value = (reg2hw.wkup_detector[k].miodio.q) ? -1- ==> ==>

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


601 assign pin_value = (reg2hw.wkup_detector[k].miodio.q) ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T74,T27
0 Covered T1,T2,T3


601 assign pin_value = (reg2hw.wkup_detector[k].miodio.q) ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T74
0 Covered T1,T2,T3


601 assign pin_value = (reg2hw.wkup_detector[k].miodio.q) ? -1- ==> ==>

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


601 assign pin_value = (reg2hw.wkup_detector[k].miodio.q) ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T74
0 Covered T1,T2,T3


162 if (!rst_ni) begin -1- 163 dio_pad_attr_q <= '0; ==> 164 for (int kk = 0; kk < NMioPads; kk++) begin 165 if (kk == TargetCfg.tap_strap0_idx) begin 166 // TAP strap 0 is sampled after reset (and only once for life cycle states that are not 167 // TEST_UNLOCKED* or RMA). To ensure it gets sampled as 0 unless driven to 1 from an 168 // external source (and specifically that it gets sampled as 0 when left floating / not 169 // connected), this enables the pull-down of the pad at reset. 170 mio_pad_attr_q[kk] <= '{pull_en: 1'b1, default: '0}; 171 end else begin 172 mio_pad_attr_q[kk] <= '0; 173 end 174 end 175 end else begin 176 // dedicated pads 177 for (int kk = 0; kk < NDioPads; kk++) begin ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


433 if (!rst_ni) begin -1- 434 sleep_en_q <= 1'b0; ==> 435 mio_out_retreg_q <= '0; 436 mio_oe_retreg_q <= '0; 437 dio_out_retreg_q <= '0; 438 dio_oe_retreg_q <= '0; 439 end else begin 440 sleep_en_q <= sleep_en_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


563 if (prim_mubi_pkg::mubi4_test_true_strict(scanmode_i)) begin -1- 564 dio_wkup_no_scan[k] = 1'b0; ==> 565 end MISSING_ELSE ==>

Branches:
-1-StatusTests
1 Not Covered
0 Covered T7,T6,T13


Assert Coverage for Module : pinmux
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 25 25 100.00 23 92.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 25 25 100.00 23 92.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AlertsKnown_A 123015988 122339418 0 0
AonWkupReqKnownO_A 1453845 1259802 0 0
DftJtagTckKnown_A 123015988 122339418 0 0
DftJtagTmsKnown_A 123015988 122339418 0 0
DftJtagTrstKnown_A 123015988 122339418 0 0
DftStrapsKnown_A 123015988 122339418 0 0
DioKnownO_A 123015988 122339418 0 0
DioOeKnownO_A 123015988 122339418 0 0
FpvSecCmBusIntegrity_A 123015988 0 0 0
FpvSecCmRegWeOnehotCheck_A 123015988 7 0 0
LcJtagTckKnown_A 123015988 122339418 0 0
LcJtagTmsKnown_A 123015988 122339418 0 0
LcJtagTrstKnown_A 123015988 122339418 0 0
MioKnownO_A 123015988 122339418 0 0
MioOeKnownO_A 123015988 122339418 0 0
PinmuxWkupStable_A 1453845 5161 0 0
PwrMgrStrapSampleOnce0_A 123015988 1692 0 0
PwrMgrStrapSampleOnce1_A 123015988 0 0 970
RvJtagTckKnown_A 123015988 122339418 0 0
RvJtagTmsKnown_A 123015988 122339418 0 0
RvJtagTrstKnown_A 123015988 122339418 0 0
TlAReadyKnownO_A 123015988 122339418 0 0
TlDValidKnownO_A 123015988 122339418 0 0
UsbWakeDetectActiveKnownO_A 1453845 1259802 0 0
UsbWkupReqKnownO_A 1453845 1259802 0 0


AlertsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 123015988 122339418 0 0
T1 27617 27229 0 0
T2 19812 19316 0 0
T3 10964 10508 0 0
T4 25985 25138 0 0
T5 25239 24581 0 0
T6 35891 34928 0 0
T7 25464 24868 0 0
T28 24307 23793 0 0
T109 17085 16650 0 0
T110 17700 16837 0 0

AonWkupReqKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1453845 1259802 0 0
T1 479 306 0 0
T2 382 209 0 0
T3 342 168 0 0
T4 388 214 0 0
T5 410 236 0 0
T6 460 286 0 0
T7 431 259 0 0
T28 414 241 0 0
T109 396 224 0 0
T110 315 143 0 0

DftJtagTckKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 123015988 122339418 0 0
T1 27617 27229 0 0
T2 19812 19316 0 0
T3 10964 10508 0 0
T4 25985 25138 0 0
T5 25239 24581 0 0
T6 35891 34928 0 0
T7 25464 24868 0 0
T28 24307 23793 0 0
T109 17085 16650 0 0
T110 17700 16837 0 0

DftJtagTmsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 123015988 122339418 0 0
T1 27617 27229 0 0
T2 19812 19316 0 0
T3 10964 10508 0 0
T4 25985 25138 0 0
T5 25239 24581 0 0
T6 35891 34928 0 0
T7 25464 24868 0 0
T28 24307 23793 0 0
T109 17085 16650 0 0
T110 17700 16837 0 0

DftJtagTrstKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 123015988 122339418 0 0
T1 27617 27229 0 0
T2 19812 19316 0 0
T3 10964 10508 0 0
T4 25985 25138 0 0
T5 25239 24581 0 0
T6 35891 34928 0 0
T7 25464 24868 0 0
T28 24307 23793 0 0
T109 17085 16650 0 0
T110 17700 16837 0 0

DftStrapsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 123015988 122339418 0 0
T1 27617 27229 0 0
T2 19812 19316 0 0
T3 10964 10508 0 0
T4 25985 25138 0 0
T5 25239 24581 0 0
T6 35891 34928 0 0
T7 25464 24868 0 0
T28 24307 23793 0 0
T109 17085 16650 0 0
T110 17700 16837 0 0

DioKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 123015988 122339418 0 0
T1 27617 27229 0 0
T2 19812 19316 0 0
T3 10964 10508 0 0
T4 25985 25138 0 0
T5 25239 24581 0 0
T6 35891 34928 0 0
T7 25464 24868 0 0
T28 24307 23793 0 0
T109 17085 16650 0 0
T110 17700 16837 0 0

DioOeKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 123015988 122339418 0 0
T1 27617 27229 0 0
T2 19812 19316 0 0
T3 10964 10508 0 0
T4 25985 25138 0 0
T5 25239 24581 0 0
T6 35891 34928 0 0
T7 25464 24868 0 0
T28 24307 23793 0 0
T109 17085 16650 0 0
T110 17700 16837 0 0

FpvSecCmBusIntegrity_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 123015988 0 0 0

FpvSecCmRegWeOnehotCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 123015988 7 0 0
T111 42055 1 0 0
T112 0 1 0 0
T113 0 1 0 0
T114 0 1 0 0
T115 0 1 0 0
T116 0 1 0 0
T117 0 1 0 0
T118 36327 0 0 0
T119 53923 0 0 0
T120 163683 0 0 0
T121 101619 0 0 0
T122 67147 0 0 0
T123 55011 0 0 0
T124 161561 0 0 0
T125 54808 0 0 0
T126 995095 0 0 0

LcJtagTckKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 123015988 122339418 0 0
T1 27617 27229 0 0
T2 19812 19316 0 0
T3 10964 10508 0 0
T4 25985 25138 0 0
T5 25239 24581 0 0
T6 35891 34928 0 0
T7 25464 24868 0 0
T28 24307 23793 0 0
T109 17085 16650 0 0
T110 17700 16837 0 0

LcJtagTmsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 123015988 122339418 0 0
T1 27617 27229 0 0
T2 19812 19316 0 0
T3 10964 10508 0 0
T4 25985 25138 0 0
T5 25239 24581 0 0
T6 35891 34928 0 0
T7 25464 24868 0 0
T28 24307 23793 0 0
T109 17085 16650 0 0
T110 17700 16837 0 0

LcJtagTrstKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 123015988 122339418 0 0
T1 27617 27229 0 0
T2 19812 19316 0 0
T3 10964 10508 0 0
T4 25985 25138 0 0
T5 25239 24581 0 0
T6 35891 34928 0 0
T7 25464 24868 0 0
T28 24307 23793 0 0
T109 17085 16650 0 0
T110 17700 16837 0 0

MioKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 123015988 122339418 0 0
T1 27617 27229 0 0
T2 19812 19316 0 0
T3 10964 10508 0 0
T4 25985 25138 0 0
T5 25239 24581 0 0
T6 35891 34928 0 0
T7 25464 24868 0 0
T28 24307 23793 0 0
T109 17085 16650 0 0
T110 17700 16837 0 0

MioOeKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 123015988 122339418 0 0
T1 27617 27229 0 0
T2 19812 19316 0 0
T3 10964 10508 0 0
T4 25985 25138 0 0
T5 25239 24581 0 0
T6 35891 34928 0 0
T7 25464 24868 0 0
T28 24307 23793 0 0
T109 17085 16650 0 0
T110 17700 16837 0 0

PinmuxWkupStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1453845 5161 0 0
T6 460 94 0 0
T8 623 0 0 0
T9 601 0 0 0
T13 420 0 0 0
T25 535 21 0 0
T26 0 558 0 0
T29 671 92 0 0
T32 654 0 0 0
T35 372 0 0 0
T46 794 0 0 0
T73 662 0 0 0
T76 0 114 0 0
T77 0 23 0 0
T78 0 525 0 0
T79 0 623 0 0
T84 0 80 0 0
T127 0 24 0 0

PwrMgrStrapSampleOnce0_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 123015988 1692 0 0
T1 27617 1 0 0
T2 19812 1 0 0
T3 10964 1 0 0
T4 25985 1 0 0
T5 25239 1 0 0
T6 35891 1 0 0
T7 25464 1 0 0
T28 24307 1 0 0
T109 17085 1 0 0
T110 17700 1 0 0

PwrMgrStrapSampleOnce1_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 123015988 0 0 970

RvJtagTckKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 123015988 122339418 0 0
T1 27617 27229 0 0
T2 19812 19316 0 0
T3 10964 10508 0 0
T4 25985 25138 0 0
T5 25239 24581 0 0
T6 35891 34928 0 0
T7 25464 24868 0 0
T28 24307 23793 0 0
T109 17085 16650 0 0
T110 17700 16837 0 0

RvJtagTmsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 123015988 122339418 0 0
T1 27617 27229 0 0
T2 19812 19316 0 0
T3 10964 10508 0 0
T4 25985 25138 0 0
T5 25239 24581 0 0
T6 35891 34928 0 0
T7 25464 24868 0 0
T28 24307 23793 0 0
T109 17085 16650 0 0
T110 17700 16837 0 0

RvJtagTrstKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 123015988 122339418 0 0
T1 27617 27229 0 0
T2 19812 19316 0 0
T3 10964 10508 0 0
T4 25985 25138 0 0
T5 25239 24581 0 0
T6 35891 34928 0 0
T7 25464 24868 0 0
T28 24307 23793 0 0
T109 17085 16650 0 0
T110 17700 16837 0 0

TlAReadyKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 123015988 122339418 0 0
T1 27617 27229 0 0
T2 19812 19316 0 0
T3 10964 10508 0 0
T4 25985 25138 0 0
T5 25239 24581 0 0
T6 35891 34928 0 0
T7 25464 24868 0 0
T28 24307 23793 0 0
T109 17085 16650 0 0
T110 17700 16837 0 0

TlDValidKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 123015988 122339418 0 0
T1 27617 27229 0 0
T2 19812 19316 0 0
T3 10964 10508 0 0
T4 25985 25138 0 0
T5 25239 24581 0 0
T6 35891 34928 0 0
T7 25464 24868 0 0
T28 24307 23793 0 0
T109 17085 16650 0 0
T110 17700 16837 0 0

UsbWakeDetectActiveKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1453845 1259802 0 0
T1 479 306 0 0
T2 382 209 0 0
T3 342 168 0 0
T4 388 214 0 0
T5 410 236 0 0
T6 460 286 0 0
T7 431 259 0 0
T28 414 241 0 0
T109 396 224 0 0
T110 315 143 0 0

UsbWkupReqKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1453845 1259802 0 0
T1 479 306 0 0
T2 382 209 0 0
T3 342 168 0 0
T4 388 214 0 0
T5 410 236 0 0
T6 460 286 0 0
T7 431 259 0 0
T28 414 241 0 0
T109 396 224 0 0
T110 315 143 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%