Line Coverage for Module :
prim_generic_pad_wrapper ( parameter PadType=3,ScanRole )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 4 | 4 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 57 | 0 | 0 | |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 66 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 71 | 1 | 1 | 100.00 |
38 logic unused_sigs;
39 unreachable assign unused_sigs = ^{attr_i.slew_rate,
40 attr_i.drive_strength[3:1],
41 attr_i.od_en,
42 attr_i.schmitt_en,
43 attr_i.keep_en,
44 scanmode_i,
45 pok_i};
46 //VCS coverage on
47 // pragma coverage on
48
49 // Input enable (active-high)
50 logic ie;
51 1/1 assign ie = ie_i & ~attr_i.input_disable;
Tests: T14 T15 T16
52
53 if (PadType == InputStd) begin : gen_input_only
54 //VCS coverage off
55 // pragma coverage off
56 logic unused_in_sigs;
57 unreachable assign unused_in_sigs = ^{out_i,
58 oe_i,
59 attr_i.virt_od_en,
60 attr_i.drive_strength};
61 //VCS coverage on
62 // pragma coverage on
63
64 1/1 assign in_raw_o = ie ? inout_io : 1'bz;
Tests: T1 T2 T3
65 // input inversion
66 1/1 assign in_o = attr_i.invert ^ in_raw_o;
Tests: T1 T2 T3
67
68 // pulls are not supported by verilator
69 `ifndef VERILATOR
70 // pullup / pulldown termination
71 1/1 assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
Tests: T14 T15 T16
Line Coverage for Module :
prim_generic_pad_wrapper ( parameter PadType=0,ScanRole=0 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 8 | 8 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
38 logic unused_sigs;
39 unreachable assign unused_sigs = ^{attr_i.slew_rate,
40 attr_i.drive_strength[3:1],
41 attr_i.od_en,
42 attr_i.schmitt_en,
43 attr_i.keep_en,
44 scanmode_i,
45 pok_i};
46 //VCS coverage on
47 // pragma coverage on
48
49 // Input enable (active-high)
50 logic ie;
51 1/1 assign ie = ie_i & ~attr_i.input_disable;
Tests: T14 T15 T16
52
53 if (PadType == InputStd) begin : gen_input_only
54 //VCS coverage off
55 // pragma coverage off
56 logic unused_in_sigs;
57 assign unused_in_sigs = ^{out_i,
58 oe_i,
59 attr_i.virt_od_en,
60 attr_i.drive_strength};
61 //VCS coverage on
62 // pragma coverage on
63
64 assign in_raw_o = ie ? inout_io : 1'bz;
65 // input inversion
66 assign in_o = attr_i.invert ^ in_raw_o;
67
68 // pulls are not supported by verilator
69 `ifndef VERILATOR
70 // pullup / pulldown termination
71 assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72 `endif
73 end else if (PadType == BidirTol ||
74 PadType == DualBidirTol ||
75 PadType == BidirOd ||
76 PadType == BidirStd) begin : gen_bidir
77
78 1/1 assign in_raw_o = ie ? inout_io : 1'bz;
Tests: T2 T25 T7
79 // input inversion
80 1/1 assign in_o = attr_i.invert ^ in_raw_o;
Tests: T2 T25 T7
81
82 // virtual open drain emulation
83 logic oe, out;
84 1/1 assign out = out_i ^ attr_i.invert;
Tests: T2 T25 T8
85 1/1 assign oe = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
Tests: T2 T25 T8
86
87 // drive strength attributes are not supported by verilator
88 `ifdef VERILATOR
89 assign inout_io = (oe) ? out : 1'bz;
90 `else
91 // different driver types
92 1/1 assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
Tests: T1 T2 T3
93 1/1 assign (pull0, pull1) inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
Tests: T1 T2 T3
94 // pullup / pulldown termination
95 1/1 assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
Tests: T7 T8 T19
Line Coverage for Module :
prim_generic_pad_wrapper ( parameter PadType=4,ScanRole=0 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 2 | 66.67 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 51 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 102 | 0 | 0 | |
| CONT_ASSIGN | 114 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 115 | 1 | 1 | 100.00 |
38 logic unused_sigs;
39 unreachable assign unused_sigs = ^{attr_i.slew_rate,
40 attr_i.drive_strength[3:1],
41 attr_i.od_en,
42 attr_i.schmitt_en,
43 attr_i.keep_en,
44 scanmode_i,
45 pok_i};
46 //VCS coverage on
47 // pragma coverage on
48
49 // Input enable (active-high)
50 logic ie;
51 0/1 ==> assign ie = ie_i & ~attr_i.input_disable;
52
53 if (PadType == InputStd) begin : gen_input_only
54 //VCS coverage off
55 // pragma coverage off
56 logic unused_in_sigs;
57 assign unused_in_sigs = ^{out_i,
58 oe_i,
59 attr_i.virt_od_en,
60 attr_i.drive_strength};
61 //VCS coverage on
62 // pragma coverage on
63
64 assign in_raw_o = ie ? inout_io : 1'bz;
65 // input inversion
66 assign in_o = attr_i.invert ^ in_raw_o;
67
68 // pulls are not supported by verilator
69 `ifndef VERILATOR
70 // pullup / pulldown termination
71 assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72 `endif
73 end else if (PadType == BidirTol ||
74 PadType == DualBidirTol ||
75 PadType == BidirOd ||
76 PadType == BidirStd) begin : gen_bidir
77
78 assign in_raw_o = ie ? inout_io : 1'bz;
79 // input inversion
80 assign in_o = attr_i.invert ^ in_raw_o;
81
82 // virtual open drain emulation
83 logic oe, out;
84 assign out = out_i ^ attr_i.invert;
85 assign oe = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
86
87 // drive strength attributes are not supported by verilator
88 `ifdef VERILATOR
89 assign inout_io = (oe) ? out : 1'bz;
90 `else
91 // different driver types
92 assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
93 assign (pull0, pull1) inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
94 // pullup / pulldown termination
95 assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
96 `endif
97 end else if (PadType == AnalogIn0 || PadType == AnalogIn1) begin : gen_analog
98
99 //VCS coverage off
100 // pragma coverage off
101 logic unused_ana_sigs;
102 unreachable assign unused_ana_sigs = ^{attr_i.invert,
103 attr_i.virt_od_en,
104 attr_i.drive_strength[0],
105 attr_i.pull_en,
106 attr_i.pull_select,
107 out_i,
108 oe_i,
109 ie_i};
110 //VCS coverage on
111 // pragma coverage on
112
113 assign inout_io = 1'bz; // explicitly make this tristate to avoid lint errors.
114 1/1 assign in_raw_o = ie ? inout_io : 1'bz;
Tests: T2 T25 T46
115 1/1 assign in_o = in_raw_o;
Tests: T2 T25 T46
Cond Coverage for Module :
prim_generic_pad_wrapper ( parameter PadType=3,ScanRole )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 10 | 10 | 100.00 |
| Logical | 10 | 10 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T14,T15,T16 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 64
EXPRESSION (ie ? inout_io : 1'bz)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T14,T15,T16 |
| 1 | Covered | T1,T2,T3 |
LINE 66
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T14,T15,T16 |
| 1 | 1 | Covered | T14,T15,T16 |
LINE 71
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Cond Coverage for Module :
prim_generic_pad_wrapper ( parameter PadType=4,ScanRole=0 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 4 | 2 | 50.00 |
| Logical | 4 | 2 | 50.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 114
EXPRESSION (ie ? inout_io : 1'bz)
-1
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Covered | T1,T2,T3 |
Cond Coverage for Module :
prim_generic_pad_wrapper ( parameter PadType=0,ScanRole=0 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 33 | 33 | 100.00 |
| Logical | 33 | 33 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T14,T15,T16 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 78
EXPRESSION (ie ? inout_io : 1'bz)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T14,T15,T16 |
| 1 | Covered | T1,T2,T3 |
LINE 80
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T14,T15,T16 |
| 1 | 1 | Covered | T14,T15,T16 |
LINE 84
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T14,T15,T16 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T14,T15,T16 |
LINE 85
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T11,T12,T13 |
| 1 | 1 | Covered | T25,T8,T9 |
LINE 85
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T11,T12,T13 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T11,T12,T13 |
LINE 85
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T11,T12,T13 |
| 1 | 1 | Covered | T11,T12,T13 |
LINE 92
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T25,T8,T9 |
LINE 92
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T25,T26 |
| 1 | 1 | Covered | T25,T8,T9 |
LINE 93
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T25,T26 |
LINE 93
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T25,T8,T9 |
| 1 | 1 | Covered | T1,T25,T26 |
LINE 95
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T19 |
Branch Coverage for Module :
prim_generic_pad_wrapper ( parameter PadType=3,ScanRole )
Branch Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
| Branches |
|
4 |
4 |
100.00 |
| TERNARY |
64 |
2 |
2 |
100.00 |
| TERNARY |
71 |
2 |
2 |
100.00 |
64 assign in_raw_o = ie ? inout_io : 1'bz;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T14,T15,T16 |
71 assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Branch Coverage for Module :
prim_generic_pad_wrapper ( parameter PadType=0,ScanRole=0 )
Branch Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
| Branches |
|
8 |
8 |
100.00 |
| TERNARY |
78 |
2 |
2 |
100.00 |
| TERNARY |
92 |
2 |
2 |
100.00 |
| TERNARY |
93 |
2 |
2 |
100.00 |
| TERNARY |
95 |
2 |
2 |
100.00 |
78 assign in_raw_o = ie ? inout_io : 1'bz;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T14,T15,T16 |
92 assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T25,T8,T9 |
| 0 |
Covered |
T1,T2,T3 |
93 assign (pull0, pull1) inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T25,T26 |
| 0 |
Covered |
T1,T2,T3 |
95 assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T7,T8,T19 |
| 0 |
Covered |
T1,T2,T3 |
Branch Coverage for Module :
prim_generic_pad_wrapper ( parameter PadType=4,ScanRole=0 )
Branch Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
1 |
50.00 |
| TERNARY |
114 |
2 |
1 |
50.00 |
114 assign in_raw_o = ie ? inout_io : 1'bz;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Not Covered |
|
Assert Coverage for Module :
prim_generic_pad_wrapper
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
70490 |
70490 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
70490 |
70490 |
0 |
0 |
| T1 |
70 |
70 |
0 |
0 |
| T2 |
70 |
70 |
0 |
0 |
| T3 |
70 |
70 |
0 |
0 |
| T4 |
70 |
70 |
0 |
0 |
| T7 |
70 |
70 |
0 |
0 |
| T25 |
70 |
70 |
0 |
0 |
| T46 |
70 |
70 |
0 |
0 |
| T99 |
70 |
70 |
0 |
0 |
| T100 |
70 |
70 |
0 |
0 |
| T101 |
70 |
70 |
0 |
0 |
