Unified Coverage Report :: Module Instance :: tb.dut.u_padring.gen_dio_pads[22].u_dio_pad.gen_generic.u_impl_generic

Module Instance : tb.dut.u_padring.gen_dio_pads[22].u_dio_pad.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_dio_pads[22].u_dio_pad

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_padring.gen_mio_pads[0].u_mio_pad.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[0].u_mio_pad

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_padring.gen_mio_pads[1].u_mio_pad.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[1].u_mio_pad

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_padring.gen_mio_pads[2].u_mio_pad.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[2].u_mio_pad

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_padring.gen_mio_pads[3].u_mio_pad.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[3].u_mio_pad

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_padring.gen_mio_pads[4].u_mio_pad.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[4].u_mio_pad

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_padring.gen_mio_pads[5].u_mio_pad.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[5].u_mio_pad

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_padring.gen_mio_pads[6].u_mio_pad.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[6].u_mio_pad

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_padring.gen_mio_pads[7].u_mio_pad.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[7].u_mio_pad

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_padring.gen_mio_pads[8].u_mio_pad.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[8].u_mio_pad

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_padring.gen_mio_pads[9].u_mio_pad.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[9].u_mio_pad

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_padring.gen_mio_pads[10].u_mio_pad.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[10].u_mio_pad

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_padring.gen_mio_pads[11].u_mio_pad.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[11].u_mio_pad

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_padring.gen_mio_pads[12].u_mio_pad.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[12].u_mio_pad

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_padring.gen_mio_pads[13].u_mio_pad.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[13].u_mio_pad

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_padring.gen_mio_pads[14].u_mio_pad.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[14].u_mio_pad

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_padring.gen_mio_pads[15].u_mio_pad.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[15].u_mio_pad

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_padring.gen_mio_pads[16].u_mio_pad.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[16].u_mio_pad

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_padring.gen_mio_pads[17].u_mio_pad.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[17].u_mio_pad

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_padring.gen_mio_pads[18].u_mio_pad.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[18].u_mio_pad

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_padring.gen_mio_pads[19].u_mio_pad.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[19].u_mio_pad

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_padring.gen_mio_pads[20].u_mio_pad.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[20].u_mio_pad

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[22].u_dio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	95	1	1	100.00

38                        logic unused_sigs;
39         unreachable    assign unused_sigs = ^{attr_i.slew_rate,
40                                               attr_i.drive_strength[3:1],
41                                               attr_i.od_en,
42                                               attr_i.schmitt_en,
43                                               attr_i.keep_en,
44                                               scanmode_i,
45                                               pok_i};
46                        //VCS coverage on
47                        // pragma coverage on
48                      
49                        // Input enable (active-high)
50                        logic ie;
51         1/1            assign ie = ie_i & ~attr_i.input_disable;
           Tests:       T14 T15 T16 
52                      
53                        if (PadType == InputStd) begin : gen_input_only
54                          //VCS coverage off
55                          // pragma coverage off
56                          logic unused_in_sigs;
57                          assign unused_in_sigs = ^{out_i,
58                                                    oe_i,
59                                                    attr_i.virt_od_en,
60                                                    attr_i.drive_strength};
61                          //VCS coverage on
62                          // pragma coverage on
63                      
64                          assign in_raw_o = ie ? inout_io : 1'bz;
65                          // input inversion
66                          assign in_o = attr_i.invert ^ in_raw_o;
67                      
68                        // pulls are not supported by verilator
69                        `ifndef VERILATOR
70                          // pullup / pulldown termination
71                          assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72                        `endif
73                        end else if (PadType == BidirTol ||
74                                     PadType == DualBidirTol ||
75                                     PadType == BidirOd ||
76                                     PadType == BidirStd) begin : gen_bidir
77                      
78         1/1              assign in_raw_o = ie ? inout_io : 1'bz;
           Tests:       T25 T4 T42 
79                          // input inversion
80         1/1              assign in_o = attr_i.invert ^ in_raw_o;
           Tests:       T25 T4 T42 
81                      
82                          // virtual open drain emulation
83                          logic oe, out;
84         1/1              assign out = out_i ^ attr_i.invert;
           Tests:       T11 T45 T54 
85         1/1              assign oe  = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
           Tests:       T25 T4 T11 
86                      
87                        // drive strength attributes are not supported by verilator
88                        `ifdef VERILATOR
89                          assign inout_io = (oe)   ? out : 1'bz;
90                        `else
91                          // different driver types
92         1/1              assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T25 T4 T11 
93         1/1              assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T25 T4 T11 
94                          // pullup / pulldown termination
95         1/1              assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
           Tests:       T14 T15 T16 

---

Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[22].u_dio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T14,T15,T16
1	1	Covered	T1,T2,T3

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1

-1-	Status	Tests
0	Covered	T14,T15,T16
1	Covered	T1,T2,T3

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T25,T4,T42
1	0	Covered	T14,T15,T16
1	1	Covered	T14,T15,T16

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T16
1	0	Covered	T11,T45,T54
1	1	Covered	T14,T15,T16

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T25,T4,T57
1	0	Covered	T11,T12,T13
1	1	Covered	T1,T2,T3

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T11,T12,T13
0	1	Covered	T1,T2,T3
1	0	Covered	T11,T12,T13

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T11,T12,T13
1	1	Covered	T11,T12,T13

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T14,T15,T16

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T14,T15,T16

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T25,T4,T11
1	Covered	T1,T2,T3

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T25,T4,T11
1	0	Covered	T14,T15,T16
1	1	Covered	T1,T2,T3

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T14,T15,T16

---

Branch Coverage for Instance : tb.dut.u_padring.gen_dio_pads[22].u_dio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	78	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	93	2	2	100.00
TERNARY	95	2	2	100.00

78             assign in_raw_o = ie ? inout_io : 1'bz;
                                    -1-  
                                    ==>  
                                    ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T14,T15,T16

92             assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                     -1-  
                                                                                     ==>  
                                                                                     ==>  

Branches:

-1-	Status	Tests
1	Covered	T14,T15,T16
0	Covered	T1,T2,T3

93             assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                      -1-  
                                                                                      ==>  
                                                                                      ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T25,T4,T11

95             assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
                                                                   -1-  
                                                                   ==>  
                                                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T14,T15,T16
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[22].u_dio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	1007	1007	0	0

AnalogNoScan_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1007	1007	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T25	1	1	0	0
T46	1	1	0	0
T99	1	1	0	0
T100	1	1	0	0
T101	1	1	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[0].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	95	1	1	100.00

38                        logic unused_sigs;
39         unreachable    assign unused_sigs = ^{attr_i.slew_rate,
40                                               attr_i.drive_strength[3:1],
41                                               attr_i.od_en,
42                                               attr_i.schmitt_en,
43                                               attr_i.keep_en,
44                                               scanmode_i,
45                                               pok_i};
46                        //VCS coverage on
47                        // pragma coverage on
48                      
49                        // Input enable (active-high)
50                        logic ie;
51         1/1            assign ie = ie_i & ~attr_i.input_disable;
           Tests:       T14 T15 T16 
52                      
53                        if (PadType == InputStd) begin : gen_input_only
54                          //VCS coverage off
55                          // pragma coverage off
56                          logic unused_in_sigs;
57                          assign unused_in_sigs = ^{out_i,
58                                                    oe_i,
59                                                    attr_i.virt_od_en,
60                                                    attr_i.drive_strength};
61                          //VCS coverage on
62                          // pragma coverage on
63                      
64                          assign in_raw_o = ie ? inout_io : 1'bz;
65                          // input inversion
66                          assign in_o = attr_i.invert ^ in_raw_o;
67                      
68                        // pulls are not supported by verilator
69                        `ifndef VERILATOR
70                          // pullup / pulldown termination
71                          assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72                        `endif
73                        end else if (PadType == BidirTol ||
74                                     PadType == DualBidirTol ||
75                                     PadType == BidirOd ||
76                                     PadType == BidirStd) begin : gen_bidir
77                      
78         1/1              assign in_raw_o = ie ? inout_io : 1'bz;
           Tests:       T25 T7 T6 
79                          // input inversion
80         1/1              assign in_o = attr_i.invert ^ in_raw_o;
           Tests:       T25 T7 T6 
81                      
82                          // virtual open drain emulation
83                          logic oe, out;
84         1/1              assign out = out_i ^ attr_i.invert;
           Tests:       T25 T6 T28 
85         1/1              assign oe  = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
           Tests:       T25 T6 T28 
86                      
87                        // drive strength attributes are not supported by verilator
88                        `ifdef VERILATOR
89                          assign inout_io = (oe)   ? out : 1'bz;
90                        `else
91                          // different driver types
92         1/1              assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T25 T7 T6 
93         1/1              assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T25 T7 T6 
94                          // pullup / pulldown termination
95         1/1              assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
           Tests:       T7 T17 T18 

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[0].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T14,T15,T16
1	1	Covered	T1,T2,T3

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1

-1-	Status	Tests
0	Covered	T14,T15,T16
1	Covered	T1,T2,T3

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T28,T39
0	1	Covered	T25,T7,T6
1	0	Covered	T14,T15,T16
1	1	Covered	T14,T15,T16

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T16
1	0	Covered	T25,T6,T28
1	1	Covered	T14,T15,T16

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T15,T16
1	1	Covered	T25,T6,T28

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T15,T16

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T15,T16
1	1	Covered	T14,T15,T16

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T14,T15,T16

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T17,T18
1	0	Covered	T25,T6,T28
1	1	Covered	T14,T15,T16

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T25,T6,T28

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T15,T16
1	1	Covered	T25,T6,T28

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T17,T18

---

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[0].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	78	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	93	2	2	100.00
TERNARY	95	2	2	100.00

78             assign in_raw_o = ie ? inout_io : 1'bz;
                                    -1-  
                                    ==>  
                                    ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T14,T15,T16

92             assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                     -1-  
                                                                                     ==>  
                                                                                     ==>  

Branches:

-1-	Status	Tests
1	Covered	T14,T15,T16
0	Covered	T1,T2,T3

93             assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                      -1-  
                                                                                      ==>  
                                                                                      ==>  

Branches:

-1-	Status	Tests
1	Covered	T25,T6,T28
0	Covered	T1,T2,T3

95             assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
                                                                   -1-  
                                                                   ==>  
                                                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T7,T17,T18
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[0].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	1007	1007	0	0

AnalogNoScan_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1007	1007	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T25	1	1	0	0
T46	1	1	0	0
T99	1	1	0	0
T100	1	1	0	0
T101	1	1	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[1].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	95	1	1	100.00

38                        logic unused_sigs;
39         unreachable    assign unused_sigs = ^{attr_i.slew_rate,
40                                               attr_i.drive_strength[3:1],
41                                               attr_i.od_en,
42                                               attr_i.schmitt_en,
43                                               attr_i.keep_en,
44                                               scanmode_i,
45                                               pok_i};
46                        //VCS coverage on
47                        // pragma coverage on
48                      
49                        // Input enable (active-high)
50                        logic ie;
51         1/1            assign ie = ie_i & ~attr_i.input_disable;
           Tests:       T14 T15 T16 
52                      
53                        if (PadType == InputStd) begin : gen_input_only
54                          //VCS coverage off
55                          // pragma coverage off
56                          logic unused_in_sigs;
57                          assign unused_in_sigs = ^{out_i,
58                                                    oe_i,
59                                                    attr_i.virt_od_en,
60                                                    attr_i.drive_strength};
61                          //VCS coverage on
62                          // pragma coverage on
63                      
64                          assign in_raw_o = ie ? inout_io : 1'bz;
65                          // input inversion
66                          assign in_o = attr_i.invert ^ in_raw_o;
67                      
68                        // pulls are not supported by verilator
69                        `ifndef VERILATOR
70                          // pullup / pulldown termination
71                          assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72                        `endif
73                        end else if (PadType == BidirTol ||
74                                     PadType == DualBidirTol ||
75                                     PadType == BidirOd ||
76                                     PadType == BidirStd) begin : gen_bidir
77                      
78         1/1              assign in_raw_o = ie ? inout_io : 1'bz;
           Tests:       T25 T6 T28 
79                          // input inversion
80         1/1              assign in_o = attr_i.invert ^ in_raw_o;
           Tests:       T25 T6 T28 
81                      
82                          // virtual open drain emulation
83                          logic oe, out;
84         1/1              assign out = out_i ^ attr_i.invert;
           Tests:       T6 T28 T39 
85         1/1              assign oe  = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
           Tests:       T25 T6 T28 
86                      
87                        // drive strength attributes are not supported by verilator
88                        `ifdef VERILATOR
89                          assign inout_io = (oe)   ? out : 1'bz;
90                        `else
91                          // different driver types
92         1/1              assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T25 T6 T28 
93         1/1              assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T25 T6 T28 
94                          // pullup / pulldown termination
95         1/1              assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
           Tests:       T14 T15 T16 

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[1].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T14,T15,T16
1	1	Covered	T1,T2,T3

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1

-1-	Status	Tests
0	Covered	T14,T15,T16
1	Covered	T1,T2,T3

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T25,T6,T28
0	1	Covered	T6,T28,T39
1	0	Covered	T14,T15,T16
1	1	Covered	T14,T15,T16

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T16
1	0	Covered	T6,T28,T39
1	1	Covered	T14,T15,T16

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T15,T16,T206
1	1	Covered	T25,T6,T28

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T15,T16

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T15,T16
1	1	Covered	T14,T15,T16

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T14,T15,T16

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T25,T6,T28
1	1	Covered	T14,T15,T16

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T25,T6,T28

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T15,T16
1	1	Covered	T25,T6,T28

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T14,T15,T16

---

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[1].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	78	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	93	2	2	100.00
TERNARY	95	2	2	100.00

78             assign in_raw_o = ie ? inout_io : 1'bz;
                                    -1-  
                                    ==>  
                                    ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T14,T15,T16

92             assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                     -1-  
                                                                                     ==>  
                                                                                     ==>  

Branches:

-1-	Status	Tests
1	Covered	T14,T15,T16
0	Covered	T1,T2,T3

93             assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                      -1-  
                                                                                      ==>  
                                                                                      ==>  

Branches:

-1-	Status	Tests
1	Covered	T25,T6,T28
0	Covered	T1,T2,T3

95             assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
                                                                   -1-  
                                                                   ==>  
                                                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T14,T15,T16
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[1].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	1007	1007	0	0

AnalogNoScan_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1007	1007	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T25	1	1	0	0
T46	1	1	0	0
T99	1	1	0	0
T100	1	1	0	0
T101	1	1	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[2].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	95	1	1	100.00

38                        logic unused_sigs;
39         unreachable    assign unused_sigs = ^{attr_i.slew_rate,
40                                               attr_i.drive_strength[3:1],
41                                               attr_i.od_en,
42                                               attr_i.schmitt_en,
43                                               attr_i.keep_en,
44                                               scanmode_i,
45                                               pok_i};
46                        //VCS coverage on
47                        // pragma coverage on
48                      
49                        // Input enable (active-high)
50                        logic ie;
51         1/1            assign ie = ie_i & ~attr_i.input_disable;
           Tests:       T14 T15 T16 
52                      
53                        if (PadType == InputStd) begin : gen_input_only
54                          //VCS coverage off
55                          // pragma coverage off
56                          logic unused_in_sigs;
57                          assign unused_in_sigs = ^{out_i,
58                                                    oe_i,
59                                                    attr_i.virt_od_en,
60                                                    attr_i.drive_strength};
61                          //VCS coverage on
62                          // pragma coverage on
63                      
64                          assign in_raw_o = ie ? inout_io : 1'bz;
65                          // input inversion
66                          assign in_o = attr_i.invert ^ in_raw_o;
67                      
68                        // pulls are not supported by verilator
69                        `ifndef VERILATOR
70                          // pullup / pulldown termination
71                          assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72                        `endif
73                        end else if (PadType == BidirTol ||
74                                     PadType == DualBidirTol ||
75                                     PadType == BidirOd ||
76                                     PadType == BidirStd) begin : gen_bidir
77                      
78         1/1              assign in_raw_o = ie ? inout_io : 1'bz;
           Tests:       T25 T6 T28 
79                          // input inversion
80         1/1              assign in_o = attr_i.invert ^ in_raw_o;
           Tests:       T25 T6 T28 
81                      
82                          // virtual open drain emulation
83                          logic oe, out;
84         1/1              assign out = out_i ^ attr_i.invert;
           Tests:       T6 T28 T52 
85         1/1              assign oe  = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
           Tests:       T25 T6 T28 
86                      
87                        // drive strength attributes are not supported by verilator
88                        `ifdef VERILATOR
89                          assign inout_io = (oe)   ? out : 1'bz;
90                        `else
91                          // different driver types
92         1/1              assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T25 T6 T28 
93         1/1              assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T25 T6 T28 
94                          // pullup / pulldown termination
95         1/1              assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
           Tests:       T14 T15 T16 

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[2].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T14,T15,T16
1	1	Covered	T1,T2,T3

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1

-1-	Status	Tests
0	Covered	T14,T15,T16
1	Covered	T1,T2,T3

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T25,T6,T28
0	1	Covered	T6,T28,T52
1	0	Covered	T14,T15,T16
1	1	Covered	T14,T15,T16

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T16
1	0	Covered	T6,T28,T52
1	1	Covered	T14,T15,T16

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T15,T16
1	1	Covered	T25,T6,T28

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T15,T16

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T15,T16
1	1	Covered	T14,T15,T16

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T14,T15,T16

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T25,T6,T28
1	1	Covered	T14,T15,T16

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T25,T6,T28

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T15,T16
1	1	Covered	T25,T6,T28

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T14,T15,T16

---

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[2].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	78	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	93	2	2	100.00
TERNARY	95	2	2	100.00

78             assign in_raw_o = ie ? inout_io : 1'bz;
                                    -1-  
                                    ==>  
                                    ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T14,T15,T16

92             assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                     -1-  
                                                                                     ==>  
                                                                                     ==>  

Branches:

-1-	Status	Tests
1	Covered	T14,T15,T16
0	Covered	T1,T2,T3

93             assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                      -1-  
                                                                                      ==>  
                                                                                      ==>  

Branches:

-1-	Status	Tests
1	Covered	T25,T6,T28
0	Covered	T1,T2,T3

95             assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
                                                                   -1-  
                                                                   ==>  
                                                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T14,T15,T16
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[2].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	1007	1007	0	0

AnalogNoScan_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1007	1007	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T25	1	1	0	0
T46	1	1	0	0
T99	1	1	0	0
T100	1	1	0	0
T101	1	1	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[3].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	95	1	1	100.00

38                        logic unused_sigs;
39         unreachable    assign unused_sigs = ^{attr_i.slew_rate,
40                                               attr_i.drive_strength[3:1],
41                                               attr_i.od_en,
42                                               attr_i.schmitt_en,
43                                               attr_i.keep_en,
44                                               scanmode_i,
45                                               pok_i};
46                        //VCS coverage on
47                        // pragma coverage on
48                      
49                        // Input enable (active-high)
50                        logic ie;
51         1/1            assign ie = ie_i & ~attr_i.input_disable;
           Tests:       T14 T15 T16 
52                      
53                        if (PadType == InputStd) begin : gen_input_only
54                          //VCS coverage off
55                          // pragma coverage off
56                          logic unused_in_sigs;
57                          assign unused_in_sigs = ^{out_i,
58                                                    oe_i,
59                                                    attr_i.virt_od_en,
60                                                    attr_i.drive_strength};
61                          //VCS coverage on
62                          // pragma coverage on
63                      
64                          assign in_raw_o = ie ? inout_io : 1'bz;
65                          // input inversion
66                          assign in_o = attr_i.invert ^ in_raw_o;
67                      
68                        // pulls are not supported by verilator
69                        `ifndef VERILATOR
70                          // pullup / pulldown termination
71                          assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72                        `endif
73                        end else if (PadType == BidirTol ||
74                                     PadType == DualBidirTol ||
75                                     PadType == BidirOd ||
76                                     PadType == BidirStd) begin : gen_bidir
77                      
78         1/1              assign in_raw_o = ie ? inout_io : 1'bz;
           Tests:       T25 T6 T28 
79                          // input inversion
80         1/1              assign in_o = attr_i.invert ^ in_raw_o;
           Tests:       T25 T6 T28 
81                      
82                          // virtual open drain emulation
83                          logic oe, out;
84         1/1              assign out = out_i ^ attr_i.invert;
           Tests:       T6 T28 T29 
85         1/1              assign oe  = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
           Tests:       T6 T28 T29 
86                      
87                        // drive strength attributes are not supported by verilator
88                        `ifdef VERILATOR
89                          assign inout_io = (oe)   ? out : 1'bz;
90                        `else
91                          // different driver types
92         1/1              assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T6 T28 T29 
93         1/1              assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T6 T28 T29 
94                          // pullup / pulldown termination
95         1/1              assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
           Tests:       T14 T15 T16 

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[3].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T14,T15,T16
1	1	Covered	T1,T2,T3

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1

-1-	Status	Tests
0	Covered	T14,T15,T16
1	Covered	T1,T2,T3

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T25,T6,T28
0	1	Covered	T25,T6,T28
1	0	Covered	T14,T15,T16
1	1	Covered	T14,T15,T16

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T16
1	0	Covered	T6,T28,T29
1	1	Covered	T14,T15,T16

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T15,T16
1	1	Covered	T6,T28,T29

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T15,T16

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T15,T16
1	1	Covered	T14,T15,T16

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T14,T15,T16

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T6,T28,T29
1	1	Covered	T14,T15,T16

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T28,T29

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T15,T16
1	1	Covered	T6,T28,T29

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T14,T15,T16

---

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[3].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	78	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	93	2	2	100.00
TERNARY	95	2	2	100.00

78             assign in_raw_o = ie ? inout_io : 1'bz;
                                    -1-  
                                    ==>  
                                    ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T14,T15,T16

92             assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                     -1-  
                                                                                     ==>  
                                                                                     ==>  

Branches:

-1-	Status	Tests
1	Covered	T14,T15,T16
0	Covered	T1,T2,T3

93             assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                      -1-  
                                                                                      ==>  
                                                                                      ==>  

Branches:

-1-	Status	Tests
1	Covered	T6,T28,T29
0	Covered	T1,T2,T3

95             assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
                                                                   -1-  
                                                                   ==>  
                                                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T14,T15,T16
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[3].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	1007	1007	0	0

AnalogNoScan_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1007	1007	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T25	1	1	0	0
T46	1	1	0	0
T99	1	1	0	0
T100	1	1	0	0
T101	1	1	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[4].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	95	1	1	100.00

38                        logic unused_sigs;
39         unreachable    assign unused_sigs = ^{attr_i.slew_rate,
40                                               attr_i.drive_strength[3:1],
41                                               attr_i.od_en,
42                                               attr_i.schmitt_en,
43                                               attr_i.keep_en,
44                                               scanmode_i,
45                                               pok_i};
46                        //VCS coverage on
47                        // pragma coverage on
48                      
49                        // Input enable (active-high)
50                        logic ie;
51         1/1            assign ie = ie_i & ~attr_i.input_disable;
           Tests:       T14 T15 T16 
52                      
53                        if (PadType == InputStd) begin : gen_input_only
54                          //VCS coverage off
55                          // pragma coverage off
56                          logic unused_in_sigs;
57                          assign unused_in_sigs = ^{out_i,
58                                                    oe_i,
59                                                    attr_i.virt_od_en,
60                                                    attr_i.drive_strength};
61                          //VCS coverage on
62                          // pragma coverage on
63                      
64                          assign in_raw_o = ie ? inout_io : 1'bz;
65                          // input inversion
66                          assign in_o = attr_i.invert ^ in_raw_o;
67                      
68                        // pulls are not supported by verilator
69                        `ifndef VERILATOR
70                          // pullup / pulldown termination
71                          assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72                        `endif
73                        end else if (PadType == BidirTol ||
74                                     PadType == DualBidirTol ||
75                                     PadType == BidirOd ||
76                                     PadType == BidirStd) begin : gen_bidir
77                      
78         1/1              assign in_raw_o = ie ? inout_io : 1'bz;
           Tests:       T25 T6 T28 
79                          // input inversion
80         1/1              assign in_o = attr_i.invert ^ in_raw_o;
           Tests:       T25 T6 T28 
81                      
82                          // virtual open drain emulation
83                          logic oe, out;
84         1/1              assign out = out_i ^ attr_i.invert;
           Tests:       T6 T28 T29 
85         1/1              assign oe  = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
           Tests:       T6 T28 T29 
86                      
87                        // drive strength attributes are not supported by verilator
88                        `ifdef VERILATOR
89                          assign inout_io = (oe)   ? out : 1'bz;
90                        `else
91                          // different driver types
92         1/1              assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T6 T28 T29 
93         1/1              assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T6 T28 T29 
94                          // pullup / pulldown termination
95         1/1              assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
           Tests:       T14 T15 T16 

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[4].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T14,T15,T16
1	1	Covered	T1,T2,T3

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1

-1-	Status	Tests
0	Covered	T14,T15,T16
1	Covered	T1,T2,T3

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T25,T6,T28
0	1	Covered	T25,T6,T28
1	0	Covered	T14,T15,T16
1	1	Covered	T14,T15,T16

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T16
1	0	Covered	T6,T28,T29
1	1	Covered	T14,T15,T16

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T15,T16
1	1	Covered	T6,T28,T29

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T15,T16

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T15,T16
1	1	Covered	T14,T15,T16

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T14,T15,T16

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T6,T28,T29
1	1	Covered	T14,T15,T16

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T28,T29

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T15,T16
1	1	Covered	T6,T28,T29

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T14,T15,T16

---

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[4].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	78	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	93	2	2	100.00
TERNARY	95	2	2	100.00

78             assign in_raw_o = ie ? inout_io : 1'bz;
                                    -1-  
                                    ==>  
                                    ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T14,T15,T16

92             assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                     -1-  
                                                                                     ==>  
                                                                                     ==>  

Branches:

-1-	Status	Tests
1	Covered	T14,T15,T16
0	Covered	T1,T2,T3

93             assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                      -1-  
                                                                                      ==>  
                                                                                      ==>  

Branches:

-1-	Status	Tests
1	Covered	T6,T28,T29
0	Covered	T1,T2,T3

95             assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
                                                                   -1-  
                                                                   ==>  
                                                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T14,T15,T16
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[4].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	1007	1007	0	0

AnalogNoScan_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1007	1007	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T25	1	1	0	0
T46	1	1	0	0
T99	1	1	0	0
T100	1	1	0	0
T101	1	1	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[5].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	95	1	1	100.00

38                        logic unused_sigs;
39         unreachable    assign unused_sigs = ^{attr_i.slew_rate,
40                                               attr_i.drive_strength[3:1],
41                                               attr_i.od_en,
42                                               attr_i.schmitt_en,
43                                               attr_i.keep_en,
44                                               scanmode_i,
45                                               pok_i};
46                        //VCS coverage on
47                        // pragma coverage on
48                      
49                        // Input enable (active-high)
50                        logic ie;
51         1/1            assign ie = ie_i & ~attr_i.input_disable;
           Tests:       T14 T15 T16 
52                      
53                        if (PadType == InputStd) begin : gen_input_only
54                          //VCS coverage off
55                          // pragma coverage off
56                          logic unused_in_sigs;
57                          assign unused_in_sigs = ^{out_i,
58                                                    oe_i,
59                                                    attr_i.virt_od_en,
60                                                    attr_i.drive_strength};
61                          //VCS coverage on
62                          // pragma coverage on
63                      
64                          assign in_raw_o = ie ? inout_io : 1'bz;
65                          // input inversion
66                          assign in_o = attr_i.invert ^ in_raw_o;
67                      
68                        // pulls are not supported by verilator
69                        `ifndef VERILATOR
70                          // pullup / pulldown termination
71                          assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72                        `endif
73                        end else if (PadType == BidirTol ||
74                                     PadType == DualBidirTol ||
75                                     PadType == BidirOd ||
76                                     PadType == BidirStd) begin : gen_bidir
77                      
78         1/1              assign in_raw_o = ie ? inout_io : 1'bz;
           Tests:       T25 T6 T28 
79                          // input inversion
80         1/1              assign in_o = attr_i.invert ^ in_raw_o;
           Tests:       T25 T6 T28 
81                      
82                          // virtual open drain emulation
83                          logic oe, out;
84         1/1              assign out = out_i ^ attr_i.invert;
           Tests:       T25 T6 T28 
85         1/1              assign oe  = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
           Tests:       T25 T6 T28 
86                      
87                        // drive strength attributes are not supported by verilator
88                        `ifdef VERILATOR
89                          assign inout_io = (oe)   ? out : 1'bz;
90                        `else
91                          // different driver types
92         1/1              assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T25 T6 T28 
93         1/1              assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T25 T6 T28 
94                          // pullup / pulldown termination
95         1/1              assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
           Tests:       T14 T15 T16 

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[5].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T14,T15,T16
1	1	Covered	T1,T2,T3

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1

-1-	Status	Tests
0	Covered	T14,T15,T16
1	Covered	T1,T2,T3

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T28,T37
0	1	Covered	T25,T6,T28
1	0	Covered	T14,T15,T16
1	1	Covered	T14,T15,T16

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T16
1	0	Covered	T25,T6,T28
1	1	Covered	T14,T15,T16

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T15,T16
1	1	Covered	T25,T6,T28

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T15,T16

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T15,T16
1	1	Covered	T14,T15,T16

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T14,T15,T16

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T25,T6,T28
1	1	Covered	T14,T15,T16

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T25,T6,T28

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T15,T16
1	1	Covered	T25,T6,T28

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T14,T15,T16

---

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[5].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	78	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	93	2	2	100.00
TERNARY	95	2	2	100.00

78             assign in_raw_o = ie ? inout_io : 1'bz;
                                    -1-  
                                    ==>  
                                    ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T14,T15,T16

92             assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                     -1-  
                                                                                     ==>  
                                                                                     ==>  

Branches:

-1-	Status	Tests
1	Covered	T14,T15,T16
0	Covered	T1,T2,T3

93             assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                      -1-  
                                                                                      ==>  
                                                                                      ==>  

Branches:

-1-	Status	Tests
1	Covered	T25,T6,T28
0	Covered	T1,T2,T3

95             assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
                                                                   -1-  
                                                                   ==>  
                                                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T14,T15,T16
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[5].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	1007	1007	0	0

AnalogNoScan_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1007	1007	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T25	1	1	0	0
T46	1	1	0	0
T99	1	1	0	0
T100	1	1	0	0
T101	1	1	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[6].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	95	1	1	100.00

38                        logic unused_sigs;
39         unreachable    assign unused_sigs = ^{attr_i.slew_rate,
40                                               attr_i.drive_strength[3:1],
41                                               attr_i.od_en,
42                                               attr_i.schmitt_en,
43                                               attr_i.keep_en,
44                                               scanmode_i,
45                                               pok_i};
46                        //VCS coverage on
47                        // pragma coverage on
48                      
49                        // Input enable (active-high)
50                        logic ie;
51         1/1            assign ie = ie_i & ~attr_i.input_disable;
           Tests:       T14 T15 T16 
52                      
53                        if (PadType == InputStd) begin : gen_input_only
54                          //VCS coverage off
55                          // pragma coverage off
56                          logic unused_in_sigs;
57                          assign unused_in_sigs = ^{out_i,
58                                                    oe_i,
59                                                    attr_i.virt_od_en,
60                                                    attr_i.drive_strength};
61                          //VCS coverage on
62                          // pragma coverage on
63                      
64                          assign in_raw_o = ie ? inout_io : 1'bz;
65                          // input inversion
66                          assign in_o = attr_i.invert ^ in_raw_o;
67                      
68                        // pulls are not supported by verilator
69                        `ifndef VERILATOR
70                          // pullup / pulldown termination
71                          assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72                        `endif
73                        end else if (PadType == BidirTol ||
74                                     PadType == DualBidirTol ||
75                                     PadType == BidirOd ||
76                                     PadType == BidirStd) begin : gen_bidir
77                      
78         1/1              assign in_raw_o = ie ? inout_io : 1'bz;
           Tests:       T25 T6 T28 
79                          // input inversion
80         1/1              assign in_o = attr_i.invert ^ in_raw_o;
           Tests:       T25 T6 T28 
81                      
82                          // virtual open drain emulation
83                          logic oe, out;
84         1/1              assign out = out_i ^ attr_i.invert;
           Tests:       T25 T6 T28 
85         1/1              assign oe  = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
           Tests:       T25 T6 T28 
86                      
87                        // drive strength attributes are not supported by verilator
88                        `ifdef VERILATOR
89                          assign inout_io = (oe)   ? out : 1'bz;
90                        `else
91                          // different driver types
92         1/1              assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T25 T6 T28 
93         1/1              assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T25 T6 T28 
94                          // pullup / pulldown termination
95         1/1              assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
           Tests:       T14 T15 T16 

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[6].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T14,T15,T16
1	1	Covered	T1,T2,T3

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1

-1-	Status	Tests
0	Covered	T14,T15,T16
1	Covered	T1,T2,T3

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T28,T58
0	1	Covered	T25,T6,T28
1	0	Covered	T14,T15,T16
1	1	Covered	T14,T15,T16

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T16
1	0	Covered	T25,T6,T28
1	1	Covered	T14,T15,T16

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T15,T16
1	1	Covered	T25,T6,T28

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T15,T16

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T15,T16
1	1	Covered	T14,T15,T16

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T14,T15,T16

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T25,T6,T28
1	1	Covered	T14,T15,T16

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T25,T6,T28

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T15,T16
1	1	Covered	T25,T6,T28

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T14,T15,T16

---

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[6].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	78	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	93	2	2	100.00
TERNARY	95	2	2	100.00

78             assign in_raw_o = ie ? inout_io : 1'bz;
                                    -1-  
                                    ==>  
                                    ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T14,T15,T16

92             assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                     -1-  
                                                                                     ==>  
                                                                                     ==>  

Branches:

-1-	Status	Tests
1	Covered	T14,T15,T16
0	Covered	T1,T2,T3

93             assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                      -1-  
                                                                                      ==>  
                                                                                      ==>  

Branches:

-1-	Status	Tests
1	Covered	T25,T6,T28
0	Covered	T1,T2,T3

95             assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
                                                                   -1-  
                                                                   ==>  
                                                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T14,T15,T16
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[6].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	1007	1007	0	0

AnalogNoScan_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1007	1007	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T25	1	1	0	0
T46	1	1	0	0
T99	1	1	0	0
T100	1	1	0	0
T101	1	1	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[7].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	95	1	1	100.00

38                        logic unused_sigs;
39         unreachable    assign unused_sigs = ^{attr_i.slew_rate,
40                                               attr_i.drive_strength[3:1],
41                                               attr_i.od_en,
42                                               attr_i.schmitt_en,
43                                               attr_i.keep_en,
44                                               scanmode_i,
45                                               pok_i};
46                        //VCS coverage on
47                        // pragma coverage on
48                      
49                        // Input enable (active-high)
50                        logic ie;
51         1/1            assign ie = ie_i & ~attr_i.input_disable;
           Tests:       T14 T15 T16 
52                      
53                        if (PadType == InputStd) begin : gen_input_only
54                          //VCS coverage off
55                          // pragma coverage off
56                          logic unused_in_sigs;
57                          assign unused_in_sigs = ^{out_i,
58                                                    oe_i,
59                                                    attr_i.virt_od_en,
60                                                    attr_i.drive_strength};
61                          //VCS coverage on
62                          // pragma coverage on
63                      
64                          assign in_raw_o = ie ? inout_io : 1'bz;
65                          // input inversion
66                          assign in_o = attr_i.invert ^ in_raw_o;
67                      
68                        // pulls are not supported by verilator
69                        `ifndef VERILATOR
70                          // pullup / pulldown termination
71                          assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72                        `endif
73                        end else if (PadType == BidirTol ||
74                                     PadType == DualBidirTol ||
75                                     PadType == BidirOd ||
76                                     PadType == BidirStd) begin : gen_bidir
77                      
78         1/1              assign in_raw_o = ie ? inout_io : 1'bz;
           Tests:       T25 T6 T26 
79                          // input inversion
80         1/1              assign in_o = attr_i.invert ^ in_raw_o;
           Tests:       T25 T6 T26 
81                      
82                          // virtual open drain emulation
83                          logic oe, out;
84         1/1              assign out = out_i ^ attr_i.invert;
           Tests:       T6 T28 T29 
85         1/1              assign oe  = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
           Tests:       T6 T26 T28 
86                      
87                        // drive strength attributes are not supported by verilator
88                        `ifdef VERILATOR
89                          assign inout_io = (oe)   ? out : 1'bz;
90                        `else
91                          // different driver types
92         1/1              assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T6 T26 T28 
93         1/1              assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T6 T26 T28 
94                          // pullup / pulldown termination
95         1/1              assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
           Tests:       T19 T20 T21 

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[7].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T14,T15,T16
1	1	Covered	T1,T2,T3

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1

-1-	Status	Tests
0	Covered	T14,T15,T16
1	Covered	T1,T2,T3

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T25,T6,T26
0	1	Covered	T25,T6,T28
1	0	Covered	T14,T15,T16
1	1	Covered	T14,T15,T16

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T16
1	0	Covered	T6,T28,T29
1	1	Covered	T14,T15,T16

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T15,T16
1	1	Covered	T6,T26,T28

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T15,T16

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T15,T16
1	1	Covered	T14,T15,T16

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T14,T15,T16

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T6,T26,T28
1	1	Covered	T14,T15,T16

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T26,T28

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T15,T16
1	1	Covered	T6,T26,T28

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T19,T20,T21

---

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[7].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	78	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	93	2	2	100.00
TERNARY	95	2	2	100.00

78             assign in_raw_o = ie ? inout_io : 1'bz;
                                    -1-  
                                    ==>  
                                    ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T14,T15,T16

92             assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                     -1-  
                                                                                     ==>  
                                                                                     ==>  

Branches:

-1-	Status	Tests
1	Covered	T14,T15,T16
0	Covered	T1,T2,T3

93             assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                      -1-  
                                                                                      ==>  
                                                                                      ==>  

Branches:

-1-	Status	Tests
1	Covered	T6,T26,T28
0	Covered	T1,T2,T3

95             assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
                                                                   -1-  
                                                                   ==>  
                                                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T19,T20,T21
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[7].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	1007	1007	0	0

AnalogNoScan_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1007	1007	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T25	1	1	0	0
T46	1	1	0	0
T99	1	1	0	0
T100	1	1	0	0
T101	1	1	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[8].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	95	1	1	100.00

38                        logic unused_sigs;
39         unreachable    assign unused_sigs = ^{attr_i.slew_rate,
40                                               attr_i.drive_strength[3:1],
41                                               attr_i.od_en,
42                                               attr_i.schmitt_en,
43                                               attr_i.keep_en,
44                                               scanmode_i,
45                                               pok_i};
46                        //VCS coverage on
47                        // pragma coverage on
48                      
49                        // Input enable (active-high)
50                        logic ie;
51         1/1            assign ie = ie_i & ~attr_i.input_disable;
           Tests:       T14 T15 T16 
52                      
53                        if (PadType == InputStd) begin : gen_input_only
54                          //VCS coverage off
55                          // pragma coverage off
56                          logic unused_in_sigs;
57                          assign unused_in_sigs = ^{out_i,
58                                                    oe_i,
59                                                    attr_i.virt_od_en,
60                                                    attr_i.drive_strength};
61                          //VCS coverage on
62                          // pragma coverage on
63                      
64                          assign in_raw_o = ie ? inout_io : 1'bz;
65                          // input inversion
66                          assign in_o = attr_i.invert ^ in_raw_o;
67                      
68                        // pulls are not supported by verilator
69                        `ifndef VERILATOR
70                          // pullup / pulldown termination
71                          assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72                        `endif
73                        end else if (PadType == BidirTol ||
74                                     PadType == DualBidirTol ||
75                                     PadType == BidirOd ||
76                                     PadType == BidirStd) begin : gen_bidir
77                      
78         1/1              assign in_raw_o = ie ? inout_io : 1'bz;
           Tests:       T25 T6 T26 
79                          // input inversion
80         1/1              assign in_o = attr_i.invert ^ in_raw_o;
           Tests:       T25 T6 T26 
81                      
82                          // virtual open drain emulation
83                          logic oe, out;
84         1/1              assign out = out_i ^ attr_i.invert;
           Tests:       T25 T28 T29 
85         1/1              assign oe  = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
           Tests:       T25 T28 T31 
86                      
87                        // drive strength attributes are not supported by verilator
88                        `ifdef VERILATOR
89                          assign inout_io = (oe)   ? out : 1'bz;
90                        `else
91                          // different driver types
92         1/1              assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T25 T28 T31 
93         1/1              assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T25 T28 T31 
94                          // pullup / pulldown termination
95         1/1              assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
           Tests:       T14 T15 T16 

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[8].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T14,T15,T16
1	1	Covered	T1,T2,T3

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1

-1-	Status	Tests
0	Covered	T14,T15,T16
1	Covered	T1,T2,T3

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T26,T28
0	1	Covered	T25,T6,T26
1	0	Covered	T14,T15,T16
1	1	Covered	T14,T15,T207

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T16
1	0	Covered	T25,T28,T29
1	1	Covered	T14,T15,T16

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T15,T16
1	1	Covered	T25,T28,T31

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T15,T16

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T15,T16
1	1	Covered	T14,T15,T16

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T14,T15,T16

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T25,T28,T31
1	1	Covered	T14,T15,T16

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T25,T28,T31

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T15,T16
1	1	Covered	T25,T28,T31

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T14,T15,T16

---

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[8].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	78	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	93	2	2	100.00
TERNARY	95	2	2	100.00

78             assign in_raw_o = ie ? inout_io : 1'bz;
                                    -1-  
                                    ==>  
                                    ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T14,T15,T16

92             assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                     -1-  
                                                                                     ==>  
                                                                                     ==>  

Branches:

-1-	Status	Tests
1	Covered	T14,T15,T16
0	Covered	T1,T2,T3

93             assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                      -1-  
                                                                                      ==>  
                                                                                      ==>  

Branches:

-1-	Status	Tests
1	Covered	T25,T28,T31
0	Covered	T1,T2,T3

95             assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
                                                                   -1-  
                                                                   ==>  
                                                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T14,T15,T16
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[8].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	1007	1007	0	0

AnalogNoScan_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1007	1007	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T25	1	1	0	0
T46	1	1	0	0
T99	1	1	0	0
T100	1	1	0	0
T101	1	1	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	95	1	1	100.00

38                        logic unused_sigs;
39         unreachable    assign unused_sigs = ^{attr_i.slew_rate,
40                                               attr_i.drive_strength[3:1],
41                                               attr_i.od_en,
42                                               attr_i.schmitt_en,
43                                               attr_i.keep_en,
44                                               scanmode_i,
45                                               pok_i};
46                        //VCS coverage on
47                        // pragma coverage on
48                      
49                        // Input enable (active-high)
50                        logic ie;
51         1/1            assign ie = ie_i & ~attr_i.input_disable;
           Tests:       T14 T15 T16 
52                      
53                        if (PadType == InputStd) begin : gen_input_only
54                          //VCS coverage off
55                          // pragma coverage off
56                          logic unused_in_sigs;
57                          assign unused_in_sigs = ^{out_i,
58                                                    oe_i,
59                                                    attr_i.virt_od_en,
60                                                    attr_i.drive_strength};
61                          //VCS coverage on
62                          // pragma coverage on
63                      
64                          assign in_raw_o = ie ? inout_io : 1'bz;
65                          // input inversion
66                          assign in_o = attr_i.invert ^ in_raw_o;
67                      
68                        // pulls are not supported by verilator
69                        `ifndef VERILATOR
70                          // pullup / pulldown termination
71                          assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72                        `endif
73                        end else if (PadType == BidirTol ||
74                                     PadType == DualBidirTol ||
75                                     PadType == BidirOd ||
76                                     PadType == BidirStd) begin : gen_bidir
77                      
78         1/1              assign in_raw_o = ie ? inout_io : 1'bz;
           Tests:       T25 T7 T58 
79                          // input inversion
80         1/1              assign in_o = attr_i.invert ^ in_raw_o;
           Tests:       T25 T7 T58 
81                      
82                          // virtual open drain emulation
83                          logic oe, out;
84         1/1              assign out = out_i ^ attr_i.invert;
           Tests:       T7 T8 T9 
85         1/1              assign oe  = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
           Tests:       T7 T8 T9 
86                      
87                        // drive strength attributes are not supported by verilator
88                        `ifdef VERILATOR
89                          assign inout_io = (oe)   ? out : 1'bz;
90                        `else
91                          // different driver types
92         1/1              assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T7 T8 T9 
93         1/1              assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T7 T8 T9 
94                          // pullup / pulldown termination
95         1/1              assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
           Tests:       T7 T17 T18 

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T14,T15,T16
1	1	Covered	T1,T2,T3

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1

-1-	Status	Tests
0	Covered	T14,T15,T16
1	Covered	T1,T2,T3

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T25,T7,T58
0	1	Covered	T25,T7,T10
1	0	Covered	T14,T15,T16
1	1	Covered	T14,T15,T16

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T16
1	0	Covered	T7,T8,T9
1	1	Covered	T14,T15,T16

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T15,T16
1	1	Covered	T7,T10,T50

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T15,T16

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T15,T16
1	1	Covered	T14,T15,T16

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T14,T15

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T17,T18
1	0	Covered	T10,T50,T51
1	1	Covered	T7,T14,T15

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T50,T51

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T14,T15
1	1	Covered	T10,T50,T51

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T17,T18

---

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	78	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	93	2	2	100.00
TERNARY	95	2	2	100.00

78             assign in_raw_o = ie ? inout_io : 1'bz;
                                    -1-  
                                    ==>  
                                    ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T14,T15,T16

92             assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                     -1-  
                                                                                     ==>  
                                                                                     ==>  

Branches:

-1-	Status	Tests
1	Covered	T7,T14,T15
0	Covered	T1,T2,T3

93             assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                      -1-  
                                                                                      ==>  
                                                                                      ==>  

Branches:

-1-	Status	Tests
1	Covered	T10,T50,T51
0	Covered	T1,T2,T3

95             assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
                                                                   -1-  
                                                                   ==>  
                                                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T7,T17,T18
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	1007	1007	0	0

AnalogNoScan_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1007	1007	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T25	1	1	0	0
T46	1	1	0	0
T99	1	1	0	0
T100	1	1	0	0
T101	1	1	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	95	1	1	100.00

38                        logic unused_sigs;
39         unreachable    assign unused_sigs = ^{attr_i.slew_rate,
40                                               attr_i.drive_strength[3:1],
41                                               attr_i.od_en,
42                                               attr_i.schmitt_en,
43                                               attr_i.keep_en,
44                                               scanmode_i,
45                                               pok_i};
46                        //VCS coverage on
47                        // pragma coverage on
48                      
49                        // Input enable (active-high)
50                        logic ie;
51         1/1            assign ie = ie_i & ~attr_i.input_disable;
           Tests:       T14 T15 T16 
52                      
53                        if (PadType == InputStd) begin : gen_input_only
54                          //VCS coverage off
55                          // pragma coverage off
56                          logic unused_in_sigs;
57                          assign unused_in_sigs = ^{out_i,
58                                                    oe_i,
59                                                    attr_i.virt_od_en,
60                                                    attr_i.drive_strength};
61                          //VCS coverage on
62                          // pragma coverage on
63                      
64                          assign in_raw_o = ie ? inout_io : 1'bz;
65                          // input inversion
66                          assign in_o = attr_i.invert ^ in_raw_o;
67                      
68                        // pulls are not supported by verilator
69                        `ifndef VERILATOR
70                          // pullup / pulldown termination
71                          assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72                        `endif
73                        end else if (PadType == BidirTol ||
74                                     PadType == DualBidirTol ||
75                                     PadType == BidirOd ||
76                                     PadType == BidirStd) begin : gen_bidir
77                      
78         1/1              assign in_raw_o = ie ? inout_io : 1'bz;
           Tests:       T25 T7 T8 
79                          // input inversion
80         1/1              assign in_o = attr_i.invert ^ in_raw_o;
           Tests:       T25 T7 T8 
81                      
82                          // virtual open drain emulation
83                          logic oe, out;
84         1/1              assign out = out_i ^ attr_i.invert;
           Tests:       T7 T10 T17 
85         1/1              assign oe  = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
           Tests:       T25 T7 T10 
86                      
87                        // drive strength attributes are not supported by verilator
88                        `ifdef VERILATOR
89                          assign inout_io = (oe)   ? out : 1'bz;
90                        `else
91                          // different driver types
92         1/1              assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T25 T7 T10 
93         1/1              assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T25 T7 T10 
94                          // pullup / pulldown termination
95         1/1              assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
           Tests:       T7 T8 T9 

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T14,T15,T16
1	1	Covered	T1,T2,T3

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1

-1-	Status	Tests
0	Covered	T14,T15,T16
1	Covered	T1,T2,T3

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T25,T7,T58
0	1	Covered	T7,T8,T9
1	0	Covered	T14,T15,T16
1	1	Covered	T14,T16,T206

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T16
1	0	Covered	T7,T10,T17
1	1	Covered	T14,T15,T16

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T15,T16
1	1	Covered	T25,T7,T10

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T15,T16

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T15,T16
1	1	Covered	T14,T15,T16

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T14,T15

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T17,T18
1	0	Covered	T25,T10,T50
1	1	Covered	T7,T14,T15

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T25,T10,T50

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T14,T15
1	1	Covered	T25,T10,T50

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T8,T9

---

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	78	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	93	2	2	100.00
TERNARY	95	2	2	100.00

78             assign in_raw_o = ie ? inout_io : 1'bz;
                                    -1-  
                                    ==>  
                                    ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T14,T15,T16

92             assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                     -1-  
                                                                                     ==>  
                                                                                     ==>  

Branches:

-1-	Status	Tests
1	Covered	T7,T14,T15
0	Covered	T1,T2,T3

93             assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                      -1-  
                                                                                      ==>  
                                                                                      ==>  

Branches:

-1-	Status	Tests
1	Covered	T25,T10,T50
0	Covered	T1,T2,T3

95             assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
                                                                   -1-  
                                                                   ==>  
                                                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	1007	1007	0	0

AnalogNoScan_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1007	1007	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T25	1	1	0	0
T46	1	1	0	0
T99	1	1	0	0
T100	1	1	0	0
T101	1	1	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	95	1	1	100.00

38                        logic unused_sigs;
39         unreachable    assign unused_sigs = ^{attr_i.slew_rate,
40                                               attr_i.drive_strength[3:1],
41                                               attr_i.od_en,
42                                               attr_i.schmitt_en,
43                                               attr_i.keep_en,
44                                               scanmode_i,
45                                               pok_i};
46                        //VCS coverage on
47                        // pragma coverage on
48                      
49                        // Input enable (active-high)
50                        logic ie;
51         1/1            assign ie = ie_i & ~attr_i.input_disable;
           Tests:       T14 T15 T16 
52                      
53                        if (PadType == InputStd) begin : gen_input_only
54                          //VCS coverage off
55                          // pragma coverage off
56                          logic unused_in_sigs;
57                          assign unused_in_sigs = ^{out_i,
58                                                    oe_i,
59                                                    attr_i.virt_od_en,
60                                                    attr_i.drive_strength};
61                          //VCS coverage on
62                          // pragma coverage on
63                      
64                          assign in_raw_o = ie ? inout_io : 1'bz;
65                          // input inversion
66                          assign in_o = attr_i.invert ^ in_raw_o;
67                      
68                        // pulls are not supported by verilator
69                        `ifndef VERILATOR
70                          // pullup / pulldown termination
71                          assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72                        `endif
73                        end else if (PadType == BidirTol ||
74                                     PadType == DualBidirTol ||
75                                     PadType == BidirOd ||
76                                     PadType == BidirStd) begin : gen_bidir
77                      
78         1/1              assign in_raw_o = ie ? inout_io : 1'bz;
           Tests:       T25 T26 T58 
79                          // input inversion
80         1/1              assign in_o = attr_i.invert ^ in_raw_o;
           Tests:       T25 T26 T58 
81                      
82                          // virtual open drain emulation
83                          logic oe, out;
84         1/1              assign out = out_i ^ attr_i.invert;
           Tests:       T10 T50 T51 
85         1/1              assign oe  = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
           Tests:       T25 T10 T50 
86                      
87                        // drive strength attributes are not supported by verilator
88                        `ifdef VERILATOR
89                          assign inout_io = (oe)   ? out : 1'bz;
90                        `else
91                          // different driver types
92         1/1              assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T25 T10 T50 
93         1/1              assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T25 T10 T50 
94                          // pullup / pulldown termination
95         1/1              assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
           Tests:       T14 T15 T16 

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T14,T15,T16
1	1	Covered	T1,T2,T3

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1

-1-	Status	Tests
0	Covered	T14,T15,T16
1	Covered	T1,T2,T3

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T25,T26,T58
0	1	Covered	T10,T50,T51
1	0	Covered	T14,T15,T206
1	1	Covered	T14,T15,T16

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T16
1	0	Covered	T10,T50,T51
1	1	Covered	T14,T15,T16

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T15,T16
1	1	Covered	T25,T10,T50

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T15,T16

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T15,T16
1	1	Covered	T14,T15,T16

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T14,T15,T16

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T25,T10,T50
1	1	Covered	T14,T15,T16

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T25,T10,T50

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T15,T16
1	1	Covered	T25,T10,T50

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T14,T15,T16

---

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	78	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	93	2	2	100.00
TERNARY	95	2	2	100.00

78             assign in_raw_o = ie ? inout_io : 1'bz;
                                    -1-  
                                    ==>  
                                    ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T14,T15,T16

92             assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                     -1-  
                                                                                     ==>  
                                                                                     ==>  

Branches:

-1-	Status	Tests
1	Covered	T14,T15,T16
0	Covered	T1,T2,T3

93             assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                      -1-  
                                                                                      ==>  
                                                                                      ==>  

Branches:

-1-	Status	Tests
1	Covered	T25,T10,T50
0	Covered	T1,T2,T3

95             assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
                                                                   -1-  
                                                                   ==>  
                                                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T14,T15,T16
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	1007	1007	0	0

AnalogNoScan_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1007	1007	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T25	1	1	0	0
T46	1	1	0	0
T99	1	1	0	0
T100	1	1	0	0
T101	1	1	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	95	1	1	100.00

38                        logic unused_sigs;
39         unreachable    assign unused_sigs = ^{attr_i.slew_rate,
40                                               attr_i.drive_strength[3:1],
41                                               attr_i.od_en,
42                                               attr_i.schmitt_en,
43                                               attr_i.keep_en,
44                                               scanmode_i,
45                                               pok_i};
46                        //VCS coverage on
47                        // pragma coverage on
48                      
49                        // Input enable (active-high)
50                        logic ie;
51         1/1            assign ie = ie_i & ~attr_i.input_disable;
           Tests:       T14 T15 T16 
52                      
53                        if (PadType == InputStd) begin : gen_input_only
54                          //VCS coverage off
55                          // pragma coverage off
56                          logic unused_in_sigs;
57                          assign unused_in_sigs = ^{out_i,
58                                                    oe_i,
59                                                    attr_i.virt_od_en,
60                                                    attr_i.drive_strength};
61                          //VCS coverage on
62                          // pragma coverage on
63                      
64                          assign in_raw_o = ie ? inout_io : 1'bz;
65                          // input inversion
66                          assign in_o = attr_i.invert ^ in_raw_o;
67                      
68                        // pulls are not supported by verilator
69                        `ifndef VERILATOR
70                          // pullup / pulldown termination
71                          assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72                        `endif
73                        end else if (PadType == BidirTol ||
74                                     PadType == DualBidirTol ||
75                                     PadType == BidirOd ||
76                                     PadType == BidirStd) begin : gen_bidir
77                      
78         1/1              assign in_raw_o = ie ? inout_io : 1'bz;
           Tests:       T25 T7 T8 
79                          // input inversion
80         1/1              assign in_o = attr_i.invert ^ in_raw_o;
           Tests:       T25 T7 T8 
81                      
82                          // virtual open drain emulation
83                          logic oe, out;
84         1/1              assign out = out_i ^ attr_i.invert;
           Tests:       T7 T14 T15 
85         1/1              assign oe  = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
           Tests:       T7 T10 T50 
86                      
87                        // drive strength attributes are not supported by verilator
88                        `ifdef VERILATOR
89                          assign inout_io = (oe)   ? out : 1'bz;
90                        `else
91                          // different driver types
92         1/1              assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T7 T10 T17 
93         1/1              assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T7 T10 T17 
94                          // pullup / pulldown termination
95         1/1              assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
           Tests:       T7 T8 T9 

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T14,T15,T16
1	1	Covered	T1,T2,T3

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1

-1-	Status	Tests
0	Covered	T14,T15,T16
1	Covered	T1,T2,T3

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T25,T7,T42
0	1	Covered	T25,T7,T8
1	0	Covered	T14,T15,T16
1	1	Covered	T14,T15,T16

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T16
1	0	Covered	T7,T14,T15
1	1	Covered	T14,T15,T16

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T16,T206
1	1	Covered	T7,T10,T50

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T15,T16

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T15,T16
1	1	Covered	T14,T15,T16

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T14,T15

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T17,T18
1	0	Covered	T10,T50,T51
1	1	Covered	T7,T14,T15

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T50,T51

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T14,T15
1	1	Covered	T10,T50,T51

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T8,T9

---

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	78	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	93	2	2	100.00
TERNARY	95	2	2	100.00

78             assign in_raw_o = ie ? inout_io : 1'bz;
                                    -1-  
                                    ==>  
                                    ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T14,T15,T16

92             assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                     -1-  
                                                                                     ==>  
                                                                                     ==>  

Branches:

-1-	Status	Tests
1	Covered	T7,T14,T15
0	Covered	T1,T2,T3

93             assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                      -1-  
                                                                                      ==>  
                                                                                      ==>  

Branches:

-1-	Status	Tests
1	Covered	T10,T50,T51
0	Covered	T1,T2,T3

95             assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
                                                                   -1-  
                                                                   ==>  
                                                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	1007	1007	0	0

AnalogNoScan_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1007	1007	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T25	1	1	0	0
T46	1	1	0	0
T99	1	1	0	0
T100	1	1	0	0
T101	1	1	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[13].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	95	1	1	100.00

38                        logic unused_sigs;
39         unreachable    assign unused_sigs = ^{attr_i.slew_rate,
40                                               attr_i.drive_strength[3:1],
41                                               attr_i.od_en,
42                                               attr_i.schmitt_en,
43                                               attr_i.keep_en,
44                                               scanmode_i,
45                                               pok_i};
46                        //VCS coverage on
47                        // pragma coverage on
48                      
49                        // Input enable (active-high)
50                        logic ie;
51         1/1            assign ie = ie_i & ~attr_i.input_disable;
           Tests:       T14 T15 T16 
52                      
53                        if (PadType == InputStd) begin : gen_input_only
54                          //VCS coverage off
55                          // pragma coverage off
56                          logic unused_in_sigs;
57                          assign unused_in_sigs = ^{out_i,
58                                                    oe_i,
59                                                    attr_i.virt_od_en,
60                                                    attr_i.drive_strength};
61                          //VCS coverage on
62                          // pragma coverage on
63                      
64                          assign in_raw_o = ie ? inout_io : 1'bz;
65                          // input inversion
66                          assign in_o = attr_i.invert ^ in_raw_o;
67                      
68                        // pulls are not supported by verilator
69                        `ifndef VERILATOR
70                          // pullup / pulldown termination
71                          assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72                        `endif
73                        end else if (PadType == BidirTol ||
74                                     PadType == DualBidirTol ||
75                                     PadType == BidirOd ||
76                                     PadType == BidirStd) begin : gen_bidir
77                      
78         1/1              assign in_raw_o = ie ? inout_io : 1'bz;
           Tests:       T25 T7 T26 
79                          // input inversion
80         1/1              assign in_o = attr_i.invert ^ in_raw_o;
           Tests:       T25 T7 T26 
81                      
82                          // virtual open drain emulation
83                          logic oe, out;
84         1/1              assign out = out_i ^ attr_i.invert;
           Tests:       T10 T50 T51 
85         1/1              assign oe  = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
           Tests:       T10 T50 T51 
86                      
87                        // drive strength attributes are not supported by verilator
88                        `ifdef VERILATOR
89                          assign inout_io = (oe)   ? out : 1'bz;
90                        `else
91                          // different driver types
92         1/1              assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T7 T10 T17 
93         1/1              assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T7 T10 T17 
94                          // pullup / pulldown termination
95         1/1              assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
           Tests:       T7 T10 T17 

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[13].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T14,T15,T16
1	1	Covered	T1,T2,T3

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1

-1-	Status	Tests
0	Covered	T14,T15,T16
1	Covered	T1,T2,T3

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T25,T7,T26
0	1	Covered	T25,T7,T126
1	0	Covered	T14,T15,T16
1	1	Covered	T14,T15,T16

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T16
1	0	Covered	T10,T50,T51
1	1	Covered	T14,T15,T16

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T15,T16
1	1	Covered	T10,T50,T51

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T15,T16

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T15,T16
1	1	Covered	T14,T15,T16

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T14,T15,T16

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T17,T18
1	0	Covered	T10,T50,T51
1	1	Covered	T14,T15,T16

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T50,T51

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T15,T16
1	1	Covered	T10,T50,T51

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T10,T17

---

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[13].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	78	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	93	2	2	100.00
TERNARY	95	2	2	100.00

78             assign in_raw_o = ie ? inout_io : 1'bz;
                                    -1-  
                                    ==>  
                                    ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T14,T15,T16

92             assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                     -1-  
                                                                                     ==>  
                                                                                     ==>  

Branches:

-1-	Status	Tests
1	Covered	T14,T15,T16
0	Covered	T1,T2,T3

93             assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                      -1-  
                                                                                      ==>  
                                                                                      ==>  

Branches:

-1-	Status	Tests
1	Covered	T10,T50,T51
0	Covered	T1,T2,T3

95             assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
                                                                   -1-  
                                                                   ==>  
                                                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T7,T10,T17
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[13].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	1007	1007	0	0

AnalogNoScan_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1007	1007	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T25	1	1	0	0
T46	1	1	0	0
T99	1	1	0	0
T100	1	1	0	0
T101	1	1	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[14].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	95	1	1	100.00

38                        logic unused_sigs;
39         unreachable    assign unused_sigs = ^{attr_i.slew_rate,
40                                               attr_i.drive_strength[3:1],
41                                               attr_i.od_en,
42                                               attr_i.schmitt_en,
43                                               attr_i.keep_en,
44                                               scanmode_i,
45                                               pok_i};
46                        //VCS coverage on
47                        // pragma coverage on
48                      
49                        // Input enable (active-high)
50                        logic ie;
51         1/1            assign ie = ie_i & ~attr_i.input_disable;
           Tests:       T14 T15 T16 
52                      
53                        if (PadType == InputStd) begin : gen_input_only
54                          //VCS coverage off
55                          // pragma coverage off
56                          logic unused_in_sigs;
57                          assign unused_in_sigs = ^{out_i,
58                                                    oe_i,
59                                                    attr_i.virt_od_en,
60                                                    attr_i.drive_strength};
61                          //VCS coverage on
62                          // pragma coverage on
63                      
64                          assign in_raw_o = ie ? inout_io : 1'bz;
65                          // input inversion
66                          assign in_o = attr_i.invert ^ in_raw_o;
67                      
68                        // pulls are not supported by verilator
69                        `ifndef VERILATOR
70                          // pullup / pulldown termination
71                          assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72                        `endif
73                        end else if (PadType == BidirTol ||
74                                     PadType == DualBidirTol ||
75                                     PadType == BidirOd ||
76                                     PadType == BidirStd) begin : gen_bidir
77                      
78         1/1              assign in_raw_o = ie ? inout_io : 1'bz;
           Tests:       T1 T2 T3 
79                          // input inversion
80         1/1              assign in_o = attr_i.invert ^ in_raw_o;
           Tests:       T1 T2 T3 
81                      
82                          // virtual open drain emulation
83                          logic oe, out;
84         1/1              assign out = out_i ^ attr_i.invert;
           Tests:       T1 T2 T3 
85         1/1              assign oe  = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
           Tests:       T1 T2 T3 
86                      
87                        // drive strength attributes are not supported by verilator
88                        `ifdef VERILATOR
89                          assign inout_io = (oe)   ? out : 1'bz;
90                        `else
91                          // different driver types
92         1/1              assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T1 T2 T3 
93         1/1              assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T1 T2 T3 
94                          // pullup / pulldown termination
95         1/1              assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
           Tests:       T7 T10 T17 

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[14].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T14,T15,T16
1	1	Covered	T1,T2,T3

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1

-1-	Status	Tests
0	Covered	T14,T15,T16
1	Covered	T1,T2,T3

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T25,T126,T127
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T15,T16
1	1	Covered	T14,T15,T16

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T14,T15,T16

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T15,T16
1	1	Covered	T1,T2,T3

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T15,T16

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T15,T16
1	1	Covered	T14,T15,T16

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T17,T18

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T17,T18
1	0	Covered	T1,T2,T3
1	1	Covered	T7,T17,T18

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T17,T18
1	1	Covered	T1,T2,T3

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T10,T17

---

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[14].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	78	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	93	2	2	100.00
TERNARY	95	2	2	100.00

78             assign in_raw_o = ie ? inout_io : 1'bz;
                                    -1-  
                                    ==>  
                                    ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T14,T15,T16

92             assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                     -1-  
                                                                                     ==>  
                                                                                     ==>  

Branches:

-1-	Status	Tests
1	Covered	T7,T17,T18
0	Covered	T1,T2,T3

93             assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                      -1-  
                                                                                      ==>  
                                                                                      ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

95             assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
                                                                   -1-  
                                                                   ==>  
                                                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T7,T10,T17
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[14].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	1007	1007	0	0

AnalogNoScan_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1007	1007	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T25	1	1	0	0
T46	1	1	0	0
T99	1	1	0	0
T100	1	1	0	0
T101	1	1	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[15].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	95	1	1	100.00

38                        logic unused_sigs;
39         unreachable    assign unused_sigs = ^{attr_i.slew_rate,
40                                               attr_i.drive_strength[3:1],
41                                               attr_i.od_en,
42                                               attr_i.schmitt_en,
43                                               attr_i.keep_en,
44                                               scanmode_i,
45                                               pok_i};
46                        //VCS coverage on
47                        // pragma coverage on
48                      
49                        // Input enable (active-high)
50                        logic ie;
51         1/1            assign ie = ie_i & ~attr_i.input_disable;
           Tests:       T14 T15 T16 
52                      
53                        if (PadType == InputStd) begin : gen_input_only
54                          //VCS coverage off
55                          // pragma coverage off
56                          logic unused_in_sigs;
57                          assign unused_in_sigs = ^{out_i,
58                                                    oe_i,
59                                                    attr_i.virt_od_en,
60                                                    attr_i.drive_strength};
61                          //VCS coverage on
62                          // pragma coverage on
63                      
64                          assign in_raw_o = ie ? inout_io : 1'bz;
65                          // input inversion
66                          assign in_o = attr_i.invert ^ in_raw_o;
67                      
68                        // pulls are not supported by verilator
69                        `ifndef VERILATOR
70                          // pullup / pulldown termination
71                          assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72                        `endif
73                        end else if (PadType == BidirTol ||
74                                     PadType == DualBidirTol ||
75                                     PadType == BidirOd ||
76                                     PadType == BidirStd) begin : gen_bidir
77                      
78         1/1              assign in_raw_o = ie ? inout_io : 1'bz;
           Tests:       T25 T7 T28 
79                          // input inversion
80         1/1              assign in_o = attr_i.invert ^ in_raw_o;
           Tests:       T25 T7 T28 
81                      
82                          // virtual open drain emulation
83                          logic oe, out;
84         1/1              assign out = out_i ^ attr_i.invert;
           Tests:       T28 T10 T29 
85         1/1              assign oe  = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
           Tests:       T28 T10 T29 
86                      
87                        // drive strength attributes are not supported by verilator
88                        `ifdef VERILATOR
89                          assign inout_io = (oe)   ? out : 1'bz;
90                        `else
91                          // different driver types
92         1/1              assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T7 T28 T10 
93         1/1              assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T7 T28 T10 
94                          // pullup / pulldown termination
95         1/1              assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
           Tests:       T7 T10 T17 

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[15].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T14,T15,T16
1	1	Covered	T1,T2,T3

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1

-1-	Status	Tests
0	Covered	T14,T15,T16
1	Covered	T1,T2,T3

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T25,T28,T42
0	1	Covered	T25,T7,T28
1	0	Covered	T14,T15,T16
1	1	Covered	T14,T15,T16

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T16
1	0	Covered	T28,T10,T29
1	1	Covered	T14,T15,T16

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T15,T16
1	1	Covered	T28,T10,T29

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T15,T16

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T15,T16
1	1	Covered	T14,T15,T16

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T14,T15,T16

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T17,T18
1	0	Covered	T28,T10,T29
1	1	Covered	T14,T15,T16

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T28,T10,T29

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T15,T16
1	1	Covered	T28,T10,T29

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T10,T17

---

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[15].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	78	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	93	2	2	100.00
TERNARY	95	2	2	100.00

78             assign in_raw_o = ie ? inout_io : 1'bz;
                                    -1-  
                                    ==>  
                                    ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T14,T15,T16

92             assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                     -1-  
                                                                                     ==>  
                                                                                     ==>  

Branches:

-1-	Status	Tests
1	Covered	T14,T15,T16
0	Covered	T1,T2,T3

93             assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                      -1-  
                                                                                      ==>  
                                                                                      ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T10,T29
0	Covered	T1,T2,T3

95             assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
                                                                   -1-  
                                                                   ==>  
                                                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T7,T10,T17
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[15].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	1007	1007	0	0

AnalogNoScan_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1007	1007	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T25	1	1	0	0
T46	1	1	0	0
T99	1	1	0	0
T100	1	1	0	0
T101	1	1	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[16].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	95	1	1	100.00

38                        logic unused_sigs;
39         unreachable    assign unused_sigs = ^{attr_i.slew_rate,
40                                               attr_i.drive_strength[3:1],
41                                               attr_i.od_en,
42                                               attr_i.schmitt_en,
43                                               attr_i.keep_en,
44                                               scanmode_i,
45                                               pok_i};
46                        //VCS coverage on
47                        // pragma coverage on
48                      
49                        // Input enable (active-high)
50                        logic ie;
51         1/1            assign ie = ie_i & ~attr_i.input_disable;
           Tests:       T14 T15 T16 
52                      
53                        if (PadType == InputStd) begin : gen_input_only
54                          //VCS coverage off
55                          // pragma coverage off
56                          logic unused_in_sigs;
57                          assign unused_in_sigs = ^{out_i,
58                                                    oe_i,
59                                                    attr_i.virt_od_en,
60                                                    attr_i.drive_strength};
61                          //VCS coverage on
62                          // pragma coverage on
63                      
64                          assign in_raw_o = ie ? inout_io : 1'bz;
65                          // input inversion
66                          assign in_o = attr_i.invert ^ in_raw_o;
67                      
68                        // pulls are not supported by verilator
69                        `ifndef VERILATOR
70                          // pullup / pulldown termination
71                          assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72                        `endif
73                        end else if (PadType == BidirTol ||
74                                     PadType == DualBidirTol ||
75                                     PadType == BidirOd ||
76                                     PadType == BidirStd) begin : gen_bidir
77                      
78         1/1              assign in_raw_o = ie ? inout_io : 1'bz;
           Tests:       T25 T28 T11 
79                          // input inversion
80         1/1              assign in_o = attr_i.invert ^ in_raw_o;
           Tests:       T25 T28 T11 
81                      
82                          // virtual open drain emulation
83                          logic oe, out;
84         1/1              assign out = out_i ^ attr_i.invert;
           Tests:       T28 T11 T45 
85         1/1              assign oe  = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
           Tests:       T28 T11 T45 
86                      
87                        // drive strength attributes are not supported by verilator
88                        `ifdef VERILATOR
89                          assign inout_io = (oe)   ? out : 1'bz;
90                        `else
91                          // different driver types
92         1/1              assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T28 T11 T45 
93         1/1              assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T28 T11 T45 
94                          // pullup / pulldown termination
95         1/1              assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
           Tests:       T14 T15 T16 

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[16].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T14,T15,T16
1	1	Covered	T1,T2,T3

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1

-1-	Status	Tests
0	Covered	T14,T15,T16
1	Covered	T1,T2,T3

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T25,T28,T11
0	1	Covered	T25,T28,T11
1	0	Covered	T14,T15,T16
1	1	Covered	T14,T15,T16

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T16
1	0	Covered	T28,T11,T45
1	1	Covered	T14,T15,T16

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T15,T16
1	1	Covered	T28,T11,T45

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T15,T16

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T15,T16
1	1	Covered	T14,T15,T16

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T14,T15,T16

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T28,T11,T45
1	1	Covered	T14,T15,T16

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T28,T11,T45

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T15,T16
1	1	Covered	T28,T11,T45

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T14,T15,T16

---

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[16].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	78	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	93	2	2	100.00
TERNARY	95	2	2	100.00

78             assign in_raw_o = ie ? inout_io : 1'bz;
                                    -1-  
                                    ==>  
                                    ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T14,T15,T16

92             assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                     -1-  
                                                                                     ==>  
                                                                                     ==>  

Branches:

-1-	Status	Tests
1	Covered	T14,T15,T16
0	Covered	T1,T2,T3

93             assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                      -1-  
                                                                                      ==>  
                                                                                      ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T11,T45
0	Covered	T1,T2,T3

95             assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
                                                                   -1-  
                                                                   ==>  
                                                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T14,T15,T16
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[16].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	1007	1007	0	0

AnalogNoScan_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1007	1007	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T25	1	1	0	0
T46	1	1	0	0
T99	1	1	0	0
T100	1	1	0	0
T101	1	1	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[17].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	95	1	1	100.00

38                        logic unused_sigs;
39         unreachable    assign unused_sigs = ^{attr_i.slew_rate,
40                                               attr_i.drive_strength[3:1],
41                                               attr_i.od_en,
42                                               attr_i.schmitt_en,
43                                               attr_i.keep_en,
44                                               scanmode_i,
45                                               pok_i};
46                        //VCS coverage on
47                        // pragma coverage on
48                      
49                        // Input enable (active-high)
50                        logic ie;
51         1/1            assign ie = ie_i & ~attr_i.input_disable;
           Tests:       T14 T15 T16 
52                      
53                        if (PadType == InputStd) begin : gen_input_only
54                          //VCS coverage off
55                          // pragma coverage off
56                          logic unused_in_sigs;
57                          assign unused_in_sigs = ^{out_i,
58                                                    oe_i,
59                                                    attr_i.virt_od_en,
60                                                    attr_i.drive_strength};
61                          //VCS coverage on
62                          // pragma coverage on
63                      
64                          assign in_raw_o = ie ? inout_io : 1'bz;
65                          // input inversion
66                          assign in_o = attr_i.invert ^ in_raw_o;
67                      
68                        // pulls are not supported by verilator
69                        `ifndef VERILATOR
70                          // pullup / pulldown termination
71                          assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72                        `endif
73                        end else if (PadType == BidirTol ||
74                                     PadType == DualBidirTol ||
75                                     PadType == BidirOd ||
76                                     PadType == BidirStd) begin : gen_bidir
77                      
78         1/1              assign in_raw_o = ie ? inout_io : 1'bz;
           Tests:       T25 T28 T42 
79                          // input inversion
80         1/1              assign in_o = attr_i.invert ^ in_raw_o;
           Tests:       T25 T28 T42 
81                      
82                          // virtual open drain emulation
83                          logic oe, out;
84         1/1              assign out = out_i ^ attr_i.invert;
           Tests:       T28 T10 T29 
85         1/1              assign oe  = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
           Tests:       T28 T10 T29 
86                      
87                        // drive strength attributes are not supported by verilator
88                        `ifdef VERILATOR
89                          assign inout_io = (oe)   ? out : 1'bz;
90                        `else
91                          // different driver types
92         1/1              assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T28 T10 T29 
93         1/1              assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T28 T10 T29 
94                          // pullup / pulldown termination
95         1/1              assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
           Tests:       T14 T15 T16 

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[17].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T14,T15,T16
1	1	Covered	T1,T2,T3

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1

-1-	Status	Tests
0	Covered	T14,T15,T16
1	Covered	T1,T2,T3

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T25,T28,T42
0	1	Covered	T25,T28,T42
1	0	Covered	T14,T15,T16
1	1	Covered	T14,T15,T16

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T16
1	0	Covered	T28,T10,T29
1	1	Covered	T14,T15,T16

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T16,T206
1	1	Covered	T28,T10,T29

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T15,T16

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T15,T16
1	1	Covered	T14,T15,T16

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T14,T15,T16

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T28,T10,T29
1	1	Covered	T14,T15,T16

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T28,T10,T29

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T15,T16
1	1	Covered	T28,T10,T29

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T14,T15,T16

---

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[17].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	78	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	93	2	2	100.00
TERNARY	95	2	2	100.00

78             assign in_raw_o = ie ? inout_io : 1'bz;
                                    -1-  
                                    ==>  
                                    ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T14,T15,T16

92             assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                     -1-  
                                                                                     ==>  
                                                                                     ==>  

Branches:

-1-	Status	Tests
1	Covered	T14,T15,T16
0	Covered	T1,T2,T3

93             assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                      -1-  
                                                                                      ==>  
                                                                                      ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T10,T29
0	Covered	T1,T2,T3

95             assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
                                                                   -1-  
                                                                   ==>  
                                                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T14,T15,T16
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[17].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	1007	1007	0	0

AnalogNoScan_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1007	1007	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T25	1	1	0	0
T46	1	1	0	0
T99	1	1	0	0
T100	1	1	0	0
T101	1	1	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[18].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	95	1	1	100.00

38                        logic unused_sigs;
39         unreachable    assign unused_sigs = ^{attr_i.slew_rate,
40                                               attr_i.drive_strength[3:1],
41                                               attr_i.od_en,
42                                               attr_i.schmitt_en,
43                                               attr_i.keep_en,
44                                               scanmode_i,
45                                               pok_i};
46                        //VCS coverage on
47                        // pragma coverage on
48                      
49                        // Input enable (active-high)
50                        logic ie;
51         1/1            assign ie = ie_i & ~attr_i.input_disable;
           Tests:       T14 T15 T16 
52                      
53                        if (PadType == InputStd) begin : gen_input_only
54                          //VCS coverage off
55                          // pragma coverage off
56                          logic unused_in_sigs;
57                          assign unused_in_sigs = ^{out_i,
58                                                    oe_i,
59                                                    attr_i.virt_od_en,
60                                                    attr_i.drive_strength};
61                          //VCS coverage on
62                          // pragma coverage on
63                      
64                          assign in_raw_o = ie ? inout_io : 1'bz;
65                          // input inversion
66                          assign in_o = attr_i.invert ^ in_raw_o;
67                      
68                        // pulls are not supported by verilator
69                        `ifndef VERILATOR
70                          // pullup / pulldown termination
71                          assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72                        `endif
73                        end else if (PadType == BidirTol ||
74                                     PadType == DualBidirTol ||
75                                     PadType == BidirOd ||
76                                     PadType == BidirStd) begin : gen_bidir
77                      
78         1/1              assign in_raw_o = ie ? inout_io : 1'bz;
           Tests:       T25 T5 T28 
79                          // input inversion
80         1/1              assign in_o = attr_i.invert ^ in_raw_o;
           Tests:       T25 T5 T28 
81                      
82                          // virtual open drain emulation
83                          logic oe, out;
84         1/1              assign out = out_i ^ attr_i.invert;
           Tests:       T28 T45 T48 
85         1/1              assign oe  = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
           Tests:       T5 T28 T33 
86                      
87                        // drive strength attributes are not supported by verilator
88                        `ifdef VERILATOR
89                          assign inout_io = (oe)   ? out : 1'bz;
90                        `else
91                          // different driver types
92         1/1              assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T5 T28 T33 
93         1/1              assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T5 T28 T33 
94                          // pullup / pulldown termination
95         1/1              assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
           Tests:       T14 T15 T16 

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[18].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T14,T15,T16
1	1	Covered	T1,T2,T3

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1

-1-	Status	Tests
0	Covered	T14,T15,T16
1	Covered	T1,T2,T3

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T25,T5,T28
0	1	Covered	T25,T28,T33
1	0	Covered	T14,T16,T206
1	1	Covered	T14,T16,T206

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T16
1	0	Covered	T28,T45,T48
1	1	Covered	T14,T16,T206

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T15,T16
1	1	Covered	T5,T28,T33

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T15,T16

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T15,T16
1	1	Covered	T14,T15,T16

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T14,T15,T16

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T5,T28,T33
1	1	Covered	T14,T15,T16

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T28,T33

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T15,T16
1	1	Covered	T5,T28,T33

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T14,T15,T16

---

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[18].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	78	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	93	2	2	100.00
TERNARY	95	2	2	100.00

78             assign in_raw_o = ie ? inout_io : 1'bz;
                                    -1-  
                                    ==>  
                                    ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T14,T15,T16

92             assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                     -1-  
                                                                                     ==>  
                                                                                     ==>  

Branches:

-1-	Status	Tests
1	Covered	T14,T15,T16
0	Covered	T1,T2,T3

93             assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                      -1-  
                                                                                      ==>  
                                                                                      ==>  

Branches:

-1-	Status	Tests
1	Covered	T5,T28,T33
0	Covered	T1,T2,T3

95             assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
                                                                   -1-  
                                                                   ==>  
                                                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T14,T15,T16
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[18].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	1007	1007	0	0

AnalogNoScan_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1007	1007	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T25	1	1	0	0
T46	1	1	0	0
T99	1	1	0	0
T100	1	1	0	0
T101	1	1	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[19].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	95	1	1	100.00

38                        logic unused_sigs;
39         unreachable    assign unused_sigs = ^{attr_i.slew_rate,
40                                               attr_i.drive_strength[3:1],
41                                               attr_i.od_en,
42                                               attr_i.schmitt_en,
43                                               attr_i.keep_en,
44                                               scanmode_i,
45                                               pok_i};
46                        //VCS coverage on
47                        // pragma coverage on
48                      
49                        // Input enable (active-high)
50                        logic ie;
51         1/1            assign ie = ie_i & ~attr_i.input_disable;
           Tests:       T14 T15 T16 
52                      
53                        if (PadType == InputStd) begin : gen_input_only
54                          //VCS coverage off
55                          // pragma coverage off
56                          logic unused_in_sigs;
57                          assign unused_in_sigs = ^{out_i,
58                                                    oe_i,
59                                                    attr_i.virt_od_en,
60                                                    attr_i.drive_strength};
61                          //VCS coverage on
62                          // pragma coverage on
63                      
64                          assign in_raw_o = ie ? inout_io : 1'bz;
65                          // input inversion
66                          assign in_o = attr_i.invert ^ in_raw_o;
67                      
68                        // pulls are not supported by verilator
69                        `ifndef VERILATOR
70                          // pullup / pulldown termination
71                          assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72                        `endif
73                        end else if (PadType == BidirTol ||
74                                     PadType == DualBidirTol ||
75                                     PadType == BidirOd ||
76                                     PadType == BidirStd) begin : gen_bidir
77                      
78         1/1              assign in_raw_o = ie ? inout_io : 1'bz;
           Tests:       T25 T5 T28 
79                          // input inversion
80         1/1              assign in_o = attr_i.invert ^ in_raw_o;
           Tests:       T25 T5 T28 
81                      
82                          // virtual open drain emulation
83                          logic oe, out;
84         1/1              assign out = out_i ^ attr_i.invert;
           Tests:       T28 T49 T52 
85         1/1              assign oe  = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
           Tests:       T25 T5 T28 
86                      
87                        // drive strength attributes are not supported by verilator
88                        `ifdef VERILATOR
89                          assign inout_io = (oe)   ? out : 1'bz;
90                        `else
91                          // different driver types
92         1/1              assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T25 T5 T28 
93         1/1              assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T25 T5 T28 
94                          // pullup / pulldown termination
95         1/1              assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
           Tests:       T14 T15 T16 

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[19].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T14,T15,T16
1	1	Covered	T1,T2,T3

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1

-1-	Status	Tests
0	Covered	T14,T15,T16
1	Covered	T1,T2,T3

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T25,T5,T28
0	1	Covered	T28,T33,T49
1	0	Covered	T14,T15,T206
1	1	Covered	T14,T15,T206

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T16
1	0	Covered	T28,T49,T52
1	1	Covered	T14,T15,T16

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T15,T16
1	1	Covered	T25,T5,T28

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T15,T16

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T15,T16
1	1	Covered	T14,T15,T16

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T14,T15,T16

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T25,T5,T28
1	1	Covered	T14,T15,T16

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T25,T5,T28

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T15,T16
1	1	Covered	T25,T5,T28

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T14,T15,T16

---

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[19].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	78	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	93	2	2	100.00
TERNARY	95	2	2	100.00

78             assign in_raw_o = ie ? inout_io : 1'bz;
                                    -1-  
                                    ==>  
                                    ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T14,T15,T16

92             assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                     -1-  
                                                                                     ==>  
                                                                                     ==>  

Branches:

-1-	Status	Tests
1	Covered	T14,T15,T16
0	Covered	T1,T2,T3

93             assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                      -1-  
                                                                                      ==>  
                                                                                      ==>  

Branches:

-1-	Status	Tests
1	Covered	T25,T5,T28
0	Covered	T1,T2,T3

95             assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
                                                                   -1-  
                                                                   ==>  
                                                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T14,T15,T16
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[19].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	1007	1007	0	0

AnalogNoScan_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1007	1007	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T25	1	1	0	0
T46	1	1	0	0
T99	1	1	0	0
T100	1	1	0	0
T101	1	1	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[20].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	95	1	1	100.00

38                        logic unused_sigs;
39         unreachable    assign unused_sigs = ^{attr_i.slew_rate,
40                                               attr_i.drive_strength[3:1],
41                                               attr_i.od_en,
42                                               attr_i.schmitt_en,
43                                               attr_i.keep_en,
44                                               scanmode_i,
45                                               pok_i};
46                        //VCS coverage on
47                        // pragma coverage on
48                      
49                        // Input enable (active-high)
50                        logic ie;
51         1/1            assign ie = ie_i & ~attr_i.input_disable;
           Tests:       T14 T15 T16 
52                      
53                        if (PadType == InputStd) begin : gen_input_only
54                          //VCS coverage off
55                          // pragma coverage off
56                          logic unused_in_sigs;
57                          assign unused_in_sigs = ^{out_i,
58                                                    oe_i,
59                                                    attr_i.virt_od_en,
60                                                    attr_i.drive_strength};
61                          //VCS coverage on
62                          // pragma coverage on
63                      
64                          assign in_raw_o = ie ? inout_io : 1'bz;
65                          // input inversion
66                          assign in_o = attr_i.invert ^ in_raw_o;
67                      
68                        // pulls are not supported by verilator
69                        `ifndef VERILATOR
70                          // pullup / pulldown termination
71                          assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72                        `endif
73                        end else if (PadType == BidirTol ||
74                                     PadType == DualBidirTol ||
75                                     PadType == BidirOd ||
76                                     PadType == BidirStd) begin : gen_bidir
77                      
78         1/1              assign in_raw_o = ie ? inout_io : 1'bz;
           Tests:       T25 T5 T28 
79                          // input inversion
80         1/1              assign in_o = attr_i.invert ^ in_raw_o;
           Tests:       T25 T5 T28 
81                      
82                          // virtual open drain emulation
83                          logic oe, out;
84         1/1              assign out = out_i ^ attr_i.invert;
           Tests:       T5 T28 T49 
85         1/1              assign oe  = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
           Tests:       T5 T28 T36 
86                      
87                        // drive strength attributes are not supported by verilator
88                        `ifdef VERILATOR
89                          assign inout_io = (oe)   ? out : 1'bz;
90                        `else
91                          // different driver types
92         1/1              assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T5 T28 T36 
93         1/1              assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T5 T28 T36 
94                          // pullup / pulldown termination
95         1/1              assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
           Tests:       T14 T15 T16 

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[20].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T14,T15,T16
1	1	Covered	T1,T2,T3

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1

-1-	Status	Tests
0	Covered	T14,T15,T16
1	Covered	T1,T2,T3

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T25,T5,T28
0	1	Covered	T25,T5,T28
1	0	Covered	T14,T15,T16
1	1	Covered	T14,T15,T16

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T16
1	0	Covered	T5,T28,T49
1	1	Covered	T14,T15,T16

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T15,T16
1	1	Covered	T5,T28,T36

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T15,T16

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T15,T16
1	1	Covered	T14,T15,T16

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T14,T15,T16

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T5,T28,T36
1	1	Covered	T14,T15,T16

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T28,T36

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T15,T16
1	1	Covered	T5,T28,T36

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T14,T15,T16

---

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[20].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	78	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	93	2	2	100.00
TERNARY	95	2	2	100.00

78             assign in_raw_o = ie ? inout_io : 1'bz;
                                    -1-  
                                    ==>  
                                    ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T14,T15,T16

92             assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                     -1-  
                                                                                     ==>  
                                                                                     ==>  

Branches:

-1-	Status	Tests
1	Covered	T14,T15,T16
0	Covered	T1,T2,T3

93             assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                      -1-  
                                                                                      ==>  
                                                                                      ==>  

Branches:

-1-	Status	Tests
1	Covered	T5,T28,T36
0	Covered	T1,T2,T3

95             assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
                                                                   -1-  
                                                                   ==>  
                                                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T14,T15,T16
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[20].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	1007	1007	0	0

AnalogNoScan_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1007	1007	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T25	1	1	0	0
T46	1	1	0	0
T99	1	1	0	0
T100	1	1	0	0
T101	1	1	0	0