Summary for Variable cp_handshake_complete
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
1 | 
0 | 
1 | 
100.00 | 
User Defined Bins for cp_handshake_complete
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| complete | 
6032 | 
1 | 
 | 
 | 
T83 | 
1 | 
 | 
T102 | 
1 | 
 | 
T266 | 
118 | 
Summary for Variable cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
1 | 
0 | 
1 | 
100.00 | 
User Defined Bins for cp_trans_type
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| alert_triggered | 
6035 | 
1 | 
 | 
 | 
T83 | 
1 | 
 | 
T102 | 
1 | 
 | 
T266 | 
118 | 
Summary for Cross alert_handshake_complete
Samples crossed: cp_handshake_complete cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
1 | 
0 | 
1 | 
100.00 | 
 | 
Automatically Generated Cross Bins for alert_handshake_complete
Bins
| cp_handshake_complete | cp_trans_type | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| complete | 
alert_triggered | 
6032 | 
1 | 
 | 
 | 
T83 | 
1 | 
 | 
T102 | 
1 | 
 | 
T266 | 
118 | 
 
Summary for Variable cp_handshake_complete
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
1 | 
0 | 
1 | 
100.00 | 
User Defined Bins for cp_handshake_complete
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| complete | 
6969 | 
1 | 
 | 
 | 
T83 | 
1 | 
 | 
T102 | 
3 | 
 | 
T84 | 
1 | 
Summary for Variable cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
1 | 
0 | 
1 | 
100.00 | 
User Defined Bins for cp_trans_type
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| alert_triggered | 
6971 | 
1 | 
 | 
 | 
T83 | 
1 | 
 | 
T102 | 
3 | 
 | 
T84 | 
1 | 
Summary for Cross alert_handshake_complete
Samples crossed: cp_handshake_complete cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
1 | 
0 | 
1 | 
100.00 | 
 | 
Automatically Generated Cross Bins for alert_handshake_complete
Bins
| cp_handshake_complete | cp_trans_type | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| complete | 
alert_triggered | 
6969 | 
1 | 
 | 
 | 
T83 | 
1 | 
 | 
T102 | 
3 | 
 | 
T84 | 
1 | 
 
Summary for Variable cp_handshake_complete
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
1 | 
0 | 
1 | 
100.00 | 
User Defined Bins for cp_handshake_complete
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| complete | 
92 | 
1 | 
 | 
 | 
T83 | 
1 | 
 | 
T84 | 
1 | 
 | 
T85 | 
1 | 
Summary for Variable cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
1 | 
0 | 
1 | 
100.00 | 
User Defined Bins for cp_trans_type
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| alert_triggered | 
92 | 
1 | 
 | 
 | 
T83 | 
1 | 
 | 
T84 | 
1 | 
 | 
T85 | 
1 | 
Summary for Cross alert_handshake_complete
Samples crossed: cp_handshake_complete cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
1 | 
0 | 
1 | 
100.00 | 
 | 
Automatically Generated Cross Bins for alert_handshake_complete
Bins
| cp_handshake_complete | cp_trans_type | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| complete | 
alert_triggered | 
92 | 
1 | 
 | 
 | 
T83 | 
1 | 
 | 
T84 | 
1 | 
 | 
T85 | 
1 | 
 
Summary for Variable cp_handshake_complete
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
1 | 
0 | 
1 | 
100.00 | 
User Defined Bins for cp_handshake_complete
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| complete | 
3803 | 
1 | 
 | 
 | 
T83 | 
1 | 
 | 
T84 | 
1 | 
 | 
T85 | 
1 | 
Summary for Variable cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
1 | 
0 | 
1 | 
100.00 | 
User Defined Bins for cp_trans_type
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| alert_triggered | 
3804 | 
1 | 
 | 
 | 
T83 | 
1 | 
 | 
T84 | 
1 | 
 | 
T85 | 
1 | 
Summary for Cross alert_handshake_complete
Samples crossed: cp_handshake_complete cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
1 | 
0 | 
1 | 
100.00 | 
 | 
Automatically Generated Cross Bins for alert_handshake_complete
Bins
| cp_handshake_complete | cp_trans_type | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| complete | 
alert_triggered | 
3803 | 
1 | 
 | 
 | 
T83 | 
1 | 
 | 
T84 | 
1 | 
 | 
T85 | 
1 | 
 
Summary for Variable cp_handshake_complete
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
1 | 
0 | 
1 | 
100.00 | 
User Defined Bins for cp_handshake_complete
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| complete | 
1798 | 
1 | 
 | 
 | 
T83 | 
1 | 
 | 
T102 | 
5 | 
 | 
T84 | 
1 | 
Summary for Variable cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
1 | 
0 | 
1 | 
100.00 | 
User Defined Bins for cp_trans_type
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| alert_triggered | 
1799 | 
1 | 
 | 
 | 
T83 | 
1 | 
 | 
T102 | 
5 | 
 | 
T84 | 
1 | 
Summary for Cross alert_handshake_complete
Samples crossed: cp_handshake_complete cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
1 | 
0 | 
1 | 
100.00 | 
 | 
Automatically Generated Cross Bins for alert_handshake_complete
Bins
| cp_handshake_complete | cp_trans_type | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| complete | 
alert_triggered | 
1798 | 
1 | 
 | 
 | 
T83 | 
1 | 
 | 
T102 | 
5 | 
 | 
T84 | 
1 | 
 
Summary for Variable cp_handshake_complete
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
1 | 
0 | 
1 | 
100.00 | 
User Defined Bins for cp_handshake_complete
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| complete | 
4034 | 
1 | 
 | 
 | 
T83 | 
1 | 
 | 
T189 | 
2 | 
 | 
T84 | 
1 | 
Summary for Variable cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
1 | 
0 | 
1 | 
100.00 | 
User Defined Bins for cp_trans_type
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| alert_triggered | 
4034 | 
1 | 
 | 
 | 
T83 | 
1 | 
 | 
T189 | 
2 | 
 | 
T84 | 
1 | 
Summary for Cross alert_handshake_complete
Samples crossed: cp_handshake_complete cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
1 | 
0 | 
1 | 
100.00 | 
 | 
Automatically Generated Cross Bins for alert_handshake_complete
Bins
| cp_handshake_complete | cp_trans_type | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| complete | 
alert_triggered | 
4034 | 
1 | 
 | 
 | 
T83 | 
1 | 
 | 
T189 | 
2 | 
 | 
T84 | 
1 | 
 
Summary for Variable cp_handshake_complete
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
1 | 
0 | 
1 | 
100.00 | 
User Defined Bins for cp_handshake_complete
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| complete | 
4916 | 
1 | 
 | 
 | 
T83 | 
1 | 
 | 
T189 | 
1 | 
 | 
T84 | 
1 | 
Summary for Variable cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
1 | 
0 | 
1 | 
100.00 | 
User Defined Bins for cp_trans_type
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| alert_triggered | 
4918 | 
1 | 
 | 
 | 
T83 | 
1 | 
 | 
T189 | 
1 | 
 | 
T84 | 
1 | 
Summary for Cross alert_handshake_complete
Samples crossed: cp_handshake_complete cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
1 | 
0 | 
1 | 
100.00 | 
 | 
Automatically Generated Cross Bins for alert_handshake_complete
Bins
| cp_handshake_complete | cp_trans_type | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| complete | 
alert_triggered | 
4916 | 
1 | 
 | 
 | 
T83 | 
1 | 
 | 
T189 | 
1 | 
 | 
T84 | 
1 | 
 
Summary for Variable cp_handshake_complete
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
1 | 
0 | 
1 | 
100.00 | 
User Defined Bins for cp_handshake_complete
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| complete | 
2764 | 
1 | 
 | 
 | 
T83 | 
1 | 
 | 
T189 | 
1 | 
 | 
T84 | 
1 | 
Summary for Variable cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
1 | 
0 | 
1 | 
100.00 | 
User Defined Bins for cp_trans_type
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| alert_triggered | 
2765 | 
1 | 
 | 
 | 
T83 | 
1 | 
 | 
T189 | 
1 | 
 | 
T84 | 
1 | 
Summary for Cross alert_handshake_complete
Samples crossed: cp_handshake_complete cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
1 | 
0 | 
1 | 
100.00 | 
 | 
Automatically Generated Cross Bins for alert_handshake_complete
Bins
| cp_handshake_complete | cp_trans_type | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| complete | 
alert_triggered | 
2764 | 
1 | 
 | 
 | 
T83 | 
1 | 
 | 
T189 | 
1 | 
 | 
T84 | 
1 | 
 
Summary for Variable cp_handshake_complete
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
1 | 
0 | 
1 | 
100.00 | 
User Defined Bins for cp_handshake_complete
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| complete | 
638 | 
1 | 
 | 
 | 
T83 | 
1 | 
 | 
T189 | 
1 | 
 | 
T84 | 
1 | 
Summary for Variable cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
1 | 
0 | 
1 | 
100.00 | 
User Defined Bins for cp_trans_type
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| alert_triggered | 
638 | 
1 | 
 | 
 | 
T83 | 
1 | 
 | 
T189 | 
1 | 
 | 
T84 | 
1 | 
Summary for Cross alert_handshake_complete
Samples crossed: cp_handshake_complete cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
1 | 
0 | 
1 | 
100.00 | 
 | 
Automatically Generated Cross Bins for alert_handshake_complete
Bins
| cp_handshake_complete | cp_trans_type | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| complete | 
alert_triggered | 
638 | 
1 | 
 | 
 | 
T83 | 
1 | 
 | 
T189 | 
1 | 
 | 
T84 | 
1 | 
 
Summary for Variable cp_handshake_complete
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
1 | 
0 | 
1 | 
100.00 | 
User Defined Bins for cp_handshake_complete
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| complete | 
3810 | 
1 | 
 | 
 | 
T83 | 
1 | 
 | 
T102 | 
8 | 
 | 
T266 | 
95 | 
Summary for Variable cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
1 | 
0 | 
1 | 
100.00 | 
User Defined Bins for cp_trans_type
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| alert_triggered | 
3811 | 
1 | 
 | 
 | 
T83 | 
1 | 
 | 
T102 | 
8 | 
 | 
T266 | 
95 | 
Summary for Cross alert_handshake_complete
Samples crossed: cp_handshake_complete cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
1 | 
0 | 
1 | 
100.00 | 
 | 
Automatically Generated Cross Bins for alert_handshake_complete
Bins
| cp_handshake_complete | cp_trans_type | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| complete | 
alert_triggered | 
3810 | 
1 | 
 | 
 | 
T83 | 
1 | 
 | 
T102 | 
8 | 
 | 
T266 | 
95 | 
 
Summary for Variable cp_handshake_complete
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
1 | 
0 | 
1 | 
100.00 | 
User Defined Bins for cp_handshake_complete
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| complete | 
84 | 
1 | 
 | 
 | 
T298 | 
1 | 
 | 
T83 | 
1 | 
 | 
T102 | 
1 | 
Summary for Variable cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
1 | 
0 | 
1 | 
100.00 | 
User Defined Bins for cp_trans_type
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| alert_triggered | 
84 | 
1 | 
 | 
 | 
T298 | 
1 | 
 | 
T83 | 
1 | 
 | 
T102 | 
1 | 
Summary for Cross alert_handshake_complete
Samples crossed: cp_handshake_complete cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
1 | 
0 | 
1 | 
100.00 | 
 | 
Automatically Generated Cross Bins for alert_handshake_complete
Bins
| cp_handshake_complete | cp_trans_type | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| complete | 
alert_triggered | 
84 | 
1 | 
 | 
 | 
T298 | 
1 | 
 | 
T83 | 
1 | 
 | 
T102 | 
1 | 
 
Summary for Variable cp_handshake_complete
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
1 | 
0 | 
1 | 
100.00 | 
User Defined Bins for cp_handshake_complete
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| complete | 
9904 | 
1 | 
 | 
 | 
T83 | 
1 | 
 | 
T102 | 
3 | 
 | 
T473 | 
1154 | 
Summary for Variable cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
1 | 
0 | 
1 | 
100.00 | 
User Defined Bins for cp_trans_type
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| alert_triggered | 
9906 | 
1 | 
 | 
 | 
T83 | 
1 | 
 | 
T102 | 
3 | 
 | 
T473 | 
1154 | 
Summary for Cross alert_handshake_complete
Samples crossed: cp_handshake_complete cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
1 | 
0 | 
1 | 
100.00 | 
 | 
Automatically Generated Cross Bins for alert_handshake_complete
Bins
| cp_handshake_complete | cp_trans_type | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| complete | 
alert_triggered | 
9904 | 
1 | 
 | 
 | 
T83 | 
1 | 
 | 
T102 | 
3 | 
 | 
T473 | 
1154 | 
 
Summary for Variable cp_handshake_complete
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
1 | 
0 | 
1 | 
100.00 | 
User Defined Bins for cp_handshake_complete
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| complete | 
118 | 
1 | 
 | 
 | 
T298 | 
1 | 
 | 
T83 | 
1 | 
 | 
T102 | 
4 | 
Summary for Variable cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
1 | 
0 | 
1 | 
100.00 | 
User Defined Bins for cp_trans_type
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| alert_triggered | 
118 | 
1 | 
 | 
 | 
T298 | 
1 | 
 | 
T83 | 
1 | 
 | 
T102 | 
4 | 
Summary for Cross alert_handshake_complete
Samples crossed: cp_handshake_complete cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
1 | 
0 | 
1 | 
100.00 | 
 | 
Automatically Generated Cross Bins for alert_handshake_complete
Bins
| cp_handshake_complete | cp_trans_type | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| complete | 
alert_triggered | 
118 | 
1 | 
 | 
 | 
T298 | 
1 | 
 | 
T83 | 
1 | 
 | 
T102 | 
4 |