Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.96 95.39 93.47 95.36 94.22 97.71 99.60


Total tests in report: 2930
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
39.40 39.40 45.68 45.68 43.93 43.93 24.68 24.68 58.70 58.70 63.29 63.29 0.13 0.13 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_device_pinmux_sleep_retention.2328773688
47.62 8.22 50.40 4.72 55.58 11.64 24.98 0.29 67.20 8.49 86.36 23.08 1.20 1.07 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_rw.249061715
53.13 5.52 62.04 11.64 63.52 7.94 27.85 2.87 77.84 10.65 86.36 0.00 1.20 0.00 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_plic_all_irqs_0.3907091489
57.97 4.84 72.50 10.46 65.50 1.98 34.79 6.95 78.50 0.66 86.36 0.00 10.19 8.99 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random.315715204
62.08 4.11 72.50 0.00 65.50 0.01 34.79 0.00 78.50 0.00 86.36 0.00 34.83 24.64 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_access_same_device_slow_rsp.529758393
65.26 3.18 77.66 5.16 69.47 3.97 38.39 3.60 80.28 1.78 90.91 4.55 34.83 0.00 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.2257647320
68.29 3.04 77.66 0.00 69.48 0.01 56.14 17.75 80.29 0.01 91.26 0.35 34.93 0.11 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.2032982923
71.11 2.82 77.80 0.14 71.24 1.77 56.83 0.69 80.58 0.28 91.26 0.00 48.95 14.02 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all_with_error.3965819642
73.83 2.72 77.80 0.00 71.39 0.15 56.83 0.00 80.59 0.02 91.26 0.00 65.10 16.16 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.899462360
76.12 2.29 79.35 1.54 74.13 2.73 61.83 5.00 82.44 1.85 91.61 0.35 67.37 2.27 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_test.704675342
77.76 1.64 83.25 3.90 75.89 1.77 64.53 2.70 83.56 1.12 91.96 0.35 67.37 0.00 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_power_virus.1533753562
79.17 1.40 83.54 0.29 76.04 0.15 72.17 7.64 83.74 0.18 92.13 0.17 67.37 0.00 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_prodend.1362335625
80.46 1.29 85.03 1.49 79.07 3.03 72.27 0.10 86.87 3.13 92.13 0.00 67.37 0.00 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.1305670900
81.58 1.13 85.03 0.00 79.07 0.00 72.27 0.00 86.87 0.00 92.13 0.00 74.14 6.77 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_access_same_device_slow_rsp.93005010
82.70 1.12 87.22 2.19 80.69 1.62 73.00 0.73 89.05 2.18 92.13 0.00 74.14 0.00 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_plic_all_irqs_20.3271276498
83.70 0.99 87.22 0.00 80.69 0.00 78.94 5.94 89.05 0.00 92.13 0.00 74.14 0.00 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_sideload_kmac.3354426397
84.62 0.93 87.22 0.00 80.69 0.00 78.94 0.00 89.05 0.00 92.13 0.00 79.71 5.57 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.3437851241
85.49 0.86 88.11 0.89 81.37 0.68 81.38 2.44 90.05 1.00 92.31 0.17 79.71 0.00 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_escalation.2328832670
86.31 0.83 88.83 0.72 81.55 0.18 81.39 0.01 90.24 0.19 96.15 3.85 79.71 0.00 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_address_translation.182508641
86.91 0.59 90.27 1.44 82.54 0.99 81.58 0.19 91.17 0.93 96.15 0.00 79.71 0.00 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.3039142094
87.49 0.58 91.24 0.97 83.12 0.58 83.01 1.43 91.69 0.52 96.15 0.00 79.71 0.00 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_gpio.145293088
88.07 0.58 91.24 0.00 83.12 0.00 83.01 0.00 91.69 0.00 96.15 0.00 83.20 3.49 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_access_same_device_slow_rsp.1768160371
88.61 0.54 91.24 0.00 83.30 0.18 83.01 0.00 91.71 0.02 96.15 0.00 86.23 3.03 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_stress_all.523704663
89.13 0.52 91.24 0.00 83.30 0.00 83.01 0.00 91.71 0.00 96.15 0.00 89.38 3.15 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.2108998015
89.65 0.51 91.73 0.48 85.31 2.00 83.05 0.04 91.88 0.17 96.15 0.00 89.77 0.39 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_mem_rw_with_rand_reset.3463797672
90.04 0.40 91.73 0.00 85.31 0.00 83.05 0.00 91.88 0.00 96.15 0.00 92.14 2.37 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_stress_all_with_error.2681393933
90.43 0.39 91.74 0.01 85.31 0.01 85.20 2.14 91.88 0.00 96.33 0.17 92.14 0.00 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_auto_mode.1328786834
90.82 0.39 92.47 0.73 85.97 0.66 85.38 0.18 92.62 0.75 96.33 0.00 92.14 0.00 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3660848620
91.18 0.37 92.47 0.00 86.39 0.41 85.38 0.00 92.62 0.00 96.33 0.00 93.93 1.79 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_access_same_device.4265523193
91.48 0.30 92.99 0.52 86.87 0.49 85.69 0.32 93.09 0.46 96.33 0.00 93.93 0.00 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_plic_all_irqs_10.645471026
91.77 0.29 93.11 0.12 86.91 0.03 87.23 1.54 93.11 0.02 96.33 0.00 93.93 0.00 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_debug_test_unlocked0.595905081
92.03 0.26 93.11 0.00 86.91 0.00 87.23 0.00 93.11 0.00 96.33 0.00 95.50 1.57 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.83128704
92.29 0.26 93.12 0.01 88.38 1.48 87.23 0.00 93.11 0.00 96.33 0.00 95.57 0.07 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_tl_errors.3950338092
92.53 0.24 93.25 0.13 88.46 0.07 88.44 1.21 93.16 0.05 96.33 0.00 95.57 0.00 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_pullup.2772542227
92.76 0.22 93.25 0.00 88.46 0.00 89.78 1.34 93.16 0.00 96.33 0.00 95.57 0.00 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_rma_unlocked.1892531916
92.97 0.22 93.25 0.00 88.48 0.02 89.78 0.00 93.16 0.00 96.33 0.00 96.85 1.28 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random_large_delays.3029794266
93.12 0.15 93.45 0.21 88.80 0.32 90.14 0.36 93.16 0.00 96.33 0.00 96.85 0.00 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.128207317
93.26 0.14 93.45 0.00 88.80 0.00 90.97 0.84 93.16 0.00 96.33 0.00 96.85 0.00 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.2947579810
93.39 0.13 93.56 0.10 88.84 0.04 91.58 0.60 93.18 0.02 96.33 0.00 96.85 0.00 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_entropy.795420628
93.51 0.12 93.56 0.00 89.10 0.26 91.58 0.00 93.20 0.02 96.33 0.00 97.32 0.47 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.1491334410
93.63 0.12 93.62 0.07 89.72 0.62 91.58 0.01 93.20 0.00 96.33 0.00 97.32 0.00 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_rw.483652756
93.74 0.11 93.62 0.00 90.03 0.31 91.59 0.01 93.56 0.36 96.33 0.00 97.32 0.00 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.3196326093
93.85 0.11 93.62 0.00 90.66 0.64 91.59 0.00 93.56 0.00 96.33 0.00 97.32 0.00 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_tl_errors.1114693959
93.95 0.11 93.87 0.25 90.78 0.12 91.60 0.01 93.63 0.07 96.50 0.17 97.33 0.01 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.2826839156
94.05 0.10 93.87 0.01 90.82 0.04 92.17 0.57 93.63 0.00 96.50 0.00 97.33 0.00 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_idx2.1548957796
94.15 0.10 94.06 0.19 90.95 0.13 92.30 0.13 93.76 0.13 96.50 0.00 97.33 0.00 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_reset.3674765664
94.24 0.09 94.06 0.00 90.95 0.01 92.30 0.00 93.76 0.00 96.50 0.00 97.90 0.56 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_stress_all_with_reset_error.3752234168
94.34 0.09 94.09 0.03 91.00 0.05 92.56 0.27 93.79 0.03 96.68 0.17 97.90 0.00 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_data_integrity_escalation.246954945
94.41 0.08 94.09 0.00 91.42 0.42 92.58 0.02 93.80 0.01 96.68 0.00 97.91 0.01 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_tl_errors.2890868409
94.48 0.07 94.11 0.01 91.44 0.02 92.58 0.01 93.83 0.02 97.03 0.35 97.91 0.00 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.1829567826
94.55 0.07 94.22 0.11 91.48 0.04 92.83 0.25 93.83 0.01 97.03 0.00 97.91 0.00 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_host_tx_rx.750359729
94.61 0.06 94.22 0.00 91.48 0.00 93.17 0.34 93.83 0.00 97.03 0.00 97.91 0.00 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.980648528
94.66 0.05 94.22 0.00 91.51 0.03 93.46 0.28 93.83 0.00 97.03 0.00 97.91 0.00 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.1508100275
94.70 0.04 94.23 0.01 91.54 0.03 93.47 0.01 93.85 0.02 97.20 0.17 97.92 0.01 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/17.chip_sw_all_escalation_resets.1810309364
94.74 0.04 94.23 0.00 91.62 0.08 93.56 0.09 93.92 0.07 97.20 0.00 97.92 0.00 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pin_retention.1738970415
94.78 0.04 94.32 0.09 91.62 0.00 93.70 0.14 93.93 0.01 97.20 0.00 97.92 0.00 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_tap_straps_testunlock0.1918509164
94.82 0.04 94.39 0.07 91.64 0.03 93.81 0.11 93.96 0.02 97.20 0.00 97.92 0.00 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.139229215
94.86 0.04 94.40 0.01 91.66 0.01 93.81 0.00 93.98 0.02 97.38 0.17 97.93 0.01 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.1701983175
94.90 0.04 94.43 0.03 91.68 0.02 93.81 0.00 93.99 0.01 97.55 0.17 97.93 0.00 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_data_integrity_escalation.4148536056
94.94 0.04 94.43 0.00 91.91 0.23 93.81 0.00 93.99 0.00 97.55 0.00 97.93 0.00 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.chip_tl_errors.1618387383
94.97 0.04 94.44 0.01 91.92 0.01 93.82 0.01 94.00 0.01 97.73 0.17 97.94 0.01 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/27.chip_sw_all_escalation_resets.352692371
95.01 0.03 94.47 0.03 91.98 0.06 93.92 0.11 94.00 0.01 97.73 0.00 97.94 0.00 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_hw_reset.1317867924
95.04 0.03 94.47 0.00 92.07 0.09 93.92 0.00 94.04 0.03 97.73 0.00 98.03 0.08 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_stress_all_with_rand_reset.2738965226
95.08 0.03 94.53 0.07 92.14 0.07 93.96 0.04 94.07 0.03 97.73 0.00 98.03 0.00 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pin_wake.1902412918
95.11 0.03 94.53 0.00 92.17 0.04 93.99 0.03 94.07 0.00 97.73 0.00 98.14 0.12 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all.3599334186
95.13 0.03 94.60 0.07 92.20 0.03 93.99 0.01 94.12 0.05 97.73 0.00 98.14 0.00 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sensor_ctrl_alert.2740303827
95.16 0.03 94.60 0.00 92.20 0.00 93.99 0.00 94.12 0.00 97.73 0.00 98.30 0.15 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_stress_all_with_reset_error.2993473174
95.18 0.03 94.60 0.00 92.21 0.01 94.14 0.15 94.12 0.00 97.73 0.00 98.30 0.00 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_jtag_csr_rw.2437862091
95.21 0.02 94.60 0.00 92.35 0.15 94.14 0.00 94.12 0.00 97.73 0.00 98.30 0.00 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_plic_all_irqs_0.2299073423
95.23 0.02 94.67 0.07 92.40 0.05 94.14 0.00 94.15 0.03 97.73 0.00 98.30 0.00 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_pin_wake.2663841827
95.25 0.02 94.67 0.00 92.40 0.00 94.26 0.12 94.15 0.00 97.73 0.00 98.31 0.01 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.114571503
95.27 0.02 94.67 0.00 92.40 0.00 94.39 0.13 94.15 0.00 97.73 0.00 98.31 0.00 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_dev.4147107723
95.29 0.02 94.67 0.00 92.51 0.11 94.39 0.00 94.15 0.00 97.73 0.00 98.31 0.00 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_plic_all_irqs_20.4267292035
95.31 0.02 94.67 0.00 92.52 0.01 94.49 0.10 94.15 0.00 97.73 0.00 98.31 0.00 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_device_pass_through_collision.2017178755
95.33 0.02 94.67 0.00 92.62 0.10 94.49 0.00 94.15 0.00 97.73 0.00 98.31 0.00 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_tl_errors.1991904353
95.34 0.02 94.67 0.00 92.71 0.10 94.49 0.00 94.15 0.00 97.73 0.00 98.31 0.00 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_plic_all_irqs_0.1597533413
95.36 0.02 94.67 0.00 92.75 0.04 94.49 0.00 94.15 0.00 97.73 0.00 98.37 0.06 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_stress_all.1151585859
95.38 0.02 94.67 0.00 92.75 0.00 94.59 0.09 94.15 0.00 97.73 0.00 98.37 0.00 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_rma_unlocked.1080613109
95.39 0.01 94.69 0.02 92.80 0.05 94.59 0.00 94.17 0.02 97.73 0.00 98.37 0.00 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_same_csr_outstanding.1054663669
95.40 0.01 94.71 0.02 92.81 0.01 94.64 0.05 94.17 0.01 97.73 0.00 98.37 0.00 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_cpu_info.3995874766
95.42 0.01 94.71 0.00 92.84 0.03 94.64 0.00 94.17 0.00 97.73 0.00 98.41 0.05 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_stress_all_with_rand_reset.1457070300
95.43 0.01 94.71 0.01 92.86 0.02 94.69 0.05 94.17 0.00 97.73 0.00 98.41 0.00 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3368188495
95.44 0.01 94.71 0.00 92.86 0.01 94.76 0.07 94.17 0.00 97.73 0.00 98.41 0.00 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke_zero_delays.72501605
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95.75 0.01 94.78 0.00 93.32 0.00 95.26 0.00 94.21 0.00 97.73 0.00 99.21 0.01 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.4011670857
95.75 0.01 94.78 0.00 93.32 0.00 95.26 0.00 94.21 0.00 97.73 0.00 99.22 0.01 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/32.chip_sw_all_escalation_resets.478389437
95.75 0.01 94.78 0.00 93.32 0.00 95.26 0.00 94.21 0.00 97.73 0.00 99.24 0.01 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/34.chip_sw_all_escalation_resets.3195258535
95.76 0.01 94.78 0.00 93.32 0.00 95.26 0.00 94.21 0.00 97.73 0.00 99.25 0.01 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.4289476168
95.76 0.01 94.78 0.00 93.32 0.00 95.26 0.00 94.21 0.00 97.73 0.00 99.26 0.01 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/35.chip_sw_all_escalation_resets.3620948104
95.76 0.01 94.78 0.00 93.32 0.00 95.26 0.00 94.21 0.00 97.73 0.00 99.27 0.01 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/36.chip_sw_all_escalation_resets.1989409123
95.76 0.01 94.78 0.00 93.32 0.00 95.26 0.00 94.21 0.00 97.73 0.00 99.28 0.01 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.1684778587
95.76 0.01 94.78 0.00 93.32 0.00 95.26 0.00 94.21 0.00 97.73 0.00 99.30 0.01 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/39.chip_sw_all_escalation_resets.3719966174
95.77 0.01 94.78 0.00 93.32 0.00 95.26 0.00 94.21 0.00 97.73 0.00 99.31 0.01 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/40.chip_sw_all_escalation_resets.3171265818
95.77 0.01 94.78 0.00 93.32 0.00 95.26 0.00 94.21 0.00 97.73 0.00 99.32 0.01 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.1454156199
95.77 0.01 94.78 0.00 93.32 0.00 95.26 0.00 94.21 0.00 97.73 0.00 99.33 0.01 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/44.chip_sw_all_escalation_resets.3207740241
95.77 0.01 94.78 0.00 93.32 0.00 95.26 0.00 94.21 0.00 97.73 0.00 99.34 0.01 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.2074042767
95.77 0.01 94.78 0.00 93.32 0.00 95.26 0.00 94.21 0.00 97.73 0.00 99.35 0.01 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/45.chip_sw_all_escalation_resets.917426127
95.78 0.01 94.78 0.00 93.32 0.00 95.26 0.00 94.21 0.00 97.73 0.00 99.37 0.01 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.3835802973
95.78 0.01 94.78 0.00 93.32 0.00 95.26 0.00 94.21 0.00 97.73 0.00 99.38 0.01 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.3146502087
95.78 0.01 94.78 0.00 93.32 0.00 95.26 0.00 94.21 0.00 97.73 0.00 99.39 0.01 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.1682675580
95.78 0.01 94.78 0.00 93.32 0.00 95.26 0.00 94.21 0.00 97.73 0.00 99.40 0.01 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.362728245
95.78 0.01 94.78 0.00 93.32 0.00 95.26 0.00 94.21 0.00 97.73 0.00 99.41 0.01 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/51.chip_sw_all_escalation_resets.4246042714
95.79 0.01 94.78 0.00 93.32 0.00 95.26 0.00 94.21 0.00 97.73 0.00 99.42 0.01 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.3753550234
95.79 0.01 94.78 0.00 93.32 0.00 95.26 0.00 94.21 0.00 97.73 0.00 99.44 0.01 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/52.chip_sw_all_escalation_resets.3597139504
95.79 0.01 94.78 0.00 93.32 0.00 95.26 0.00 94.21 0.00 97.73 0.00 99.45 0.01 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/54.chip_sw_all_escalation_resets.1555745145
95.79 0.01 94.78 0.00 93.32 0.00 95.26 0.00 94.21 0.00 97.73 0.00 99.46 0.01 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.1319982490
95.79 0.01 94.78 0.00 93.32 0.00 95.26 0.00 94.21 0.00 97.73 0.00 99.47 0.01 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/59.chip_sw_all_escalation_resets.1433237480
95.80 0.01 94.78 0.00 93.32 0.00 95.26 0.00 94.21 0.00 97.73 0.00 99.48 0.01 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.4033488501
95.80 0.01 94.78 0.00 93.32 0.00 95.26 0.00 94.21 0.00 97.73 0.00 99.49 0.01 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.498940890
95.80 0.01 94.78 0.00 93.32 0.00 95.26 0.00 94.21 0.00 97.73 0.00 99.51 0.01 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.2936340143
95.80 0.01 94.78 0.00 93.32 0.00 95.26 0.00 94.21 0.00 97.73 0.00 99.52 0.01 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/67.chip_sw_all_escalation_resets.3799903063
95.80 0.01 94.78 0.00 93.32 0.00 95.26 0.00 94.21 0.00 97.73 0.00 99.53 0.01 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/69.chip_sw_all_escalation_resets.3875993600
95.81 0.01 94.78 0.00 93.32 0.00 95.26 0.00 94.21 0.00 97.73 0.00 99.54 0.01 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.37608834
95.81 0.01 94.78 0.00 93.32 0.00 95.26 0.00 94.21 0.00 97.73 0.00 99.55 0.01 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/71.chip_sw_all_escalation_resets.662269067
95.81 0.01 94.78 0.00 93.32 0.00 95.26 0.00 94.21 0.00 97.73 0.00 99.57 0.01 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.4247274381
95.81 0.01 94.78 0.00 93.32 0.00 95.26 0.00 94.21 0.00 97.73 0.00 99.58 0.01 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/75.chip_sw_all_escalation_resets.3428993905
95.81 0.01 94.78 0.00 93.32 0.00 95.26 0.00 94.21 0.00 97.73 0.00 99.59 0.01 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/81.chip_sw_all_escalation_resets.2712349361
95.82 0.01 94.78 0.00 93.32 0.00 95.26 0.00 94.21 0.00 97.73 0.00 99.60 0.01 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.4228067095
95.82 0.01 94.78 0.00 93.32 0.00 95.27 0.01 94.21 0.00 97.73 0.00 99.60 0.00 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.1939056178
95.82 0.01 94.78 0.00 93.33 0.01 95.27 0.00 94.21 0.00 97.73 0.00 99.60 0.00 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_stress_all.81810302
95.82 0.01 94.78 0.00 93.34 0.01 95.27 0.00 94.21 0.00 97.73 0.00 99.60 0.00 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.chip_tl_errors.1383239754
95.82 0.01 94.78 0.00 93.35 0.01 95.27 0.00 94.21 0.00 97.73 0.00 99.60 0.00 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_entropy_src_csrng.1098863704
95.82 0.01 94.78 0.00 93.36 0.01 95.27 0.00 94.21 0.00 97.73 0.00 99.60 0.00 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.2143753619
95.83 0.01 94.78 0.00 93.37 0.01 95.27 0.00 94.21 0.00 97.73 0.00 99.60 0.00 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.1677094239
95.83 0.01 94.78 0.00 93.38 0.01 95.27 0.00 94.21 0.00 97.73 0.00 99.60 0.00 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.2612955004
95.83 0.01 94.78 0.01 93.38 0.00 95.28 0.01 94.21 0.00 97.73 0.00 99.60 0.00 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/53.chip_sw_all_escalation_resets.3583254812
95.83 0.01 94.78 0.00 93.38 0.00 95.29 0.01 94.21 0.00 97.73 0.00 99.60 0.00 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.3397390534
95.83 0.01 94.78 0.00 93.38 0.00 95.30 0.01 94.21 0.00 97.73 0.00 99.60 0.00 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.281265504
95.83 0.01 94.78 0.00 93.39 0.01 95.31 0.01 94.21 0.00 97.73 0.00 99.60 0.00 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_hw_reset.4109239630
95.84 0.01 94.78 0.00 93.39 0.00 95.31 0.00 94.22 0.01 97.73 0.00 99.60 0.00 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.2453237909
95.84 0.01 94.78 0.00 93.39 0.00 95.31 0.00 94.22 0.01 97.73 0.00 99.60 0.00 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_tap_straps_dev.1729706238
95.84 0.01 94.78 0.00 93.39 0.01 95.31 0.00 94.22 0.00 97.73 0.00 99.60 0.00 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_stress_all.4150943218
95.84 0.01 94.78 0.00 93.40 0.01 95.31 0.00 94.22 0.00 97.73 0.00 99.60 0.00 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_stress_all.2660873854
95.84 0.01 94.78 0.00 93.41 0.01 95.31 0.00 94.22 0.00 97.73 0.00 99.60 0.00 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_stress_all_with_error.4262055706
95.84 0.01 94.78 0.00 93.41 0.01 95.31 0.00 94.22 0.00 97.73 0.00 99.60 0.00 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_alert_info.1171347372
95.84 0.01 94.78 0.00 93.42 0.01 95.31 0.00 94.22 0.00 97.73 0.00 99.60 0.00 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_gpio.419705065
95.84 0.01 94.78 0.00 93.42 0.00 95.31 0.01 94.22 0.00 97.73 0.00 99.60 0.00 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.1113959095
95.84 0.01 94.78 0.01 93.42 0.00 95.31 0.01 94.22 0.00 97.73 0.00 99.60 0.00 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_host_tx_rx.1433311874
95.85 0.01 94.78 0.00 93.42 0.00 95.32 0.01 94.22 0.00 97.73 0.00 99.60 0.00 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.3057463180
95.85 0.01 94.78 0.00 93.42 0.00 95.32 0.01 94.22 0.00 97.73 0.00 99.60 0.00 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.1124093454
95.85 0.01 94.78 0.00 93.42 0.00 95.33 0.01 94.22 0.00 97.73 0.00 99.60 0.00 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_program_error.4258427135
95.85 0.01 94.78 0.00 93.42 0.00 95.33 0.01 94.22 0.00 97.73 0.00 99.60 0.00 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.1168182900
95.85 0.01 94.78 0.00 93.42 0.00 95.34 0.01 94.22 0.00 97.73 0.00 99.60 0.00 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.195751197
95.85 0.01 94.78 0.00 93.42 0.00 95.34 0.01 94.22 0.00 97.73 0.00 99.60 0.00 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.1300799734
95.85 0.01 94.78 0.00 93.42 0.00 95.35 0.01 94.22 0.00 97.73 0.00 99.60 0.00 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.2524156836
95.85 0.01 94.78 0.00 93.42 0.01 95.35 0.00 94.22 0.00 97.73 0.00 99.60 0.00 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_same_source.659234429
95.85 0.01 94.78 0.00 93.43 0.01 95.35 0.00 94.22 0.00 97.73 0.00 99.60 0.00 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.chip_tl_errors.11834395
95.85 0.01 94.78 0.00 93.43 0.01 95.35 0.00 94.22 0.00 97.73 0.00 99.60 0.00 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_stress_all_with_error.1691341435
95.85 0.01 94.78 0.00 93.44 0.01 95.35 0.00 94.22 0.00 97.73 0.00 99.60 0.00 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_stress_all_with_error.2952086382
95.85 0.01 94.78 0.00 93.44 0.01 95.35 0.00 94.22 0.00 97.73 0.00 99.60 0.00 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_stress_all_with_error.3825179932
95.85 0.01 94.78 0.00 93.44 0.01 95.35 0.00 94.22 0.00 97.73 0.00 99.60 0.00 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_stress_all_with_reset_error.2231563341
95.85 0.01 94.78 0.00 93.45 0.01 95.35 0.00 94.22 0.00 97.73 0.00 99.60 0.00 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_stress_all_with_reset_error.1330328967
95.86 0.01 94.78 0.00 93.45 0.01 95.35 0.00 94.22 0.00 97.73 0.00 99.60 0.00 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1869044760
95.86 0.01 94.78 0.00 93.45 0.01 95.35 0.00 94.22 0.00 97.73 0.00 99.60 0.00 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.1441774412
95.86 0.01 94.78 0.00 93.46 0.01 95.35 0.00 94.22 0.00 97.73 0.00 99.60 0.00 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pattgen_ios.2620684142
95.86 0.01 94.78 0.00 93.46 0.01 95.35 0.00 94.22 0.00 97.73 0.00 99.60 0.00 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.2515837909
95.86 0.01 94.78 0.00 93.46 0.01 95.35 0.00 94.22 0.00 97.73 0.00 99.60 0.00 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.281341273
95.86 0.01 94.78 0.00 93.47 0.01 95.35 0.00 94.22 0.00 97.73 0.00 99.60 0.00 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_gpio.544984516
95.86 0.01 94.78 0.00 93.47 0.00 95.35 0.01 94.22 0.00 97.73 0.00 99.60 0.00 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_ping_ok.885822273
95.86 0.01 94.78 0.00 93.47 0.00 95.35 0.01 94.22 0.00 97.73 0.00 99.60 0.00 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_aes_trans.1335774234
95.86 0.01 94.78 0.00 93.47 0.00 95.35 0.01 94.22 0.00 97.73 0.00 99.60 0.00 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_boot_mode.4098365187
95.86 0.01 94.78 0.00 93.47 0.00 95.36 0.01 94.22 0.00 97.73 0.00 99.60 0.00 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_sideload_aes.2995644887
95.86 0.01 94.78 0.00 93.47 0.00 95.36 0.01 94.22 0.00 97.73 0.00 99.60 0.00 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_sideload_otbn.1709971978
95.86 0.01 94.78 0.00 93.47 0.00 95.36 0.01 94.22 0.00 97.73 0.00 99.60 0.00 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_execution_main.2624093990
95.86 0.01 94.78 0.00 93.47 0.00 95.36 0.01 94.22 0.00 97.73 0.00 99.60 0.00 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.139949142
95.86 0.01 94.78 0.00 93.47 0.00 95.36 0.01 94.22 0.00 97.73 0.00 99.60 0.00 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.3645945533

Tests that do not contribute to grading

Name   
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_aliasing.1523558722
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_bit_bash.2506435368
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/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.915541859
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.3189286277
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.2978532156



Total test records in report: 2930
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TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_example_rom.2725930177 Feb 09 05:29:05 PM UTC 25 Feb 09 05:30:33 PM UTC 25 2022353130 ps
T2 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pattgen_ios.2620684142 Feb 09 05:31:03 PM UTC 25 Feb 09 05:33:53 PM UTC 25 2835669944 ps
T3 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_example_flash.2682579288 Feb 09 05:33:33 PM UTC 25 Feb 09 05:36:32 PM UTC 25 2904295178 ps
T4 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_example_manufacturer.1113937913 Feb 09 05:33:29 PM UTC 25 Feb 09 05:37:00 PM UTC 25 3314928648 ps
T38 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_toggle_restore.424537835 Feb 09 05:33:15 PM UTC 25 Feb 09 05:37:00 PM UTC 25 2587571480 ps
T5 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pin_wake.1902412918 Feb 09 05:33:56 PM UTC 25 Feb 09 05:37:01 PM UTC 25 2599313728 ps
T106 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_example_concurrency.2783012809 Feb 09 05:34:26 PM UTC 25 Feb 09 05:38:57 PM UTC 25 2771224400 ps
T6 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_device_pinmux_sleep_retention.2328773688 Feb 09 05:34:31 PM UTC 25 Feb 09 05:39:07 PM UTC 25 2516493045 ps
T39 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_vbus.1832845400 Feb 09 05:34:25 PM UTC 25 Feb 09 05:39:25 PM UTC 25 2950505880 ps
T7 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_pullup.2772542227 Feb 09 05:33:58 PM UTC 25 Feb 09 05:39:34 PM UTC 25 3006939524 ps
T8 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_aon_pullup.2315647623 Feb 09 05:32:39 PM UTC 25 Feb 09 05:39:41 PM UTC 25 3675348416 ps
T121 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sival_flash_info_access.3577643643 Feb 09 05:35:05 PM UTC 25 Feb 09 05:40:03 PM UTC 25 3470107268 ps
T122 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.3990817428 Feb 09 05:35:15 PM UTC 25 Feb 09 05:40:15 PM UTC 25 2739839894 ps
T10 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_host_tx_rx.750359729 Feb 09 05:35:14 PM UTC 25 Feb 09 05:40:23 PM UTC 25 3180763032 ps
T14 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_device_tpm.1417004602 Feb 09 05:34:30 PM UTC 25 Feb 09 05:40:25 PM UTC 25 2950145967 ps
T27 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pin_retention.1738970415 Feb 09 05:34:58 PM UTC 25 Feb 09 05:40:28 PM UTC 25 3353831584 ps
T44 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.2501218248 Feb 09 05:38:28 PM UTC 25 Feb 09 05:41:00 PM UTC 25 2400064416 ps
T31 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_idx2.1548957796 Feb 09 05:32:09 PM UTC 25 Feb 09 05:41:08 PM UTC 25 4161506764 ps
T28 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_gpio.145293088 Feb 09 05:34:29 PM UTC 25 Feb 09 05:41:30 PM UTC 25 3447931552 ps
T29 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_idx3.3960234254 Feb 09 05:33:57 PM UTC 25 Feb 09 05:41:55 PM UTC 25 3849018458 ps
T9 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_setuprx.1781256688 Feb 09 05:33:02 PM UTC 25 Feb 09 05:42:14 PM UTC 25 4205738608 ps
T267 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.1389907194 Feb 09 05:35:08 PM UTC 25 Feb 09 05:42:21 PM UTC 25 3674882542 ps
T35 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_i2c_device_tx_rx.3983882519 Feb 09 05:34:28 PM UTC 25 Feb 09 05:42:28 PM UTC 25 3461189512 ps
T184 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.472892920 Feb 09 05:38:44 PM UTC 25 Feb 09 05:42:29 PM UTC 25 3145880704 ps
T46 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.2032982923 Feb 09 05:33:59 PM UTC 25 Feb 09 05:42:37 PM UTC 25 5243881461 ps
T131 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx.188622421 Feb 09 05:33:19 PM UTC 25 Feb 09 05:43:04 PM UTC 25 3904570668 ps
T34 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.3364195204 Feb 09 05:34:26 PM UTC 25 Feb 09 05:43:15 PM UTC 25 3807641572 ps
T11 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_device_pass_through_collision.2017178755 Feb 09 05:35:06 PM UTC 25 Feb 09 05:44:11 PM UTC 25 4150751394 ps
T225 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_ops.856020271 Feb 09 05:34:26 PM UTC 25 Feb 09 05:44:17 PM UTC 25 3835211254 ps
T145 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.1997735991 Feb 09 05:33:16 PM UTC 25 Feb 09 05:44:17 PM UTC 25 4495026256 ps
T32 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_idx1.2052737844 Feb 09 05:35:13 PM UTC 25 Feb 09 05:44:36 PM UTC 25 4087683196 ps
T36 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3496874350 Feb 09 05:42:39 PM UTC 25 Feb 09 05:44:37 PM UTC 25 2434764294 ps
T53 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.1027052683 Feb 09 05:34:59 PM UTC 25 Feb 09 05:45:01 PM UTC 25 4893050120 ps
T37 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.3290288907 Feb 09 05:33:52 PM UTC 25 Feb 09 05:45:07 PM UTC 25 4563238566 ps
T68 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_i2c_host_tx_rx.1869106686 Feb 09 05:33:49 PM UTC 25 Feb 09 05:45:08 PM UTC 25 4266352388 ps
T47 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.2947579810 Feb 09 05:41:22 PM UTC 25 Feb 09 05:45:25 PM UTC 25 3131313851 ps
T88 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_data_integrity_escalation.246954945 Feb 09 05:33:50 PM UTC 25 Feb 09 05:45:29 PM UTC 25 5431324880 ps
T48 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.2363862008 Feb 09 05:43:05 PM UTC 25 Feb 09 05:45:46 PM UTC 25 3132055258 ps
T66 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.121625926 Feb 09 05:43:15 PM UTC 25 Feb 09 05:45:47 PM UTC 25 3146263539 ps
T150 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.1774011072 Feb 09 05:43:06 PM UTC 25 Feb 09 05:45:51 PM UTC 25 3488266226 ps
T192 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.1248353373 Feb 09 05:43:36 PM UTC 25 Feb 09 05:45:56 PM UTC 25 2480241599 ps
T89 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_all_escalation_resets.3398334412 Feb 09 05:33:56 PM UTC 25 Feb 09 05:46:02 PM UTC 25 6126240548 ps
T12 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_device_pass_through.2749873984 Feb 09 05:33:05 PM UTC 25 Feb 09 05:46:21 PM UTC 25 7264842587 ps
T242 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.77097373 Feb 09 05:35:00 PM UTC 25 Feb 09 05:46:49 PM UTC 25 4275496582 ps
T315 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_sw_rst.4195558102 Feb 09 05:43:36 PM UTC 25 Feb 09 05:47:44 PM UTC 25 3082504848 ps
T188 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_escalation.2328832670 Feb 09 05:38:42 PM UTC 25 Feb 09 05:47:59 PM UTC 25 5369502900 ps
T71 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.1441774412 Feb 09 05:35:03 PM UTC 25 Feb 09 05:48:29 PM UTC 25 5067466270 ps
T224 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_sw_req.2284436863 Feb 09 05:43:05 PM UTC 25 Feb 09 05:49:38 PM UTC 25 4285173936 ps
T659 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.989653447 Feb 09 05:43:47 PM UTC 25 Feb 09 05:51:14 PM UTC 25 3438570305 ps
T466 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_access.3237006204 Feb 09 05:33:50 PM UTC 25 Feb 09 05:51:43 PM UTC 25 5587462436 ps
T146 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.1824761900 Feb 09 05:35:14 PM UTC 25 Feb 09 05:51:50 PM UTC 25 6152309103 ps
T358 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.887168081 Feb 09 05:46:31 PM UTC 25 Feb 09 05:51:56 PM UTC 25 3432259860 ps
T127 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_timer_irq.1089376609 Feb 09 05:46:24 PM UTC 25 Feb 09 05:51:56 PM UTC 25 3595960424 ps
T147 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.1305757005 Feb 09 05:35:13 PM UTC 25 Feb 09 05:52:21 PM UTC 25 5784409152 ps
T33 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_inputs.3732764626 Feb 09 05:47:46 PM UTC 25 Feb 09 05:52:37 PM UTC 25 2492769498 ps
T277 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.114571503 Feb 09 05:46:39 PM UTC 25 Feb 09 05:52:56 PM UTC 25 5512828476 ps
T196 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.1901905872 Feb 09 05:35:02 PM UTC 25 Feb 09 05:53:20 PM UTC 25 7539179126 ps
T434 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.1897515580 Feb 09 05:47:47 PM UTC 25 Feb 09 05:53:33 PM UTC 25 4546551088 ps
T15 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_outputs.64707878 Feb 09 05:47:55 PM UTC 25 Feb 09 05:53:42 PM UTC 25 3313863347 ps
T138 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2350381209 Feb 09 05:47:55 PM UTC 25 Feb 09 05:54:19 PM UTC 25 17709029370 ps
T154 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.195751197 Feb 09 05:46:14 PM UTC 25 Feb 09 05:54:26 PM UTC 25 6545787512 ps
T268 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aon_timer_irq.3208532368 Feb 09 05:47:09 PM UTC 25 Feb 09 05:54:32 PM UTC 25 3132536600 ps
T43 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pwm_pulses.905654896 Feb 09 05:33:16 PM UTC 25 Feb 09 05:54:37 PM UTC 25 9492948872 ps
T162 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.1939056178 Feb 09 05:44:20 PM UTC 25 Feb 09 05:54:59 PM UTC 25 6318684395 ps
T197 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.235685598 Feb 09 05:35:29 PM UTC 25 Feb 09 05:55:19 PM UTC 25 7088791160 ps
T901 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_descrambling.788620273 Feb 09 05:43:58 PM UTC 25 Feb 09 05:55:23 PM UTC 25 4270630072 ps
T18 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.861447325 Feb 09 05:47:41 PM UTC 25 Feb 09 05:55:26 PM UTC 25 5865272500 ps
T241 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_cpu_info.3995874766 Feb 09 05:44:18 PM UTC 25 Feb 09 05:56:08 PM UTC 25 6336119626 ps
T293 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.3892837023 Feb 09 05:47:44 PM UTC 25 Feb 09 05:56:25 PM UTC 25 6631661976 ps
T244 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.350281452 Feb 09 05:37:12 PM UTC 25 Feb 09 05:56:33 PM UTC 25 7706327458 ps
T269 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_wdog_reset.2902634036 Feb 09 05:47:54 PM UTC 25 Feb 09 05:56:39 PM UTC 25 5001656628 ps
T294 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_enc.227022164 Feb 09 05:52:58 PM UTC 25 Feb 09 05:57:18 PM UTC 25 3734870790 ps
T295 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.1546114559 Feb 09 05:47:55 PM UTC 25 Feb 09 05:57:37 PM UTC 25 4644501560 ps
T296 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_enc_jitter_en.428892572 Feb 09 05:53:15 PM UTC 25 Feb 09 05:58:29 PM UTC 25 2554506132 ps
T209 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_mem_scramble.893311865 Feb 09 05:50:17 PM UTC 25 Feb 09 05:58:29 PM UTC 25 4115554300 ps
T297 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_idle.2512179783 Feb 09 05:53:15 PM UTC 25 Feb 09 05:58:43 PM UTC 25 3681239816 ps
T298 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_masking_off.3996195566 Feb 09 05:53:14 PM UTC 25 Feb 09 05:59:00 PM UTC 25 3326348554 ps
T83 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_test.704675342 Feb 09 05:53:16 PM UTC 25 Feb 09 05:59:02 PM UTC 25 4034702800 ps
T72 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_rand_baudrate.1443844323 Feb 09 05:33:29 PM UTC 25 Feb 09 05:59:11 PM UTC 25 8678466472 ps
T76 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.1387927402 Feb 09 05:44:24 PM UTC 25 Feb 09 05:59:23 PM UTC 25 10656965866 ps
T193 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_prodend.1362335625 Feb 09 05:44:01 PM UTC 25 Feb 09 05:59:27 PM UTC 25 6725708616 ps
T158 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_entropy_src_kat_test.4261412628 Feb 09 05:55:42 PM UTC 25 Feb 09 05:59:47 PM UTC 25 3052952000 ps
T137 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.3128114840 Feb 09 05:45:47 PM UTC 25 Feb 09 05:59:49 PM UTC 25 7570000016 ps
T356 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_ping_timeout.248541967 Feb 09 05:54:03 PM UTC 25 Feb 09 05:59:51 PM UTC 25 2890142508 ps
T75 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.1268470319 Feb 09 05:47:50 PM UTC 25 Feb 09 06:00:01 PM UTC 25 4266957120 ps
T415 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_entropy.3387365234 Feb 09 05:55:36 PM UTC 25 Feb 09 06:00:43 PM UTC 25 3532713832 ps
T416 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_kat_test.3525608264 Feb 09 05:57:27 PM UTC 25 Feb 09 06:00:50 PM UTC 25 2893012812 ps
T102 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_entropy.795420628 Feb 09 05:55:39 PM UTC 25 Feb 09 06:00:53 PM UTC 25 3119252893 ps
T214 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_transition.1040440429 Feb 09 05:42:17 PM UTC 25 Feb 09 06:01:07 PM UTC 25 12589010377 ps
T223 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_escalation.1768517751 Feb 09 05:53:19 PM UTC 25 Feb 09 06:01:12 PM UTC 25 4236636308 ps
T660 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.1342692679 Feb 09 05:44:21 PM UTC 25 Feb 09 06:01:26 PM UTC 25 6811893020 ps
T473 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.3214972921 Feb 09 05:54:08 PM UTC 25 Feb 09 06:01:27 PM UTC 25 3360396464 ps
T19 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_config_host.1824264434 Feb 09 05:33:12 PM UTC 25 Feb 09 06:01:32 PM UTC 25 7590946348 ps
T902 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.3157329273 Feb 09 05:47:54 PM UTC 25 Feb 09 06:01:36 PM UTC 25 8369286272 ps
T159 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_entropy_src_ast_rng_req.315217146 Feb 09 05:58:14 PM UTC 25 Feb 09 06:01:55 PM UTC 25 2799413548 ps
T73 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3368188495 Feb 09 05:33:19 PM UTC 25 Feb 09 06:01:59 PM UTC 25 13062812431 ps
T375 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.139229215 Feb 09 05:44:25 PM UTC 25 Feb 09 06:03:59 PM UTC 25 7398520303 ps
T160 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_randomness.1890803470 Feb 09 05:48:21 PM UTC 25 Feb 09 06:04:12 PM UTC 25 6154755104 ps
T155 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_boot_mode.4098365187 Feb 09 05:56:19 PM UTC 25 Feb 09 06:04:43 PM UTC 25 3107835248 ps
T347 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_enc_jitter_en.2631858334 Feb 09 06:00:53 PM UTC 25 Feb 09 06:04:59 PM UTC 25 2401873425 ps
T212 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.1916703449 Feb 09 05:57:57 PM UTC 25 Feb 09 06:06:09 PM UTC 25 4179265940 ps
T467 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_idle.1417944906 Feb 09 06:02:52 PM UTC 25 Feb 09 06:06:26 PM UTC 25 2206243164 ps
T475 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.281341273 Feb 09 05:51:49 PM UTC 25 Feb 09 06:06:34 PM UTC 25 5116624636 ps
T156 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.980648528 Feb 09 05:57:24 PM UTC 25 Feb 09 06:06:53 PM UTC 25 6482090799 ps
T348 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_enc.530447497 Feb 09 06:00:19 PM UTC 25 Feb 09 06:06:57 PM UTC 25 3410108232 ps
T157 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_kat.4170050666 Feb 09 05:56:19 PM UTC 25 Feb 09 06:06:59 PM UTC 25 3053545650 ps
T274 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_rnd.712277952 Feb 09 05:50:59 PM UTC 25 Feb 09 06:07:09 PM UTC 25 5684119562 ps
T438 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_app_rom.549637450 Feb 09 06:03:16 PM UTC 25 Feb 09 06:08:10 PM UTC 25 3187580716 ps
T395 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3819094582 Feb 09 05:44:18 PM UTC 25 Feb 09 06:08:10 PM UTC 25 10137365951 ps
T903 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.678868749 Feb 09 05:44:16 PM UTC 25 Feb 09 06:08:16 PM UTC 25 14319224741 ps
T667 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_oneshot.336295560 Feb 09 06:01:39 PM UTC 25 Feb 09 06:08:16 PM UTC 25 2986419654 ps
T468 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.2333309924 Feb 09 06:03:09 PM UTC 25 Feb 09 06:08:46 PM UTC 25 2352242378 ps
T469 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_mode_cshake.431601942 Feb 09 06:03:08 PM UTC 25 Feb 09 06:08:58 PM UTC 25 2469854132 ps
T904 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_enc_idle.684165689 Feb 09 06:03:03 PM UTC 25 Feb 09 06:09:03 PM UTC 25 3354610860 ps
T905 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_mode_kmac.3631637855 Feb 09 06:02:53 PM UTC 25 Feb 09 06:09:07 PM UTC 25 3234401026 ps
T177 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sensor_ctrl_status.4264909380 Feb 09 06:05:38 PM UTC 25 Feb 09 06:09:37 PM UTC 25 2678964136 ps
T275 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_auto_mode.1328786834 Feb 09 05:56:19 PM UTC 25 Feb 09 06:10:58 PM UTC 25 3870447598 ps
T201 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_init.1049464327 Feb 09 05:33:52 PM UTC 25 Feb 09 06:11:09 PM UTC 25 26761413120 ps
T203 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.1706915050 Feb 09 06:03:04 PM UTC 25 Feb 09 06:12:02 PM UTC 25 4375772176 ps
T346 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_plic_all_irqs_20.3271276498 Feb 09 06:08:09 PM UTC 25 Feb 09 06:21:13 PM UTC 25 4609896040 ps
T189 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_alert_info.1171347372 Feb 09 05:43:16 PM UTC 25 Feb 09 06:12:03 PM UTC 25 9938055768 ps
T300 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rom_ctrl_integrity_check.1223717689 Feb 09 06:03:17 PM UTC 25 Feb 09 06:12:08 PM UTC 25 9028618399 ps
T470 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_entropy.2302938797 Feb 09 05:35:12 PM UTC 25 Feb 09 06:12:12 PM UTC 25 10238584300 ps
T16 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_reset.3674765664 Feb 09 05:46:58 PM UTC 25 Feb 09 06:13:24 PM UTC 25 23019418060 ps
T283 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_plic_sw_irq.3898881488 Feb 09 06:08:08 PM UTC 25 Feb 09 06:14:24 PM UTC 25 2754114120 ps
T163 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.128207317 Feb 09 06:06:50 PM UTC 25 Feb 09 06:14:45 PM UTC 25 5386479126 ps
T148 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.1508100275 Feb 09 06:03:08 PM UTC 25 Feb 09 06:15:18 PM UTC 25 5156489683 ps
T265 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_ping_ok.885822273 Feb 09 05:54:02 PM UTC 25 Feb 09 06:15:50 PM UTC 25 7730877304 ps
T479 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.1235899720 Feb 09 06:04:49 PM UTC 25 Feb 09 06:17:00 PM UTC 25 6732851272 ps
T164 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sensor_ctrl_alert.2740303827 Feb 09 06:05:18 PM UTC 25 Feb 09 06:17:12 PM UTC 25 6832232620 ps
T906 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_jitter.233565728 Feb 09 06:13:23 PM UTC 25 Feb 09 06:18:01 PM UTC 25 3120168530 ps
T262 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_entropy_reqs.1374592490 Feb 09 06:01:04 PM UTC 25 Feb 09 06:18:13 PM UTC 25 6081951000 ps
T907 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.2756431300 Feb 09 06:10:03 PM UTC 25 Feb 09 06:18:16 PM UTC 25 4616544820 ps
T128 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_plic_all_irqs_10.645471026 Feb 09 06:08:03 PM UTC 25 Feb 09 06:18:45 PM UTC 25 4022488360 ps
T648 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_sw_mode.3334077765 Feb 09 05:56:46 PM UTC 25 Feb 09 06:19:01 PM UTC 25 6599007750 ps
T243 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_sideload_kmac.3354426397 Feb 09 06:01:27 PM UTC 25 Feb 09 06:19:29 PM UTC 25 7024643038 ps
T908 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.1998892584 Feb 09 06:10:00 PM UTC 25 Feb 09 06:19:43 PM UTC 25 4903169898 ps
T195 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.2371176680 Feb 09 05:42:41 PM UTC 25 Feb 09 06:20:23 PM UTC 25 24096409832 ps
T671 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_reset_frequency.3471317427 Feb 09 06:13:26 PM UTC 25 Feb 09 06:20:27 PM UTC 25 2743299376 ps
T204 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.4179761617 Feb 09 06:04:53 PM UTC 25 Feb 09 06:20:36 PM UTC 25 7590167050 ps
T151 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.895683715 Feb 09 06:10:15 PM UTC 25 Feb 09 06:21:10 PM UTC 25 4030781630 ps
T909 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.3631157953 Feb 09 06:10:01 PM UTC 25 Feb 09 06:21:27 PM UTC 25 5178595216 ps
T142 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.374773679 Feb 09 06:01:01 PM UTC 25 Feb 09 06:21:47 PM UTC 25 6765842059 ps
T152 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.901835208 Feb 09 06:10:20 PM UTC 25 Feb 09 06:21:52 PM UTC 25 4452428854 ps
T910 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_aes_trans.1335774234 Feb 09 06:09:45 PM UTC 25 Feb 09 06:22:06 PM UTC 25 5985743840 ps
T205 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_execution_main.2624093990 Feb 09 06:03:16 PM UTC 25 Feb 09 06:22:46 PM UTC 25 10774038191 ps
T153 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.4256391256 Feb 09 06:11:49 PM UTC 25 Feb 09 06:23:07 PM UTC 25 4169678920 ps
T341 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3934787773 Feb 09 06:10:20 PM UTC 25 Feb 09 06:23:22 PM UTC 25 4484689776 ps
T95 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_tap_straps_rma.2497177714 Feb 09 06:20:58 PM UTC 25 Feb 09 06:23:24 PM UTC 25 2847353667 ps
T342 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3607796001 Feb 09 06:11:47 PM UTC 25 Feb 09 06:23:57 PM UTC 25 4621784424 ps
T343 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.598089780 Feb 09 06:13:21 PM UTC 25 Feb 09 06:24:36 PM UTC 25 4561475530 ps
T40 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_tap_straps_prod.2834786090 Feb 09 06:21:05 PM UTC 25 Feb 09 06:24:38 PM UTC 25 2911438774 ps
T215 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.1124093454 Feb 09 06:10:15 PM UTC 25 Feb 09 06:25:13 PM UTC 25 10756129867 ps
T344 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_plic_all_irqs_0.3907091489 Feb 09 06:08:07 PM UTC 25 Feb 09 06:25:30 PM UTC 25 6245623926 ps
T80 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3660848620 Feb 09 06:16:28 PM UTC 25 Feb 09 06:25:40 PM UTC 25 7448485312 ps
T92 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_dm_access_after_wakeup.1597321101 Feb 09 06:20:08 PM UTC 25 Feb 09 06:25:46 PM UTC 25 5959147100 ps
T276 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.1829567826 Feb 09 06:22:10 PM UTC 25 Feb 09 06:26:08 PM UTC 25 2747828400 ps
T316 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.2143753619 Feb 09 06:19:04 PM UTC 25 Feb 09 06:26:07 PM UTC 25 5066897456 ps
T93 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_rv_dm_ndm_reset_req.2176689620 Feb 09 06:19:23 PM UTC 25 Feb 09 06:26:17 PM UTC 25 3879774540 ps
T20 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_dpi.2732046474 Feb 09 05:34:48 PM UTC 25 Feb 09 06:26:20 PM UTC 25 11532791392 ps
T317 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.2515837909 Feb 09 06:17:50 PM UTC 25 Feb 09 06:26:24 PM UTC 25 3548024612 ps
T198 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_program_error.4258427135 Feb 09 06:15:58 PM UTC 25 Feb 09 06:26:43 PM UTC 25 5417741898 ps
T318 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.4005257507 Feb 09 06:23:25 PM UTC 25 Feb 09 06:26:44 PM UTC 25 2995048791 ps
T206 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_address_translation.182508641 Feb 09 06:22:08 PM UTC 25 Feb 09 06:26:50 PM UTC 25 2812056888 ps
T319 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_sleep_frequency.1286426583 Feb 09 06:13:21 PM UTC 25 Feb 09 06:26:54 PM UTC 25 4889784184 ps
T207 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.335512151 Feb 09 06:22:11 PM UTC 25 Feb 09 06:26:58 PM UTC 25 2183195090 ps
T335 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_jitter_frequency.1279900663 Feb 09 06:13:27 PM UTC 25 Feb 09 06:27:00 PM UTC 25 5088415419 ps
T266 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.281265504 Feb 09 05:55:42 PM UTC 25 Feb 09 06:27:20 PM UTC 25 8469725528 ps
T165 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.2434369680 Feb 09 06:19:04 PM UTC 25 Feb 09 06:27:53 PM UTC 25 5797199612 ps
T336 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usb_ast_clk_calib.4029882715 Feb 09 06:22:46 PM UTC 25 Feb 09 06:28:26 PM UTC 25 3685588469 ps
T337 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.287317126 Feb 09 06:24:34 PM UTC 25 Feb 09 06:28:43 PM UTC 25 3096217997 ps
T338 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_write_clear.918770747 Feb 09 06:22:49 PM UTC 25 Feb 09 06:28:49 PM UTC 25 2742291960 ps
T94 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.559031982 Feb 09 06:19:39 PM UTC 25 Feb 09 06:28:54 PM UTC 25 4773942042 ps
T384 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.1021721807 Feb 09 06:25:27 PM UTC 25 Feb 09 06:29:30 PM UTC 25 2776318310 ps
T911 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_multistream.349303893 Feb 09 06:01:28 PM UTC 25 Feb 09 06:30:30 PM UTC 25 7693929412 ps
T912 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3641446707 Feb 09 06:25:52 PM UTC 25 Feb 09 06:30:36 PM UTC 25 2859309361 ps
T349 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_peri.1951020499 Feb 09 06:09:46 PM UTC 25 Feb 09 06:30:48 PM UTC 25 10307640714 ps
T41 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_tap_straps_testunlock0.1918509164 Feb 09 06:20:58 PM UTC 25 Feb 09 06:32:26 PM UTC 25 7009442926 ps
T913 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_ast_clk_outputs.3916482367 Feb 09 06:15:25 PM UTC 25 Feb 09 06:32:45 PM UTC 25 7511289558 ps
T237 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.2638274509 Feb 09 05:55:37 PM UTC 25 Feb 09 06:33:14 PM UTC 25 8694534888 ps
T357 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_crash_alert.4020331999 Feb 09 06:22:48 PM UTC 25 Feb 09 06:33:23 PM UTC 25 4958023800 ps
T30 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_jtag_csr_rw.2437862091 Feb 09 06:13:46 PM UTC 25 Feb 09 06:33:33 PM UTC 25 10746915336 ps
T360 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_entropy_src_csrng.1098863704 Feb 09 06:01:03 PM UTC 25 Feb 09 06:33:48 PM UTC 25 8761387912 ps
T437 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_scrambling_smoketest.1511579415 Feb 09 06:31:13 PM UTC 25 Feb 09 06:34:37 PM UTC 25 3030925362 ps
T77 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_power_sleep_load.822060759 Feb 09 06:28:18 PM UTC 25 Feb 09 06:34:51 PM UTC 25 4690680840 ps
T149 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.607629322 Feb 09 06:26:24 PM UTC 25 Feb 09 06:35:34 PM UTC 25 4324746104 ps
T383 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1869044760 Feb 09 06:23:46 PM UTC 25 Feb 09 06:36:36 PM UTC 25 5120823256 ps
T245 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_key_derivation_prod.804718380 Feb 09 06:01:38 PM UTC 25 Feb 09 06:37:13 PM UTC 25 9133373000 ps
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T247 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_key_derivation.3620213344 Feb 09 06:01:39 PM UTC 25 Feb 09 06:38:40 PM UTC 25 10176208686 ps
T45 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_jtag_mem_access.3417653901 Feb 09 06:14:50 PM UTC 25 Feb 09 06:38:45 PM UTC 25 14133261780 ps
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T914 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.11434445 Feb 09 06:24:11 PM UTC 25 Feb 09 06:41:39 PM UTC 25 7472939668 ps
T240 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.1910980928 Feb 09 05:46:57 PM UTC 25 Feb 09 06:42:18 PM UTC 25 41820832893 ps
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T82 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.4057895777 Feb 09 06:17:53 PM UTC 25 Feb 09 06:50:01 PM UTC 25 21662124678 ps
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T42 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_tap_straps_dev.1729706238 Feb 09 06:20:41 PM UTC 25 Feb 09 06:51:03 PM UTC 25 15697851870 ps
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T144 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.2370077189 Feb 09 05:49:09 PM UTC 25 Feb 09 07:10:57 PM UTC 25 18788379708 ps
T180 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.3814244459 Feb 09 05:48:39 PM UTC 25 Feb 09 07:11:29 PM UTC 25 17159653676 ps
T202 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_init_reduced_freq.3087819443 Feb 09 06:26:11 PM UTC 25 Feb 09 07:12:07 PM UTC 25 26364589585 ps
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T213 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_rma_unlocked.1892531916 Feb 09 05:34:48 PM UTC 25 Feb 09 07:29:08 PM UTC 25 42876850765 ps
T64 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.1182400497 Feb 09 06:32:36 PM UTC 25 Feb 09 07:30:50 PM UTC 25 11325568280 ps
T65 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.584026598 Feb 09 06:30:05 PM UTC 25 Feb 09 07:31:08 PM UTC 25 11985716000 ps
T285 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_debug_dev.1539203082 Feb 09 06:52:24 PM UTC 25 Feb 09 07:31:08 PM UTC 25 11116591889 ps
T60 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.2640966850 Feb 09 06:36:41 PM UTC 25 Feb 09 07:32:24 PM UTC 25 11458387140 ps
T299 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_volatile_raw_unlock.1628957803 Feb 09 07:31:29 PM UTC 25 Feb 09 07:33:30 PM UTC 25 2427555130 ps
T139 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_ast_clk_rst_inputs.692918581 Feb 09 06:31:11 PM UTC 25 Feb 09 07:35:36 PM UTC 25 21969945783 ps
T182 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_raw_unlock.1260823853 Feb 09 07:32:05 PM UTC 25 Feb 09 07:36:19 PM UTC 25 6105886469 ps
T918 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_dai_lock.3088926516 Feb 09 05:38:17 PM UTC 25 Feb 09 07:36:57 PM UTC 25 28430428272 ps
T61 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_shutdown_exception_c.4112108413 Feb 09 06:31:11 PM UTC 25 Feb 09 07:38:49 PM UTC 25 15088037118 ps
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T919 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_smoketest.3765806734 Feb 09 07:34:09 PM UTC 25 Feb 09 07:39:38 PM UTC 25 2596684176 ps
T286 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_debug_rma.3725158951 Feb 09 06:55:09 PM UTC 25 Feb 09 07:40:15 PM UTC 25 11754092036 ps
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T921 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aon_timer_smoketest.932597921 Feb 09 07:36:15 PM UTC 25 Feb 09 07:42:02 PM UTC 25 3362451800 ps
T257 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_dev.4147107723 Feb 09 05:44:19 PM UTC 25 Feb 09 07:43:06 PM UTC 25 48063499690 ps
T922 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_smoketest.403758983 Feb 09 07:37:36 PM UTC 25 Feb 09 07:43:13 PM UTC 25 2708840804 ps
T50 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_gpio_smoketest.3571625412 Feb 09 07:39:46 PM UTC 25 Feb 09 07:43:49 PM UTC 25 2798827431 ps
T256 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_rma.2405437091 Feb 09 05:43:57 PM UTC 25 Feb 09 07:45:43 PM UTC 25 47941545828 ps
T923 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_keymgr_functest.679180704 Feb 09 07:33:04 PM UTC 25 Feb 09 07:46:45 PM UTC 25 4458840136 ps
T181 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.1168182900 Feb 09 06:24:12 PM UTC 25 Feb 09 07:47:38 PM UTC 25 24951200061 ps
T924 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_smoketest.149166844 Feb 09 07:40:18 PM UTC 25 Feb 09 07:47:54 PM UTC 25 3760813400 ps
T400 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.3039142094 Feb 09 06:30:52 PM UTC 25 Feb 09 07:48:06 PM UTC 25 15755212184 ps
T351 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_plic_smoketest.1793556587 Feb 09 07:44:26 PM UTC 25 Feb 09 07:48:15 PM UTC 25 2996593382 ps
T925 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_asm_init_test_unlocked0.1884093156 Feb 09 06:44:29 PM UTC 25 Feb 09 07:48:31 PM UTC 25 12135324232 ps
T926 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_smoketest.2631059126 Feb 09 07:42:36 PM UTC 25 Feb 09 07:48:32 PM UTC 25 3271183412 ps
T927 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_smoketest.2682981121 Feb 09 07:40:54 PM UTC 25 Feb 09 07:48:56 PM UTC 25 3185144338 ps
T928 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_entropy_src_smoketest.2602457617 Feb 09 07:39:28 PM UTC 25 Feb 09 07:49:59 PM UTC 25 3459191192 ps
T129 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_timer_smoketest.1555047419 Feb 09 07:45:41 PM UTC 25 Feb 09 07:50:09 PM UTC 25 2592417036 ps
T401 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.1098381469 Feb 09 06:37:19 PM UTC 25 Feb 09 07:50:29 PM UTC 25 14852496768 ps
T929 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_smoketest.2518359187 Feb 09 07:46:21 PM UTC 25 Feb 09 07:50:46 PM UTC 25 2664484802 ps
T930 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_smoketest.3229192492 Feb 09 07:47:25 PM UTC 25 Feb 09 07:50:50 PM UTC 25 2733816920 ps
T931 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_example_rom.400256466 Feb 09 07:48:38 PM UTC 25 Feb 09 07:51:03 PM UTC 25 2803692344 ps
T932 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_example_flash.2533657847 Feb 09 07:48:38 PM UTC 25 Feb 09 07:51:35 PM UTC 25 2565945336 ps
T933 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.618863863 Feb 09 06:32:47 PM UTC 25 Feb 09 07:52:12 PM UTC 25 15604889280 ps
T435 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.1740893971 Feb 09 07:43:57 PM UTC 25 Feb 09 07:53:05 PM UTC 25 6447845032 ps
T934 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_smoke.3131393081 Feb 09 06:31:39 PM UTC 25 Feb 09 07:53:10 PM UTC 25 15181610640 ps
T935 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.2094541351 Feb 09 06:32:27 PM UTC 25 Feb 09 07:53:14 PM UTC 25 15402819340 ps
T936 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.1002579218 Feb 09 06:37:55 PM UTC 25 Feb 09 07:53:20 PM UTC 25 15292815524 ps
T937 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_smoketest.1138258979 Feb 09 07:43:57 PM UTC 25 Feb 09 07:53:33 PM UTC 25 5530161096 ps
T938 /workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.3990846779 Feb 09 06:31:44 PM UTC 25 Feb 09 07:53:33 PM UTC 25 15534245816 ps