Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.95	95.51	93.50	95.41		94.18	97.57	99.53

Total tests in report: 2918

Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
40.15	40.15	45.13	45.13	46.59	46.59	27.70	27.70			63.10	63.10	58.25	58.25	0.14	0.14	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.1306388313
47.62	7.47	49.61	4.48	56.45	9.87	27.97	0.27			69.77	6.67	80.93	22.68	1.00	0.86	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_rw.1957782106
53.20	5.58	61.28	11.68	64.40	7.95	31.17	3.20			80.44	10.67	80.93	0.00	1.00	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_plic_all_irqs_0.2489854872
57.23	4.03	69.86	8.58	65.57	1.17	38.07	6.90			80.65	0.21	80.93	0.00	8.30	7.30	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random_zero_delays.893910055
60.38	3.15	75.88	6.01	69.09	3.52	42.71	4.64			82.27	1.62	84.02	3.09	8.30	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_device_pinmux_sleep_retention.3207409523
63.35	2.97	80.72	4.84	72.77	3.68	46.18	3.47			83.97	1.70	88.14	4.12	8.30	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.1518550779
66.21	2.86	80.73	0.01	74.28	1.51	46.18	0.00			84.02	0.05	88.14	0.00	23.90	15.60	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_access_same_device.119132068
68.63	2.42	82.27	1.54	77.01	2.73	51.68	5.50			85.87	1.85	88.49	0.34	26.46	2.56	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_test.1571003460
70.95	2.32	82.27	0.00	77.01	0.00	65.61	13.93			85.87	0.00	88.49	0.00	26.46	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_sideload_kmac.3918988103
73.25	2.30	82.27	0.00	77.16	0.15	65.61	0.00			85.87	0.00	88.49	0.00	40.12	13.66	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_access_same_device_slow_rsp.2513297111
75.03	1.78	82.27	0.00	77.16	0.00	65.61	0.00			85.87	0.00	88.49	0.00	50.79	10.67	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_access_same_device_slow_rsp.3315961131
76.58	1.55	82.27	0.00	77.16	0.00	65.61	0.00			85.87	0.00	88.49	0.00	60.10	9.31	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.3104908762
78.08	1.50	85.14	2.87	78.51	1.35	68.37	2.76			86.84	0.97	89.52	1.03	60.10	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_power_virus.3542890733
79.43	1.35	85.24	0.10	78.58	0.07	75.95	7.58			87.01	0.17	89.69	0.17	60.10	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_prodend.3476517609
80.53	1.10	85.29	0.06	79.23	0.65	76.64	0.69			87.10	0.09	89.69	0.00	65.22	5.12	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all_with_error.1043148884
81.60	1.07	86.34	1.04	79.92	0.69	79.96	3.31			88.12	1.02	90.03	0.34	65.22	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_escalation.2344320273
82.62	1.03	88.21	1.87	81.50	1.57	80.61	0.65			90.17	2.05	90.03	0.00	65.22	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_plic_all_irqs_20.3988919047
83.62	0.99	88.21	0.00	81.50	0.00	80.61	0.00			90.17	0.00	90.03	0.00	71.17	5.95	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.1129413028
84.47	0.86	89.10	0.89	82.39	0.90	80.89	0.28			91.19	1.01	92.10	2.06	71.17	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2594053075
85.29	0.82	89.83	0.73	82.57	0.18	80.90	0.01			91.39	0.20	95.88	3.78	71.17	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_address_translation.4072462383
86.04	0.75	89.83	0.00	82.57	0.00	80.90	0.00			91.39	0.00	95.88	0.00	75.68	4.51	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_access_same_device_slow_rsp.2454376042
86.70	0.65	89.83	0.00	82.63	0.05	80.90	0.00			91.41	0.02	95.88	0.00	79.53	3.85	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_stress_all.4252469196
87.28	0.58	89.83	0.00	82.63	0.00	80.90	0.00			91.41	0.00	95.88	0.00	83.02	3.49	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_access_same_device_slow_rsp.2760038309
87.86	0.58	89.84	0.01	85.65	3.03	80.90	0.00			91.42	0.01	95.88	0.00	83.44	0.42	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_tl_errors.2486320966
88.42	0.56	90.99	1.15	86.32	0.67	81.87	0.96			92.01	0.59	95.88	0.00	83.44	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_gpio.2125597632
88.93	0.51	90.99	0.00	86.37	0.05	81.87	0.01			92.01	0.00	95.88	0.00	86.45	3.01	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_access_same_device.2021124001
89.38	0.45	90.99	0.00	86.37	0.00	81.87	0.00			92.01	0.00	95.88	0.00	89.14	2.69	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_access_same_device_slow_rsp.2589638547
89.82	0.44	90.99	0.00	86.39	0.02	81.87	0.00			92.01	0.00	95.88	0.00	91.78	2.63	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_stress_all_with_rand_reset.2182370743
90.26	0.44	91.00	0.01	86.39	0.01	84.32	2.44			92.01	0.00	96.05	0.17	91.78	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_auto_mode.3307039762
90.64	0.38	91.00	0.00	86.39	0.00	86.62	2.30			92.01	0.00	96.05	0.00	91.78	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.2944693724
90.98	0.34	91.79	0.79	86.73	0.34	87.31	0.69			92.20	0.19	96.05	0.00	91.82	0.05	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.2334965620
91.32	0.33	91.79	0.00	86.73	0.00	87.31	0.00			92.20	0.00	96.05	0.00	93.83	2.01	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_access_same_device_slow_rsp.2049130751
91.65	0.33	92.15	0.35	87.18	0.45	88.42	1.12			92.29	0.09	96.05	0.00	93.83	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_jtag_csr_rw.1304447684
91.95	0.30	92.69	0.54	87.63	0.46	88.78	0.35			92.75	0.46	96.05	0.00	93.83	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_plic_all_irqs_10.2581688470
92.20	0.25	92.69	0.00	87.63	0.00	88.78	0.00			92.75	0.00	96.05	0.00	95.32	1.49	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.1811700218
92.45	0.25	92.98	0.29	88.78	1.14	88.79	0.01			92.78	0.02	96.05	0.00	95.34	0.01	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_rw.2271284629
92.69	0.24	92.98	0.00	88.78	0.00	90.23	1.44			92.78	0.00	96.05	0.00	95.34	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_rma_unlocked.1477559899
92.89	0.20	93.39	0.41	89.05	0.27	90.44	0.21			93.07	0.29	96.05	0.00	95.34	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.3953305357
93.04	0.15	93.59	0.21	89.37	0.32	90.80	0.36			93.07	0.00	96.05	0.00	95.34	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1249021650
93.18	0.15	93.88	0.29	89.40	0.04	91.33	0.53			93.10	0.02	96.05	0.00	95.34	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_debug_dev.3676207375
93.32	0.13	93.99	0.11	89.44	0.04	91.98	0.65			93.10	0.01	96.05	0.00	95.34	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_host_tx_rx.4287006219
93.45	0.13	94.03	0.04	89.79	0.35	92.00	0.02			93.49	0.39	96.05	0.00	95.34	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.3883379957
93.58	0.13	94.03	0.00	89.79	0.00	92.78	0.78			93.49	0.00	96.05	0.00	95.34	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.260524251
93.71	0.13	94.03	0.00	89.79	0.00	92.78	0.00			93.49	0.00	96.05	0.00	96.10	0.76	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_access_same_device.1674754665
93.83	0.13	94.03	0.00	89.79	0.01	92.78	0.00			93.49	0.00	96.05	0.00	96.85	0.75	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random_large_delays.2737342931
93.96	0.12	94.03	0.00	90.53	0.74	92.78	0.00			93.49	0.00	96.05	0.00	96.85	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.chip_tl_errors.3618386424
94.05	0.09	94.07	0.04	90.61	0.08	92.99	0.21			93.55	0.06	96.22	0.17	96.85	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_data_integrity_escalation.2181454404
94.14	0.09	94.07	0.00	90.74	0.13	92.99	0.00			93.58	0.03	96.22	0.00	97.25	0.40	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.2398973709
94.22	0.08	94.20	0.13	90.84	0.10	93.17	0.18			93.66	0.08	96.22	0.00	97.25	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_jtag_csr_rw.1268816861
94.30	0.08	94.20	0.00	90.96	0.12	93.17	0.01			93.67	0.01	96.56	0.34	97.25	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.3537552837
94.37	0.07	94.29	0.09	91.02	0.06	93.36	0.19			93.74	0.07	96.56	0.00	97.25	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_outputs.760865872
94.44	0.07	94.36	0.07	91.20	0.19	93.49	0.14			93.75	0.01	96.56	0.00	97.25	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_hw_reset.2518803727
94.50	0.07	94.36	0.00	91.21	0.01	93.49	0.00			93.75	0.00	96.56	0.00	97.64	0.39	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_stress_all_with_error.1228763579
94.56	0.06	94.36	0.00	91.23	0.02	93.84	0.34			93.75	0.00	96.56	0.00	97.64	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx.3781214030
94.62	0.06	94.36	0.00	91.58	0.35	93.84	0.00			93.75	0.00	96.56	0.00	97.64	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.chip_tl_errors.4044267816
94.68	0.06	94.39	0.03	91.61	0.02	93.94	0.10			93.78	0.02	96.74	0.17	97.64	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_cpu_info.2296573935
94.73	0.05	94.39	0.00	91.62	0.01	93.94	0.00			93.78	0.00	96.74	0.00	97.94	0.31	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.1923535748
94.78	0.04	94.39	0.00	91.62	0.00	94.19	0.25			93.78	0.00	96.74	0.00	97.94	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.1833041491
94.81	0.04	94.40	0.01	91.63	0.01	94.19	0.01			93.80	0.02	96.91	0.17	97.96	0.01	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.742189054
94.85	0.04	94.47	0.07	91.68	0.05	94.28	0.09			93.83	0.03	96.91	0.00	97.96	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pin_wake.277864208
94.89	0.04	94.47	0.01	91.69	0.01	94.29	0.01			93.84	0.01	97.08	0.17	97.97	0.01	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/46.chip_sw_all_escalation_resets.555130794
94.92	0.04	94.47	0.01	91.70	0.01	94.29	0.01			93.85	0.01	97.25	0.17	97.98	0.01	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/67.chip_sw_all_escalation_resets.3920886767
94.96	0.04	94.48	0.01	91.72	0.01	94.29	0.00			93.86	0.01	97.42	0.17	97.99	0.01	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.2128782994
94.99	0.03	94.48	0.00	91.72	0.01	94.29	0.00			93.86	0.00	97.59	0.17	97.99	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_data_integrity_escalation.3248569339
95.02	0.03	94.48	0.00	91.74	0.02	94.33	0.03			93.86	0.00	97.59	0.00	98.11	0.12	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_error_random.145394080
95.05	0.03	94.48	0.00	91.79	0.05	94.33	0.00			93.86	0.00	97.59	0.00	98.23	0.12	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_stress_all_with_rand_reset.222019219
95.07	0.03	94.55	0.07	91.79	0.00	94.41	0.09			93.87	0.01	97.59	0.00	98.23	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_tap_straps_rma.3024375410
95.10	0.03	94.62	0.07	91.83	0.04	94.44	0.03			93.89	0.02	97.59	0.00	98.23	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_alert_info.3588952837
95.13	0.03	94.69	0.07	91.86	0.03	94.45	0.01			93.94	0.05	97.59	0.00	98.23	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sensor_ctrl_alert.1303787820
95.15	0.03	94.69	0.00	92.01	0.15	94.45	0.00			93.94	0.00	97.59	0.00	98.23	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_plic_all_irqs_0.2348272035
95.18	0.02	94.69	0.00	92.15	0.14	94.45	0.00			93.94	0.00	97.59	0.00	98.24	0.01	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_tl_errors.3991326269
95.20	0.02	94.76	0.07	92.20	0.05	94.45	0.00			93.96	0.02	97.59	0.00	98.24	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_pin_wake.3768603348
95.22	0.02	94.76	0.00	92.20	0.00	94.58	0.13			93.96	0.00	97.59	0.00	98.24	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_dev.2345341243
95.24	0.02	94.76	0.00	92.22	0.03	94.58	0.00			93.96	0.00	97.59	0.00	98.33	0.09	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.1560509237
95.26	0.02	94.77	0.01	92.27	0.05	94.62	0.04			93.97	0.02	97.59	0.00	98.33	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_aon_pullup.3898896910
95.28	0.02	94.77	0.00	92.30	0.03	94.71	0.09			93.97	0.00	97.59	0.00	98.33	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.299537368
95.30	0.02	94.78	0.01	92.41	0.11	94.71	0.00			93.97	0.00	97.59	0.00	98.33	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.chip_csr_rw.4117604441
95.32	0.02	94.78	0.00	92.44	0.03	94.71	0.00			93.97	0.00	97.59	0.00	98.41	0.08	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_stress_all.2357891817
95.34	0.02	94.78	0.00	92.54	0.11	94.71	0.00			93.97	0.00	97.59	0.00	98.41	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_plic_all_irqs_20.872858121
95.35	0.02	94.78	0.00	92.54	0.00	94.71	0.00			93.97	0.00	97.59	0.00	98.51	0.09	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_access_same_device_slow_rsp.1905987109
95.37	0.02	94.78	0.00	92.59	0.05	94.71	0.00			94.01	0.04	97.59	0.00	98.51	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_pin_retention.2980333504
95.38	0.01	94.81	0.03	92.62	0.02	94.74	0.02			94.02	0.01	97.59	0.00	98.51	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_same_source.2947946459
95.39	0.01	94.81	0.00	92.62	0.01	94.80	0.07			94.02	0.00	97.59	0.00	98.52	0.01	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.679410984
95.41	0.01	94.81	0.01	92.64	0.02	94.86	0.05			94.02	0.00	97.59	0.00	98.52	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.1011553124
95.42	0.01	94.81	0.00	92.68	0.04	94.86	0.00			94.04	0.02	97.59	0.00	98.54	0.02	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_stress_all_with_rand_reset.1274454738
95.43	0.01	94.81	0.00	92.76	0.08	94.86	0.00			94.04	0.00	97.59	0.00	98.54	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_plic_all_irqs_0.4098756749
95.45	0.01	94.81	0.00	92.82	0.06	94.86	0.00			94.05	0.02	97.59	0.00	98.54	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_access_same_device_slow_rsp.1334091840
95.46	0.01	94.81	0.00	92.84	0.02	94.86	0.00			94.05	0.00	97.59	0.00	98.59	0.05	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_stress_all_with_rand_reset.3305589034
95.47	0.01	94.81	0.00	92.85	0.01	94.90	0.04			94.06	0.01	97.59	0.00	98.59	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rom_ctrl_integrity_check.1938722805
95.48	0.01	94.81	0.00	92.88	0.03	94.90	0.00			94.08	0.02	97.59	0.00	98.60	0.01	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.1301841266
95.49	0.01	94.82	0.01	92.92	0.04	94.90	0.00			94.09	0.02	97.59	0.00	98.60	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_same_csr_outstanding.2099451887
95.50	0.01	94.82	0.00	92.92	0.00	94.95	0.06			94.09	0.00	97.59	0.00	98.60	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_rma_unlocked.595486883
95.51	0.01	94.84	0.02	92.93	0.01	94.97	0.01			94.11	0.02	97.59	0.00	98.60	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_rv_dm_ndm_reset_req.934407260
95.52	0.01	94.84	0.01	92.96	0.03	94.98	0.02			94.11	0.00	97.59	0.00	98.60	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_hw_reset.1534873813
95.52	0.01	94.87	0.02	92.96	0.01	94.99	0.01			94.13	0.02	97.59	0.00	98.60	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sensor_ctrl_alert.2164972895
95.53	0.01	94.87	0.00	93.01	0.05	94.99	0.00			94.13	0.00	97.59	0.00	98.60	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_tl_errors.1635854579
95.54	0.01	94.89	0.02	93.02	0.01	94.99	0.01			94.14	0.02	97.59	0.00	98.60	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_sensor_ctrl_alert.390962482
95.55	0.01	94.89	0.00	93.03	0.01	94.99	0.00			94.14	0.00	97.59	0.00	98.64	0.04	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_stress_all_with_rand_reset.2592805031
95.55	0.01	94.89	0.00	93.03	0.00	95.03	0.04			94.14	0.00	97.59	0.00	98.64	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.3396535290
95.56	0.01	94.89	0.00	93.03	0.01	95.07	0.04			94.14	0.00	97.59	0.00	98.64	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2863386317
95.57	0.01	94.89	0.00	93.04	0.01	95.07	0.00			94.14	0.00	97.59	0.00	98.66	0.02	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_stress_all_with_rand_reset.2180061143
95.57	0.01	94.89	0.00	93.07	0.02	95.07	0.00			94.14	0.00	97.59	0.00	98.67	0.01	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_stress_all_with_rand_reset.3562353885
95.58	0.01	94.89	0.00	93.07	0.00	95.07	0.00			94.14	0.00	97.59	0.00	98.71	0.04	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_stress_all_with_reset_error.1416242314
95.58	0.01	94.89	0.00	93.07	0.00	95.10	0.04			94.14	0.00	97.59	0.00	98.71	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_init.1689023247
95.59	0.01	94.89	0.00	93.10	0.03	95.10	0.00			94.14	0.00	97.59	0.00	98.71	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_plic_all_irqs_10.790652363
95.59	0.01	94.89	0.00	93.11	0.01	95.10	0.00			94.16	0.02	97.59	0.00	98.71	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_pin_retention.1876355282
95.60	0.01	94.89	0.01	93.13	0.01	95.11	0.01			94.16	0.00	97.59	0.00	98.71	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_idx3.3546590765
95.60	0.01	94.89	0.00	93.15	0.02	95.12	0.01			94.16	0.00	97.59	0.00	98.71	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_ops.295717720
95.61	0.01	94.89	0.00	93.15	0.00	95.15	0.03			94.16	0.00	97.59	0.00	98.71	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.1650751045
95.61	0.01	94.89	0.00	93.15	0.01	95.15	0.00			94.16	0.00	97.59	0.00	98.73	0.02	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_stress_all_with_reset_error.1440066468
95.62	0.01	94.89	0.00	93.15	0.00	95.18	0.03			94.16	0.00	97.59	0.00	98.73	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_config_host.1865048805
95.62	0.01	94.89	0.00	93.18	0.02	95.18	0.00			94.16	0.00	97.59	0.00	98.73	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_plic_all_irqs_20.63146853
95.63	0.01	94.89	0.00	93.20	0.02	95.18	0.00			94.16	0.00	97.59	0.00	98.73	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_plic_all_irqs_10.2736840894
95.63	0.01	94.89	0.00	93.22	0.02	95.18	0.01			94.16	0.00	97.59	0.00	98.73	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_entropy_src_csrng.1392483567
95.63	0.01	94.89	0.00	93.22	0.00	95.20	0.02			94.16	0.00	97.59	0.00	98.73	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_rma_unlocked.2997783656
95.64	0.01	94.89	0.00	93.24	0.02	95.20	0.00			94.16	0.00	97.59	0.00	98.73	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_tl_errors.1066727521
95.64	0.01	94.89	0.00	93.27	0.02	95.20	0.00			94.16	0.00	97.59	0.00	98.73	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_stress_all.2222930624
95.64	0.01	94.89	0.00	93.29	0.02	95.20	0.00			94.16	0.00	97.59	0.00	98.73	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_stress_all.64111298
95.65	0.01	94.89	0.00	93.31	0.02	95.20	0.00			94.16	0.00	97.59	0.00	98.73	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_gpio.3400356568
95.65	0.01	94.90	0.01	93.32	0.01	95.21	0.01			94.16	0.00	97.59	0.00	98.73	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_idx1.762190912
95.65	0.01	94.90	0.00	93.32	0.00	95.23	0.02			94.16	0.00	97.59	0.00	98.73	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3659769456
95.66	0.01	94.90	0.00	93.32	0.00	95.25	0.02			94.16	0.00	97.59	0.00	98.73	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.2802991324
95.66	0.01	94.90	0.00	93.32	0.00	95.25	0.01			94.16	0.00	97.59	0.00	98.74	0.01	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_all_escalation_resets.2394730861
95.66	0.01	94.90	0.00	93.32	0.00	95.26	0.01			94.16	0.00	97.59	0.00	98.75	0.01	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/44.chip_sw_all_escalation_resets.3470243632
95.67	0.01	94.90	0.00	93.32	0.00	95.27	0.02			94.16	0.00	97.59	0.00	98.75	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1084356784
95.67	0.01	94.90	0.00	93.33	0.01	95.27	0.00			94.16	0.00	97.59	0.00	98.75	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_stress_all.3571006043
95.67	0.01	94.90	0.00	93.35	0.01	95.27	0.00			94.16	0.00	97.59	0.00	98.75	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_stress_all_with_rand_reset.1203504145
95.67	0.01	94.90	0.00	93.36	0.01	95.27	0.00			94.16	0.00	97.59	0.00	98.75	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.666692745
95.68	0.01	94.90	0.00	93.38	0.01	95.27	0.00			94.16	0.00	97.59	0.00	98.75	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.2726207450
95.68	0.01	94.90	0.00	93.38	0.00	95.29	0.01			94.16	0.00	97.59	0.00	98.75	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_reset.1628526757
95.68	0.01	94.90	0.00	93.38	0.00	95.30	0.01			94.16	0.00	97.59	0.00	98.75	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke.1814981314
95.68	0.01	94.90	0.00	93.38	0.00	95.30	0.00			94.16	0.00	97.59	0.00	98.77	0.01	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.3437116877
95.68	0.01	94.90	0.00	93.38	0.00	95.30	0.00			94.16	0.00	97.59	0.00	98.78	0.01	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_stress_all_with_reset_error.325693060
95.69	0.01	94.90	0.00	93.38	0.00	95.30	0.00			94.16	0.00	97.59	0.00	98.79	0.01	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.320266329
95.69	0.01	94.90	0.00	93.38	0.00	95.30	0.00			94.16	0.00	97.59	0.00	98.80	0.01	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_all_escalation_resets.1666230560
95.69	0.01	94.90	0.00	93.38	0.00	95.30	0.00			94.16	0.00	97.59	0.00	98.81	0.01	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.616379289
95.69	0.01	94.90	0.00	93.38	0.00	95.30	0.00			94.16	0.00	97.59	0.00	98.83	0.01	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.3449186825
95.69	0.01	94.90	0.00	93.38	0.00	95.30	0.00			94.16	0.00	97.59	0.00	98.84	0.01	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/12.chip_sw_all_escalation_resets.2040927038
95.70	0.01	94.90	0.00	93.38	0.00	95.30	0.00			94.16	0.00	97.59	0.00	98.85	0.01	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.3767851500
95.70	0.01	94.90	0.00	93.38	0.00	95.30	0.00			94.16	0.00	97.59	0.00	98.86	0.01	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/13.chip_sw_all_escalation_resets.2558051558
95.70	0.01	94.90	0.00	93.38	0.00	95.30	0.00			94.16	0.00	97.59	0.00	98.87	0.01	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.27839123
95.70	0.01	94.90	0.00	93.38	0.00	95.30	0.00			94.16	0.00	97.59	0.00	98.88	0.01	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/14.chip_sw_all_escalation_resets.3081544491
95.70	0.01	94.90	0.00	93.38	0.00	95.30	0.00			94.16	0.00	97.59	0.00	98.90	0.01	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.492563653
95.71	0.01	94.90	0.00	93.38	0.00	95.30	0.00			94.16	0.00	97.59	0.00	98.91	0.01	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/15.chip_sw_all_escalation_resets.16660305
95.71	0.01	94.90	0.00	93.38	0.00	95.30	0.00			94.16	0.00	97.59	0.00	98.92	0.01	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.28068873
95.71	0.01	94.90	0.00	93.38	0.00	95.30	0.00			94.16	0.00	97.59	0.00	98.93	0.01	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/16.chip_sw_all_escalation_resets.2458382729
95.71	0.01	94.90	0.00	93.38	0.00	95.30	0.00			94.16	0.00	97.59	0.00	98.94	0.01	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.3471067837
95.71	0.01	94.90	0.00	93.38	0.00	95.30	0.00			94.16	0.00	97.59	0.00	98.95	0.01	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/17.chip_sw_all_escalation_resets.2876946232
95.72	0.01	94.90	0.00	93.38	0.00	95.30	0.00			94.16	0.00	97.59	0.00	98.97	0.01	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/19.chip_sw_all_escalation_resets.677545201
95.72	0.01	94.90	0.00	93.38	0.00	95.30	0.00			94.16	0.00	97.59	0.00	98.98	0.01	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.1117293690
95.72	0.01	94.90	0.00	93.38	0.00	95.30	0.00			94.16	0.00	97.59	0.00	98.99	0.01	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.3704845956
95.72	0.01	94.90	0.00	93.38	0.00	95.30	0.00			94.16	0.00	97.59	0.00	99.00	0.01	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/20.chip_sw_all_escalation_resets.3027620644
95.72	0.01	94.90	0.00	93.38	0.00	95.30	0.00			94.16	0.00	97.59	0.00	99.01	0.01	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.1602693643
95.73	0.01	94.90	0.00	93.38	0.00	95.30	0.00			94.16	0.00	97.59	0.00	99.02	0.01	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/21.chip_sw_all_escalation_resets.3179621641
95.73	0.01	94.90	0.00	93.38	0.00	95.30	0.00			94.16	0.00	97.59	0.00	99.04	0.01	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.4201940802
95.73	0.01	94.90	0.00	93.38	0.00	95.30	0.00			94.16	0.00	97.59	0.00	99.05	0.01	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/22.chip_sw_all_escalation_resets.3153499393
95.73	0.01	94.90	0.00	93.38	0.00	95.30	0.00			94.16	0.00	97.59	0.00	99.06	0.01	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.2113796347
95.73	0.01	94.90	0.00	93.38	0.00	95.30	0.00			94.16	0.00	97.59	0.00	99.07	0.01	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/24.chip_sw_all_escalation_resets.2334104956
95.73	0.01	94.90	0.00	93.38	0.00	95.30	0.00			94.16	0.00	97.59	0.00	99.08	0.01	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.527018359
95.74	0.01	94.90	0.00	93.38	0.00	95.30	0.00			94.16	0.00	97.59	0.00	99.10	0.01	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/25.chip_sw_all_escalation_resets.2405015778
95.74	0.01	94.90	0.00	93.38	0.00	95.30	0.00			94.16	0.00	97.59	0.00	99.11	0.01	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.2466573803
95.74	0.01	94.90	0.00	93.38	0.00	95.30	0.00			94.16	0.00	97.59	0.00	99.12	0.01	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/26.chip_sw_all_escalation_resets.1917520292
95.74	0.01	94.90	0.00	93.38	0.00	95.30	0.00			94.16	0.00	97.59	0.00	99.13	0.01	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.3597849758
95.74	0.01	94.90	0.00	93.38	0.00	95.30	0.00			94.16	0.00	97.59	0.00	99.14	0.01	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.119092272
95.75	0.01	94.90	0.00	93.38	0.00	95.30	0.00			94.16	0.00	97.59	0.00	99.15	0.01	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.3305498976
95.75	0.01	94.90	0.00	93.38	0.00	95.30	0.00			94.16	0.00	97.59	0.00	99.17	0.01	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.2280897673
95.75	0.01	94.90	0.00	93.38	0.00	95.30	0.00			94.16	0.00	97.59	0.00	99.18	0.01	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/31.chip_sw_all_escalation_resets.3589078227
95.75	0.01	94.90	0.00	93.38	0.00	95.30	0.00			94.16	0.00	97.59	0.00	99.19	0.01	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/32.chip_sw_all_escalation_resets.220708375
95.75	0.01	94.90	0.00	93.38	0.00	95.30	0.00			94.16	0.00	97.59	0.00	99.20	0.01	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/33.chip_sw_all_escalation_resets.3142889702
95.76	0.01	94.90	0.00	93.38	0.00	95.30	0.00			94.16	0.00	97.59	0.00	99.21	0.01	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.950645652
95.76	0.01	94.90	0.00	93.38	0.00	95.30	0.00			94.16	0.00	97.59	0.00	99.22	0.01	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.1997275097
95.76	0.01	94.90	0.00	93.38	0.00	95.30	0.00			94.16	0.00	97.59	0.00	99.24	0.01	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/36.chip_sw_all_escalation_resets.3451212320
95.76	0.01	94.90	0.00	93.38	0.00	95.30	0.00			94.16	0.00	97.59	0.00	99.25	0.01	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.3182184232
95.76	0.01	94.90	0.00	93.38	0.00	95.30	0.00			94.16	0.00	97.59	0.00	99.26	0.01	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.1086030753
95.77	0.01	94.90	0.00	93.38	0.00	95.30	0.00			94.16	0.00	97.59	0.00	99.27	0.01	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.398366835
95.77	0.01	94.90	0.00	93.38	0.00	95.30	0.00			94.16	0.00	97.59	0.00	99.28	0.01	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.1911288685
95.77	0.01	94.90	0.00	93.38	0.00	95.30	0.00			94.16	0.00	97.59	0.00	99.30	0.01	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/41.chip_sw_all_escalation_resets.3962169476
95.77	0.01	94.90	0.00	93.38	0.00	95.30	0.00			94.16	0.00	97.59	0.00	99.31	0.01	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.1197410477
95.77	0.01	94.90	0.00	93.38	0.00	95.30	0.00			94.16	0.00	97.59	0.00	99.32	0.01	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/43.chip_sw_all_escalation_resets.3526116750
95.78	0.01	94.90	0.00	93.38	0.00	95.30	0.00			94.16	0.00	97.59	0.00	99.33	0.01	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.3366383931
95.78	0.01	94.90	0.00	93.38	0.00	95.30	0.00			94.16	0.00	97.59	0.00	99.34	0.01	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/48.chip_sw_all_escalation_resets.2307870351
95.78	0.01	94.90	0.00	93.38	0.00	95.30	0.00			94.16	0.00	97.59	0.00	99.35	0.01	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_all_escalation_resets.1327665551
95.78	0.01	94.90	0.00	93.38	0.00	95.30	0.00			94.16	0.00	97.59	0.00	99.37	0.01	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.170880096
95.78	0.01	94.90	0.00	93.38	0.00	95.30	0.00			94.16	0.00	97.59	0.00	99.38	0.01	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.3148506608
95.79	0.01	94.90	0.00	93.38	0.00	95.30	0.00			94.16	0.00	97.59	0.00	99.39	0.01	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.2264518898
95.79	0.01	94.90	0.00	93.38	0.00	95.30	0.00			94.16	0.00	97.59	0.00	99.40	0.01	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/60.chip_sw_all_escalation_resets.3150889338
95.79	0.01	94.90	0.00	93.38	0.00	95.30	0.00			94.16	0.00	97.59	0.00	99.41	0.01	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/61.chip_sw_all_escalation_resets.812938731
95.79	0.01	94.90	0.00	93.38	0.00	95.30	0.00			94.16	0.00	97.59	0.00	99.42	0.01	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/62.chip_sw_all_escalation_resets.1119243745
95.79	0.01	94.90	0.00	93.38	0.00	95.30	0.00			94.16	0.00	97.59	0.00	99.44	0.01	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.939306642
95.80	0.01	94.90	0.00	93.38	0.00	95.30	0.00			94.16	0.00	97.59	0.00	99.45	0.01	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/68.chip_sw_all_escalation_resets.399483852
95.80	0.01	94.90	0.00	93.38	0.00	95.30	0.00			94.16	0.00	97.59	0.00	99.46	0.01	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/72.chip_sw_all_escalation_resets.458649141
95.80	0.01	94.90	0.00	93.38	0.00	95.30	0.00			94.16	0.00	97.59	0.00	99.47	0.01	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/81.chip_sw_all_escalation_resets.1294446426
95.80	0.01	94.90	0.00	93.38	0.00	95.30	0.00			94.16	0.00	97.59	0.00	99.48	0.01	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.2543311347
95.80	0.01	94.90	0.00	93.38	0.00	95.30	0.00			94.16	0.00	97.59	0.00	99.49	0.01	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/87.chip_sw_all_escalation_resets.3243796038
95.81	0.01	94.90	0.00	93.38	0.00	95.30	0.00			94.16	0.00	97.59	0.00	99.51	0.01	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.3846036497
95.81	0.01	94.90	0.00	93.38	0.00	95.30	0.00			94.16	0.00	97.59	0.00	99.52	0.01	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/90.chip_sw_all_escalation_resets.888964536
95.81	0.01	94.90	0.00	93.38	0.00	95.30	0.00			94.16	0.00	97.59	0.00	99.53	0.01	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/99.chip_sw_all_escalation_resets.4290475739
95.81	0.01	94.90	0.00	93.38	0.00	95.31	0.01			94.16	0.00	97.59	0.00	99.53	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.22062186
95.81	0.01	94.90	0.00	93.38	0.01	95.31	0.00			94.17	0.01	97.59	0.00	99.53	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_pin_wake.119125465
95.81	0.01	94.90	0.00	93.39	0.01	95.31	0.00			94.17	0.00	97.59	0.00	99.53	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.chip_csr_rw.4177952935
95.82	0.01	94.90	0.00	93.40	0.01	95.31	0.00			94.17	0.00	97.59	0.00	99.53	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.4182468640
95.82	0.01	94.90	0.00	93.40	0.00	95.32	0.01			94.17	0.00	97.59	0.00	99.53	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_ast_clk_rst_inputs.4138400627
95.82	0.01	94.90	0.01	93.40	0.00	95.33	0.01			94.17	0.00	97.59	0.00	99.53	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/23.chip_sw_all_escalation_resets.2161020547
95.82	0.01	94.90	0.00	93.40	0.00	95.34	0.01			94.17	0.00	97.59	0.00	99.53	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_sideload_aes.3382468684
95.82	0.01	94.90	0.00	93.40	0.00	95.35	0.01			94.17	0.00	97.59	0.00	99.53	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.2513960201
95.82	0.01	94.90	0.00	93.40	0.00	95.35	0.01			94.17	0.01	97.59	0.00	99.53	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.63589624
95.83	0.01	94.90	0.00	93.40	0.01	95.36	0.01			94.17	0.00	97.59	0.00	99.53	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.2454839893
95.83	0.01	94.90	0.00	93.40	0.00	95.36	0.00			94.18	0.01	97.59	0.00	99.53	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.2501257628
95.83	0.01	94.90	0.00	93.41	0.01	95.36	0.00			94.18	0.00	97.59	0.00	99.53	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_tl_errors.3829108913
95.83	0.01	94.90	0.00	93.42	0.01	95.36	0.00			94.18	0.00	97.59	0.00	99.53	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all.604594041
95.83	0.01	94.90	0.00	93.42	0.01	95.36	0.00			94.18	0.00	97.59	0.00	99.53	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1985247024
95.83	0.01	94.90	0.00	93.43	0.01	95.36	0.00			94.18	0.00	97.59	0.00	99.53	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_gpio.1196680088
95.83	0.01	94.90	0.00	93.43	0.00	95.36	0.01			94.18	0.00	97.59	0.00	99.53	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_enc_idle.3285089516
95.83	0.01	94.90	0.00	93.43	0.00	95.37	0.01			94.18	0.00	97.59	0.00	99.53	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2939280831
95.84	0.01	94.90	0.00	93.43	0.00	95.37	0.01			94.18	0.00	97.59	0.00	99.53	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_init_reduced_freq.833078192
95.84	0.01	94.90	0.00	93.43	0.00	95.38	0.01			94.18	0.00	97.59	0.00	99.53	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_sideload_otbn.1234712438
95.84	0.01	94.90	0.00	93.43	0.00	95.38	0.01			94.18	0.00	97.59	0.00	99.53	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_program_error.1851917788
95.84	0.01	94.90	0.00	93.43	0.00	95.39	0.01			94.18	0.00	97.59	0.00	99.53	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_power_idle_load.3472654868
95.84	0.01	94.90	0.00	93.43	0.00	95.39	0.01			94.18	0.00	97.59	0.00	99.53	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_execution_main.3227658147
95.84	0.01	94.90	0.00	93.44	0.01	95.39	0.00			94.18	0.00	97.59	0.00	99.53	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all.3428243165
95.84	0.01	94.90	0.00	93.44	0.01	95.39	0.00			94.18	0.00	97.59	0.00	99.53	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_unmapped_addr.2962897092
95.84	0.01	94.90	0.00	93.44	0.01	95.39	0.00			94.18	0.00	97.59	0.00	99.53	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all_with_error.4098126740
95.84	0.01	94.90	0.00	93.45	0.01	95.39	0.00			94.18	0.00	97.59	0.00	99.53	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all_with_error.2439822474
95.84	0.01	94.90	0.00	93.45	0.01	95.39	0.00			94.18	0.00	97.59	0.00	99.53	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_tl_errors.2934392937
95.84	0.01	94.90	0.00	93.45	0.01	95.39	0.00			94.18	0.00	97.59	0.00	99.53	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.199508307
95.84	0.01	94.90	0.00	93.46	0.01	95.39	0.00			94.18	0.00	97.59	0.00	99.53	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_stress_all_with_error.401370608
95.84	0.01	94.90	0.00	93.46	0.01	95.39	0.00			94.18	0.00	97.59	0.00	99.53	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.chip_tl_errors.437916660
95.84	0.01	94.90	0.00	93.46	0.01	95.39	0.00			94.18	0.00	97.59	0.00	99.53	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_stress_all_with_error.3963597407
95.84	0.01	94.90	0.00	93.47	0.01	95.39	0.00			94.18	0.00	97.59	0.00	99.53	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_stress_all_with_error.2663529854
95.85	0.01	94.90	0.00	93.47	0.01	95.39	0.00			94.18	0.00	97.59	0.00	99.53	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_stress_all_with_error.2810520147
95.85	0.01	94.90	0.00	93.47	0.01	95.39	0.00			94.18	0.00	97.59	0.00	99.53	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_stress_all_with_error.2427263513
95.85	0.01	94.90	0.00	93.48	0.01	95.39	0.00			94.18	0.00	97.59	0.00	99.53	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_stress_all_with_error.610477052
95.85	0.01	94.90	0.00	93.48	0.01	95.39	0.00			94.18	0.00	97.59	0.00	99.53	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.1906069546
95.85	0.01	94.90	0.00	93.48	0.01	95.39	0.00			94.18	0.00	97.59	0.00	99.53	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.2403313520
95.85	0.01	94.90	0.00	93.49	0.01	95.39	0.00			94.18	0.00	97.59	0.00	99.53	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.2631940540
95.85	0.01	94.90	0.00	93.49	0.01	95.39	0.00			94.18	0.00	97.59	0.00	99.53	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_i2c_device_tx_rx.3381313723
95.85	0.01	94.90	0.00	93.50	0.01	95.39	0.00			94.18	0.00	97.59	0.00	99.53	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_i2c_device_tx_rx.1338689358
95.85	0.01	94.90	0.00	93.50	0.00	95.40	0.01			94.18	0.00	97.59	0.00	99.53	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_tap_straps_rma.3949024433
95.85	0.01	94.90	0.00	93.50	0.00	95.40	0.01			94.18	0.00	97.59	0.00	99.53	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_hw_reset.1085338609
95.85	0.01	94.90	0.00	93.50	0.00	95.40	0.01			94.18	0.00	97.59	0.00	99.53	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_edn_concurrency.3040524989
95.85	0.01	94.90	0.00	93.50	0.00	95.40	0.01			94.18	0.00	97.59	0.00	99.53	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.3295385573
95.85	0.01	94.90	0.00	93.50	0.00	95.41	0.01			94.18	0.00	97.59	0.00	99.53	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_boot_mode.2339833587
95.85	0.01	94.90	0.00	93.50	0.00	95.41	0.01			94.18	0.00	97.59	0.00	99.53	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_example_concurrency.2576956708
95.85	0.01	94.90	0.00	93.50	0.00	95.41	0.01			94.18	0.00	97.59	0.00	99.53	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_inject_scramble_seed.3876849537
95.85	0.01	94.90	0.00	93.50	0.00	95.41	0.01			94.18	0.00	97.59	0.00	99.53	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.3817941680
95.85	0.01	94.90	0.00	93.50	0.00	95.41	0.01			94.18	0.00	97.59	0.00	99.53	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.1458593946

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_aliasing.1523825251
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_bit_bash.1648433276
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_mem_rw_with_rand_reset.2485968885
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_prim_tl_access.1300601798
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.1420867645
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_same_csr_outstanding.1600214059
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.1996709499
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random.1937604364
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random_large_delays.3667233011
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random_slow_rsp.831781322
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_same_source.144280168
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke_large_delays.3820958803
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.214340773
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke_zero_delays.1295054350
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.3704600559
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_bit_bash.96174530
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_mem_rw_with_rand_reset.3527250003
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_rw.454435975
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_prim_tl_access.3206134075
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.1983175253
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_same_csr_outstanding.147958393
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.1632968768
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_error_random.112429211
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random.1235338693
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random_slow_rsp.2503038513
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random_zero_delays.849563140
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke.2587145476
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke_large_delays.2759213920
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.1760641400
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke_zero_delays.605005905
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all.2975095113
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_unmapped_addr.1063905248
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_csr_mem_rw_with_rand_reset.716394922
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_csr_rw.2126712918
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_same_csr_outstanding.590535679
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_access_same_device.4017564249
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.2367494868
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.3562138454
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_error_random.3457536851
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/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.2000777839
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/76.chip_sw_all_escalation_resets.140877038
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/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/96.chip_sw_all_escalation_resets.400749384
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/97.chip_sw_all_escalation_resets.3449181592
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/98.chip_sw_all_escalation_resets.1456208283
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.2795468401
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.370398643
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.2337620663
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.2541626455
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.2389656765
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.612371195
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.1116460058
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Total test records in report: 2918

TEST NO	TEST LOCATION	STARTED	FINISHED	SIMULATION TIME
T1	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_example_rom.2029738548	Oct 15 04:46:06 PM UTC 24	Oct 15 04:48:00 PM UTC 24	3108814940 ps
T2	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pattgen_ios.1817815894	Oct 15 04:45:45 PM UTC 24	Oct 15 04:48:42 PM UTC 24	3312385020 ps
T3	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sival_flash_info_access.3433966101	Oct 15 04:46:48 PM UTC 24	Oct 15 04:50:47 PM UTC 24	2875866412 ps
T4	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_pullup.3152223753	Oct 15 04:47:02 PM UTC 24	Oct 15 04:51:38 PM UTC 24	3157931944 ps
T5	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_device_pinmux_sleep_retention.3207409523	Oct 15 04:48:46 PM UTC 24	Oct 15 04:51:54 PM UTC 24	3074580144 ps
T30	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_vbus.3193763243	Oct 15 04:49:20 PM UTC 24	Oct 15 04:53:24 PM UTC 24	2383363448 ps
T104	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_example_concurrency.2576956708	Oct 15 04:49:10 PM UTC 24	Oct 15 04:53:32 PM UTC 24	2581722988 ps
T105	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_example_flash.426655095	Oct 15 04:50:12 PM UTC 24	Oct 15 04:53:52 PM UTC 24	2731478894 ps
T68	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx.3781214030	Oct 15 04:46:06 PM UTC 24	Oct 15 04:54:02 PM UTC 24	3955612140 ps
T6	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.1306388313	Oct 15 04:48:09 PM UTC 24	Oct 15 04:54:12 PM UTC 24	3909709478 ps
T23	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pin_wake.277864208	Oct 15 04:50:03 PM UTC 24	Oct 15 04:54:12 PM UTC 24	3066221186 ps
T121	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_example_manufacturer.2601875770	Oct 15 04:49:55 PM UTC 24	Oct 15 04:54:24 PM UTC 24	2611051604 ps
T25	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_host_tx_rx.4287006219	Oct 15 04:50:16 PM UTC 24	Oct 15 04:54:27 PM UTC 24	3591032026 ps
T11	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_device_tpm.1200294726	Oct 15 04:49:25 PM UTC 24	Oct 15 04:54:37 PM UTC 24	3178264585 ps
T34	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.2802991324	Oct 15 04:51:30 PM UTC 24	Oct 15 04:55:02 PM UTC 24	2227083320 ps
T264	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.2454839893	Oct 15 04:49:27 PM UTC 24	Oct 15 04:55:07 PM UTC 24	3252116030 ps
T7	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_aon_pullup.3898896910	Oct 15 04:48:46 PM UTC 24	Oct 15 04:55:07 PM UTC 24	3357611244 ps
T423	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_entropy.319121747	Oct 15 04:50:33 PM UTC 24	Oct 15 04:55:23 PM UTC 24	2711714456 ps
T28	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3975974497	Oct 15 04:49:09 PM UTC 24	Oct 15 04:55:28 PM UTC 24	4140999276 ps
T26	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pin_retention.1184795453	Oct 15 04:50:15 PM UTC 24	Oct 15 04:55:42 PM UTC 24	3322200792 ps
T188	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.40157969	Oct 15 04:50:28 PM UTC 24	Oct 15 04:55:46 PM UTC 24	3265125400 ps
T27	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_gpio.2125597632	Oct 15 04:49:25 PM UTC 24	Oct 15 04:56:04 PM UTC 24	4124506780 ps
T29	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.600579376	Oct 15 04:54:13 PM UTC 24	Oct 15 04:56:29 PM UTC 24	3299113880 ps
T59	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_i2c_device_tx_rx.3767922381	Oct 15 04:50:19 PM UTC 24	Oct 15 04:57:27 PM UTC 24	3629290130 ps
T231	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_ops.295717720	Oct 15 04:48:46 PM UTC 24	Oct 15 04:57:59 PM UTC 24	3898535808 ps
T57	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1084356784	Oct 15 04:56:18 PM UTC 24	Oct 15 04:58:04 PM UTC 24	2520718477 ps
T189	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.2112849321	Oct 15 04:52:35 PM UTC 24	Oct 15 04:58:06 PM UTC 24	3284851785 ps
T8	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_device_pass_through_collision.1749966007	Oct 15 04:49:12 PM UTC 24	Oct 15 04:58:15 PM UTC 24	5184988174 ps
T132	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_idx1.762190912	Oct 15 04:49:09 PM UTC 24	Oct 15 04:58:25 PM UTC 24	3719779386 ps
T38	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_idx3.3546590765	Oct 15 04:49:26 PM UTC 24	Oct 15 04:58:28 PM UTC 24	3836360648 ps
T82	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.3048138390	Oct 15 04:56:43 PM UTC 24	Oct 15 04:58:34 PM UTC 24	2253248056 ps
T36	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.260524251	Oct 15 04:54:13 PM UTC 24	Oct 15 04:58:46 PM UTC 24	3759920874 ps
T37	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.2098265580	Oct 15 04:56:11 PM UTC 24	Oct 15 04:58:47 PM UTC 24	3352201350 ps
T42	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.2944693724	Oct 15 04:50:43 PM UTC 24	Oct 15 04:58:57 PM UTC 24	4506710270 ps
T63	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_idx2.3350953627	Oct 15 04:49:47 PM UTC 24	Oct 15 04:59:15 PM UTC 24	3881074280 ps
T247	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2837045409	Oct 15 04:49:28 PM UTC 24	Oct 15 04:59:18 PM UTC 24	4809734100 ps
T16	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_setuprx.548115970	Oct 15 04:50:27 PM UTC 24	Oct 15 04:59:25 PM UTC 24	3528737778 ps
T43	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_all_escalation_resets.2394730861	Oct 15 04:49:45 PM UTC 24	Oct 15 04:59:26 PM UTC 24	5206862696 ps
T65	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_rand_baudrate.1714784439	Oct 15 04:50:03 PM UTC 24	Oct 15 04:59:39 PM UTC 24	4068097530 ps
T64	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.1011553124	Oct 15 04:50:01 PM UTC 24	Oct 15 04:59:54 PM UTC 24	4575968691 ps
T242	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_sw_rst.2038678383	Oct 15 04:57:24 PM UTC 24	Oct 15 05:00:17 PM UTC 24	2656278200 ps
T60	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.3733582772	Oct 15 04:47:58 PM UTC 24	Oct 15 05:00:40 PM UTC 24	5403801152 ps
T201	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.3486612599	Oct 15 04:57:04 PM UTC 24	Oct 15 05:00:42 PM UTC 24	4071989809 ps
T148	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.2010124741	Oct 15 04:50:00 PM UTC 24	Oct 15 05:00:43 PM UTC 24	4115374262 ps
T81	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.543249055	Oct 15 04:49:24 PM UTC 24	Oct 15 05:01:08 PM UTC 24	5772906032 ps
T83	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_escalation.2344320273	Oct 15 04:51:31 PM UTC 24	Oct 15 05:01:18 PM UTC 24	4891474704 ps
T61	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.1906069546	Oct 15 04:50:27 PM UTC 24	Oct 15 05:01:23 PM UTC 24	4473717800 ps
T58	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_i2c_host_tx_rx.4204769168	Oct 15 04:49:43 PM UTC 24	Oct 15 05:01:36 PM UTC 24	5474332440 ps
T9	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_device_pass_through.3492576068	Oct 15 04:50:31 PM UTC 24	Oct 15 05:01:44 PM UTC 24	7472048345 ps
T228	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_sw_req.667529340	Oct 15 04:57:28 PM UTC 24	Oct 15 05:02:22 PM UTC 24	4503222250 ps
T229	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_data_integrity_escalation.2181454404	Oct 15 04:50:38 PM UTC 24	Oct 15 05:02:24 PM UTC 24	5806418712 ps
T304	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_descrambling.539807620	Oct 15 04:53:18 PM UTC 24	Oct 15 05:02:40 PM UTC 24	4180439176 ps
T206	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.60847606	Oct 15 04:57:07 PM UTC 24	Oct 15 05:03:04 PM UTC 24	3886225640 ps
T202	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_transition.1252547209	Oct 15 04:53:20 PM UTC 24	Oct 15 05:03:10 PM UTC 24	9154304255 ps
T246	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_cpu_info.2296573935	Oct 15 04:56:29 PM UTC 24	Oct 15 05:04:38 PM UTC 24	5673441300 ps
T286	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_access.3001119312	Oct 15 04:49:12 PM UTC 24	Oct 15 05:04:52 PM UTC 24	5371731744 ps
T126	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_timer_irq.2155169617	Oct 15 05:01:03 PM UTC 24	Oct 15 05:05:15 PM UTC 24	3001483830 ps
T155	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2939280831	Oct 15 04:59:57 PM UTC 24	Oct 15 05:05:18 PM UTC 24	7184082404 ps
T149	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.1681416132	Oct 15 04:49:27 PM UTC 24	Oct 15 05:05:39 PM UTC 24	6096151495 ps
T163	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.2513960201	Oct 15 04:57:25 PM UTC 24	Oct 15 05:05:46 PM UTC 24	7308844687 ps
T150	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.16248891	Oct 15 04:49:11 PM UTC 24	Oct 15 05:05:52 PM UTC 24	5364175264 ps
T287	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.3915999831	Oct 15 05:02:34 PM UTC 24	Oct 15 05:06:08 PM UTC 24	2672617780 ps
T207	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.2755999434	Oct 15 04:50:01 PM UTC 24	Oct 15 05:06:46 PM UTC 24	7248545546 ps
T199	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.742264891	Oct 15 04:50:40 PM UTC 24	Oct 15 05:07:21 PM UTC 24	7369901580 ps
T407	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_enc.4232648279	Oct 15 05:03:27 PM UTC 24	Oct 15 05:07:37 PM UTC 24	2956675452 ps
T408	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_idle.573736494	Oct 15 05:03:53 PM UTC 24	Oct 15 05:07:38 PM UTC 24	2186233594 ps
T12	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_outputs.760865872	Oct 15 05:03:21 PM UTC 24	Oct 15 05:08:25 PM UTC 24	3486146798 ps
T66	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_inputs.175942067	Oct 15 05:02:22 PM UTC 24	Oct 15 05:09:03 PM UTC 24	3259115027 ps
T265	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aon_timer_irq.2795622286	Oct 15 05:01:40 PM UTC 24	Oct 15 05:09:07 PM UTC 24	4011187144 ps
T409	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_enc_jitter_en.2314652391	Oct 15 05:03:52 PM UTC 24	Oct 15 05:09:16 PM UTC 24	2410329658 ps
T200	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.1698960211	Oct 15 04:50:40 PM UTC 24	Oct 15 05:10:01 PM UTC 24	7072280000 ps
T623	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_masking_off.4136536742	Oct 15 05:05:28 PM UTC 24	Oct 15 05:11:03 PM UTC 24	3279073633 ps
T15	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.396301591	Oct 15 05:01:31 PM UTC 24	Oct 15 05:10:18 PM UTC 24	6768325860 ps
T273	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.679410984	Oct 15 05:01:32 PM UTC 24	Oct 15 05:10:21 PM UTC 24	4348339216 ps
T156	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.1686117515	Oct 15 05:02:44 PM UTC 24	Oct 15 05:10:22 PM UTC 24	7944743520 ps
T217	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_mem_scramble.2383695574	Oct 15 05:02:48 PM UTC 24	Oct 15 05:10:44 PM UTC 24	4035868560 ps
T336	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_ping_timeout.622474638	Oct 15 05:06:26 PM UTC 24	Oct 15 05:10:45 PM UTC 24	2836566360 ps
T75	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_test.1571003460	Oct 15 05:05:41 PM UTC 24	Oct 15 05:11:10 PM UTC 24	2532121980 ps
T33	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pwm_pulses.3770146012	Oct 15 04:50:40 PM UTC 24	Oct 15 05:11:13 PM UTC 24	7930580984 ps
T142	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2863386317	Oct 15 05:02:21 PM UTC 24	Oct 15 05:12:03 PM UTC 24	18655467832 ps
T67	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.1754197305	Oct 15 05:01:50 PM UTC 24	Oct 15 05:12:09 PM UTC 24	4322767458 ps
T380	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_entropy.1776412205	Oct 15 05:08:24 PM UTC 24	Oct 15 05:12:30 PM UTC 24	2926761626 ps
T138	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.2706881592	Oct 15 04:57:32 PM UTC 24	Oct 15 05:12:43 PM UTC 24	8358065316 ps
T139	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.4161589807	Oct 15 05:01:05 PM UTC 24	Oct 15 05:12:59 PM UTC 24	9132167500 ps
T334	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.742189054	Oct 15 05:06:40 PM UTC 24	Oct 15 05:13:12 PM UTC 24	4272242776 ps
T160	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_entropy_src_kat_test.4109839280	Oct 15 05:08:24 PM UTC 24	Oct 15 05:13:14 PM UTC 24	3280555816 ps
T335	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.2297810579	Oct 15 05:03:18 PM UTC 24	Oct 15 05:13:21 PM UTC 24	5737345712 ps
T389	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.833959629	Oct 15 05:02:58 PM UTC 24	Oct 15 05:13:53 PM UTC 24	6591166284 ps
T100	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_entropy.2339129580	Oct 15 05:08:01 PM UTC 24	Oct 15 05:13:54 PM UTC 24	2937342493 ps
T390	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_wdog_reset.309051585	Oct 15 05:03:19 PM UTC 24	Oct 15 05:14:45 PM UTC 24	5332277244 ps
T227	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_escalation.2200574052	Oct 15 05:06:23 PM UTC 24	Oct 15 05:14:56 PM UTC 24	4950277622 ps
T197	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_prodend.3476517609	Oct 15 04:57:07 PM UTC 24	Oct 15 05:15:07 PM UTC 24	11842936376 ps
T161	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_entropy_src_ast_rng_req.2458196057	Oct 15 05:12:13 PM UTC 24	Oct 15 05:16:36 PM UTC 24	2425616624 ps
T391	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.2631940540	Oct 15 05:03:31 PM UTC 24	Oct 15 05:16:46 PM UTC 24	4734318388 ps
T892	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.2773628133	Oct 15 05:03:29 PM UTC 24	Oct 15 05:17:14 PM UTC 24	9936734400 ps
T162	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_randomness.726127900	Oct 15 05:02:46 PM UTC 24	Oct 15 05:17:26 PM UTC 24	5579997776 ps
T326	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_enc.3466353228	Oct 15 05:12:21 PM UTC 24	Oct 15 05:17:29 PM UTC 24	3154116316 ps
T650	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_enc_idle.3285089516	Oct 15 05:12:53 PM UTC 24	Oct 15 05:17:41 PM UTC 24	3181097990 ps
T893	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_kat_test.637576484	Oct 15 05:12:09 PM UTC 24	Oct 15 05:17:47 PM UTC 24	2629207848 ps
T157	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_boot_mode.2339833587	Oct 15 05:10:02 PM UTC 24	Oct 15 05:17:53 PM UTC 24	2720957780 ps
T327	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_enc_jitter_en.3700488676	Oct 15 05:12:52 PM UTC 24	Oct 15 05:18:11 PM UTC 24	3108698193 ps
T208	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_init.1689023247	Oct 15 04:49:21 PM UTC 24	Oct 15 05:18:25 PM UTC 24	18930670125 ps
T17	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_config_host.1865048805	Oct 15 04:49:12 PM UTC 24	Oct 15 05:18:45 PM UTC 24	8305925824 ps
T158	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_kat.1408994825	Oct 15 05:10:03 PM UTC 24	Oct 15 05:19:01 PM UTC 24	3235388000 ps
T894	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_oneshot.4065744281	Oct 15 05:13:07 PM UTC 24	Oct 15 05:19:38 PM UTC 24	2888362976 ps
T192	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_alert_info.3588952837	Oct 15 04:57:22 PM UTC 24	Oct 15 05:19:41 PM UTC 24	12540247804 ps
T218	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.3295385573	Oct 15 05:11:59 PM UTC 24	Oct 15 05:20:13 PM UTC 24	4855291304 ps
T440	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_mode_cshake.1725656954	Oct 15 05:15:32 PM UTC 24	Oct 15 05:20:15 PM UTC 24	2513143956 ps
T413	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_app_rom.643631366	Oct 15 05:17:25 PM UTC 24	Oct 15 05:20:33 PM UTC 24	2518875568 ps
T271	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_rnd.625501318	Oct 15 05:03:30 PM UTC 24	Oct 15 05:20:34 PM UTC 24	5559455592 ps
T441	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.3065691461	Oct 15 05:15:48 PM UTC 24	Oct 15 05:20:56 PM UTC 24	3331091238 ps
T895	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_mode_kmac.1259307939	Oct 15 05:15:45 PM UTC 24	Oct 15 05:21:13 PM UTC 24	2742869802 ps
T159	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.1833041491	Oct 15 05:10:39 PM UTC 24	Oct 15 05:21:45 PM UTC 24	6739229477 ps
T272	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_auto_mode.3307039762	Oct 15 05:09:06 PM UTC 24	Oct 15 05:22:24 PM UTC 24	4046816010 ps
T352	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.506091264	Oct 15 04:58:07 PM UTC 24	Oct 15 05:22:42 PM UTC 24	11408583027 ps
T896	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_idle.2133387598	Oct 15 05:17:28 PM UTC 24	Oct 15 05:22:48 PM UTC 24	2902441032 ps
T179	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sensor_ctrl_status.443781774	Oct 15 05:19:24 PM UTC 24	Oct 15 05:23:19 PM UTC 24	3363308331 ps
T370	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.3470420283	Oct 15 04:57:32 PM UTC 24	Oct 15 05:24:25 PM UTC 24	11570541184 ps
T245	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1801969908	Oct 15 04:57:31 PM UTC 24	Oct 15 05:24:37 PM UTC 24	14489690146 ps
T101	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.2334965620	Oct 15 05:06:56 PM UTC 24	Oct 15 05:24:59 PM UTC 24	9502444116 ps
T281	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_plic_sw_irq.3754374924	Oct 15 05:21:34 PM UTC 24	Oct 15 05:26:14 PM UTC 24	2730132140 ps
T164	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1249021650	Oct 15 05:19:36 PM UTC 24	Oct 15 05:26:20 PM UTC 24	5317626670 ps
T13	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_reset.1628526757	Oct 15 05:02:20 PM UTC 24	Oct 15 05:28:01 PM UTC 24	23378020056 ps
T151	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.299537368	Oct 15 05:19:12 PM UTC 24	Oct 15 05:28:16 PM UTC 24	5481648884 ps
T146	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.192223172	Oct 15 05:12:12 PM UTC 24	Oct 15 05:28:39 PM UTC 24	6083165162 ps
T897	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.596753036	Oct 15 05:22:26 PM UTC 24	Oct 15 05:28:45 PM UTC 24	4777146308 ps
T289	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rom_ctrl_integrity_check.1938722805	Oct 15 05:17:52 PM UTC 24	Oct 15 05:28:53 PM UTC 24	9273792123 ps
T647	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_ping_ok.1539998401	Oct 15 05:06:29 PM UTC 24	Oct 15 05:29:37 PM UTC 24	7539178948 ps
T210	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.91774519	Oct 15 05:19:03 PM UTC 24	Oct 15 05:29:37 PM UTC 24	4181426670 ps
T898	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.930812106	Oct 15 05:23:05 PM UTC 24	Oct 15 05:29:46 PM UTC 24	5635896808 ps
T899	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_aes_trans.2038828042	Oct 15 05:21:41 PM UTC 24	Oct 15 05:30:26 PM UTC 24	4475461520 ps
T900	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.2108006308	Oct 15 05:21:55 PM UTC 24	Oct 15 05:31:19 PM UTC 24	4935202176 ps
T18	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_dpi.475969809	Oct 15 04:45:53 PM UTC 24	Oct 15 05:31:53 PM UTC 24	11356010250 ps
T127	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_plic_all_irqs_10.2581688470	Oct 15 05:21:40 PM UTC 24	Oct 15 05:32:06 PM UTC 24	3706783982 ps
T901	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_jitter.3027766761	Oct 15 05:28:51 PM UTC 24	Oct 15 05:32:12 PM UTC 24	2443120333 ps
T243	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.1196311860	Oct 15 05:07:23 PM UTC 24	Oct 15 05:32:38 PM UTC 24	7620120576 ps
T622	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.1034493759	Oct 15 05:19:03 PM UTC 24	Oct 15 05:32:46 PM UTC 24	8993925124 ps
T213	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_execution_main.3227658147	Oct 15 05:19:23 PM UTC 24	Oct 15 05:32:49 PM UTC 24	7900403312 ps
T212	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.330373764	Oct 15 05:19:23 PM UTC 24	Oct 15 05:32:58 PM UTC 24	7663505400 ps
T152	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2065651808	Oct 15 05:23:57 PM UTC 24	Oct 15 05:34:13 PM UTC 24	4394758440 ps
T184	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_entropy_reqs.4127454605	Oct 15 05:12:18 PM UTC 24	Oct 15 05:34:19 PM UTC 24	7220454180 ps
T198	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.663828766	Oct 15 04:56:56 PM UTC 24	Oct 15 05:34:41 PM UTC 24	34260066834 ps
T322	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_plic_all_irqs_20.3988919047	Oct 15 05:21:37 PM UTC 24	Oct 15 05:34:52 PM UTC 24	4631227690 ps
T153	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1426065192	Oct 15 05:23:32 PM UTC 24	Oct 15 05:35:27 PM UTC 24	4648119148 ps
T31	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_tap_straps_dev.2790203955	Oct 15 05:33:41 PM UTC 24	Oct 15 05:36:28 PM UTC 24	2455209677 ps
T323	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_jitter_frequency.3338238028	Oct 15 05:28:39 PM UTC 24	Oct 15 05:36:29 PM UTC 24	3678653070 ps
T154	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3644773013	Oct 15 05:25:17 PM UTC 24	Oct 15 05:36:34 PM UTC 24	5294515612 ps
T143	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_ast_clk_rst_inputs.4138400627	Oct 15 05:40:56 PM UTC 24	Oct 15 06:33:00 PM UTC 24	19891290262 ps
T165	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sensor_ctrl_alert.1303787820	Oct 15 05:19:25 PM UTC 24	Oct 15 05:36:35 PM UTC 24	7199667888 ps
T902	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.1650751045	Oct 15 05:25:13 PM UTC 24	Oct 15 05:36:38 PM UTC 24	4117449960 ps
T903	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.3585556009	Oct 15 05:27:05 PM UTC 24	Oct 15 05:36:42 PM UTC 24	4534774788 ps
T904	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2156919526	Oct 15 05:25:36 PM UTC 24	Oct 15 05:36:55 PM UTC 24	3703161080 ps
T679	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_reset_frequency.232252135	Oct 15 05:27:05 PM UTC 24	Oct 15 05:36:58 PM UTC 24	4101756904 ps
T351	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.2403313520	Oct 15 05:31:05 PM UTC 24	Oct 15 05:37:48 PM UTC 24	4263016416 ps
T32	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_tap_straps_prod.1585014482	Oct 15 05:35:07 PM UTC 24	Oct 15 05:38:01 PM UTC 24	2484208871 ps
T331	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_plic_all_irqs_0.2489854872	Oct 15 05:20:30 PM UTC 24	Oct 15 05:38:07 PM UTC 24	5993197320 ps
T72	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2594053075	Oct 15 05:30:40 PM UTC 24	Oct 15 05:38:58 PM UTC 24	8044081900 ps
T87	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_rv_dm_ndm_reset_req.934407260	Oct 15 05:32:55 PM UTC 24	Oct 15 05:38:58 PM UTC 24	4979217880 ps
T340	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_entropy_src_csrng.1392483567	Oct 15 05:12:19 PM UTC 24	Oct 15 05:39:05 PM UTC 24	7105568292 ps
T166	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.218283336	Oct 15 05:32:50 PM UTC 24	Oct 15 05:39:28 PM UTC 24	6204343980 ps
T88	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.645357205	Oct 15 05:33:40 PM UTC 24	Oct 15 05:39:29 PM UTC 24	4853932584 ps
T214	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_address_translation.4072462383	Oct 15 05:35:30 PM UTC 24	Oct 15 05:39:42 PM UTC 24	3516452734 ps
T203	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_program_error.1851917788	Oct 15 05:30:40 PM UTC 24	Oct 15 05:40:06 PM UTC 24	4347828670 ps
T215	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.353172831	Oct 15 05:36:07 PM UTC 24	Oct 15 05:40:10 PM UTC 24	3013532057 ps
T221	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.3253375702	Oct 15 05:23:32 PM UTC 24	Oct 15 05:40:14 PM UTC 24	12366887173 ps
T315	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.4182468640	Oct 15 05:32:55 PM UTC 24	Oct 15 05:40:30 PM UTC 24	5608468136 ps
T316	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_peri.2695540574	Oct 15 05:21:53 PM UTC 24	Oct 15 05:40:55 PM UTC 24	8378905500 ps
T89	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.63589624	Oct 15 05:33:40 PM UTC 24	Oct 15 05:41:01 PM UTC 24	4238507717 ps
T317	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usb_ast_clk_calib.1444851963	Oct 15 05:36:21 PM UTC 24	Oct 15 05:41:08 PM UTC 24	2831636041 ps
T318	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.817817549	Oct 15 05:06:56 PM UTC 24	Oct 15 05:41:09 PM UTC 24	8578617416 ps
T319	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_sleep_frequency.1788408641	Oct 15 05:29:17 PM UTC 24	Oct 15 05:41:25 PM UTC 24	4763769752 ps
T90	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_dm_access_after_wakeup.657161052	Oct 15 05:33:42 PM UTC 24	Oct 15 05:41:35 PM UTC 24	7188770672 ps
T35	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_jtag_csr_rw.1304447684	Oct 15 05:29:11 PM UTC 24	Oct 15 05:41:59 PM UTC 24	9162338744 ps
T905	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_sw_mode.328241160	Oct 15 05:10:03 PM UTC 24	Oct 15 05:42:07 PM UTC 24	9108401208 ps
T249	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_sideload_kmac.3918988103	Oct 15 05:14:18 PM UTC 24	Oct 15 05:42:17 PM UTC 24	8642297000 ps
T906	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.3461295327	Oct 15 05:39:12 PM UTC 24	Oct 15 05:42:28 PM UTC 24	2737730809 ps
T365	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.181486474	Oct 15 05:39:17 PM UTC 24	Oct 15 05:42:54 PM UTC 24	2652987819 ps
T680	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_ast_clk_outputs.1645723409	Oct 15 05:30:40 PM UTC 24	Oct 15 05:42:56 PM UTC 24	6794124180 ps
T907	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.1442436695	Oct 15 05:39:19 PM UTC 24	Oct 15 05:43:40 PM UTC 24	2981873581 ps
T908	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2814320727	Oct 15 04:57:35 PM UTC 24	Oct 15 05:43:57 PM UTC 24	20656886855 ps
T909	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1647528951	Oct 15 05:39:19 PM UTC 24	Oct 15 05:44:06 PM UTC 24	2946675211 ps
T910	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_write_clear.577714759	Oct 15 05:39:06 PM UTC 24	Oct 15 05:44:27 PM UTC 24	3838548982 ps
T84	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_tap_straps_rma.3024375410	Oct 15 05:34:51 PM UTC 24	Oct 15 05:45:25 PM UTC 24	7466856102 ps
T85	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_tap_straps_testunlock0.2575882697	Oct 15 05:34:50 PM UTC 24	Oct 15 05:45:30 PM UTC 24	6596108711 ps
T911	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_multistream.2906905494	Oct 15 05:13:22 PM UTC 24	Oct 15 05:46:20 PM UTC 24	8537957944 ps
T412	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_scrambling_smoketest.2152303161	Oct 15 05:43:25 PM UTC 24	Oct 15 05:46:22 PM UTC 24	3265365912 ps
T70	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_power_sleep_load.1897855628	Oct 15 05:41:46 PM UTC 24	Oct 15 05:47:21 PM UTC 24	4662129736 ps
T211	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1682677438	Oct 15 05:39:20 PM UTC 24	Oct 15 05:47:27 PM UTC 24	5313682008 ps
T361	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3996841600	Oct 15 05:39:11 PM UTC 24	Oct 15 05:48:19 PM UTC 24	5367349223 ps
T130	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_power_idle_load.3472654868	Oct 15 05:39:18 PM UTC 24	Oct 15 05:48:50 PM UTC 24	4863094112 ps
T337	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_crash_alert.991137440	Oct 15 05:39:06 PM UTC 24	Oct 15 05:49:54 PM UTC 24	5817540848 ps
T250	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_sideload_aes.3382468684	Oct 15 05:14:45 PM UTC 24	Oct 15 05:52:25 PM UTC 24	10797182808 ps
T97	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_jtag_mem_access.1166427854	Oct 15 05:29:18 PM UTC 24	Oct 15 05:53:49 PM UTC 24	13211874108 ps
T912	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.4017474883	Oct 15 05:38:56 PM UTC 24	Oct 15 05:56:33 PM UTC 24	7524880881 ps
T913	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_mem_protection.767899457	Oct 15 05:42:16 PM UTC 24	Oct 15 05:58:32 PM UTC 24	5608426008 ps
T73	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.2501257628	Oct 15 05:32:00 PM UTC 24	Oct 15 05:58:36 PM UTC 24	21976366520 ps
T651	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.1656471808	Oct 15 05:20:29 PM UTC 24	Oct 15 06:01:14 PM UTC 24	23096119530 ps
T411	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_stream.2733026354	Oct 15 04:48:44 PM UTC 24	Oct 15 06:01:50 PM UTC 24	18424956862 ps
T14	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.2131796516	Oct 15 05:02:47 PM UTC 24	Oct 15 06:02:51 PM UTC 24	20674718909 ps
T74	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1426745932	Oct 15 05:31:46 PM UTC 24	Oct 15 06:08:58 PM UTC 24	23371822240 ps
T10	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_power_virus.3542890733	Oct 15 05:44:31 PM UTC 24	Oct 15 06:09:03 PM UTC 24	5828805390 ps
T209	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_init_reduced_freq.833078192	Oct 15 05:38:42 PM UTC 24	Oct 15 06:11:51 PM UTC 24	18778914097 ps
T185	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.478322313	Oct 15 05:02:47 PM UTC 24	Oct 15 06:13:41 PM UTC 24	17083071992 ps
T147	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.1212430955	Oct 15 05:03:21 PM UTC 24	Oct 15 06:17:00 PM UTC 24	18851499869 ps
T325	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_rma_unlocked.1477559899	Oct 15 04:47:50 PM UTC 24	Oct 15 06:18:33 PM UTC 24	43681280472 ps
T914	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_dai_lock.3558578620	Oct 15 04:52:18 PM UTC 24	Oct 15 06:22:41 PM UTC 24	27242642344 ps
T288	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_volatile_raw_unlock.1163955819	Oct 15 06:23:22 PM UTC 24	Oct 15 06:26:10 PM UTC 24	2462756020 ps
T186	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_raw_unlock.1995165270	Oct 15 06:26:52 PM UTC 24	Oct 15 06:31:28 PM UTC 24	4597318883 ps
T54	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_debug_dev.3676207375	Oct 15 06:02:28 PM UTC 24	Oct 15 06:35:48 PM UTC 24	11851498473 ps
T55	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_debug_test_unlocked0.2741813149	Oct 15 06:01:51 PM UTC 24	Oct 15 06:37:54 PM UTC 24	11378167570 ps
T56	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.2069393780	Oct 15 05:46:17 PM UTC 24	Oct 15 06:38:30 PM UTC 24	11332164072 ps
T51	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.2123007188	Oct 15 05:49:54 PM UTC 24	Oct 15 06:38:50 PM UTC 24	11004628280 ps
T656	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_debug_rma.493477440	Oct 15 06:03:28 PM UTC 24	Oct 15 06:39:10 PM UTC 24	12049694631 ps
T406	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.2157344846	Oct 15 05:47:21 PM UTC 24	Oct 15 06:39:28 PM UTC 24	11407324000 ps
T253	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_sideload_otbn.1234712438	Oct 15 05:14:46 PM UTC 24	Oct 15 06:39:35 PM UTC 24	18485953748 ps
T256	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_prod.411560593	Oct 15 04:56:30 PM UTC 24	Oct 15 06:40:25 PM UTC 24	46892846170 ps
T915	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_smoketest.794240503	Oct 15 06:36:29 PM UTC 24	Oct 15 06:41:59 PM UTC 24	3323876686 ps
T916	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_asm_init_test_unlocked0.1125088878	Oct 15 05:53:14 PM UTC 24	Oct 15 06:42:00 PM UTC 24	12063431080 ps
T917	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_keymgr_functest.2463147686	Oct 15 06:33:42 PM UTC 24	Oct 15 06:42:17 PM UTC 24	4678010976 ps
T52	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.1121896896	Oct 15 05:48:45 PM UTC 24	Oct 15 06:42:48 PM UTC 24	11504992130 ps
T918	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_smoketest.3374669730	Oct 15 06:39:30 PM UTC 24	Oct 15 06:44:14 PM UTC 24	2414893390 ps
T919	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aon_timer_smoketest.3656102238	Oct 15 06:38:34 PM UTC 24	Oct 15 06:44:59 PM UTC 24	3137604710 ps
T920	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_smoketest.3773522273	Oct 15 06:39:11 PM UTC 24	Oct 15 06:45:36 PM UTC 24	2457630182 ps
T39	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_gpio_smoketest.2732951675	Oct 15 06:40:16 PM UTC 24	Oct 15 06:46:41 PM UTC 24	2980886902 ps
T921	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_smoketest.2658162282	Oct 15 06:41:06 PM UTC 24	Oct 15 06:46:47 PM UTC 24	3351740092 ps
T922	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_smoketest.3642643037	Oct 15 06:40:16 PM UTC 24	Oct 15 06:46:53 PM UTC 24	3382969160 ps
T923	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_smoketest.3517791199	Oct 15 06:43:02 PM UTC 24	Oct 15 06:46:57 PM UTC 24	2833208064 ps
T924	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_entropy_src_smoketest.1496392932	Oct 15 06:39:44 PM UTC 24	Oct 15 06:47:04 PM UTC 24	3002794492 ps
T259	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_rma.3200818440	Oct 15 04:56:40 PM UTC 24	Oct 15 06:47:16 PM UTC 24	44863429944 ps
T257	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_dev.2345341243	Oct 15 04:56:30 PM UTC 24	Oct 15 06:48:13 PM UTC 24	50102527890 ps
T53	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_shutdown_exception_c.2131860323	Oct 15 05:44:20 PM UTC 24	Oct 15 06:48:32 PM UTC 24	15498965160 ps
T128	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_timer_smoketest.3177564116	Oct 15 06:45:39 PM UTC 24	Oct 15 06:48:53 PM UTC 24	3098725050 ps
T328	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_plic_smoketest.104473051	Oct 15 06:44:54 PM UTC 24	Oct 15 06:49:25 PM UTC 24	2509356688 ps
T410	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.3670835819	Oct 15 06:43:26 PM UTC 24	Oct 15 06:49:29 PM UTC 24	5707703636 ps
T925	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_example_rom.760866969	Oct 15 06:47:41 PM UTC 24	Oct 15 06:49:43 PM UTC 24	2291027564 ps
T926	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_smoketest.2163289169	Oct 15 06:46:16 PM UTC 24	Oct 15 06:50:18 PM UTC 24	3342053136 ps
T628	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3659769456	Oct 15 05:38:55 PM UTC 24	Oct 15 06:50:24 PM UTC 24	24809247925 ps
T927	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_smoketest.637946119	Oct 15 06:48:14 PM UTC 24	Oct 15 06:51:27 PM UTC 24	2841040862 ps
T928	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_example_manufacturer.590819662	Oct 15 06:48:14 PM UTC 24	Oct 15 06:51:47 PM UTC 24	3304130760 ps
T929	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.2907957468	Oct 15 05:49:27 PM UTC 24	Oct 15 06:51:53 PM UTC 24	14533738132 ps
T930	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_smoketest.106476708	Oct 15 06:48:11 PM UTC 24	Oct 15 06:52:18 PM UTC 24	3121169940 ps
T931	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_example_flash.1613716515	Oct 15 06:48:08 PM UTC 24	Oct 15 06:52:29 PM UTC 24	2796625896 ps
T932	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_example_concurrency.2669402184	Oct 15 06:48:15 PM UTC 24	Oct 15 06:52:31 PM UTC 24	2642576660 ps
T933	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_smoketest.2859634255	Oct 15 06:43:02 PM UTC 24	Oct 15 06:52:36 PM UTC 24	6217548916 ps
T290	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.3953305357	Oct 15 05:50:14 PM UTC 24	Oct 15 06:52:46 PM UTC 24	14179660586 ps
T381	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.3354209102	Oct 15 05:50:38 PM UTC 24	Oct 15 06:53:16 PM UTC 24	14964500824 ps
T364	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sival_flash_info_access.4013876461	Oct 15 06:48:54 PM UTC 24	Oct 15 06:54:10 PM UTC 24	3374558060 ps
T934	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.4261278902	Oct 15 05:51:23 PM UTC 24	Oct 15 06:54:14 PM UTC 24	14481562102 ps
T935	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.1604338995	Oct 15 05:49:09 PM UTC 24	Oct 15 06:54:51 PM UTC 24	15193126200 ps
T936	/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.2920395935	Oct 15 05:47:19 PM UTC 24	Oct 15 06:54:52 PM UTC 24	15470141386 ps