Assertions
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Assertions by Category
ASSERTPROPERTIESSEQUENCES
Total58200
Category 058200


Assertions by Severity
ASSERTPROPERTIESSEQUENCES
Total58200
Severity 058200


Summary for Assertions
NUMBERPERCENT
Total Number582100.00
Uncovered142.41
Success56396.74
Failure00.00
Incomplete183.09
Without Attempts00.00
Excluded50.86


Detail Report for Assertions

Assertions Uncovered:
ASSERTIONS   CATEGORY   SEVERITY   ATTEMPTS   REAL SUCCESSES   FAILURES   INCOMPLETE   SRC   
tb.dut.top_earlgrey.u_pinmux_aon.FpvSecCmBusIntegrity_A 00122322034000
tb.dut.top_earlgrey.u_pinmux_aon.PwrMgrStrapSampleOnce1_A 0012232203400963
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmIbexLockstepResetCountAlertCheck_A 00491226693000
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmIbexPcMismatchCheck_A 00491226693000
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmIbexRfEccErrCheck_A 00491226693000
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmIbexStoreRespIntgErrCheck_A 00491226693000
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmRvCoreRegWeOnehotCheckRAddrA_A 00491226693000
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmRvCoreRegWeOnehotCheckRAddrB_A 00491226693000
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmRvCoreRegWeOnehotCheck_A 00491226693000
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.NoReadyValidNoGrant_A 00491226693000
tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_packer_fifo.DataOStableWhenPending_A 0049122669300999
tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_packer_fifo.ValidOPairedWithReadyI_A 00491226693000
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.NoReadyValidNoGrant_A 00491226693000
tb.dut.top_earlgrey.u_rv_plic.FpvSecCmBusIntegrity_A 00491226693000

Assertions Success:
ASSERTIONS   CATEGORY   SEVERITY   ATTEMPTS   REAL SUCCESSES   FAILURES   INCOMPLETE   SRC   
tb.dut.top_earlgrey.scanmodeKnown 0049780744249780744200
tb.dut.top_earlgrey.u_pinmux_aon.AlertsKnown_A 0012232203412163765600
tb.dut.top_earlgrey.u_pinmux_aon.AonWkupReqKnownO_A 001471672127856000
tb.dut.top_earlgrey.u_pinmux_aon.DftJtagTckKnown_A 0012232203412163765600
tb.dut.top_earlgrey.u_pinmux_aon.DftJtagTmsKnown_A 0012232203412163765600
tb.dut.top_earlgrey.u_pinmux_aon.DftJtagTrstKnown_A 0012232203412163765600
tb.dut.top_earlgrey.u_pinmux_aon.DftStrapsKnown_A 0012232203412163765600
tb.dut.top_earlgrey.u_pinmux_aon.DioKnownO_A 0012232203412163765600
tb.dut.top_earlgrey.u_pinmux_aon.DioOeKnownO_A 0012232203412163765600
tb.dut.top_earlgrey.u_pinmux_aon.FpvSecCmRegWeOnehotCheck_A 00122322034500
tb.dut.top_earlgrey.u_pinmux_aon.LcJtagTckKnown_A 0012232203412163765600
tb.dut.top_earlgrey.u_pinmux_aon.LcJtagTmsKnown_A 0012232203412163765600
tb.dut.top_earlgrey.u_pinmux_aon.LcJtagTrstKnown_A 0012232203412163765600
tb.dut.top_earlgrey.u_pinmux_aon.MioKnownO_A 0012232203412163765600
tb.dut.top_earlgrey.u_pinmux_aon.MioOeKnownO_A 0012232203412163765600
tb.dut.top_earlgrey.u_pinmux_aon.PinmuxWkupStable_A 001471672518600
tb.dut.top_earlgrey.u_pinmux_aon.PwrMgrStrapSampleOnce0_A 00122322034168300
tb.dut.top_earlgrey.u_pinmux_aon.RvJtagTckKnown_A 0012232203412163765600
tb.dut.top_earlgrey.u_pinmux_aon.RvJtagTmsKnown_A 0012232203412163765600
tb.dut.top_earlgrey.u_pinmux_aon.RvJtagTrstKnown_A 0012232203412163765600
tb.dut.top_earlgrey.u_pinmux_aon.TlAReadyKnownO_A 0012232203412163765600
tb.dut.top_earlgrey.u_pinmux_aon.TlDValidKnownO_A 0012232203412163765600
tb.dut.top_earlgrey.u_pinmux_aon.UsbWakeDetectActiveKnownO_A 001471672127856000
tb.dut.top_earlgrey.u_pinmux_aon.UsbWkupReqKnownO_A 001471672127856000
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.DftTapOff0_A 00122322034377694670276
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.LcHwDebugEnClear_A 0012232203411934624015
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.LcHwDebugEnSetRev0_A 001223220341430098
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.LcHwDebugEnSetRev1_A 001223220341430098
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.LcHwDebugEnSet_A 00122322034143000
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.RvTapOff0_A 001223220342530196
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.RvTapOff1_A 001223220343484548600
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.TapStrapKnown_A 0012232203412163776400
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.dft_strap0_idxRange_A 001010101000
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.dft_strap1_idxRange_A 001010101000
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.tap_strap0_idxRange_A 001010101000
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.tap_strap1_idxRange_A 001010101000
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.tck_idxRange_A 001010101000
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.tdi_idxRange_A 001010101000
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.tdo_idxRange_A 001010101000
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.tms_idxRange_A 001010101000
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.trst_idxRange_A 001010101000
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_por_scanmode_sync.NumCopiesMustBeGreaterZero_A 001010101000
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_por_scanmode_sync.OutputsKnown_A 0012232203412163776400
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_por_scanmode_sync.gen_no_flops.OutputDelay_A 0012232203412163776400
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.FunctionCheck_A 0012232203412163776400
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.OutputsKnown_A 0012232203412163776400
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_a.NumCopiesMustBeGreaterZero_A 001010101000
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_a.OutputsKnown_A 0012232203412163776400
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_a.gen_no_flops.OutputDelay_A 0012232203412163776400
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_b.NumCopiesMustBeGreaterZero_A 001010101000
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_b.OutputsKnown_A 0012232203412163776400
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_b.gen_no_flops.OutputDelay_A 0012232203412163776400
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_check_byp_en.NumCopiesMustBeGreaterZero_A 001010101000
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_check_byp_en.OutputsKnown_A 0012232203412163776400
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_check_byp_en.gen_flops.OutputDelay_A 0012232203412163090403003
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en.NumCopiesMustBeGreaterZero_A 001010101000
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en.OutputsKnown_A 0012232203412163776400
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en.gen_flops.OutputDelay_A 0012232203412163090403003
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_escalate_en.NumCopiesMustBeGreaterZero_A 001010101000
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_escalate_en.OutputsKnown_A 0012232203412163776400
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_escalate_en.gen_flops.OutputDelay_A 0012232203412163090403003
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_hw_debug_en.NumCopiesMustBeGreaterZero_A 001010101000
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_hw_debug_en.OutputsKnown_A 0012232203412163776400
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_hw_debug_en.gen_flops.OutputDelay_A 0012232203412163090403003
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_pinmux_hw_debug_en.NumCopiesMustBeGreaterZero_A 001010101000
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_pinmux_hw_debug_en.OutputsKnown_A 0012232203412163776400
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_pinmux_hw_debug_en.gen_no_flops.OutputDelay_A 0012232203412163776400
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_rst_por_aon_n_mux.gen_generic.u_impl_generic.selKnown0 0078064900
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_rst_por_aon_n_mux.gen_generic.u_impl_generic.selKnown1 00172572500
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.en2addrHit 0014059584941494500
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.reAfterRv 0014059584941494500
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.rePulse 0014059584928327900
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_chk.PayLoadWidthCheck 002918291800
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_reg_if.AllowedLatency_A 002918291800
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_reg_if.MatchedWidthAssert 002918291800
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_reg_if.u_err.dataWidthOnly32_A 002918291800
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A 002918291800
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck 002918291800
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_rsp_intg_gen.DataWidthCheck_A 002918291800
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_rsp_intg_gen.PayLoadWidthCheck 002918291800
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.BusySrcReqChk_A 0014059584912369200
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.DstReqKnown_A 001668691144678900
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.SrcAckBusyChk_A 0014059584927000
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.SrcBusyKnown_A 0014059584913978954700
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A 001668691320972
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.u_arb.gen_wr_req.HwIdSelCheck_A 0016686913200
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq 0014059584930200
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq 00166869115700
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.u_src_to_dst_req.DstPulseCheck_A 00166869126900
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.u_src_to_dst_req.SrcPulseCheck_M 0014059584927300
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc.BusySrcReqChk_A 001405958499247500
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc.DstReqKnown_A 001668691144678900
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc.SrcAckBusyChk_A 0014059584923600
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc.SrcBusyKnown_A 0014059584913978954700
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 0014059584923600
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 00166869123600
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc.u_src_to_dst_req.DstPulseCheck_A 00166869123600
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc.u_src_to_dst_req.SrcPulseCheck_M 0014059584923600
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc.BusySrcReqChk_A 001405958498016900
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc.DstReqKnown_A 001668691144678900
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc.SrcAckBusyChk_A 0014059584920600
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc.SrcBusyKnown_A 0014059584913978954700
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 0014059584920600
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 00166869120600
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc.u_src_to_dst_req.DstPulseCheck_A 00166869120600
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc.u_src_to_dst_req.SrcPulseCheck_M 0014059584920600
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc.BusySrcReqChk_A 001405958498656600
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc.DstReqKnown_A 001668691144678900
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc.SrcAckBusyChk_A 0014059584922400
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc.SrcBusyKnown_A 0014059584913978954700
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 0014059584922400
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 00166869122400
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc.u_src_to_dst_req.DstPulseCheck_A 00166869122400
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc.u_src_to_dst_req.SrcPulseCheck_M 0014059584922400
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc.BusySrcReqChk_A 001405958498974300
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc.DstReqKnown_A 001668691144678900
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc.SrcAckBusyChk_A 0014059584922600
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc.SrcBusyKnown_A 0014059584913978954700
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 0014059584922600
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 00166869122600
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc.u_src_to_dst_req.DstPulseCheck_A 00166869122600
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc.u_src_to_dst_req.SrcPulseCheck_M 0014059584922600
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc.BusySrcReqChk_A 001405958498712300
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc.DstReqKnown_A 001668691144678900
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc.SrcAckBusyChk_A 0014059584922400
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc.SrcBusyKnown_A 0014059584913978954700
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 0014059584922400
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 00166869122400
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc.u_src_to_dst_req.DstPulseCheck_A 00166869122400
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc.u_src_to_dst_req.SrcPulseCheck_M 0014059584922400
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc.BusySrcReqChk_A 001405958498048400
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc.DstReqKnown_A 001668691144678900
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc.SrcAckBusyChk_A 0014059584920800
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc.SrcBusyKnown_A 0014059584913978954700
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 0014059584920800
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 00166869120800
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc.u_src_to_dst_req.DstPulseCheck_A 00166869120800
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc.u_src_to_dst_req.SrcPulseCheck_M 0014059584920800
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc.BusySrcReqChk_A 001405958498757000
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc.DstReqKnown_A 001668691144678900
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc.SrcAckBusyChk_A 0014059584922300
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc.SrcBusyKnown_A 0014059584913978954700
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 0014059584922300
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 00166869122300
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc.u_src_to_dst_req.DstPulseCheck_A 00166869122300
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc.u_src_to_dst_req.SrcPulseCheck_M 0014059584922300
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc.BusySrcReqChk_A 001405958498768500
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc.DstReqKnown_A 001668691144678900
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc.SrcAckBusyChk_A 0014059584922600
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc.SrcBusyKnown_A 0014059584913978954700
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 0014059584922600
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 00166869122600
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc.u_src_to_dst_req.DstPulseCheck_A 00166869122600
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc.u_src_to_dst_req.SrcPulseCheck_M 0014059584922600
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc.BusySrcReqChk_A 0014059584910191200
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc.DstReqKnown_A 001668691144678900
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc.SrcAckBusyChk_A 0014059584925700
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc.SrcBusyKnown_A 0014059584913978954700
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 0014059584925700
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 00166869125700
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc.u_src_to_dst_req.DstPulseCheck_A 00166869125700
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc.u_src_to_dst_req.SrcPulseCheck_M 0014059584925700
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc.BusySrcReqChk_A 001405958497951900
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc.DstReqKnown_A 001668691144678900
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc.SrcAckBusyChk_A 0014059584920600
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc.SrcBusyKnown_A 0014059584913978954700
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 0014059584920600
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 00166869120600
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc.u_src_to_dst_req.DstPulseCheck_A 00166869120200
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc.u_src_to_dst_req.SrcPulseCheck_M 0014059584920600
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc.BusySrcReqChk_A 001405958498376100
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc.DstReqKnown_A 001668691144678900
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc.SrcAckBusyChk_A 0014059584921200
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc.SrcBusyKnown_A 0014059584913978954700
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 0014059584921200
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 00166869121200
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc.u_src_to_dst_req.DstPulseCheck_A 00166869121200
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc.u_src_to_dst_req.SrcPulseCheck_M 0014059584921200
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.BusySrcReqChk_A 001405958498741800
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.DstReqKnown_A 001668691144678900
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.SrcAckBusyChk_A 0014059584922400
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.SrcBusyKnown_A 0014059584913978954700
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 0014059584922400
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 00166869122400
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.u_src_to_dst_req.DstPulseCheck_A 00166869122400
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.u_src_to_dst_req.SrcPulseCheck_M 0014059584922400
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.BusySrcReqChk_A 001405958499581200
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.DstReqKnown_A 001668691144678900
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.SrcAckBusyChk_A 0014059584924200
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.SrcBusyKnown_A 0014059584913978954700
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 0014059584924200
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 00166869124200
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.u_src_to_dst_req.DstPulseCheck_A 00166869124200
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.u_src_to_dst_req.SrcPulseCheck_M 0014059584924200
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.BusySrcReqChk_A 001405958497950200
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.DstReqKnown_A 001668691144678900
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.SrcAckBusyChk_A 0014059584920500
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.SrcBusyKnown_A 0014059584913978954700
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 0014059584920500
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 00166869120500
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.u_src_to_dst_req.DstPulseCheck_A 00166869120500
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.u_src_to_dst_req.SrcPulseCheck_M 0014059584920500
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.BusySrcReqChk_A 001405958499070000
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.DstReqKnown_A 001668691144678900
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.SrcAckBusyChk_A 0014059584923000
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.SrcBusyKnown_A 0014059584913978954700
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 0014059584923000
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 00166869123000
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.u_src_to_dst_req.DstPulseCheck_A 00166869123000
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.u_src_to_dst_req.SrcPulseCheck_M 0014059584923000
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.BusySrcReqChk_A 001405958498843300
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.DstReqKnown_A 001668691144678900
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.SrcAckBusyChk_A 0014059584922500
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.SrcBusyKnown_A 0014059584913978954700
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 0014059584922500
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 00166869122500
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.u_src_to_dst_req.DstPulseCheck_A 00166869122500
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.u_src_to_dst_req.SrcPulseCheck_M 0014059584922500
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc.BusySrcReqChk_A 001405958499172000
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc.DstReqKnown_A 001668691144678900
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc.SrcAckBusyChk_A 0014059584923300
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc.SrcBusyKnown_A 0014059584913978954700
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 0014059584923300
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 00166869123300
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc.u_src_to_dst_req.DstPulseCheck_A 00166869123300
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc.u_src_to_dst_req.SrcPulseCheck_M 0014059584923500
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc.BusySrcReqChk_A 001405958497823400
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc.DstReqKnown_A 001668691144678900
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc.SrcAckBusyChk_A 0014059584920400
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc.SrcBusyKnown_A 0014059584913978954700
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 0014059584920400
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 00166869120400
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc.u_src_to_dst_req.DstPulseCheck_A 00166869120400
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc.u_src_to_dst_req.SrcPulseCheck_M 0014059584920400
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc.BusySrcReqChk_A 001405958498994700
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc.DstReqKnown_A 001668691144678900
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc.SrcAckBusyChk_A 0014059584923000
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc.SrcBusyKnown_A 0014059584913978954700
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 0014059584923000
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 00166869123000
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc.u_src_to_dst_req.DstPulseCheck_A 00166869123000
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc.u_src_to_dst_req.SrcPulseCheck_M 0014059584923000
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc.BusySrcReqChk_A 001405958499105800
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc.DstReqKnown_A 001668691144678900
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc.SrcAckBusyChk_A 0014059584923300
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc.SrcBusyKnown_A 0014059584913978954700
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 0014059584923300
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 00166869123300
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc.u_src_to_dst_req.DstPulseCheck_A 00166869123300
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc.u_src_to_dst_req.SrcPulseCheck_M 0014059584923400
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc.BusySrcReqChk_A 001405958498376300
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc.DstReqKnown_A 001668691144678900
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc.SrcAckBusyChk_A 0014059584921500
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc.SrcBusyKnown_A 0014059584913978954700
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 0014059584921500
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 00166869121500
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc.u_src_to_dst_req.DstPulseCheck_A 00166869121400
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc.u_src_to_dst_req.SrcPulseCheck_M 0014059584921500
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc.BusySrcReqChk_A 001405958499984700
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc.DstReqKnown_A 001668691144678900
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc.SrcAckBusyChk_A 0014059584925700
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc.SrcBusyKnown_A 0014059584913978954700
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 0014059584925700
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 00166869125700
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc.u_src_to_dst_req.DstPulseCheck_A 00166869125700
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc.u_src_to_dst_req.SrcPulseCheck_M 0014059584925800
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc.BusySrcReqChk_A 001405958498540200
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc.DstReqKnown_A 001668691144678900
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc.SrcAckBusyChk_A 0014059584922100
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc.SrcBusyKnown_A 0014059584913978954700
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 0014059584922100
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 00166869122100
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc.u_src_to_dst_req.DstPulseCheck_A 00166869122100
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc.u_src_to_dst_req.SrcPulseCheck_M 0014059584922200
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc.BusySrcReqChk_A 001405958498500200
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc.DstReqKnown_A 001668691144678900
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc.SrcAckBusyChk_A 0014059584921800
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc.SrcBusyKnown_A 0014059584913978954700
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 0014059584921800
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 00166869121800
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc.u_src_to_dst_req.DstPulseCheck_A 00166869121700
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc.u_src_to_dst_req.SrcPulseCheck_M 0014059584921800
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.wePulse 0014059584913166600
tb.dut.top_earlgrey.u_pinmux_aon.u_usbdev_aon_wake.WakeDetectActiveAonKnown_A 001471672127856000
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmIbexFetchEnable0_A 00491226693500
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmIbexFetchEnable1_A 0049122669324416272096
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmIbexFetchEnable2_A 0049122669364195315082
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmIbexFetchEnable3Rev_A 0049122669342241632701998
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmIbexFetchEnable3_A 0049122669342241816801895
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmIbexInstrIntgErrCheck_A 0049122669330700
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmIbexLoadRespIntgErrCheck_A 0049122669358600
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmRegWeOnehotCheck_A 00491226693300
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo.DataKnown_A 004912266934294765800
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo.DataKnown_AKnownEnable 0049122669349112205100
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo.DepthKnown_A 0049122669349112205100
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo.RvalidKnown_A 0049122669349112205100
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo.WreadyKnown_A 0049122669349112205100
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass 001010101000
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo.DataKnown_A 004912266933598509500
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo.DataKnown_AKnownEnable 0049122669349112205100
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo.DepthKnown_A 0049122669349112205100
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo.RvalidKnown_A 0049122669349112205100
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo.WreadyKnown_A 0049122669349112205100
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass 001010101000
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo.DataKnown_A 004912266935941367100
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo.DataKnown_AKnownEnable 0049122669349112205100
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo.DepthKnown_A 0049122669349112205100
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo.RvalidKnown_A 0049122669349112205100
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo.WreadyKnown_A 0049122669349112205100
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo.gen_passthru_fifo.paramCheckPass 001010101000
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo.DataKnown_A 004912266934446977500
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo.DataKnown_AKnownEnable 0049122669349112205100
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo.DepthKnown_A 0049122669349112205100
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo.RvalidKnown_A 0049122669349112205100
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo.WreadyKnown_A 0049122669349112205100
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo.gen_passthru_fifo.paramCheckPass 001010101000
tb.dut.top_earlgrey.u_rv_core_ibex.g_instr_intg_err_assert_signals.AssertConnected_A 001010101000
tb.dut.top_earlgrey.u_rv_core_ibex.g_lsu_load_resp_intg_err_assert_signals.AssertConnected_A 001010101000
tb.dut.top_earlgrey.u_rv_core_ibex.g_lsu_store_resp_intg_err_assert_signals.AssertConnected_A 001010101000
tb.dut.top_earlgrey.u_rv_core_ibex.g_pc_mismatch_alert_o_assert_signals.AssertConnected_A 001010101000
tb.dut.top_earlgrey.u_rv_core_ibex.g_rf_ecc_err_comb_assert_signals.AssertConnected_A 001010101000
tb.dut.top_earlgrey.u_rv_core_ibex.gen_icache_scramble_asserts.IbexIcacheScrambleKeyForwardedToCore_A 0049122669316900
tb.dut.top_earlgrey.u_rv_core_ibex.gen_icache_scramble_asserts.IbexIcacheScrambleKeyRequestAfterFenceI_A 0049122669319000
tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex.DontExceeedMaxReqs 004912266934290328000
tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex.u_cmd_intg_gen.PayMaxWidthCheck_A 001010101000
tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex.u_rsp_chk.PayLoadWidthCheck 001010101000
tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_i_ibex.DontExceeedMaxReqs 004912266935941367100
tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_i_ibex.u_cmd_intg_gen.PayMaxWidthCheck_A 001010101000
tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_i_ibex.u_rsp_chk.PayLoadWidthCheck 001010101000
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.CheckHotOne_A 0049122669348407190900
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.CheckNGreaterZero_A 001010101000
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.GntImpliesReady_A 00491226693318900
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.GntImpliesValid_A 00491226693318900
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.GrantKnown_A 0049122669348407190900
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.IdxKnown_A 0049122669348407190900
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.IndexIsCorrect_A 00491226693318900
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.Priority_A 00491226693318900
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.ReadyAndValidImplyGrant_A 00491226693318900
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.ReqAndReadyImplyGrant_A 00491226693318900
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.ReqImpliesValid_A 00491226693318900
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.ValidKnown_A 0049122669348407190900
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.gen_data_port_assertion.DataFlow_A 00491226693318900
tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.DataOutputDiffFromPrev_A 0049057513710368033500
tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.DataOutputValid_A 00491226693433400
tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data.gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA 00491226693433400
tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data.gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB 00491226693433400
tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data.u_prim_sync_reqack.SyncReqAckAckNeedsReq 00491226693433400
tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data.u_prim_sync_reqack.SyncReqAckHoldReq 00491226693433400
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.CheckHotOne_A 0049122669348407190900
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.CheckNGreaterZero_A 001010101000
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.GntImpliesReady_A 00491226693517500
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.GntImpliesValid_A 00491226693517500
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.GrantKnown_A 0049122669348407190900
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.IdxKnown_A 0049122669348407190900
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.IndexIsCorrect_A 00491226693517500
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.Priority_A 00491226693517500
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.ReadyAndValidImplyGrant_A 00491226693517500
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.ReqAndReadyImplyGrant_A 00491226693517500
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.ReqImpliesValid_A 00491226693517500
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.ValidKnown_A 0049122669348407190900
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.gen_data_port_assertion.DataFlow_A 00491226693517500
tb.dut.top_earlgrey.u_rv_core_ibex.u_lc_sync.NumCopiesMustBeGreaterZero_A 001010101000
tb.dut.top_earlgrey.u_rv_core_ibex.u_lc_sync.OutputsKnown_A 0049122669349112205100
tb.dut.top_earlgrey.u_rv_core_ibex.u_lc_sync.gen_flops.OutputDelay_A 0049122669349111464702997
tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data.gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA 004912266934000
tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data.gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB 004912266934000
tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data.u_prim_sync_reqack.SyncReqAckAckNeedsReq 001210641624000
tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data.u_prim_sync_reqack.SyncReqAckHoldReq 004912266934000
tb.dut.top_earlgrey.u_rv_core_ibex.u_pwrmgr_sync.NumCopiesMustBeGreaterZero_A 001010101000
tb.dut.top_earlgrey.u_rv_core_ibex.u_pwrmgr_sync.OutputsKnown_A 0049122669349112205100
tb.dut.top_earlgrey.u_rv_core_ibex.u_pwrmgr_sync.gen_flops.OutputDelay_A 0049122669349111464702997
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.en2addrHit 005641250523992400
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.reAfterRv 005641250523992400
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.rePulse 005641250523110100
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_chk.PayLoadWidthCheck 002918291800
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_reg_if.AllowedLatency_A 002918291800
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_reg_if.MatchedWidthAssert 002918291800
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_reg_if.u_err.dataWidthOnly32_A 002918291800
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A 002918291800
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck 002918291800
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_rsp_intg_gen.DataWidthCheck_A 002918291800
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_rsp_intg_gen.PayLoadWidthCheck 002918291800
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.NotOverflowed_A 0056412505256400496600
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo.DataKnown_A 005641250529426700
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo.DataKnown_AKnownEnable 0056412505256400496600
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo.DepthKnown_A 0056412505256400496600
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo.RvalidKnown_A 0056412505256400496600
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo.WreadyKnown_A 0056412505256400496600
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo.gen_passthru_fifo.paramCheckPass 002918291800
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo.DataKnown_A 005641250529577900
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo.DataKnown_AKnownEnable 0056412505256400496600
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo.DepthKnown_A 0056412505256400496600
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo.RvalidKnown_A 0056412505256400496600
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo.WreadyKnown_A 0056412505256400496600
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo.gen_passthru_fifo.paramCheckPass 002918291800
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo.DataKnown_A 005641250525140200
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo.DataKnown_AKnownEnable 0056412505256400496600
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo.DepthKnown_A 0056412505256400496600
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo.RvalidKnown_A 0056412505256400496600
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo.WreadyKnown_A 0056412505256400496600
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass 002918291800
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo.DataKnown_A 005641250525140200
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo.DataKnown_AKnownEnable 0056412505256400496600
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo.DepthKnown_A 0056412505256400496600
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo.RvalidKnown_A 0056412505256400496600
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo.WreadyKnown_A 0056412505256400496600
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass 002918291800
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo.DataKnown_A 005641250524286500
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo.DataKnown_AKnownEnable 0056412505256400496600
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo.DepthKnown_A 0056412505256400496600
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo.RvalidKnown_A 0056412505256400496600
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo.WreadyKnown_A 0056412505256400496600
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass 002918291800
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo.DataKnown_A 005641250524437700
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo.DataKnown_AKnownEnable 0056412505256400496600
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo.DepthKnown_A 0056412505256400496600
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo.RvalidKnown_A 0056412505256400496600
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo.WreadyKnown_A 0056412505256400496600
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass 002918291800
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.maxN 002918291800
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.wePulse 00564125052882300
tb.dut.top_earlgrey.u_rv_core_ibex.u_sim_win_rsp.u_intg_gen.DataWidthCheck_A 001010101000
tb.dut.top_earlgrey.u_rv_core_ibex.u_sim_win_rsp.u_intg_gen.PayLoadWidthCheck 001010101000
tb.dut.top_earlgrey.u_rv_plic.FpvSecCmRegWeOnehotCheck_A 00491226693400
tb.dut.top_earlgrey.u_rv_plic.Irq0Tied_A 0049122669349112205100
tb.dut.top_earlgrey.u_rv_plic.IrqKnownO_A 0049122669349112205100
tb.dut.top_earlgrey.u_rv_plic.MsipKnownO_A 0049122669349112205100
tb.dut.top_earlgrey.u_rv_plic.TlAReadyKnownO_A 0049122669349112205100
tb.dut.top_earlgrey.u_rv_plic.TlDValidKnownO_A 0049122669349112205100
tb.dut.top_earlgrey.u_rv_plic.gen_irq_id_known[0].IrqIdKnownO_A 0049122669349112205100
tb.dut.top_earlgrey.u_rv_plic.gen_target[0].u_target.u_prim_max_tree.MaxComputationInvalid_A 0049122669348915596700
tb.dut.top_earlgrey.u_rv_plic.gen_target[0].u_target.u_prim_max_tree.MaxComputation_A 00491226693196608400
tb.dut.top_earlgrey.u_rv_plic.gen_target[0].u_target.u_prim_max_tree.MaxIndexComputationInvalid_A 0049122669348915596700
tb.dut.top_earlgrey.u_rv_plic.gen_target[0].u_target.u_prim_max_tree.MaxIndexComputation_A 00491226693196608400
tb.dut.top_earlgrey.u_rv_plic.gen_target[0].u_target.u_prim_max_tree.NumSources_A 001010101000
tb.dut.top_earlgrey.u_rv_plic.gen_target[0].u_target.u_prim_max_tree.ValidInImpliesValidOut_A 0049122669349112205100
tb.dut.top_earlgrey.u_rv_plic.onehot0Claim 0049122669349112205100
tb.dut.top_earlgrey.u_rv_plic.onehot0Complete 0049122669349112205100
tb.dut.top_earlgrey.u_rv_plic.u_reg.en2addrHit 0056412505217609500
tb.dut.top_earlgrey.u_rv_plic.u_reg.reAfterRv 0056412505217609500
tb.dut.top_earlgrey.u_rv_plic.u_reg.rePulse 0056412505210846000
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_chk.PayLoadWidthCheck 002918291800
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_reg_if.AllowedLatency_A 002918291800
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_reg_if.MatchedWidthAssert 002918291800
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_reg_if.u_err.dataWidthOnly32_A 002918291800
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A 002918291800
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck 002918291800
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_rsp_intg_gen.DataWidthCheck_A 002918291800
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_rsp_intg_gen.PayLoadWidthCheck 002918291800
tb.dut.top_earlgrey.u_rv_plic.u_reg.wePulse 005641250526763500
tb.dut.top_earlgrey.u_sensor_ctrl_aon.FpvSecCmRegWeOnehotCheck_A 00121064162800
tb.dut.top_earlgrey.u_sensor_ctrl_aon.NumAlertsMatch_A 001010101000
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_init_intr.IntrTKind_A 001010101000
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_io_intr.IntrTKind_A 001010101000
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.en2addrHit 00121064162546900
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.reAfterRv 00121064162546900
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.rePulse 00121064162394400
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_chk.PayLoadWidthCheck 001010101000
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_reg_if.AllowedLatency_A 001010101000
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_reg_if.MatchedWidthAssert 001010101000
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_reg_if.u_err.dataWidthOnly32_A 001010101000
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A 001010101000
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck 001010101000
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_rsp_intg_gen.DataWidthCheck_A 001010101000
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_rsp_intg_gen.PayLoadWidthCheck 001010101000
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.wePulse 00121064162152500
tb.dut.u_padring.gen_dio_pads[10].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001010101000
tb.dut.u_padring.gen_dio_pads[11].gen_mux_spi_host_d2.u_mux_dio_oe.gen_generic.u_impl_generic.selKnown0 00463600
tb.dut.u_padring.gen_dio_pads[11].gen_mux_spi_host_d2.u_mux_dio_oe.gen_generic.u_impl_generic.selKnown1 0018216700
tb.dut.u_padring.gen_dio_pads[11].gen_mux_spi_host_d2.u_mux_dio_out.gen_generic.u_impl_generic.selKnown0 005379536000
tb.dut.u_padring.gen_dio_pads[11].gen_mux_spi_host_d2.u_mux_dio_out.gen_generic.u_impl_generic.selKnown1 002492247100
tb.dut.u_padring.gen_dio_pads[11].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001010101000
tb.dut.u_padring.gen_dio_pads[12].gen_mux_spi_host_d3.u_mux_dio_oe.gen_generic.u_impl_generic.selKnown0 00372700
tb.dut.u_padring.gen_dio_pads[12].gen_mux_spi_host_d3.u_mux_dio_oe.gen_generic.u_impl_generic.selKnown1 0015013400
tb.dut.u_padring.gen_dio_pads[12].gen_mux_spi_host_d3.u_mux_dio_out.gen_generic.u_impl_generic.selKnown0 005383536400
tb.dut.u_padring.gen_dio_pads[12].gen_mux_spi_host_d3.u_mux_dio_out.gen_generic.u_impl_generic.selKnown1 0017916100
tb.dut.u_padring.gen_dio_pads[12].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001010101000
tb.dut.u_padring.gen_dio_pads[13].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001010101000
tb.dut.u_padring.gen_dio_pads[14].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001010101000
tb.dut.u_padring.gen_dio_pads[15].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001010101000
tb.dut.u_padring.gen_dio_pads[16].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001010101000
tb.dut.u_padring.gen_dio_pads[17].gen_mux_spi_dev_d2.u_mux_dio_oe.gen_generic.u_impl_generic.selKnown0 00735100
tb.dut.u_padring.gen_dio_pads[17].gen_mux_spi_dev_d2.u_mux_dio_oe.gen_generic.u_impl_generic.selKnown1 0015213800
tb.dut.u_padring.gen_dio_pads[17].gen_mux_spi_dev_d2.u_mux_dio_out.gen_generic.u_impl_generic.selKnown0 005723570100
tb.dut.u_padring.gen_dio_pads[17].gen_mux_spi_dev_d2.u_mux_dio_out.gen_generic.u_impl_generic.selKnown1 0053151700
tb.dut.u_padring.gen_dio_pads[17].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001010101000
tb.dut.u_padring.gen_dio_pads[18].gen_mux_spi_dev_d3.u_mux_dio_oe.gen_generic.u_impl_generic.selKnown0 00694700
tb.dut.u_padring.gen_dio_pads[18].gen_mux_spi_dev_d3.u_mux_dio_oe.gen_generic.u_impl_generic.selKnown1 0016515000
tb.dut.u_padring.gen_dio_pads[18].gen_mux_spi_dev_d3.u_mux_dio_out.gen_generic.u_impl_generic.selKnown0 005713569000
tb.dut.u_padring.gen_dio_pads[18].gen_mux_spi_dev_d3.u_mux_dio_out.gen_generic.u_impl_generic.selKnown1 0031330200
tb.dut.u_padring.gen_dio_pads[18].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001010101000
tb.dut.u_padring.gen_dio_pads[19].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001010101000
tb.dut.u_padring.gen_dio_pads[1].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001010101000
tb.dut.u_padring.gen_dio_pads[20].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001010101000
tb.dut.u_padring.gen_dio_pads[21].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001010101000
tb.dut.u_padring.gen_dio_pads[22].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001010101000
tb.dut.u_padring.gen_dio_pads[2].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001010101000
tb.dut.u_padring.gen_dio_pads[5].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001010101000
tb.dut.u_padring.gen_dio_pads[8].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001010101000
tb.dut.u_padring.gen_dio_pads[9].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001010101000
tb.dut.u_padring.gen_mio_pads[0].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001010101000
tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in.gen_generic.u_impl_generic.selKnown0 0023420400
tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in.gen_generic.u_impl_generic.selKnown1 005214518400
tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in_raw.gen_generic.u_impl_generic.selKnown0 0023720700
tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in_raw.gen_generic.u_impl_generic.selKnown1 005209517900
tb.dut.u_padring.gen_mio_pads[10].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001010101000
tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in.gen_generic.u_impl_generic.selKnown0 0055153000
tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in.gen_generic.u_impl_generic.selKnown1 00282762824300
tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in_raw.gen_generic.u_impl_generic.selKnown0 0055653500
tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in_raw.gen_generic.u_impl_generic.selKnown1 00282752824200
tb.dut.u_padring.gen_mio_pads[11].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001010101000
tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in.gen_generic.u_impl_generic.selKnown0 0047643200
tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in.gen_generic.u_impl_generic.selKnown1 00282692823500
tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in_raw.gen_generic.u_impl_generic.selKnown0 0047643200
tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in_raw.gen_generic.u_impl_generic.selKnown1 00282672823300
tb.dut.u_padring.gen_mio_pads[12].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001010101000
tb.dut.u_padring.gen_mio_pads[13].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001010101000
tb.dut.u_padring.gen_mio_pads[14].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001010101000
tb.dut.u_padring.gen_mio_pads[15].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001010101000
tb.dut.u_padring.gen_mio_pads[16].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001010101000
tb.dut.u_padring.gen_mio_pads[17].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001010101000
tb.dut.u_padring.gen_mio_pads[18].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001010101000
tb.dut.u_padring.gen_mio_pads[19].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001010101000
tb.dut.u_padring.gen_mio_pads[1].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001010101000
tb.dut.u_padring.gen_mio_pads[20].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001010101000
tb.dut.u_padring.gen_mio_pads[21].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001010101000
tb.dut.u_padring.gen_mio_pads[22].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001010101000
tb.dut.u_padring.gen_mio_pads[23].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001010101000
tb.dut.u_padring.gen_mio_pads[24].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001010101000
tb.dut.u_padring.gen_mio_pads[25].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001010101000
tb.dut.u_padring.gen_mio_pads[26].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001010101000
tb.dut.u_padring.gen_mio_pads[27].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001010101000
tb.dut.u_padring.gen_mio_pads[28].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001010101000
tb.dut.u_padring.gen_mio_pads[29].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001010101000
tb.dut.u_padring.gen_mio_pads[2].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001010101000
tb.dut.u_padring.gen_mio_pads[30].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001010101000
tb.dut.u_padring.gen_mio_pads[31].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001010101000
tb.dut.u_padring.gen_mio_pads[32].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001010101000
tb.dut.u_padring.gen_mio_pads[33].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001010101000
tb.dut.u_padring.gen_mio_pads[34].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001010101000
tb.dut.u_padring.gen_mio_pads[35].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001010101000
tb.dut.u_padring.gen_mio_pads[36].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001010101000
tb.dut.u_padring.gen_mio_pads[37].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001010101000
tb.dut.u_padring.gen_mio_pads[38].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001010101000
tb.dut.u_padring.gen_mio_pads[39].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001010101000
tb.dut.u_padring.gen_mio_pads[3].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001010101000
tb.dut.u_padring.gen_mio_pads[40].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001010101000
tb.dut.u_padring.gen_mio_pads[41].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001010101000
tb.dut.u_padring.gen_mio_pads[42].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001010101000
tb.dut.u_padring.gen_mio_pads[43].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001010101000
tb.dut.u_padring.gen_mio_pads[44].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001010101000
tb.dut.u_padring.gen_mio_pads[45].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001010101000
tb.dut.u_padring.gen_mio_pads[46].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001010101000
tb.dut.u_padring.gen_mio_pads[4].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001010101000
tb.dut.u_padring.gen_mio_pads[5].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001010101000
tb.dut.u_padring.gen_mio_pads[6].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001010101000
tb.dut.u_padring.gen_mio_pads[7].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001010101000
tb.dut.u_padring.gen_mio_pads[8].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001010101000
tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in.gen_generic.u_impl_generic.selKnown0 002533250900
tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in.gen_generic.u_impl_generic.selKnown1 005219519000
tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in_raw.gen_generic.u_impl_generic.selKnown0 002533250900
tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in_raw.gen_generic.u_impl_generic.selKnown1 005220519100
tb.dut.u_padring.gen_mio_pads[9].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 001010101000

Assertions Incomplete:
ASSERTIONS   CATEGORY   SEVERITY   ATTEMPTS   REAL SUCCESSES   FAILURES   INCOMPLETE   SRC   
tb.dut.top_earlgrey.u_pinmux_aon.PwrMgrStrapSampleOnce1_A 0012232203400963
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.DftTapOff0_A 00122322034377694670276
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.LcHwDebugEnClear_A 0012232203411934624015
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.LcHwDebugEnSetRev0_A 001223220341430098
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.LcHwDebugEnSetRev1_A 001223220341430098
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.RvTapOff0_A 001223220342530196
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_check_byp_en.gen_flops.OutputDelay_A 0012232203412163090403003
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en.gen_flops.OutputDelay_A 0012232203412163090403003
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_escalate_en.gen_flops.OutputDelay_A 0012232203412163090403003
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_hw_debug_en.gen_flops.OutputDelay_A 0012232203412163090403003
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A 001668691320972
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmIbexFetchEnable1_A 0049122669324416272096
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmIbexFetchEnable2_A 0049122669364195315082
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmIbexFetchEnable3Rev_A 0049122669342241632701998
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmIbexFetchEnable3_A 0049122669342241816801895
tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_packer_fifo.DataOStableWhenPending_A 0049122669300999
tb.dut.top_earlgrey.u_rv_core_ibex.u_lc_sync.gen_flops.OutputDelay_A 0049122669349111464702997
tb.dut.top_earlgrey.u_rv_core_ibex.u_pwrmgr_sync.gen_flops.OutputDelay_A 0049122669349111464702997

Assertions Excluded:
ASSERTIONS   CATEGORY   SEVERITY   EXCLUSION   SRC   
tb.dut.u_padring.gen_dio_pads[0].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 00Excluded
tb.dut.u_padring.gen_dio_pads[3].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 00Excluded
tb.dut.u_padring.gen_dio_pads[4].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 00Excluded
tb.dut.u_padring.gen_dio_pads[6].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 00Excluded
tb.dut.u_padring.gen_dio_pads[7].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A 00Excluded