| | | | | | | |
tb.dut.top_earlgrey.scanmodeKnown
| 0 | 0 | 497807442 | 497807442 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.AlertsKnown_A
| 0 | 0 | 122322034 | 121637656 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.AonWkupReqKnownO_A
| 0 | 0 | 1471672 | 1278560 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.DftJtagTckKnown_A
| 0 | 0 | 122322034 | 121637656 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.DftJtagTmsKnown_A
| 0 | 0 | 122322034 | 121637656 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.DftJtagTrstKnown_A
| 0 | 0 | 122322034 | 121637656 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.DftStrapsKnown_A
| 0 | 0 | 122322034 | 121637656 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.DioKnownO_A
| 0 | 0 | 122322034 | 121637656 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.DioOeKnownO_A
| 0 | 0 | 122322034 | 121637656 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.FpvSecCmRegWeOnehotCheck_A
| 0 | 0 | 122322034 | 5 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.LcJtagTckKnown_A
| 0 | 0 | 122322034 | 121637656 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.LcJtagTmsKnown_A
| 0 | 0 | 122322034 | 121637656 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.LcJtagTrstKnown_A
| 0 | 0 | 122322034 | 121637656 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.MioKnownO_A
| 0 | 0 | 122322034 | 121637656 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.MioOeKnownO_A
| 0 | 0 | 122322034 | 121637656 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.PinmuxWkupStable_A
| 0 | 0 | 1471672 | 5186 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.PwrMgrStrapSampleOnce0_A
| 0 | 0 | 122322034 | 1683 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.RvJtagTckKnown_A
| 0 | 0 | 122322034 | 121637656 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.RvJtagTmsKnown_A
| 0 | 0 | 122322034 | 121637656 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.RvJtagTrstKnown_A
| 0 | 0 | 122322034 | 121637656 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.TlAReadyKnownO_A
| 0 | 0 | 122322034 | 121637656 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.TlDValidKnownO_A
| 0 | 0 | 122322034 | 121637656 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.UsbWakeDetectActiveKnownO_A
| 0 | 0 | 1471672 | 1278560 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.UsbWkupReqKnownO_A
| 0 | 0 | 1471672 | 1278560 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.DftTapOff0_A
| 0 | 0 | 122322034 | 37769467 | 0 | 276 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.LcHwDebugEnClear_A
| 0 | 0 | 122322034 | 11934624 | 0 | 15 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.LcHwDebugEnSetRev0_A
| 0 | 0 | 122322034 | 1430 | 0 | 98 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.LcHwDebugEnSetRev1_A
| 0 | 0 | 122322034 | 1430 | 0 | 98 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.LcHwDebugEnSet_A
| 0 | 0 | 122322034 | 1430 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.RvTapOff0_A
| 0 | 0 | 122322034 | 253 | 0 | 196 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.RvTapOff1_A
| 0 | 0 | 122322034 | 34845486 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.TapStrapKnown_A
| 0 | 0 | 122322034 | 121637764 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.dft_strap0_idxRange_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.dft_strap1_idxRange_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.tap_strap0_idxRange_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.tap_strap1_idxRange_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.tck_idxRange_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.tdi_idxRange_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.tdo_idxRange_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.tms_idxRange_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.trst_idxRange_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_por_scanmode_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_por_scanmode_sync.OutputsKnown_A
| 0 | 0 | 122322034 | 121637764 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_por_scanmode_sync.gen_no_flops.OutputDelay_A
| 0 | 0 | 122322034 | 121637764 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.FunctionCheck_A
| 0 | 0 | 122322034 | 121637764 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.OutputsKnown_A
| 0 | 0 | 122322034 | 121637764 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_a.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_a.OutputsKnown_A
| 0 | 0 | 122322034 | 121637764 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_a.gen_no_flops.OutputDelay_A
| 0 | 0 | 122322034 | 121637764 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_b.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_b.OutputsKnown_A
| 0 | 0 | 122322034 | 121637764 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_b.gen_no_flops.OutputDelay_A
| 0 | 0 | 122322034 | 121637764 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_check_byp_en.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_check_byp_en.OutputsKnown_A
| 0 | 0 | 122322034 | 121637764 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_check_byp_en.gen_flops.OutputDelay_A
| 0 | 0 | 122322034 | 121630904 | 0 | 3003 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en.OutputsKnown_A
| 0 | 0 | 122322034 | 121637764 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en.gen_flops.OutputDelay_A
| 0 | 0 | 122322034 | 121630904 | 0 | 3003 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_escalate_en.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_escalate_en.OutputsKnown_A
| 0 | 0 | 122322034 | 121637764 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_escalate_en.gen_flops.OutputDelay_A
| 0 | 0 | 122322034 | 121630904 | 0 | 3003 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_hw_debug_en.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_hw_debug_en.OutputsKnown_A
| 0 | 0 | 122322034 | 121637764 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_hw_debug_en.gen_flops.OutputDelay_A
| 0 | 0 | 122322034 | 121630904 | 0 | 3003 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_pinmux_hw_debug_en.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_pinmux_hw_debug_en.OutputsKnown_A
| 0 | 0 | 122322034 | 121637764 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_pinmux_hw_debug_en.gen_no_flops.OutputDelay_A
| 0 | 0 | 122322034 | 121637764 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_rst_por_aon_n_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 780 | 649 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_rst_por_aon_n_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 1725 | 725 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.en2addrHit
| 0 | 0 | 140595849 | 414945 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.reAfterRv
| 0 | 0 | 140595849 | 414945 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.rePulse
| 0 | 0 | 140595849 | 283279 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_chk.PayLoadWidthCheck
| 0 | 0 | 2918 | 2918 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_reg_if.AllowedLatency_A
| 0 | 0 | 2918 | 2918 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_reg_if.MatchedWidthAssert
| 0 | 0 | 2918 | 2918 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_reg_if.u_err.dataWidthOnly32_A
| 0 | 0 | 2918 | 2918 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A
| 0 | 0 | 2918 | 2918 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck
| 0 | 0 | 2918 | 2918 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_rsp_intg_gen.DataWidthCheck_A
| 0 | 0 | 2918 | 2918 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_rsp_intg_gen.PayLoadWidthCheck
| 0 | 0 | 2918 | 2918 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.BusySrcReqChk_A
| 0 | 0 | 140595849 | 123692 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.DstReqKnown_A
| 0 | 0 | 1668691 | 1446789 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.SrcAckBusyChk_A
| 0 | 0 | 140595849 | 270 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.SrcBusyKnown_A
| 0 | 0 | 140595849 | 139789547 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A
| 0 | 0 | 1668691 | 32 | 0 | 972 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.u_arb.gen_wr_req.HwIdSelCheck_A
| 0 | 0 | 1668691 | 32 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq
| 0 | 0 | 140595849 | 302 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq
| 0 | 0 | 1668691 | 157 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 1668691 | 269 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 140595849 | 273 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc.BusySrcReqChk_A
| 0 | 0 | 140595849 | 92475 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc.DstReqKnown_A
| 0 | 0 | 1668691 | 1446789 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc.SrcAckBusyChk_A
| 0 | 0 | 140595849 | 236 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc.SrcBusyKnown_A
| 0 | 0 | 140595849 | 139789547 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 140595849 | 236 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 1668691 | 236 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 1668691 | 236 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 140595849 | 236 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc.BusySrcReqChk_A
| 0 | 0 | 140595849 | 80169 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc.DstReqKnown_A
| 0 | 0 | 1668691 | 1446789 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc.SrcAckBusyChk_A
| 0 | 0 | 140595849 | 206 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc.SrcBusyKnown_A
| 0 | 0 | 140595849 | 139789547 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 140595849 | 206 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 1668691 | 206 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 1668691 | 206 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 140595849 | 206 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc.BusySrcReqChk_A
| 0 | 0 | 140595849 | 86566 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc.DstReqKnown_A
| 0 | 0 | 1668691 | 1446789 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc.SrcAckBusyChk_A
| 0 | 0 | 140595849 | 224 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc.SrcBusyKnown_A
| 0 | 0 | 140595849 | 139789547 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 140595849 | 224 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 1668691 | 224 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 1668691 | 224 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 140595849 | 224 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc.BusySrcReqChk_A
| 0 | 0 | 140595849 | 89743 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc.DstReqKnown_A
| 0 | 0 | 1668691 | 1446789 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc.SrcAckBusyChk_A
| 0 | 0 | 140595849 | 226 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc.SrcBusyKnown_A
| 0 | 0 | 140595849 | 139789547 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 140595849 | 226 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 1668691 | 226 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 1668691 | 226 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 140595849 | 226 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc.BusySrcReqChk_A
| 0 | 0 | 140595849 | 87123 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc.DstReqKnown_A
| 0 | 0 | 1668691 | 1446789 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc.SrcAckBusyChk_A
| 0 | 0 | 140595849 | 224 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc.SrcBusyKnown_A
| 0 | 0 | 140595849 | 139789547 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 140595849 | 224 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 1668691 | 224 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 1668691 | 224 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 140595849 | 224 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc.BusySrcReqChk_A
| 0 | 0 | 140595849 | 80484 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc.DstReqKnown_A
| 0 | 0 | 1668691 | 1446789 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc.SrcAckBusyChk_A
| 0 | 0 | 140595849 | 208 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc.SrcBusyKnown_A
| 0 | 0 | 140595849 | 139789547 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 140595849 | 208 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 1668691 | 208 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 1668691 | 208 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 140595849 | 208 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc.BusySrcReqChk_A
| 0 | 0 | 140595849 | 87570 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc.DstReqKnown_A
| 0 | 0 | 1668691 | 1446789 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc.SrcAckBusyChk_A
| 0 | 0 | 140595849 | 223 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc.SrcBusyKnown_A
| 0 | 0 | 140595849 | 139789547 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 140595849 | 223 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 1668691 | 223 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 1668691 | 223 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 140595849 | 223 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc.BusySrcReqChk_A
| 0 | 0 | 140595849 | 87685 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc.DstReqKnown_A
| 0 | 0 | 1668691 | 1446789 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc.SrcAckBusyChk_A
| 0 | 0 | 140595849 | 226 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc.SrcBusyKnown_A
| 0 | 0 | 140595849 | 139789547 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 140595849 | 226 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 1668691 | 226 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 1668691 | 226 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 140595849 | 226 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc.BusySrcReqChk_A
| 0 | 0 | 140595849 | 101912 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc.DstReqKnown_A
| 0 | 0 | 1668691 | 1446789 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc.SrcAckBusyChk_A
| 0 | 0 | 140595849 | 257 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc.SrcBusyKnown_A
| 0 | 0 | 140595849 | 139789547 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 140595849 | 257 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 1668691 | 257 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 1668691 | 257 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 140595849 | 257 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc.BusySrcReqChk_A
| 0 | 0 | 140595849 | 79519 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc.DstReqKnown_A
| 0 | 0 | 1668691 | 1446789 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc.SrcAckBusyChk_A
| 0 | 0 | 140595849 | 206 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc.SrcBusyKnown_A
| 0 | 0 | 140595849 | 139789547 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 140595849 | 206 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 1668691 | 206 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 1668691 | 202 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 140595849 | 206 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc.BusySrcReqChk_A
| 0 | 0 | 140595849 | 83761 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc.DstReqKnown_A
| 0 | 0 | 1668691 | 1446789 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc.SrcAckBusyChk_A
| 0 | 0 | 140595849 | 212 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc.SrcBusyKnown_A
| 0 | 0 | 140595849 | 139789547 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 140595849 | 212 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 1668691 | 212 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 1668691 | 212 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 140595849 | 212 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.BusySrcReqChk_A
| 0 | 0 | 140595849 | 87418 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.DstReqKnown_A
| 0 | 0 | 1668691 | 1446789 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.SrcAckBusyChk_A
| 0 | 0 | 140595849 | 224 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.SrcBusyKnown_A
| 0 | 0 | 140595849 | 139789547 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 140595849 | 224 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 1668691 | 224 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 1668691 | 224 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 140595849 | 224 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.BusySrcReqChk_A
| 0 | 0 | 140595849 | 95812 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.DstReqKnown_A
| 0 | 0 | 1668691 | 1446789 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.SrcAckBusyChk_A
| 0 | 0 | 140595849 | 242 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.SrcBusyKnown_A
| 0 | 0 | 140595849 | 139789547 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 140595849 | 242 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 1668691 | 242 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 1668691 | 242 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 140595849 | 242 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.BusySrcReqChk_A
| 0 | 0 | 140595849 | 79502 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.DstReqKnown_A
| 0 | 0 | 1668691 | 1446789 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.SrcAckBusyChk_A
| 0 | 0 | 140595849 | 205 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.SrcBusyKnown_A
| 0 | 0 | 140595849 | 139789547 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 140595849 | 205 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 1668691 | 205 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 1668691 | 205 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 140595849 | 205 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.BusySrcReqChk_A
| 0 | 0 | 140595849 | 90700 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.DstReqKnown_A
| 0 | 0 | 1668691 | 1446789 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.SrcAckBusyChk_A
| 0 | 0 | 140595849 | 230 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.SrcBusyKnown_A
| 0 | 0 | 140595849 | 139789547 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 140595849 | 230 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 1668691 | 230 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 1668691 | 230 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 140595849 | 230 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.BusySrcReqChk_A
| 0 | 0 | 140595849 | 88433 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.DstReqKnown_A
| 0 | 0 | 1668691 | 1446789 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.SrcAckBusyChk_A
| 0 | 0 | 140595849 | 225 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.SrcBusyKnown_A
| 0 | 0 | 140595849 | 139789547 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 140595849 | 225 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 1668691 | 225 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 1668691 | 225 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 140595849 | 225 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc.BusySrcReqChk_A
| 0 | 0 | 140595849 | 91720 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc.DstReqKnown_A
| 0 | 0 | 1668691 | 1446789 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc.SrcAckBusyChk_A
| 0 | 0 | 140595849 | 233 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc.SrcBusyKnown_A
| 0 | 0 | 140595849 | 139789547 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 140595849 | 233 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 1668691 | 233 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 1668691 | 233 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 140595849 | 235 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc.BusySrcReqChk_A
| 0 | 0 | 140595849 | 78234 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc.DstReqKnown_A
| 0 | 0 | 1668691 | 1446789 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc.SrcAckBusyChk_A
| 0 | 0 | 140595849 | 204 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc.SrcBusyKnown_A
| 0 | 0 | 140595849 | 139789547 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 140595849 | 204 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 1668691 | 204 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 1668691 | 204 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 140595849 | 204 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc.BusySrcReqChk_A
| 0 | 0 | 140595849 | 89947 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc.DstReqKnown_A
| 0 | 0 | 1668691 | 1446789 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc.SrcAckBusyChk_A
| 0 | 0 | 140595849 | 230 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc.SrcBusyKnown_A
| 0 | 0 | 140595849 | 139789547 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 140595849 | 230 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 1668691 | 230 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 1668691 | 230 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 140595849 | 230 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc.BusySrcReqChk_A
| 0 | 0 | 140595849 | 91058 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc.DstReqKnown_A
| 0 | 0 | 1668691 | 1446789 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc.SrcAckBusyChk_A
| 0 | 0 | 140595849 | 233 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc.SrcBusyKnown_A
| 0 | 0 | 140595849 | 139789547 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 140595849 | 233 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 1668691 | 233 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 1668691 | 233 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 140595849 | 234 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc.BusySrcReqChk_A
| 0 | 0 | 140595849 | 83763 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc.DstReqKnown_A
| 0 | 0 | 1668691 | 1446789 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc.SrcAckBusyChk_A
| 0 | 0 | 140595849 | 215 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc.SrcBusyKnown_A
| 0 | 0 | 140595849 | 139789547 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 140595849 | 215 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 1668691 | 215 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 1668691 | 214 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 140595849 | 215 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc.BusySrcReqChk_A
| 0 | 0 | 140595849 | 99847 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc.DstReqKnown_A
| 0 | 0 | 1668691 | 1446789 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc.SrcAckBusyChk_A
| 0 | 0 | 140595849 | 257 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc.SrcBusyKnown_A
| 0 | 0 | 140595849 | 139789547 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 140595849 | 257 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 1668691 | 257 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 1668691 | 257 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 140595849 | 258 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc.BusySrcReqChk_A
| 0 | 0 | 140595849 | 85402 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc.DstReqKnown_A
| 0 | 0 | 1668691 | 1446789 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc.SrcAckBusyChk_A
| 0 | 0 | 140595849 | 221 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc.SrcBusyKnown_A
| 0 | 0 | 140595849 | 139789547 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 140595849 | 221 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 1668691 | 221 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 1668691 | 221 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 140595849 | 222 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc.BusySrcReqChk_A
| 0 | 0 | 140595849 | 85002 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc.DstReqKnown_A
| 0 | 0 | 1668691 | 1446789 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc.SrcAckBusyChk_A
| 0 | 0 | 140595849 | 218 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc.SrcBusyKnown_A
| 0 | 0 | 140595849 | 139789547 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 140595849 | 218 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 1668691 | 218 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 1668691 | 217 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 140595849 | 218 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.wePulse
| 0 | 0 | 140595849 | 131666 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_usbdev_aon_wake.WakeDetectActiveAonKnown_A
| 0 | 0 | 1471672 | 1278560 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmIbexFetchEnable0_A
| 0 | 0 | 491226693 | 5 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmIbexFetchEnable1_A
| 0 | 0 | 491226693 | 24416272 | 0 | 96 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmIbexFetchEnable2_A
| 0 | 0 | 491226693 | 64195315 | 0 | 82 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmIbexFetchEnable3Rev_A
| 0 | 0 | 491226693 | 422416327 | 0 | 1998 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmIbexFetchEnable3_A
| 0 | 0 | 491226693 | 422418168 | 0 | 1895 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmIbexInstrIntgErrCheck_A
| 0 | 0 | 491226693 | 307 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmIbexLoadRespIntgErrCheck_A
| 0 | 0 | 491226693 | 586 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmRegWeOnehotCheck_A
| 0 | 0 | 491226693 | 3 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo.DataKnown_A
| 0 | 0 | 491226693 | 42947658 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo.DataKnown_AKnownEnable
| 0 | 0 | 491226693 | 491122051 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo.DepthKnown_A
| 0 | 0 | 491226693 | 491122051 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo.RvalidKnown_A
| 0 | 0 | 491226693 | 491122051 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo.WreadyKnown_A
| 0 | 0 | 491226693 | 491122051 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo.DataKnown_A
| 0 | 0 | 491226693 | 35985095 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo.DataKnown_AKnownEnable
| 0 | 0 | 491226693 | 491122051 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo.DepthKnown_A
| 0 | 0 | 491226693 | 491122051 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo.RvalidKnown_A
| 0 | 0 | 491226693 | 491122051 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo.WreadyKnown_A
| 0 | 0 | 491226693 | 491122051 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo.DataKnown_A
| 0 | 0 | 491226693 | 59413671 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo.DataKnown_AKnownEnable
| 0 | 0 | 491226693 | 491122051 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo.DepthKnown_A
| 0 | 0 | 491226693 | 491122051 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo.RvalidKnown_A
| 0 | 0 | 491226693 | 491122051 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo.WreadyKnown_A
| 0 | 0 | 491226693 | 491122051 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo.gen_passthru_fifo.paramCheckPass
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo.DataKnown_A
| 0 | 0 | 491226693 | 44469775 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo.DataKnown_AKnownEnable
| 0 | 0 | 491226693 | 491122051 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo.DepthKnown_A
| 0 | 0 | 491226693 | 491122051 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo.RvalidKnown_A
| 0 | 0 | 491226693 | 491122051 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo.WreadyKnown_A
| 0 | 0 | 491226693 | 491122051 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo.gen_passthru_fifo.paramCheckPass
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.g_instr_intg_err_assert_signals.AssertConnected_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.g_lsu_load_resp_intg_err_assert_signals.AssertConnected_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.g_lsu_store_resp_intg_err_assert_signals.AssertConnected_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.g_pc_mismatch_alert_o_assert_signals.AssertConnected_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.g_rf_ecc_err_comb_assert_signals.AssertConnected_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.gen_icache_scramble_asserts.IbexIcacheScrambleKeyForwardedToCore_A
| 0 | 0 | 491226693 | 169 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.gen_icache_scramble_asserts.IbexIcacheScrambleKeyRequestAfterFenceI_A
| 0 | 0 | 491226693 | 190 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex.DontExceeedMaxReqs
| 0 | 0 | 491226693 | 42903280 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex.u_cmd_intg_gen.PayMaxWidthCheck_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex.u_rsp_chk.PayLoadWidthCheck
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_i_ibex.DontExceeedMaxReqs
| 0 | 0 | 491226693 | 59413671 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_i_ibex.u_cmd_intg_gen.PayMaxWidthCheck_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_i_ibex.u_rsp_chk.PayLoadWidthCheck
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.CheckHotOne_A
| 0 | 0 | 491226693 | 484071909 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.CheckNGreaterZero_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.GntImpliesReady_A
| 0 | 0 | 491226693 | 3189 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.GntImpliesValid_A
| 0 | 0 | 491226693 | 3189 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.GrantKnown_A
| 0 | 0 | 491226693 | 484071909 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.IdxKnown_A
| 0 | 0 | 491226693 | 484071909 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.IndexIsCorrect_A
| 0 | 0 | 491226693 | 3189 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.Priority_A
| 0 | 0 | 491226693 | 3189 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.ReadyAndValidImplyGrant_A
| 0 | 0 | 491226693 | 3189 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.ReqAndReadyImplyGrant_A
| 0 | 0 | 491226693 | 3189 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.ReqImpliesValid_A
| 0 | 0 | 491226693 | 3189 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.ValidKnown_A
| 0 | 0 | 491226693 | 484071909 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.gen_data_port_assertion.DataFlow_A
| 0 | 0 | 491226693 | 3189 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.DataOutputDiffFromPrev_A
| 0 | 0 | 490575137 | 103680335 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.DataOutputValid_A
| 0 | 0 | 491226693 | 4334 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data.gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA
| 0 | 0 | 491226693 | 4334 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data.gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB
| 0 | 0 | 491226693 | 4334 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data.u_prim_sync_reqack.SyncReqAckAckNeedsReq
| 0 | 0 | 491226693 | 4334 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data.u_prim_sync_reqack.SyncReqAckHoldReq
| 0 | 0 | 491226693 | 4334 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.CheckHotOne_A
| 0 | 0 | 491226693 | 484071909 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.CheckNGreaterZero_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.GntImpliesReady_A
| 0 | 0 | 491226693 | 5175 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.GntImpliesValid_A
| 0 | 0 | 491226693 | 5175 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.GrantKnown_A
| 0 | 0 | 491226693 | 484071909 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.IdxKnown_A
| 0 | 0 | 491226693 | 484071909 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.IndexIsCorrect_A
| 0 | 0 | 491226693 | 5175 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.Priority_A
| 0 | 0 | 491226693 | 5175 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.ReadyAndValidImplyGrant_A
| 0 | 0 | 491226693 | 5175 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.ReqAndReadyImplyGrant_A
| 0 | 0 | 491226693 | 5175 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.ReqImpliesValid_A
| 0 | 0 | 491226693 | 5175 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.ValidKnown_A
| 0 | 0 | 491226693 | 484071909 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.gen_data_port_assertion.DataFlow_A
| 0 | 0 | 491226693 | 5175 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_lc_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_lc_sync.OutputsKnown_A
| 0 | 0 | 491226693 | 491122051 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_lc_sync.gen_flops.OutputDelay_A
| 0 | 0 | 491226693 | 491114647 | 0 | 2997 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data.gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA
| 0 | 0 | 491226693 | 40 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data.gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB
| 0 | 0 | 491226693 | 40 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data.u_prim_sync_reqack.SyncReqAckAckNeedsReq
| 0 | 0 | 121064162 | 40 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data.u_prim_sync_reqack.SyncReqAckHoldReq
| 0 | 0 | 491226693 | 40 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_pwrmgr_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_pwrmgr_sync.OutputsKnown_A
| 0 | 0 | 491226693 | 491122051 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_pwrmgr_sync.gen_flops.OutputDelay_A
| 0 | 0 | 491226693 | 491114647 | 0 | 2997 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.en2addrHit
| 0 | 0 | 564125052 | 39924 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.reAfterRv
| 0 | 0 | 564125052 | 39924 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.rePulse
| 0 | 0 | 564125052 | 31101 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_chk.PayLoadWidthCheck
| 0 | 0 | 2918 | 2918 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_reg_if.AllowedLatency_A
| 0 | 0 | 2918 | 2918 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_reg_if.MatchedWidthAssert
| 0 | 0 | 2918 | 2918 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_reg_if.u_err.dataWidthOnly32_A
| 0 | 0 | 2918 | 2918 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A
| 0 | 0 | 2918 | 2918 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck
| 0 | 0 | 2918 | 2918 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_rsp_intg_gen.DataWidthCheck_A
| 0 | 0 | 2918 | 2918 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_rsp_intg_gen.PayLoadWidthCheck
| 0 | 0 | 2918 | 2918 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.NotOverflowed_A
| 0 | 0 | 564125052 | 564004966 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo.DataKnown_A
| 0 | 0 | 564125052 | 94267 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo.DataKnown_AKnownEnable
| 0 | 0 | 564125052 | 564004966 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo.DepthKnown_A
| 0 | 0 | 564125052 | 564004966 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo.RvalidKnown_A
| 0 | 0 | 564125052 | 564004966 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo.WreadyKnown_A
| 0 | 0 | 564125052 | 564004966 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo.gen_passthru_fifo.paramCheckPass
| 0 | 0 | 2918 | 2918 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo.DataKnown_A
| 0 | 0 | 564125052 | 95779 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo.DataKnown_AKnownEnable
| 0 | 0 | 564125052 | 564004966 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo.DepthKnown_A
| 0 | 0 | 564125052 | 564004966 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo.RvalidKnown_A
| 0 | 0 | 564125052 | 564004966 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo.WreadyKnown_A
| 0 | 0 | 564125052 | 564004966 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo.gen_passthru_fifo.paramCheckPass
| 0 | 0 | 2918 | 2918 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo.DataKnown_A
| 0 | 0 | 564125052 | 51402 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo.DataKnown_AKnownEnable
| 0 | 0 | 564125052 | 564004966 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo.DepthKnown_A
| 0 | 0 | 564125052 | 564004966 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo.RvalidKnown_A
| 0 | 0 | 564125052 | 564004966 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo.WreadyKnown_A
| 0 | 0 | 564125052 | 564004966 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass
| 0 | 0 | 2918 | 2918 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo.DataKnown_A
| 0 | 0 | 564125052 | 51402 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo.DataKnown_AKnownEnable
| 0 | 0 | 564125052 | 564004966 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo.DepthKnown_A
| 0 | 0 | 564125052 | 564004966 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo.RvalidKnown_A
| 0 | 0 | 564125052 | 564004966 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo.WreadyKnown_A
| 0 | 0 | 564125052 | 564004966 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass
| 0 | 0 | 2918 | 2918 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo.DataKnown_A
| 0 | 0 | 564125052 | 42865 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo.DataKnown_AKnownEnable
| 0 | 0 | 564125052 | 564004966 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo.DepthKnown_A
| 0 | 0 | 564125052 | 564004966 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo.RvalidKnown_A
| 0 | 0 | 564125052 | 564004966 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo.WreadyKnown_A
| 0 | 0 | 564125052 | 564004966 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass
| 0 | 0 | 2918 | 2918 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo.DataKnown_A
| 0 | 0 | 564125052 | 44377 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo.DataKnown_AKnownEnable
| 0 | 0 | 564125052 | 564004966 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo.DepthKnown_A
| 0 | 0 | 564125052 | 564004966 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo.RvalidKnown_A
| 0 | 0 | 564125052 | 564004966 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo.WreadyKnown_A
| 0 | 0 | 564125052 | 564004966 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass
| 0 | 0 | 2918 | 2918 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.maxN
| 0 | 0 | 2918 | 2918 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.wePulse
| 0 | 0 | 564125052 | 8823 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_sim_win_rsp.u_intg_gen.DataWidthCheck_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_sim_win_rsp.u_intg_gen.PayLoadWidthCheck
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.FpvSecCmRegWeOnehotCheck_A
| 0 | 0 | 491226693 | 4 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.Irq0Tied_A
| 0 | 0 | 491226693 | 491122051 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.IrqKnownO_A
| 0 | 0 | 491226693 | 491122051 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.MsipKnownO_A
| 0 | 0 | 491226693 | 491122051 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.TlAReadyKnownO_A
| 0 | 0 | 491226693 | 491122051 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.TlDValidKnownO_A
| 0 | 0 | 491226693 | 491122051 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.gen_irq_id_known[0].IrqIdKnownO_A
| 0 | 0 | 491226693 | 491122051 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.gen_target[0].u_target.u_prim_max_tree.MaxComputationInvalid_A
| 0 | 0 | 491226693 | 489155967 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.gen_target[0].u_target.u_prim_max_tree.MaxComputation_A
| 0 | 0 | 491226693 | 1966084 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.gen_target[0].u_target.u_prim_max_tree.MaxIndexComputationInvalid_A
| 0 | 0 | 491226693 | 489155967 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.gen_target[0].u_target.u_prim_max_tree.MaxIndexComputation_A
| 0 | 0 | 491226693 | 1966084 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.gen_target[0].u_target.u_prim_max_tree.NumSources_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.gen_target[0].u_target.u_prim_max_tree.ValidInImpliesValidOut_A
| 0 | 0 | 491226693 | 491122051 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.onehot0Claim
| 0 | 0 | 491226693 | 491122051 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.onehot0Complete
| 0 | 0 | 491226693 | 491122051 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.u_reg.en2addrHit
| 0 | 0 | 564125052 | 176095 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.u_reg.reAfterRv
| 0 | 0 | 564125052 | 176095 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.u_reg.rePulse
| 0 | 0 | 564125052 | 108460 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_chk.PayLoadWidthCheck
| 0 | 0 | 2918 | 2918 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_reg_if.AllowedLatency_A
| 0 | 0 | 2918 | 2918 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_reg_if.MatchedWidthAssert
| 0 | 0 | 2918 | 2918 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_reg_if.u_err.dataWidthOnly32_A
| 0 | 0 | 2918 | 2918 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A
| 0 | 0 | 2918 | 2918 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck
| 0 | 0 | 2918 | 2918 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_rsp_intg_gen.DataWidthCheck_A
| 0 | 0 | 2918 | 2918 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_rsp_intg_gen.PayLoadWidthCheck
| 0 | 0 | 2918 | 2918 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.u_reg.wePulse
| 0 | 0 | 564125052 | 67635 | 0 | 0 |
|
tb.dut.top_earlgrey.u_sensor_ctrl_aon.FpvSecCmRegWeOnehotCheck_A
| 0 | 0 | 121064162 | 8 | 0 | 0 |
|
tb.dut.top_earlgrey.u_sensor_ctrl_aon.NumAlertsMatch_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_init_intr.IntrTKind_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_io_intr.IntrTKind_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.en2addrHit
| 0 | 0 | 121064162 | 5469 | 0 | 0 |
|
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.reAfterRv
| 0 | 0 | 121064162 | 5469 | 0 | 0 |
|
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.rePulse
| 0 | 0 | 121064162 | 3944 | 0 | 0 |
|
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_chk.PayLoadWidthCheck
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_reg_if.AllowedLatency_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_reg_if.MatchedWidthAssert
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_reg_if.u_err.dataWidthOnly32_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_rsp_intg_gen.DataWidthCheck_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_rsp_intg_gen.PayLoadWidthCheck
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.wePulse
| 0 | 0 | 121064162 | 1525 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[10].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[11].gen_mux_spi_host_d2.u_mux_dio_oe.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 46 | 36 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[11].gen_mux_spi_host_d2.u_mux_dio_oe.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 182 | 167 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[11].gen_mux_spi_host_d2.u_mux_dio_out.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 5379 | 5360 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[11].gen_mux_spi_host_d2.u_mux_dio_out.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2492 | 2471 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[11].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[12].gen_mux_spi_host_d3.u_mux_dio_oe.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 37 | 27 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[12].gen_mux_spi_host_d3.u_mux_dio_oe.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 150 | 134 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[12].gen_mux_spi_host_d3.u_mux_dio_out.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 5383 | 5364 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[12].gen_mux_spi_host_d3.u_mux_dio_out.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 179 | 161 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[12].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[13].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[14].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[15].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[16].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[17].gen_mux_spi_dev_d2.u_mux_dio_oe.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 73 | 51 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[17].gen_mux_spi_dev_d2.u_mux_dio_oe.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 152 | 138 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[17].gen_mux_spi_dev_d2.u_mux_dio_out.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 5723 | 5701 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[17].gen_mux_spi_dev_d2.u_mux_dio_out.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 531 | 517 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[17].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[18].gen_mux_spi_dev_d3.u_mux_dio_oe.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 69 | 47 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[18].gen_mux_spi_dev_d3.u_mux_dio_oe.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 165 | 150 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[18].gen_mux_spi_dev_d3.u_mux_dio_out.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 5713 | 5690 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[18].gen_mux_spi_dev_d3.u_mux_dio_out.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 313 | 302 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[18].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[19].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[1].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[20].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[21].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[22].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[2].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[5].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[8].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[9].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[0].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 234 | 204 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 5214 | 5184 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in_raw.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 237 | 207 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in_raw.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 5209 | 5179 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[10].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 551 | 530 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 28276 | 28243 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in_raw.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 556 | 535 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in_raw.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 28275 | 28242 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[11].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 476 | 432 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 28269 | 28235 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in_raw.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 476 | 432 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in_raw.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 28267 | 28233 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[12].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[13].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[14].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[15].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[16].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[17].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[18].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[19].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[1].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[20].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[21].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[22].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[23].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[24].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[25].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[26].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[27].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[28].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[29].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[2].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[30].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[31].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[32].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[33].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[34].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[35].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[36].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[37].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[38].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[39].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[3].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[40].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[41].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[42].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[43].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[44].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[45].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[46].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[4].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[5].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[6].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[7].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[8].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 2533 | 2509 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 5219 | 5190 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in_raw.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 2533 | 2509 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in_raw.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 5220 | 5191 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[9].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1010 | 1010 | 0 | 0 |
|