| | | | | | | |
tb.dut.top_earlgrey.scanmodeKnown
| 0 | 0 | 515741770 | 515741770 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.AlertsKnown_A
| 0 | 0 | 128850066 | 128149990 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.AonWkupReqKnownO_A
| 0 | 0 | 1494058 | 1299108 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.DftJtagTckKnown_A
| 0 | 0 | 128850066 | 128149990 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.DftJtagTmsKnown_A
| 0 | 0 | 128850066 | 128149990 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.DftJtagTrstKnown_A
| 0 | 0 | 128850066 | 128149990 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.DftStrapsKnown_A
| 0 | 0 | 128850066 | 128149990 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.DioKnownO_A
| 0 | 0 | 128850066 | 128149990 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.DioOeKnownO_A
| 0 | 0 | 128850066 | 128149990 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.FpvSecCmRegWeOnehotCheck_A
| 0 | 0 | 128850066 | 4 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.LcJtagTckKnown_A
| 0 | 0 | 128850066 | 128149990 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.LcJtagTmsKnown_A
| 0 | 0 | 128850066 | 128149990 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.LcJtagTrstKnown_A
| 0 | 0 | 128850066 | 128149990 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.MioKnownO_A
| 0 | 0 | 128850066 | 128149990 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.MioOeKnownO_A
| 0 | 0 | 128850066 | 128149990 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.PinmuxWkupStable_A
| 0 | 0 | 1494058 | 3968 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.PwrMgrStrapSampleOnce0_A
| 0 | 0 | 128850066 | 1730 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.RvJtagTckKnown_A
| 0 | 0 | 128850066 | 128149990 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.RvJtagTmsKnown_A
| 0 | 0 | 128850066 | 128149990 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.RvJtagTrstKnown_A
| 0 | 0 | 128850066 | 128149990 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.TlAReadyKnownO_A
| 0 | 0 | 128850066 | 128149990 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.TlDValidKnownO_A
| 0 | 0 | 128850066 | 128149990 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.UsbWakeDetectActiveKnownO_A
| 0 | 0 | 1494058 | 1299108 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.UsbWkupReqKnownO_A
| 0 | 0 | 1494058 | 1299108 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.DftTapOff0_A
| 0 | 0 | 128850066 | 33994255 | 0 | 272 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.LcHwDebugEnClear_A
| 0 | 0 | 128850066 | 11879814 | 0 | 15 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.LcHwDebugEnSetRev0_A
| 0 | 0 | 128850066 | 1479 | 0 | 96 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.LcHwDebugEnSetRev1_A
| 0 | 0 | 128850066 | 1479 | 0 | 96 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.LcHwDebugEnSet_A
| 0 | 0 | 128850066 | 1479 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.RvTapOff0_A
| 0 | 0 | 128850066 | 251 | 0 | 192 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.RvTapOff1_A
| 0 | 0 | 128850066 | 30906616 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.TapStrapKnown_A
| 0 | 0 | 128850066 | 128150096 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.dft_strap0_idxRange_A
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.dft_strap1_idxRange_A
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.tap_strap0_idxRange_A
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.tap_strap1_idxRange_A
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.tck_idxRange_A
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.tdi_idxRange_A
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.tdo_idxRange_A
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.tms_idxRange_A
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.trst_idxRange_A
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_por_scanmode_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_por_scanmode_sync.OutputsKnown_A
| 0 | 0 | 128850066 | 128150096 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_por_scanmode_sync.gen_no_flops.OutputDelay_A
| 0 | 0 | 128850066 | 128150096 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.FunctionCheck_A
| 0 | 0 | 128850066 | 128150096 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.OutputsKnown_A
| 0 | 0 | 128850066 | 128150096 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_a.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_a.OutputsKnown_A
| 0 | 0 | 128850066 | 128150096 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_a.gen_no_flops.OutputDelay_A
| 0 | 0 | 128850066 | 128150096 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_b.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_b.OutputsKnown_A
| 0 | 0 | 128850066 | 128150096 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_b.gen_no_flops.OutputDelay_A
| 0 | 0 | 128850066 | 128150096 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_check_byp_en.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_check_byp_en.OutputsKnown_A
| 0 | 0 | 128850066 | 128150096 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_check_byp_en.gen_flops.OutputDelay_A
| 0 | 0 | 128850066 | 128143056 | 0 | 3030 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en.OutputsKnown_A
| 0 | 0 | 128850066 | 128150096 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en.gen_flops.OutputDelay_A
| 0 | 0 | 128850066 | 128143056 | 0 | 3030 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_escalate_en.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_escalate_en.OutputsKnown_A
| 0 | 0 | 128850066 | 128150096 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_escalate_en.gen_flops.OutputDelay_A
| 0 | 0 | 128850066 | 128143056 | 0 | 3030 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_hw_debug_en.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_hw_debug_en.OutputsKnown_A
| 0 | 0 | 128850066 | 128150096 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_hw_debug_en.gen_flops.OutputDelay_A
| 0 | 0 | 128850066 | 128143056 | 0 | 3030 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_pinmux_hw_debug_en.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_pinmux_hw_debug_en.OutputsKnown_A
| 0 | 0 | 128850066 | 128150096 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_pinmux_hw_debug_en.gen_no_flops.OutputDelay_A
| 0 | 0 | 128850066 | 128150096 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_rst_por_aon_n_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 1023 | 896 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_rst_por_aon_n_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 1770 | 759 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.en2addrHit
| 0 | 0 | 149665596 | 499038 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.reAfterRv
| 0 | 0 | 149665596 | 499038 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.rePulse
| 0 | 0 | 149665596 | 338675 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_chk.PayLoadWidthCheck
| 0 | 0 | 2930 | 2930 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_reg_if.AllowedLatency_A
| 0 | 0 | 2930 | 2930 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_reg_if.MatchedWidthAssert
| 0 | 0 | 2930 | 2930 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_reg_if.u_err.dataWidthOnly32_A
| 0 | 0 | 2930 | 2930 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A
| 0 | 0 | 2930 | 2930 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck
| 0 | 0 | 2930 | 2930 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_rsp_intg_gen.DataWidthCheck_A
| 0 | 0 | 2930 | 2930 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_rsp_intg_gen.PayLoadWidthCheck
| 0 | 0 | 2930 | 2930 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.BusySrcReqChk_A
| 0 | 0 | 149665596 | 164724 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.DstReqKnown_A
| 0 | 0 | 1714815 | 1490053 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.SrcAckBusyChk_A
| 0 | 0 | 149665596 | 348 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.SrcBusyKnown_A
| 0 | 0 | 149665596 | 148839673 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A
| 0 | 0 | 1714815 | 33 | 0 | 983 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.u_arb.gen_wr_req.HwIdSelCheck_A
| 0 | 0 | 1714815 | 33 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq
| 0 | 0 | 149665596 | 381 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq
| 0 | 0 | 1714815 | 169 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 1714815 | 348 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 149665596 | 351 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc.BusySrcReqChk_A
| 0 | 0 | 149665596 | 134631 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc.DstReqKnown_A
| 0 | 0 | 1714815 | 1490053 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc.SrcAckBusyChk_A
| 0 | 0 | 149665596 | 337 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc.SrcBusyKnown_A
| 0 | 0 | 149665596 | 148839673 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 149665596 | 337 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 1714815 | 337 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 1714815 | 337 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 149665596 | 337 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc.BusySrcReqChk_A
| 0 | 0 | 149665596 | 125826 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc.DstReqKnown_A
| 0 | 0 | 1714815 | 1490053 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc.SrcAckBusyChk_A
| 0 | 0 | 149665596 | 315 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc.SrcBusyKnown_A
| 0 | 0 | 149665596 | 148839673 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 149665596 | 315 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 1714815 | 315 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 1714815 | 315 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 149665596 | 315 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc.BusySrcReqChk_A
| 0 | 0 | 149665596 | 128315 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc.DstReqKnown_A
| 0 | 0 | 1714815 | 1490053 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc.SrcAckBusyChk_A
| 0 | 0 | 149665596 | 323 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc.SrcBusyKnown_A
| 0 | 0 | 149665596 | 148839673 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 149665596 | 323 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 1714815 | 323 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 1714815 | 323 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 149665596 | 323 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc.BusySrcReqChk_A
| 0 | 0 | 149665596 | 132852 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc.DstReqKnown_A
| 0 | 0 | 1714815 | 1490053 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc.SrcAckBusyChk_A
| 0 | 0 | 149665596 | 330 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc.SrcBusyKnown_A
| 0 | 0 | 149665596 | 148839673 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 149665596 | 330 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 1714815 | 330 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 1714815 | 330 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 149665596 | 331 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc.BusySrcReqChk_A
| 0 | 0 | 149665596 | 118037 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc.DstReqKnown_A
| 0 | 0 | 1714815 | 1490053 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc.SrcAckBusyChk_A
| 0 | 0 | 149665596 | 297 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc.SrcBusyKnown_A
| 0 | 0 | 149665596 | 148839673 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 149665596 | 297 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 1714815 | 297 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 1714815 | 297 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 149665596 | 297 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc.BusySrcReqChk_A
| 0 | 0 | 149665596 | 130969 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc.DstReqKnown_A
| 0 | 0 | 1714815 | 1490053 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc.SrcAckBusyChk_A
| 0 | 0 | 149665596 | 330 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc.SrcBusyKnown_A
| 0 | 0 | 149665596 | 148839673 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 149665596 | 330 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 1714815 | 330 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 1714815 | 330 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 149665596 | 331 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc.BusySrcReqChk_A
| 0 | 0 | 149665596 | 116464 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc.DstReqKnown_A
| 0 | 0 | 1714815 | 1490053 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc.SrcAckBusyChk_A
| 0 | 0 | 149665596 | 293 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc.SrcBusyKnown_A
| 0 | 0 | 149665596 | 148839673 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 149665596 | 293 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 1714815 | 293 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 1714815 | 293 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 149665596 | 293 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc.BusySrcReqChk_A
| 0 | 0 | 149665596 | 112149 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc.DstReqKnown_A
| 0 | 0 | 1714815 | 1490053 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc.SrcAckBusyChk_A
| 0 | 0 | 149665596 | 281 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc.SrcBusyKnown_A
| 0 | 0 | 149665596 | 148839673 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 149665596 | 281 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 1714815 | 281 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 1714815 | 281 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 149665596 | 281 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc.BusySrcReqChk_A
| 0 | 0 | 149665596 | 123222 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc.DstReqKnown_A
| 0 | 0 | 1714815 | 1490053 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc.SrcAckBusyChk_A
| 0 | 0 | 149665596 | 309 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc.SrcBusyKnown_A
| 0 | 0 | 149665596 | 148839673 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 149665596 | 309 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 1714815 | 309 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 1714815 | 309 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 149665596 | 309 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc.BusySrcReqChk_A
| 0 | 0 | 149665596 | 129762 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc.DstReqKnown_A
| 0 | 0 | 1714815 | 1490053 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc.SrcAckBusyChk_A
| 0 | 0 | 149665596 | 326 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc.SrcBusyKnown_A
| 0 | 0 | 149665596 | 148839673 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 149665596 | 326 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 1714815 | 326 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 1714815 | 326 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 149665596 | 326 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc.BusySrcReqChk_A
| 0 | 0 | 149665596 | 122032 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc.DstReqKnown_A
| 0 | 0 | 1714815 | 1490053 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc.SrcAckBusyChk_A
| 0 | 0 | 149665596 | 303 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc.SrcBusyKnown_A
| 0 | 0 | 149665596 | 148839673 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 149665596 | 303 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 1714815 | 303 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 1714815 | 303 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 149665596 | 303 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.BusySrcReqChk_A
| 0 | 0 | 149665596 | 110430 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.DstReqKnown_A
| 0 | 0 | 1714815 | 1490053 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.SrcAckBusyChk_A
| 0 | 0 | 149665596 | 279 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.SrcBusyKnown_A
| 0 | 0 | 149665596 | 148839673 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 149665596 | 279 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 1714815 | 279 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 1714815 | 279 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 149665596 | 279 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.BusySrcReqChk_A
| 0 | 0 | 149665596 | 125572 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.DstReqKnown_A
| 0 | 0 | 1714815 | 1490053 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.SrcAckBusyChk_A
| 0 | 0 | 149665596 | 315 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.SrcBusyKnown_A
| 0 | 0 | 149665596 | 148839673 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 149665596 | 315 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 1714815 | 315 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 1714815 | 315 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 149665596 | 315 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.BusySrcReqChk_A
| 0 | 0 | 149665596 | 118830 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.DstReqKnown_A
| 0 | 0 | 1714815 | 1490053 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.SrcAckBusyChk_A
| 0 | 0 | 149665596 | 298 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.SrcBusyKnown_A
| 0 | 0 | 149665596 | 148839673 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 149665596 | 298 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 1714815 | 298 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 1714815 | 298 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 149665596 | 298 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.BusySrcReqChk_A
| 0 | 0 | 149665596 | 126276 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.DstReqKnown_A
| 0 | 0 | 1714815 | 1490053 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.SrcAckBusyChk_A
| 0 | 0 | 149665596 | 315 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.SrcBusyKnown_A
| 0 | 0 | 149665596 | 148839673 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 149665596 | 315 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 1714815 | 315 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 1714815 | 315 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 149665596 | 315 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.BusySrcReqChk_A
| 0 | 0 | 149665596 | 120759 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.DstReqKnown_A
| 0 | 0 | 1714815 | 1490053 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.SrcAckBusyChk_A
| 0 | 0 | 149665596 | 305 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.SrcBusyKnown_A
| 0 | 0 | 149665596 | 148839673 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 149665596 | 305 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 1714815 | 305 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 1714815 | 305 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 149665596 | 305 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc.BusySrcReqChk_A
| 0 | 0 | 149665596 | 133367 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc.DstReqKnown_A
| 0 | 0 | 1714815 | 1490053 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc.SrcAckBusyChk_A
| 0 | 0 | 149665596 | 333 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc.SrcBusyKnown_A
| 0 | 0 | 149665596 | 148839673 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 149665596 | 333 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 1714815 | 333 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 1714815 | 332 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 149665596 | 335 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc.BusySrcReqChk_A
| 0 | 0 | 149665596 | 112791 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc.DstReqKnown_A
| 0 | 0 | 1714815 | 1490053 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc.SrcAckBusyChk_A
| 0 | 0 | 149665596 | 285 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc.SrcBusyKnown_A
| 0 | 0 | 149665596 | 148839673 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 149665596 | 285 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 1714815 | 285 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 1714815 | 285 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 149665596 | 285 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc.BusySrcReqChk_A
| 0 | 0 | 149665596 | 126705 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc.DstReqKnown_A
| 0 | 0 | 1714815 | 1490053 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc.SrcAckBusyChk_A
| 0 | 0 | 149665596 | 316 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc.SrcBusyKnown_A
| 0 | 0 | 149665596 | 148839673 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 149665596 | 316 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 1714815 | 316 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 1714815 | 316 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 149665596 | 316 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc.BusySrcReqChk_A
| 0 | 0 | 149665596 | 124807 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc.DstReqKnown_A
| 0 | 0 | 1714815 | 1490053 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc.SrcAckBusyChk_A
| 0 | 0 | 149665596 | 312 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc.SrcBusyKnown_A
| 0 | 0 | 149665596 | 148839673 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 149665596 | 312 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 1714815 | 312 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 1714815 | 312 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 149665596 | 312 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc.BusySrcReqChk_A
| 0 | 0 | 149665596 | 129317 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc.DstReqKnown_A
| 0 | 0 | 1714815 | 1490053 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc.SrcAckBusyChk_A
| 0 | 0 | 149665596 | 324 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc.SrcBusyKnown_A
| 0 | 0 | 149665596 | 148839673 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 149665596 | 324 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 1714815 | 324 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 1714815 | 324 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 149665596 | 325 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc.BusySrcReqChk_A
| 0 | 0 | 149665596 | 123863 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc.DstReqKnown_A
| 0 | 0 | 1714815 | 1490053 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc.SrcAckBusyChk_A
| 0 | 0 | 149665596 | 312 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc.SrcBusyKnown_A
| 0 | 0 | 149665596 | 148839673 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 149665596 | 312 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 1714815 | 312 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 1714815 | 312 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 149665596 | 312 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc.BusySrcReqChk_A
| 0 | 0 | 149665596 | 115196 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc.DstReqKnown_A
| 0 | 0 | 1714815 | 1490053 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc.SrcAckBusyChk_A
| 0 | 0 | 149665596 | 290 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc.SrcBusyKnown_A
| 0 | 0 | 149665596 | 148839673 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 149665596 | 290 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 1714815 | 290 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 1714815 | 289 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 149665596 | 290 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc.BusySrcReqChk_A
| 0 | 0 | 149665596 | 135291 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc.DstReqKnown_A
| 0 | 0 | 1714815 | 1490053 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc.SrcAckBusyChk_A
| 0 | 0 | 149665596 | 335 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc.SrcBusyKnown_A
| 0 | 0 | 149665596 | 148839673 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 149665596 | 335 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 1714815 | 335 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 1714815 | 335 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 149665596 | 337 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.wePulse
| 0 | 0 | 149665596 | 160363 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_usbdev_aon_wake.WakeDetectActiveAonKnown_A
| 0 | 0 | 1494058 | 1299108 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmIbexFetchEnable0_A
| 0 | 0 | 508511374 | 12 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmIbexFetchEnable1_A
| 0 | 0 | 508511374 | 24705251 | 0 | 92 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmIbexFetchEnable2_A
| 0 | 0 | 508511374 | 65893065 | 0 | 82 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmIbexFetchEnable3Rev_A
| 0 | 0 | 508511374 | 437960575 | 0 | 2020 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmIbexFetchEnable3_A
| 0 | 0 | 508511374 | 437962418 | 0 | 1916 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmIbexInstrIntgErrCheck_A
| 0 | 0 | 508511374 | 231 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmIbexLoadRespIntgErrCheck_A
| 0 | 0 | 508511374 | 588 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmIbexRfEccErrCheck_A
| 0 | 0 | 508511374 | 1 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmRegWeOnehotCheck_A
| 0 | 0 | 508511374 | 8 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo.DataKnown_A
| 0 | 0 | 508511374 | 44998325 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo.DepthKnown_A
| 0 | 0 | 508511374 | 508404287 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo.RvalidKnown_A
| 0 | 0 | 508511374 | 508404287 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo.WreadyKnown_A
| 0 | 0 | 508511374 | 508404287 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo.DataKnown_A
| 0 | 0 | 508511374 | 37453089 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo.DepthKnown_A
| 0 | 0 | 508511374 | 508404287 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo.RvalidKnown_A
| 0 | 0 | 508511374 | 508404287 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo.WreadyKnown_A
| 0 | 0 | 508511374 | 508404287 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo.DataKnown_A
| 0 | 0 | 508511374 | 61722147 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo.DepthKnown_A
| 0 | 0 | 508511374 | 508404287 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo.RvalidKnown_A
| 0 | 0 | 508511374 | 508404287 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo.WreadyKnown_A
| 0 | 0 | 508511374 | 508404287 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo.gen_passthru_fifo.paramCheckPass
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo.DataKnown_A
| 0 | 0 | 508511374 | 46863145 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo.DepthKnown_A
| 0 | 0 | 508511374 | 508404287 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo.RvalidKnown_A
| 0 | 0 | 508511374 | 508404287 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo.WreadyKnown_A
| 0 | 0 | 508511374 | 508404287 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo.gen_passthru_fifo.paramCheckPass
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.g_instr_intg_err_assert_signals.AssertConnected_A
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.g_lsu_load_resp_intg_err_assert_signals.AssertConnected_A
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.g_lsu_store_resp_intg_err_assert_signals.AssertConnected_A
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.g_pc_mismatch_alert_o_assert_signals.AssertConnected_A
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.g_rf_ecc_err_comb_assert_signals.AssertConnected_A
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.gen_icache_scramble_asserts.IbexIcacheScrambleKeyForwardedToCore_A
| 0 | 0 | 508511374 | 205 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.gen_icache_scramble_asserts.IbexIcacheScrambleKeyRequestAfterFenceI_A
| 0 | 0 | 508511374 | 200 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex.DontExceeedMaxReqs
| 0 | 0 | 508511374 | 44948330 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex.u_cmd_intg_gen.PayMaxWidthCheck_A
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex.u_rsp_chk.PayLoadWidthCheck
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_i_ibex.DontExceeedMaxReqs
| 0 | 0 | 508511374 | 61722147 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_i_ibex.u_cmd_intg_gen.PayMaxWidthCheck_A
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_i_ibex.u_rsp_chk.PayLoadWidthCheck
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.CheckHotOne_A
| 0 | 0 | 508511374 | 500808109 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.CheckNGreaterZero_A
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.GntImpliesReady_A
| 0 | 0 | 508511374 | 3190 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.GntImpliesValid_A
| 0 | 0 | 508511374 | 3190 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.GrantKnown_A
| 0 | 0 | 508511374 | 500808109 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.IdxKnown_A
| 0 | 0 | 508511374 | 500808109 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.IndexIsCorrect_A
| 0 | 0 | 508511374 | 3190 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.Priority_A
| 0 | 0 | 508511374 | 3190 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.ReadyAndValidImplyGrant_A
| 0 | 0 | 508511374 | 3190 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.ReqAndReadyImplyGrant_A
| 0 | 0 | 508511374 | 3190 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.ReqImpliesValid_A
| 0 | 0 | 508511374 | 3190 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.ValidKnown_A
| 0 | 0 | 508511374 | 500808109 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.gen_data_port_assertion.DataFlow_A
| 0 | 0 | 508511374 | 3190 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.DataOutputDiffFromPrev_A
| 0 | 0 | 507859813 | 122233596 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.DataOutputValid_A
| 0 | 0 | 508511374 | 4467 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data.gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA
| 0 | 0 | 508511374 | 4467 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data.gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB
| 0 | 0 | 508511374 | 4467 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data.u_prim_sync_reqack.SyncReqAckAckNeedsReq
| 0 | 0 | 508511374 | 4467 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data.u_prim_sync_reqack.SyncReqAckHoldReq
| 0 | 0 | 508511374 | 4467 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.CheckHotOne_A
| 0 | 0 | 508511374 | 500808109 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.CheckNGreaterZero_A
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.GntImpliesReady_A
| 0 | 0 | 508511374 | 5192 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.GntImpliesValid_A
| 0 | 0 | 508511374 | 5192 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.GrantKnown_A
| 0 | 0 | 508511374 | 500808109 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.IdxKnown_A
| 0 | 0 | 508511374 | 500808109 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.IndexIsCorrect_A
| 0 | 0 | 508511374 | 5192 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.Priority_A
| 0 | 0 | 508511374 | 5192 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.ReadyAndValidImplyGrant_A
| 0 | 0 | 508511374 | 5192 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.ReqAndReadyImplyGrant_A
| 0 | 0 | 508511374 | 5192 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.ReqImpliesValid_A
| 0 | 0 | 508511374 | 5192 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.ValidKnown_A
| 0 | 0 | 508511374 | 500808109 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.gen_data_port_assertion.DataFlow_A
| 0 | 0 | 508511374 | 5192 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_lc_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_lc_sync.OutputsKnown_A
| 0 | 0 | 508511374 | 508404287 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_lc_sync.gen_flops.OutputDelay_A
| 0 | 0 | 508511374 | 508396689 | 0 | 3030 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data.gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA
| 0 | 0 | 508511374 | 50 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data.gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB
| 0 | 0 | 508511374 | 50 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data.u_prim_sync_reqack.SyncReqAckAckNeedsReq
| 0 | 0 | 127399211 | 50 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data.u_prim_sync_reqack.SyncReqAckHoldReq
| 0 | 0 | 508511374 | 50 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_pwrmgr_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_pwrmgr_sync.OutputsKnown_A
| 0 | 0 | 508511374 | 508404287 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_pwrmgr_sync.gen_flops.OutputDelay_A
| 0 | 0 | 508511374 | 508396689 | 0 | 3030 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.en2addrHit
| 0 | 0 | 590329365 | 33698 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.reAfterRv
| 0 | 0 | 590329365 | 33698 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.rePulse
| 0 | 0 | 590329365 | 25659 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_chk.PayLoadWidthCheck
| 0 | 0 | 2930 | 2930 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_reg_if.AllowedLatency_A
| 0 | 0 | 2930 | 2930 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_reg_if.MatchedWidthAssert
| 0 | 0 | 2930 | 2930 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_reg_if.u_err.dataWidthOnly32_A
| 0 | 0 | 2930 | 2930 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A
| 0 | 0 | 2930 | 2930 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck
| 0 | 0 | 2930 | 2930 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_rsp_intg_gen.DataWidthCheck_A
| 0 | 0 | 2930 | 2930 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_rsp_intg_gen.PayLoadWidthCheck
| 0 | 0 | 2930 | 2930 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.NotOverflowed_A
| 0 | 0 | 590329365 | 590206011 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo.DataKnown_A
| 0 | 0 | 590329365 | 89799 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo.DepthKnown_A
| 0 | 0 | 590329365 | 590206011 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo.RvalidKnown_A
| 0 | 0 | 590329365 | 590206011 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo.WreadyKnown_A
| 0 | 0 | 590329365 | 590206011 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo.gen_passthru_fifo.paramCheckPass
| 0 | 0 | 2930 | 2930 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo.DataKnown_A
| 0 | 0 | 590329365 | 92380 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo.DepthKnown_A
| 0 | 0 | 590329365 | 590206011 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo.RvalidKnown_A
| 0 | 0 | 590329365 | 590206011 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo.WreadyKnown_A
| 0 | 0 | 590329365 | 590206011 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo.gen_passthru_fifo.paramCheckPass
| 0 | 0 | 2930 | 2930 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo.DataKnown_A
| 0 | 0 | 590329365 | 52673 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo.DepthKnown_A
| 0 | 0 | 590329365 | 590206011 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo.RvalidKnown_A
| 0 | 0 | 590329365 | 590206011 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo.WreadyKnown_A
| 0 | 0 | 590329365 | 590206011 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass
| 0 | 0 | 2930 | 2930 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo.DataKnown_A
| 0 | 0 | 590329365 | 52672 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo.DepthKnown_A
| 0 | 0 | 590329365 | 590206011 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo.RvalidKnown_A
| 0 | 0 | 590329365 | 590206011 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo.WreadyKnown_A
| 0 | 0 | 590329365 | 590206011 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass
| 0 | 0 | 2930 | 2930 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo.DataKnown_A
| 0 | 0 | 590329365 | 37126 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo.DepthKnown_A
| 0 | 0 | 590329365 | 590206011 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo.RvalidKnown_A
| 0 | 0 | 590329365 | 590206011 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo.WreadyKnown_A
| 0 | 0 | 590329365 | 590206011 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass
| 0 | 0 | 2930 | 2930 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo.DataKnown_A
| 0 | 0 | 590329365 | 39708 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo.DepthKnown_A
| 0 | 0 | 590329365 | 590206011 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo.RvalidKnown_A
| 0 | 0 | 590329365 | 590206011 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo.WreadyKnown_A
| 0 | 0 | 590329365 | 590206011 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass
| 0 | 0 | 2930 | 2930 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.maxN
| 0 | 0 | 2930 | 2930 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.wePulse
| 0 | 0 | 590329365 | 8039 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_sim_win_rsp.u_intg_gen.DataWidthCheck_A
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_sim_win_rsp.u_intg_gen.PayLoadWidthCheck
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.FpvSecCmRegWeOnehotCheck_A
| 0 | 0 | 508511374 | 4 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.Irq0Tied_A
| 0 | 0 | 508511374 | 508404287 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.IrqKnownO_A
| 0 | 0 | 508511374 | 508404287 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.MsipKnownO_A
| 0 | 0 | 508511374 | 508404287 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.TlAReadyKnownO_A
| 0 | 0 | 508511374 | 508404287 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.TlDValidKnownO_A
| 0 | 0 | 508511374 | 508404287 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.gen_irq_id_known[0].IrqIdKnownO_A
| 0 | 0 | 508511374 | 508404287 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.gen_target[0].u_target.u_prim_max_tree.MaxComputationInvalid_A
| 0 | 0 | 508511374 | 506423937 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.gen_target[0].u_target.u_prim_max_tree.MaxComputation_A
| 0 | 0 | 508511374 | 1980350 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.gen_target[0].u_target.u_prim_max_tree.MaxIndexComputationInvalid_A
| 0 | 0 | 508511374 | 506423937 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.gen_target[0].u_target.u_prim_max_tree.MaxIndexComputation_A
| 0 | 0 | 508511374 | 1980350 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.gen_target[0].u_target.u_prim_max_tree.NumSources_A
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.gen_target[0].u_target.u_prim_max_tree.ValidInImpliesValidOut_A
| 0 | 0 | 508511374 | 508404287 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.onehot0Claim
| 0 | 0 | 508511374 | 508404287 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.onehot0Complete
| 0 | 0 | 508511374 | 508404287 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.u_reg.en2addrHit
| 0 | 0 | 590329365 | 198468 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.u_reg.reAfterRv
| 0 | 0 | 590329365 | 198468 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.u_reg.rePulse
| 0 | 0 | 590329365 | 127135 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_chk.PayLoadWidthCheck
| 0 | 0 | 2930 | 2930 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_reg_if.AllowedLatency_A
| 0 | 0 | 2930 | 2930 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_reg_if.MatchedWidthAssert
| 0 | 0 | 2930 | 2930 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_reg_if.u_err.dataWidthOnly32_A
| 0 | 0 | 2930 | 2930 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A
| 0 | 0 | 2930 | 2930 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck
| 0 | 0 | 2930 | 2930 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_rsp_intg_gen.DataWidthCheck_A
| 0 | 0 | 2930 | 2930 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_rsp_intg_gen.PayLoadWidthCheck
| 0 | 0 | 2930 | 2930 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.u_reg.wePulse
| 0 | 0 | 590329365 | 71333 | 0 | 0 |
|
tb.dut.top_earlgrey.u_sensor_ctrl_aon.FpvSecCmRegWeOnehotCheck_A
| 0 | 0 | 127399211 | 3 | 0 | 0 |
|
tb.dut.top_earlgrey.u_sensor_ctrl_aon.NumAlertsMatch_A
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_init_intr.IntrTKind_A
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_io_intr.IntrTKind_A
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.en2addrHit
| 0 | 0 | 127399211 | 5576 | 0 | 0 |
|
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.reAfterRv
| 0 | 0 | 127399211 | 5576 | 0 | 0 |
|
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.rePulse
| 0 | 0 | 127399211 | 4004 | 0 | 0 |
|
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_chk.PayLoadWidthCheck
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_reg_if.AllowedLatency_A
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_reg_if.MatchedWidthAssert
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_reg_if.u_err.dataWidthOnly32_A
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_rsp_intg_gen.DataWidthCheck_A
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_rsp_intg_gen.PayLoadWidthCheck
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.wePulse
| 0 | 0 | 127399211 | 1572 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[10].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[11].gen_mux_spi_host_d2.u_mux_dio_oe.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 76 | 64 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[11].gen_mux_spi_host_d2.u_mux_dio_oe.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 139 | 122 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[11].gen_mux_spi_host_d2.u_mux_dio_out.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 4936 | 4916 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[11].gen_mux_spi_host_d2.u_mux_dio_out.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2982 | 2961 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[11].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[12].gen_mux_spi_host_d3.u_mux_dio_oe.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 61 | 49 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[12].gen_mux_spi_host_d3.u_mux_dio_oe.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 136 | 119 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[12].gen_mux_spi_host_d3.u_mux_dio_out.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 4889 | 4870 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[12].gen_mux_spi_host_d3.u_mux_dio_out.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 170 | 152 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[12].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[13].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[14].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[15].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[16].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[17].gen_mux_spi_dev_d2.u_mux_dio_oe.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 79 | 58 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[17].gen_mux_spi_dev_d2.u_mux_dio_oe.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 159 | 144 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[17].gen_mux_spi_dev_d2.u_mux_dio_out.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 5252 | 5229 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[17].gen_mux_spi_dev_d2.u_mux_dio_out.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 519 | 505 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[17].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[18].gen_mux_spi_dev_d3.u_mux_dio_oe.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 81 | 61 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[18].gen_mux_spi_dev_d3.u_mux_dio_oe.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 143 | 128 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[18].gen_mux_spi_dev_d3.u_mux_dio_out.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 5210 | 5188 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[18].gen_mux_spi_dev_d3.u_mux_dio_out.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 412 | 400 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[18].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[19].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[1].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[20].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[21].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[22].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[2].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[5].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[8].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[9].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[0].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 215 | 185 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 4698 | 4670 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in_raw.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 227 | 197 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in_raw.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 4694 | 4666 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[10].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 578 | 558 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 21413 | 21382 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in_raw.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 579 | 559 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in_raw.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 21405 | 21374 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[11].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 592 | 547 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 21364 | 21333 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in_raw.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 586 | 541 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in_raw.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 21364 | 21333 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[12].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[13].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[14].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[15].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[16].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[17].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[18].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[19].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[1].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[20].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[21].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[22].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[23].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[24].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[25].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[26].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[27].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[28].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[29].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[2].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[30].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[31].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[32].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[33].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[34].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[35].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[36].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[37].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[38].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[39].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[3].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[40].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[41].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[42].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[43].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[44].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[45].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[46].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[4].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[5].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[6].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[7].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[8].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 3003 | 2981 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 4754 | 4724 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in_raw.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 3001 | 2979 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in_raw.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 4748 | 4718 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[9].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 1021 | 1021 | 0 | 0 |
|