Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.i2c2_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	142792	1			T94	2		T95	7		T96	37
values[2]	12085	1			T96	1		T443	3		T452	1
values[3]	4625	1			T552	1		T553	1		T822	1
values[4]	2645	1			T612	43		T782	1		T499	5
values[5]	1872	1			T612	24		T782	3		T784	3
values[6]	1406	1			T612	1		T782	3		T614	18
values[7]	1022	1			T782	3		T614	3		T796	1
values[8]	710	1			T782	3		T796	1		T638	14
values[9]	589	1			T782	5		T796	1		T638	5
values[10]	528	1			T782	6		T796	1		T638	10
values[11]	398	1			T782	3		T796	1		T638	6
values[12]	447	1			T782	2		T796	1		T638	4
values[13]	449	1			T782	11		T796	1		T638	7
values[14]	412	1			T782	4		T796	1		T638	6
values[15]	395	1			T782	2		T796	1		T638	3
values[16]	374	1			T782	3		T796	1		T638	6
values[17]	362	1			T782	1		T796	1		T638	3
values[18]	376	1			T782	3		T796	1		T638	19
values[19]	335	1			T782	3		T796	1		T638	7
values[20]	379	1			T782	9		T796	1		T638	4
values[21]	370	1			T782	2		T796	1		T638	6
values[22]	349	1			T782	1		T796	1		T638	4
values[23]	364	1			T782	3		T796	1		T638	2
values[24]	407	1			T782	12		T796	1		T638	11
values[25]	350	1			T782	3		T796	1		T638	4
values[26]	336	1			T782	2		T796	1		T638	13
values[27]	360	1			T782	1		T796	1		T638	8
values[28]	307	1			T782	3		T796	1		T638	5
values[29]	289	1			T782	2		T796	1		T638	18
values[30]	397	1			T782	8		T796	1		T638	11
values[31]	325	1			T782	1		T796	1		T638	7
values[32]	328	1			T782	4		T796	1		T638	6
values[33]	329	1			T782	3		T796	1		T638	5
values[34]	299	1			T782	1		T796	1		T638	6
values[35]	321	1			T782	1		T796	1		T638	14
values[36]	354	1			T782	3		T796	1		T638	4
values[37]	365	1			T782	2		T796	1		T638	5
values[38]	342	1			T782	2		T796	1		T638	12
values[39]	307	1			T782	2		T796	1		T638	7
values[40]	290	1			T782	2		T796	1		T638	24
values[41]	286	1			T782	7		T796	1		T638	5
values[42]	295	1			T782	2		T796	1		T638	12
values[43]	300	1			T782	2		T796	1		T638	5
values[44]	322	1			T782	1		T796	1		T638	4
values[45]	333	1			T782	1		T796	1		T638	3
values[46]	317	1			T782	3		T796	1		T638	3
values[47]	300	1			T782	11		T796	1		T638	4
values[48]	281	1			T782	3		T796	1		T638	4
values[49]	263	1			T782	3		T796	1		T638	3
values[50]	299	1			T782	2		T796	1		T638	8
values[51]	291	1			T782	2		T796	1		T638	10
values[52]	241	1			T782	6		T796	1		T638	8
values[53]	247	1			T782	5		T796	1		T638	10
values[54]	267	1			T782	3		T796	1		T638	3
values[55]	245	1			T782	1		T796	1		T638	15
values[56]	279	1			T782	1		T796	1		T638	14
values[57]	253	1			T782	1		T796	1		T638	6
values[58]	206	1			T782	3		T796	1		T638	10
values[59]	201	1			T782	2		T796	1		T638	5
values[60]	188	1			T782	2		T796	1		T638	4
values[61]	197	1			T782	2		T796	1		T638	7
values[62]	210	1			T782	2		T796	1		T638	8
values[63]	155	1			T782	3		T796	1		T638	6
values[64]	150	1			T782	2		T796	1		T638	5
values[65]	155	1			T782	1		T796	1		T638	14
values[66]	174	1			T782	2		T796	1		T638	3
values[67]	171	1			T782	2		T796	1		T638	5
values[68]	133	1			T782	1		T796	1		T638	12
values[69]	147	1			T782	3		T796	1		T638	7
values[70]	135	1			T782	4		T796	1		T638	12
values[71]	124	1			T782	3		T796	1		T638	4
values[72]	98	1			T782	3		T796	1		T638	5
values[73]	84	1			T782	2		T796	1		T638	8
values[74]	93	1			T782	2		T796	1		T638	8
values[75]	64	1			T782	3		T796	1		T638	3
values[76]	99	1			T782	3		T796	1		T638	5
values[77]	91	1			T782	2		T796	1		T638	4
values[78]	64	1			T782	2		T796	1		T638	1
values[79]	56	1			T782	2		T796	1		T802	1
values[80]	59	1			T782	7		T796	1		T802	1
values[81]	50	1			T782	8		T796	1		T802	1
values[82]	63	1			T782	4		T796	1		T802	1
values[83]	64	1			T782	3		T796	1		T802	1
values[84]	68	1			T782	5		T796	1		T802	1
values[85]	57	1			T796	1		T802	1		T823	1
values[86]	61	1			T796	3		T802	1		T823	1
values[87]	52	1			T796	9		T802	1		T823	1
values[88]	76	1			T796	2		T802	3		T823	1
values[89]	73	1			T796	1		T802	3		T823	1
values[90]	47	1			T796	2		T802	2		T823	1
values[91]	54	1			T796	2		T802	2		T823	8
values[92]	50	1			T796	4		T802	1		T823	1
values[93]	51	1			T796	1		T802	2		T823	2
values[94]	68	1			T796	3		T802	1		T823	3
values[95]	67	1			T796	1		T802	4		T823	1
values[96]	44	1			T796	2		T802	1		T823	3
values[97]	73	1			T796	6		T802	7		T823	5
values[98]	54	1			T796	1		T802	4		T823	2
values[99]	55	1			T796	1		T802	2		T823	2
values[100]	50	1			T796	2		T802	4		T823	1
values[101]	54	1			T796	2		T802	1		T823	1
values[102]	63	1			T796	2		T802	4		T823	3
values[103]	47	1			T796	1		T802	2		T823	3
values[104]	48	1			T796	1		T802	1		T823	2
values[105]	48	1			T796	4		T802	2		T823	3
values[106]	51	1			T796	8		T802	1		T823	3
values[107]	56	1			T796	5		T802	3		T823	2
values[108]	37	1			T796	4		T802	1		T823	1
values[109]	53	1			T796	6		T802	3		T823	1
values[110]	70	1			T796	2		T802	4		T823	1
values[111]	49	1			T796	4		T802	1		T823	1
values[112]	35	1			T796	4		T802	1		T823	1
values[113]	41	1			T796	3		T802	2		T823	2
values[114]	40	1			T796	6		T802	4		T823	3
values[115]	34	1			T796	1		T802	5		T823	2
values[116]	25	1			T796	1		T802	2		T823	6
values[117]	34	1			T796	2		T802	3		T823	1
values[118]	18	1			T796	1		T802	1		T823	1
values[119]	34	1			T796	1		T802	2		T823	2
values[120]	32	1			T796	1		T802	2		T823	2
values[121]	32	1			T796	1		T802	2		T823	2
values[122]	29	1			T796	1		T802	2		T823	1
values[123]	35	1			T796	2		T802	1		T823	3
values[124]	39	1			T796	2		T802	1		T823	3
values[125]	34	1			T796	1		T802	2		T823	3
values[126]	58	1			T796	1		T802	2		T823	8
values[127]	444	1			T796	24		T802	38		T823	35
values[128]	3699	1			T796	287		T802	344		T823	241