Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.i2c2_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	137422	1			T98	11		T99	4		T100	53
values[2]	8708	1			T100	3		T161	1		T458	1
values[3]	3054	1			T459	9		T655	8		T541	93
values[4]	1850	1			T459	7		T655	3		T541	48
values[5]	1244	1			T459	7		T655	2		T541	38
values[6]	889	1			T459	10		T541	15		T530	7
values[7]	651	1			T459	9		T541	17		T530	2
values[8]	502	1			T459	8		T541	17		T530	2
values[9]	498	1			T459	7		T541	14		T530	2
values[10]	457	1			T459	4		T541	14		T530	1
values[11]	363	1			T459	13		T541	11		T530	4
values[12]	422	1			T459	6		T541	19		T530	1
values[13]	386	1			T459	2		T541	4		T530	1
values[14]	364	1			T459	5		T541	7		T530	2
values[15]	316	1			T459	5		T541	11		T530	1
values[16]	349	1			T459	10		T541	7		T530	1
values[17]	314	1			T459	3		T541	2		T530	2
values[18]	313	1			T459	8		T530	2		T836	5
values[19]	307	1			T459	6		T530	1		T836	3
values[20]	340	1			T459	10		T530	1		T836	12
values[21]	395	1			T459	12		T530	5		T836	10
values[22]	314	1			T459	16		T530	6		T836	5
values[23]	359	1			T459	14		T530	5		T836	4
values[24]	289	1			T459	15		T530	2		T836	3
values[25]	307	1			T459	5		T530	5		T836	16
values[26]	309	1			T459	11		T530	4		T836	5
values[27]	323	1			T459	10		T530	3		T836	5
values[28]	344	1			T459	3		T530	2		T836	5
values[29]	316	1			T459	5		T530	4		T836	8
values[30]	354	1			T459	6		T530	2		T836	4
values[31]	305	1			T459	3		T530	2		T836	5
values[32]	325	1			T459	4		T530	3		T836	10
values[33]	281	1			T459	3		T530	4		T836	15
values[34]	318	1			T459	4		T530	3		T836	8
values[35]	309	1			T459	10		T530	4		T836	3
values[36]	282	1			T459	6		T530	2		T836	4
values[37]	244	1			T459	3		T530	2		T836	6
values[38]	291	1			T459	10		T530	3		T836	7
values[39]	256	1			T459	8		T530	1		T836	3
values[40]	348	1			T459	6		T530	3		T836	2
values[41]	307	1			T459	15		T530	4		T836	23
values[42]	286	1			T459	17		T530	3		T836	3
values[43]	302	1			T459	9		T530	2		T836	7
values[44]	266	1			T459	5		T530	1		T836	6
values[45]	302	1			T459	5		T530	3		T836	10
values[46]	239	1			T459	5		T530	1		T836	3
values[47]	252	1			T459	2		T530	3		T836	3
values[48]	288	1			T459	4		T530	8		T836	7
values[49]	232	1			T459	4		T530	1		T836	3
values[50]	290	1			T459	3		T530	2		T836	17
values[51]	254	1			T459	2		T530	4		T836	8
values[52]	266	1			T459	5		T530	2		T836	4
values[53]	288	1			T459	4		T530	3		T836	4
values[54]	240	1			T459	16		T530	3		T836	5
values[55]	252	1			T459	8		T530	2		T836	18
values[56]	237	1			T459	10		T530	2		T836	5
values[57]	285	1			T459	3		T530	1		T836	7
values[58]	253	1			T459	21		T530	1		T836	6
values[59]	247	1			T459	6		T530	8		T836	8
values[60]	249	1			T459	6		T530	6		T836	7
values[61]	219	1			T530	4		T836	6		T669	9
values[62]	241	1			T530	3		T836	7		T669	8
values[63]	224	1			T530	3		T836	3		T669	10
values[64]	213	1			T530	1		T836	4		T669	20
values[65]	179	1			T530	2		T836	9		T669	4
values[66]	205	1			T530	2		T669	6		T661	18
values[67]	194	1			T530	6		T669	5		T661	9
values[68]	176	1			T530	10		T669	3		T808	1
values[69]	120	1			T530	9		T669	1		T808	1
values[70]	136	1			T530	12		T808	1		T508	1
values[71]	116	1			T530	12		T808	1		T508	1
values[72]	131	1			T530	4		T808	1		T508	1
values[73]	96	1			T530	5		T808	1		T508	1
values[74]	112	1			T530	11		T808	1		T508	1
values[75]	71	1			T530	4		T808	1		T508	1
values[76]	78	1			T530	10		T808	1		T508	1
values[77]	83	1			T530	10		T808	1		T508	1
values[78]	91	1			T530	9		T808	1		T508	1
values[79]	73	1			T530	4		T808	1		T508	1
values[80]	63	1			T530	3		T808	1		T508	1
values[81]	63	1			T530	3		T808	1		T508	1
values[82]	91	1			T530	9		T808	1		T508	1
values[83]	68	1			T530	7		T808	1		T508	1
values[84]	59	1			T530	8		T808	1		T508	1
values[85]	64	1			T530	12		T808	1		T508	1
values[86]	57	1			T530	10		T808	1		T508	1
values[87]	78	1			T530	13		T808	1		T508	1
values[88]	72	1			T530	13		T808	1		T508	1
values[89]	62	1			T530	12		T808	1		T508	1
values[90]	62	1			T530	11		T808	1		T508	1
values[91]	65	1			T530	9		T808	1		T508	1
values[92]	72	1			T530	4		T808	1		T508	1
values[93]	60	1			T530	5		T808	1		T508	1
values[94]	63	1			T530	2		T808	1		T508	1
values[95]	73	1			T530	5		T808	1		T508	1
values[96]	47	1			T530	3		T808	1		T508	1
values[97]	58	1			T530	4		T808	1		T508	1
values[98]	54	1			T530	2		T808	1		T508	1
values[99]	74	1			T530	6		T808	1		T508	1
values[100]	52	1			T530	1		T808	1		T508	1
values[101]	72	1			T530	3		T808	1		T508	1
values[102]	72	1			T530	2		T808	1		T508	1
values[103]	80	1			T530	14		T808	1		T508	1
values[104]	66	1			T530	5		T808	1		T508	1
values[105]	66	1			T530	3		T808	1		T508	1
values[106]	73	1			T530	6		T808	1		T508	1
values[107]	66	1			T530	5		T808	2		T508	1
values[108]	78	1			T530	13		T808	4		T508	1
values[109]	68	1			T530	11		T808	5		T508	1
values[110]	59	1			T530	9		T808	2		T508	1
values[111]	53	1			T530	3		T808	4		T508	1
values[112]	54	1			T530	2		T808	2		T508	1
values[113]	44	1			T530	4		T808	1		T508	1
values[114]	50	1			T530	2		T808	1		T508	1
values[115]	60	1			T530	4		T808	3		T508	1
values[116]	55	1			T530	3		T808	2		T508	1
values[117]	45	1			T530	2		T808	1		T508	1
values[118]	50	1			T530	6		T808	3		T508	3
values[119]	57	1			T530	6		T808	2		T508	1
values[120]	69	1			T530	4		T808	3		T508	2
values[121]	50	1			T530	4		T808	3		T508	2
values[122]	70	1			T530	5		T808	4		T508	1
values[123]	55	1			T530	2		T808	1		T508	3
values[124]	68	1			T530	2		T808	1		T508	1
values[125]	59	1			T808	2		T508	2		T832	2
values[126]	74	1			T808	4		T508	3		T832	5
values[127]	755	1			T808	29		T508	36		T832	53
values[128]	7395	1			T808	328		T508	339		T832	657