Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__regs_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	151166	1			T94	8		T95	4		T96	35
values[2]	4645	1			T443	2		T546	1		T548	2
values[3]	2560	1			T550	1		T446	3		T543	1
values[4]	2126	1			T446	13		T543	3		T783	10
values[5]	1808	1			T446	27		T543	1		T783	11
values[6]	1622	1			T446	28		T543	4		T783	35
values[7]	1381	1			T446	24		T543	5		T783	21
values[8]	1175	1			T446	21		T543	7		T783	46
values[9]	962	1			T446	9		T543	2		T783	71
values[10]	771	1			T446	4		T543	2		T783	46
values[11]	685	1			T446	1		T543	3		T783	32
values[12]	672	1			T543	4		T783	22		T455	10
values[13]	657	1			T543	4		T783	36		T455	12
values[14]	628	1			T543	4		T783	46		T455	1
values[15]	639	1			T543	3		T783	53		T455	3
values[16]	590	1			T543	1		T783	49		T455	4
values[17]	535	1			T543	5		T783	17		T455	7
values[18]	522	1			T543	2		T783	14		T455	12
values[19]	456	1			T543	1		T783	4		T455	26
values[20]	428	1			T543	2		T455	28		T784	6
values[21]	386	1			T543	5		T455	14		T784	4
values[22]	346	1			T543	8		T455	3		T784	2
values[23]	342	1			T543	7		T455	2		T784	8
values[24]	327	1			T543	6		T455	8		T784	3
values[25]	282	1			T543	3		T455	13		T784	7
values[26]	273	1			T543	3		T455	31		T784	9
values[27]	302	1			T543	4		T455	36		T784	10
values[28]	257	1			T543	5		T455	38		T784	6
values[29]	223	1			T543	3		T455	15		T784	13
values[30]	275	1			T543	6		T455	17		T784	18
values[31]	307	1			T543	8		T455	12		T784	32
values[32]	266	1			T543	4		T455	21		T784	28
values[33]	264	1			T543	4		T455	12		T784	48
values[34]	269	1			T543	2		T455	1		T784	64
values[35]	176	1			T543	4		T784	30		T796	1
values[36]	168	1			T543	2		T784	42		T796	1
values[37]	167	1			T543	3		T784	20		T796	1
values[38]	155	1			T543	2		T784	13		T796	1
values[39]	130	1			T543	2		T784	1		T796	1
values[40]	128	1			T543	6		T796	1		T789	8
values[41]	96	1			T543	3		T796	1		T840	1
values[42]	96	1			T543	3		T796	1		T840	1
values[43]	84	1			T543	3		T796	1		T840	1
values[44]	81	1			T543	3		T796	1		T840	1
values[45]	79	1			T543	1		T796	1		T840	1
values[46]	84	1			T543	2		T796	1		T840	1
values[47]	89	1			T543	3		T796	1		T840	1
values[48]	103	1			T543	3		T796	1		T840	1
values[49]	83	1			T543	1		T796	1		T840	1
values[50]	107	1			T543	2		T796	1		T840	1
values[51]	112	1			T543	2		T796	1		T840	1
values[52]	98	1			T543	3		T796	1		T840	1
values[53]	70	1			T543	2		T796	1		T840	1
values[54]	84	1			T543	5		T796	1		T840	1
values[55]	88	1			T543	9		T796	1		T840	1
values[56]	84	1			T543	3		T796	1		T840	1
values[57]	93	1			T543	1		T796	1		T840	1
values[58]	81	1			T543	1		T796	1		T840	1
values[59]	91	1			T543	6		T796	1		T840	1
values[60]	97	1			T543	4		T796	1		T840	1
values[61]	103	1			T543	5		T796	1		T840	1
values[62]	96	1			T543	6		T796	1		T840	1
values[63]	94	1			T543	3		T796	1		T840	2
values[64]	74	1			T543	3		T796	1		T840	1
values[65]	71	1			T543	1		T796	1		T840	1
values[66]	92	1			T543	1		T796	1		T840	1
values[67]	73	1			T543	2		T796	1		T840	1
values[68]	74	1			T543	2		T796	1		T840	1
values[69]	81	1			T543	3		T796	1		T840	1
values[70]	80	1			T543	1		T796	1		T840	1
values[71]	83	1			T543	2		T796	1		T840	1
values[72]	79	1			T543	2		T796	1		T840	1
values[73]	71	1			T543	2		T796	1		T840	1
values[74]	94	1			T543	2		T796	1		T840	1
values[75]	89	1			T543	2		T796	1		T840	1
values[76]	113	1			T543	1		T796	1		T840	1
values[77]	84	1			T543	3		T796	1		T840	1
values[78]	90	1			T543	4		T796	1		T840	1
values[79]	78	1			T543	3		T796	1		T840	1
values[80]	78	1			T543	3		T796	1		T840	1
values[81]	90	1			T543	2		T796	1		T840	1
values[82]	83	1			T543	4		T796	1		T840	1
values[83]	94	1			T543	4		T796	1		T840	1
values[84]	99	1			T543	8		T796	1		T840	1
values[85]	81	1			T543	7		T796	1		T840	1
values[86]	73	1			T543	2		T796	1		T840	1
values[87]	89	1			T543	3		T796	1		T840	1
values[88]	104	1			T543	3		T796	1		T840	1
values[89]	111	1			T543	4		T796	1		T840	1
values[90]	98	1			T543	6		T796	1		T840	1
values[91]	81	1			T543	5		T796	1		T840	1
values[92]	89	1			T543	5		T796	1		T840	1
values[93]	87	1			T543	6		T796	2		T840	1
values[94]	93	1			T543	4		T796	5		T840	1
values[95]	87	1			T543	1		T796	5		T840	1
values[96]	95	1			T543	1		T796	2		T840	1
values[97]	96	1			T543	4		T796	3		T840	1
values[98]	98	1			T543	3		T796	1		T840	1
values[99]	108	1			T543	6		T796	1		T840	1
values[100]	96	1			T543	7		T796	1		T840	1
values[101]	102	1			T543	4		T796	1		T840	1
values[102]	103	1			T543	6		T796	3		T840	1
values[103]	109	1			T543	4		T796	1		T840	1
values[104]	127	1			T543	7		T796	3		T840	1
values[105]	112	1			T543	4		T796	1		T840	1
values[106]	114	1			T543	1		T796	1		T840	1
values[107]	125	1			T543	6		T796	2		T840	1
values[108]	139	1			T543	6		T796	1		T840	1
values[109]	113	1			T543	1		T796	2		T840	1
values[110]	142	1			T543	4		T796	4		T840	1
values[111]	139	1			T543	6		T796	6		T840	1
values[112]	135	1			T543	6		T796	2		T840	1
values[113]	171	1			T543	7		T796	3		T840	1
values[114]	149	1			T543	14		T796	1		T840	1
values[115]	144	1			T543	11		T796	1		T840	1
values[116]	122	1			T543	3		T796	2		T840	2
values[117]	116	1			T796	1		T840	3		T786	2
values[118]	129	1			T796	9		T840	1		T786	4
values[119]	133	1			T796	6		T840	2		T786	2
values[120]	127	1			T796	3		T840	2		T786	2
values[121]	144	1			T796	3		T840	1		T786	2
values[122]	155	1			T796	3		T840	1		T786	7
values[123]	173	1			T796	1		T840	1		T786	14
values[124]	331	1			T796	1		T840	3		T786	23
values[125]	594	1			T796	1		T840	2		T786	48
values[126]	968	1			T796	14		T840	16		T786	82
values[127]	2201	1			T796	112		T840	144		T786	48
values[128]	3331	1			T796	160		T840	217		T786	2