Unified Coverage Report :: Group Instance : rv_core_ibex__cfg

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T280	1		T451	1		T550	1
small_delay	668	1			T278	1		T443	1		T545	1
zero	632	1			T94	1		T95	1		T96	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T280	1		T444	1		T551	1
small_delay	968	1			T278	1		T443	1		T545	1
zero	632	1			T94	1		T95	1		T96	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T280	1		T451	1		T550	1
small_delay	668	1			T278	1		T443	1		T545	1
zero	632	1			T94	1		T95	1		T96	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T280	1		T444	1		T551	1
small_delay	968	1			T278	1		T443	1		T545	1
zero	632	1			T94	1		T95	1		T96	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T280	1		T451	1		T550	1
small_delay	668	1			T278	1		T443	1		T545	1
zero	632	1			T94	1		T95	1		T96	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T280	1		T444	1		T551	1
small_delay	968	1			T278	1		T443	1		T545	1
zero	632	1			T94	1		T95	1		T96	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T280	1		T451	1		T550	1
small_delay	668	1			T278	1		T443	1		T545	1
zero	632	1			T94	1		T95	1		T96	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T280	1		T444	1		T551	1
small_delay	968	1			T278	1		T443	1		T545	1
zero	632	1			T94	1		T95	1		T96	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T280	1		T451	1		T550	1
small_delay	668	1			T278	1		T443	1		T545	1
zero	632	1			T94	1		T95	1		T96	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T280	1		T444	1		T551	1
small_delay	968	1			T278	1		T443	1		T545	1
zero	632	1			T94	1		T95	1		T96	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T280	1		T451	1		T550	1
small_delay	668	1			T278	1		T443	1		T545	1
zero	632	1			T94	1		T95	1		T96	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T280	1		T444	1		T551	1
small_delay	968	1			T278	1		T443	1		T545	1
zero	632	1			T94	1		T95	1		T96	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T280	1		T451	1		T550	1
small_delay	668	1			T278	1		T443	1		T545	1
zero	632	1			T94	1		T95	1		T96	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T280	1		T444	1		T551	1
small_delay	968	1			T278	1		T443	1		T545	1
zero	632	1			T94	1		T95	1		T96	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T280	1		T451	1		T550	1
small_delay	668	1			T278	1		T443	1		T545	1
zero	632	1			T94	1		T95	1		T96	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T280	1		T444	1		T551	1
small_delay	968	1			T278	1		T443	1		T545	1
zero	632	1			T94	1		T95	1		T96	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T280	1		T451	1		T550	1
small_delay	668	1			T278	1		T443	1		T545	1
zero	632	1			T94	1		T95	1		T96	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T280	1		T444	1		T551	1
small_delay	968	1			T278	1		T443	1		T545	1
zero	632	1			T94	1		T95	1		T96	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T280	1		T451	1		T550	1
small_delay	668	1			T278	1		T443	1		T545	1
zero	632	1			T94	1		T95	1		T96	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T280	1		T444	1		T551	1
small_delay	968	1			T278	1		T443	1		T545	1
zero	632	1			T94	1		T95	1		T96	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T280	1		T451	1		T550	1
small_delay	668	1			T278	1		T443	1		T545	1
zero	632	1			T94	1		T95	1		T96	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T280	1		T444	1		T551	1
small_delay	968	1			T278	1		T443	1		T545	1
zero	632	1			T94	1		T95	1		T96	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T280	1		T451	1		T550	1
small_delay	668	1			T278	1		T443	1		T545	1
zero	632	1			T94	1		T95	1		T96	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T280	1		T444	1		T551	1
small_delay	968	1			T278	1		T443	1		T545	1
zero	632	1			T94	1		T95	1		T96	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T280	1		T451	1		T550	1
small_delay	668	1			T278	1		T443	1		T545	1
zero	632	1			T94	1		T95	1		T96	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T280	1		T444	1		T551	1
small_delay	968	1			T278	1		T443	1		T545	1
zero	632	1			T94	1		T95	1		T96	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T280	1		T451	1		T550	1
small_delay	668	1			T278	1		T443	1		T545	1
zero	632	1			T94	1		T95	1		T96	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T280	1		T444	1		T551	1
small_delay	968	1			T278	1		T443	1		T545	1
zero	632	1			T94	1		T95	1		T96	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T280	1		T451	1		T550	1
small_delay	668	1			T278	1		T443	1		T545	1
zero	632	1			T94	1		T95	1		T96	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T280	1		T444	1		T551	1
small_delay	968	1			T278	1		T443	1		T545	1
zero	632	1			T94	1		T95	1		T96	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T280	1		T451	1		T550	1
small_delay	668	1			T278	1		T443	1		T545	1
zero	632	1			T94	1		T95	1		T96	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T280	1		T444	1		T551	1
small_delay	968	1			T278	1		T443	1		T545	1
zero	632	1			T94	1		T95	1		T96	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T280	1		T451	1		T550	1
small_delay	668	1			T278	1		T443	1		T545	1
zero	632	1			T94	1		T95	1		T96	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T280	1		T444	1		T551	1
small_delay	968	1			T278	1		T443	1		T545	1
zero	632	1			T94	1		T95	1		T96	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T280	1		T451	1		T550	1
small_delay	668	1			T278	1		T443	1		T545	1
zero	632	1			T94	1		T95	1		T96	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T280	1		T444	1		T551	1
small_delay	968	1			T278	1		T443	1		T545	1
zero	632	1			T94	1		T95	1		T96	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T280	1		T451	1		T550	1
small_delay	668	1			T278	1		T443	1		T545	1
zero	632	1			T94	1		T95	1		T96	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T280	1		T444	1		T551	1
small_delay	968	1			T278	1		T443	1		T545	1
zero	632	1			T94	1		T95	1		T96	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T280	1		T451	1		T550	1
small_delay	668	1			T278	1		T443	1		T545	1
zero	632	1			T94	1		T95	1		T96	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T280	1		T444	1		T551	1
small_delay	968	1			T278	1		T443	1		T545	1
zero	632	1			T94	1		T95	1		T96	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T280	1		T451	1		T550	1
small_delay	668	1			T278	1		T443	1		T545	1
zero	632	1			T94	1		T95	1		T96	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T280	1		T444	1		T551	1
small_delay	968	1			T278	1		T443	1		T545	1
zero	632	1			T94	1		T95	1		T96	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T280	1		T451	1		T550	1
small_delay	668	1			T278	1		T443	1		T545	1
zero	632	1			T94	1		T95	1		T96	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T280	1		T444	1		T551	1
small_delay	968	1			T278	1		T443	1		T545	1
zero	632	1			T94	1		T95	1		T96	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T280	1		T451	1		T550	1
small_delay	668	1			T278	1		T443	1		T545	1
zero	632	1			T94	1		T95	1		T96	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T280	1		T444	1		T551	1
small_delay	968	1			T278	1		T443	1		T545	1
zero	632	1			T94	1		T95	1		T96	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T280	1		T451	1		T550	1
small_delay	668	1			T278	1		T443	1		T545	1
zero	632	1			T94	1		T95	1		T96	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T280	1		T444	1		T551	1
small_delay	968	1			T278	1		T443	1		T545	1
zero	632	1			T94	1		T95	1		T96	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T280	1		T451	1		T550	1
small_delay	668	1			T278	1		T443	1		T545	1
zero	632	1			T94	1		T95	1		T96	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T280	1		T444	1		T551	1
small_delay	968	1			T278	1		T443	1		T545	1
zero	632	1			T94	1		T95	1		T96	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T280	1		T451	1		T550	1
small_delay	668	1			T278	1		T443	1		T545	1
zero	632	1			T94	1		T95	1		T96	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T280	1		T444	1		T551	1
small_delay	968	1			T278	1		T443	1		T545	1
zero	632	1			T94	1		T95	1		T96	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T280	1		T451	1		T550	1
small_delay	668	1			T278	1		T443	1		T545	1
zero	632	1			T94	1		T95	1		T96	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T280	1		T444	1		T551	1
small_delay	968	1			T278	1		T443	1		T545	1
zero	632	1			T94	1		T95	1		T96	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T280	1		T451	1		T550	1
small_delay	668	1			T278	1		T443	1		T545	1
zero	632	1			T94	1		T95	1		T96	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T280	1		T444	1		T551	1
small_delay	968	1			T278	1		T443	1		T545	1
zero	632	1			T94	1		T95	1		T96	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T280	1		T451	1		T550	1
small_delay	668	1			T278	1		T443	1		T545	1
zero	632	1			T94	1		T95	1		T96	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T280	1		T444	1		T551	1
small_delay	968	1			T278	1		T443	1		T545	1
zero	632	1			T94	1		T95	1		T96	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T280	1		T451	1		T550	1
small_delay	668	1			T278	1		T443	1		T545	1
zero	632	1			T94	1		T95	1		T96	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T280	1		T444	1		T551	1
small_delay	968	1			T278	1		T443	1		T545	1
zero	632	1			T94	1		T95	1		T96	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T280	1		T451	1		T550	1
small_delay	668	1			T278	1		T443	1		T545	1
zero	632	1			T94	1		T95	1		T96	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T280	1		T444	1		T551	1
small_delay	968	1			T278	1		T443	1		T545	1
zero	632	1			T94	1		T95	1		T96	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T280	1		T451	1		T550	1
small_delay	668	1			T278	1		T443	1		T545	1
zero	632	1			T94	1		T95	1		T96	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T280	1		T444	1		T551	1
small_delay	968	1			T278	1		T443	1		T545	1
zero	632	1			T94	1		T95	1		T96	1