Summary for Variable cp_req_dly
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for cp_req_dly
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| big_delay |
200 |
1 |
|
|
T236 |
1 |
|
T565 |
1 |
|
T668 |
1 |
| small_delay |
930 |
1 |
|
|
T99 |
1 |
|
T100 |
1 |
|
T161 |
1 |
| zero |
670 |
1 |
|
|
T98 |
1 |
|
T185 |
1 |
|
T457 |
1 |
Summary for Variable cp_rsp_dly
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for cp_rsp_dly
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| big_delay |
500 |
1 |
|
|
T161 |
1 |
|
T236 |
1 |
|
T565 |
1 |
| small_delay |
630 |
1 |
|
|
T99 |
1 |
|
T100 |
1 |
|
T462 |
1 |
| zero |
670 |
1 |
|
|
T98 |
1 |
|
T185 |
1 |
|
T457 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |