Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

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Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	462	1			T279	1		T446	1		T543	1
all_values[1]	439	1			T543	1		T600	1		T475	4
all_values[2]	468	1			T279	1		T600	1		T475	3
all_values[3]	451	1			T567	1		T600	3		T612	1
all_values[4]	413	1			T841	1		T475	5		T783	1
all_values[5]	432	1			T446	1		T841	1		T600	1
all_values[6]	485	1			T279	2		T450	2		T600	1
all_values[7]	477	1			T450	1		T543	1		T567	1
all_values[8]	450	1			T450	1		T446	1		T543	1
all_values[9]	466	1			T446	1		T600	2		T612	1
all_values[10]	441	1			T543	1		T600	2		T475	6
all_values[11]	449	1			T600	3		T782	1		T475	4
all_values[12]	446	1			T475	3		T783	1		T455	1
all_values[13]	485	1			T543	1		T567	1		T600	2
all_values[14]	447	1			T543	2		T475	1		T641	1
all_values[15]	445	1			T543	1		T567	1		T475	5
all_values[16]	454	1			T450	1		T600	1		T475	4
all_values[17]	455	1			T279	1		T446	1		T600	2
all_values[18]	438	1			T446	1		T600	2		T782	1
all_values[19]	459	1			T279	2		T543	1		T600	1
all_values[20]	495	1			T543	1		T600	1		T475	3
all_values[21]	466	1			T450	1		T600	1		T475	1
all_values[22]	422	1			T446	1		T543	1		T600	2
all_values[23]	465	1			T475	6		T584	1		T455	4
all_values[24]	474	1			T450	1		T600	1		T475	5
all_values[25]	430	1			T279	1		T450	1		T600	2
all_values[26]	434	1			T279	1		T475	2		T584	2
all_values[27]	469	1			T446	1		T612	1		T475	3
all_values[28]	483	1			T567	1		T475	2		T584	2
all_values[29]	483	1			T600	1		T612	1		T782	1
all_values[30]	424	1			T475	3		T783	1		T617	3
all_values[31]	482	1			T543	1		T567	1		T782	1
all_values[32]	466	1			T450	1		T543	1		T812	1
all_values[33]	469	1			T600	1		T475	3		T455	1
all_values[34]	446	1			T446	1		T600	2		T475	4
all_values[35]	457	1			T600	3		T475	3		T584	2
all_values[36]	434	1			T279	1		T450	1		T600	2
all_values[37]	425	1			T279	1		T450	2		T446	1
all_values[38]	452	1			T600	1		T475	1		T783	1
all_values[39]	475	1			T446	1		T475	4		T584	2
all_values[40]	479	1			T475	5		T783	3		T455	2
all_values[41]	468	1			T600	2		T612	1		T475	2
all_values[42]	453	1			T841	1		T600	2		T475	6
all_values[43]	441	1			T600	1		T475	2		T783	1
all_values[44]	484	1			T450	1		T612	1		T475	1
all_values[45]	439	1			T279	1		T450	1		T543	1
all_values[46]	471	1			T543	1		T600	1		T475	2
all_values[47]	425	1			T450	1		T446	1		T543	1
all_values[48]	448	1			T450	1		T600	2		T782	1
all_values[49]	433	1			T543	3		T475	2		T783	1