Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

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Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	436	1			T865	1		T485	3		T511	1
all_values[1]	470	1			T448	2		T562	1		T865	3
all_values[2]	456	1			T448	1		T841	1		T865	3
all_values[3]	479	1			T448	1		T459	1		T865	3
all_values[4]	423	1			T803	1		T485	3		T596	1
all_values[5]	443	1			T562	1		T865	3		T485	1
all_values[6]	472	1			T457	1		T448	1		T562	1
all_values[7]	432	1			T673	1		T865	2		T485	2
all_values[8]	446	1			T562	1		T803	1		T865	3
all_values[9]	445	1			T448	1		T562	1		T459	2
all_values[10]	456	1			T865	2		T485	2		T594	2
all_values[11]	466	1			T865	1		T485	3		T594	3
all_values[12]	448	1			T448	1		T562	1		T459	2
all_values[13]	431	1			T562	2		T459	1		T865	2
all_values[14]	446	1			T457	1		T653	2		T485	1
all_values[15]	462	1			T448	1		T803	1		T865	1
all_values[16]	461	1			T865	4		T653	1		T594	4
all_values[17]	463	1			T841	1		T459	2		T803	1
all_values[18]	443	1			T841	1		T865	5		T485	3
all_values[19]	458	1			T594	1		T596	2		T511	3
all_values[20]	461	1			T459	1		T865	1		T485	3
all_values[21]	471	1			T562	1		T803	1		T865	2
all_values[22]	458	1			T865	1		T653	1		T485	4
all_values[23]	425	1			T562	1		T459	1		T803	1
all_values[24]	476	1			T865	1		T485	2		T594	2
all_values[25]	462	1			T459	1		T865	1		T485	1
all_values[26]	492	1			T803	2		T865	2		T798	1
all_values[27]	474	1			T562	1		T803	1		T485	4
all_values[28]	460	1			T448	1		T562	3		T803	1
all_values[29]	480	1			T459	1		T865	2		T485	2
all_values[30]	480	1			T562	1		T485	6		T594	1
all_values[31]	446	1			T841	1		T562	1		T803	1
all_values[32]	467	1			T562	2		T865	2		T485	2
all_values[33]	446	1			T865	1		T485	4		T594	2
all_values[34]	482	1			T562	1		T803	1		T673	1
all_values[35]	457	1			T448	1		T562	2		T653	1
all_values[36]	452	1			T459	1		T865	2		T485	7
all_values[37]	438	1			T459	1		T803	1		T865	2
all_values[38]	421	1			T457	1		T562	1		T459	2
all_values[39]	448	1			T457	1		T865	1		T653	2
all_values[40]	457	1			T562	1		T459	1		T803	1
all_values[41]	443	1			T673	1		T865	1		T653	1
all_values[42]	444	1			T841	1		T459	1		T865	4
all_values[43]	453	1			T562	1		T803	1		T865	1
all_values[44]	470	1			T448	1		T841	1		T562	1
all_values[45]	403	1			T562	1		T485	3		T594	1
all_values[46]	402	1			T562	1		T803	1		T865	2
all_values[47]	396	1			T865	3		T653	1		T485	1
all_values[48]	502	1			T865	1		T653	1		T485	5
all_values[49]	430	1			T448	1		T865	2		T485	3