Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3461	1			T480	4		T401	1		T482	3
all_values[1]	3484	1			T396	1		T480	4		T401	4
all_values[2]	3475	1			T396	5		T480	1		T401	3
all_values[3]	3421	1			T396	5		T401	5		T482	2
all_values[4]	3591	1			T396	4		T480	4		T401	4
all_values[5]	3309	1			T396	2		T480	3		T401	3
all_values[6]	3410	1			T396	4		T480	1		T401	6
all_values[7]	3460	1			T396	2		T480	1		T401	2
all_values[8]	3452	1			T396	2		T480	4		T401	2
all_values[9]	3451	1			T396	1		T401	1		T482	5
all_values[10]	3376	1			T396	3		T480	2		T401	2
all_values[11]	3489	1			T396	1		T401	5		T482	3
all_values[12]	3561	1			T396	5		T480	1		T401	10
all_values[13]	3515	1			T396	2		T480	2		T401	3
all_values[14]	3465	1			T396	1		T480	1		T401	2
all_values[15]	3457	1			T396	4		T480	1		T482	3
all_values[16]	3456	1			T480	4		T401	5		T482	3
all_values[17]	3369	1			T396	3		T480	1		T401	3
all_values[18]	3447	1			T396	2		T480	2		T401	4
all_values[19]	3503	1			T396	3		T480	4		T401	2
all_values[20]	3412	1			T396	1		T480	1		T401	1
all_values[21]	3379	1			T396	8		T480	2		T401	4
all_values[22]	3476	1			T396	4		T480	1		T401	2
all_values[23]	3439	1			T396	3		T480	4		T401	3
all_values[24]	3378	1			T396	1		T480	3		T401	1
all_values[25]	3442	1			T396	3		T480	2		T401	4
all_values[26]	3593	1			T396	4		T480	2		T401	1
all_values[27]	3377	1			T396	2		T480	2		T401	5
all_values[28]	3468	1			T396	3		T480	1		T401	3
all_values[29]	3510	1			T396	4		T480	1		T401	2
all_values[30]	3504	1			T396	3		T480	4		T401	3
all_values[31]	3540	1			T396	4		T480	2		T401	1
all_values[32]	3393	1			T396	5		T480	3		T401	2
all_values[33]	3515	1			T396	2		T401	2		T482	3
all_values[34]	3424	1			T396	4		T480	1		T401	3
all_values[35]	3506	1			T396	3		T480	1		T401	1
all_values[36]	3542	1			T396	2		T480	7		T401	3
all_values[37]	3414	1			T396	7		T480	2		T401	2
all_values[38]	3452	1			T396	2		T480	1		T482	6
all_values[39]	3399	1			T396	4		T480	1		T401	2
all_values[40]	3551	1			T396	3		T480	2		T401	2
all_values[41]	3429	1			T396	2		T401	2		T482	4
all_values[42]	3497	1			T396	2		T480	2		T401	2
all_values[43]	3502	1			T396	5		T480	1		T401	5
all_values[44]	3416	1			T396	8		T480	1		T401	6
all_values[45]	3481	1			T396	4		T480	3		T401	2
all_values[46]	3367	1			T480	1		T401	1		T484	14
all_values[47]	3411	1			T396	2		T401	5		T482	5
all_values[48]	3426	1			T396	2		T480	4		T401	3
all_values[49]	3493	1			T396	8		T480	2		T401	3
all_values[50]	3445	1			T396	1		T480	1		T401	3
all_values[51]	3424	1			T396	3		T480	3		T401	2
all_values[52]	3490	1			T396	7		T480	4		T401	4
all_values[53]	3396	1			T396	4		T480	2		T401	7
all_values[54]	3415	1			T480	3		T401	3		T482	4
all_values[55]	3501	1			T480	1		T401	2		T482	2
all_values[56]	3425	1			T396	2		T480	3		T401	2
all_values[57]	3496	1			T396	3		T480	1		T401	2
all_values[58]	3456	1			T396	5		T480	2		T401	3
all_values[59]	3359	1			T396	2		T480	3		T401	1
all_values[60]	3405	1			T396	1		T480	3		T401	2
all_values[61]	3478	1			T396	2		T480	2		T401	5
all_values[62]	3500	1			T396	6		T480	1		T401	5
all_values[63]	3529	1			T396	5		T480	4		T401	2