Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

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Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3341	1			T445	6		T449	2		T446	2
all_values[1]	3153	1			T279	1		T445	3		T446	2
all_values[2]	3245	1			T445	5		T446	1		T600	5
all_values[3]	3192	1			T279	4		T445	2		T449	5
all_values[4]	3255	1			T279	2		T445	1		T449	2
all_values[5]	3195	1			T279	2		T445	3		T533	1
all_values[6]	3278	1			T279	1		T449	2		T446	3
all_values[7]	3177	1			T279	1		T445	3		T449	1
all_values[8]	3258	1			T279	3		T445	4		T449	1
all_values[9]	3246	1			T279	1		T449	1		T446	5
all_values[10]	3216	1			T279	1		T445	4		T449	7
all_values[11]	3361	1			T279	2		T445	5		T449	2
all_values[12]	3179	1			T445	2		T449	2		T446	2
all_values[13]	3298	1			T279	1		T445	4		T449	2
all_values[14]	3307	1			T279	2		T445	3		T449	1
all_values[15]	3326	1			T445	2		T449	3		T446	4
all_values[16]	3353	1			T279	1		T445	2		T567	1
all_values[17]	3319	1			T279	1		T445	1		T449	1
all_values[18]	3268	1			T445	2		T449	2		T446	2
all_values[19]	3181	1			T445	2		T449	1		T446	1
all_values[20]	3281	1			T279	2		T445	6		T449	4
all_values[21]	3330	1			T279	3		T445	5		T449	2
all_values[22]	3286	1			T279	2		T445	1		T449	2
all_values[23]	3263	1			T279	2		T445	5		T449	3
all_values[24]	3295	1			T279	4		T445	3		T449	2
all_values[25]	3402	1			T279	2		T445	1		T449	3
all_values[26]	3262	1			T279	3		T445	3		T449	4
all_values[27]	3339	1			T445	4		T449	4		T446	2
all_values[28]	3232	1			T445	2		T449	2		T446	2
all_values[29]	3178	1			T279	1		T445	5		T449	1
all_values[30]	3362	1			T279	2		T449	2		T446	1
all_values[31]	3255	1			T279	1		T445	1		T449	3
all_values[32]	3264	1			T445	1		T449	2		T446	2
all_values[33]	3299	1			T449	2		T567	2		T600	5
all_values[34]	3308	1			T279	1		T445	3		T446	1
all_values[35]	3150	1			T279	3		T445	2		T449	2
all_values[36]	3212	1			T279	2		T445	2		T449	2
all_values[37]	3260	1			T445	3		T449	1		T446	2
all_values[38]	3182	1			T279	1		T445	5		T446	2
all_values[39]	3271	1			T279	3		T445	6		T449	3
all_values[40]	3308	1			T445	5		T449	3		T446	3
all_values[41]	3225	1			T279	4		T445	4		T446	2
all_values[42]	3298	1			T279	3		T445	3		T449	3
all_values[43]	3286	1			T279	4		T445	6		T449	3
all_values[44]	3316	1			T279	2		T445	2		T446	3
all_values[45]	3269	1			T279	1		T445	2		T446	2
all_values[46]	3149	1			T445	5		T449	2		T446	2
all_values[47]	3247	1			T445	5		T449	1		T446	4
all_values[48]	3338	1			T279	1		T445	8		T449	4
all_values[49]	3226	1			T279	1		T445	2		T449	2
all_values[50]	3229	1			T445	3		T449	3		T446	2
all_values[51]	3214	1			T279	2		T445	1		T449	2
all_values[52]	3324	1			T279	1		T445	3		T449	5
all_values[53]	3312	1			T445	8		T449	1		T446	3
all_values[54]	3332	1			T279	1		T445	4		T449	3
all_values[55]	3273	1			T445	2		T449	1		T567	2
all_values[56]	3156	1			T445	5		T449	3		T446	1
all_values[57]	3339	1			T279	2		T445	4		T449	2
all_values[58]	3281	1			T445	1		T449	3		T446	1
all_values[59]	3319	1			T279	1		T445	2		T446	3
all_values[60]	3237	1			T449	2		T567	3		T600	7
all_values[61]	3144	1			T445	2		T446	1		T567	1
all_values[62]	3135	1			T279	1		T445	3		T449	1
all_values[63]	3307	1			T279	2		T445	2		T449	2