Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

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Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3513	1			T462	2		T282	3		T557	2
all_values[1]	3448	1			T462	2		T282	11		T448	1
all_values[2]	3473	1			T462	1		T448	1		T557	2
all_values[3]	3540	1			T462	2		T282	4		T448	2
all_values[4]	3464	1			T462	5		T282	4		T448	1
all_values[5]	3435	1			T462	2		T282	3		T557	3
all_values[6]	3499	1			T462	4		T282	6		T557	1
all_values[7]	3424	1			T282	3		T448	2		T557	4
all_values[8]	3404	1			T462	2		T282	3		T448	1
all_values[9]	3542	1			T282	1		T448	1		T562	2
all_values[10]	3463	1			T462	7		T282	5		T448	1
all_values[11]	3418	1			T282	5		T448	1		T557	1
all_values[12]	3562	1			T282	4		T448	2		T562	3
all_values[13]	3471	1			T282	6		T448	2		T557	5
all_values[14]	3441	1			T462	1		T282	3		T557	1
all_values[15]	3616	1			T282	6		T557	1		T538	3
all_values[16]	3373	1			T282	7		T448	1		T557	4
all_values[17]	3551	1			T462	1		T282	2		T557	2
all_values[18]	3451	1			T462	3		T282	4		T448	1
all_values[19]	3454	1			T462	2		T282	7		T557	2
all_values[20]	3417	1			T462	4		T282	8		T562	3
all_values[21]	3607	1			T462	1		T282	2		T448	2
all_values[22]	3588	1			T282	5		T448	2		T557	1
all_values[23]	3526	1			T282	3		T448	4		T557	1
all_values[24]	3539	1			T462	2		T282	2		T557	3
all_values[25]	3453	1			T462	1		T282	3		T448	2
all_values[26]	3497	1			T462	2		T282	3		T448	1
all_values[27]	3566	1			T462	1		T282	6		T448	2
all_values[28]	3532	1			T462	3		T282	3		T448	3
all_values[29]	3452	1			T462	1		T282	4		T448	1
all_values[30]	3596	1			T462	1		T282	5		T448	2
all_values[31]	3446	1			T462	3		T282	4		T562	2
all_values[32]	3429	1			T462	2		T282	7		T448	1
all_values[33]	3512	1			T462	1		T282	4		T448	3
all_values[34]	3512	1			T282	9		T448	2		T557	3
all_values[35]	3453	1			T462	1		T282	4		T448	1
all_values[36]	3531	1			T282	6		T557	4		T562	1
all_values[37]	3476	1			T462	3		T282	3		T448	3
all_values[38]	3463	1			T462	1		T282	5		T448	3
all_values[39]	3543	1			T462	2		T282	2		T448	2
all_values[40]	3432	1			T462	2		T282	3		T448	2
all_values[41]	3448	1			T462	2		T282	2		T557	3
all_values[42]	3518	1			T462	2		T282	4		T448	2
all_values[43]	3488	1			T462	2		T282	5		T448	1
all_values[44]	3549	1			T282	5		T448	4		T557	4
all_values[45]	3439	1			T462	3		T282	8		T448	2
all_values[46]	3508	1			T282	4		T448	2		T557	1
all_values[47]	3436	1			T282	2		T448	3		T557	3
all_values[48]	3451	1			T462	3		T282	4		T448	2
all_values[49]	3408	1			T282	4		T448	3		T557	3
all_values[50]	3562	1			T282	4		T448	1		T557	1
all_values[51]	3497	1			T462	1		T282	5		T448	2
all_values[52]	3573	1			T462	3		T282	3		T448	1
all_values[53]	3413	1			T462	5		T282	7		T557	3
all_values[54]	3412	1			T462	1		T282	2		T448	1
all_values[55]	3416	1			T462	2		T282	5		T448	1
all_values[56]	3528	1			T462	2		T282	2		T448	3
all_values[57]	3471	1			T282	4		T448	1		T557	1
all_values[58]	3454	1			T462	2		T282	5		T557	1
all_values[59]	3421	1			T462	2		T282	5		T448	1
all_values[60]	3505	1			T462	2		T282	3		T557	2
all_values[61]	3573	1			T462	2		T282	3		T448	2
all_values[62]	3507	1			T462	2		T282	6		T557	3
all_values[63]	3480	1			T462	3		T282	5		T448	1