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back
132
133 1/1 assign alert_test = {
Tests: T1 T2 T3
134 reg2hw.alert_test.q &
135 reg2hw.alert_test.qe
136 };
137
138 for (genvar i = 0; i < NumAlerts; i++) begin : gen_alert_tx
139 prim_alert_sender #(
140 .AsyncOn(AlertAsyncOn[i]),
141 .IsFatal(1'b1)
142 ) u_prim_alert_sender (
143 .clk_i,
144 .rst_ni,
145 .alert_test_i ( alert_test[i] ),
146 .alert_req_i ( alerts[0] ),
147 .alert_ack_o ( ),
148 .alert_state_o ( ),
149 .alert_rx_i ( alert_rx_i[i] ),
150 .alert_tx_o ( alert_tx_o[i] )
151 );
152 end
153
154 /////////////////////////////
155 // Pad attribute registers //
156 /////////////////////////////
157
158 prim_pad_wrapper_pkg::pad_attr_t [NDioPads-1:0] dio_pad_attr_q;
159 prim_pad_wrapper_pkg::pad_attr_t [NMioPads-1:0] mio_pad_attr_q;
160
161 always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs
162 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
163 1/1 dio_pad_attr_q <= '0;
Tests: T1 T2 T3
164 1/1 for (int kk = 0; kk < NMioPads; kk++) begin
Tests: T1 T2 T3
165 1/1 if (kk == TargetCfg.tap_strap0_idx) begin
Tests: T1 T2 T3
166 // TAP strap 0 is sampled after reset (and only once for life cycle states that are not
167 // TEST_UNLOCKED* or RMA). To ensure it gets sampled as 0 unless driven to 1 from an
168 // external source (and specifically that it gets sampled as 0 when left floating / not
169 // connected), this enables the pull-down of the pad at reset.
170 1/1 mio_pad_attr_q[kk] <= '{pull_en: 1'b1, default: '0};
Tests: T1 T2 T3
171 end else begin
172 1/1 mio_pad_attr_q[kk] <= '0;
Tests: T1 T2 T3
173 end
174 end
175 end else begin
176 // dedicated pads
177 1/1 for (int kk = 0; kk < NDioPads; kk++) begin
Tests: T1 T2 T3
178 1/1 if (reg2hw.dio_pad_attr[kk].drive_strength.qe) begin
Tests: T1 T2 T3
179 1/1 dio_pad_attr_q[kk].drive_strength <= reg2hw.dio_pad_attr[kk].drive_strength.q;
Tests: T1 T2 T3
180 end
MISSING_ELSE
181 1/1 if (reg2hw.dio_pad_attr[kk].slew_rate.qe) begin
Tests: T1 T2 T3
182 1/1 dio_pad_attr_q[kk].slew_rate <= reg2hw.dio_pad_attr[kk].slew_rate.q;
Tests: T1 T2 T3
183 end
MISSING_ELSE
184 1/1 if (reg2hw.dio_pad_attr[kk].input_disable.qe) begin
Tests: T1 T2 T3
185 1/1 dio_pad_attr_q[kk].input_disable <= reg2hw.dio_pad_attr[kk].input_disable.q;
Tests: T1 T2 T3
186 end
MISSING_ELSE
187 1/1 if (reg2hw.dio_pad_attr[kk].od_en.qe) begin
Tests: T1 T2 T3
188 1/1 dio_pad_attr_q[kk].od_en <= reg2hw.dio_pad_attr[kk].od_en.q;
Tests: T1 T2 T3
189 end
MISSING_ELSE
190 1/1 if (reg2hw.dio_pad_attr[kk].schmitt_en.qe) begin
Tests: T1 T2 T3
191 1/1 dio_pad_attr_q[kk].schmitt_en <= reg2hw.dio_pad_attr[kk].schmitt_en.q;
Tests: T1 T2 T3
192 end
MISSING_ELSE
193 1/1 if (reg2hw.dio_pad_attr[kk].keeper_en.qe) begin
Tests: T1 T2 T3
194 1/1 dio_pad_attr_q[kk].keep_en <= reg2hw.dio_pad_attr[kk].keeper_en.q;
Tests: T1 T2 T3
195 end
MISSING_ELSE
196 1/1 if (reg2hw.dio_pad_attr[kk].pull_select.qe) begin
Tests: T1 T2 T3
197 1/1 dio_pad_attr_q[kk].pull_select <= reg2hw.dio_pad_attr[kk].pull_select.q;
Tests: T1 T2 T3
198 end
MISSING_ELSE
199 1/1 if (reg2hw.dio_pad_attr[kk].pull_en.qe) begin
Tests: T1 T2 T3
200 1/1 dio_pad_attr_q[kk].pull_en <= reg2hw.dio_pad_attr[kk].pull_en.q;
Tests: T1 T2 T3
201 end
MISSING_ELSE
202 1/1 if (reg2hw.dio_pad_attr[kk].virtual_od_en.qe) begin
Tests: T1 T2 T3
203 1/1 dio_pad_attr_q[kk].virt_od_en <= reg2hw.dio_pad_attr[kk].virtual_od_en.q;
Tests: T1 T2 T3
204 end
MISSING_ELSE
205 1/1 if (reg2hw.dio_pad_attr[kk].invert.qe) begin
Tests: T1 T2 T3
206 1/1 dio_pad_attr_q[kk].invert <= reg2hw.dio_pad_attr[kk].invert.q;
Tests: T1 T2 T3
207 end
MISSING_ELSE
208 end
209 // muxed pads
210 1/1 for (int kk = 0; kk < NMioPads; kk++) begin
Tests: T1 T2 T3
211 1/1 if (reg2hw.mio_pad_attr[kk].drive_strength.qe) begin
Tests: T1 T2 T3
212 1/1 mio_pad_attr_q[kk].drive_strength <= reg2hw.mio_pad_attr[kk].drive_strength.q;
Tests: T1 T2 T3
213 end
MISSING_ELSE
214 1/1 if (reg2hw.mio_pad_attr[kk].slew_rate.qe) begin
Tests: T1 T2 T3
215 1/1 mio_pad_attr_q[kk].slew_rate <= reg2hw.mio_pad_attr[kk].slew_rate.q;
Tests: T1 T2 T3
216 end
MISSING_ELSE
217 1/1 if (reg2hw.mio_pad_attr[kk].input_disable.qe) begin
Tests: T1 T2 T3
218 1/1 mio_pad_attr_q[kk].input_disable <= reg2hw.mio_pad_attr[kk].input_disable.q;
Tests: T1 T2 T3
219 end
MISSING_ELSE
220 1/1 if (reg2hw.mio_pad_attr[kk].od_en.qe) begin
Tests: T1 T2 T3
221 1/1 mio_pad_attr_q[kk].od_en <= reg2hw.mio_pad_attr[kk].od_en.q;
Tests: T1 T2 T3
222 end
MISSING_ELSE
223 1/1 if (reg2hw.mio_pad_attr[kk].schmitt_en.qe) begin
Tests: T1 T2 T3
224 1/1 mio_pad_attr_q[kk].schmitt_en <= reg2hw.mio_pad_attr[kk].schmitt_en.q;
Tests: T1 T2 T3
225 end
MISSING_ELSE
226 1/1 if (reg2hw.mio_pad_attr[kk].keeper_en.qe) begin
Tests: T1 T2 T3
227 1/1 mio_pad_attr_q[kk].keep_en <= reg2hw.mio_pad_attr[kk].keeper_en.q;
Tests: T1 T2 T3
228 end
MISSING_ELSE
229 1/1 if (reg2hw.mio_pad_attr[kk].pull_select.qe) begin
Tests: T1 T2 T3
230 1/1 mio_pad_attr_q[kk].pull_select <= reg2hw.mio_pad_attr[kk].pull_select.q;
Tests: T1 T2 T3
231 end
MISSING_ELSE
232 1/1 if (reg2hw.mio_pad_attr[kk].pull_en.qe) begin
Tests: T1 T2 T3
233 1/1 mio_pad_attr_q[kk].pull_en <= reg2hw.mio_pad_attr[kk].pull_en.q;
Tests: T1 T2 T3
234 end
MISSING_ELSE
235 1/1 if (reg2hw.mio_pad_attr[kk].virtual_od_en.qe) begin
Tests: T1 T2 T3
236 1/1 mio_pad_attr_q[kk].virt_od_en <= reg2hw.mio_pad_attr[kk].virtual_od_en.q;
Tests: T1 T2 T3
237 end
MISSING_ELSE
238 1/1 if (reg2hw.mio_pad_attr[kk].invert.qe) begin
Tests: T1 T2 T3
239 1/1 mio_pad_attr_q[kk].invert <= reg2hw.mio_pad_attr[kk].invert.q;
Tests: T1 T2 T3
240 end
MISSING_ELSE
241 end
242 end
243 end
244
245 ////////////////////////
246 // Connect attributes //
247 ////////////////////////
248
249 pad_attr_t [NDioPads-1:0] dio_attr;
250 for (genvar k = 0; k < NDioPads; k++) begin : gen_dio_attr
251 pad_attr_t warl_mask;
252
253 prim_pad_attr #(
254 .PadType(TargetCfg.dio_pad_type[k])
255 ) u_prim_pad_attr (
256 .attr_warl_o(warl_mask)
257 );
258
259 16/16 assign dio_attr[k] = dio_pad_attr_q[k] & warl_mask;
Tests: T1 T2 T3 | T1 T2 T3 | T9 T10 T11 | T9 T10 T11 | T9 T10 T11 | T9 T10 T11 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T15 T51 T52 | T15 T51 T52 | T20 T21 T22 | T20 T21 T22 | T9 T47 T48 | T9 T47 T48
260 14/16 ==> assign hw2reg.dio_pad_attr[k].drive_strength.d = dio_attr[k].drive_strength;
Tests: T1 T2 T3 | T1 T2 T3 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T49 T50
261 0/16 ==> assign hw2reg.dio_pad_attr[k].slew_rate.d = dio_attr[k].slew_rate;
262 16/16 assign hw2reg.dio_pad_attr[k].input_disable.d = dio_attr[k].input_disable;
Tests: T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T49
263 0/16 ==> assign hw2reg.dio_pad_attr[k].od_en.d = dio_attr[k].od_en;
264 0/16 ==> assign hw2reg.dio_pad_attr[k].schmitt_en.d = dio_attr[k].schmitt_en;
265 0/16 ==> assign hw2reg.dio_pad_attr[k].keeper_en.d = dio_attr[k].keep_en;
266 16/16 assign hw2reg.dio_pad_attr[k].pull_select.d = dio_attr[k].pull_select;
Tests: T20 T21 T22 | T20 T21 T22 | T9 T10 T11 | T9 T10 T11 | T9 T10 T11 | T9 T10 T11 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T49 | T20 T21 T22 | T20 T22 T49 | T20 T21 T22 | T20 T21 T22 | T9 T47 T48 | T9 T47 T48
267 16/16 assign hw2reg.dio_pad_attr[k].pull_en.d = dio_attr[k].pull_en;
Tests: T20 T21 T22 | T20 T21 T22 | T9 T10 T11 | T9 T10 T11 | T9 T10 T11 | T9 T10 T11 | T20 T22 T49 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T9 T47 T48 | T9 T47 T48
268 14/16 ==> assign hw2reg.dio_pad_attr[k].virtual_od_en.d = dio_attr[k].virt_od_en;
Tests: T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T15 T51 T52 | T15 T51 T52 | T20 T21 T22 | T20 T21 T22
269 16/16 assign hw2reg.dio_pad_attr[k].invert.d = dio_attr[k].invert;
Tests: T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22
270 end
271
272 pad_attr_t [NMioPads-1:0] mio_attr;
273 for (genvar k = 0; k < NMioPads; k++) begin : gen_mio_attr
274 pad_attr_t warl_mask;
275
276 prim_pad_attr #(
277 .PadType(TargetCfg.mio_pad_type[k])
278 ) u_prim_pad_attr (
279 .attr_warl_o(warl_mask)
280 );
281
282 47/47 assign mio_attr[k] = mio_pad_attr_q[k] & warl_mask;
Tests: T20 T21 T22 | T20 T21 T22 | T9 T47 T48 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T12 T53 T54 | T20 T21 T22 | T9 T47 T48 | T9 T10 T11 | T20 T21 T22 | T9 T10 T11 | T9 T37 T47 | T9 T37 T47 | T9 T37 T47 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T58 T55 T59 | T58 T55 T59 | T58 T55 T59 | T1 T2 T3 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22
283 47/47 assign hw2reg.mio_pad_attr[k].drive_strength.d = mio_attr[k].drive_strength;
Tests: T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22
284 0/47 ==> assign hw2reg.mio_pad_attr[k].slew_rate.d = mio_attr[k].slew_rate;
285 47/47 assign hw2reg.mio_pad_attr[k].input_disable.d = mio_attr[k].input_disable;
Tests: T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22
286 0/47 ==> assign hw2reg.mio_pad_attr[k].od_en.d = mio_attr[k].od_en;
287 0/47 ==> assign hw2reg.mio_pad_attr[k].schmitt_en.d = mio_attr[k].schmitt_en;
288 0/47 ==> assign hw2reg.mio_pad_attr[k].keeper_en.d = mio_attr[k].keep_en;
289 47/47 assign hw2reg.mio_pad_attr[k].pull_select.d = mio_attr[k].pull_select;
Tests: T20 T21 T22 | T20 T21 T22 | T9 T47 T48 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T12 T53 T54 | T20 T21 T22 | T9 T47 T48 | T9 T10 T11 | T20 T21 T22 | T9 T10 T11 | T9 T37 T47 | T9 T37 T47 | T9 T37 T47 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T58 T55 T59 | T20 T21 T22 | T20 T21 T22 | T1 T2 T3 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22
290 47/47 assign hw2reg.mio_pad_attr[k].pull_en.d = mio_attr[k].pull_en;
Tests: T20 T21 T22 | T20 T21 T22 | T9 T47 T48 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T12 T53 T54 | T20 T21 T22 | T9 T47 T48 | T9 T10 T11 | T20 T21 T22 | T9 T10 T11 | T9 T37 T47 | T9 T37 T47 | T9 T37 T47 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T58 T55 T59 | T58 T55 T59 | T58 T55 T59 | T1 T2 T3 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22
291 47/47 assign hw2reg.mio_pad_attr[k].virtual_od_en.d = mio_attr[k].virt_od_en;
Tests: T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22
292 47/47 assign hw2reg.mio_pad_attr[k].invert.d = mio_attr[k].invert;
Tests: T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22 | T20 T21 T22
293 end
294
295
296 //////////////////////////
297 // Strap Sampling Logic //
298 //////////////////////////
299
300 logic strap_en;
301 if (SecVolatileRawUnlockEn) begin : gen_strap_override
302 logic strap_en_override_d, strap_en_override_q;
303 prim_flop_2sync #(
304 .Width(1),
305 .ResetValue(0)
306 ) u_prim_flop_2sync (
307 .clk_i,
308 .rst_ni,
309 .d_i(strap_en_override_i),
310 .q_o(strap_en_override_d)
311 );
312
313 always_ff @(posedge clk_i or negedge rst_ni) begin : p_strap_override_reg
314 if(!rst_ni) begin
315 strap_en_override_q <= 1'b0;
316 end else begin
317 strap_en_override_q <= strap_en_override_d;
318 end
319 end
320
321 // Detect a change from 0 -> 1 on the override signal (it will stay at 1 afterwards).
322 assign strap_en = strap_en_i || (strap_en_override_d && !strap_en_override_q);
323
324 // The strap sampling override shall be set to high exactly once.
325 `ASSUME(LcCtrlStrapSampleOverrideOnce_A,
326 $rose(strap_en_override_i) |-> always strap_en_override_i)
327
328 end else begin : gen_no_strap_override
329 logic unused_strap_en_override;
330 unreachable assign unused_strap_en_override = strap_en_override_i;
331 1/1 assign strap_en = strap_en_i;
Tests: T1 T2 T3
332 end
333
334 // Local versions of the input signals
335 logic [NMioPads-1:0] mio_out, mio_oe, mio_in;
336 logic [NDioPads-1:0] dio_out, dio_oe, dio_in;
337
338 // This module contains the strap sampling and JTAG mux.
339 // Affected inputs are intercepted/tapped before they go to the pinmux
340 // matrix. Likewise, affected outputs are intercepted/tapped after the
341 // retention registers.
342 pinmux_strap_sampling #(
343 .TargetCfg (TargetCfg)
344 ) u_pinmux_strap_sampling (
345 .clk_i,
346 // Inside the pinmux, the strap sampling module is the only module using SYS_RST. The reason for
347 // that is that SYS_RST reset will not be asserted during a NDM reset from the RV_DM and hence
348 // it retains some of the TAP selection state during an active debug session where NDM reset
349 // is triggered. To that end, the strap sampling module latches the lc_hw_debug_en_i signal
350 // whenever strap_en_i is asserted. Note that this does not affect the DFT TAP selection, since
351 // we always consume the live lc_dft_en_i signal.
352 .rst_ni (rst_sys_ni),
353 .scanmode_i,
354 // To padring side
355 .out_padring_o ( {dio_out_o, mio_out_o} ),
356 .oe_padring_o ( {dio_oe_o , mio_oe_o } ),
357 .in_padring_i ( {dio_in_i , mio_in_i } ),
358 .attr_padring_o ( {dio_attr_o, mio_attr_o} ),
359 // To core side
360 .out_core_i ( {dio_out, mio_out} ),
361 .oe_core_i ( {dio_oe, mio_oe} ),
362 .in_core_o ( {dio_in, mio_in} ),
363 .attr_core_i ( {dio_attr, mio_attr} ),
364 // Strap and JTAG signals
365 .strap_en_i ( strap_en ),
366 .lc_dft_en_i,
367 .lc_hw_debug_en_i,
368 .lc_escalate_en_i,
369 .lc_check_byp_en_i,
370 // This is the latched version of lc_hw_debug_en_i. We use it exclusively to gate the JTAG
371 // signals and TAP side of the RV_DM so that RV_DM can remain live during an NDM reset cycle.
372 .pinmux_hw_debug_en_o,
373 .dft_strap_test_o,
374 .dft_hold_tap_sel_i,
375 .lc_jtag_o,
376 .lc_jtag_i,
377 .rv_jtag_o,
378 .rv_jtag_i,
379 .dft_jtag_o,
380 .dft_jtag_i
381 );
382
383 ///////////////////////////////////////
384 // USB wake detect module connection //
385 ///////////////////////////////////////
386
387 // Dedicated Peripheral side
388 usbdev_aon_wake u_usbdev_aon_wake (
389 .clk_aon_i,
390 .rst_aon_ni,
391
392 // input signals for resume detection
393 .usb_dp_i(dio_to_periph_o[TargetCfg.usb_dp_idx]),
394 .usb_dn_i(dio_to_periph_o[TargetCfg.usb_dn_idx]),
395 .usb_sense_i(mio_to_periph_o[TargetCfg.usb_sense_idx]),
396 .usbdev_dppullup_en_i(usbdev_dppullup_en_i),
397 .usbdev_dnpullup_en_i(usbdev_dnpullup_en_i),
398
399 // output signals for pullup connectivity
400 .usb_dppullup_en_o(usb_dppullup_en_o),
401 .usb_dnpullup_en_o(usb_dnpullup_en_o),
402
403 // tie this to something from usbdev to indicate its out of reset
404 .suspend_req_aon_i(usbdev_suspend_req_i),
405 .wake_ack_aon_i(usbdev_wake_ack_i),
406
407 // wake/powerup request
408 .wake_req_aon_o(usb_wkup_req_o),
409 .bus_not_idle_aon_o(usbdev_bus_not_idle_o),
410 .bus_reset_aon_o(usbdev_bus_reset_o),
411 .sense_lost_aon_o(usbdev_sense_lost_o),
412 .wake_detect_active_aon_o(usbdev_wake_detect_active_o)
413 );
414
415 /////////////////////////
416 // Retention Registers //
417 /////////////////////////
418
419 logic sleep_en_q, sleep_trig;
420
421 logic [NMioPads-1:0] mio_sleep_trig;
422 logic [NMioPads-1:0] mio_out_retreg_d, mio_oe_retreg_d;
423 logic [NMioPads-1:0] mio_out_retreg_q, mio_oe_retreg_q;
424
425 logic [NDioPads-1:0] dio_sleep_trig;
426 logic [NDioPads-1:0] dio_out_retreg_d, dio_oe_retreg_d;
427 logic [NDioPads-1:0] dio_out_retreg_q, dio_oe_retreg_q;
428
429 // Sleep entry trigger
430 1/1 assign sleep_trig = sleep_en_i & ~sleep_en_q;
Tests: T1 T2 T3
431
432 always_ff @(posedge clk_i or negedge rst_ni) begin : p_sleep
433 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
434 1/1 sleep_en_q <= 1'b0;
Tests: T1 T2 T3
435 1/1 mio_out_retreg_q <= '0;
Tests: T1 T2 T3
436 1/1 mio_oe_retreg_q <= '0;
Tests: T1 T2 T3
437 1/1 dio_out_retreg_q <= '0;
Tests: T1 T2 T3
438 1/1 dio_oe_retreg_q <= '0;
Tests: T1 T2 T3
439 end else begin
440 1/1 sleep_en_q <= sleep_en_i;
Tests: T1 T2 T3
441
442 // MIOs
443 1/1 for (int k = 0; k < NMioPads; k++) begin
Tests: T1 T2 T3
444 1/1 if (mio_sleep_trig[k]) begin
Tests: T1 T2 T3
445 1/1 mio_out_retreg_q[k] <= mio_out_retreg_d[k];
Tests: T2 T6 T25
446 1/1 mio_oe_retreg_q[k] <= mio_oe_retreg_d[k];
Tests: T2 T6 T25
447 end
MISSING_ELSE
448 end
449
450 // DIOs
451 1/1 for (int k = 0; k < NDioPads; k++) begin
Tests: T1 T2 T3
452 1/1 if (dio_sleep_trig[k]) begin
Tests: T1 T2 T3
453 1/1 dio_out_retreg_q[k] <= dio_out_retreg_d[k];
Tests: T2 T6 T19
454 1/1 dio_oe_retreg_q[k] <= dio_oe_retreg_d[k];
Tests: T2 T6 T19
455 end
MISSING_ELSE
456 end
457 end
458 end
459
460 /////////////////////
461 // MIO Input Muxes //
462 /////////////////////
463
464 localparam int AlignedMuxSize = (NMioPads + 2 > NDioPads) ? 2**$clog2(NMioPads + 2) :
465 2**$clog2(NDioPads);
466
467 // stack input and default signals for convenient indexing below possible defaults:
468 // constant 0 or 1. make sure mux is aligned to a power of 2 to avoid Xes.
469 logic [AlignedMuxSize-1:0] mio_mux;
470 1/1 assign mio_mux = AlignedMuxSize'({mio_in, 1'b1, 1'b0});
Tests: T1 T2 T3
471
472 for (genvar k = 0; k < NMioPeriphIn; k++) begin : gen_mio_periph_in
473 // index using configured insel
474 57/57 assign mio_to_periph_o[k] = mio_mux[reg2hw.mio_periph_insel[k].q];
Tests: T6 T27 T42 | T25 T27 T42 | T25 T27 T42 | T25 T27 T42 | T25 T27 T42 | T25 T27 T42 | T25 T27 T42 | T25 T27 T42 | T25 T27 T42 | T27 T42 T43 | T27 T42 T43 | T27 T42 T43 | T27 T42 T43 | T27 T42 T43 | T27 T42 T43 | T27 T42 T43 | T27 T42 T43 | T27 T42 T43 | T27 T42 T43 | T27 T42 T43 | T27 T42 T43 | T27 T42 T43 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T27 T42 T43 | T27 T42 T43 | T27 T42 T43 | T27 T42 T43 | T27 T42 T43 | T27 T42 T43 | T27 T42 T43 | T62 T37 T63 | T62 T37 T63 | T64 T65 T37 | T64 T65 T37 | T66 T37 T67 | T66 T37 T67 | T9 T37 T47 | T9 T37 T47 | T9 T37 T47 | T9 T10 T11 | T1 T2 T3 | T1 T2 T3 | T68 T37 T69 | T26 T70 T37 | T12 T53 T54 | T71 T20 T21 | T71 T20 T21 | T71 T20 T21 | T28 T15 T72 | T28 T13 T72 | T28 T13 T72 | T28 T13 T72 | T28 T13 T15 | T28 T15 T72 | T7 T31 T8
475 end
476
477 //////////////////////
478 // MIO Output Muxes //
479 //////////////////////
480
481 // stack output data/enable and default signals for convenient indexing below
482 // possible defaults: 0, 1 or 2 (high-Z). make sure mux is aligned to a power of 2 to avoid Xes.
483 logic [2**$clog2(NMioPeriphOut+3)-1:0] periph_data_mux, periph_oe_mux;
484 1/1 assign periph_data_mux = $bits(periph_data_mux)'({periph_to_mio_i, 1'b0, 1'b1, 1'b0});
Tests: T5 T25 T26
485 1/1 assign periph_oe_mux = $bits(periph_oe_mux)'({periph_to_mio_oe_i, 1'b0, 1'b1, 1'b1});
Tests: T1 T3 T4
486
487 for (genvar k = 0; k < NMioPads; k++) begin : gen_mio_out
488 // Check individual sleep enable status bits
489 47/47 assign mio_out[k] = reg2hw.mio_pad_sleep_status[k].q ?
Tests: T2 T25 T27 | T2 T25 T26 | T2 T25 T27 | T2 T25 T27 | T2 T25 T27 | T2 T25 T27 | T2 T25 T27 | T2 T6 T25 | T2 T27 T62 | T2 T9 T10 | T2 T9 T10 | T2 T10 T11 | T2 T9 T10 | T2 T9 T37 | T1 T2 T3 | T2 T9 T27 | T2 T27 T13 | T2 T27 T37 | T2 T5 T27 | T2 T5 T27 | T2 T5 T27 | T2 T5 T27 | T2 T19 T40 | T2 T19 T40 | T2 T19 T40 | T2 T19 T40 | T1 T2 T3 | T2 T19 T40 | T2 T19 T40 | T2 T13 T41 | T2 T19 T40 | T2 T27 T13 | T2 T27 T35 | T2 T27 T35 | T2 T27 T35 | T2 T27 T37 | T2 T27 T37 | T2 T27 T37 | T2 T27 T37 | T2 T27 T42 | T2 T27 T13 | T2 T27 T13 | T2 T27 T37 | T2 T27 T37 | T2 T27 T37 | T2 T27 T42 | T2 T27 T37
490 mio_out_retreg_q[k] :
491 periph_data_mux[reg2hw.mio_outsel[k].q];
492
493 47/47 assign mio_oe[k] = reg2hw.mio_pad_sleep_status[k].q ?
Tests: T2 T25 T27 | T2 T25 T26 | T2 T25 T27 | T2 T25 T27 | T2 T25 T27 | T2 T25 T27 | T2 T25 T27 | T2 T6 T25 | T2 T27 T62 | T2 T9 T10 | T2 T9 T10 | T2 T10 T11 | T2 T9 T10 | T2 T9 T37 | T1 T2 T3 | T2 T9 T27 | T2 T27 T13 | T2 T27 T37 | T2 T5 T27 | T2 T5 T27 | T2 T5 T27 | T2 T5 T27 | T2 T19 T40 | T2 T19 T40 | T2 T19 T40 | T2 T19 T40 | T1 T2 T3 | T2 T19 T40 | T2 T19 T40 | T2 T13 T41 | T2 T19 T40 | T2 T27 T13 | T2 T27 T35 | T2 T27 T35 | T2 T27 T35 | T2 T27 T37 | T2 T27 T37 | T2 T27 T37 | T2 T27 T37 | T2 T27 T42 | T2 T27 T13 | T2 T27 T13 | T2 T27 T37 | T2 T27 T37 | T2 T27 T37 | T2 T27 T42 | T2 T27 T37
494 mio_oe_retreg_q[k] :
495 periph_oe_mux[reg2hw.mio_outsel[k].q];
496
497 // latch state when going to sleep
498 // 0: drive low
499 // 1: drive high
500 // 2: high-z
501 // 3: previous value
502 47/47 assign mio_out_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b0 :
Tests: T2 T25 T27 | T25 T26 T27 | T2 T25 T27 | T2 T25 T27 | T25 T27 T42 | T25 T27 T68 | T25 T27 T42 | T2 T6 T25 | T2 T27 T42 | T10 T11 T37 | T2 T9 T37 | T2 T37 T19 | T2 T19 T47 | T37 T73 T74 | T1 T2 T3 | T27 T37 T42 | T2 T27 T13 | T2 T27 T37 | T5 T27 T13 | T2 T5 T27 | T5 T27 T35 | T5 T27 T35 | T2 T19 T40 | T19 T40 T20 | T2 T40 T20 | T2 T19 T40 | T1 T2 T3 | T19 T40 T20 | T2 T40 T20 | T13 T41 T19 | T2 T19 T40 | T27 T13 T41 | T2 T27 T35 | T2 T27 T35 | T27 T35 T75 | T2 T27 T37 | T2 T27 T37 | T2 T27 T37 | T2 T27 T37 | T2 T27 T42 | T2 T27 T13 | T2 T27 T13 | T2 T27 T37 | T2 T27 T37 | T2 T27 T37 | T2 T27 T42 | T2 T27 T37
503 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 :
504 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_out[k];
505
506 47/47 assign mio_oe_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b1 :
Tests: T2 T25 T27 | T25 T26 T27 | T2 T25 T27 | T2 T25 T27 | T25 T27 T42 | T25 T27 T68 | T25 T27 T42 | T2 T6 T25 | T2 T27 T62 | T37 T19 T47 | T2 T37 T19 | T2 T37 T19 | T2 T37 T19 | T37 T73 T74 | T1 T2 T3 | T27 T37 T42 | T2 T27 T13 | T2 T27 T37 | T5 T27 T65 | T2 T5 T27 | T5 T27 T66 | T5 T27 T66 | T2 T19 T40 | T19 T40 T20 | T2 T40 T20 | T2 T19 T40 | T1 T2 T3 | T19 T40 T20 | T2 T40 T20 | T13 T41 T19 | T2 T19 T40 | T27 T13 T41 | T2 T27 T35 | T2 T27 T35 | T27 T35 T75 | T2 T27 T37 | T2 T27 T37 | T2 T27 T37 | T2 T27 T37 | T2 T27 T42 | T2 T27 T13 | T2 T27 T13 | T2 T27 T37 | T2 T27 T37 | T2 T27 T37 | T2 T27 T42 | T2 T27 T37
507 (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 :
508 (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_oe[k];
509
510 // Activate sleep behavior only if it has been enabled
511 47/47 assign mio_sleep_trig[k] = reg2hw.mio_pad_sleep_en[k].q & sleep_trig;
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3
512 assign hw2reg.mio_pad_sleep_status[k].d = 1'b1;
513 47/47 assign hw2reg.mio_pad_sleep_status[k].de = mio_sleep_trig[k];
Tests: T2 T25 T19 | T2 T25 T19 | T2 T25 T19 | T2 T25 T19 | T2 T25 T19 | T2 T25 T19 | T2 T25 T19 | T2 T6 T25 | T2 T19 T40 | T2 T19 T40 | T2 T19 T40 | T2 T19 T40 | T2 T19 T40 | T2 T19 T40 | T2 T19 T40 | T2 T19 T40 | T2 T19 T40 | T2 T19 T40 | T2 T19 T40 | T2 T19 T40 | T2 T19 T40 | T2 T19 T40 | T2 T19 T40 | T2 T19 T40 | T2 T19 T40 | T2 T19 T40 | T2 T19 T40 | T2 T19 T40 | T2 T19 T40 | T2 T19 T40 | T2 T19 T40 | T2 T19 T40 | T2 T19 T40 | T2 T19 T40 | T2 T19 T40 | T2 T19 T40 | T2 T19 T40 | T2 T19 T40 | T2 T19 T40 | T2 T19 T40 | T2 T19 T40 | T2 T19 T40 | T2 T19 T40 | T2 T19 T40 | T2 T19 T40 | T2 T19 T40 | T2 T19 T40
514 end
515
516 /////////////////////
517 // DIO connections //
518 /////////////////////
519
520 // Inputs are just fed through
521 1/1 assign dio_to_periph_o = dio_in;
Tests: T2 T4 T7
522
523 for (genvar k = 0; k < NDioPads; k++) begin : gen_dio_out
524 // Check individual sleep enable status bits
525 16/16 assign dio_out[k] = reg2hw.dio_pad_sleep_status[k].q ?
Tests: T2 T7 T8 | T2 T7 T8 | T2 T9 T10 | T2 T10 T11 | T2 T10 T11 | T2 T10 T11 | T2 T6 T10 | T2 T6 T12 | T2 T6 T10 | T2 T6 T10 | T2 T13 T14 | T2 T13 T15 | T2 T19 T40 | T2 T19 T40 | T2 T9 T10 | T2 T9 T10
526 dio_out_retreg_q[k] :
527 periph_to_dio_i[k];
528
529 16/16 assign dio_oe[k] = reg2hw.dio_pad_sleep_status[k].q ?
Tests: T2 T16 T17 | T2 T16 T17 | T2 T9 T10 | T2 T19 T40 | T2 T19 T40 | T2 T19 T40 | T2 T6 T10 | T2 T6 T12 | T2 T6 T10 | T2 T6 T10 | T2 T4 T19 | T2 T4 T19 | T2 T19 T40 | T2 T19 T40 | T2 T9 T10 | T2 T9 T10
530 dio_oe_retreg_q[k] :
531 periph_to_dio_oe_i[k];
532
533 // latch state when going to sleep
534 // 0: drive low
535 // 1: drive high
536 // 2: high-z
537 // 3: previous value
538 14/16 ==> assign dio_out_retreg_d[k] = (reg2hw.dio_pad_sleep_mode[k].q == 0) ? 1'b0 :
Tests: T2 T7 T8 | T2 T7 T8 | T2 T9 T10 | T2 T10 T11 | T2 T10 T11 | T2 T10 T11 | T2 T6 T10 | T2 T6 T12 | T2 T6 T10 | T6 T10 T11 | T2 T13 T14 | T2 T13 T15 | T2 T9 T10 | T2 T9 T10
539 (reg2hw.dio_pad_sleep_mode[k].q == 1) ? 1'b1 :
540 (reg2hw.dio_pad_sleep_mode[k].q == 2) ? 1'b0 : dio_out[k];
541
542 16/16 assign dio_oe_retreg_d[k] = (reg2hw.dio_pad_sleep_mode[k].q == 0) ? 1'b1 :
Tests: T16 T17 T18 | T2 T16 T17 | T2 T9 T10 | T2 T19 T20 | T2 T20 T21 | T2 T19 T20 | T2 T6 T10 | T2 T6 T12 | T2 T6 T10 | T6 T10 T37 | T2 T4 T19 | T2 T4 T19 | T20 T21 T22 | T20 T21 T22 | T2 T9 T10 | T2 T9 T10
543 (reg2hw.dio_pad_sleep_mode[k].q == 1) ? 1'b1 :
544 (reg2hw.dio_pad_sleep_mode[k].q == 2) ? 1'b0 : dio_oe[k];
545
546 // Activate sleep behavior only if it has been enabled
547 16/16 assign dio_sleep_trig[k] = reg2hw.dio_pad_sleep_en[k].q & sleep_trig;
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3
548 assign hw2reg.dio_pad_sleep_status[k].d = 1'b1;
549 16/16 assign hw2reg.dio_pad_sleep_status[k].de = dio_sleep_trig[k];
Tests: T2 T19 T40 | T2 T19 T40 | T2 T19 T40 | T2 T19 T40 | T2 T19 T40 | T2 T19 T40 | T2 T6 T19 | T2 T6 T19 | T2 T6 T19 | T2 T6 T19 | T2 T19 T40 | T2 T19 T40 | T2 T19 T40 | T2 T19 T40 | T2 T19 T40 | T2 T19 T40
550 end
551
552 //////////////////////
553 // Wakeup detectors //
554 //////////////////////
555
556 // Wakeup detectors should not be connected to the scan clock, so filter
557 // those inputs.
558 logic [NDioPads-1:0] dio_wkup_no_scan;
559 for (genvar k = 0; k < NDioPads; k++) begin : gen_dio_wkup_filter
560 if (TargetCfg.dio_scan_role[k] == ScanClock) begin : gen_dio_scan
561 always_comb begin
562 1/1 dio_wkup_no_scan[k] = dio_in_i[k];
Tests: T2 T6 T12
563 1/1 if (prim_mubi_pkg::mubi4_test_true_strict(scanmode_i)) begin
Tests: T2 T6 T12
564 0/1 ==> dio_wkup_no_scan[k] = 1'b0;
565 end
MISSING_ELSE
566 end
567 end else begin : gen_no_dio_scan
568 15/15 assign dio_wkup_no_scan[k] = dio_in_i[k];
Tests: T2 T7 T31 | T2 T7 T8 | T2 T9 T10 | T2 T9 T10 | T2 T9 T10 | T2 T9 T10 | T2 T4 T6 | T2 T4 T6 | T2 T4 T6 | T2 T4 T6 | T2 T4 T28 | T4 T28 T13 | T2 T4 T6 | T2 T9 T10 | T2 T6 T9
569 end
570 end
571
572 logic [NMioPads-1:0] mio_wkup_no_scan;
573 for (genvar k = 0; k < NMioPads; k++) begin : gen_mio_wkup_filter
574 if (TargetCfg.mio_scan_role[k] == ScanClock) begin : gen_mio_scan
575 always_comb begin
576 mio_wkup_no_scan[k] = mio_in_i[k];
577 if (prim_mubi_pkg::mubi4_test_true_strict(scanmode_i)) begin
578 mio_wkup_no_scan[k] = 1'b0;
579 end
580 end
581 end else begin : gen_no_mio_scan
582 47/47 assign mio_wkup_no_scan[k] = mio_in_i[k];
Tests: T2 T25 T26 | T2 T25 T26 | T2 T25 T9 | T2 T25 T27 | T2 T25 T27 | T2 T4 T25 | T2 T25 T27 | T2 T6 T25 | T2 T6 T25 | T2 T9 T37 | T2 T9 T10 | T2 T6 T37 | T2 T9 T10 | T2 T6 T9 | T1 T2 T3 | T2 T9 T27 | T2 T27 T13 | T2 T27 T28 | T2 T5 T27 | T2 T5 T27 | T2 T5 T27 | T2 T5 T27 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T2 T29 T30 | T2 T7 T31 | T32 T33 T34 | T2 T27 T28 | T2 T27 T35 | T2 T27 T35 | T2 T27 T35 | T2 T27 T36 | T2 T27 T36 | T2 T27 T36 | T2 T27 T36 | T2 T27 T36 | T1 T2 T3 | T2 T27 T13 | T1 T2 T3 | T2 T27 T37 | T2 T27 T37 | T2 T27 T38 | T2 T27 T28
583 end
584 end
585
586 // Wakeup detector taps are not affected by JTAG/strap
587 // selection mux. I.e., we always sample the unmuxed inputs
588 // that come directly from the pads.
589 logic [AlignedMuxSize-1:0] dio_wkup_mux;
590 logic [AlignedMuxSize-1:0] mio_wkup_mux;
591 1/1 assign dio_wkup_mux = AlignedMuxSize'(dio_wkup_no_scan);
Tests: T2 T4 T7
592 // The two constants that are concatenated here make sure tha the selection
593 // indices used to index this array are the same as the ones used to index
594 // the mio_mux array above, where positions 0 and 1 select constant 0 and
595 // 1, respectively.
596 1/1 assign mio_wkup_mux = AlignedMuxSize'({mio_wkup_no_scan, 1'b1, 1'b0});
Tests: T1 T2 T3
597
598 logic [NWkupDetect-1:0] aon_wkup_req;
599 for (genvar k = 0; k < NWkupDetect; k++) begin : gen_wkup_detect
600 logic pin_value;
601 8/8 assign pin_value = (reg2hw.wkup_detector[k].miodio.q) ?
Tests: T2 T7 T6 | T2 T7 T31 | T2 T7 T31 | T2 T7 T31 | T2 T7 T31 | T2 T7 T31 | T2 T7 T31 | T2 T4 T7
602 dio_wkup_mux[reg2hw.wkup_detector_padsel[k]] :
603 mio_wkup_mux[reg2hw.wkup_detector_padsel[k]];
604
605 // This module runs on the AON clock entirely
606 pinmux_wkup u_pinmux_wkup (
607 .clk_i (clk_aon_i ),
608 .rst_ni (rst_aon_ni ),
609 // config signals have already been synced to the AON domain inside the CSR node.
610 .wkup_en_i ( reg2hw.wkup_detector_en[k].q ),
611 .filter_en_i ( reg2hw.wkup_detector[k].filter.q ),
612 .wkup_mode_i ( wkup_mode_e'(reg2hw.wkup_detector[k].mode.q) ),
613 .wkup_cnt_th_i ( reg2hw.wkup_detector_cnt_th[k].q ),
614 .pin_value_i ( pin_value ),
615 // wakeup request pulse on clk_aon, will be synced back to the bus domain insie the CSR node.
616 .aon_wkup_pulse_o ( hw2reg.wkup_cause[k].de )
617 );
618
619 assign hw2reg.wkup_cause[k].d = 1'b1;
620
621 // This is the latched wakeup request, hence this request signal is level encoded.
622 4/8 ==> assign aon_wkup_req[k] = reg2hw.wkup_cause[k].q;
Tests: T6 T25 T76 | T23 | T77 T78 T79 | T4 T24
623 end
624
625 // OR' together all wakeup requests
626 1/1 assign pin_wkup_req_o = |aon_wkup_req;
Tests: T4 T6 T25