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 LINE       16856
 SUB-EXPRESSION (addr_hit[104] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T346,T283,T128
1	1	Covered	T428,T429,T421

 LINE       16856
 SUB-EXPRESSION (addr_hit[105] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T346,T283,T128
1	1	Covered	T429,T421,T173

 LINE       16856
 SUB-EXPRESSION (addr_hit[106] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T346,T283,T128
1	1	Covered	T428,T429,T169

 LINE       16856
 SUB-EXPRESSION (addr_hit[107] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T71,T346,T283
1	1	Covered	T428,T429,T169

 LINE       16856
 SUB-EXPRESSION (addr_hit[108] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T71,T346,T283
1	1	Covered	T428,T429,T173

 LINE       16856
 SUB-EXPRESSION (addr_hit[109] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T346,T283,T128
1	1	Covered	T429,T169,T173

 LINE       16856
 SUB-EXPRESSION (addr_hit[110] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T71,T346,T283
1	1	Covered	T428,T429,T173

 LINE       16856
 SUB-EXPRESSION (addr_hit[111] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T71,T346,T283
1	1	Covered	T428,T169,T571

 LINE       16856
 SUB-EXPRESSION (addr_hit[112] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T71,T346,T283
1	1	Covered	T428,T429,T571

 LINE       16856
 SUB-EXPRESSION (addr_hit[113] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T71,T346,T283
1	1	Covered	T428,T429,T173

 LINE       16856
 SUB-EXPRESSION (addr_hit[114] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T71,T346,T283
1	1	Covered	T428,T429,T571

 LINE       16856
 SUB-EXPRESSION (addr_hit[115] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T346,T283,T128
1	1	Covered	T428,T429,T169

 LINE       16856
 SUB-EXPRESSION (addr_hit[116] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T35,T71,T346
1	1	Covered	T428,T429,T421

 LINE       16856
 SUB-EXPRESSION (addr_hit[117] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T35,T346,T283
1	1	Covered	T428,T173,T571

 LINE       16856
 SUB-EXPRESSION (addr_hit[118] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T346,T283,T128
1	1	Covered	T428,T429,T169

 LINE       16856
 SUB-EXPRESSION (addr_hit[119] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T35,T346,T283
1	1	Covered	T428,T429,T169

 LINE       16856
 SUB-EXPRESSION (addr_hit[120] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T35,T346,T283
1	1	Covered	T428,T429,T173

 LINE       16856
 SUB-EXPRESSION (addr_hit[121] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T35,T346,T283
1	1	Covered	T428,T429,T169

 LINE       16856
 SUB-EXPRESSION (addr_hit[122] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T2,T346,T283
1	1	Covered	T428,T429,T571

 LINE       16856
 SUB-EXPRESSION (addr_hit[123] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T2,T346,T283
1	1	Covered	T428,T429,T169

 LINE       16856
 SUB-EXPRESSION (addr_hit[124] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T346,T283,T128
1	1	Covered	T428,T429,T169

 LINE       16856
 SUB-EXPRESSION (addr_hit[125] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T346,T283,T128
1	1	Covered	T428,T429,T169

 LINE       16856
 SUB-EXPRESSION (addr_hit[126] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T346,T283,T128
1	1	Covered	T429,T571,T568

 LINE       16856
 SUB-EXPRESSION (addr_hit[127] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T53,T88,T89
1	1	Covered	T428,T429,T421

 LINE       16856
 SUB-EXPRESSION (addr_hit[128] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T53,T88,T89
1	1	Covered	T428,T429,T169

 LINE       16856
 SUB-EXPRESSION (addr_hit[129] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T53,T88,T89
1	1	Covered	T428,T429,T571

 LINE       16856
 SUB-EXPRESSION (addr_hit[130] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T53,T88,T89
1	1	Covered	T428,T429,T169

 LINE       16856
 SUB-EXPRESSION (addr_hit[131] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T11,T12,T346
1	1	Covered	T428,T429,T169

 LINE       16856
 SUB-EXPRESSION (addr_hit[132] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T11,T12,T346
1	1	Covered	T428,T429,T169

 LINE       16856
 SUB-EXPRESSION (addr_hit[133] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T346,T283,T128
1	1	Covered	T428,T429,T571

 LINE       16856
 SUB-EXPRESSION (addr_hit[134] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T346,T283,T128
1	1	Covered	T429,T169,T571

 LINE       16856
 SUB-EXPRESSION (addr_hit[135] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T346,T283,T128
1	1	Covered	T428,T429,T169

 LINE       16856
 SUB-EXPRESSION (addr_hit[136] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T346,T283,T128
1	1	Covered	T428,T429,T173

 LINE       16856
 SUB-EXPRESSION (addr_hit[137] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T346,T283,T128
1	1	Covered	T428,T429,T169

 LINE       16856
 SUB-EXPRESSION (addr_hit[138] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T346,T283,T128
1	1	Covered	T428,T429,T571

 LINE       16856
 SUB-EXPRESSION (addr_hit[139] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T346,T283,T128
1	1	Covered	T429,T169,T571

 LINE       16856
 SUB-EXPRESSION (addr_hit[140] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T346,T283,T128
1	1	Covered	T428,T429,T169

 LINE       16856
 SUB-EXPRESSION (addr_hit[141] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T346,T283,T128
1	1	Covered	T428,T429,T421

 LINE       16856
 SUB-EXPRESSION (addr_hit[142] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T346,T283,T128
1	1	Covered	T428,T429,T169

 LINE       16856
 SUB-EXPRESSION (addr_hit[143] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T346,T283,T128
1	1	Covered	T428,T429,T421

 LINE       16856
 SUB-EXPRESSION (addr_hit[144] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T346,T283,T128
1	1	Covered	T428,T429,T571

 LINE       16856
 SUB-EXPRESSION (addr_hit[145] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T346,T283,T128
1	1	Covered	T428,T429,T571

 LINE       16856
 SUB-EXPRESSION (addr_hit[146] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T346,T283,T128
1	1	Covered	T428,T429,T169

 LINE       16856
 SUB-EXPRESSION (addr_hit[147] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T346,T283,T128
1	1	Covered	T428,T429,T173

 LINE       16856
 SUB-EXPRESSION (addr_hit[148] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T346,T283,T128
1	1	Covered	T428,T429,T173

 LINE       16856
 SUB-EXPRESSION (addr_hit[149] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T346,T283,T128
1	1	Covered	T428,T429,T169

 LINE       16856
 SUB-EXPRESSION (addr_hit[150] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T346,T283,T128
1	1	Covered	T428,T429,T421

 LINE       16856
 SUB-EXPRESSION (addr_hit[151] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T346,T283,T128
1	1	Covered	T428,T429,T571

 LINE       16856
 SUB-EXPRESSION (addr_hit[152] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T346,T283,T128
1	1	Covered	T428,T429,T173

 LINE       16856
 SUB-EXPRESSION (addr_hit[153] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T5,T6,T27
1	1	Covered	T428,T429,T169

 LINE       16856
 SUB-EXPRESSION (addr_hit[154] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T75,T346,T283
1	1	Covered	T428,T429,T173

 LINE       16856
 SUB-EXPRESSION (addr_hit[155] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T138,T346,T283
1	1	Covered	T429,T571,T179

 LINE       16856
 SUB-EXPRESSION (addr_hit[156] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T53,T88,T89
1	1	Covered	T428,T429,T169

 LINE       16856
 SUB-EXPRESSION (addr_hit[157] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T267,T53,T88
1	1	Covered	T428,T429,T571

 LINE       16856
 SUB-EXPRESSION (addr_hit[158] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T177,T346,T283
1	1	Covered	T428,T429,T169

 LINE       16856
 SUB-EXPRESSION (addr_hit[159] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T346,T283,T128
1	1	Covered	T428,T429,T173

 LINE       16856
 SUB-EXPRESSION (addr_hit[160] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T121,T225,T145
1	1	Covered	T428,T429,T169

 LINE       16856
 SUB-EXPRESSION (addr_hit[161] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T121,T225,T145
1	1	Covered	T429,T421,T173

 LINE       16856
 SUB-EXPRESSION (addr_hit[162] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T121,T225,T145
1	1	Covered	T428,T429,T169

 LINE       16856
 SUB-EXPRESSION (addr_hit[163] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T121,T225,T145
1	1	Covered	T428,T429,T169

 LINE       16856
 SUB-EXPRESSION (addr_hit[164] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T121,T225,T145
1	1	Covered	T428,T429,T173

 LINE       16856
 SUB-EXPRESSION (addr_hit[165] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T346,T283,T128
1	1	Covered	T428,T429,T571

 LINE       16856
 SUB-EXPRESSION (addr_hit[166] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T347,T348,T346
1	1	Covered	T428,T421,T571

 LINE       16856
 SUB-EXPRESSION (addr_hit[167] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T347,T348,T346
1	1	Covered	T428,T429,T173

 LINE       16856
 SUB-EXPRESSION (addr_hit[168] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T346,T283,T128
1	1	Covered	T428,T429,T421

 LINE       16856
 SUB-EXPRESSION (addr_hit[169] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T346,T283,T128
1	1	Covered	T428,T429,T421

 LINE       16856
 SUB-EXPRESSION (addr_hit[170] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T346,T283,T128
1	1	Covered	T428,T429,T571

 LINE       16856
 SUB-EXPRESSION (addr_hit[171] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T346,T283,T128
1	1	Covered	T428,T429,T169

 LINE       16856
 SUB-EXPRESSION (addr_hit[172] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T160,T346,T283
1	1	Covered	T429,T421,T571

 LINE       16856
 SUB-EXPRESSION (addr_hit[173] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T346,T283,T128
1	1	Covered	T428,T429,T169

 LINE       16856
 SUB-EXPRESSION (addr_hit[174] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T346,T283,T128
1	1	Covered	T428,T173,T571

 LINE       16856
 SUB-EXPRESSION (addr_hit[175] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T346,T283,T128
1	1	Covered	T428,T429,T169

 LINE       16856
 SUB-EXPRESSION (addr_hit[176] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T346,T283,T128
1	1	Covered	T428,T429,T169

 LINE       16856
 SUB-EXPRESSION (addr_hit[177] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T346,T283,T128
1	1	Covered	T428,T429,T571

 LINE       16856
 SUB-EXPRESSION (addr_hit[178] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T346,T283,T128
1	1	Covered	T428,T429,T571

 LINE       16856
 SUB-EXPRESSION (addr_hit[179] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T346,T283,T128
1	1	Covered	T428,T429,T179

 LINE       16856
 SUB-EXPRESSION (addr_hit[180] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T346,T283,T128
1	1	Covered	T428,T429,T169

 LINE       16856
 SUB-EXPRESSION (addr_hit[181] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T346,T283,T128
1	1	Covered	T428,T429,T173

 LINE       16856
 SUB-EXPRESSION (addr_hit[182] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T346,T283,T128
1	1	Covered	T429,T169,T571

 LINE       16856
 SUB-EXPRESSION (addr_hit[183] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T346,T283,T128
1	1	Covered	T429,T169,T571

 LINE       16856
 SUB-EXPRESSION (addr_hit[184] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T346,T283,T128
1	1	Covered	T428,T429,T421

 LINE       16856
 SUB-EXPRESSION (addr_hit[185] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T346,T283,T128
1	1	Covered	T428,T429,T173

 LINE       16856
 SUB-EXPRESSION (addr_hit[186] & ((|(4'b1111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T169,T421,T173
1	1	Covered	T428,T429,T173

 LINE       16856
 SUB-EXPRESSION (addr_hit[187] & ((|(4'b1111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T169,T421,T173
1	1	Covered	T429,T173,T571

 LINE       16856
 SUB-EXPRESSION (addr_hit[188] & ((|(4'b1111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T169,T421,T173
1	1	Covered	T428,T429,T169

 LINE       16856
 SUB-EXPRESSION (addr_hit[189] & ((|(4'b1111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T169,T421,T173
1	1	Covered	T428,T429,T169

 LINE       16856
 SUB-EXPRESSION (addr_hit[190] & ((|(4'b1111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T358,T663,T664
1	1	Covered	T428,T429,T169

 LINE       16856
 SUB-EXPRESSION (addr_hit[191] & ((|(4'b1111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T169,T421,T173
1	1	Covered	T428,T429,T169

 LINE       16856
 SUB-EXPRESSION (addr_hit[192] & ((|(4'b1111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T31,T29,T131
1	1	Covered	T428,T429,T169

 LINE       16856
 SUB-EXPRESSION (addr_hit[193] & ((|(4'b1111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T28,T29,T72
1	1	Covered	T428,T429,T173

 LINE       16856
 SUB-EXPRESSION (addr_hit[194] & ((|(4'b1111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T14,T28,T34
1	1	Covered	T429,T169,T421

 LINE       16856
 SUB-EXPRESSION (addr_hit[195] & ((|(4'b1111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T2,T35,T34
1	1	Covered	T428,T429,T169

 LINE       16856
 SUB-EXPRESSION (addr_hit[196] & ((|(4'b1111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T5,T6,T27
1	1	Covered	T428,T169,T421

 LINE       16856
 SUB-EXPRESSION (addr_hit[197] & ((|(4'b1111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T121,T225,T145
1	1	Covered	T428,T429,T421

 LINE       16856
 SUB-EXPRESSION (addr_hit[198] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T2,T5,T6
1	1	Covered	T429,T169,T173

 LINE       16856
 SUB-EXPRESSION (addr_hit[199] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T2,T5,T6
1	1	Covered	T428,T429,T169

 LINE       16856
 SUB-EXPRESSION (addr_hit[200] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T283,T77,T284
1	1	Covered	T428,T429,T173

 LINE       16856
 SUB-EXPRESSION (addr_hit[201] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T83,T84,T85
1	1	Covered	T428,T429,T173

 LINE       17062
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T5,T6
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T571,T576,T604
1	1	1	Covered	T283,T284,T345

 LINE       17065
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T5,T6
1	0	1	Covered	T428,T169,T421
1	1	0	Covered	T429,T571,T568
1	1	1	Covered	T131,T346,T283

 LINE       17068
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T5,T6
1	0	1	Covered	T429,T169,T421
1	1	0	Covered	T571,T578,T577
1	1	1	Covered	T131,T346,T283

 LINE       17071
 EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T5,T6
1	0	1	Covered	T428,T429,T169
1	1	0	Covered	T579,T569,T600
1	1	1	Covered	T131,T346,T283