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67 always_ff @(posedge clk_i or negedge rst_ni) begin
68 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
69 1/1 err_q <= '0;
Tests: T1 T2 T3
70 1/1 end else if (intg_err || reg_we_err) begin
Tests: T1 T2 T3
71 0/1 ==> err_q <= 1'b1;
72 end
MISSING_ELSE
73 end
74
75 // integrity error output is permanent and should be used for alert generation
76 // register errors are transactional
77 1/1 assign intg_err_o = err_q | intg_err | reg_we_err;
Tests: T2 T4 T5
78
79 // outgoing integrity generation
80 tlul_pkg::tl_d2h_t tl_o_pre;
81 tlul_rsp_intg_gen #(
82 .EnableRspIntgGen(1),
83 .EnableDataIntgGen(1)
84 ) u_rsp_intg_gen (
85 .tl_i(tl_o_pre),
86 .tl_o(tl_o)
87 );
88
89 1/1 assign tl_reg_h2d = tl_i;
Tests: T1 T2 T3
90 1/1 assign tl_o_pre = tl_reg_d2h;
Tests: T2 T4 T5
91
92 tlul_adapter_reg #(
93 .RegAw(AW),
94 .RegDw(DW),
95 .EnableDataIntgGen(0)
96 ) u_reg_if (
97 .clk_i (clk_i),
98 .rst_ni (rst_ni),
99
100 .tl_i (tl_reg_h2d),
101 .tl_o (tl_reg_d2h),
102
103 .en_ifetch_i(prim_mubi_pkg::MuBi4False),
104 .intg_error_o(),
105
106 .we_o (reg_we),
107 .re_o (reg_re),
108 .addr_o (reg_addr),
109 .wdata_o (reg_wdata),
110 .be_o (reg_be),
111 .busy_i (reg_busy),
112 .rdata_i (reg_rdata),
113 .error_i (reg_error)
114 );
115
116 // cdc oversampling signals
117
118 1/1 assign reg_rdata = reg_rdata_next ;
Tests: T2 T4 T5
119 1/1 assign reg_error = addrmiss | wr_err | intg_err;
Tests: T2 T4 T5
120
121 // Define SW related signals
122 // Format: <reg>_<field>_{wd|we|qs}
123 // or <reg>_{wd|we|qs} if field == 1 or 0
124 logic prio0_we;
125 logic [1:0] prio0_qs;
126 logic [1:0] prio0_wd;
127 logic prio1_we;
128 logic [1:0] prio1_qs;
129 logic [1:0] prio1_wd;
130 logic prio2_we;
131 logic [1:0] prio2_qs;
132 logic [1:0] prio2_wd;
133 logic prio3_we;
134 logic [1:0] prio3_qs;
135 logic [1:0] prio3_wd;
136 logic prio4_we;
137 logic [1:0] prio4_qs;
138 logic [1:0] prio4_wd;
139 logic prio5_we;
140 logic [1:0] prio5_qs;
141 logic [1:0] prio5_wd;
142 logic prio6_we;
143 logic [1:0] prio6_qs;
144 logic [1:0] prio6_wd;
145 logic prio7_we;
146 logic [1:0] prio7_qs;
147 logic [1:0] prio7_wd;
148 logic prio8_we;
149 logic [1:0] prio8_qs;
150 logic [1:0] prio8_wd;
151 logic prio9_we;
152 logic [1:0] prio9_qs;
153 logic [1:0] prio9_wd;
154 logic prio10_we;
155 logic [1:0] prio10_qs;
156 logic [1:0] prio10_wd;
157 logic prio11_we;
158 logic [1:0] prio11_qs;
159 logic [1:0] prio11_wd;
160 logic prio12_we;
161 logic [1:0] prio12_qs;
162 logic [1:0] prio12_wd;
163 logic prio13_we;
164 logic [1:0] prio13_qs;
165 logic [1:0] prio13_wd;
166 logic prio14_we;
167 logic [1:0] prio14_qs;
168 logic [1:0] prio14_wd;
169 logic prio15_we;
170 logic [1:0] prio15_qs;
171 logic [1:0] prio15_wd;
172 logic prio16_we;
173 logic [1:0] prio16_qs;
174 logic [1:0] prio16_wd;
175 logic prio17_we;
176 logic [1:0] prio17_qs;
177 logic [1:0] prio17_wd;
178 logic prio18_we;
179 logic [1:0] prio18_qs;
180 logic [1:0] prio18_wd;
181 logic prio19_we;
182 logic [1:0] prio19_qs;
183 logic [1:0] prio19_wd;
184 logic prio20_we;
185 logic [1:0] prio20_qs;
186 logic [1:0] prio20_wd;
187 logic prio21_we;
188 logic [1:0] prio21_qs;
189 logic [1:0] prio21_wd;
190 logic prio22_we;
191 logic [1:0] prio22_qs;
192 logic [1:0] prio22_wd;
193 logic prio23_we;
194 logic [1:0] prio23_qs;
195 logic [1:0] prio23_wd;
196 logic prio24_we;
197 logic [1:0] prio24_qs;
198 logic [1:0] prio24_wd;
199 logic prio25_we;
200 logic [1:0] prio25_qs;
201 logic [1:0] prio25_wd;
202 logic prio26_we;
203 logic [1:0] prio26_qs;
204 logic [1:0] prio26_wd;
205 logic prio27_we;
206 logic [1:0] prio27_qs;
207 logic [1:0] prio27_wd;
208 logic prio28_we;
209 logic [1:0] prio28_qs;
210 logic [1:0] prio28_wd;
211 logic prio29_we;
212 logic [1:0] prio29_qs;
213 logic [1:0] prio29_wd;
214 logic prio30_we;
215 logic [1:0] prio30_qs;
216 logic [1:0] prio30_wd;
217 logic prio31_we;
218 logic [1:0] prio31_qs;
219 logic [1:0] prio31_wd;
220 logic prio32_we;
221 logic [1:0] prio32_qs;
222 logic [1:0] prio32_wd;
223 logic prio33_we;
224 logic [1:0] prio33_qs;
225 logic [1:0] prio33_wd;
226 logic prio34_we;
227 logic [1:0] prio34_qs;
228 logic [1:0] prio34_wd;
229 logic prio35_we;
230 logic [1:0] prio35_qs;
231 logic [1:0] prio35_wd;
232 logic prio36_we;
233 logic [1:0] prio36_qs;
234 logic [1:0] prio36_wd;
235 logic prio37_we;
236 logic [1:0] prio37_qs;
237 logic [1:0] prio37_wd;
238 logic prio38_we;
239 logic [1:0] prio38_qs;
240 logic [1:0] prio38_wd;
241 logic prio39_we;
242 logic [1:0] prio39_qs;
243 logic [1:0] prio39_wd;
244 logic prio40_we;
245 logic [1:0] prio40_qs;
246 logic [1:0] prio40_wd;
247 logic prio41_we;
248 logic [1:0] prio41_qs;
249 logic [1:0] prio41_wd;
250 logic prio42_we;
251 logic [1:0] prio42_qs;
252 logic [1:0] prio42_wd;
253 logic prio43_we;
254 logic [1:0] prio43_qs;
255 logic [1:0] prio43_wd;
256 logic prio44_we;
257 logic [1:0] prio44_qs;
258 logic [1:0] prio44_wd;
259 logic prio45_we;
260 logic [1:0] prio45_qs;
261 logic [1:0] prio45_wd;
262 logic prio46_we;
263 logic [1:0] prio46_qs;
264 logic [1:0] prio46_wd;
265 logic prio47_we;
266 logic [1:0] prio47_qs;
267 logic [1:0] prio47_wd;
268 logic prio48_we;
269 logic [1:0] prio48_qs;
270 logic [1:0] prio48_wd;
271 logic prio49_we;
272 logic [1:0] prio49_qs;
273 logic [1:0] prio49_wd;
274 logic prio50_we;
275 logic [1:0] prio50_qs;
276 logic [1:0] prio50_wd;
277 logic prio51_we;
278 logic [1:0] prio51_qs;
279 logic [1:0] prio51_wd;
280 logic prio52_we;
281 logic [1:0] prio52_qs;
282 logic [1:0] prio52_wd;
283 logic prio53_we;
284 logic [1:0] prio53_qs;
285 logic [1:0] prio53_wd;
286 logic prio54_we;
287 logic [1:0] prio54_qs;
288 logic [1:0] prio54_wd;
289 logic prio55_we;
290 logic [1:0] prio55_qs;
291 logic [1:0] prio55_wd;
292 logic prio56_we;
293 logic [1:0] prio56_qs;
294 logic [1:0] prio56_wd;
295 logic prio57_we;
296 logic [1:0] prio57_qs;
297 logic [1:0] prio57_wd;
298 logic prio58_we;
299 logic [1:0] prio58_qs;
300 logic [1:0] prio58_wd;
301 logic prio59_we;
302 logic [1:0] prio59_qs;
303 logic [1:0] prio59_wd;
304 logic prio60_we;
305 logic [1:0] prio60_qs;
306 logic [1:0] prio60_wd;
307 logic prio61_we;
308 logic [1:0] prio61_qs;
309 logic [1:0] prio61_wd;
310 logic prio62_we;
311 logic [1:0] prio62_qs;
312 logic [1:0] prio62_wd;
313 logic prio63_we;
314 logic [1:0] prio63_qs;
315 logic [1:0] prio63_wd;
316 logic prio64_we;
317 logic [1:0] prio64_qs;
318 logic [1:0] prio64_wd;
319 logic prio65_we;
320 logic [1:0] prio65_qs;
321 logic [1:0] prio65_wd;
322 logic prio66_we;
323 logic [1:0] prio66_qs;
324 logic [1:0] prio66_wd;
325 logic prio67_we;
326 logic [1:0] prio67_qs;
327 logic [1:0] prio67_wd;
328 logic prio68_we;
329 logic [1:0] prio68_qs;
330 logic [1:0] prio68_wd;
331 logic prio69_we;
332 logic [1:0] prio69_qs;
333 logic [1:0] prio69_wd;
334 logic prio70_we;
335 logic [1:0] prio70_qs;
336 logic [1:0] prio70_wd;
337 logic prio71_we;
338 logic [1:0] prio71_qs;
339 logic [1:0] prio71_wd;
340 logic prio72_we;
341 logic [1:0] prio72_qs;
342 logic [1:0] prio72_wd;
343 logic prio73_we;
344 logic [1:0] prio73_qs;
345 logic [1:0] prio73_wd;
346 logic prio74_we;
347 logic [1:0] prio74_qs;
348 logic [1:0] prio74_wd;
349 logic prio75_we;
350 logic [1:0] prio75_qs;
351 logic [1:0] prio75_wd;
352 logic prio76_we;
353 logic [1:0] prio76_qs;
354 logic [1:0] prio76_wd;
355 logic prio77_we;
356 logic [1:0] prio77_qs;
357 logic [1:0] prio77_wd;
358 logic prio78_we;
359 logic [1:0] prio78_qs;
360 logic [1:0] prio78_wd;
361 logic prio79_we;
362 logic [1:0] prio79_qs;
363 logic [1:0] prio79_wd;
364 logic prio80_we;
365 logic [1:0] prio80_qs;
366 logic [1:0] prio80_wd;
367 logic prio81_we;
368 logic [1:0] prio81_qs;
369 logic [1:0] prio81_wd;
370 logic prio82_we;
371 logic [1:0] prio82_qs;
372 logic [1:0] prio82_wd;
373 logic prio83_we;
374 logic [1:0] prio83_qs;
375 logic [1:0] prio83_wd;
376 logic prio84_we;
377 logic [1:0] prio84_qs;
378 logic [1:0] prio84_wd;
379 logic prio85_we;
380 logic [1:0] prio85_qs;
381 logic [1:0] prio85_wd;
382 logic prio86_we;
383 logic [1:0] prio86_qs;
384 logic [1:0] prio86_wd;
385 logic prio87_we;
386 logic [1:0] prio87_qs;
387 logic [1:0] prio87_wd;
388 logic prio88_we;
389 logic [1:0] prio88_qs;
390 logic [1:0] prio88_wd;
391 logic prio89_we;
392 logic [1:0] prio89_qs;
393 logic [1:0] prio89_wd;
394 logic prio90_we;
395 logic [1:0] prio90_qs;
396 logic [1:0] prio90_wd;
397 logic prio91_we;
398 logic [1:0] prio91_qs;
399 logic [1:0] prio91_wd;
400 logic prio92_we;
401 logic [1:0] prio92_qs;
402 logic [1:0] prio92_wd;
403 logic prio93_we;
404 logic [1:0] prio93_qs;
405 logic [1:0] prio93_wd;
406 logic prio94_we;
407 logic [1:0] prio94_qs;
408 logic [1:0] prio94_wd;
409 logic prio95_we;
410 logic [1:0] prio95_qs;
411 logic [1:0] prio95_wd;
412 logic prio96_we;
413 logic [1:0] prio96_qs;
414 logic [1:0] prio96_wd;
415 logic prio97_we;
416 logic [1:0] prio97_qs;
417 logic [1:0] prio97_wd;
418 logic prio98_we;
419 logic [1:0] prio98_qs;
420 logic [1:0] prio98_wd;
421 logic prio99_we;
422 logic [1:0] prio99_qs;
423 logic [1:0] prio99_wd;
424 logic prio100_we;
425 logic [1:0] prio100_qs;
426 logic [1:0] prio100_wd;
427 logic prio101_we;
428 logic [1:0] prio101_qs;
429 logic [1:0] prio101_wd;
430 logic prio102_we;
431 logic [1:0] prio102_qs;
432 logic [1:0] prio102_wd;
433 logic prio103_we;
434 logic [1:0] prio103_qs;
435 logic [1:0] prio103_wd;
436 logic prio104_we;
437 logic [1:0] prio104_qs;
438 logic [1:0] prio104_wd;
439 logic prio105_we;
440 logic [1:0] prio105_qs;
441 logic [1:0] prio105_wd;
442 logic prio106_we;
443 logic [1:0] prio106_qs;
444 logic [1:0] prio106_wd;
445 logic prio107_we;
446 logic [1:0] prio107_qs;
447 logic [1:0] prio107_wd;
448 logic prio108_we;
449 logic [1:0] prio108_qs;
450 logic [1:0] prio108_wd;
451 logic prio109_we;
452 logic [1:0] prio109_qs;
453 logic [1:0] prio109_wd;
454 logic prio110_we;
455 logic [1:0] prio110_qs;
456 logic [1:0] prio110_wd;
457 logic prio111_we;
458 logic [1:0] prio111_qs;
459 logic [1:0] prio111_wd;
460 logic prio112_we;
461 logic [1:0] prio112_qs;
462 logic [1:0] prio112_wd;
463 logic prio113_we;
464 logic [1:0] prio113_qs;
465 logic [1:0] prio113_wd;
466 logic prio114_we;
467 logic [1:0] prio114_qs;
468 logic [1:0] prio114_wd;
469 logic prio115_we;
470 logic [1:0] prio115_qs;
471 logic [1:0] prio115_wd;
472 logic prio116_we;
473 logic [1:0] prio116_qs;
474 logic [1:0] prio116_wd;
475 logic prio117_we;
476 logic [1:0] prio117_qs;
477 logic [1:0] prio117_wd;
478 logic prio118_we;
479 logic [1:0] prio118_qs;
480 logic [1:0] prio118_wd;
481 logic prio119_we;
482 logic [1:0] prio119_qs;
483 logic [1:0] prio119_wd;
484 logic prio120_we;
485 logic [1:0] prio120_qs;
486 logic [1:0] prio120_wd;
487 logic prio121_we;
488 logic [1:0] prio121_qs;
489 logic [1:0] prio121_wd;
490 logic prio122_we;
491 logic [1:0] prio122_qs;
492 logic [1:0] prio122_wd;
493 logic prio123_we;
494 logic [1:0] prio123_qs;
495 logic [1:0] prio123_wd;
496 logic prio124_we;
497 logic [1:0] prio124_qs;
498 logic [1:0] prio124_wd;
499 logic prio125_we;
500 logic [1:0] prio125_qs;
501 logic [1:0] prio125_wd;
502 logic prio126_we;
503 logic [1:0] prio126_qs;
504 logic [1:0] prio126_wd;
505 logic prio127_we;
506 logic [1:0] prio127_qs;
507 logic [1:0] prio127_wd;
508 logic prio128_we;
509 logic [1:0] prio128_qs;
510 logic [1:0] prio128_wd;
511 logic prio129_we;
512 logic [1:0] prio129_qs;
513 logic [1:0] prio129_wd;
514 logic prio130_we;
515 logic [1:0] prio130_qs;
516 logic [1:0] prio130_wd;
517 logic prio131_we;
518 logic [1:0] prio131_qs;
519 logic [1:0] prio131_wd;
520 logic prio132_we;
521 logic [1:0] prio132_qs;
522 logic [1:0] prio132_wd;
523 logic prio133_we;
524 logic [1:0] prio133_qs;
525 logic [1:0] prio133_wd;
526 logic prio134_we;
527 logic [1:0] prio134_qs;
528 logic [1:0] prio134_wd;
529 logic prio135_we;
530 logic [1:0] prio135_qs;
531 logic [1:0] prio135_wd;
532 logic prio136_we;
533 logic [1:0] prio136_qs;
534 logic [1:0] prio136_wd;
535 logic prio137_we;
536 logic [1:0] prio137_qs;
537 logic [1:0] prio137_wd;
538 logic prio138_we;
539 logic [1:0] prio138_qs;
540 logic [1:0] prio138_wd;
541 logic prio139_we;
542 logic [1:0] prio139_qs;
543 logic [1:0] prio139_wd;
544 logic prio140_we;
545 logic [1:0] prio140_qs;
546 logic [1:0] prio140_wd;
547 logic prio141_we;
548 logic [1:0] prio141_qs;
549 logic [1:0] prio141_wd;
550 logic prio142_we;
551 logic [1:0] prio142_qs;
552 logic [1:0] prio142_wd;
553 logic prio143_we;
554 logic [1:0] prio143_qs;
555 logic [1:0] prio143_wd;
556 logic prio144_we;
557 logic [1:0] prio144_qs;
558 logic [1:0] prio144_wd;
559 logic prio145_we;
560 logic [1:0] prio145_qs;
561 logic [1:0] prio145_wd;
562 logic prio146_we;
563 logic [1:0] prio146_qs;
564 logic [1:0] prio146_wd;
565 logic prio147_we;
566 logic [1:0] prio147_qs;
567 logic [1:0] prio147_wd;
568 logic prio148_we;
569 logic [1:0] prio148_qs;
570 logic [1:0] prio148_wd;
571 logic prio149_we;
572 logic [1:0] prio149_qs;
573 logic [1:0] prio149_wd;
574 logic prio150_we;
575 logic [1:0] prio150_qs;
576 logic [1:0] prio150_wd;
577 logic prio151_we;
578 logic [1:0] prio151_qs;
579 logic [1:0] prio151_wd;
580 logic prio152_we;
581 logic [1:0] prio152_qs;
582 logic [1:0] prio152_wd;
583 logic prio153_we;
584 logic [1:0] prio153_qs;
585 logic [1:0] prio153_wd;
586 logic prio154_we;
587 logic [1:0] prio154_qs;
588 logic [1:0] prio154_wd;
589 logic prio155_we;
590 logic [1:0] prio155_qs;
591 logic [1:0] prio155_wd;
592 logic prio156_we;
593 logic [1:0] prio156_qs;
594 logic [1:0] prio156_wd;
595 logic prio157_we;
596 logic [1:0] prio157_qs;
597 logic [1:0] prio157_wd;
598 logic prio158_we;
599 logic [1:0] prio158_qs;
600 logic [1:0] prio158_wd;
601 logic prio159_we;
602 logic [1:0] prio159_qs;
603 logic [1:0] prio159_wd;
604 logic prio160_we;
605 logic [1:0] prio160_qs;
606 logic [1:0] prio160_wd;
607 logic prio161_we;
608 logic [1:0] prio161_qs;
609 logic [1:0] prio161_wd;
610 logic prio162_we;
611 logic [1:0] prio162_qs;
612 logic [1:0] prio162_wd;
613 logic prio163_we;
614 logic [1:0] prio163_qs;
615 logic [1:0] prio163_wd;
616 logic prio164_we;
617 logic [1:0] prio164_qs;
618 logic [1:0] prio164_wd;
619 logic prio165_we;
620 logic [1:0] prio165_qs;
621 logic [1:0] prio165_wd;
622 logic prio166_we;
623 logic [1:0] prio166_qs;
624 logic [1:0] prio166_wd;
625 logic prio167_we;
626 logic [1:0] prio167_qs;
627 logic [1:0] prio167_wd;
628 logic prio168_we;
629 logic [1:0] prio168_qs;
630 logic [1:0] prio168_wd;
631 logic prio169_we;
632 logic [1:0] prio169_qs;
633 logic [1:0] prio169_wd;
634 logic prio170_we;
635 logic [1:0] prio170_qs;
636 logic [1:0] prio170_wd;
637 logic prio171_we;
638 logic [1:0] prio171_qs;
639 logic [1:0] prio171_wd;
640 logic prio172_we;
641 logic [1:0] prio172_qs;
642 logic [1:0] prio172_wd;
643 logic prio173_we;
644 logic [1:0] prio173_qs;
645 logic [1:0] prio173_wd;
646 logic prio174_we;
647 logic [1:0] prio174_qs;
648 logic [1:0] prio174_wd;
649 logic prio175_we;
650 logic [1:0] prio175_qs;
651 logic [1:0] prio175_wd;
652 logic prio176_we;
653 logic [1:0] prio176_qs;
654 logic [1:0] prio176_wd;
655 logic prio177_we;
656 logic [1:0] prio177_qs;
657 logic [1:0] prio177_wd;
658 logic prio178_we;
659 logic [1:0] prio178_qs;
660 logic [1:0] prio178_wd;
661 logic prio179_we;
662 logic [1:0] prio179_qs;
663 logic [1:0] prio179_wd;
664 logic prio180_we;
665 logic [1:0] prio180_qs;
666 logic [1:0] prio180_wd;
667 logic prio181_we;
668 logic [1:0] prio181_qs;
669 logic [1:0] prio181_wd;
670 logic prio182_we;
671 logic [1:0] prio182_qs;
672 logic [1:0] prio182_wd;
673 logic prio183_we;
674 logic [1:0] prio183_qs;
675 logic [1:0] prio183_wd;
676 logic prio184_we;
677 logic [1:0] prio184_qs;
678 logic [1:0] prio184_wd;
679 logic prio185_we;
680 logic [1:0] prio185_qs;
681 logic [1:0] prio185_wd;
682 logic ip_0_p_0_qs;
683 logic ip_0_p_1_qs;
684 logic ip_0_p_2_qs;
685 logic ip_0_p_3_qs;
686 logic ip_0_p_4_qs;
687 logic ip_0_p_5_qs;
688 logic ip_0_p_6_qs;
689 logic ip_0_p_7_qs;
690 logic ip_0_p_8_qs;
691 logic ip_0_p_9_qs;
692 logic ip_0_p_10_qs;
693 logic ip_0_p_11_qs;
694 logic ip_0_p_12_qs;
695 logic ip_0_p_13_qs;
696 logic ip_0_p_14_qs;
697 logic ip_0_p_15_qs;
698 logic ip_0_p_16_qs;
699 logic ip_0_p_17_qs;
700 logic ip_0_p_18_qs;
701 logic ip_0_p_19_qs;
702 logic ip_0_p_20_qs;
703 logic ip_0_p_21_qs;
704 logic ip_0_p_22_qs;
705 logic ip_0_p_23_qs;
706 logic ip_0_p_24_qs;
707 logic ip_0_p_25_qs;
708 logic ip_0_p_26_qs;
709 logic ip_0_p_27_qs;
710 logic ip_0_p_28_qs;
711 logic ip_0_p_29_qs;
712 logic ip_0_p_30_qs;
713 logic ip_0_p_31_qs;
714 logic ip_1_p_32_qs;
715 logic ip_1_p_33_qs;
716 logic ip_1_p_34_qs;
717 logic ip_1_p_35_qs;
718 logic ip_1_p_36_qs;
719 logic ip_1_p_37_qs;
720 logic ip_1_p_38_qs;
721 logic ip_1_p_39_qs;
722 logic ip_1_p_40_qs;
723 logic ip_1_p_41_qs;
724 logic ip_1_p_42_qs;
725 logic ip_1_p_43_qs;
726 logic ip_1_p_44_qs;
727 logic ip_1_p_45_qs;
728 logic ip_1_p_46_qs;
729 logic ip_1_p_47_qs;
730 logic ip_1_p_48_qs;
731 logic ip_1_p_49_qs;
732 logic ip_1_p_50_qs;
733 logic ip_1_p_51_qs;
734 logic ip_1_p_52_qs;
735 logic ip_1_p_53_qs;
736 logic ip_1_p_54_qs;
737 logic ip_1_p_55_qs;
738 logic ip_1_p_56_qs;
739 logic ip_1_p_57_qs;
740 logic ip_1_p_58_qs;
741 logic ip_1_p_59_qs;
742 logic ip_1_p_60_qs;
743 logic ip_1_p_61_qs;
744 logic ip_1_p_62_qs;
745 logic ip_1_p_63_qs;
746 logic ip_2_p_64_qs;
747 logic ip_2_p_65_qs;
748 logic ip_2_p_66_qs;
749 logic ip_2_p_67_qs;
750 logic ip_2_p_68_qs;
751 logic ip_2_p_69_qs;
752 logic ip_2_p_70_qs;
753 logic ip_2_p_71_qs;
754 logic ip_2_p_72_qs;
755 logic ip_2_p_73_qs;
756 logic ip_2_p_74_qs;
757 logic ip_2_p_75_qs;
758 logic ip_2_p_76_qs;
759 logic ip_2_p_77_qs;
760 logic ip_2_p_78_qs;
761 logic ip_2_p_79_qs;
762 logic ip_2_p_80_qs;
763 logic ip_2_p_81_qs;
764 logic ip_2_p_82_qs;
765 logic ip_2_p_83_qs;
766 logic ip_2_p_84_qs;
767 logic ip_2_p_85_qs;
768 logic ip_2_p_86_qs;
769 logic ip_2_p_87_qs;
770 logic ip_2_p_88_qs;
771 logic ip_2_p_89_qs;
772 logic ip_2_p_90_qs;
773 logic ip_2_p_91_qs;
774 logic ip_2_p_92_qs;
775 logic ip_2_p_93_qs;
776 logic ip_2_p_94_qs;
777 logic ip_2_p_95_qs;
778 logic ip_3_p_96_qs;
779 logic ip_3_p_97_qs;
780 logic ip_3_p_98_qs;
781 logic ip_3_p_99_qs;
782 logic ip_3_p_100_qs;
783 logic ip_3_p_101_qs;
784 logic ip_3_p_102_qs;
785 logic ip_3_p_103_qs;
786 logic ip_3_p_104_qs;
787 logic ip_3_p_105_qs;
788 logic ip_3_p_106_qs;
789 logic ip_3_p_107_qs;
790 logic ip_3_p_108_qs;
791 logic ip_3_p_109_qs;
792 logic ip_3_p_110_qs;
793 logic ip_3_p_111_qs;
794 logic ip_3_p_112_qs;
795 logic ip_3_p_113_qs;
796 logic ip_3_p_114_qs;
797 logic ip_3_p_115_qs;
798 logic ip_3_p_116_qs;
799 logic ip_3_p_117_qs;
800 logic ip_3_p_118_qs;
801 logic ip_3_p_119_qs;
802 logic ip_3_p_120_qs;
803 logic ip_3_p_121_qs;
804 logic ip_3_p_122_qs;
805 logic ip_3_p_123_qs;
806 logic ip_3_p_124_qs;
807 logic ip_3_p_125_qs;
808 logic ip_3_p_126_qs;
809 logic ip_3_p_127_qs;
810 logic ip_4_p_128_qs;
811 logic ip_4_p_129_qs;
812 logic ip_4_p_130_qs;
813 logic ip_4_p_131_qs;
814 logic ip_4_p_132_qs;
815 logic ip_4_p_133_qs;
816 logic ip_4_p_134_qs;
817 logic ip_4_p_135_qs;
818 logic ip_4_p_136_qs;
819 logic ip_4_p_137_qs;
820 logic ip_4_p_138_qs;
821 logic ip_4_p_139_qs;
822 logic ip_4_p_140_qs;
823 logic ip_4_p_141_qs;
824 logic ip_4_p_142_qs;
825 logic ip_4_p_143_qs;
826 logic ip_4_p_144_qs;
827 logic ip_4_p_145_qs;
828 logic ip_4_p_146_qs;
829 logic ip_4_p_147_qs;
830 logic ip_4_p_148_qs;
831 logic ip_4_p_149_qs;
832 logic ip_4_p_150_qs;
833 logic ip_4_p_151_qs;
834 logic ip_4_p_152_qs;
835 logic ip_4_p_153_qs;
836 logic ip_4_p_154_qs;
837 logic ip_4_p_155_qs;
838 logic ip_4_p_156_qs;
839 logic ip_4_p_157_qs;
840 logic ip_4_p_158_qs;
841 logic ip_4_p_159_qs;
842 logic ip_5_p_160_qs;
843 logic ip_5_p_161_qs;
844 logic ip_5_p_162_qs;
845 logic ip_5_p_163_qs;
846 logic ip_5_p_164_qs;
847 logic ip_5_p_165_qs;
848 logic ip_5_p_166_qs;
849 logic ip_5_p_167_qs;
850 logic ip_5_p_168_qs;
851 logic ip_5_p_169_qs;
852 logic ip_5_p_170_qs;
853 logic ip_5_p_171_qs;
854 logic ip_5_p_172_qs;
855 logic ip_5_p_173_qs;
856 logic ip_5_p_174_qs;
857 logic ip_5_p_175_qs;
858 logic ip_5_p_176_qs;
859 logic ip_5_p_177_qs;
860 logic ip_5_p_178_qs;
861 logic ip_5_p_179_qs;
862 logic ip_5_p_180_qs;
863 logic ip_5_p_181_qs;
864 logic ip_5_p_182_qs;
865 logic ip_5_p_183_qs;
866 logic ip_5_p_184_qs;
867 logic ip_5_p_185_qs;
868 logic ie0_0_we;
869 logic ie0_0_e_0_qs;
870 logic ie0_0_e_0_wd;
871 logic ie0_0_e_1_qs;
872 logic ie0_0_e_1_wd;
873 logic ie0_0_e_2_qs;
874 logic ie0_0_e_2_wd;
875 logic ie0_0_e_3_qs;
876 logic ie0_0_e_3_wd;
877 logic ie0_0_e_4_qs;
878 logic ie0_0_e_4_wd;
879 logic ie0_0_e_5_qs;
880 logic ie0_0_e_5_wd;
881 logic ie0_0_e_6_qs;
882 logic ie0_0_e_6_wd;
883 logic ie0_0_e_7_qs;
884 logic ie0_0_e_7_wd;
885 logic ie0_0_e_8_qs;
886 logic ie0_0_e_8_wd;
887 logic ie0_0_e_9_qs;
888 logic ie0_0_e_9_wd;
889 logic ie0_0_e_10_qs;
890 logic ie0_0_e_10_wd;
891 logic ie0_0_e_11_qs;
892 logic ie0_0_e_11_wd;
893 logic ie0_0_e_12_qs;
894 logic ie0_0_e_12_wd;
895 logic ie0_0_e_13_qs;
896 logic ie0_0_e_13_wd;
897 logic ie0_0_e_14_qs;
898 logic ie0_0_e_14_wd;
899 logic ie0_0_e_15_qs;
900 logic ie0_0_e_15_wd;
901 logic ie0_0_e_16_qs;
902 logic ie0_0_e_16_wd;
903 logic ie0_0_e_17_qs;
904 logic ie0_0_e_17_wd;
905 logic ie0_0_e_18_qs;
906 logic ie0_0_e_18_wd;
907 logic ie0_0_e_19_qs;
908 logic ie0_0_e_19_wd;
909 logic ie0_0_e_20_qs;
910 logic ie0_0_e_20_wd;
911 logic ie0_0_e_21_qs;
912 logic ie0_0_e_21_wd;
913 logic ie0_0_e_22_qs;
914 logic ie0_0_e_22_wd;
915 logic ie0_0_e_23_qs;
916 logic ie0_0_e_23_wd;
917 logic ie0_0_e_24_qs;
918 logic ie0_0_e_24_wd;
919 logic ie0_0_e_25_qs;
920 logic ie0_0_e_25_wd;
921 logic ie0_0_e_26_qs;
922 logic ie0_0_e_26_wd;
923 logic ie0_0_e_27_qs;
924 logic ie0_0_e_27_wd;
925 logic ie0_0_e_28_qs;
926 logic ie0_0_e_28_wd;
927 logic ie0_0_e_29_qs;
928 logic ie0_0_e_29_wd;
929 logic ie0_0_e_30_qs;
930 logic ie0_0_e_30_wd;
931 logic ie0_0_e_31_qs;
932 logic ie0_0_e_31_wd;
933 logic ie0_1_we;
934 logic ie0_1_e_32_qs;
935 logic ie0_1_e_32_wd;
936 logic ie0_1_e_33_qs;
937 logic ie0_1_e_33_wd;
938 logic ie0_1_e_34_qs;
939 logic ie0_1_e_34_wd;
940 logic ie0_1_e_35_qs;
941 logic ie0_1_e_35_wd;
942 logic ie0_1_e_36_qs;
943 logic ie0_1_e_36_wd;
944 logic ie0_1_e_37_qs;
945 logic ie0_1_e_37_wd;
946 logic ie0_1_e_38_qs;
947 logic ie0_1_e_38_wd;
948 logic ie0_1_e_39_qs;
949 logic ie0_1_e_39_wd;
950 logic ie0_1_e_40_qs;
951 logic ie0_1_e_40_wd;
952 logic ie0_1_e_41_qs;
953 logic ie0_1_e_41_wd;
954 logic ie0_1_e_42_qs;
955 logic ie0_1_e_42_wd;
956 logic ie0_1_e_43_qs;
957 logic ie0_1_e_43_wd;
958 logic ie0_1_e_44_qs;
959 logic ie0_1_e_44_wd;
960 logic ie0_1_e_45_qs;
961 logic ie0_1_e_45_wd;
962 logic ie0_1_e_46_qs;
963 logic ie0_1_e_46_wd;
964 logic ie0_1_e_47_qs;
965 logic ie0_1_e_47_wd;
966 logic ie0_1_e_48_qs;
967 logic ie0_1_e_48_wd;
968 logic ie0_1_e_49_qs;
969 logic ie0_1_e_49_wd;
970 logic ie0_1_e_50_qs;
971 logic ie0_1_e_50_wd;
972 logic ie0_1_e_51_qs;
973 logic ie0_1_e_51_wd;
974 logic ie0_1_e_52_qs;
975 logic ie0_1_e_52_wd;
976 logic ie0_1_e_53_qs;
977 logic ie0_1_e_53_wd;
978 logic ie0_1_e_54_qs;
979 logic ie0_1_e_54_wd;
980 logic ie0_1_e_55_qs;
981 logic ie0_1_e_55_wd;
982 logic ie0_1_e_56_qs;
983 logic ie0_1_e_56_wd;
984 logic ie0_1_e_57_qs;
985 logic ie0_1_e_57_wd;
986 logic ie0_1_e_58_qs;
987 logic ie0_1_e_58_wd;
988 logic ie0_1_e_59_qs;
989 logic ie0_1_e_59_wd;
990 logic ie0_1_e_60_qs;
991 logic ie0_1_e_60_wd;
992 logic ie0_1_e_61_qs;
993 logic ie0_1_e_61_wd;
994 logic ie0_1_e_62_qs;
995 logic ie0_1_e_62_wd;
996 logic ie0_1_e_63_qs;
997 logic ie0_1_e_63_wd;
998 logic ie0_2_we;
999 logic ie0_2_e_64_qs;
1000 logic ie0_2_e_64_wd;
1001 logic ie0_2_e_65_qs;
1002 logic ie0_2_e_65_wd;
1003 logic ie0_2_e_66_qs;
1004 logic ie0_2_e_66_wd;
1005 logic ie0_2_e_67_qs;
1006 logic ie0_2_e_67_wd;
1007 logic ie0_2_e_68_qs;
1008 logic ie0_2_e_68_wd;
1009 logic ie0_2_e_69_qs;
1010 logic ie0_2_e_69_wd;
1011 logic ie0_2_e_70_qs;
1012 logic ie0_2_e_70_wd;
1013 logic ie0_2_e_71_qs;
1014 logic ie0_2_e_71_wd;
1015 logic ie0_2_e_72_qs;
1016 logic ie0_2_e_72_wd;
1017 logic ie0_2_e_73_qs;
1018 logic ie0_2_e_73_wd;
1019 logic ie0_2_e_74_qs;
1020 logic ie0_2_e_74_wd;
1021 logic ie0_2_e_75_qs;
1022 logic ie0_2_e_75_wd;
1023 logic ie0_2_e_76_qs;
1024 logic ie0_2_e_76_wd;
1025 logic ie0_2_e_77_qs;
1026 logic ie0_2_e_77_wd;
1027 logic ie0_2_e_78_qs;
1028 logic ie0_2_e_78_wd;
1029 logic ie0_2_e_79_qs;
1030 logic ie0_2_e_79_wd;
1031 logic ie0_2_e_80_qs;
1032 logic ie0_2_e_80_wd;
1033 logic ie0_2_e_81_qs;
1034 logic ie0_2_e_81_wd;
1035 logic ie0_2_e_82_qs;
1036 logic ie0_2_e_82_wd;
1037 logic ie0_2_e_83_qs;
1038 logic ie0_2_e_83_wd;
1039 logic ie0_2_e_84_qs;
1040 logic ie0_2_e_84_wd;
1041 logic ie0_2_e_85_qs;
1042 logic ie0_2_e_85_wd;
1043 logic ie0_2_e_86_qs;
1044 logic ie0_2_e_86_wd;
1045 logic ie0_2_e_87_qs;
1046 logic ie0_2_e_87_wd;
1047 logic ie0_2_e_88_qs;
1048 logic ie0_2_e_88_wd;
1049 logic ie0_2_e_89_qs;
1050 logic ie0_2_e_89_wd;
1051 logic ie0_2_e_90_qs;
1052 logic ie0_2_e_90_wd;
1053 logic ie0_2_e_91_qs;
1054 logic ie0_2_e_91_wd;
1055 logic ie0_2_e_92_qs;
1056 logic ie0_2_e_92_wd;
1057 logic ie0_2_e_93_qs;
1058 logic ie0_2_e_93_wd;
1059 logic ie0_2_e_94_qs;
1060 logic ie0_2_e_94_wd;
1061 logic ie0_2_e_95_qs;
1062 logic ie0_2_e_95_wd;
1063 logic ie0_3_we;
1064 logic ie0_3_e_96_qs;
1065 logic ie0_3_e_96_wd;
1066 logic ie0_3_e_97_qs;
1067 logic ie0_3_e_97_wd;
1068 logic ie0_3_e_98_qs;
1069 logic ie0_3_e_98_wd;
1070 logic ie0_3_e_99_qs;
1071 logic ie0_3_e_99_wd;
1072 logic ie0_3_e_100_qs;
1073 logic ie0_3_e_100_wd;
1074 logic ie0_3_e_101_qs;
1075 logic ie0_3_e_101_wd;
1076 logic ie0_3_e_102_qs;
1077 logic ie0_3_e_102_wd;
1078 logic ie0_3_e_103_qs;
1079 logic ie0_3_e_103_wd;
1080 logic ie0_3_e_104_qs;
1081 logic ie0_3_e_104_wd;
1082 logic ie0_3_e_105_qs;
1083 logic ie0_3_e_105_wd;
1084 logic ie0_3_e_106_qs;
1085 logic ie0_3_e_106_wd;
1086 logic ie0_3_e_107_qs;
1087 logic ie0_3_e_107_wd;
1088 logic ie0_3_e_108_qs;
1089 logic ie0_3_e_108_wd;
1090 logic ie0_3_e_109_qs;
1091 logic ie0_3_e_109_wd;
1092 logic ie0_3_e_110_qs;
1093 logic ie0_3_e_110_wd;
1094 logic ie0_3_e_111_qs;
1095 logic ie0_3_e_111_wd;
1096 logic ie0_3_e_112_qs;
1097 logic ie0_3_e_112_wd;
1098 logic ie0_3_e_113_qs;
1099 logic ie0_3_e_113_wd;
1100 logic ie0_3_e_114_qs;
1101 logic ie0_3_e_114_wd;
1102 logic ie0_3_e_115_qs;
1103 logic ie0_3_e_115_wd;
1104 logic ie0_3_e_116_qs;
1105 logic ie0_3_e_116_wd;
1106 logic ie0_3_e_117_qs;
1107 logic ie0_3_e_117_wd;
1108 logic ie0_3_e_118_qs;
1109 logic ie0_3_e_118_wd;
1110 logic ie0_3_e_119_qs;
1111 logic ie0_3_e_119_wd;
1112 logic ie0_3_e_120_qs;
1113 logic ie0_3_e_120_wd;
1114 logic ie0_3_e_121_qs;
1115 logic ie0_3_e_121_wd;
1116 logic ie0_3_e_122_qs;
1117 logic ie0_3_e_122_wd;
1118 logic ie0_3_e_123_qs;
1119 logic ie0_3_e_123_wd;
1120 logic ie0_3_e_124_qs;
1121 logic ie0_3_e_124_wd;
1122 logic ie0_3_e_125_qs;
1123 logic ie0_3_e_125_wd;
1124 logic ie0_3_e_126_qs;
1125 logic ie0_3_e_126_wd;
1126 logic ie0_3_e_127_qs;
1127 logic ie0_3_e_127_wd;
1128 logic ie0_4_we;
1129 logic ie0_4_e_128_qs;
1130 logic ie0_4_e_128_wd;
1131 logic ie0_4_e_129_qs;
1132 logic ie0_4_e_129_wd;
1133 logic ie0_4_e_130_qs;
1134 logic ie0_4_e_130_wd;
1135 logic ie0_4_e_131_qs;
1136 logic ie0_4_e_131_wd;
1137 logic ie0_4_e_132_qs;
1138 logic ie0_4_e_132_wd;
1139 logic ie0_4_e_133_qs;
1140 logic ie0_4_e_133_wd;
1141 logic ie0_4_e_134_qs;
1142 logic ie0_4_e_134_wd;
1143 logic ie0_4_e_135_qs;
1144 logic ie0_4_e_135_wd;
1145 logic ie0_4_e_136_qs;
1146 logic ie0_4_e_136_wd;
1147 logic ie0_4_e_137_qs;
1148 logic ie0_4_e_137_wd;
1149 logic ie0_4_e_138_qs;
1150 logic ie0_4_e_138_wd;
1151 logic ie0_4_e_139_qs;
1152 logic ie0_4_e_139_wd;
1153 logic ie0_4_e_140_qs;
1154 logic ie0_4_e_140_wd;
1155 logic ie0_4_e_141_qs;
1156 logic ie0_4_e_141_wd;
1157 logic ie0_4_e_142_qs;
1158 logic ie0_4_e_142_wd;
1159 logic ie0_4_e_143_qs;
1160 logic ie0_4_e_143_wd;
1161 logic ie0_4_e_144_qs;
1162 logic ie0_4_e_144_wd;
1163 logic ie0_4_e_145_qs;
1164 logic ie0_4_e_145_wd;
1165 logic ie0_4_e_146_qs;
1166 logic ie0_4_e_146_wd;
1167 logic ie0_4_e_147_qs;
1168 logic ie0_4_e_147_wd;
1169 logic ie0_4_e_148_qs;
1170 logic ie0_4_e_148_wd;
1171 logic ie0_4_e_149_qs;
1172 logic ie0_4_e_149_wd;
1173 logic ie0_4_e_150_qs;
1174 logic ie0_4_e_150_wd;
1175 logic ie0_4_e_151_qs;
1176 logic ie0_4_e_151_wd;
1177 logic ie0_4_e_152_qs;
1178 logic ie0_4_e_152_wd;
1179 logic ie0_4_e_153_qs;
1180 logic ie0_4_e_153_wd;
1181 logic ie0_4_e_154_qs;
1182 logic ie0_4_e_154_wd;
1183 logic ie0_4_e_155_qs;
1184 logic ie0_4_e_155_wd;
1185 logic ie0_4_e_156_qs;
1186 logic ie0_4_e_156_wd;
1187 logic ie0_4_e_157_qs;
1188 logic ie0_4_e_157_wd;
1189 logic ie0_4_e_158_qs;
1190 logic ie0_4_e_158_wd;
1191 logic ie0_4_e_159_qs;
1192 logic ie0_4_e_159_wd;
1193 logic ie0_5_we;
1194 logic ie0_5_e_160_qs;
1195 logic ie0_5_e_160_wd;
1196 logic ie0_5_e_161_qs;
1197 logic ie0_5_e_161_wd;
1198 logic ie0_5_e_162_qs;
1199 logic ie0_5_e_162_wd;
1200 logic ie0_5_e_163_qs;
1201 logic ie0_5_e_163_wd;
1202 logic ie0_5_e_164_qs;
1203 logic ie0_5_e_164_wd;
1204 logic ie0_5_e_165_qs;
1205 logic ie0_5_e_165_wd;
1206 logic ie0_5_e_166_qs;
1207 logic ie0_5_e_166_wd;
1208 logic ie0_5_e_167_qs;
1209 logic ie0_5_e_167_wd;
1210 logic ie0_5_e_168_qs;
1211 logic ie0_5_e_168_wd;
1212 logic ie0_5_e_169_qs;
1213 logic ie0_5_e_169_wd;
1214 logic ie0_5_e_170_qs;
1215 logic ie0_5_e_170_wd;
1216 logic ie0_5_e_171_qs;
1217 logic ie0_5_e_171_wd;
1218 logic ie0_5_e_172_qs;
1219 logic ie0_5_e_172_wd;
1220 logic ie0_5_e_173_qs;
1221 logic ie0_5_e_173_wd;
1222 logic ie0_5_e_174_qs;
1223 logic ie0_5_e_174_wd;
1224 logic ie0_5_e_175_qs;
1225 logic ie0_5_e_175_wd;
1226 logic ie0_5_e_176_qs;
1227 logic ie0_5_e_176_wd;
1228 logic ie0_5_e_177_qs;
1229 logic ie0_5_e_177_wd;
1230 logic ie0_5_e_178_qs;
1231 logic ie0_5_e_178_wd;
1232 logic ie0_5_e_179_qs;
1233 logic ie0_5_e_179_wd;
1234 logic ie0_5_e_180_qs;
1235 logic ie0_5_e_180_wd;
1236 logic ie0_5_e_181_qs;
1237 logic ie0_5_e_181_wd;
1238 logic ie0_5_e_182_qs;
1239 logic ie0_5_e_182_wd;
1240 logic ie0_5_e_183_qs;
1241 logic ie0_5_e_183_wd;
1242 logic ie0_5_e_184_qs;
1243 logic ie0_5_e_184_wd;
1244 logic ie0_5_e_185_qs;
1245 logic ie0_5_e_185_wd;
1246 logic threshold0_we;
1247 logic [1:0] threshold0_qs;
1248 logic [1:0] threshold0_wd;
1249 logic cc0_re;
1250 logic cc0_we;
1251 logic [7:0] cc0_qs;
1252 logic [7:0] cc0_wd;
1253 logic msip0_we;
1254 logic msip0_qs;
1255 logic msip0_wd;
1256 logic alert_test_we;
1257 logic alert_test_wd;
1258
1259 // Register instances
1260 // R[prio0]: V(False)
1261 prim_subreg #(
1262 .DW (2),
1263 .SwAccess(prim_subreg_pkg::SwAccessRW),
1264 .RESVAL (2'h0),
1265 .Mubi (1'b0)
1266 ) u_prio0 (
1267 .clk_i (clk_i),
1268 .rst_ni (rst_ni),
1269
1270 // from register interface
1271 .we (prio0_we),
1272 .wd (prio0_wd),
1273
1274 // from internal hardware
1275 .de (1'b0),
1276 .d ('0),
1277
1278 // to internal hardware
1279 .qe (),
1280 .q (reg2hw.prio0.q),
1281 .ds (),
1282
1283 // to register interface (read)
1284 .qs (prio0_qs)
1285 );
1286
1287
1288 // R[prio1]: V(False)
1289 prim_subreg #(
1290 .DW (2),
1291 .SwAccess(prim_subreg_pkg::SwAccessRW),
1292 .RESVAL (2'h0),
1293 .Mubi (1'b0)
1294 ) u_prio1 (
1295 .clk_i (clk_i),
1296 .rst_ni (rst_ni),
1297
1298 // from register interface
1299 .we (prio1_we),
1300 .wd (prio1_wd),
1301
1302 // from internal hardware
1303 .de (1'b0),
1304 .d ('0),
1305
1306 // to internal hardware
1307 .qe (),
1308 .q (reg2hw.prio1.q),
1309 .ds (),
1310
1311 // to register interface (read)
1312 .qs (prio1_qs)
1313 );
1314
1315
1316 // R[prio2]: V(False)
1317 prim_subreg #(
1318 .DW (2),
1319 .SwAccess(prim_subreg_pkg::SwAccessRW),
1320 .RESVAL (2'h0),
1321 .Mubi (1'b0)
1322 ) u_prio2 (
1323 .clk_i (clk_i),
1324 .rst_ni (rst_ni),
1325
1326 // from register interface
1327 .we (prio2_we),
1328 .wd (prio2_wd),
1329
1330 // from internal hardware
1331 .de (1'b0),
1332 .d ('0),
1333
1334 // to internal hardware
1335 .qe (),
1336 .q (reg2hw.prio2.q),
1337 .ds (),
1338
1339 // to register interface (read)
1340 .qs (prio2_qs)
1341 );
1342
1343
1344 // R[prio3]: V(False)
1345 prim_subreg #(
1346 .DW (2),
1347 .SwAccess(prim_subreg_pkg::SwAccessRW),
1348 .RESVAL (2'h0),
1349 .Mubi (1'b0)
1350 ) u_prio3 (
1351 .clk_i (clk_i),
1352 .rst_ni (rst_ni),
1353
1354 // from register interface
1355 .we (prio3_we),
1356 .wd (prio3_wd),
1357
1358 // from internal hardware
1359 .de (1'b0),
1360 .d ('0),
1361
1362 // to internal hardware
1363 .qe (),
1364 .q (reg2hw.prio3.q),
1365 .ds (),
1366
1367 // to register interface (read)
1368 .qs (prio3_qs)
1369 );
1370
1371
1372 // R[prio4]: V(False)
1373 prim_subreg #(
1374 .DW (2),
1375 .SwAccess(prim_subreg_pkg::SwAccessRW),
1376 .RESVAL (2'h0),
1377 .Mubi (1'b0)
1378 ) u_prio4 (
1379 .clk_i (clk_i),
1380 .rst_ni (rst_ni),
1381
1382 // from register interface
1383 .we (prio4_we),
1384 .wd (prio4_wd),
1385
1386 // from internal hardware
1387 .de (1'b0),
1388 .d ('0),
1389
1390 // to internal hardware
1391 .qe (),
1392 .q (reg2hw.prio4.q),
1393 .ds (),
1394
1395 // to register interface (read)
1396 .qs (prio4_qs)
1397 );
1398
1399
1400 // R[prio5]: V(False)
1401 prim_subreg #(
1402 .DW (2),
1403 .SwAccess(prim_subreg_pkg::SwAccessRW),
1404 .RESVAL (2'h0),
1405 .Mubi (1'b0)
1406 ) u_prio5 (
1407 .clk_i (clk_i),
1408 .rst_ni (rst_ni),
1409
1410 // from register interface
1411 .we (prio5_we),
1412 .wd (prio5_wd),
1413
1414 // from internal hardware
1415 .de (1'b0),
1416 .d ('0),
1417
1418 // to internal hardware
1419 .qe (),
1420 .q (reg2hw.prio5.q),
1421 .ds (),
1422
1423 // to register interface (read)
1424 .qs (prio5_qs)
1425 );
1426
1427
1428 // R[prio6]: V(False)
1429 prim_subreg #(
1430 .DW (2),
1431 .SwAccess(prim_subreg_pkg::SwAccessRW),
1432 .RESVAL (2'h0),
1433 .Mubi (1'b0)
1434 ) u_prio6 (
1435 .clk_i (clk_i),
1436 .rst_ni (rst_ni),
1437
1438 // from register interface
1439 .we (prio6_we),
1440 .wd (prio6_wd),
1441
1442 // from internal hardware
1443 .de (1'b0),
1444 .d ('0),
1445
1446 // to internal hardware
1447 .qe (),
1448 .q (reg2hw.prio6.q),
1449 .ds (),
1450
1451 // to register interface (read)
1452 .qs (prio6_qs)
1453 );
1454
1455
1456 // R[prio7]: V(False)
1457 prim_subreg #(
1458 .DW (2),
1459 .SwAccess(prim_subreg_pkg::SwAccessRW),
1460 .RESVAL (2'h0),
1461 .Mubi (1'b0)
1462 ) u_prio7 (
1463 .clk_i (clk_i),
1464 .rst_ni (rst_ni),
1465
1466 // from register interface
1467 .we (prio7_we),
1468 .wd (prio7_wd),
1469
1470 // from internal hardware
1471 .de (1'b0),
1472 .d ('0),
1473
1474 // to internal hardware
1475 .qe (),
1476 .q (reg2hw.prio7.q),
1477 .ds (),
1478
1479 // to register interface (read)
1480 .qs (prio7_qs)
1481 );
1482
1483
1484 // R[prio8]: V(False)
1485 prim_subreg #(
1486 .DW (2),
1487 .SwAccess(prim_subreg_pkg::SwAccessRW),
1488 .RESVAL (2'h0),
1489 .Mubi (1'b0)
1490 ) u_prio8 (
1491 .clk_i (clk_i),
1492 .rst_ni (rst_ni),
1493
1494 // from register interface
1495 .we (prio8_we),
1496 .wd (prio8_wd),
1497
1498 // from internal hardware
1499 .de (1'b0),
1500 .d ('0),
1501
1502 // to internal hardware
1503 .qe (),
1504 .q (reg2hw.prio8.q),
1505 .ds (),
1506
1507 // to register interface (read)
1508 .qs (prio8_qs)
1509 );
1510
1511
1512 // R[prio9]: V(False)
1513 prim_subreg #(
1514 .DW (2),
1515 .SwAccess(prim_subreg_pkg::SwAccessRW),
1516 .RESVAL (2'h0),
1517 .Mubi (1'b0)
1518 ) u_prio9 (
1519 .clk_i (clk_i),
1520 .rst_ni (rst_ni),
1521
1522 // from register interface
1523 .we (prio9_we),
1524 .wd (prio9_wd),
1525
1526 // from internal hardware
1527 .de (1'b0),
1528 .d ('0),
1529
1530 // to internal hardware
1531 .qe (),
1532 .q (reg2hw.prio9.q),
1533 .ds (),
1534
1535 // to register interface (read)
1536 .qs (prio9_qs)
1537 );
1538
1539
1540 // R[prio10]: V(False)
1541 prim_subreg #(
1542 .DW (2),
1543 .SwAccess(prim_subreg_pkg::SwAccessRW),
1544 .RESVAL (2'h0),
1545 .Mubi (1'b0)
1546 ) u_prio10 (
1547 .clk_i (clk_i),
1548 .rst_ni (rst_ni),
1549
1550 // from register interface
1551 .we (prio10_we),
1552 .wd (prio10_wd),
1553
1554 // from internal hardware
1555 .de (1'b0),
1556 .d ('0),
1557
1558 // to internal hardware
1559 .qe (),
1560 .q (reg2hw.prio10.q),
1561 .ds (),
1562
1563 // to register interface (read)
1564 .qs (prio10_qs)
1565 );
1566
1567
1568 // R[prio11]: V(False)
1569 prim_subreg #(
1570 .DW (2),
1571 .SwAccess(prim_subreg_pkg::SwAccessRW),
1572 .RESVAL (2'h0),
1573 .Mubi (1'b0)
1574 ) u_prio11 (
1575 .clk_i (clk_i),
1576 .rst_ni (rst_ni),
1577
1578 // from register interface
1579 .we (prio11_we),
1580 .wd (prio11_wd),
1581
1582 // from internal hardware
1583 .de (1'b0),
1584 .d ('0),
1585
1586 // to internal hardware
1587 .qe (),
1588 .q (reg2hw.prio11.q),
1589 .ds (),
1590
1591 // to register interface (read)
1592 .qs (prio11_qs)
1593 );
1594
1595
1596 // R[prio12]: V(False)
1597 prim_subreg #(
1598 .DW (2),
1599 .SwAccess(prim_subreg_pkg::SwAccessRW),
1600 .RESVAL (2'h0),
1601 .Mubi (1'b0)
1602 ) u_prio12 (
1603 .clk_i (clk_i),
1604 .rst_ni (rst_ni),
1605
1606 // from register interface
1607 .we (prio12_we),
1608 .wd (prio12_wd),
1609
1610 // from internal hardware
1611 .de (1'b0),
1612 .d ('0),
1613
1614 // to internal hardware
1615 .qe (),
1616 .q (reg2hw.prio12.q),
1617 .ds (),
1618
1619 // to register interface (read)
1620 .qs (prio12_qs)
1621 );
1622
1623
1624 // R[prio13]: V(False)
1625 prim_subreg #(
1626 .DW (2),
1627 .SwAccess(prim_subreg_pkg::SwAccessRW),
1628 .RESVAL (2'h0),
1629 .Mubi (1'b0)
1630 ) u_prio13 (
1631 .clk_i (clk_i),
1632 .rst_ni (rst_ni),
1633
1634 // from register interface
1635 .we (prio13_we),
1636 .wd (prio13_wd),
1637
1638 // from internal hardware
1639 .de (1'b0),
1640 .d ('0),
1641
1642 // to internal hardware
1643 .qe (),
1644 .q (reg2hw.prio13.q),
1645 .ds (),
1646
1647 // to register interface (read)
1648 .qs (prio13_qs)
1649 );
1650
1651
1652 // R[prio14]: V(False)
1653 prim_subreg #(
1654 .DW (2),
1655 .SwAccess(prim_subreg_pkg::SwAccessRW),
1656 .RESVAL (2'h0),
1657 .Mubi (1'b0)
1658 ) u_prio14 (
1659 .clk_i (clk_i),
1660 .rst_ni (rst_ni),
1661
1662 // from register interface
1663 .we (prio14_we),
1664 .wd (prio14_wd),
1665
1666 // from internal hardware
1667 .de (1'b0),
1668 .d ('0),
1669
1670 // to internal hardware
1671 .qe (),
1672 .q (reg2hw.prio14.q),
1673 .ds (),
1674
1675 // to register interface (read)
1676 .qs (prio14_qs)
1677 );
1678
1679
1680 // R[prio15]: V(False)
1681 prim_subreg #(
1682 .DW (2),
1683 .SwAccess(prim_subreg_pkg::SwAccessRW),
1684 .RESVAL (2'h0),
1685 .Mubi (1'b0)
1686 ) u_prio15 (
1687 .clk_i (clk_i),
1688 .rst_ni (rst_ni),
1689
1690 // from register interface
1691 .we (prio15_we),
1692 .wd (prio15_wd),
1693
1694 // from internal hardware
1695 .de (1'b0),
1696 .d ('0),
1697
1698 // to internal hardware
1699 .qe (),
1700 .q (reg2hw.prio15.q),
1701 .ds (),
1702
1703 // to register interface (read)
1704 .qs (prio15_qs)
1705 );
1706
1707
1708 // R[prio16]: V(False)
1709 prim_subreg #(
1710 .DW (2),
1711 .SwAccess(prim_subreg_pkg::SwAccessRW),
1712 .RESVAL (2'h0),
1713 .Mubi (1'b0)
1714 ) u_prio16 (
1715 .clk_i (clk_i),
1716 .rst_ni (rst_ni),
1717
1718 // from register interface
1719 .we (prio16_we),
1720 .wd (prio16_wd),
1721
1722 // from internal hardware
1723 .de (1'b0),
1724 .d ('0),
1725
1726 // to internal hardware
1727 .qe (),
1728 .q (reg2hw.prio16.q),
1729 .ds (),
1730
1731 // to register interface (read)
1732 .qs (prio16_qs)
1733 );
1734
1735
1736 // R[prio17]: V(False)
1737 prim_subreg #(
1738 .DW (2),
1739 .SwAccess(prim_subreg_pkg::SwAccessRW),
1740 .RESVAL (2'h0),
1741 .Mubi (1'b0)
1742 ) u_prio17 (
1743 .clk_i (clk_i),
1744 .rst_ni (rst_ni),
1745
1746 // from register interface
1747 .we (prio17_we),
1748 .wd (prio17_wd),
1749
1750 // from internal hardware
1751 .de (1'b0),
1752 .d ('0),
1753
1754 // to internal hardware
1755 .qe (),
1756 .q (reg2hw.prio17.q),
1757 .ds (),
1758
1759 // to register interface (read)
1760 .qs (prio17_qs)
1761 );
1762
1763
1764 // R[prio18]: V(False)
1765 prim_subreg #(
1766 .DW (2),
1767 .SwAccess(prim_subreg_pkg::SwAccessRW),
1768 .RESVAL (2'h0),
1769 .Mubi (1'b0)
1770 ) u_prio18 (
1771 .clk_i (clk_i),
1772 .rst_ni (rst_ni),
1773
1774 // from register interface
1775 .we (prio18_we),
1776 .wd (prio18_wd),
1777
1778 // from internal hardware
1779 .de (1'b0),
1780 .d ('0),
1781
1782 // to internal hardware
1783 .qe (),
1784 .q (reg2hw.prio18.q),
1785 .ds (),
1786
1787 // to register interface (read)
1788 .qs (prio18_qs)
1789 );
1790
1791
1792 // R[prio19]: V(False)
1793 prim_subreg #(
1794 .DW (2),
1795 .SwAccess(prim_subreg_pkg::SwAccessRW),
1796 .RESVAL (2'h0),
1797 .Mubi (1'b0)
1798 ) u_prio19 (
1799 .clk_i (clk_i),
1800 .rst_ni (rst_ni),
1801
1802 // from register interface
1803 .we (prio19_we),
1804 .wd (prio19_wd),
1805
1806 // from internal hardware
1807 .de (1'b0),
1808 .d ('0),
1809
1810 // to internal hardware
1811 .qe (),
1812 .q (reg2hw.prio19.q),
1813 .ds (),
1814
1815 // to register interface (read)
1816 .qs (prio19_qs)
1817 );
1818
1819
1820 // R[prio20]: V(False)
1821 prim_subreg #(
1822 .DW (2),
1823 .SwAccess(prim_subreg_pkg::SwAccessRW),
1824 .RESVAL (2'h0),
1825 .Mubi (1'b0)
1826 ) u_prio20 (
1827 .clk_i (clk_i),
1828 .rst_ni (rst_ni),
1829
1830 // from register interface
1831 .we (prio20_we),
1832 .wd (prio20_wd),
1833
1834 // from internal hardware
1835 .de (1'b0),
1836 .d ('0),
1837
1838 // to internal hardware
1839 .qe (),
1840 .q (reg2hw.prio20.q),
1841 .ds (),
1842
1843 // to register interface (read)
1844 .qs (prio20_qs)
1845 );
1846
1847
1848 // R[prio21]: V(False)
1849 prim_subreg #(
1850 .DW (2),
1851 .SwAccess(prim_subreg_pkg::SwAccessRW),
1852 .RESVAL (2'h0),
1853 .Mubi (1'b0)
1854 ) u_prio21 (
1855 .clk_i (clk_i),
1856 .rst_ni (rst_ni),
1857
1858 // from register interface
1859 .we (prio21_we),
1860 .wd (prio21_wd),
1861
1862 // from internal hardware
1863 .de (1'b0),
1864 .d ('0),
1865
1866 // to internal hardware
1867 .qe (),
1868 .q (reg2hw.prio21.q),
1869 .ds (),
1870
1871 // to register interface (read)
1872 .qs (prio21_qs)
1873 );
1874
1875
1876 // R[prio22]: V(False)
1877 prim_subreg #(
1878 .DW (2),
1879 .SwAccess(prim_subreg_pkg::SwAccessRW),
1880 .RESVAL (2'h0),
1881 .Mubi (1'b0)
1882 ) u_prio22 (
1883 .clk_i (clk_i),
1884 .rst_ni (rst_ni),
1885
1886 // from register interface
1887 .we (prio22_we),
1888 .wd (prio22_wd),
1889
1890 // from internal hardware
1891 .de (1'b0),
1892 .d ('0),
1893
1894 // to internal hardware
1895 .qe (),
1896 .q (reg2hw.prio22.q),
1897 .ds (),
1898
1899 // to register interface (read)
1900 .qs (prio22_qs)
1901 );
1902
1903
1904 // R[prio23]: V(False)
1905 prim_subreg #(
1906 .DW (2),
1907 .SwAccess(prim_subreg_pkg::SwAccessRW),
1908 .RESVAL (2'h0),
1909 .Mubi (1'b0)
1910 ) u_prio23 (
1911 .clk_i (clk_i),
1912 .rst_ni (rst_ni),
1913
1914 // from register interface
1915 .we (prio23_we),
1916 .wd (prio23_wd),
1917
1918 // from internal hardware
1919 .de (1'b0),
1920 .d ('0),
1921
1922 // to internal hardware
1923 .qe (),
1924 .q (reg2hw.prio23.q),
1925 .ds (),
1926
1927 // to register interface (read)
1928 .qs (prio23_qs)
1929 );
1930
1931
1932 // R[prio24]: V(False)
1933 prim_subreg #(
1934 .DW (2),
1935 .SwAccess(prim_subreg_pkg::SwAccessRW),
1936 .RESVAL (2'h0),
1937 .Mubi (1'b0)
1938 ) u_prio24 (
1939 .clk_i (clk_i),
1940 .rst_ni (rst_ni),
1941
1942 // from register interface
1943 .we (prio24_we),
1944 .wd (prio24_wd),
1945
1946 // from internal hardware
1947 .de (1'b0),
1948 .d ('0),
1949
1950 // to internal hardware
1951 .qe (),
1952 .q (reg2hw.prio24.q),
1953 .ds (),
1954
1955 // to register interface (read)
1956 .qs (prio24_qs)
1957 );
1958
1959
1960 // R[prio25]: V(False)
1961 prim_subreg #(
1962 .DW (2),
1963 .SwAccess(prim_subreg_pkg::SwAccessRW),
1964 .RESVAL (2'h0),
1965 .Mubi (1'b0)
1966 ) u_prio25 (
1967 .clk_i (clk_i),
1968 .rst_ni (rst_ni),
1969
1970 // from register interface
1971 .we (prio25_we),
1972 .wd (prio25_wd),
1973
1974 // from internal hardware
1975 .de (1'b0),
1976 .d ('0),
1977
1978 // to internal hardware
1979 .qe (),
1980 .q (reg2hw.prio25.q),
1981 .ds (),
1982
1983 // to register interface (read)
1984 .qs (prio25_qs)
1985 );
1986
1987
1988 // R[prio26]: V(False)
1989 prim_subreg #(
1990 .DW (2),
1991 .SwAccess(prim_subreg_pkg::SwAccessRW),
1992 .RESVAL (2'h0),
1993 .Mubi (1'b0)
1994 ) u_prio26 (
1995 .clk_i (clk_i),
1996 .rst_ni (rst_ni),
1997
1998 // from register interface
1999 .we (prio26_we),
2000 .wd (prio26_wd),
2001
2002 // from internal hardware
2003 .de (1'b0),
2004 .d ('0),
2005
2006 // to internal hardware
2007 .qe (),
2008 .q (reg2hw.prio26.q),
2009 .ds (),
2010
2011 // to register interface (read)
2012 .qs (prio26_qs)
2013 );
2014
2015
2016 // R[prio27]: V(False)
2017 prim_subreg #(
2018 .DW (2),
2019 .SwAccess(prim_subreg_pkg::SwAccessRW),
2020 .RESVAL (2'h0),
2021 .Mubi (1'b0)
2022 ) u_prio27 (
2023 .clk_i (clk_i),
2024 .rst_ni (rst_ni),
2025
2026 // from register interface
2027 .we (prio27_we),
2028 .wd (prio27_wd),
2029
2030 // from internal hardware
2031 .de (1'b0),
2032 .d ('0),
2033
2034 // to internal hardware
2035 .qe (),
2036 .q (reg2hw.prio27.q),
2037 .ds (),
2038
2039 // to register interface (read)
2040 .qs (prio27_qs)
2041 );
2042
2043
2044 // R[prio28]: V(False)
2045 prim_subreg #(
2046 .DW (2),
2047 .SwAccess(prim_subreg_pkg::SwAccessRW),
2048 .RESVAL (2'h0),
2049 .Mubi (1'b0)
2050 ) u_prio28 (
2051 .clk_i (clk_i),
2052 .rst_ni (rst_ni),
2053
2054 // from register interface
2055 .we (prio28_we),
2056 .wd (prio28_wd),
2057
2058 // from internal hardware
2059 .de (1'b0),
2060 .d ('0),
2061
2062 // to internal hardware
2063 .qe (),
2064 .q (reg2hw.prio28.q),
2065 .ds (),
2066
2067 // to register interface (read)
2068 .qs (prio28_qs)
2069 );
2070
2071
2072 // R[prio29]: V(False)
2073 prim_subreg #(
2074 .DW (2),
2075 .SwAccess(prim_subreg_pkg::SwAccessRW),
2076 .RESVAL (2'h0),
2077 .Mubi (1'b0)
2078 ) u_prio29 (
2079 .clk_i (clk_i),
2080 .rst_ni (rst_ni),
2081
2082 // from register interface
2083 .we (prio29_we),
2084 .wd (prio29_wd),
2085
2086 // from internal hardware
2087 .de (1'b0),
2088 .d ('0),
2089
2090 // to internal hardware
2091 .qe (),
2092 .q (reg2hw.prio29.q),
2093 .ds (),
2094
2095 // to register interface (read)
2096 .qs (prio29_qs)
2097 );
2098
2099
2100 // R[prio30]: V(False)
2101 prim_subreg #(
2102 .DW (2),
2103 .SwAccess(prim_subreg_pkg::SwAccessRW),
2104 .RESVAL (2'h0),
2105 .Mubi (1'b0)
2106 ) u_prio30 (
2107 .clk_i (clk_i),
2108 .rst_ni (rst_ni),
2109
2110 // from register interface
2111 .we (prio30_we),
2112 .wd (prio30_wd),
2113
2114 // from internal hardware
2115 .de (1'b0),
2116 .d ('0),
2117
2118 // to internal hardware
2119 .qe (),
2120 .q (reg2hw.prio30.q),
2121 .ds (),
2122
2123 // to register interface (read)
2124 .qs (prio30_qs)
2125 );
2126
2127
2128 // R[prio31]: V(False)
2129 prim_subreg #(
2130 .DW (2),
2131 .SwAccess(prim_subreg_pkg::SwAccessRW),
2132 .RESVAL (2'h0),
2133 .Mubi (1'b0)
2134 ) u_prio31 (
2135 .clk_i (clk_i),
2136 .rst_ni (rst_ni),
2137
2138 // from register interface
2139 .we (prio31_we),
2140 .wd (prio31_wd),
2141
2142 // from internal hardware
2143 .de (1'b0),
2144 .d ('0),
2145
2146 // to internal hardware
2147 .qe (),
2148 .q (reg2hw.prio31.q),
2149 .ds (),
2150
2151 // to register interface (read)
2152 .qs (prio31_qs)
2153 );
2154
2155
2156 // R[prio32]: V(False)
2157 prim_subreg #(
2158 .DW (2),
2159 .SwAccess(prim_subreg_pkg::SwAccessRW),
2160 .RESVAL (2'h0),
2161 .Mubi (1'b0)
2162 ) u_prio32 (
2163 .clk_i (clk_i),
2164 .rst_ni (rst_ni),
2165
2166 // from register interface
2167 .we (prio32_we),
2168 .wd (prio32_wd),
2169
2170 // from internal hardware
2171 .de (1'b0),
2172 .d ('0),
2173
2174 // to internal hardware
2175 .qe (),
2176 .q (reg2hw.prio32.q),
2177 .ds (),
2178
2179 // to register interface (read)
2180 .qs (prio32_qs)
2181 );
2182
2183
2184 // R[prio33]: V(False)
2185 prim_subreg #(
2186 .DW (2),
2187 .SwAccess(prim_subreg_pkg::SwAccessRW),
2188 .RESVAL (2'h0),
2189 .Mubi (1'b0)
2190 ) u_prio33 (
2191 .clk_i (clk_i),
2192 .rst_ni (rst_ni),
2193
2194 // from register interface
2195 .we (prio33_we),
2196 .wd (prio33_wd),
2197
2198 // from internal hardware
2199 .de (1'b0),
2200 .d ('0),
2201
2202 // to internal hardware
2203 .qe (),
2204 .q (reg2hw.prio33.q),
2205 .ds (),
2206
2207 // to register interface (read)
2208 .qs (prio33_qs)
2209 );
2210
2211
2212 // R[prio34]: V(False)
2213 prim_subreg #(
2214 .DW (2),
2215 .SwAccess(prim_subreg_pkg::SwAccessRW),
2216 .RESVAL (2'h0),
2217 .Mubi (1'b0)
2218 ) u_prio34 (
2219 .clk_i (clk_i),
2220 .rst_ni (rst_ni),
2221
2222 // from register interface
2223 .we (prio34_we),
2224 .wd (prio34_wd),
2225
2226 // from internal hardware
2227 .de (1'b0),
2228 .d ('0),
2229
2230 // to internal hardware
2231 .qe (),
2232 .q (reg2hw.prio34.q),
2233 .ds (),
2234
2235 // to register interface (read)
2236 .qs (prio34_qs)
2237 );
2238
2239
2240 // R[prio35]: V(False)
2241 prim_subreg #(
2242 .DW (2),
2243 .SwAccess(prim_subreg_pkg::SwAccessRW),
2244 .RESVAL (2'h0),
2245 .Mubi (1'b0)
2246 ) u_prio35 (
2247 .clk_i (clk_i),
2248 .rst_ni (rst_ni),
2249
2250 // from register interface
2251 .we (prio35_we),
2252 .wd (prio35_wd),
2253
2254 // from internal hardware
2255 .de (1'b0),
2256 .d ('0),
2257
2258 // to internal hardware
2259 .qe (),
2260 .q (reg2hw.prio35.q),
2261 .ds (),
2262
2263 // to register interface (read)
2264 .qs (prio35_qs)
2265 );
2266
2267
2268 // R[prio36]: V(False)
2269 prim_subreg #(
2270 .DW (2),
2271 .SwAccess(prim_subreg_pkg::SwAccessRW),
2272 .RESVAL (2'h0),
2273 .Mubi (1'b0)
2274 ) u_prio36 (
2275 .clk_i (clk_i),
2276 .rst_ni (rst_ni),
2277
2278 // from register interface
2279 .we (prio36_we),
2280 .wd (prio36_wd),
2281
2282 // from internal hardware
2283 .de (1'b0),
2284 .d ('0),
2285
2286 // to internal hardware
2287 .qe (),
2288 .q (reg2hw.prio36.q),
2289 .ds (),
2290
2291 // to register interface (read)
2292 .qs (prio36_qs)
2293 );
2294
2295
2296 // R[prio37]: V(False)
2297 prim_subreg #(
2298 .DW (2),
2299 .SwAccess(prim_subreg_pkg::SwAccessRW),
2300 .RESVAL (2'h0),
2301 .Mubi (1'b0)
2302 ) u_prio37 (
2303 .clk_i (clk_i),
2304 .rst_ni (rst_ni),
2305
2306 // from register interface
2307 .we (prio37_we),
2308 .wd (prio37_wd),
2309
2310 // from internal hardware
2311 .de (1'b0),
2312 .d ('0),
2313
2314 // to internal hardware
2315 .qe (),
2316 .q (reg2hw.prio37.q),
2317 .ds (),
2318
2319 // to register interface (read)
2320 .qs (prio37_qs)
2321 );
2322
2323
2324 // R[prio38]: V(False)
2325 prim_subreg #(
2326 .DW (2),
2327 .SwAccess(prim_subreg_pkg::SwAccessRW),
2328 .RESVAL (2'h0),
2329 .Mubi (1'b0)
2330 ) u_prio38 (
2331 .clk_i (clk_i),
2332 .rst_ni (rst_ni),
2333
2334 // from register interface
2335 .we (prio38_we),
2336 .wd (prio38_wd),
2337
2338 // from internal hardware
2339 .de (1'b0),
2340 .d ('0),
2341
2342 // to internal hardware
2343 .qe (),
2344 .q (reg2hw.prio38.q),
2345 .ds (),
2346
2347 // to register interface (read)
2348 .qs (prio38_qs)
2349 );
2350
2351
2352 // R[prio39]: V(False)
2353 prim_subreg #(
2354 .DW (2),
2355 .SwAccess(prim_subreg_pkg::SwAccessRW),
2356 .RESVAL (2'h0),
2357 .Mubi (1'b0)
2358 ) u_prio39 (
2359 .clk_i (clk_i),
2360 .rst_ni (rst_ni),
2361
2362 // from register interface
2363 .we (prio39_we),
2364 .wd (prio39_wd),
2365
2366 // from internal hardware
2367 .de (1'b0),
2368 .d ('0),
2369
2370 // to internal hardware
2371 .qe (),
2372 .q (reg2hw.prio39.q),
2373 .ds (),
2374
2375 // to register interface (read)
2376 .qs (prio39_qs)
2377 );
2378
2379
2380 // R[prio40]: V(False)
2381 prim_subreg #(
2382 .DW (2),
2383 .SwAccess(prim_subreg_pkg::SwAccessRW),
2384 .RESVAL (2'h0),
2385 .Mubi (1'b0)
2386 ) u_prio40 (
2387 .clk_i (clk_i),
2388 .rst_ni (rst_ni),
2389
2390 // from register interface
2391 .we (prio40_we),
2392 .wd (prio40_wd),
2393
2394 // from internal hardware
2395 .de (1'b0),
2396 .d ('0),
2397
2398 // to internal hardware
2399 .qe (),
2400 .q (reg2hw.prio40.q),
2401 .ds (),
2402
2403 // to register interface (read)
2404 .qs (prio40_qs)
2405 );
2406
2407
2408 // R[prio41]: V(False)
2409 prim_subreg #(
2410 .DW (2),
2411 .SwAccess(prim_subreg_pkg::SwAccessRW),
2412 .RESVAL (2'h0),
2413 .Mubi (1'b0)
2414 ) u_prio41 (
2415 .clk_i (clk_i),
2416 .rst_ni (rst_ni),
2417
2418 // from register interface
2419 .we (prio41_we),
2420 .wd (prio41_wd),
2421
2422 // from internal hardware
2423 .de (1'b0),
2424 .d ('0),
2425
2426 // to internal hardware
2427 .qe (),
2428 .q (reg2hw.prio41.q),
2429 .ds (),
2430
2431 // to register interface (read)
2432 .qs (prio41_qs)
2433 );
2434
2435
2436 // R[prio42]: V(False)
2437 prim_subreg #(
2438 .DW (2),
2439 .SwAccess(prim_subreg_pkg::SwAccessRW),
2440 .RESVAL (2'h0),
2441 .Mubi (1'b0)
2442 ) u_prio42 (
2443 .clk_i (clk_i),
2444 .rst_ni (rst_ni),
2445
2446 // from register interface
2447 .we (prio42_we),
2448 .wd (prio42_wd),
2449
2450 // from internal hardware
2451 .de (1'b0),
2452 .d ('0),
2453
2454 // to internal hardware
2455 .qe (),
2456 .q (reg2hw.prio42.q),
2457 .ds (),
2458
2459 // to register interface (read)
2460 .qs (prio42_qs)
2461 );
2462
2463
2464 // R[prio43]: V(False)
2465 prim_subreg #(
2466 .DW (2),
2467 .SwAccess(prim_subreg_pkg::SwAccessRW),
2468 .RESVAL (2'h0),
2469 .Mubi (1'b0)
2470 ) u_prio43 (
2471 .clk_i (clk_i),
2472 .rst_ni (rst_ni),
2473
2474 // from register interface
2475 .we (prio43_we),
2476 .wd (prio43_wd),
2477
2478 // from internal hardware
2479 .de (1'b0),
2480 .d ('0),
2481
2482 // to internal hardware
2483 .qe (),
2484 .q (reg2hw.prio43.q),
2485 .ds (),
2486
2487 // to register interface (read)
2488 .qs (prio43_qs)
2489 );
2490
2491
2492 // R[prio44]: V(False)
2493 prim_subreg #(
2494 .DW (2),
2495 .SwAccess(prim_subreg_pkg::SwAccessRW),
2496 .RESVAL (2'h0),
2497 .Mubi (1'b0)
2498 ) u_prio44 (
2499 .clk_i (clk_i),
2500 .rst_ni (rst_ni),
2501
2502 // from register interface
2503 .we (prio44_we),
2504 .wd (prio44_wd),
2505
2506 // from internal hardware
2507 .de (1'b0),
2508 .d ('0),
2509
2510 // to internal hardware
2511 .qe (),
2512 .q (reg2hw.prio44.q),
2513 .ds (),
2514
2515 // to register interface (read)
2516 .qs (prio44_qs)
2517 );
2518
2519
2520 // R[prio45]: V(False)
2521 prim_subreg #(
2522 .DW (2),
2523 .SwAccess(prim_subreg_pkg::SwAccessRW),
2524 .RESVAL (2'h0),
2525 .Mubi (1'b0)
2526 ) u_prio45 (
2527 .clk_i (clk_i),
2528 .rst_ni (rst_ni),
2529
2530 // from register interface
2531 .we (prio45_we),
2532 .wd (prio45_wd),
2533
2534 // from internal hardware
2535 .de (1'b0),
2536 .d ('0),
2537
2538 // to internal hardware
2539 .qe (),
2540 .q (reg2hw.prio45.q),
2541 .ds (),
2542
2543 // to register interface (read)
2544 .qs (prio45_qs)
2545 );
2546
2547
2548 // R[prio46]: V(False)
2549 prim_subreg #(
2550 .DW (2),
2551 .SwAccess(prim_subreg_pkg::SwAccessRW),
2552 .RESVAL (2'h0),
2553 .Mubi (1'b0)
2554 ) u_prio46 (
2555 .clk_i (clk_i),
2556 .rst_ni (rst_ni),
2557
2558 // from register interface
2559 .we (prio46_we),
2560 .wd (prio46_wd),
2561
2562 // from internal hardware
2563 .de (1'b0),
2564 .d ('0),
2565
2566 // to internal hardware
2567 .qe (),
2568 .q (reg2hw.prio46.q),
2569 .ds (),
2570
2571 // to register interface (read)
2572 .qs (prio46_qs)
2573 );
2574
2575
2576 // R[prio47]: V(False)
2577 prim_subreg #(
2578 .DW (2),
2579 .SwAccess(prim_subreg_pkg::SwAccessRW),
2580 .RESVAL (2'h0),
2581 .Mubi (1'b0)
2582 ) u_prio47 (
2583 .clk_i (clk_i),
2584 .rst_ni (rst_ni),
2585
2586 // from register interface
2587 .we (prio47_we),
2588 .wd (prio47_wd),
2589
2590 // from internal hardware
2591 .de (1'b0),
2592 .d ('0),
2593
2594 // to internal hardware
2595 .qe (),
2596 .q (reg2hw.prio47.q),
2597 .ds (),
2598
2599 // to register interface (read)
2600 .qs (prio47_qs)
2601 );
2602
2603
2604 // R[prio48]: V(False)
2605 prim_subreg #(
2606 .DW (2),
2607 .SwAccess(prim_subreg_pkg::SwAccessRW),
2608 .RESVAL (2'h0),
2609 .Mubi (1'b0)
2610 ) u_prio48 (
2611 .clk_i (clk_i),
2612 .rst_ni (rst_ni),
2613
2614 // from register interface
2615 .we (prio48_we),
2616 .wd (prio48_wd),
2617
2618 // from internal hardware
2619 .de (1'b0),
2620 .d ('0),
2621
2622 // to internal hardware
2623 .qe (),
2624 .q (reg2hw.prio48.q),
2625 .ds (),
2626
2627 // to register interface (read)
2628 .qs (prio48_qs)
2629 );
2630
2631
2632 // R[prio49]: V(False)
2633 prim_subreg #(
2634 .DW (2),
2635 .SwAccess(prim_subreg_pkg::SwAccessRW),
2636 .RESVAL (2'h0),
2637 .Mubi (1'b0)
2638 ) u_prio49 (
2639 .clk_i (clk_i),
2640 .rst_ni (rst_ni),
2641
2642 // from register interface
2643 .we (prio49_we),
2644 .wd (prio49_wd),
2645
2646 // from internal hardware
2647 .de (1'b0),
2648 .d ('0),
2649
2650 // to internal hardware
2651 .qe (),
2652 .q (reg2hw.prio49.q),
2653 .ds (),
2654
2655 // to register interface (read)
2656 .qs (prio49_qs)
2657 );
2658
2659
2660 // R[prio50]: V(False)
2661 prim_subreg #(
2662 .DW (2),
2663 .SwAccess(prim_subreg_pkg::SwAccessRW),
2664 .RESVAL (2'h0),
2665 .Mubi (1'b0)
2666 ) u_prio50 (
2667 .clk_i (clk_i),
2668 .rst_ni (rst_ni),
2669
2670 // from register interface
2671 .we (prio50_we),
2672 .wd (prio50_wd),
2673
2674 // from internal hardware
2675 .de (1'b0),
2676 .d ('0),
2677
2678 // to internal hardware
2679 .qe (),
2680 .q (reg2hw.prio50.q),
2681 .ds (),
2682
2683 // to register interface (read)
2684 .qs (prio50_qs)
2685 );
2686
2687
2688 // R[prio51]: V(False)
2689 prim_subreg #(
2690 .DW (2),
2691 .SwAccess(prim_subreg_pkg::SwAccessRW),
2692 .RESVAL (2'h0),
2693 .Mubi (1'b0)
2694 ) u_prio51 (
2695 .clk_i (clk_i),
2696 .rst_ni (rst_ni),
2697
2698 // from register interface
2699 .we (prio51_we),
2700 .wd (prio51_wd),
2701
2702 // from internal hardware
2703 .de (1'b0),
2704 .d ('0),
2705
2706 // to internal hardware
2707 .qe (),
2708 .q (reg2hw.prio51.q),
2709 .ds (),
2710
2711 // to register interface (read)
2712 .qs (prio51_qs)
2713 );
2714
2715
2716 // R[prio52]: V(False)
2717 prim_subreg #(
2718 .DW (2),
2719 .SwAccess(prim_subreg_pkg::SwAccessRW),
2720 .RESVAL (2'h0),
2721 .Mubi (1'b0)
2722 ) u_prio52 (
2723 .clk_i (clk_i),
2724 .rst_ni (rst_ni),
2725
2726 // from register interface
2727 .we (prio52_we),
2728 .wd (prio52_wd),
2729
2730 // from internal hardware
2731 .de (1'b0),
2732 .d ('0),
2733
2734 // to internal hardware
2735 .qe (),
2736 .q (reg2hw.prio52.q),
2737 .ds (),
2738
2739 // to register interface (read)
2740 .qs (prio52_qs)
2741 );
2742
2743
2744 // R[prio53]: V(False)
2745 prim_subreg #(
2746 .DW (2),
2747 .SwAccess(prim_subreg_pkg::SwAccessRW),
2748 .RESVAL (2'h0),
2749 .Mubi (1'b0)
2750 ) u_prio53 (
2751 .clk_i (clk_i),
2752 .rst_ni (rst_ni),
2753
2754 // from register interface
2755 .we (prio53_we),
2756 .wd (prio53_wd),
2757
2758 // from internal hardware
2759 .de (1'b0),
2760 .d ('0),
2761
2762 // to internal hardware
2763 .qe (),
2764 .q (reg2hw.prio53.q),
2765 .ds (),
2766
2767 // to register interface (read)
2768 .qs (prio53_qs)
2769 );
2770
2771
2772 // R[prio54]: V(False)
2773 prim_subreg #(
2774 .DW (2),
2775 .SwAccess(prim_subreg_pkg::SwAccessRW),
2776 .RESVAL (2'h0),
2777 .Mubi (1'b0)
2778 ) u_prio54 (
2779 .clk_i (clk_i),
2780 .rst_ni (rst_ni),
2781
2782 // from register interface
2783 .we (prio54_we),
2784 .wd (prio54_wd),
2785
2786 // from internal hardware
2787 .de (1'b0),
2788 .d ('0),
2789
2790 // to internal hardware
2791 .qe (),
2792 .q (reg2hw.prio54.q),
2793 .ds (),
2794
2795 // to register interface (read)
2796 .qs (prio54_qs)
2797 );
2798
2799
2800 // R[prio55]: V(False)
2801 prim_subreg #(
2802 .DW (2),
2803 .SwAccess(prim_subreg_pkg::SwAccessRW),
2804 .RESVAL (2'h0),
2805 .Mubi (1'b0)
2806 ) u_prio55 (
2807 .clk_i (clk_i),
2808 .rst_ni (rst_ni),
2809
2810 // from register interface
2811 .we (prio55_we),
2812 .wd (prio55_wd),
2813
2814 // from internal hardware
2815 .de (1'b0),
2816 .d ('0),
2817
2818 // to internal hardware
2819 .qe (),
2820 .q (reg2hw.prio55.q),
2821 .ds (),
2822
2823 // to register interface (read)
2824 .qs (prio55_qs)
2825 );
2826
2827
2828 // R[prio56]: V(False)
2829 prim_subreg #(
2830 .DW (2),
2831 .SwAccess(prim_subreg_pkg::SwAccessRW),
2832 .RESVAL (2'h0),
2833 .Mubi (1'b0)
2834 ) u_prio56 (
2835 .clk_i (clk_i),
2836 .rst_ni (rst_ni),
2837
2838 // from register interface
2839 .we (prio56_we),
2840 .wd (prio56_wd),
2841
2842 // from internal hardware
2843 .de (1'b0),
2844 .d ('0),
2845
2846 // to internal hardware
2847 .qe (),
2848 .q (reg2hw.prio56.q),
2849 .ds (),
2850
2851 // to register interface (read)
2852 .qs (prio56_qs)
2853 );
2854
2855
2856 // R[prio57]: V(False)
2857 prim_subreg #(
2858 .DW (2),
2859 .SwAccess(prim_subreg_pkg::SwAccessRW),
2860 .RESVAL (2'h0),
2861 .Mubi (1'b0)
2862 ) u_prio57 (
2863 .clk_i (clk_i),
2864 .rst_ni (rst_ni),
2865
2866 // from register interface
2867 .we (prio57_we),
2868 .wd (prio57_wd),
2869
2870 // from internal hardware
2871 .de (1'b0),
2872 .d ('0),
2873
2874 // to internal hardware
2875 .qe (),
2876 .q (reg2hw.prio57.q),
2877 .ds (),
2878
2879 // to register interface (read)
2880 .qs (prio57_qs)
2881 );
2882
2883
2884 // R[prio58]: V(False)
2885 prim_subreg #(
2886 .DW (2),
2887 .SwAccess(prim_subreg_pkg::SwAccessRW),
2888 .RESVAL (2'h0),
2889 .Mubi (1'b0)
2890 ) u_prio58 (
2891 .clk_i (clk_i),
2892 .rst_ni (rst_ni),
2893
2894 // from register interface
2895 .we (prio58_we),
2896 .wd (prio58_wd),
2897
2898 // from internal hardware
2899 .de (1'b0),
2900 .d ('0),
2901
2902 // to internal hardware
2903 .qe (),
2904 .q (reg2hw.prio58.q),
2905 .ds (),
2906
2907 // to register interface (read)
2908 .qs (prio58_qs)
2909 );
2910
2911
2912 // R[prio59]: V(False)
2913 prim_subreg #(
2914 .DW (2),
2915 .SwAccess(prim_subreg_pkg::SwAccessRW),
2916 .RESVAL (2'h0),
2917 .Mubi (1'b0)
2918 ) u_prio59 (
2919 .clk_i (clk_i),
2920 .rst_ni (rst_ni),
2921
2922 // from register interface
2923 .we (prio59_we),
2924 .wd (prio59_wd),
2925
2926 // from internal hardware
2927 .de (1'b0),
2928 .d ('0),
2929
2930 // to internal hardware
2931 .qe (),
2932 .q (reg2hw.prio59.q),
2933 .ds (),
2934
2935 // to register interface (read)
2936 .qs (prio59_qs)
2937 );
2938
2939
2940 // R[prio60]: V(False)
2941 prim_subreg #(
2942 .DW (2),
2943 .SwAccess(prim_subreg_pkg::SwAccessRW),
2944 .RESVAL (2'h0),
2945 .Mubi (1'b0)
2946 ) u_prio60 (
2947 .clk_i (clk_i),
2948 .rst_ni (rst_ni),
2949
2950 // from register interface
2951 .we (prio60_we),
2952 .wd (prio60_wd),
2953
2954 // from internal hardware
2955 .de (1'b0),
2956 .d ('0),
2957
2958 // to internal hardware
2959 .qe (),
2960 .q (reg2hw.prio60.q),
2961 .ds (),
2962
2963 // to register interface (read)
2964 .qs (prio60_qs)
2965 );
2966
2967
2968 // R[prio61]: V(False)
2969 prim_subreg #(
2970 .DW (2),
2971 .SwAccess(prim_subreg_pkg::SwAccessRW),
2972 .RESVAL (2'h0),
2973 .Mubi (1'b0)
2974 ) u_prio61 (
2975 .clk_i (clk_i),
2976 .rst_ni (rst_ni),
2977
2978 // from register interface
2979 .we (prio61_we),
2980 .wd (prio61_wd),
2981
2982 // from internal hardware
2983 .de (1'b0),
2984 .d ('0),
2985
2986 // to internal hardware
2987 .qe (),
2988 .q (reg2hw.prio61.q),
2989 .ds (),
2990
2991 // to register interface (read)
2992 .qs (prio61_qs)
2993 );
2994
2995
2996 // R[prio62]: V(False)
2997 prim_subreg #(
2998 .DW (2),
2999 .SwAccess(prim_subreg_pkg::SwAccessRW),
3000 .RESVAL (2'h0),
3001 .Mubi (1'b0)
3002 ) u_prio62 (
3003 .clk_i (clk_i),
3004 .rst_ni (rst_ni),
3005
3006 // from register interface
3007 .we (prio62_we),
3008 .wd (prio62_wd),
3009
3010 // from internal hardware
3011 .de (1'b0),
3012 .d ('0),
3013
3014 // to internal hardware
3015 .qe (),
3016 .q (reg2hw.prio62.q),
3017 .ds (),
3018
3019 // to register interface (read)
3020 .qs (prio62_qs)
3021 );
3022
3023
3024 // R[prio63]: V(False)
3025 prim_subreg #(
3026 .DW (2),
3027 .SwAccess(prim_subreg_pkg::SwAccessRW),
3028 .RESVAL (2'h0),
3029 .Mubi (1'b0)
3030 ) u_prio63 (
3031 .clk_i (clk_i),
3032 .rst_ni (rst_ni),
3033
3034 // from register interface
3035 .we (prio63_we),
3036 .wd (prio63_wd),
3037
3038 // from internal hardware
3039 .de (1'b0),
3040 .d ('0),
3041
3042 // to internal hardware
3043 .qe (),
3044 .q (reg2hw.prio63.q),
3045 .ds (),
3046
3047 // to register interface (read)
3048 .qs (prio63_qs)
3049 );
3050
3051
3052 // R[prio64]: V(False)
3053 prim_subreg #(
3054 .DW (2),
3055 .SwAccess(prim_subreg_pkg::SwAccessRW),
3056 .RESVAL (2'h0),
3057 .Mubi (1'b0)
3058 ) u_prio64 (
3059 .clk_i (clk_i),
3060 .rst_ni (rst_ni),
3061
3062 // from register interface
3063 .we (prio64_we),
3064 .wd (prio64_wd),
3065
3066 // from internal hardware
3067 .de (1'b0),
3068 .d ('0),
3069
3070 // to internal hardware
3071 .qe (),
3072 .q (reg2hw.prio64.q),
3073 .ds (),
3074
3075 // to register interface (read)
3076 .qs (prio64_qs)
3077 );
3078
3079
3080 // R[prio65]: V(False)
3081 prim_subreg #(
3082 .DW (2),
3083 .SwAccess(prim_subreg_pkg::SwAccessRW),
3084 .RESVAL (2'h0),
3085 .Mubi (1'b0)
3086 ) u_prio65 (
3087 .clk_i (clk_i),
3088 .rst_ni (rst_ni),
3089
3090 // from register interface
3091 .we (prio65_we),
3092 .wd (prio65_wd),
3093
3094 // from internal hardware
3095 .de (1'b0),
3096 .d ('0),
3097
3098 // to internal hardware
3099 .qe (),
3100 .q (reg2hw.prio65.q),
3101 .ds (),
3102
3103 // to register interface (read)
3104 .qs (prio65_qs)
3105 );
3106
3107
3108 // R[prio66]: V(False)
3109 prim_subreg #(
3110 .DW (2),
3111 .SwAccess(prim_subreg_pkg::SwAccessRW),
3112 .RESVAL (2'h0),
3113 .Mubi (1'b0)
3114 ) u_prio66 (
3115 .clk_i (clk_i),
3116 .rst_ni (rst_ni),
3117
3118 // from register interface
3119 .we (prio66_we),
3120 .wd (prio66_wd),
3121
3122 // from internal hardware
3123 .de (1'b0),
3124 .d ('0),
3125
3126 // to internal hardware
3127 .qe (),
3128 .q (reg2hw.prio66.q),
3129 .ds (),
3130
3131 // to register interface (read)
3132 .qs (prio66_qs)
3133 );
3134
3135
3136 // R[prio67]: V(False)
3137 prim_subreg #(
3138 .DW (2),
3139 .SwAccess(prim_subreg_pkg::SwAccessRW),
3140 .RESVAL (2'h0),
3141 .Mubi (1'b0)
3142 ) u_prio67 (
3143 .clk_i (clk_i),
3144 .rst_ni (rst_ni),
3145
3146 // from register interface
3147 .we (prio67_we),
3148 .wd (prio67_wd),
3149
3150 // from internal hardware
3151 .de (1'b0),
3152 .d ('0),
3153
3154 // to internal hardware
3155 .qe (),
3156 .q (reg2hw.prio67.q),
3157 .ds (),
3158
3159 // to register interface (read)
3160 .qs (prio67_qs)
3161 );
3162
3163
3164 // R[prio68]: V(False)
3165 prim_subreg #(
3166 .DW (2),
3167 .SwAccess(prim_subreg_pkg::SwAccessRW),
3168 .RESVAL (2'h0),
3169 .Mubi (1'b0)
3170 ) u_prio68 (
3171 .clk_i (clk_i),
3172 .rst_ni (rst_ni),
3173
3174 // from register interface
3175 .we (prio68_we),
3176 .wd (prio68_wd),
3177
3178 // from internal hardware
3179 .de (1'b0),
3180 .d ('0),
3181
3182 // to internal hardware
3183 .qe (),
3184 .q (reg2hw.prio68.q),
3185 .ds (),
3186
3187 // to register interface (read)
3188 .qs (prio68_qs)
3189 );
3190
3191
3192 // R[prio69]: V(False)
3193 prim_subreg #(
3194 .DW (2),
3195 .SwAccess(prim_subreg_pkg::SwAccessRW),
3196 .RESVAL (2'h0),
3197 .Mubi (1'b0)
3198 ) u_prio69 (
3199 .clk_i (clk_i),
3200 .rst_ni (rst_ni),
3201
3202 // from register interface
3203 .we (prio69_we),
3204 .wd (prio69_wd),
3205
3206 // from internal hardware
3207 .de (1'b0),
3208 .d ('0),
3209
3210 // to internal hardware
3211 .qe (),
3212 .q (reg2hw.prio69.q),
3213 .ds (),
3214
3215 // to register interface (read)
3216 .qs (prio69_qs)
3217 );
3218
3219
3220 // R[prio70]: V(False)
3221 prim_subreg #(
3222 .DW (2),
3223 .SwAccess(prim_subreg_pkg::SwAccessRW),
3224 .RESVAL (2'h0),
3225 .Mubi (1'b0)
3226 ) u_prio70 (
3227 .clk_i (clk_i),
3228 .rst_ni (rst_ni),
3229
3230 // from register interface
3231 .we (prio70_we),
3232 .wd (prio70_wd),
3233
3234 // from internal hardware
3235 .de (1'b0),
3236 .d ('0),
3237
3238 // to internal hardware
3239 .qe (),
3240 .q (reg2hw.prio70.q),
3241 .ds (),
3242
3243 // to register interface (read)
3244 .qs (prio70_qs)
3245 );
3246
3247
3248 // R[prio71]: V(False)
3249 prim_subreg #(
3250 .DW (2),
3251 .SwAccess(prim_subreg_pkg::SwAccessRW),
3252 .RESVAL (2'h0),
3253 .Mubi (1'b0)
3254 ) u_prio71 (
3255 .clk_i (clk_i),
3256 .rst_ni (rst_ni),
3257
3258 // from register interface
3259 .we (prio71_we),
3260 .wd (prio71_wd),
3261
3262 // from internal hardware
3263 .de (1'b0),
3264 .d ('0),
3265
3266 // to internal hardware
3267 .qe (),
3268 .q (reg2hw.prio71.q),
3269 .ds (),
3270
3271 // to register interface (read)
3272 .qs (prio71_qs)
3273 );
3274
3275
3276 // R[prio72]: V(False)
3277 prim_subreg #(
3278 .DW (2),
3279 .SwAccess(prim_subreg_pkg::SwAccessRW),
3280 .RESVAL (2'h0),
3281 .Mubi (1'b0)
3282 ) u_prio72 (
3283 .clk_i (clk_i),
3284 .rst_ni (rst_ni),
3285
3286 // from register interface
3287 .we (prio72_we),
3288 .wd (prio72_wd),
3289
3290 // from internal hardware
3291 .de (1'b0),
3292 .d ('0),
3293
3294 // to internal hardware
3295 .qe (),
3296 .q (reg2hw.prio72.q),
3297 .ds (),
3298
3299 // to register interface (read)
3300 .qs (prio72_qs)
3301 );
3302
3303
3304 // R[prio73]: V(False)
3305 prim_subreg #(
3306 .DW (2),
3307 .SwAccess(prim_subreg_pkg::SwAccessRW),
3308 .RESVAL (2'h0),
3309 .Mubi (1'b0)
3310 ) u_prio73 (
3311 .clk_i (clk_i),
3312 .rst_ni (rst_ni),
3313
3314 // from register interface
3315 .we (prio73_we),
3316 .wd (prio73_wd),
3317
3318 // from internal hardware
3319 .de (1'b0),
3320 .d ('0),
3321
3322 // to internal hardware
3323 .qe (),
3324 .q (reg2hw.prio73.q),
3325 .ds (),
3326
3327 // to register interface (read)
3328 .qs (prio73_qs)
3329 );
3330
3331
3332 // R[prio74]: V(False)
3333 prim_subreg #(
3334 .DW (2),
3335 .SwAccess(prim_subreg_pkg::SwAccessRW),
3336 .RESVAL (2'h0),
3337 .Mubi (1'b0)
3338 ) u_prio74 (
3339 .clk_i (clk_i),
3340 .rst_ni (rst_ni),
3341
3342 // from register interface
3343 .we (prio74_we),
3344 .wd (prio74_wd),
3345
3346 // from internal hardware
3347 .de (1'b0),
3348 .d ('0),
3349
3350 // to internal hardware
3351 .qe (),
3352 .q (reg2hw.prio74.q),
3353 .ds (),
3354
3355 // to register interface (read)
3356 .qs (prio74_qs)
3357 );
3358
3359
3360 // R[prio75]: V(False)
3361 prim_subreg #(
3362 .DW (2),
3363 .SwAccess(prim_subreg_pkg::SwAccessRW),
3364 .RESVAL (2'h0),
3365 .Mubi (1'b0)
3366 ) u_prio75 (
3367 .clk_i (clk_i),
3368 .rst_ni (rst_ni),
3369
3370 // from register interface
3371 .we (prio75_we),
3372 .wd (prio75_wd),
3373
3374 // from internal hardware
3375 .de (1'b0),
3376 .d ('0),
3377
3378 // to internal hardware
3379 .qe (),
3380 .q (reg2hw.prio75.q),
3381 .ds (),
3382
3383 // to register interface (read)
3384 .qs (prio75_qs)
3385 );
3386
3387
3388 // R[prio76]: V(False)
3389 prim_subreg #(
3390 .DW (2),
3391 .SwAccess(prim_subreg_pkg::SwAccessRW),
3392 .RESVAL (2'h0),
3393 .Mubi (1'b0)
3394 ) u_prio76 (
3395 .clk_i (clk_i),
3396 .rst_ni (rst_ni),
3397
3398 // from register interface
3399 .we (prio76_we),
3400 .wd (prio76_wd),
3401
3402 // from internal hardware
3403 .de (1'b0),
3404 .d ('0),
3405
3406 // to internal hardware
3407 .qe (),
3408 .q (reg2hw.prio76.q),
3409 .ds (),
3410
3411 // to register interface (read)
3412 .qs (prio76_qs)
3413 );
3414
3415
3416 // R[prio77]: V(False)
3417 prim_subreg #(
3418 .DW (2),
3419 .SwAccess(prim_subreg_pkg::SwAccessRW),
3420 .RESVAL (2'h0),
3421 .Mubi (1'b0)
3422 ) u_prio77 (
3423 .clk_i (clk_i),
3424 .rst_ni (rst_ni),
3425
3426 // from register interface
3427 .we (prio77_we),
3428 .wd (prio77_wd),
3429
3430 // from internal hardware
3431 .de (1'b0),
3432 .d ('0),
3433
3434 // to internal hardware
3435 .qe (),
3436 .q (reg2hw.prio77.q),
3437 .ds (),
3438
3439 // to register interface (read)
3440 .qs (prio77_qs)
3441 );
3442
3443
3444 // R[prio78]: V(False)
3445 prim_subreg #(
3446 .DW (2),
3447 .SwAccess(prim_subreg_pkg::SwAccessRW),
3448 .RESVAL (2'h0),
3449 .Mubi (1'b0)
3450 ) u_prio78 (
3451 .clk_i (clk_i),
3452 .rst_ni (rst_ni),
3453
3454 // from register interface
3455 .we (prio78_we),
3456 .wd (prio78_wd),
3457
3458 // from internal hardware
3459 .de (1'b0),
3460 .d ('0),
3461
3462 // to internal hardware
3463 .qe (),
3464 .q (reg2hw.prio78.q),
3465 .ds (),
3466
3467 // to register interface (read)
3468 .qs (prio78_qs)
3469 );
3470
3471
3472 // R[prio79]: V(False)
3473 prim_subreg #(
3474 .DW (2),
3475 .SwAccess(prim_subreg_pkg::SwAccessRW),
3476 .RESVAL (2'h0),
3477 .Mubi (1'b0)
3478 ) u_prio79 (
3479 .clk_i (clk_i),
3480 .rst_ni (rst_ni),
3481
3482 // from register interface
3483 .we (prio79_we),
3484 .wd (prio79_wd),
3485
3486 // from internal hardware
3487 .de (1'b0),
3488 .d ('0),
3489
3490 // to internal hardware
3491 .qe (),
3492 .q (reg2hw.prio79.q),
3493 .ds (),
3494
3495 // to register interface (read)
3496 .qs (prio79_qs)
3497 );
3498
3499
3500 // R[prio80]: V(False)
3501 prim_subreg #(
3502 .DW (2),
3503 .SwAccess(prim_subreg_pkg::SwAccessRW),
3504 .RESVAL (2'h0),
3505 .Mubi (1'b0)
3506 ) u_prio80 (
3507 .clk_i (clk_i),
3508 .rst_ni (rst_ni),
3509
3510 // from register interface
3511 .we (prio80_we),
3512 .wd (prio80_wd),
3513
3514 // from internal hardware
3515 .de (1'b0),
3516 .d ('0),
3517
3518 // to internal hardware
3519 .qe (),
3520 .q (reg2hw.prio80.q),
3521 .ds (),
3522
3523 // to register interface (read)
3524 .qs (prio80_qs)
3525 );
3526
3527
3528 // R[prio81]: V(False)
3529 prim_subreg #(
3530 .DW (2),
3531 .SwAccess(prim_subreg_pkg::SwAccessRW),
3532 .RESVAL (2'h0),
3533 .Mubi (1'b0)
3534 ) u_prio81 (
3535 .clk_i (clk_i),
3536 .rst_ni (rst_ni),
3537
3538 // from register interface
3539 .we (prio81_we),
3540 .wd (prio81_wd),
3541
3542 // from internal hardware
3543 .de (1'b0),
3544 .d ('0),
3545
3546 // to internal hardware
3547 .qe (),
3548 .q (reg2hw.prio81.q),
3549 .ds (),
3550
3551 // to register interface (read)
3552 .qs (prio81_qs)
3553 );
3554
3555
3556 // R[prio82]: V(False)
3557 prim_subreg #(
3558 .DW (2),
3559 .SwAccess(prim_subreg_pkg::SwAccessRW),
3560 .RESVAL (2'h0),
3561 .Mubi (1'b0)
3562 ) u_prio82 (
3563 .clk_i (clk_i),
3564 .rst_ni (rst_ni),
3565
3566 // from register interface
3567 .we (prio82_we),
3568 .wd (prio82_wd),
3569
3570 // from internal hardware
3571 .de (1'b0),
3572 .d ('0),
3573
3574 // to internal hardware
3575 .qe (),
3576 .q (reg2hw.prio82.q),
3577 .ds (),
3578
3579 // to register interface (read)
3580 .qs (prio82_qs)
3581 );
3582
3583
3584 // R[prio83]: V(False)
3585 prim_subreg #(
3586 .DW (2),
3587 .SwAccess(prim_subreg_pkg::SwAccessRW),
3588 .RESVAL (2'h0),
3589 .Mubi (1'b0)
3590 ) u_prio83 (
3591 .clk_i (clk_i),
3592 .rst_ni (rst_ni),
3593
3594 // from register interface
3595 .we (prio83_we),
3596 .wd (prio83_wd),
3597
3598 // from internal hardware
3599 .de (1'b0),
3600 .d ('0),
3601
3602 // to internal hardware
3603 .qe (),
3604 .q (reg2hw.prio83.q),
3605 .ds (),
3606
3607 // to register interface (read)
3608 .qs (prio83_qs)
3609 );
3610
3611
3612 // R[prio84]: V(False)
3613 prim_subreg #(
3614 .DW (2),
3615 .SwAccess(prim_subreg_pkg::SwAccessRW),
3616 .RESVAL (2'h0),
3617 .Mubi (1'b0)
3618 ) u_prio84 (
3619 .clk_i (clk_i),
3620 .rst_ni (rst_ni),
3621
3622 // from register interface
3623 .we (prio84_we),
3624 .wd (prio84_wd),
3625
3626 // from internal hardware
3627 .de (1'b0),
3628 .d ('0),
3629
3630 // to internal hardware
3631 .qe (),
3632 .q (reg2hw.prio84.q),
3633 .ds (),
3634
3635 // to register interface (read)
3636 .qs (prio84_qs)
3637 );
3638
3639
3640 // R[prio85]: V(False)
3641 prim_subreg #(
3642 .DW (2),
3643 .SwAccess(prim_subreg_pkg::SwAccessRW),
3644 .RESVAL (2'h0),
3645 .Mubi (1'b0)
3646 ) u_prio85 (
3647 .clk_i (clk_i),
3648 .rst_ni (rst_ni),
3649
3650 // from register interface
3651 .we (prio85_we),
3652 .wd (prio85_wd),
3653
3654 // from internal hardware
3655 .de (1'b0),
3656 .d ('0),
3657
3658 // to internal hardware
3659 .qe (),
3660 .q (reg2hw.prio85.q),
3661 .ds (),
3662
3663 // to register interface (read)
3664 .qs (prio85_qs)
3665 );
3666
3667
3668 // R[prio86]: V(False)
3669 prim_subreg #(
3670 .DW (2),
3671 .SwAccess(prim_subreg_pkg::SwAccessRW),
3672 .RESVAL (2'h0),
3673 .Mubi (1'b0)
3674 ) u_prio86 (
3675 .clk_i (clk_i),
3676 .rst_ni (rst_ni),
3677
3678 // from register interface
3679 .we (prio86_we),
3680 .wd (prio86_wd),
3681
3682 // from internal hardware
3683 .de (1'b0),
3684 .d ('0),
3685
3686 // to internal hardware
3687 .qe (),
3688 .q (reg2hw.prio86.q),
3689 .ds (),
3690
3691 // to register interface (read)
3692 .qs (prio86_qs)
3693 );
3694
3695
3696 // R[prio87]: V(False)
3697 prim_subreg #(
3698 .DW (2),
3699 .SwAccess(prim_subreg_pkg::SwAccessRW),
3700 .RESVAL (2'h0),
3701 .Mubi (1'b0)
3702 ) u_prio87 (
3703 .clk_i (clk_i),
3704 .rst_ni (rst_ni),
3705
3706 // from register interface
3707 .we (prio87_we),
3708 .wd (prio87_wd),
3709
3710 // from internal hardware
3711 .de (1'b0),
3712 .d ('0),
3713
3714 // to internal hardware
3715 .qe (),
3716 .q (reg2hw.prio87.q),
3717 .ds (),
3718
3719 // to register interface (read)
3720 .qs (prio87_qs)
3721 );
3722
3723
3724 // R[prio88]: V(False)
3725 prim_subreg #(
3726 .DW (2),
3727 .SwAccess(prim_subreg_pkg::SwAccessRW),
3728 .RESVAL (2'h0),
3729 .Mubi (1'b0)
3730 ) u_prio88 (
3731 .clk_i (clk_i),
3732 .rst_ni (rst_ni),
3733
3734 // from register interface
3735 .we (prio88_we),
3736 .wd (prio88_wd),
3737
3738 // from internal hardware
3739 .de (1'b0),
3740 .d ('0),
3741
3742 // to internal hardware
3743 .qe (),
3744 .q (reg2hw.prio88.q),
3745 .ds (),
3746
3747 // to register interface (read)
3748 .qs (prio88_qs)
3749 );
3750
3751
3752 // R[prio89]: V(False)
3753 prim_subreg #(
3754 .DW (2),
3755 .SwAccess(prim_subreg_pkg::SwAccessRW),
3756 .RESVAL (2'h0),
3757 .Mubi (1'b0)
3758 ) u_prio89 (
3759 .clk_i (clk_i),
3760 .rst_ni (rst_ni),
3761
3762 // from register interface
3763 .we (prio89_we),
3764 .wd (prio89_wd),
3765
3766 // from internal hardware
3767 .de (1'b0),
3768 .d ('0),
3769
3770 // to internal hardware
3771 .qe (),
3772 .q (reg2hw.prio89.q),
3773 .ds (),
3774
3775 // to register interface (read)
3776 .qs (prio89_qs)
3777 );
3778
3779
3780 // R[prio90]: V(False)
3781 prim_subreg #(
3782 .DW (2),
3783 .SwAccess(prim_subreg_pkg::SwAccessRW),
3784 .RESVAL (2'h0),
3785 .Mubi (1'b0)
3786 ) u_prio90 (
3787 .clk_i (clk_i),
3788 .rst_ni (rst_ni),
3789
3790 // from register interface
3791 .we (prio90_we),
3792 .wd (prio90_wd),
3793
3794 // from internal hardware
3795 .de (1'b0),
3796 .d ('0),
3797
3798 // to internal hardware
3799 .qe (),
3800 .q (reg2hw.prio90.q),
3801 .ds (),
3802
3803 // to register interface (read)
3804 .qs (prio90_qs)
3805 );
3806
3807
3808 // R[prio91]: V(False)
3809 prim_subreg #(
3810 .DW (2),
3811 .SwAccess(prim_subreg_pkg::SwAccessRW),
3812 .RESVAL (2'h0),
3813 .Mubi (1'b0)
3814 ) u_prio91 (
3815 .clk_i (clk_i),
3816 .rst_ni (rst_ni),
3817
3818 // from register interface
3819 .we (prio91_we),
3820 .wd (prio91_wd),
3821
3822 // from internal hardware
3823 .de (1'b0),
3824 .d ('0),
3825
3826 // to internal hardware
3827 .qe (),
3828 .q (reg2hw.prio91.q),
3829 .ds (),
3830
3831 // to register interface (read)
3832 .qs (prio91_qs)
3833 );
3834
3835
3836 // R[prio92]: V(False)
3837 prim_subreg #(
3838 .DW (2),
3839 .SwAccess(prim_subreg_pkg::SwAccessRW),
3840 .RESVAL (2'h0),
3841 .Mubi (1'b0)
3842 ) u_prio92 (
3843 .clk_i (clk_i),
3844 .rst_ni (rst_ni),
3845
3846 // from register interface
3847 .we (prio92_we),
3848 .wd (prio92_wd),
3849
3850 // from internal hardware
3851 .de (1'b0),
3852 .d ('0),
3853
3854 // to internal hardware
3855 .qe (),
3856 .q (reg2hw.prio92.q),
3857 .ds (),
3858
3859 // to register interface (read)
3860 .qs (prio92_qs)
3861 );
3862
3863
3864 // R[prio93]: V(False)
3865 prim_subreg #(
3866 .DW (2),
3867 .SwAccess(prim_subreg_pkg::SwAccessRW),
3868 .RESVAL (2'h0),
3869 .Mubi (1'b0)
3870 ) u_prio93 (
3871 .clk_i (clk_i),
3872 .rst_ni (rst_ni),
3873
3874 // from register interface
3875 .we (prio93_we),
3876 .wd (prio93_wd),
3877
3878 // from internal hardware
3879 .de (1'b0),
3880 .d ('0),
3881
3882 // to internal hardware
3883 .qe (),
3884 .q (reg2hw.prio93.q),
3885 .ds (),
3886
3887 // to register interface (read)
3888 .qs (prio93_qs)
3889 );
3890
3891
3892 // R[prio94]: V(False)
3893 prim_subreg #(
3894 .DW (2),
3895 .SwAccess(prim_subreg_pkg::SwAccessRW),
3896 .RESVAL (2'h0),
3897 .Mubi (1'b0)
3898 ) u_prio94 (
3899 .clk_i (clk_i),
3900 .rst_ni (rst_ni),
3901
3902 // from register interface
3903 .we (prio94_we),
3904 .wd (prio94_wd),
3905
3906 // from internal hardware
3907 .de (1'b0),
3908 .d ('0),
3909
3910 // to internal hardware
3911 .qe (),
3912 .q (reg2hw.prio94.q),
3913 .ds (),
3914
3915 // to register interface (read)
3916 .qs (prio94_qs)
3917 );
3918
3919
3920 // R[prio95]: V(False)
3921 prim_subreg #(
3922 .DW (2),
3923 .SwAccess(prim_subreg_pkg::SwAccessRW),
3924 .RESVAL (2'h0),
3925 .Mubi (1'b0)
3926 ) u_prio95 (
3927 .clk_i (clk_i),
3928 .rst_ni (rst_ni),
3929
3930 // from register interface
3931 .we (prio95_we),
3932 .wd (prio95_wd),
3933
3934 // from internal hardware
3935 .de (1'b0),
3936 .d ('0),
3937
3938 // to internal hardware
3939 .qe (),
3940 .q (reg2hw.prio95.q),
3941 .ds (),
3942
3943 // to register interface (read)
3944 .qs (prio95_qs)
3945 );
3946
3947
3948 // R[prio96]: V(False)
3949 prim_subreg #(
3950 .DW (2),
3951 .SwAccess(prim_subreg_pkg::SwAccessRW),
3952 .RESVAL (2'h0),
3953 .Mubi (1'b0)
3954 ) u_prio96 (
3955 .clk_i (clk_i),
3956 .rst_ni (rst_ni),
3957
3958 // from register interface
3959 .we (prio96_we),
3960 .wd (prio96_wd),
3961
3962 // from internal hardware
3963 .de (1'b0),
3964 .d ('0),
3965
3966 // to internal hardware
3967 .qe (),
3968 .q (reg2hw.prio96.q),
3969 .ds (),
3970
3971 // to register interface (read)
3972 .qs (prio96_qs)
3973 );
3974
3975
3976 // R[prio97]: V(False)
3977 prim_subreg #(
3978 .DW (2),
3979 .SwAccess(prim_subreg_pkg::SwAccessRW),
3980 .RESVAL (2'h0),
3981 .Mubi (1'b0)
3982 ) u_prio97 (
3983 .clk_i (clk_i),
3984 .rst_ni (rst_ni),
3985
3986 // from register interface
3987 .we (prio97_we),
3988 .wd (prio97_wd),
3989
3990 // from internal hardware
3991 .de (1'b0),
3992 .d ('0),
3993
3994 // to internal hardware
3995 .qe (),
3996 .q (reg2hw.prio97.q),
3997 .ds (),
3998
3999 // to register interface (read)
4000 .qs (prio97_qs)
4001 );
4002
4003
4004 // R[prio98]: V(False)
4005 prim_subreg #(
4006 .DW (2),
4007 .SwAccess(prim_subreg_pkg::SwAccessRW),
4008 .RESVAL (2'h0),
4009 .Mubi (1'b0)
4010 ) u_prio98 (
4011 .clk_i (clk_i),
4012 .rst_ni (rst_ni),
4013
4014 // from register interface
4015 .we (prio98_we),
4016 .wd (prio98_wd),
4017
4018 // from internal hardware
4019 .de (1'b0),
4020 .d ('0),
4021
4022 // to internal hardware
4023 .qe (),
4024 .q (reg2hw.prio98.q),
4025 .ds (),
4026
4027 // to register interface (read)
4028 .qs (prio98_qs)
4029 );
4030
4031
4032 // R[prio99]: V(False)
4033 prim_subreg #(
4034 .DW (2),
4035 .SwAccess(prim_subreg_pkg::SwAccessRW),
4036 .RESVAL (2'h0),
4037 .Mubi (1'b0)
4038 ) u_prio99 (
4039 .clk_i (clk_i),
4040 .rst_ni (rst_ni),
4041
4042 // from register interface
4043 .we (prio99_we),
4044 .wd (prio99_wd),
4045
4046 // from internal hardware
4047 .de (1'b0),
4048 .d ('0),
4049
4050 // to internal hardware
4051 .qe (),
4052 .q (reg2hw.prio99.q),
4053 .ds (),
4054
4055 // to register interface (read)
4056 .qs (prio99_qs)
4057 );
4058
4059
4060 // R[prio100]: V(False)
4061 prim_subreg #(
4062 .DW (2),
4063 .SwAccess(prim_subreg_pkg::SwAccessRW),
4064 .RESVAL (2'h0),
4065 .Mubi (1'b0)
4066 ) u_prio100 (
4067 .clk_i (clk_i),
4068 .rst_ni (rst_ni),
4069
4070 // from register interface
4071 .we (prio100_we),
4072 .wd (prio100_wd),
4073
4074 // from internal hardware
4075 .de (1'b0),
4076 .d ('0),
4077
4078 // to internal hardware
4079 .qe (),
4080 .q (reg2hw.prio100.q),
4081 .ds (),
4082
4083 // to register interface (read)
4084 .qs (prio100_qs)
4085 );
4086
4087
4088 // R[prio101]: V(False)
4089 prim_subreg #(
4090 .DW (2),
4091 .SwAccess(prim_subreg_pkg::SwAccessRW),
4092 .RESVAL (2'h0),
4093 .Mubi (1'b0)
4094 ) u_prio101 (
4095 .clk_i (clk_i),
4096 .rst_ni (rst_ni),
4097
4098 // from register interface
4099 .we (prio101_we),
4100 .wd (prio101_wd),
4101
4102 // from internal hardware
4103 .de (1'b0),
4104 .d ('0),
4105
4106 // to internal hardware
4107 .qe (),
4108 .q (reg2hw.prio101.q),
4109 .ds (),
4110
4111 // to register interface (read)
4112 .qs (prio101_qs)
4113 );
4114
4115
4116 // R[prio102]: V(False)
4117 prim_subreg #(
4118 .DW (2),
4119 .SwAccess(prim_subreg_pkg::SwAccessRW),
4120 .RESVAL (2'h0),
4121 .Mubi (1'b0)
4122 ) u_prio102 (
4123 .clk_i (clk_i),
4124 .rst_ni (rst_ni),
4125
4126 // from register interface
4127 .we (prio102_we),
4128 .wd (prio102_wd),
4129
4130 // from internal hardware
4131 .de (1'b0),
4132 .d ('0),
4133
4134 // to internal hardware
4135 .qe (),
4136 .q (reg2hw.prio102.q),
4137 .ds (),
4138
4139 // to register interface (read)
4140 .qs (prio102_qs)
4141 );
4142
4143
4144 // R[prio103]: V(False)
4145 prim_subreg #(
4146 .DW (2),
4147 .SwAccess(prim_subreg_pkg::SwAccessRW),
4148 .RESVAL (2'h0),
4149 .Mubi (1'b0)
4150 ) u_prio103 (
4151 .clk_i (clk_i),
4152 .rst_ni (rst_ni),
4153
4154 // from register interface
4155 .we (prio103_we),
4156 .wd (prio103_wd),
4157
4158 // from internal hardware
4159 .de (1'b0),
4160 .d ('0),
4161
4162 // to internal hardware
4163 .qe (),
4164 .q (reg2hw.prio103.q),
4165 .ds (),
4166
4167 // to register interface (read)
4168 .qs (prio103_qs)
4169 );
4170
4171
4172 // R[prio104]: V(False)
4173 prim_subreg #(
4174 .DW (2),
4175 .SwAccess(prim_subreg_pkg::SwAccessRW),
4176 .RESVAL (2'h0),
4177 .Mubi (1'b0)
4178 ) u_prio104 (
4179 .clk_i (clk_i),
4180 .rst_ni (rst_ni),
4181
4182 // from register interface
4183 .we (prio104_we),
4184 .wd (prio104_wd),
4185
4186 // from internal hardware
4187 .de (1'b0),
4188 .d ('0),
4189
4190 // to internal hardware
4191 .qe (),
4192 .q (reg2hw.prio104.q),
4193 .ds (),
4194
4195 // to register interface (read)
4196 .qs (prio104_qs)
4197 );
4198
4199
4200 // R[prio105]: V(False)
4201 prim_subreg #(
4202 .DW (2),
4203 .SwAccess(prim_subreg_pkg::SwAccessRW),
4204 .RESVAL (2'h0),
4205 .Mubi (1'b0)
4206 ) u_prio105 (
4207 .clk_i (clk_i),
4208 .rst_ni (rst_ni),
4209
4210 // from register interface
4211 .we (prio105_we),
4212 .wd (prio105_wd),
4213
4214 // from internal hardware
4215 .de (1'b0),
4216 .d ('0),
4217
4218 // to internal hardware
4219 .qe (),
4220 .q (reg2hw.prio105.q),
4221 .ds (),
4222
4223 // to register interface (read)
4224 .qs (prio105_qs)
4225 );
4226
4227
4228 // R[prio106]: V(False)
4229 prim_subreg #(
4230 .DW (2),
4231 .SwAccess(prim_subreg_pkg::SwAccessRW),
4232 .RESVAL (2'h0),
4233 .Mubi (1'b0)
4234 ) u_prio106 (
4235 .clk_i (clk_i),
4236 .rst_ni (rst_ni),
4237
4238 // from register interface
4239 .we (prio106_we),
4240 .wd (prio106_wd),
4241
4242 // from internal hardware
4243 .de (1'b0),
4244 .d ('0),
4245
4246 // to internal hardware
4247 .qe (),
4248 .q (reg2hw.prio106.q),
4249 .ds (),
4250
4251 // to register interface (read)
4252 .qs (prio106_qs)
4253 );
4254
4255
4256 // R[prio107]: V(False)
4257 prim_subreg #(
4258 .DW (2),
4259 .SwAccess(prim_subreg_pkg::SwAccessRW),
4260 .RESVAL (2'h0),
4261 .Mubi (1'b0)
4262 ) u_prio107 (
4263 .clk_i (clk_i),
4264 .rst_ni (rst_ni),
4265
4266 // from register interface
4267 .we (prio107_we),
4268 .wd (prio107_wd),
4269
4270 // from internal hardware
4271 .de (1'b0),
4272 .d ('0),
4273
4274 // to internal hardware
4275 .qe (),
4276 .q (reg2hw.prio107.q),
4277 .ds (),
4278
4279 // to register interface (read)
4280 .qs (prio107_qs)
4281 );
4282
4283
4284 // R[prio108]: V(False)
4285 prim_subreg #(
4286 .DW (2),
4287 .SwAccess(prim_subreg_pkg::SwAccessRW),
4288 .RESVAL (2'h0),
4289 .Mubi (1'b0)
4290 ) u_prio108 (
4291 .clk_i (clk_i),
4292 .rst_ni (rst_ni),
4293
4294 // from register interface
4295 .we (prio108_we),
4296 .wd (prio108_wd),
4297
4298 // from internal hardware
4299 .de (1'b0),
4300 .d ('0),
4301
4302 // to internal hardware
4303 .qe (),
4304 .q (reg2hw.prio108.q),
4305 .ds (),
4306
4307 // to register interface (read)
4308 .qs (prio108_qs)
4309 );
4310
4311
4312 // R[prio109]: V(False)
4313 prim_subreg #(
4314 .DW (2),
4315 .SwAccess(prim_subreg_pkg::SwAccessRW),
4316 .RESVAL (2'h0),
4317 .Mubi (1'b0)
4318 ) u_prio109 (
4319 .clk_i (clk_i),
4320 .rst_ni (rst_ni),
4321
4322 // from register interface
4323 .we (prio109_we),
4324 .wd (prio109_wd),
4325
4326 // from internal hardware
4327 .de (1'b0),
4328 .d ('0),
4329
4330 // to internal hardware
4331 .qe (),
4332 .q (reg2hw.prio109.q),
4333 .ds (),
4334
4335 // to register interface (read)
4336 .qs (prio109_qs)
4337 );
4338
4339
4340 // R[prio110]: V(False)
4341 prim_subreg #(
4342 .DW (2),
4343 .SwAccess(prim_subreg_pkg::SwAccessRW),
4344 .RESVAL (2'h0),
4345 .Mubi (1'b0)
4346 ) u_prio110 (
4347 .clk_i (clk_i),
4348 .rst_ni (rst_ni),
4349
4350 // from register interface
4351 .we (prio110_we),
4352 .wd (prio110_wd),
4353
4354 // from internal hardware
4355 .de (1'b0),
4356 .d ('0),
4357
4358 // to internal hardware
4359 .qe (),
4360 .q (reg2hw.prio110.q),
4361 .ds (),
4362
4363 // to register interface (read)
4364 .qs (prio110_qs)
4365 );
4366
4367
4368 // R[prio111]: V(False)
4369 prim_subreg #(
4370 .DW (2),
4371 .SwAccess(prim_subreg_pkg::SwAccessRW),
4372 .RESVAL (2'h0),
4373 .Mubi (1'b0)
4374 ) u_prio111 (
4375 .clk_i (clk_i),
4376 .rst_ni (rst_ni),
4377
4378 // from register interface
4379 .we (prio111_we),
4380 .wd (prio111_wd),
4381
4382 // from internal hardware
4383 .de (1'b0),
4384 .d ('0),
4385
4386 // to internal hardware
4387 .qe (),
4388 .q (reg2hw.prio111.q),
4389 .ds (),
4390
4391 // to register interface (read)
4392 .qs (prio111_qs)
4393 );
4394
4395
4396 // R[prio112]: V(False)
4397 prim_subreg #(
4398 .DW (2),
4399 .SwAccess(prim_subreg_pkg::SwAccessRW),
4400 .RESVAL (2'h0),
4401 .Mubi (1'b0)
4402 ) u_prio112 (
4403 .clk_i (clk_i),
4404 .rst_ni (rst_ni),
4405
4406 // from register interface
4407 .we (prio112_we),
4408 .wd (prio112_wd),
4409
4410 // from internal hardware
4411 .de (1'b0),
4412 .d ('0),
4413
4414 // to internal hardware
4415 .qe (),
4416 .q (reg2hw.prio112.q),
4417 .ds (),
4418
4419 // to register interface (read)
4420 .qs (prio112_qs)
4421 );
4422
4423
4424 // R[prio113]: V(False)
4425 prim_subreg #(
4426 .DW (2),
4427 .SwAccess(prim_subreg_pkg::SwAccessRW),
4428 .RESVAL (2'h0),
4429 .Mubi (1'b0)
4430 ) u_prio113 (
4431 .clk_i (clk_i),
4432 .rst_ni (rst_ni),
4433
4434 // from register interface
4435 .we (prio113_we),
4436 .wd (prio113_wd),
4437
4438 // from internal hardware
4439 .de (1'b0),
4440 .d ('0),
4441
4442 // to internal hardware
4443 .qe (),
4444 .q (reg2hw.prio113.q),
4445 .ds (),
4446
4447 // to register interface (read)
4448 .qs (prio113_qs)
4449 );
4450
4451
4452 // R[prio114]: V(False)
4453 prim_subreg #(
4454 .DW (2),
4455 .SwAccess(prim_subreg_pkg::SwAccessRW),
4456 .RESVAL (2'h0),
4457 .Mubi (1'b0)
4458 ) u_prio114 (
4459 .clk_i (clk_i),
4460 .rst_ni (rst_ni),
4461
4462 // from register interface
4463 .we (prio114_we),
4464 .wd (prio114_wd),
4465
4466 // from internal hardware
4467 .de (1'b0),
4468 .d ('0),
4469
4470 // to internal hardware
4471 .qe (),
4472 .q (reg2hw.prio114.q),
4473 .ds (),
4474
4475 // to register interface (read)
4476 .qs (prio114_qs)
4477 );
4478
4479
4480 // R[prio115]: V(False)
4481 prim_subreg #(
4482 .DW (2),
4483 .SwAccess(prim_subreg_pkg::SwAccessRW),
4484 .RESVAL (2'h0),
4485 .Mubi (1'b0)
4486 ) u_prio115 (
4487 .clk_i (clk_i),
4488 .rst_ni (rst_ni),
4489
4490 // from register interface
4491 .we (prio115_we),
4492 .wd (prio115_wd),
4493
4494 // from internal hardware
4495 .de (1'b0),
4496 .d ('0),
4497
4498 // to internal hardware
4499 .qe (),
4500 .q (reg2hw.prio115.q),
4501 .ds (),
4502
4503 // to register interface (read)
4504 .qs (prio115_qs)
4505 );
4506
4507
4508 // R[prio116]: V(False)
4509 prim_subreg #(
4510 .DW (2),
4511 .SwAccess(prim_subreg_pkg::SwAccessRW),
4512 .RESVAL (2'h0),
4513 .Mubi (1'b0)
4514 ) u_prio116 (
4515 .clk_i (clk_i),
4516 .rst_ni (rst_ni),
4517
4518 // from register interface
4519 .we (prio116_we),
4520 .wd (prio116_wd),
4521
4522 // from internal hardware
4523 .de (1'b0),
4524 .d ('0),
4525
4526 // to internal hardware
4527 .qe (),
4528 .q (reg2hw.prio116.q),
4529 .ds (),
4530
4531 // to register interface (read)
4532 .qs (prio116_qs)
4533 );
4534
4535
4536 // R[prio117]: V(False)
4537 prim_subreg #(
4538 .DW (2),
4539 .SwAccess(prim_subreg_pkg::SwAccessRW),
4540 .RESVAL (2'h0),
4541 .Mubi (1'b0)
4542 ) u_prio117 (
4543 .clk_i (clk_i),
4544 .rst_ni (rst_ni),
4545
4546 // from register interface
4547 .we (prio117_we),
4548 .wd (prio117_wd),
4549
4550 // from internal hardware
4551 .de (1'b0),
4552 .d ('0),
4553
4554 // to internal hardware
4555 .qe (),
4556 .q (reg2hw.prio117.q),
4557 .ds (),
4558
4559 // to register interface (read)
4560 .qs (prio117_qs)
4561 );
4562
4563
4564 // R[prio118]: V(False)
4565 prim_subreg #(
4566 .DW (2),
4567 .SwAccess(prim_subreg_pkg::SwAccessRW),
4568 .RESVAL (2'h0),
4569 .Mubi (1'b0)
4570 ) u_prio118 (
4571 .clk_i (clk_i),
4572 .rst_ni (rst_ni),
4573
4574 // from register interface
4575 .we (prio118_we),
4576 .wd (prio118_wd),
4577
4578 // from internal hardware
4579 .de (1'b0),
4580 .d ('0),
4581
4582 // to internal hardware
4583 .qe (),
4584 .q (reg2hw.prio118.q),
4585 .ds (),
4586
4587 // to register interface (read)
4588 .qs (prio118_qs)
4589 );
4590
4591
4592 // R[prio119]: V(False)
4593 prim_subreg #(
4594 .DW (2),
4595 .SwAccess(prim_subreg_pkg::SwAccessRW),
4596 .RESVAL (2'h0),
4597 .Mubi (1'b0)
4598 ) u_prio119 (
4599 .clk_i (clk_i),
4600 .rst_ni (rst_ni),
4601
4602 // from register interface
4603 .we (prio119_we),
4604 .wd (prio119_wd),
4605
4606 // from internal hardware
4607 .de (1'b0),
4608 .d ('0),
4609
4610 // to internal hardware
4611 .qe (),
4612 .q (reg2hw.prio119.q),
4613 .ds (),
4614
4615 // to register interface (read)
4616 .qs (prio119_qs)
4617 );
4618
4619
4620 // R[prio120]: V(False)
4621 prim_subreg #(
4622 .DW (2),
4623 .SwAccess(prim_subreg_pkg::SwAccessRW),
4624 .RESVAL (2'h0),
4625 .Mubi (1'b0)
4626 ) u_prio120 (
4627 .clk_i (clk_i),
4628 .rst_ni (rst_ni),
4629
4630 // from register interface
4631 .we (prio120_we),
4632 .wd (prio120_wd),
4633
4634 // from internal hardware
4635 .de (1'b0),
4636 .d ('0),
4637
4638 // to internal hardware
4639 .qe (),
4640 .q (reg2hw.prio120.q),
4641 .ds (),
4642
4643 // to register interface (read)
4644 .qs (prio120_qs)
4645 );
4646
4647
4648 // R[prio121]: V(False)
4649 prim_subreg #(
4650 .DW (2),
4651 .SwAccess(prim_subreg_pkg::SwAccessRW),
4652 .RESVAL (2'h0),
4653 .Mubi (1'b0)
4654 ) u_prio121 (
4655 .clk_i (clk_i),
4656 .rst_ni (rst_ni),
4657
4658 // from register interface
4659 .we (prio121_we),
4660 .wd (prio121_wd),
4661
4662 // from internal hardware
4663 .de (1'b0),
4664 .d ('0),
4665
4666 // to internal hardware
4667 .qe (),
4668 .q (reg2hw.prio121.q),
4669 .ds (),
4670
4671 // to register interface (read)
4672 .qs (prio121_qs)
4673 );
4674
4675
4676 // R[prio122]: V(False)
4677 prim_subreg #(
4678 .DW (2),
4679 .SwAccess(prim_subreg_pkg::SwAccessRW),
4680 .RESVAL (2'h0),
4681 .Mubi (1'b0)
4682 ) u_prio122 (
4683 .clk_i (clk_i),
4684 .rst_ni (rst_ni),
4685
4686 // from register interface
4687 .we (prio122_we),
4688 .wd (prio122_wd),
4689
4690 // from internal hardware
4691 .de (1'b0),
4692 .d ('0),
4693
4694 // to internal hardware
4695 .qe (),
4696 .q (reg2hw.prio122.q),
4697 .ds (),
4698
4699 // to register interface (read)
4700 .qs (prio122_qs)
4701 );
4702
4703
4704 // R[prio123]: V(False)
4705 prim_subreg #(
4706 .DW (2),
4707 .SwAccess(prim_subreg_pkg::SwAccessRW),
4708 .RESVAL (2'h0),
4709 .Mubi (1'b0)
4710 ) u_prio123 (
4711 .clk_i (clk_i),
4712 .rst_ni (rst_ni),
4713
4714 // from register interface
4715 .we (prio123_we),
4716 .wd (prio123_wd),
4717
4718 // from internal hardware
4719 .de (1'b0),
4720 .d ('0),
4721
4722 // to internal hardware
4723 .qe (),
4724 .q (reg2hw.prio123.q),
4725 .ds (),
4726
4727 // to register interface (read)
4728 .qs (prio123_qs)
4729 );
4730
4731
4732 // R[prio124]: V(False)
4733 prim_subreg #(
4734 .DW (2),
4735 .SwAccess(prim_subreg_pkg::SwAccessRW),
4736 .RESVAL (2'h0),
4737 .Mubi (1'b0)
4738 ) u_prio124 (
4739 .clk_i (clk_i),
4740 .rst_ni (rst_ni),
4741
4742 // from register interface
4743 .we (prio124_we),
4744 .wd (prio124_wd),
4745
4746 // from internal hardware
4747 .de (1'b0),
4748 .d ('0),
4749
4750 // to internal hardware
4751 .qe (),
4752 .q (reg2hw.prio124.q),
4753 .ds (),
4754
4755 // to register interface (read)
4756 .qs (prio124_qs)
4757 );
4758
4759
4760 // R[prio125]: V(False)
4761 prim_subreg #(
4762 .DW (2),
4763 .SwAccess(prim_subreg_pkg::SwAccessRW),
4764 .RESVAL (2'h0),
4765 .Mubi (1'b0)
4766 ) u_prio125 (
4767 .clk_i (clk_i),
4768 .rst_ni (rst_ni),
4769
4770 // from register interface
4771 .we (prio125_we),
4772 .wd (prio125_wd),
4773
4774 // from internal hardware
4775 .de (1'b0),
4776 .d ('0),
4777
4778 // to internal hardware
4779 .qe (),
4780 .q (reg2hw.prio125.q),
4781 .ds (),
4782
4783 // to register interface (read)
4784 .qs (prio125_qs)
4785 );
4786
4787
4788 // R[prio126]: V(False)
4789 prim_subreg #(
4790 .DW (2),
4791 .SwAccess(prim_subreg_pkg::SwAccessRW),
4792 .RESVAL (2'h0),
4793 .Mubi (1'b0)
4794 ) u_prio126 (
4795 .clk_i (clk_i),
4796 .rst_ni (rst_ni),
4797
4798 // from register interface
4799 .we (prio126_we),
4800 .wd (prio126_wd),
4801
4802 // from internal hardware
4803 .de (1'b0),
4804 .d ('0),
4805
4806 // to internal hardware
4807 .qe (),
4808 .q (reg2hw.prio126.q),
4809 .ds (),
4810
4811 // to register interface (read)
4812 .qs (prio126_qs)
4813 );
4814
4815
4816 // R[prio127]: V(False)
4817 prim_subreg #(
4818 .DW (2),
4819 .SwAccess(prim_subreg_pkg::SwAccessRW),
4820 .RESVAL (2'h0),
4821 .Mubi (1'b0)
4822 ) u_prio127 (
4823 .clk_i (clk_i),
4824 .rst_ni (rst_ni),
4825
4826 // from register interface
4827 .we (prio127_we),
4828 .wd (prio127_wd),
4829
4830 // from internal hardware
4831 .de (1'b0),
4832 .d ('0),
4833
4834 // to internal hardware
4835 .qe (),
4836 .q (reg2hw.prio127.q),
4837 .ds (),
4838
4839 // to register interface (read)
4840 .qs (prio127_qs)
4841 );
4842
4843
4844 // R[prio128]: V(False)
4845 prim_subreg #(
4846 .DW (2),
4847 .SwAccess(prim_subreg_pkg::SwAccessRW),
4848 .RESVAL (2'h0),
4849 .Mubi (1'b0)
4850 ) u_prio128 (
4851 .clk_i (clk_i),
4852 .rst_ni (rst_ni),
4853
4854 // from register interface
4855 .we (prio128_we),
4856 .wd (prio128_wd),
4857
4858 // from internal hardware
4859 .de (1'b0),
4860 .d ('0),
4861
4862 // to internal hardware
4863 .qe (),
4864 .q (reg2hw.prio128.q),
4865 .ds (),
4866
4867 // to register interface (read)
4868 .qs (prio128_qs)
4869 );
4870
4871
4872 // R[prio129]: V(False)
4873 prim_subreg #(
4874 .DW (2),
4875 .SwAccess(prim_subreg_pkg::SwAccessRW),
4876 .RESVAL (2'h0),
4877 .Mubi (1'b0)
4878 ) u_prio129 (
4879 .clk_i (clk_i),
4880 .rst_ni (rst_ni),
4881
4882 // from register interface
4883 .we (prio129_we),
4884 .wd (prio129_wd),
4885
4886 // from internal hardware
4887 .de (1'b0),
4888 .d ('0),
4889
4890 // to internal hardware
4891 .qe (),
4892 .q (reg2hw.prio129.q),
4893 .ds (),
4894
4895 // to register interface (read)
4896 .qs (prio129_qs)
4897 );
4898
4899
4900 // R[prio130]: V(False)
4901 prim_subreg #(
4902 .DW (2),
4903 .SwAccess(prim_subreg_pkg::SwAccessRW),
4904 .RESVAL (2'h0),
4905 .Mubi (1'b0)
4906 ) u_prio130 (
4907 .clk_i (clk_i),
4908 .rst_ni (rst_ni),
4909
4910 // from register interface
4911 .we (prio130_we),
4912 .wd (prio130_wd),
4913
4914 // from internal hardware
4915 .de (1'b0),
4916 .d ('0),
4917
4918 // to internal hardware
4919 .qe (),
4920 .q (reg2hw.prio130.q),
4921 .ds (),
4922
4923 // to register interface (read)
4924 .qs (prio130_qs)
4925 );
4926
4927
4928 // R[prio131]: V(False)
4929 prim_subreg #(
4930 .DW (2),
4931 .SwAccess(prim_subreg_pkg::SwAccessRW),
4932 .RESVAL (2'h0),
4933 .Mubi (1'b0)
4934 ) u_prio131 (
4935 .clk_i (clk_i),
4936 .rst_ni (rst_ni),
4937
4938 // from register interface
4939 .we (prio131_we),
4940 .wd (prio131_wd),
4941
4942 // from internal hardware
4943 .de (1'b0),
4944 .d ('0),
4945
4946 // to internal hardware
4947 .qe (),
4948 .q (reg2hw.prio131.q),
4949 .ds (),
4950
4951 // to register interface (read)
4952 .qs (prio131_qs)
4953 );
4954
4955
4956 // R[prio132]: V(False)
4957 prim_subreg #(
4958 .DW (2),
4959 .SwAccess(prim_subreg_pkg::SwAccessRW),
4960 .RESVAL (2'h0),
4961 .Mubi (1'b0)
4962 ) u_prio132 (
4963 .clk_i (clk_i),
4964 .rst_ni (rst_ni),
4965
4966 // from register interface
4967 .we (prio132_we),
4968 .wd (prio132_wd),
4969
4970 // from internal hardware
4971 .de (1'b0),
4972 .d ('0),
4973
4974 // to internal hardware
4975 .qe (),
4976 .q (reg2hw.prio132.q),
4977 .ds (),
4978
4979 // to register interface (read)
4980 .qs (prio132_qs)
4981 );
4982
4983
4984 // R[prio133]: V(False)
4985 prim_subreg #(
4986 .DW (2),
4987 .SwAccess(prim_subreg_pkg::SwAccessRW),
4988 .RESVAL (2'h0),
4989 .Mubi (1'b0)
4990 ) u_prio133 (
4991 .clk_i (clk_i),
4992 .rst_ni (rst_ni),
4993
4994 // from register interface
4995 .we (prio133_we),
4996 .wd (prio133_wd),
4997
4998 // from internal hardware
4999 .de (1'b0),
5000 .d ('0),
5001
5002 // to internal hardware
5003 .qe (),
5004 .q (reg2hw.prio133.q),
5005 .ds (),
5006
5007 // to register interface (read)
5008 .qs (prio133_qs)
5009 );
5010
5011
5012 // R[prio134]: V(False)
5013 prim_subreg #(
5014 .DW (2),
5015 .SwAccess(prim_subreg_pkg::SwAccessRW),
5016 .RESVAL (2'h0),
5017 .Mubi (1'b0)
5018 ) u_prio134 (
5019 .clk_i (clk_i),
5020 .rst_ni (rst_ni),
5021
5022 // from register interface
5023 .we (prio134_we),
5024 .wd (prio134_wd),
5025
5026 // from internal hardware
5027 .de (1'b0),
5028 .d ('0),
5029
5030 // to internal hardware
5031 .qe (),
5032 .q (reg2hw.prio134.q),
5033 .ds (),
5034
5035 // to register interface (read)
5036 .qs (prio134_qs)
5037 );
5038
5039
5040 // R[prio135]: V(False)
5041 prim_subreg #(
5042 .DW (2),
5043 .SwAccess(prim_subreg_pkg::SwAccessRW),
5044 .RESVAL (2'h0),
5045 .Mubi (1'b0)
5046 ) u_prio135 (
5047 .clk_i (clk_i),
5048 .rst_ni (rst_ni),
5049
5050 // from register interface
5051 .we (prio135_we),
5052 .wd (prio135_wd),
5053
5054 // from internal hardware
5055 .de (1'b0),
5056 .d ('0),
5057
5058 // to internal hardware
5059 .qe (),
5060 .q (reg2hw.prio135.q),
5061 .ds (),
5062
5063 // to register interface (read)
5064 .qs (prio135_qs)
5065 );
5066
5067
5068 // R[prio136]: V(False)
5069 prim_subreg #(
5070 .DW (2),
5071 .SwAccess(prim_subreg_pkg::SwAccessRW),
5072 .RESVAL (2'h0),
5073 .Mubi (1'b0)
5074 ) u_prio136 (
5075 .clk_i (clk_i),
5076 .rst_ni (rst_ni),
5077
5078 // from register interface
5079 .we (prio136_we),
5080 .wd (prio136_wd),
5081
5082 // from internal hardware
5083 .de (1'b0),
5084 .d ('0),
5085
5086 // to internal hardware
5087 .qe (),
5088 .q (reg2hw.prio136.q),
5089 .ds (),
5090
5091 // to register interface (read)
5092 .qs (prio136_qs)
5093 );
5094
5095
5096 // R[prio137]: V(False)
5097 prim_subreg #(
5098 .DW (2),
5099 .SwAccess(prim_subreg_pkg::SwAccessRW),
5100 .RESVAL (2'h0),
5101 .Mubi (1'b0)
5102 ) u_prio137 (
5103 .clk_i (clk_i),
5104 .rst_ni (rst_ni),
5105
5106 // from register interface
5107 .we (prio137_we),
5108 .wd (prio137_wd),
5109
5110 // from internal hardware
5111 .de (1'b0),
5112 .d ('0),
5113
5114 // to internal hardware
5115 .qe (),
5116 .q (reg2hw.prio137.q),
5117 .ds (),
5118
5119 // to register interface (read)
5120 .qs (prio137_qs)
5121 );
5122
5123
5124 // R[prio138]: V(False)
5125 prim_subreg #(
5126 .DW (2),
5127 .SwAccess(prim_subreg_pkg::SwAccessRW),
5128 .RESVAL (2'h0),
5129 .Mubi (1'b0)
5130 ) u_prio138 (
5131 .clk_i (clk_i),
5132 .rst_ni (rst_ni),
5133
5134 // from register interface
5135 .we (prio138_we),
5136 .wd (prio138_wd),
5137
5138 // from internal hardware
5139 .de (1'b0),
5140 .d ('0),
5141
5142 // to internal hardware
5143 .qe (),
5144 .q (reg2hw.prio138.q),
5145 .ds (),
5146
5147 // to register interface (read)
5148 .qs (prio138_qs)
5149 );
5150
5151
5152 // R[prio139]: V(False)
5153 prim_subreg #(
5154 .DW (2),
5155 .SwAccess(prim_subreg_pkg::SwAccessRW),
5156 .RESVAL (2'h0),
5157 .Mubi (1'b0)
5158 ) u_prio139 (
5159 .clk_i (clk_i),
5160 .rst_ni (rst_ni),
5161
5162 // from register interface
5163 .we (prio139_we),
5164 .wd (prio139_wd),
5165
5166 // from internal hardware
5167 .de (1'b0),
5168 .d ('0),
5169
5170 // to internal hardware
5171 .qe (),
5172 .q (reg2hw.prio139.q),
5173 .ds (),
5174
5175 // to register interface (read)
5176 .qs (prio139_qs)
5177 );
5178
5179
5180 // R[prio140]: V(False)
5181 prim_subreg #(
5182 .DW (2),
5183 .SwAccess(prim_subreg_pkg::SwAccessRW),
5184 .RESVAL (2'h0),
5185 .Mubi (1'b0)
5186 ) u_prio140 (
5187 .clk_i (clk_i),
5188 .rst_ni (rst_ni),
5189
5190 // from register interface
5191 .we (prio140_we),
5192 .wd (prio140_wd),
5193
5194 // from internal hardware
5195 .de (1'b0),
5196 .d ('0),
5197
5198 // to internal hardware
5199 .qe (),
5200 .q (reg2hw.prio140.q),
5201 .ds (),
5202
5203 // to register interface (read)
5204 .qs (prio140_qs)
5205 );
5206
5207
5208 // R[prio141]: V(False)
5209 prim_subreg #(
5210 .DW (2),
5211 .SwAccess(prim_subreg_pkg::SwAccessRW),
5212 .RESVAL (2'h0),
5213 .Mubi (1'b0)
5214 ) u_prio141 (
5215 .clk_i (clk_i),
5216 .rst_ni (rst_ni),
5217
5218 // from register interface
5219 .we (prio141_we),
5220 .wd (prio141_wd),
5221
5222 // from internal hardware
5223 .de (1'b0),
5224 .d ('0),
5225
5226 // to internal hardware
5227 .qe (),
5228 .q (reg2hw.prio141.q),
5229 .ds (),
5230
5231 // to register interface (read)
5232 .qs (prio141_qs)
5233 );
5234
5235
5236 // R[prio142]: V(False)
5237 prim_subreg #(
5238 .DW (2),
5239 .SwAccess(prim_subreg_pkg::SwAccessRW),
5240 .RESVAL (2'h0),
5241 .Mubi (1'b0)
5242 ) u_prio142 (
5243 .clk_i (clk_i),
5244 .rst_ni (rst_ni),
5245
5246 // from register interface
5247 .we (prio142_we),
5248 .wd (prio142_wd),
5249
5250 // from internal hardware
5251 .de (1'b0),
5252 .d ('0),
5253
5254 // to internal hardware
5255 .qe (),
5256 .q (reg2hw.prio142.q),
5257 .ds (),
5258
5259 // to register interface (read)
5260 .qs (prio142_qs)
5261 );
5262
5263
5264 // R[prio143]: V(False)
5265 prim_subreg #(
5266 .DW (2),
5267 .SwAccess(prim_subreg_pkg::SwAccessRW),
5268 .RESVAL (2'h0),
5269 .Mubi (1'b0)
5270 ) u_prio143 (
5271 .clk_i (clk_i),
5272 .rst_ni (rst_ni),
5273
5274 // from register interface
5275 .we (prio143_we),
5276 .wd (prio143_wd),
5277
5278 // from internal hardware
5279 .de (1'b0),
5280 .d ('0),
5281
5282 // to internal hardware
5283 .qe (),
5284 .q (reg2hw.prio143.q),
5285 .ds (),
5286
5287 // to register interface (read)
5288 .qs (prio143_qs)
5289 );
5290
5291
5292 // R[prio144]: V(False)
5293 prim_subreg #(
5294 .DW (2),
5295 .SwAccess(prim_subreg_pkg::SwAccessRW),
5296 .RESVAL (2'h0),
5297 .Mubi (1'b0)
5298 ) u_prio144 (
5299 .clk_i (clk_i),
5300 .rst_ni (rst_ni),
5301
5302 // from register interface
5303 .we (prio144_we),
5304 .wd (prio144_wd),
5305
5306 // from internal hardware
5307 .de (1'b0),
5308 .d ('0),
5309
5310 // to internal hardware
5311 .qe (),
5312 .q (reg2hw.prio144.q),
5313 .ds (),
5314
5315 // to register interface (read)
5316 .qs (prio144_qs)
5317 );
5318
5319
5320 // R[prio145]: V(False)
5321 prim_subreg #(
5322 .DW (2),
5323 .SwAccess(prim_subreg_pkg::SwAccessRW),
5324 .RESVAL (2'h0),
5325 .Mubi (1'b0)
5326 ) u_prio145 (
5327 .clk_i (clk_i),
5328 .rst_ni (rst_ni),
5329
5330 // from register interface
5331 .we (prio145_we),
5332 .wd (prio145_wd),
5333
5334 // from internal hardware
5335 .de (1'b0),
5336 .d ('0),
5337
5338 // to internal hardware
5339 .qe (),
5340 .q (reg2hw.prio145.q),
5341 .ds (),
5342
5343 // to register interface (read)
5344 .qs (prio145_qs)
5345 );
5346
5347
5348 // R[prio146]: V(False)
5349 prim_subreg #(
5350 .DW (2),
5351 .SwAccess(prim_subreg_pkg::SwAccessRW),
5352 .RESVAL (2'h0),
5353 .Mubi (1'b0)
5354 ) u_prio146 (
5355 .clk_i (clk_i),
5356 .rst_ni (rst_ni),
5357
5358 // from register interface
5359 .we (prio146_we),
5360 .wd (prio146_wd),
5361
5362 // from internal hardware
5363 .de (1'b0),
5364 .d ('0),
5365
5366 // to internal hardware
5367 .qe (),
5368 .q (reg2hw.prio146.q),
5369 .ds (),
5370
5371 // to register interface (read)
5372 .qs (prio146_qs)
5373 );
5374
5375
5376 // R[prio147]: V(False)
5377 prim_subreg #(
5378 .DW (2),
5379 .SwAccess(prim_subreg_pkg::SwAccessRW),
5380 .RESVAL (2'h0),
5381 .Mubi (1'b0)
5382 ) u_prio147 (
5383 .clk_i (clk_i),
5384 .rst_ni (rst_ni),
5385
5386 // from register interface
5387 .we (prio147_we),
5388 .wd (prio147_wd),
5389
5390 // from internal hardware
5391 .de (1'b0),
5392 .d ('0),
5393
5394 // to internal hardware
5395 .qe (),
5396 .q (reg2hw.prio147.q),
5397 .ds (),
5398
5399 // to register interface (read)
5400 .qs (prio147_qs)
5401 );
5402
5403
5404 // R[prio148]: V(False)
5405 prim_subreg #(
5406 .DW (2),
5407 .SwAccess(prim_subreg_pkg::SwAccessRW),
5408 .RESVAL (2'h0),
5409 .Mubi (1'b0)
5410 ) u_prio148 (
5411 .clk_i (clk_i),
5412 .rst_ni (rst_ni),
5413
5414 // from register interface
5415 .we (prio148_we),
5416 .wd (prio148_wd),
5417
5418 // from internal hardware
5419 .de (1'b0),
5420 .d ('0),
5421
5422 // to internal hardware
5423 .qe (),
5424 .q (reg2hw.prio148.q),
5425 .ds (),
5426
5427 // to register interface (read)
5428 .qs (prio148_qs)
5429 );
5430
5431
5432 // R[prio149]: V(False)
5433 prim_subreg #(
5434 .DW (2),
5435 .SwAccess(prim_subreg_pkg::SwAccessRW),
5436 .RESVAL (2'h0),
5437 .Mubi (1'b0)
5438 ) u_prio149 (
5439 .clk_i (clk_i),
5440 .rst_ni (rst_ni),
5441
5442 // from register interface
5443 .we (prio149_we),
5444 .wd (prio149_wd),
5445
5446 // from internal hardware
5447 .de (1'b0),
5448 .d ('0),
5449
5450 // to internal hardware
5451 .qe (),
5452 .q (reg2hw.prio149.q),
5453 .ds (),
5454
5455 // to register interface (read)
5456 .qs (prio149_qs)
5457 );
5458
5459
5460 // R[prio150]: V(False)
5461 prim_subreg #(
5462 .DW (2),
5463 .SwAccess(prim_subreg_pkg::SwAccessRW),
5464 .RESVAL (2'h0),
5465 .Mubi (1'b0)
5466 ) u_prio150 (
5467 .clk_i (clk_i),
5468 .rst_ni (rst_ni),
5469
5470 // from register interface
5471 .we (prio150_we),
5472 .wd (prio150_wd),
5473
5474 // from internal hardware
5475 .de (1'b0),
5476 .d ('0),
5477
5478 // to internal hardware
5479 .qe (),
5480 .q (reg2hw.prio150.q),
5481 .ds (),
5482
5483 // to register interface (read)
5484 .qs (prio150_qs)
5485 );
5486
5487
5488 // R[prio151]: V(False)
5489 prim_subreg #(
5490 .DW (2),
5491 .SwAccess(prim_subreg_pkg::SwAccessRW),
5492 .RESVAL (2'h0),
5493 .Mubi (1'b0)
5494 ) u_prio151 (
5495 .clk_i (clk_i),
5496 .rst_ni (rst_ni),
5497
5498 // from register interface
5499 .we (prio151_we),
5500 .wd (prio151_wd),
5501
5502 // from internal hardware
5503 .de (1'b0),
5504 .d ('0),
5505
5506 // to internal hardware
5507 .qe (),
5508 .q (reg2hw.prio151.q),
5509 .ds (),
5510
5511 // to register interface (read)
5512 .qs (prio151_qs)
5513 );
5514
5515
5516 // R[prio152]: V(False)
5517 prim_subreg #(
5518 .DW (2),
5519 .SwAccess(prim_subreg_pkg::SwAccessRW),
5520 .RESVAL (2'h0),
5521 .Mubi (1'b0)
5522 ) u_prio152 (
5523 .clk_i (clk_i),
5524 .rst_ni (rst_ni),
5525
5526 // from register interface
5527 .we (prio152_we),
5528 .wd (prio152_wd),
5529
5530 // from internal hardware
5531 .de (1'b0),
5532 .d ('0),
5533
5534 // to internal hardware
5535 .qe (),
5536 .q (reg2hw.prio152.q),
5537 .ds (),
5538
5539 // to register interface (read)
5540 .qs (prio152_qs)
5541 );
5542
5543
5544 // R[prio153]: V(False)
5545 prim_subreg #(
5546 .DW (2),
5547 .SwAccess(prim_subreg_pkg::SwAccessRW),
5548 .RESVAL (2'h0),
5549 .Mubi (1'b0)
5550 ) u_prio153 (
5551 .clk_i (clk_i),
5552 .rst_ni (rst_ni),
5553
5554 // from register interface
5555 .we (prio153_we),
5556 .wd (prio153_wd),
5557
5558 // from internal hardware
5559 .de (1'b0),
5560 .d ('0),
5561
5562 // to internal hardware
5563 .qe (),
5564 .q (reg2hw.prio153.q),
5565 .ds (),
5566
5567 // to register interface (read)
5568 .qs (prio153_qs)
5569 );
5570
5571
5572 // R[prio154]: V(False)
5573 prim_subreg #(
5574 .DW (2),
5575 .SwAccess(prim_subreg_pkg::SwAccessRW),
5576 .RESVAL (2'h0),
5577 .Mubi (1'b0)
5578 ) u_prio154 (
5579 .clk_i (clk_i),
5580 .rst_ni (rst_ni),
5581
5582 // from register interface
5583 .we (prio154_we),
5584 .wd (prio154_wd),
5585
5586 // from internal hardware
5587 .de (1'b0),
5588 .d ('0),
5589
5590 // to internal hardware
5591 .qe (),
5592 .q (reg2hw.prio154.q),
5593 .ds (),
5594
5595 // to register interface (read)
5596 .qs (prio154_qs)
5597 );
5598
5599
5600 // R[prio155]: V(False)
5601 prim_subreg #(
5602 .DW (2),
5603 .SwAccess(prim_subreg_pkg::SwAccessRW),
5604 .RESVAL (2'h0),
5605 .Mubi (1'b0)
5606 ) u_prio155 (
5607 .clk_i (clk_i),
5608 .rst_ni (rst_ni),
5609
5610 // from register interface
5611 .we (prio155_we),
5612 .wd (prio155_wd),
5613
5614 // from internal hardware
5615 .de (1'b0),
5616 .d ('0),
5617
5618 // to internal hardware
5619 .qe (),
5620 .q (reg2hw.prio155.q),
5621 .ds (),
5622
5623 // to register interface (read)
5624 .qs (prio155_qs)
5625 );
5626
5627
5628 // R[prio156]: V(False)
5629 prim_subreg #(
5630 .DW (2),
5631 .SwAccess(prim_subreg_pkg::SwAccessRW),
5632 .RESVAL (2'h0),
5633 .Mubi (1'b0)
5634 ) u_prio156 (
5635 .clk_i (clk_i),
5636 .rst_ni (rst_ni),
5637
5638 // from register interface
5639 .we (prio156_we),
5640 .wd (prio156_wd),
5641
5642 // from internal hardware
5643 .de (1'b0),
5644 .d ('0),
5645
5646 // to internal hardware
5647 .qe (),
5648 .q (reg2hw.prio156.q),
5649 .ds (),
5650
5651 // to register interface (read)
5652 .qs (prio156_qs)
5653 );
5654
5655
5656 // R[prio157]: V(False)
5657 prim_subreg #(
5658 .DW (2),
5659 .SwAccess(prim_subreg_pkg::SwAccessRW),
5660 .RESVAL (2'h0),
5661 .Mubi (1'b0)
5662 ) u_prio157 (
5663 .clk_i (clk_i),
5664 .rst_ni (rst_ni),
5665
5666 // from register interface
5667 .we (prio157_we),
5668 .wd (prio157_wd),
5669
5670 // from internal hardware
5671 .de (1'b0),
5672 .d ('0),
5673
5674 // to internal hardware
5675 .qe (),
5676 .q (reg2hw.prio157.q),
5677 .ds (),
5678
5679 // to register interface (read)
5680 .qs (prio157_qs)
5681 );
5682
5683
5684 // R[prio158]: V(False)
5685 prim_subreg #(
5686 .DW (2),
5687 .SwAccess(prim_subreg_pkg::SwAccessRW),
5688 .RESVAL (2'h0),
5689 .Mubi (1'b0)
5690 ) u_prio158 (
5691 .clk_i (clk_i),
5692 .rst_ni (rst_ni),
5693
5694 // from register interface
5695 .we (prio158_we),
5696 .wd (prio158_wd),
5697
5698 // from internal hardware
5699 .de (1'b0),
5700 .d ('0),
5701
5702 // to internal hardware
5703 .qe (),
5704 .q (reg2hw.prio158.q),
5705 .ds (),
5706
5707 // to register interface (read)
5708 .qs (prio158_qs)
5709 );
5710
5711
5712 // R[prio159]: V(False)
5713 prim_subreg #(
5714 .DW (2),
5715 .SwAccess(prim_subreg_pkg::SwAccessRW),
5716 .RESVAL (2'h0),
5717 .Mubi (1'b0)
5718 ) u_prio159 (
5719 .clk_i (clk_i),
5720 .rst_ni (rst_ni),
5721
5722 // from register interface
5723 .we (prio159_we),
5724 .wd (prio159_wd),
5725
5726 // from internal hardware
5727 .de (1'b0),
5728 .d ('0),
5729
5730 // to internal hardware
5731 .qe (),
5732 .q (reg2hw.prio159.q),
5733 .ds (),
5734
5735 // to register interface (read)
5736 .qs (prio159_qs)
5737 );
5738
5739
5740 // R[prio160]: V(False)
5741 prim_subreg #(
5742 .DW (2),
5743 .SwAccess(prim_subreg_pkg::SwAccessRW),
5744 .RESVAL (2'h0),
5745 .Mubi (1'b0)
5746 ) u_prio160 (
5747 .clk_i (clk_i),
5748 .rst_ni (rst_ni),
5749
5750 // from register interface
5751 .we (prio160_we),
5752 .wd (prio160_wd),
5753
5754 // from internal hardware
5755 .de (1'b0),
5756 .d ('0),
5757
5758 // to internal hardware
5759 .qe (),
5760 .q (reg2hw.prio160.q),
5761 .ds (),
5762
5763 // to register interface (read)
5764 .qs (prio160_qs)
5765 );
5766
5767
5768 // R[prio161]: V(False)
5769 prim_subreg #(
5770 .DW (2),
5771 .SwAccess(prim_subreg_pkg::SwAccessRW),
5772 .RESVAL (2'h0),
5773 .Mubi (1'b0)
5774 ) u_prio161 (
5775 .clk_i (clk_i),
5776 .rst_ni (rst_ni),
5777
5778 // from register interface
5779 .we (prio161_we),
5780 .wd (prio161_wd),
5781
5782 // from internal hardware
5783 .de (1'b0),
5784 .d ('0),
5785
5786 // to internal hardware
5787 .qe (),
5788 .q (reg2hw.prio161.q),
5789 .ds (),
5790
5791 // to register interface (read)
5792 .qs (prio161_qs)
5793 );
5794
5795
5796 // R[prio162]: V(False)
5797 prim_subreg #(
5798 .DW (2),
5799 .SwAccess(prim_subreg_pkg::SwAccessRW),
5800 .RESVAL (2'h0),
5801 .Mubi (1'b0)
5802 ) u_prio162 (
5803 .clk_i (clk_i),
5804 .rst_ni (rst_ni),
5805
5806 // from register interface
5807 .we (prio162_we),
5808 .wd (prio162_wd),
5809
5810 // from internal hardware
5811 .de (1'b0),
5812 .d ('0),
5813
5814 // to internal hardware
5815 .qe (),
5816 .q (reg2hw.prio162.q),
5817 .ds (),
5818
5819 // to register interface (read)
5820 .qs (prio162_qs)
5821 );
5822
5823
5824 // R[prio163]: V(False)
5825 prim_subreg #(
5826 .DW (2),
5827 .SwAccess(prim_subreg_pkg::SwAccessRW),
5828 .RESVAL (2'h0),
5829 .Mubi (1'b0)
5830 ) u_prio163 (
5831 .clk_i (clk_i),
5832 .rst_ni (rst_ni),
5833
5834 // from register interface
5835 .we (prio163_we),
5836 .wd (prio163_wd),
5837
5838 // from internal hardware
5839 .de (1'b0),
5840 .d ('0),
5841
5842 // to internal hardware
5843 .qe (),
5844 .q (reg2hw.prio163.q),
5845 .ds (),
5846
5847 // to register interface (read)
5848 .qs (prio163_qs)
5849 );
5850
5851
5852 // R[prio164]: V(False)
5853 prim_subreg #(
5854 .DW (2),
5855 .SwAccess(prim_subreg_pkg::SwAccessRW),
5856 .RESVAL (2'h0),
5857 .Mubi (1'b0)
5858 ) u_prio164 (
5859 .clk_i (clk_i),
5860 .rst_ni (rst_ni),
5861
5862 // from register interface
5863 .we (prio164_we),
5864 .wd (prio164_wd),
5865
5866 // from internal hardware
5867 .de (1'b0),
5868 .d ('0),
5869
5870 // to internal hardware
5871 .qe (),
5872 .q (reg2hw.prio164.q),
5873 .ds (),
5874
5875 // to register interface (read)
5876 .qs (prio164_qs)
5877 );
5878
5879
5880 // R[prio165]: V(False)
5881 prim_subreg #(
5882 .DW (2),
5883 .SwAccess(prim_subreg_pkg::SwAccessRW),
5884 .RESVAL (2'h0),
5885 .Mubi (1'b0)
5886 ) u_prio165 (
5887 .clk_i (clk_i),
5888 .rst_ni (rst_ni),
5889
5890 // from register interface
5891 .we (prio165_we),
5892 .wd (prio165_wd),
5893
5894 // from internal hardware
5895 .de (1'b0),
5896 .d ('0),
5897
5898 // to internal hardware
5899 .qe (),
5900 .q (reg2hw.prio165.q),
5901 .ds (),
5902
5903 // to register interface (read)
5904 .qs (prio165_qs)
5905 );
5906
5907
5908 // R[prio166]: V(False)
5909 prim_subreg #(
5910 .DW (2),
5911 .SwAccess(prim_subreg_pkg::SwAccessRW),
5912 .RESVAL (2'h0),
5913 .Mubi (1'b0)
5914 ) u_prio166 (
5915 .clk_i (clk_i),
5916 .rst_ni (rst_ni),
5917
5918 // from register interface
5919 .we (prio166_we),
5920 .wd (prio166_wd),
5921
5922 // from internal hardware
5923 .de (1'b0),
5924 .d ('0),
5925
5926 // to internal hardware
5927 .qe (),
5928 .q (reg2hw.prio166.q),
5929 .ds (),
5930
5931 // to register interface (read)
5932 .qs (prio166_qs)
5933 );
5934
5935
5936 // R[prio167]: V(False)
5937 prim_subreg #(
5938 .DW (2),
5939 .SwAccess(prim_subreg_pkg::SwAccessRW),
5940 .RESVAL (2'h0),
5941 .Mubi (1'b0)
5942 ) u_prio167 (
5943 .clk_i (clk_i),
5944 .rst_ni (rst_ni),
5945
5946 // from register interface
5947 .we (prio167_we),
5948 .wd (prio167_wd),
5949
5950 // from internal hardware
5951 .de (1'b0),
5952 .d ('0),
5953
5954 // to internal hardware
5955 .qe (),
5956 .q (reg2hw.prio167.q),
5957 .ds (),
5958
5959 // to register interface (read)
5960 .qs (prio167_qs)
5961 );
5962
5963
5964 // R[prio168]: V(False)
5965 prim_subreg #(
5966 .DW (2),
5967 .SwAccess(prim_subreg_pkg::SwAccessRW),
5968 .RESVAL (2'h0),
5969 .Mubi (1'b0)
5970 ) u_prio168 (
5971 .clk_i (clk_i),
5972 .rst_ni (rst_ni),
5973
5974 // from register interface
5975 .we (prio168_we),
5976 .wd (prio168_wd),
5977
5978 // from internal hardware
5979 .de (1'b0),
5980 .d ('0),
5981
5982 // to internal hardware
5983 .qe (),
5984 .q (reg2hw.prio168.q),
5985 .ds (),
5986
5987 // to register interface (read)
5988 .qs (prio168_qs)
5989 );
5990
5991
5992 // R[prio169]: V(False)
5993 prim_subreg #(
5994 .DW (2),
5995 .SwAccess(prim_subreg_pkg::SwAccessRW),
5996 .RESVAL (2'h0),
5997 .Mubi (1'b0)
5998 ) u_prio169 (
5999 .clk_i (clk_i),
6000 .rst_ni (rst_ni),
6001
6002 // from register interface
6003 .we (prio169_we),
6004 .wd (prio169_wd),
6005
6006 // from internal hardware
6007 .de (1'b0),
6008 .d ('0),
6009
6010 // to internal hardware
6011 .qe (),
6012 .q (reg2hw.prio169.q),
6013 .ds (),
6014
6015 // to register interface (read)
6016 .qs (prio169_qs)
6017 );
6018
6019
6020 // R[prio170]: V(False)
6021 prim_subreg #(
6022 .DW (2),
6023 .SwAccess(prim_subreg_pkg::SwAccessRW),
6024 .RESVAL (2'h0),
6025 .Mubi (1'b0)
6026 ) u_prio170 (
6027 .clk_i (clk_i),
6028 .rst_ni (rst_ni),
6029
6030 // from register interface
6031 .we (prio170_we),
6032 .wd (prio170_wd),
6033
6034 // from internal hardware
6035 .de (1'b0),
6036 .d ('0),
6037
6038 // to internal hardware
6039 .qe (),
6040 .q (reg2hw.prio170.q),
6041 .ds (),
6042
6043 // to register interface (read)
6044 .qs (prio170_qs)
6045 );
6046
6047
6048 // R[prio171]: V(False)
6049 prim_subreg #(
6050 .DW (2),
6051 .SwAccess(prim_subreg_pkg::SwAccessRW),
6052 .RESVAL (2'h0),
6053 .Mubi (1'b0)
6054 ) u_prio171 (
6055 .clk_i (clk_i),
6056 .rst_ni (rst_ni),
6057
6058 // from register interface
6059 .we (prio171_we),
6060 .wd (prio171_wd),
6061
6062 // from internal hardware
6063 .de (1'b0),
6064 .d ('0),
6065
6066 // to internal hardware
6067 .qe (),
6068 .q (reg2hw.prio171.q),
6069 .ds (),
6070
6071 // to register interface (read)
6072 .qs (prio171_qs)
6073 );
6074
6075
6076 // R[prio172]: V(False)
6077 prim_subreg #(
6078 .DW (2),
6079 .SwAccess(prim_subreg_pkg::SwAccessRW),
6080 .RESVAL (2'h0),
6081 .Mubi (1'b0)
6082 ) u_prio172 (
6083 .clk_i (clk_i),
6084 .rst_ni (rst_ni),
6085
6086 // from register interface
6087 .we (prio172_we),
6088 .wd (prio172_wd),
6089
6090 // from internal hardware
6091 .de (1'b0),
6092 .d ('0),
6093
6094 // to internal hardware
6095 .qe (),
6096 .q (reg2hw.prio172.q),
6097 .ds (),
6098
6099 // to register interface (read)
6100 .qs (prio172_qs)
6101 );
6102
6103
6104 // R[prio173]: V(False)
6105 prim_subreg #(
6106 .DW (2),
6107 .SwAccess(prim_subreg_pkg::SwAccessRW),
6108 .RESVAL (2'h0),
6109 .Mubi (1'b0)
6110 ) u_prio173 (
6111 .clk_i (clk_i),
6112 .rst_ni (rst_ni),
6113
6114 // from register interface
6115 .we (prio173_we),
6116 .wd (prio173_wd),
6117
6118 // from internal hardware
6119 .de (1'b0),
6120 .d ('0),
6121
6122 // to internal hardware
6123 .qe (),
6124 .q (reg2hw.prio173.q),
6125 .ds (),
6126
6127 // to register interface (read)
6128 .qs (prio173_qs)
6129 );
6130
6131
6132 // R[prio174]: V(False)
6133 prim_subreg #(
6134 .DW (2),
6135 .SwAccess(prim_subreg_pkg::SwAccessRW),
6136 .RESVAL (2'h0),
6137 .Mubi (1'b0)
6138 ) u_prio174 (
6139 .clk_i (clk_i),
6140 .rst_ni (rst_ni),
6141
6142 // from register interface
6143 .we (prio174_we),
6144 .wd (prio174_wd),
6145
6146 // from internal hardware
6147 .de (1'b0),
6148 .d ('0),
6149
6150 // to internal hardware
6151 .qe (),
6152 .q (reg2hw.prio174.q),
6153 .ds (),
6154
6155 // to register interface (read)
6156 .qs (prio174_qs)
6157 );
6158
6159
6160 // R[prio175]: V(False)
6161 prim_subreg #(
6162 .DW (2),
6163 .SwAccess(prim_subreg_pkg::SwAccessRW),
6164 .RESVAL (2'h0),
6165 .Mubi (1'b0)
6166 ) u_prio175 (
6167 .clk_i (clk_i),
6168 .rst_ni (rst_ni),
6169
6170 // from register interface
6171 .we (prio175_we),
6172 .wd (prio175_wd),
6173
6174 // from internal hardware
6175 .de (1'b0),
6176 .d ('0),
6177
6178 // to internal hardware
6179 .qe (),
6180 .q (reg2hw.prio175.q),
6181 .ds (),
6182
6183 // to register interface (read)
6184 .qs (prio175_qs)
6185 );
6186
6187
6188 // R[prio176]: V(False)
6189 prim_subreg #(
6190 .DW (2),
6191 .SwAccess(prim_subreg_pkg::SwAccessRW),
6192 .RESVAL (2'h0),
6193 .Mubi (1'b0)
6194 ) u_prio176 (
6195 .clk_i (clk_i),
6196 .rst_ni (rst_ni),
6197
6198 // from register interface
6199 .we (prio176_we),
6200 .wd (prio176_wd),
6201
6202 // from internal hardware
6203 .de (1'b0),
6204 .d ('0),
6205
6206 // to internal hardware
6207 .qe (),
6208 .q (reg2hw.prio176.q),
6209 .ds (),
6210
6211 // to register interface (read)
6212 .qs (prio176_qs)
6213 );
6214
6215
6216 // R[prio177]: V(False)
6217 prim_subreg #(
6218 .DW (2),
6219 .SwAccess(prim_subreg_pkg::SwAccessRW),
6220 .RESVAL (2'h0),
6221 .Mubi (1'b0)
6222 ) u_prio177 (
6223 .clk_i (clk_i),
6224 .rst_ni (rst_ni),
6225
6226 // from register interface
6227 .we (prio177_we),
6228 .wd (prio177_wd),
6229
6230 // from internal hardware
6231 .de (1'b0),
6232 .d ('0),
6233
6234 // to internal hardware
6235 .qe (),
6236 .q (reg2hw.prio177.q),
6237 .ds (),
6238
6239 // to register interface (read)
6240 .qs (prio177_qs)
6241 );
6242
6243
6244 // R[prio178]: V(False)
6245 prim_subreg #(
6246 .DW (2),
6247 .SwAccess(prim_subreg_pkg::SwAccessRW),
6248 .RESVAL (2'h0),
6249 .Mubi (1'b0)
6250 ) u_prio178 (
6251 .clk_i (clk_i),
6252 .rst_ni (rst_ni),
6253
6254 // from register interface
6255 .we (prio178_we),
6256 .wd (prio178_wd),
6257
6258 // from internal hardware
6259 .de (1'b0),
6260 .d ('0),
6261
6262 // to internal hardware
6263 .qe (),
6264 .q (reg2hw.prio178.q),
6265 .ds (),
6266
6267 // to register interface (read)
6268 .qs (prio178_qs)
6269 );
6270
6271
6272 // R[prio179]: V(False)
6273 prim_subreg #(
6274 .DW (2),
6275 .SwAccess(prim_subreg_pkg::SwAccessRW),
6276 .RESVAL (2'h0),
6277 .Mubi (1'b0)
6278 ) u_prio179 (
6279 .clk_i (clk_i),
6280 .rst_ni (rst_ni),
6281
6282 // from register interface
6283 .we (prio179_we),
6284 .wd (prio179_wd),
6285
6286 // from internal hardware
6287 .de (1'b0),
6288 .d ('0),
6289
6290 // to internal hardware
6291 .qe (),
6292 .q (reg2hw.prio179.q),
6293 .ds (),
6294
6295 // to register interface (read)
6296 .qs (prio179_qs)
6297 );
6298
6299
6300 // R[prio180]: V(False)
6301 prim_subreg #(
6302 .DW (2),
6303 .SwAccess(prim_subreg_pkg::SwAccessRW),
6304 .RESVAL (2'h0),
6305 .Mubi (1'b0)
6306 ) u_prio180 (
6307 .clk_i (clk_i),
6308 .rst_ni (rst_ni),
6309
6310 // from register interface
6311 .we (prio180_we),
6312 .wd (prio180_wd),
6313
6314 // from internal hardware
6315 .de (1'b0),
6316 .d ('0),
6317
6318 // to internal hardware
6319 .qe (),
6320 .q (reg2hw.prio180.q),
6321 .ds (),
6322
6323 // to register interface (read)
6324 .qs (prio180_qs)
6325 );
6326
6327
6328 // R[prio181]: V(False)
6329 prim_subreg #(
6330 .DW (2),
6331 .SwAccess(prim_subreg_pkg::SwAccessRW),
6332 .RESVAL (2'h0),
6333 .Mubi (1'b0)
6334 ) u_prio181 (
6335 .clk_i (clk_i),
6336 .rst_ni (rst_ni),
6337
6338 // from register interface
6339 .we (prio181_we),
6340 .wd (prio181_wd),
6341
6342 // from internal hardware
6343 .de (1'b0),
6344 .d ('0),
6345
6346 // to internal hardware
6347 .qe (),
6348 .q (reg2hw.prio181.q),
6349 .ds (),
6350
6351 // to register interface (read)
6352 .qs (prio181_qs)
6353 );
6354
6355
6356 // R[prio182]: V(False)
6357 prim_subreg #(
6358 .DW (2),
6359 .SwAccess(prim_subreg_pkg::SwAccessRW),
6360 .RESVAL (2'h0),
6361 .Mubi (1'b0)
6362 ) u_prio182 (
6363 .clk_i (clk_i),
6364 .rst_ni (rst_ni),
6365
6366 // from register interface
6367 .we (prio182_we),
6368 .wd (prio182_wd),
6369
6370 // from internal hardware
6371 .de (1'b0),
6372 .d ('0),
6373
6374 // to internal hardware
6375 .qe (),
6376 .q (reg2hw.prio182.q),
6377 .ds (),
6378
6379 // to register interface (read)
6380 .qs (prio182_qs)
6381 );
6382
6383
6384 // R[prio183]: V(False)
6385 prim_subreg #(
6386 .DW (2),
6387 .SwAccess(prim_subreg_pkg::SwAccessRW),
6388 .RESVAL (2'h0),
6389 .Mubi (1'b0)
6390 ) u_prio183 (
6391 .clk_i (clk_i),
6392 .rst_ni (rst_ni),
6393
6394 // from register interface
6395 .we (prio183_we),
6396 .wd (prio183_wd),
6397
6398 // from internal hardware
6399 .de (1'b0),
6400 .d ('0),
6401
6402 // to internal hardware
6403 .qe (),
6404 .q (reg2hw.prio183.q),
6405 .ds (),
6406
6407 // to register interface (read)
6408 .qs (prio183_qs)
6409 );
6410
6411
6412 // R[prio184]: V(False)
6413 prim_subreg #(
6414 .DW (2),
6415 .SwAccess(prim_subreg_pkg::SwAccessRW),
6416 .RESVAL (2'h0),
6417 .Mubi (1'b0)
6418 ) u_prio184 (
6419 .clk_i (clk_i),
6420 .rst_ni (rst_ni),
6421
6422 // from register interface
6423 .we (prio184_we),
6424 .wd (prio184_wd),
6425
6426 // from internal hardware
6427 .de (1'b0),
6428 .d ('0),
6429
6430 // to internal hardware
6431 .qe (),
6432 .q (reg2hw.prio184.q),
6433 .ds (),
6434
6435 // to register interface (read)
6436 .qs (prio184_qs)
6437 );
6438
6439
6440 // R[prio185]: V(False)
6441 prim_subreg #(
6442 .DW (2),
6443 .SwAccess(prim_subreg_pkg::SwAccessRW),
6444 .RESVAL (2'h0),
6445 .Mubi (1'b0)
6446 ) u_prio185 (
6447 .clk_i (clk_i),
6448 .rst_ni (rst_ni),
6449
6450 // from register interface
6451 .we (prio185_we),
6452 .wd (prio185_wd),
6453
6454 // from internal hardware
6455 .de (1'b0),
6456 .d ('0),
6457
6458 // to internal hardware
6459 .qe (),
6460 .q (reg2hw.prio185.q),
6461 .ds (),
6462
6463 // to register interface (read)
6464 .qs (prio185_qs)
6465 );
6466
6467
6468 // Subregister 0 of Multireg ip
6469 // R[ip_0]: V(False)
6470 // F[p_0]: 0:0
6471 prim_subreg #(
6472 .DW (1),
6473 .SwAccess(prim_subreg_pkg::SwAccessRO),
6474 .RESVAL (1'h0),
6475 .Mubi (1'b0)
6476 ) u_ip_0_p_0 (
6477 .clk_i (clk_i),
6478 .rst_ni (rst_ni),
6479
6480 // from register interface
6481 .we (1'b0),
6482 .wd ('0),
6483
6484 // from internal hardware
6485 .de (hw2reg.ip[0].de),
6486 .d (hw2reg.ip[0].d),
6487
6488 // to internal hardware
6489 .qe (),
6490 .q (),
6491 .ds (),
6492
6493 // to register interface (read)
6494 .qs (ip_0_p_0_qs)
6495 );
6496
6497 // F[p_1]: 1:1
6498 prim_subreg #(
6499 .DW (1),
6500 .SwAccess(prim_subreg_pkg::SwAccessRO),
6501 .RESVAL (1'h0),
6502 .Mubi (1'b0)
6503 ) u_ip_0_p_1 (
6504 .clk_i (clk_i),
6505 .rst_ni (rst_ni),
6506
6507 // from register interface
6508 .we (1'b0),
6509 .wd ('0),
6510
6511 // from internal hardware
6512 .de (hw2reg.ip[1].de),
6513 .d (hw2reg.ip[1].d),
6514
6515 // to internal hardware
6516 .qe (),
6517 .q (),
6518 .ds (),
6519
6520 // to register interface (read)
6521 .qs (ip_0_p_1_qs)
6522 );
6523
6524 // F[p_2]: 2:2
6525 prim_subreg #(
6526 .DW (1),
6527 .SwAccess(prim_subreg_pkg::SwAccessRO),
6528 .RESVAL (1'h0),
6529 .Mubi (1'b0)
6530 ) u_ip_0_p_2 (
6531 .clk_i (clk_i),
6532 .rst_ni (rst_ni),
6533
6534 // from register interface
6535 .we (1'b0),
6536 .wd ('0),
6537
6538 // from internal hardware
6539 .de (hw2reg.ip[2].de),
6540 .d (hw2reg.ip[2].d),
6541
6542 // to internal hardware
6543 .qe (),
6544 .q (),
6545 .ds (),
6546
6547 // to register interface (read)
6548 .qs (ip_0_p_2_qs)
6549 );
6550
6551 // F[p_3]: 3:3
6552 prim_subreg #(
6553 .DW (1),
6554 .SwAccess(prim_subreg_pkg::SwAccessRO),
6555 .RESVAL (1'h0),
6556 .Mubi (1'b0)
6557 ) u_ip_0_p_3 (
6558 .clk_i (clk_i),
6559 .rst_ni (rst_ni),
6560
6561 // from register interface
6562 .we (1'b0),
6563 .wd ('0),
6564
6565 // from internal hardware
6566 .de (hw2reg.ip[3].de),
6567 .d (hw2reg.ip[3].d),
6568
6569 // to internal hardware
6570 .qe (),
6571 .q (),
6572 .ds (),
6573
6574 // to register interface (read)
6575 .qs (ip_0_p_3_qs)
6576 );
6577
6578 // F[p_4]: 4:4
6579 prim_subreg #(
6580 .DW (1),
6581 .SwAccess(prim_subreg_pkg::SwAccessRO),
6582 .RESVAL (1'h0),
6583 .Mubi (1'b0)
6584 ) u_ip_0_p_4 (
6585 .clk_i (clk_i),
6586 .rst_ni (rst_ni),
6587
6588 // from register interface
6589 .we (1'b0),
6590 .wd ('0),
6591
6592 // from internal hardware
6593 .de (hw2reg.ip[4].de),
6594 .d (hw2reg.ip[4].d),
6595
6596 // to internal hardware
6597 .qe (),
6598 .q (),
6599 .ds (),
6600
6601 // to register interface (read)
6602 .qs (ip_0_p_4_qs)
6603 );
6604
6605 // F[p_5]: 5:5
6606 prim_subreg #(
6607 .DW (1),
6608 .SwAccess(prim_subreg_pkg::SwAccessRO),
6609 .RESVAL (1'h0),
6610 .Mubi (1'b0)
6611 ) u_ip_0_p_5 (
6612 .clk_i (clk_i),
6613 .rst_ni (rst_ni),
6614
6615 // from register interface
6616 .we (1'b0),
6617 .wd ('0),
6618
6619 // from internal hardware
6620 .de (hw2reg.ip[5].de),
6621 .d (hw2reg.ip[5].d),
6622
6623 // to internal hardware
6624 .qe (),
6625 .q (),
6626 .ds (),
6627
6628 // to register interface (read)
6629 .qs (ip_0_p_5_qs)
6630 );
6631
6632 // F[p_6]: 6:6
6633 prim_subreg #(
6634 .DW (1),
6635 .SwAccess(prim_subreg_pkg::SwAccessRO),
6636 .RESVAL (1'h0),
6637 .Mubi (1'b0)
6638 ) u_ip_0_p_6 (
6639 .clk_i (clk_i),
6640 .rst_ni (rst_ni),
6641
6642 // from register interface
6643 .we (1'b0),
6644 .wd ('0),
6645
6646 // from internal hardware
6647 .de (hw2reg.ip[6].de),
6648 .d (hw2reg.ip[6].d),
6649
6650 // to internal hardware
6651 .qe (),
6652 .q (),
6653 .ds (),
6654
6655 // to register interface (read)
6656 .qs (ip_0_p_6_qs)
6657 );
6658
6659 // F[p_7]: 7:7
6660 prim_subreg #(
6661 .DW (1),
6662 .SwAccess(prim_subreg_pkg::SwAccessRO),
6663 .RESVAL (1'h0),
6664 .Mubi (1'b0)
6665 ) u_ip_0_p_7 (
6666 .clk_i (clk_i),
6667 .rst_ni (rst_ni),
6668
6669 // from register interface
6670 .we (1'b0),
6671 .wd ('0),
6672
6673 // from internal hardware
6674 .de (hw2reg.ip[7].de),
6675 .d (hw2reg.ip[7].d),
6676
6677 // to internal hardware
6678 .qe (),
6679 .q (),
6680 .ds (),
6681
6682 // to register interface (read)
6683 .qs (ip_0_p_7_qs)
6684 );
6685
6686 // F[p_8]: 8:8
6687 prim_subreg #(
6688 .DW (1),
6689 .SwAccess(prim_subreg_pkg::SwAccessRO),
6690 .RESVAL (1'h0),
6691 .Mubi (1'b0)
6692 ) u_ip_0_p_8 (
6693 .clk_i (clk_i),
6694 .rst_ni (rst_ni),
6695
6696 // from register interface
6697 .we (1'b0),
6698 .wd ('0),
6699
6700 // from internal hardware
6701 .de (hw2reg.ip[8].de),
6702 .d (hw2reg.ip[8].d),
6703
6704 // to internal hardware
6705 .qe (),
6706 .q (),
6707 .ds (),
6708
6709 // to register interface (read)
6710 .qs (ip_0_p_8_qs)
6711 );
6712
6713 // F[p_9]: 9:9
6714 prim_subreg #(
6715 .DW (1),
6716 .SwAccess(prim_subreg_pkg::SwAccessRO),
6717 .RESVAL (1'h0),
6718 .Mubi (1'b0)
6719 ) u_ip_0_p_9 (
6720 .clk_i (clk_i),
6721 .rst_ni (rst_ni),
6722
6723 // from register interface
6724 .we (1'b0),
6725 .wd ('0),
6726
6727 // from internal hardware
6728 .de (hw2reg.ip[9].de),
6729 .d (hw2reg.ip[9].d),
6730
6731 // to internal hardware
6732 .qe (),
6733 .q (),
6734 .ds (),
6735
6736 // to register interface (read)
6737 .qs (ip_0_p_9_qs)
6738 );
6739
6740 // F[p_10]: 10:10
6741 prim_subreg #(
6742 .DW (1),
6743 .SwAccess(prim_subreg_pkg::SwAccessRO),
6744 .RESVAL (1'h0),
6745 .Mubi (1'b0)
6746 ) u_ip_0_p_10 (
6747 .clk_i (clk_i),
6748 .rst_ni (rst_ni),
6749
6750 // from register interface
6751 .we (1'b0),
6752 .wd ('0),
6753
6754 // from internal hardware
6755 .de (hw2reg.ip[10].de),
6756 .d (hw2reg.ip[10].d),
6757
6758 // to internal hardware
6759 .qe (),
6760 .q (),
6761 .ds (),
6762
6763 // to register interface (read)
6764 .qs (ip_0_p_10_qs)
6765 );
6766
6767 // F[p_11]: 11:11
6768 prim_subreg #(
6769 .DW (1),
6770 .SwAccess(prim_subreg_pkg::SwAccessRO),
6771 .RESVAL (1'h0),
6772 .Mubi (1'b0)
6773 ) u_ip_0_p_11 (
6774 .clk_i (clk_i),
6775 .rst_ni (rst_ni),
6776
6777 // from register interface
6778 .we (1'b0),
6779 .wd ('0),
6780
6781 // from internal hardware
6782 .de (hw2reg.ip[11].de),
6783 .d (hw2reg.ip[11].d),
6784
6785 // to internal hardware
6786 .qe (),
6787 .q (),
6788 .ds (),
6789
6790 // to register interface (read)
6791 .qs (ip_0_p_11_qs)
6792 );
6793
6794 // F[p_12]: 12:12
6795 prim_subreg #(
6796 .DW (1),
6797 .SwAccess(prim_subreg_pkg::SwAccessRO),
6798 .RESVAL (1'h0),
6799 .Mubi (1'b0)
6800 ) u_ip_0_p_12 (
6801 .clk_i (clk_i),
6802 .rst_ni (rst_ni),
6803
6804 // from register interface
6805 .we (1'b0),
6806 .wd ('0),
6807
6808 // from internal hardware
6809 .de (hw2reg.ip[12].de),
6810 .d (hw2reg.ip[12].d),
6811
6812 // to internal hardware
6813 .qe (),
6814 .q (),
6815 .ds (),
6816
6817 // to register interface (read)
6818 .qs (ip_0_p_12_qs)
6819 );
6820
6821 // F[p_13]: 13:13
6822 prim_subreg #(
6823 .DW (1),
6824 .SwAccess(prim_subreg_pkg::SwAccessRO),
6825 .RESVAL (1'h0),
6826 .Mubi (1'b0)
6827 ) u_ip_0_p_13 (
6828 .clk_i (clk_i),
6829 .rst_ni (rst_ni),
6830
6831 // from register interface
6832 .we (1'b0),
6833 .wd ('0),
6834
6835 // from internal hardware
6836 .de (hw2reg.ip[13].de),
6837 .d (hw2reg.ip[13].d),
6838
6839 // to internal hardware
6840 .qe (),
6841 .q (),
6842 .ds (),
6843
6844 // to register interface (read)
6845 .qs (ip_0_p_13_qs)
6846 );
6847
6848 // F[p_14]: 14:14
6849 prim_subreg #(
6850 .DW (1),
6851 .SwAccess(prim_subreg_pkg::SwAccessRO),
6852 .RESVAL (1'h0),
6853 .Mubi (1'b0)
6854 ) u_ip_0_p_14 (
6855 .clk_i (clk_i),
6856 .rst_ni (rst_ni),
6857
6858 // from register interface
6859 .we (1'b0),
6860 .wd ('0),
6861
6862 // from internal hardware
6863 .de (hw2reg.ip[14].de),
6864 .d (hw2reg.ip[14].d),
6865
6866 // to internal hardware
6867 .qe (),
6868 .q (),
6869 .ds (),
6870
6871 // to register interface (read)
6872 .qs (ip_0_p_14_qs)
6873 );
6874
6875 // F[p_15]: 15:15
6876 prim_subreg #(
6877 .DW (1),
6878 .SwAccess(prim_subreg_pkg::SwAccessRO),
6879 .RESVAL (1'h0),
6880 .Mubi (1'b0)
6881 ) u_ip_0_p_15 (
6882 .clk_i (clk_i),
6883 .rst_ni (rst_ni),
6884
6885 // from register interface
6886 .we (1'b0),
6887 .wd ('0),
6888
6889 // from internal hardware
6890 .de (hw2reg.ip[15].de),
6891 .d (hw2reg.ip[15].d),
6892
6893 // to internal hardware
6894 .qe (),
6895 .q (),
6896 .ds (),
6897
6898 // to register interface (read)
6899 .qs (ip_0_p_15_qs)
6900 );
6901
6902 // F[p_16]: 16:16
6903 prim_subreg #(
6904 .DW (1),
6905 .SwAccess(prim_subreg_pkg::SwAccessRO),
6906 .RESVAL (1'h0),
6907 .Mubi (1'b0)
6908 ) u_ip_0_p_16 (
6909 .clk_i (clk_i),
6910 .rst_ni (rst_ni),
6911
6912 // from register interface
6913 .we (1'b0),
6914 .wd ('0),
6915
6916 // from internal hardware
6917 .de (hw2reg.ip[16].de),
6918 .d (hw2reg.ip[16].d),
6919
6920 // to internal hardware
6921 .qe (),
6922 .q (),
6923 .ds (),
6924
6925 // to register interface (read)
6926 .qs (ip_0_p_16_qs)
6927 );
6928
6929 // F[p_17]: 17:17
6930 prim_subreg #(
6931 .DW (1),
6932 .SwAccess(prim_subreg_pkg::SwAccessRO),
6933 .RESVAL (1'h0),
6934 .Mubi (1'b0)
6935 ) u_ip_0_p_17 (
6936 .clk_i (clk_i),
6937 .rst_ni (rst_ni),
6938
6939 // from register interface
6940 .we (1'b0),
6941 .wd ('0),
6942
6943 // from internal hardware
6944 .de (hw2reg.ip[17].de),
6945 .d (hw2reg.ip[17].d),
6946
6947 // to internal hardware
6948 .qe (),
6949 .q (),
6950 .ds (),
6951
6952 // to register interface (read)
6953 .qs (ip_0_p_17_qs)
6954 );
6955
6956 // F[p_18]: 18:18
6957 prim_subreg #(
6958 .DW (1),
6959 .SwAccess(prim_subreg_pkg::SwAccessRO),
6960 .RESVAL (1'h0),
6961 .Mubi (1'b0)
6962 ) u_ip_0_p_18 (
6963 .clk_i (clk_i),
6964 .rst_ni (rst_ni),
6965
6966 // from register interface
6967 .we (1'b0),
6968 .wd ('0),
6969
6970 // from internal hardware
6971 .de (hw2reg.ip[18].de),
6972 .d (hw2reg.ip[18].d),
6973
6974 // to internal hardware
6975 .qe (),
6976 .q (),
6977 .ds (),
6978
6979 // to register interface (read)
6980 .qs (ip_0_p_18_qs)
6981 );
6982
6983 // F[p_19]: 19:19
6984 prim_subreg #(
6985 .DW (1),
6986 .SwAccess(prim_subreg_pkg::SwAccessRO),
6987 .RESVAL (1'h0),
6988 .Mubi (1'b0)
6989 ) u_ip_0_p_19 (
6990 .clk_i (clk_i),
6991 .rst_ni (rst_ni),
6992
6993 // from register interface
6994 .we (1'b0),
6995 .wd ('0),
6996
6997 // from internal hardware
6998 .de (hw2reg.ip[19].de),
6999 .d (hw2reg.ip[19].d),
7000
7001 // to internal hardware
7002 .qe (),
7003 .q (),
7004 .ds (),
7005
7006 // to register interface (read)
7007 .qs (ip_0_p_19_qs)
7008 );
7009
7010 // F[p_20]: 20:20
7011 prim_subreg #(
7012 .DW (1),
7013 .SwAccess(prim_subreg_pkg::SwAccessRO),
7014 .RESVAL (1'h0),
7015 .Mubi (1'b0)
7016 ) u_ip_0_p_20 (
7017 .clk_i (clk_i),
7018 .rst_ni (rst_ni),
7019
7020 // from register interface
7021 .we (1'b0),
7022 .wd ('0),
7023
7024 // from internal hardware
7025 .de (hw2reg.ip[20].de),
7026 .d (hw2reg.ip[20].d),
7027
7028 // to internal hardware
7029 .qe (),
7030 .q (),
7031 .ds (),
7032
7033 // to register interface (read)
7034 .qs (ip_0_p_20_qs)
7035 );
7036
7037 // F[p_21]: 21:21
7038 prim_subreg #(
7039 .DW (1),
7040 .SwAccess(prim_subreg_pkg::SwAccessRO),
7041 .RESVAL (1'h0),
7042 .Mubi (1'b0)
7043 ) u_ip_0_p_21 (
7044 .clk_i (clk_i),
7045 .rst_ni (rst_ni),
7046
7047 // from register interface
7048 .we (1'b0),
7049 .wd ('0),
7050
7051 // from internal hardware
7052 .de (hw2reg.ip[21].de),
7053 .d (hw2reg.ip[21].d),
7054
7055 // to internal hardware
7056 .qe (),
7057 .q (),
7058 .ds (),
7059
7060 // to register interface (read)
7061 .qs (ip_0_p_21_qs)
7062 );
7063
7064 // F[p_22]: 22:22
7065 prim_subreg #(
7066 .DW (1),
7067 .SwAccess(prim_subreg_pkg::SwAccessRO),
7068 .RESVAL (1'h0),
7069 .Mubi (1'b0)
7070 ) u_ip_0_p_22 (
7071 .clk_i (clk_i),
7072 .rst_ni (rst_ni),
7073
7074 // from register interface
7075 .we (1'b0),
7076 .wd ('0),
7077
7078 // from internal hardware
7079 .de (hw2reg.ip[22].de),
7080 .d (hw2reg.ip[22].d),
7081
7082 // to internal hardware
7083 .qe (),
7084 .q (),
7085 .ds (),
7086
7087 // to register interface (read)
7088 .qs (ip_0_p_22_qs)
7089 );
7090
7091 // F[p_23]: 23:23
7092 prim_subreg #(
7093 .DW (1),
7094 .SwAccess(prim_subreg_pkg::SwAccessRO),
7095 .RESVAL (1'h0),
7096 .Mubi (1'b0)
7097 ) u_ip_0_p_23 (
7098 .clk_i (clk_i),
7099 .rst_ni (rst_ni),
7100
7101 // from register interface
7102 .we (1'b0),
7103 .wd ('0),
7104
7105 // from internal hardware
7106 .de (hw2reg.ip[23].de),
7107 .d (hw2reg.ip[23].d),
7108
7109 // to internal hardware
7110 .qe (),
7111 .q (),
7112 .ds (),
7113
7114 // to register interface (read)
7115 .qs (ip_0_p_23_qs)
7116 );
7117
7118 // F[p_24]: 24:24
7119 prim_subreg #(
7120 .DW (1),
7121 .SwAccess(prim_subreg_pkg::SwAccessRO),
7122 .RESVAL (1'h0),
7123 .Mubi (1'b0)
7124 ) u_ip_0_p_24 (
7125 .clk_i (clk_i),
7126 .rst_ni (rst_ni),
7127
7128 // from register interface
7129 .we (1'b0),
7130 .wd ('0),
7131
7132 // from internal hardware
7133 .de (hw2reg.ip[24].de),
7134 .d (hw2reg.ip[24].d),
7135
7136 // to internal hardware
7137 .qe (),
7138 .q (),
7139 .ds (),
7140
7141 // to register interface (read)
7142 .qs (ip_0_p_24_qs)
7143 );
7144
7145 // F[p_25]: 25:25
7146 prim_subreg #(
7147 .DW (1),
7148 .SwAccess(prim_subreg_pkg::SwAccessRO),
7149 .RESVAL (1'h0),
7150 .Mubi (1'b0)
7151 ) u_ip_0_p_25 (
7152 .clk_i (clk_i),
7153 .rst_ni (rst_ni),
7154
7155 // from register interface
7156 .we (1'b0),
7157 .wd ('0),
7158
7159 // from internal hardware
7160 .de (hw2reg.ip[25].de),
7161 .d (hw2reg.ip[25].d),
7162
7163 // to internal hardware
7164 .qe (),
7165 .q (),
7166 .ds (),
7167
7168 // to register interface (read)
7169 .qs (ip_0_p_25_qs)
7170 );
7171
7172 // F[p_26]: 26:26
7173 prim_subreg #(
7174 .DW (1),
7175 .SwAccess(prim_subreg_pkg::SwAccessRO),
7176 .RESVAL (1'h0),
7177 .Mubi (1'b0)
7178 ) u_ip_0_p_26 (
7179 .clk_i (clk_i),
7180 .rst_ni (rst_ni),
7181
7182 // from register interface
7183 .we (1'b0),
7184 .wd ('0),
7185
7186 // from internal hardware
7187 .de (hw2reg.ip[26].de),
7188 .d (hw2reg.ip[26].d),
7189
7190 // to internal hardware
7191 .qe (),
7192 .q (),
7193 .ds (),
7194
7195 // to register interface (read)
7196 .qs (ip_0_p_26_qs)
7197 );
7198
7199 // F[p_27]: 27:27
7200 prim_subreg #(
7201 .DW (1),
7202 .SwAccess(prim_subreg_pkg::SwAccessRO),
7203 .RESVAL (1'h0),
7204 .Mubi (1'b0)
7205 ) u_ip_0_p_27 (
7206 .clk_i (clk_i),
7207 .rst_ni (rst_ni),
7208
7209 // from register interface
7210 .we (1'b0),
7211 .wd ('0),
7212
7213 // from internal hardware
7214 .de (hw2reg.ip[27].de),
7215 .d (hw2reg.ip[27].d),
7216
7217 // to internal hardware
7218 .qe (),
7219 .q (),
7220 .ds (),
7221
7222 // to register interface (read)
7223 .qs (ip_0_p_27_qs)
7224 );
7225
7226 // F[p_28]: 28:28
7227 prim_subreg #(
7228 .DW (1),
7229 .SwAccess(prim_subreg_pkg::SwAccessRO),
7230 .RESVAL (1'h0),
7231 .Mubi (1'b0)
7232 ) u_ip_0_p_28 (
7233 .clk_i (clk_i),
7234 .rst_ni (rst_ni),
7235
7236 // from register interface
7237 .we (1'b0),
7238 .wd ('0),
7239
7240 // from internal hardware
7241 .de (hw2reg.ip[28].de),
7242 .d (hw2reg.ip[28].d),
7243
7244 // to internal hardware
7245 .qe (),
7246 .q (),
7247 .ds (),
7248
7249 // to register interface (read)
7250 .qs (ip_0_p_28_qs)
7251 );
7252
7253 // F[p_29]: 29:29
7254 prim_subreg #(
7255 .DW (1),
7256 .SwAccess(prim_subreg_pkg::SwAccessRO),
7257 .RESVAL (1'h0),
7258 .Mubi (1'b0)
7259 ) u_ip_0_p_29 (
7260 .clk_i (clk_i),
7261 .rst_ni (rst_ni),
7262
7263 // from register interface
7264 .we (1'b0),
7265 .wd ('0),
7266
7267 // from internal hardware
7268 .de (hw2reg.ip[29].de),
7269 .d (hw2reg.ip[29].d),
7270
7271 // to internal hardware
7272 .qe (),
7273 .q (),
7274 .ds (),
7275
7276 // to register interface (read)
7277 .qs (ip_0_p_29_qs)
7278 );
7279
7280 // F[p_30]: 30:30
7281 prim_subreg #(
7282 .DW (1),
7283 .SwAccess(prim_subreg_pkg::SwAccessRO),
7284 .RESVAL (1'h0),
7285 .Mubi (1'b0)
7286 ) u_ip_0_p_30 (
7287 .clk_i (clk_i),
7288 .rst_ni (rst_ni),
7289
7290 // from register interface
7291 .we (1'b0),
7292 .wd ('0),
7293
7294 // from internal hardware
7295 .de (hw2reg.ip[30].de),
7296 .d (hw2reg.ip[30].d),
7297
7298 // to internal hardware
7299 .qe (),
7300 .q (),
7301 .ds (),
7302
7303 // to register interface (read)
7304 .qs (ip_0_p_30_qs)
7305 );
7306
7307 // F[p_31]: 31:31
7308 prim_subreg #(
7309 .DW (1),
7310 .SwAccess(prim_subreg_pkg::SwAccessRO),
7311 .RESVAL (1'h0),
7312 .Mubi (1'b0)
7313 ) u_ip_0_p_31 (
7314 .clk_i (clk_i),
7315 .rst_ni (rst_ni),
7316
7317 // from register interface
7318 .we (1'b0),
7319 .wd ('0),
7320
7321 // from internal hardware
7322 .de (hw2reg.ip[31].de),
7323 .d (hw2reg.ip[31].d),
7324
7325 // to internal hardware
7326 .qe (),
7327 .q (),
7328 .ds (),
7329
7330 // to register interface (read)
7331 .qs (ip_0_p_31_qs)
7332 );
7333
7334
7335 // Subregister 1 of Multireg ip
7336 // R[ip_1]: V(False)
7337 // F[p_32]: 0:0
7338 prim_subreg #(
7339 .DW (1),
7340 .SwAccess(prim_subreg_pkg::SwAccessRO),
7341 .RESVAL (1'h0),
7342 .Mubi (1'b0)
7343 ) u_ip_1_p_32 (
7344 .clk_i (clk_i),
7345 .rst_ni (rst_ni),
7346
7347 // from register interface
7348 .we (1'b0),
7349 .wd ('0),
7350
7351 // from internal hardware
7352 .de (hw2reg.ip[32].de),
7353 .d (hw2reg.ip[32].d),
7354
7355 // to internal hardware
7356 .qe (),
7357 .q (),
7358 .ds (),
7359
7360 // to register interface (read)
7361 .qs (ip_1_p_32_qs)
7362 );
7363
7364 // F[p_33]: 1:1
7365 prim_subreg #(
7366 .DW (1),
7367 .SwAccess(prim_subreg_pkg::SwAccessRO),
7368 .RESVAL (1'h0),
7369 .Mubi (1'b0)
7370 ) u_ip_1_p_33 (
7371 .clk_i (clk_i),
7372 .rst_ni (rst_ni),
7373
7374 // from register interface
7375 .we (1'b0),
7376 .wd ('0),
7377
7378 // from internal hardware
7379 .de (hw2reg.ip[33].de),
7380 .d (hw2reg.ip[33].d),
7381
7382 // to internal hardware
7383 .qe (),
7384 .q (),
7385 .ds (),
7386
7387 // to register interface (read)
7388 .qs (ip_1_p_33_qs)
7389 );
7390
7391 // F[p_34]: 2:2
7392 prim_subreg #(
7393 .DW (1),
7394 .SwAccess(prim_subreg_pkg::SwAccessRO),
7395 .RESVAL (1'h0),
7396 .Mubi (1'b0)
7397 ) u_ip_1_p_34 (
7398 .clk_i (clk_i),
7399 .rst_ni (rst_ni),
7400
7401 // from register interface
7402 .we (1'b0),
7403 .wd ('0),
7404
7405 // from internal hardware
7406 .de (hw2reg.ip[34].de),
7407 .d (hw2reg.ip[34].d),
7408
7409 // to internal hardware
7410 .qe (),
7411 .q (),
7412 .ds (),
7413
7414 // to register interface (read)
7415 .qs (ip_1_p_34_qs)
7416 );
7417
7418 // F[p_35]: 3:3
7419 prim_subreg #(
7420 .DW (1),
7421 .SwAccess(prim_subreg_pkg::SwAccessRO),
7422 .RESVAL (1'h0),
7423 .Mubi (1'b0)
7424 ) u_ip_1_p_35 (
7425 .clk_i (clk_i),
7426 .rst_ni (rst_ni),
7427
7428 // from register interface
7429 .we (1'b0),
7430 .wd ('0),
7431
7432 // from internal hardware
7433 .de (hw2reg.ip[35].de),
7434 .d (hw2reg.ip[35].d),
7435
7436 // to internal hardware
7437 .qe (),
7438 .q (),
7439 .ds (),
7440
7441 // to register interface (read)
7442 .qs (ip_1_p_35_qs)
7443 );
7444
7445 // F[p_36]: 4:4
7446 prim_subreg #(
7447 .DW (1),
7448 .SwAccess(prim_subreg_pkg::SwAccessRO),
7449 .RESVAL (1'h0),
7450 .Mubi (1'b0)
7451 ) u_ip_1_p_36 (
7452 .clk_i (clk_i),
7453 .rst_ni (rst_ni),
7454
7455 // from register interface
7456 .we (1'b0),
7457 .wd ('0),
7458
7459 // from internal hardware
7460 .de (hw2reg.ip[36].de),
7461 .d (hw2reg.ip[36].d),
7462
7463 // to internal hardware
7464 .qe (),
7465 .q (),
7466 .ds (),
7467
7468 // to register interface (read)
7469 .qs (ip_1_p_36_qs)
7470 );
7471
7472 // F[p_37]: 5:5
7473 prim_subreg #(
7474 .DW (1),
7475 .SwAccess(prim_subreg_pkg::SwAccessRO),
7476 .RESVAL (1'h0),
7477 .Mubi (1'b0)
7478 ) u_ip_1_p_37 (
7479 .clk_i (clk_i),
7480 .rst_ni (rst_ni),
7481
7482 // from register interface
7483 .we (1'b0),
7484 .wd ('0),
7485
7486 // from internal hardware
7487 .de (hw2reg.ip[37].de),
7488 .d (hw2reg.ip[37].d),
7489
7490 // to internal hardware
7491 .qe (),
7492 .q (),
7493 .ds (),
7494
7495 // to register interface (read)
7496 .qs (ip_1_p_37_qs)
7497 );
7498
7499 // F[p_38]: 6:6
7500 prim_subreg #(
7501 .DW (1),
7502 .SwAccess(prim_subreg_pkg::SwAccessRO),
7503 .RESVAL (1'h0),
7504 .Mubi (1'b0)
7505 ) u_ip_1_p_38 (
7506 .clk_i (clk_i),
7507 .rst_ni (rst_ni),
7508
7509 // from register interface
7510 .we (1'b0),
7511 .wd ('0),
7512
7513 // from internal hardware
7514 .de (hw2reg.ip[38].de),
7515 .d (hw2reg.ip[38].d),
7516
7517 // to internal hardware
7518 .qe (),
7519 .q (),
7520 .ds (),
7521
7522 // to register interface (read)
7523 .qs (ip_1_p_38_qs)
7524 );
7525
7526 // F[p_39]: 7:7
7527 prim_subreg #(
7528 .DW (1),
7529 .SwAccess(prim_subreg_pkg::SwAccessRO),
7530 .RESVAL (1'h0),
7531 .Mubi (1'b0)
7532 ) u_ip_1_p_39 (
7533 .clk_i (clk_i),
7534 .rst_ni (rst_ni),
7535
7536 // from register interface
7537 .we (1'b0),
7538 .wd ('0),
7539
7540 // from internal hardware
7541 .de (hw2reg.ip[39].de),
7542 .d (hw2reg.ip[39].d),
7543
7544 // to internal hardware
7545 .qe (),
7546 .q (),
7547 .ds (),
7548
7549 // to register interface (read)
7550 .qs (ip_1_p_39_qs)
7551 );
7552
7553 // F[p_40]: 8:8
7554 prim_subreg #(
7555 .DW (1),
7556 .SwAccess(prim_subreg_pkg::SwAccessRO),
7557 .RESVAL (1'h0),
7558 .Mubi (1'b0)
7559 ) u_ip_1_p_40 (
7560 .clk_i (clk_i),
7561 .rst_ni (rst_ni),
7562
7563 // from register interface
7564 .we (1'b0),
7565 .wd ('0),
7566
7567 // from internal hardware
7568 .de (hw2reg.ip[40].de),
7569 .d (hw2reg.ip[40].d),
7570
7571 // to internal hardware
7572 .qe (),
7573 .q (),
7574 .ds (),
7575
7576 // to register interface (read)
7577 .qs (ip_1_p_40_qs)
7578 );
7579
7580 // F[p_41]: 9:9
7581 prim_subreg #(
7582 .DW (1),
7583 .SwAccess(prim_subreg_pkg::SwAccessRO),
7584 .RESVAL (1'h0),
7585 .Mubi (1'b0)
7586 ) u_ip_1_p_41 (
7587 .clk_i (clk_i),
7588 .rst_ni (rst_ni),
7589
7590 // from register interface
7591 .we (1'b0),
7592 .wd ('0),
7593
7594 // from internal hardware
7595 .de (hw2reg.ip[41].de),
7596 .d (hw2reg.ip[41].d),
7597
7598 // to internal hardware
7599 .qe (),
7600 .q (),
7601 .ds (),
7602
7603 // to register interface (read)
7604 .qs (ip_1_p_41_qs)
7605 );
7606
7607 // F[p_42]: 10:10
7608 prim_subreg #(
7609 .DW (1),
7610 .SwAccess(prim_subreg_pkg::SwAccessRO),
7611 .RESVAL (1'h0),
7612 .Mubi (1'b0)
7613 ) u_ip_1_p_42 (
7614 .clk_i (clk_i),
7615 .rst_ni (rst_ni),
7616
7617 // from register interface
7618 .we (1'b0),
7619 .wd ('0),
7620
7621 // from internal hardware
7622 .de (hw2reg.ip[42].de),
7623 .d (hw2reg.ip[42].d),
7624
7625 // to internal hardware
7626 .qe (),
7627 .q (),
7628 .ds (),
7629
7630 // to register interface (read)
7631 .qs (ip_1_p_42_qs)
7632 );
7633
7634 // F[p_43]: 11:11
7635 prim_subreg #(
7636 .DW (1),
7637 .SwAccess(prim_subreg_pkg::SwAccessRO),
7638 .RESVAL (1'h0),
7639 .Mubi (1'b0)
7640 ) u_ip_1_p_43 (
7641 .clk_i (clk_i),
7642 .rst_ni (rst_ni),
7643
7644 // from register interface
7645 .we (1'b0),
7646 .wd ('0),
7647
7648 // from internal hardware
7649 .de (hw2reg.ip[43].de),
7650 .d (hw2reg.ip[43].d),
7651
7652 // to internal hardware
7653 .qe (),
7654 .q (),
7655 .ds (),
7656
7657 // to register interface (read)
7658 .qs (ip_1_p_43_qs)
7659 );
7660
7661 // F[p_44]: 12:12
7662 prim_subreg #(
7663 .DW (1),
7664 .SwAccess(prim_subreg_pkg::SwAccessRO),
7665 .RESVAL (1'h0),
7666 .Mubi (1'b0)
7667 ) u_ip_1_p_44 (
7668 .clk_i (clk_i),
7669 .rst_ni (rst_ni),
7670
7671 // from register interface
7672 .we (1'b0),
7673 .wd ('0),
7674
7675 // from internal hardware
7676 .de (hw2reg.ip[44].de),
7677 .d (hw2reg.ip[44].d),
7678
7679 // to internal hardware
7680 .qe (),
7681 .q (),
7682 .ds (),
7683
7684 // to register interface (read)
7685 .qs (ip_1_p_44_qs)
7686 );
7687
7688 // F[p_45]: 13:13
7689 prim_subreg #(
7690 .DW (1),
7691 .SwAccess(prim_subreg_pkg::SwAccessRO),
7692 .RESVAL (1'h0),
7693 .Mubi (1'b0)
7694 ) u_ip_1_p_45 (
7695 .clk_i (clk_i),
7696 .rst_ni (rst_ni),
7697
7698 // from register interface
7699 .we (1'b0),
7700 .wd ('0),
7701
7702 // from internal hardware
7703 .de (hw2reg.ip[45].de),
7704 .d (hw2reg.ip[45].d),
7705
7706 // to internal hardware
7707 .qe (),
7708 .q (),
7709 .ds (),
7710
7711 // to register interface (read)
7712 .qs (ip_1_p_45_qs)
7713 );
7714
7715 // F[p_46]: 14:14
7716 prim_subreg #(
7717 .DW (1),
7718 .SwAccess(prim_subreg_pkg::SwAccessRO),
7719 .RESVAL (1'h0),
7720 .Mubi (1'b0)
7721 ) u_ip_1_p_46 (
7722 .clk_i (clk_i),
7723 .rst_ni (rst_ni),
7724
7725 // from register interface
7726 .we (1'b0),
7727 .wd ('0),
7728
7729 // from internal hardware
7730 .de (hw2reg.ip[46].de),
7731 .d (hw2reg.ip[46].d),
7732
7733 // to internal hardware
7734 .qe (),
7735 .q (),
7736 .ds (),
7737
7738 // to register interface (read)
7739 .qs (ip_1_p_46_qs)
7740 );
7741
7742 // F[p_47]: 15:15
7743 prim_subreg #(
7744 .DW (1),
7745 .SwAccess(prim_subreg_pkg::SwAccessRO),
7746 .RESVAL (1'h0),
7747 .Mubi (1'b0)
7748 ) u_ip_1_p_47 (
7749 .clk_i (clk_i),
7750 .rst_ni (rst_ni),
7751
7752 // from register interface
7753 .we (1'b0),
7754 .wd ('0),
7755
7756 // from internal hardware
7757 .de (hw2reg.ip[47].de),
7758 .d (hw2reg.ip[47].d),
7759
7760 // to internal hardware
7761 .qe (),
7762 .q (),
7763 .ds (),
7764
7765 // to register interface (read)
7766 .qs (ip_1_p_47_qs)
7767 );
7768
7769 // F[p_48]: 16:16
7770 prim_subreg #(
7771 .DW (1),
7772 .SwAccess(prim_subreg_pkg::SwAccessRO),
7773 .RESVAL (1'h0),
7774 .Mubi (1'b0)
7775 ) u_ip_1_p_48 (
7776 .clk_i (clk_i),
7777 .rst_ni (rst_ni),
7778
7779 // from register interface
7780 .we (1'b0),
7781 .wd ('0),
7782
7783 // from internal hardware
7784 .de (hw2reg.ip[48].de),
7785 .d (hw2reg.ip[48].d),
7786
7787 // to internal hardware
7788 .qe (),
7789 .q (),
7790 .ds (),
7791
7792 // to register interface (read)
7793 .qs (ip_1_p_48_qs)
7794 );
7795
7796 // F[p_49]: 17:17
7797 prim_subreg #(
7798 .DW (1),
7799 .SwAccess(prim_subreg_pkg::SwAccessRO),
7800 .RESVAL (1'h0),
7801 .Mubi (1'b0)
7802 ) u_ip_1_p_49 (
7803 .clk_i (clk_i),
7804 .rst_ni (rst_ni),
7805
7806 // from register interface
7807 .we (1'b0),
7808 .wd ('0),
7809
7810 // from internal hardware
7811 .de (hw2reg.ip[49].de),
7812 .d (hw2reg.ip[49].d),
7813
7814 // to internal hardware
7815 .qe (),
7816 .q (),
7817 .ds (),
7818
7819 // to register interface (read)
7820 .qs (ip_1_p_49_qs)
7821 );
7822
7823 // F[p_50]: 18:18
7824 prim_subreg #(
7825 .DW (1),
7826 .SwAccess(prim_subreg_pkg::SwAccessRO),
7827 .RESVAL (1'h0),
7828 .Mubi (1'b0)
7829 ) u_ip_1_p_50 (
7830 .clk_i (clk_i),
7831 .rst_ni (rst_ni),
7832
7833 // from register interface
7834 .we (1'b0),
7835 .wd ('0),
7836
7837 // from internal hardware
7838 .de (hw2reg.ip[50].de),
7839 .d (hw2reg.ip[50].d),
7840
7841 // to internal hardware
7842 .qe (),
7843 .q (),
7844 .ds (),
7845
7846 // to register interface (read)
7847 .qs (ip_1_p_50_qs)
7848 );
7849
7850 // F[p_51]: 19:19
7851 prim_subreg #(
7852 .DW (1),
7853 .SwAccess(prim_subreg_pkg::SwAccessRO),
7854 .RESVAL (1'h0),
7855 .Mubi (1'b0)
7856 ) u_ip_1_p_51 (
7857 .clk_i (clk_i),
7858 .rst_ni (rst_ni),
7859
7860 // from register interface
7861 .we (1'b0),
7862 .wd ('0),
7863
7864 // from internal hardware
7865 .de (hw2reg.ip[51].de),
7866 .d (hw2reg.ip[51].d),
7867
7868 // to internal hardware
7869 .qe (),
7870 .q (),
7871 .ds (),
7872
7873 // to register interface (read)
7874 .qs (ip_1_p_51_qs)
7875 );
7876
7877 // F[p_52]: 20:20
7878 prim_subreg #(
7879 .DW (1),
7880 .SwAccess(prim_subreg_pkg::SwAccessRO),
7881 .RESVAL (1'h0),
7882 .Mubi (1'b0)
7883 ) u_ip_1_p_52 (
7884 .clk_i (clk_i),
7885 .rst_ni (rst_ni),
7886
7887 // from register interface
7888 .we (1'b0),
7889 .wd ('0),
7890
7891 // from internal hardware
7892 .de (hw2reg.ip[52].de),
7893 .d (hw2reg.ip[52].d),
7894
7895 // to internal hardware
7896 .qe (),
7897 .q (),
7898 .ds (),
7899
7900 // to register interface (read)
7901 .qs (ip_1_p_52_qs)
7902 );
7903
7904 // F[p_53]: 21:21
7905 prim_subreg #(
7906 .DW (1),
7907 .SwAccess(prim_subreg_pkg::SwAccessRO),
7908 .RESVAL (1'h0),
7909 .Mubi (1'b0)
7910 ) u_ip_1_p_53 (
7911 .clk_i (clk_i),
7912 .rst_ni (rst_ni),
7913
7914 // from register interface
7915 .we (1'b0),
7916 .wd ('0),
7917
7918 // from internal hardware
7919 .de (hw2reg.ip[53].de),
7920 .d (hw2reg.ip[53].d),
7921
7922 // to internal hardware
7923 .qe (),
7924 .q (),
7925 .ds (),
7926
7927 // to register interface (read)
7928 .qs (ip_1_p_53_qs)
7929 );
7930
7931 // F[p_54]: 22:22
7932 prim_subreg #(
7933 .DW (1),
7934 .SwAccess(prim_subreg_pkg::SwAccessRO),
7935 .RESVAL (1'h0),
7936 .Mubi (1'b0)
7937 ) u_ip_1_p_54 (
7938 .clk_i (clk_i),
7939 .rst_ni (rst_ni),
7940
7941 // from register interface
7942 .we (1'b0),
7943 .wd ('0),
7944
7945 // from internal hardware
7946 .de (hw2reg.ip[54].de),
7947 .d (hw2reg.ip[54].d),
7948
7949 // to internal hardware
7950 .qe (),
7951 .q (),
7952 .ds (),
7953
7954 // to register interface (read)
7955 .qs (ip_1_p_54_qs)
7956 );
7957
7958 // F[p_55]: 23:23
7959 prim_subreg #(
7960 .DW (1),
7961 .SwAccess(prim_subreg_pkg::SwAccessRO),
7962 .RESVAL (1'h0),
7963 .Mubi (1'b0)
7964 ) u_ip_1_p_55 (
7965 .clk_i (clk_i),
7966 .rst_ni (rst_ni),
7967
7968 // from register interface
7969 .we (1'b0),
7970 .wd ('0),
7971
7972 // from internal hardware
7973 .de (hw2reg.ip[55].de),
7974 .d (hw2reg.ip[55].d),
7975
7976 // to internal hardware
7977 .qe (),
7978 .q (),
7979 .ds (),
7980
7981 // to register interface (read)
7982 .qs (ip_1_p_55_qs)
7983 );
7984
7985 // F[p_56]: 24:24
7986 prim_subreg #(
7987 .DW (1),
7988 .SwAccess(prim_subreg_pkg::SwAccessRO),
7989 .RESVAL (1'h0),
7990 .Mubi (1'b0)
7991 ) u_ip_1_p_56 (
7992 .clk_i (clk_i),
7993 .rst_ni (rst_ni),
7994
7995 // from register interface
7996 .we (1'b0),
7997 .wd ('0),
7998
7999 // from internal hardware
8000 .de (hw2reg.ip[56].de),
8001 .d (hw2reg.ip[56].d),
8002
8003 // to internal hardware
8004 .qe (),
8005 .q (),
8006 .ds (),
8007
8008 // to register interface (read)
8009 .qs (ip_1_p_56_qs)
8010 );
8011
8012 // F[p_57]: 25:25
8013 prim_subreg #(
8014 .DW (1),
8015 .SwAccess(prim_subreg_pkg::SwAccessRO),
8016 .RESVAL (1'h0),
8017 .Mubi (1'b0)
8018 ) u_ip_1_p_57 (
8019 .clk_i (clk_i),
8020 .rst_ni (rst_ni),
8021
8022 // from register interface
8023 .we (1'b0),
8024 .wd ('0),
8025
8026 // from internal hardware
8027 .de (hw2reg.ip[57].de),
8028 .d (hw2reg.ip[57].d),
8029
8030 // to internal hardware
8031 .qe (),
8032 .q (),
8033 .ds (),
8034
8035 // to register interface (read)
8036 .qs (ip_1_p_57_qs)
8037 );
8038
8039 // F[p_58]: 26:26
8040 prim_subreg #(
8041 .DW (1),
8042 .SwAccess(prim_subreg_pkg::SwAccessRO),
8043 .RESVAL (1'h0),
8044 .Mubi (1'b0)
8045 ) u_ip_1_p_58 (
8046 .clk_i (clk_i),
8047 .rst_ni (rst_ni),
8048
8049 // from register interface
8050 .we (1'b0),
8051 .wd ('0),
8052
8053 // from internal hardware
8054 .de (hw2reg.ip[58].de),
8055 .d (hw2reg.ip[58].d),
8056
8057 // to internal hardware
8058 .qe (),
8059 .q (),
8060 .ds (),
8061
8062 // to register interface (read)
8063 .qs (ip_1_p_58_qs)
8064 );
8065
8066 // F[p_59]: 27:27
8067 prim_subreg #(
8068 .DW (1),
8069 .SwAccess(prim_subreg_pkg::SwAccessRO),
8070 .RESVAL (1'h0),
8071 .Mubi (1'b0)
8072 ) u_ip_1_p_59 (
8073 .clk_i (clk_i),
8074 .rst_ni (rst_ni),
8075
8076 // from register interface
8077 .we (1'b0),
8078 .wd ('0),
8079
8080 // from internal hardware
8081 .de (hw2reg.ip[59].de),
8082 .d (hw2reg.ip[59].d),
8083
8084 // to internal hardware
8085 .qe (),
8086 .q (),
8087 .ds (),
8088
8089 // to register interface (read)
8090 .qs (ip_1_p_59_qs)
8091 );
8092
8093 // F[p_60]: 28:28
8094 prim_subreg #(
8095 .DW (1),
8096 .SwAccess(prim_subreg_pkg::SwAccessRO),
8097 .RESVAL (1'h0),
8098 .Mubi (1'b0)
8099 ) u_ip_1_p_60 (
8100 .clk_i (clk_i),
8101 .rst_ni (rst_ni),
8102
8103 // from register interface
8104 .we (1'b0),
8105 .wd ('0),
8106
8107 // from internal hardware
8108 .de (hw2reg.ip[60].de),
8109 .d (hw2reg.ip[60].d),
8110
8111 // to internal hardware
8112 .qe (),
8113 .q (),
8114 .ds (),
8115
8116 // to register interface (read)
8117 .qs (ip_1_p_60_qs)
8118 );
8119
8120 // F[p_61]: 29:29
8121 prim_subreg #(
8122 .DW (1),
8123 .SwAccess(prim_subreg_pkg::SwAccessRO),
8124 .RESVAL (1'h0),
8125 .Mubi (1'b0)
8126 ) u_ip_1_p_61 (
8127 .clk_i (clk_i),
8128 .rst_ni (rst_ni),
8129
8130 // from register interface
8131 .we (1'b0),
8132 .wd ('0),
8133
8134 // from internal hardware
8135 .de (hw2reg.ip[61].de),
8136 .d (hw2reg.ip[61].d),
8137
8138 // to internal hardware
8139 .qe (),
8140 .q (),
8141 .ds (),
8142
8143 // to register interface (read)
8144 .qs (ip_1_p_61_qs)
8145 );
8146
8147 // F[p_62]: 30:30
8148 prim_subreg #(
8149 .DW (1),
8150 .SwAccess(prim_subreg_pkg::SwAccessRO),
8151 .RESVAL (1'h0),
8152 .Mubi (1'b0)
8153 ) u_ip_1_p_62 (
8154 .clk_i (clk_i),
8155 .rst_ni (rst_ni),
8156
8157 // from register interface
8158 .we (1'b0),
8159 .wd ('0),
8160
8161 // from internal hardware
8162 .de (hw2reg.ip[62].de),
8163 .d (hw2reg.ip[62].d),
8164
8165 // to internal hardware
8166 .qe (),
8167 .q (),
8168 .ds (),
8169
8170 // to register interface (read)
8171 .qs (ip_1_p_62_qs)
8172 );
8173
8174 // F[p_63]: 31:31
8175 prim_subreg #(
8176 .DW (1),
8177 .SwAccess(prim_subreg_pkg::SwAccessRO),
8178 .RESVAL (1'h0),
8179 .Mubi (1'b0)
8180 ) u_ip_1_p_63 (
8181 .clk_i (clk_i),
8182 .rst_ni (rst_ni),
8183
8184 // from register interface
8185 .we (1'b0),
8186 .wd ('0),
8187
8188 // from internal hardware
8189 .de (hw2reg.ip[63].de),
8190 .d (hw2reg.ip[63].d),
8191
8192 // to internal hardware
8193 .qe (),
8194 .q (),
8195 .ds (),
8196
8197 // to register interface (read)
8198 .qs (ip_1_p_63_qs)
8199 );
8200
8201
8202 // Subregister 2 of Multireg ip
8203 // R[ip_2]: V(False)
8204 // F[p_64]: 0:0
8205 prim_subreg #(
8206 .DW (1),
8207 .SwAccess(prim_subreg_pkg::SwAccessRO),
8208 .RESVAL (1'h0),
8209 .Mubi (1'b0)
8210 ) u_ip_2_p_64 (
8211 .clk_i (clk_i),
8212 .rst_ni (rst_ni),
8213
8214 // from register interface
8215 .we (1'b0),
8216 .wd ('0),
8217
8218 // from internal hardware
8219 .de (hw2reg.ip[64].de),
8220 .d (hw2reg.ip[64].d),
8221
8222 // to internal hardware
8223 .qe (),
8224 .q (),
8225 .ds (),
8226
8227 // to register interface (read)
8228 .qs (ip_2_p_64_qs)
8229 );
8230
8231 // F[p_65]: 1:1
8232 prim_subreg #(
8233 .DW (1),
8234 .SwAccess(prim_subreg_pkg::SwAccessRO),
8235 .RESVAL (1'h0),
8236 .Mubi (1'b0)
8237 ) u_ip_2_p_65 (
8238 .clk_i (clk_i),
8239 .rst_ni (rst_ni),
8240
8241 // from register interface
8242 .we (1'b0),
8243 .wd ('0),
8244
8245 // from internal hardware
8246 .de (hw2reg.ip[65].de),
8247 .d (hw2reg.ip[65].d),
8248
8249 // to internal hardware
8250 .qe (),
8251 .q (),
8252 .ds (),
8253
8254 // to register interface (read)
8255 .qs (ip_2_p_65_qs)
8256 );
8257
8258 // F[p_66]: 2:2
8259 prim_subreg #(
8260 .DW (1),
8261 .SwAccess(prim_subreg_pkg::SwAccessRO),
8262 .RESVAL (1'h0),
8263 .Mubi (1'b0)
8264 ) u_ip_2_p_66 (
8265 .clk_i (clk_i),
8266 .rst_ni (rst_ni),
8267
8268 // from register interface
8269 .we (1'b0),
8270 .wd ('0),
8271
8272 // from internal hardware
8273 .de (hw2reg.ip[66].de),
8274 .d (hw2reg.ip[66].d),
8275
8276 // to internal hardware
8277 .qe (),
8278 .q (),
8279 .ds (),
8280
8281 // to register interface (read)
8282 .qs (ip_2_p_66_qs)
8283 );
8284
8285 // F[p_67]: 3:3
8286 prim_subreg #(
8287 .DW (1),
8288 .SwAccess(prim_subreg_pkg::SwAccessRO),
8289 .RESVAL (1'h0),
8290 .Mubi (1'b0)
8291 ) u_ip_2_p_67 (
8292 .clk_i (clk_i),
8293 .rst_ni (rst_ni),
8294
8295 // from register interface
8296 .we (1'b0),
8297 .wd ('0),
8298
8299 // from internal hardware
8300 .de (hw2reg.ip[67].de),
8301 .d (hw2reg.ip[67].d),
8302
8303 // to internal hardware
8304 .qe (),
8305 .q (),
8306 .ds (),
8307
8308 // to register interface (read)
8309 .qs (ip_2_p_67_qs)
8310 );
8311
8312 // F[p_68]: 4:4
8313 prim_subreg #(
8314 .DW (1),
8315 .SwAccess(prim_subreg_pkg::SwAccessRO),
8316 .RESVAL (1'h0),
8317 .Mubi (1'b0)
8318 ) u_ip_2_p_68 (
8319 .clk_i (clk_i),
8320 .rst_ni (rst_ni),
8321
8322 // from register interface
8323 .we (1'b0),
8324 .wd ('0),
8325
8326 // from internal hardware
8327 .de (hw2reg.ip[68].de),
8328 .d (hw2reg.ip[68].d),
8329
8330 // to internal hardware
8331 .qe (),
8332 .q (),
8333 .ds (),
8334
8335 // to register interface (read)
8336 .qs (ip_2_p_68_qs)
8337 );
8338
8339 // F[p_69]: 5:5
8340 prim_subreg #(
8341 .DW (1),
8342 .SwAccess(prim_subreg_pkg::SwAccessRO),
8343 .RESVAL (1'h0),
8344 .Mubi (1'b0)
8345 ) u_ip_2_p_69 (
8346 .clk_i (clk_i),
8347 .rst_ni (rst_ni),
8348
8349 // from register interface
8350 .we (1'b0),
8351 .wd ('0),
8352
8353 // from internal hardware
8354 .de (hw2reg.ip[69].de),
8355 .d (hw2reg.ip[69].d),
8356
8357 // to internal hardware
8358 .qe (),
8359 .q (),
8360 .ds (),
8361
8362 // to register interface (read)
8363 .qs (ip_2_p_69_qs)
8364 );
8365
8366 // F[p_70]: 6:6
8367 prim_subreg #(
8368 .DW (1),
8369 .SwAccess(prim_subreg_pkg::SwAccessRO),
8370 .RESVAL (1'h0),
8371 .Mubi (1'b0)
8372 ) u_ip_2_p_70 (
8373 .clk_i (clk_i),
8374 .rst_ni (rst_ni),
8375
8376 // from register interface
8377 .we (1'b0),
8378 .wd ('0),
8379
8380 // from internal hardware
8381 .de (hw2reg.ip[70].de),
8382 .d (hw2reg.ip[70].d),
8383
8384 // to internal hardware
8385 .qe (),
8386 .q (),
8387 .ds (),
8388
8389 // to register interface (read)
8390 .qs (ip_2_p_70_qs)
8391 );
8392
8393 // F[p_71]: 7:7
8394 prim_subreg #(
8395 .DW (1),
8396 .SwAccess(prim_subreg_pkg::SwAccessRO),
8397 .RESVAL (1'h0),
8398 .Mubi (1'b0)
8399 ) u_ip_2_p_71 (
8400 .clk_i (clk_i),
8401 .rst_ni (rst_ni),
8402
8403 // from register interface
8404 .we (1'b0),
8405 .wd ('0),
8406
8407 // from internal hardware
8408 .de (hw2reg.ip[71].de),
8409 .d (hw2reg.ip[71].d),
8410
8411 // to internal hardware
8412 .qe (),
8413 .q (),
8414 .ds (),
8415
8416 // to register interface (read)
8417 .qs (ip_2_p_71_qs)
8418 );
8419
8420 // F[p_72]: 8:8
8421 prim_subreg #(
8422 .DW (1),
8423 .SwAccess(prim_subreg_pkg::SwAccessRO),
8424 .RESVAL (1'h0),
8425 .Mubi (1'b0)
8426 ) u_ip_2_p_72 (
8427 .clk_i (clk_i),
8428 .rst_ni (rst_ni),
8429
8430 // from register interface
8431 .we (1'b0),
8432 .wd ('0),
8433
8434 // from internal hardware
8435 .de (hw2reg.ip[72].de),
8436 .d (hw2reg.ip[72].d),
8437
8438 // to internal hardware
8439 .qe (),
8440 .q (),
8441 .ds (),
8442
8443 // to register interface (read)
8444 .qs (ip_2_p_72_qs)
8445 );
8446
8447 // F[p_73]: 9:9
8448 prim_subreg #(
8449 .DW (1),
8450 .SwAccess(prim_subreg_pkg::SwAccessRO),
8451 .RESVAL (1'h0),
8452 .Mubi (1'b0)
8453 ) u_ip_2_p_73 (
8454 .clk_i (clk_i),
8455 .rst_ni (rst_ni),
8456
8457 // from register interface
8458 .we (1'b0),
8459 .wd ('0),
8460
8461 // from internal hardware
8462 .de (hw2reg.ip[73].de),
8463 .d (hw2reg.ip[73].d),
8464
8465 // to internal hardware
8466 .qe (),
8467 .q (),
8468 .ds (),
8469
8470 // to register interface (read)
8471 .qs (ip_2_p_73_qs)
8472 );
8473
8474 // F[p_74]: 10:10
8475 prim_subreg #(
8476 .DW (1),
8477 .SwAccess(prim_subreg_pkg::SwAccessRO),
8478 .RESVAL (1'h0),
8479 .Mubi (1'b0)
8480 ) u_ip_2_p_74 (
8481 .clk_i (clk_i),
8482 .rst_ni (rst_ni),
8483
8484 // from register interface
8485 .we (1'b0),
8486 .wd ('0),
8487
8488 // from internal hardware
8489 .de (hw2reg.ip[74].de),
8490 .d (hw2reg.ip[74].d),
8491
8492 // to internal hardware
8493 .qe (),
8494 .q (),
8495 .ds (),
8496
8497 // to register interface (read)
8498 .qs (ip_2_p_74_qs)
8499 );
8500
8501 // F[p_75]: 11:11
8502 prim_subreg #(
8503 .DW (1),
8504 .SwAccess(prim_subreg_pkg::SwAccessRO),
8505 .RESVAL (1'h0),
8506 .Mubi (1'b0)
8507 ) u_ip_2_p_75 (
8508 .clk_i (clk_i),
8509 .rst_ni (rst_ni),
8510
8511 // from register interface
8512 .we (1'b0),
8513 .wd ('0),
8514
8515 // from internal hardware
8516 .de (hw2reg.ip[75].de),
8517 .d (hw2reg.ip[75].d),
8518
8519 // to internal hardware
8520 .qe (),
8521 .q (),
8522 .ds (),
8523
8524 // to register interface (read)
8525 .qs (ip_2_p_75_qs)
8526 );
8527
8528 // F[p_76]: 12:12
8529 prim_subreg #(
8530 .DW (1),
8531 .SwAccess(prim_subreg_pkg::SwAccessRO),
8532 .RESVAL (1'h0),
8533 .Mubi (1'b0)
8534 ) u_ip_2_p_76 (
8535 .clk_i (clk_i),
8536 .rst_ni (rst_ni),
8537
8538 // from register interface
8539 .we (1'b0),
8540 .wd ('0),
8541
8542 // from internal hardware
8543 .de (hw2reg.ip[76].de),
8544 .d (hw2reg.ip[76].d),
8545
8546 // to internal hardware
8547 .qe (),
8548 .q (),
8549 .ds (),
8550
8551 // to register interface (read)
8552 .qs (ip_2_p_76_qs)
8553 );
8554
8555 // F[p_77]: 13:13
8556 prim_subreg #(
8557 .DW (1),
8558 .SwAccess(prim_subreg_pkg::SwAccessRO),
8559 .RESVAL (1'h0),
8560 .Mubi (1'b0)
8561 ) u_ip_2_p_77 (
8562 .clk_i (clk_i),
8563 .rst_ni (rst_ni),
8564
8565 // from register interface
8566 .we (1'b0),
8567 .wd ('0),
8568
8569 // from internal hardware
8570 .de (hw2reg.ip[77].de),
8571 .d (hw2reg.ip[77].d),
8572
8573 // to internal hardware
8574 .qe (),
8575 .q (),
8576 .ds (),
8577
8578 // to register interface (read)
8579 .qs (ip_2_p_77_qs)
8580 );
8581
8582 // F[p_78]: 14:14
8583 prim_subreg #(
8584 .DW (1),
8585 .SwAccess(prim_subreg_pkg::SwAccessRO),
8586 .RESVAL (1'h0),
8587 .Mubi (1'b0)
8588 ) u_ip_2_p_78 (
8589 .clk_i (clk_i),
8590 .rst_ni (rst_ni),
8591
8592 // from register interface
8593 .we (1'b0),
8594 .wd ('0),
8595
8596 // from internal hardware
8597 .de (hw2reg.ip[78].de),
8598 .d (hw2reg.ip[78].d),
8599
8600 // to internal hardware
8601 .qe (),
8602 .q (),
8603 .ds (),
8604
8605 // to register interface (read)
8606 .qs (ip_2_p_78_qs)
8607 );
8608
8609 // F[p_79]: 15:15
8610 prim_subreg #(
8611 .DW (1),
8612 .SwAccess(prim_subreg_pkg::SwAccessRO),
8613 .RESVAL (1'h0),
8614 .Mubi (1'b0)
8615 ) u_ip_2_p_79 (
8616 .clk_i (clk_i),
8617 .rst_ni (rst_ni),
8618
8619 // from register interface
8620 .we (1'b0),
8621 .wd ('0),
8622
8623 // from internal hardware
8624 .de (hw2reg.ip[79].de),
8625 .d (hw2reg.ip[79].d),
8626
8627 // to internal hardware
8628 .qe (),
8629 .q (),
8630 .ds (),
8631
8632 // to register interface (read)
8633 .qs (ip_2_p_79_qs)
8634 );
8635
8636 // F[p_80]: 16:16
8637 prim_subreg #(
8638 .DW (1),
8639 .SwAccess(prim_subreg_pkg::SwAccessRO),
8640 .RESVAL (1'h0),
8641 .Mubi (1'b0)
8642 ) u_ip_2_p_80 (
8643 .clk_i (clk_i),
8644 .rst_ni (rst_ni),
8645
8646 // from register interface
8647 .we (1'b0),
8648 .wd ('0),
8649
8650 // from internal hardware
8651 .de (hw2reg.ip[80].de),
8652 .d (hw2reg.ip[80].d),
8653
8654 // to internal hardware
8655 .qe (),
8656 .q (),
8657 .ds (),
8658
8659 // to register interface (read)
8660 .qs (ip_2_p_80_qs)
8661 );
8662
8663 // F[p_81]: 17:17
8664 prim_subreg #(
8665 .DW (1),
8666 .SwAccess(prim_subreg_pkg::SwAccessRO),
8667 .RESVAL (1'h0),
8668 .Mubi (1'b0)
8669 ) u_ip_2_p_81 (
8670 .clk_i (clk_i),
8671 .rst_ni (rst_ni),
8672
8673 // from register interface
8674 .we (1'b0),
8675 .wd ('0),
8676
8677 // from internal hardware
8678 .de (hw2reg.ip[81].de),
8679 .d (hw2reg.ip[81].d),
8680
8681 // to internal hardware
8682 .qe (),
8683 .q (),
8684 .ds (),
8685
8686 // to register interface (read)
8687 .qs (ip_2_p_81_qs)
8688 );
8689
8690 // F[p_82]: 18:18
8691 prim_subreg #(
8692 .DW (1),
8693 .SwAccess(prim_subreg_pkg::SwAccessRO),
8694 .RESVAL (1'h0),
8695 .Mubi (1'b0)
8696 ) u_ip_2_p_82 (
8697 .clk_i (clk_i),
8698 .rst_ni (rst_ni),
8699
8700 // from register interface
8701 .we (1'b0),
8702 .wd ('0),
8703
8704 // from internal hardware
8705 .de (hw2reg.ip[82].de),
8706 .d (hw2reg.ip[82].d),
8707
8708 // to internal hardware
8709 .qe (),
8710 .q (),
8711 .ds (),
8712
8713 // to register interface (read)
8714 .qs (ip_2_p_82_qs)
8715 );
8716
8717 // F[p_83]: 19:19
8718 prim_subreg #(
8719 .DW (1),
8720 .SwAccess(prim_subreg_pkg::SwAccessRO),
8721 .RESVAL (1'h0),
8722 .Mubi (1'b0)
8723 ) u_ip_2_p_83 (
8724 .clk_i (clk_i),
8725 .rst_ni (rst_ni),
8726
8727 // from register interface
8728 .we (1'b0),
8729 .wd ('0),
8730
8731 // from internal hardware
8732 .de (hw2reg.ip[83].de),
8733 .d (hw2reg.ip[83].d),
8734
8735 // to internal hardware
8736 .qe (),
8737 .q (),
8738 .ds (),
8739
8740 // to register interface (read)
8741 .qs (ip_2_p_83_qs)
8742 );
8743
8744 // F[p_84]: 20:20
8745 prim_subreg #(
8746 .DW (1),
8747 .SwAccess(prim_subreg_pkg::SwAccessRO),
8748 .RESVAL (1'h0),
8749 .Mubi (1'b0)
8750 ) u_ip_2_p_84 (
8751 .clk_i (clk_i),
8752 .rst_ni (rst_ni),
8753
8754 // from register interface
8755 .we (1'b0),
8756 .wd ('0),
8757
8758 // from internal hardware
8759 .de (hw2reg.ip[84].de),
8760 .d (hw2reg.ip[84].d),
8761
8762 // to internal hardware
8763 .qe (),
8764 .q (),
8765 .ds (),
8766
8767 // to register interface (read)
8768 .qs (ip_2_p_84_qs)
8769 );
8770
8771 // F[p_85]: 21:21
8772 prim_subreg #(
8773 .DW (1),
8774 .SwAccess(prim_subreg_pkg::SwAccessRO),
8775 .RESVAL (1'h0),
8776 .Mubi (1'b0)
8777 ) u_ip_2_p_85 (
8778 .clk_i (clk_i),
8779 .rst_ni (rst_ni),
8780
8781 // from register interface
8782 .we (1'b0),
8783 .wd ('0),
8784
8785 // from internal hardware
8786 .de (hw2reg.ip[85].de),
8787 .d (hw2reg.ip[85].d),
8788
8789 // to internal hardware
8790 .qe (),
8791 .q (),
8792 .ds (),
8793
8794 // to register interface (read)
8795 .qs (ip_2_p_85_qs)
8796 );
8797
8798 // F[p_86]: 22:22
8799 prim_subreg #(
8800 .DW (1),
8801 .SwAccess(prim_subreg_pkg::SwAccessRO),
8802 .RESVAL (1'h0),
8803 .Mubi (1'b0)
8804 ) u_ip_2_p_86 (
8805 .clk_i (clk_i),
8806 .rst_ni (rst_ni),
8807
8808 // from register interface
8809 .we (1'b0),
8810 .wd ('0),
8811
8812 // from internal hardware
8813 .de (hw2reg.ip[86].de),
8814 .d (hw2reg.ip[86].d),
8815
8816 // to internal hardware
8817 .qe (),
8818 .q (),
8819 .ds (),
8820
8821 // to register interface (read)
8822 .qs (ip_2_p_86_qs)
8823 );
8824
8825 // F[p_87]: 23:23
8826 prim_subreg #(
8827 .DW (1),
8828 .SwAccess(prim_subreg_pkg::SwAccessRO),
8829 .RESVAL (1'h0),
8830 .Mubi (1'b0)
8831 ) u_ip_2_p_87 (
8832 .clk_i (clk_i),
8833 .rst_ni (rst_ni),
8834
8835 // from register interface
8836 .we (1'b0),
8837 .wd ('0),
8838
8839 // from internal hardware
8840 .de (hw2reg.ip[87].de),
8841 .d (hw2reg.ip[87].d),
8842
8843 // to internal hardware
8844 .qe (),
8845 .q (),
8846 .ds (),
8847
8848 // to register interface (read)
8849 .qs (ip_2_p_87_qs)
8850 );
8851
8852 // F[p_88]: 24:24
8853 prim_subreg #(
8854 .DW (1),
8855 .SwAccess(prim_subreg_pkg::SwAccessRO),
8856 .RESVAL (1'h0),
8857 .Mubi (1'b0)
8858 ) u_ip_2_p_88 (
8859 .clk_i (clk_i),
8860 .rst_ni (rst_ni),
8861
8862 // from register interface
8863 .we (1'b0),
8864 .wd ('0),
8865
8866 // from internal hardware
8867 .de (hw2reg.ip[88].de),
8868 .d (hw2reg.ip[88].d),
8869
8870 // to internal hardware
8871 .qe (),
8872 .q (),
8873 .ds (),
8874
8875 // to register interface (read)
8876 .qs (ip_2_p_88_qs)
8877 );
8878
8879 // F[p_89]: 25:25
8880 prim_subreg #(
8881 .DW (1),
8882 .SwAccess(prim_subreg_pkg::SwAccessRO),
8883 .RESVAL (1'h0),
8884 .Mubi (1'b0)
8885 ) u_ip_2_p_89 (
8886 .clk_i (clk_i),
8887 .rst_ni (rst_ni),
8888
8889 // from register interface
8890 .we (1'b0),
8891 .wd ('0),
8892
8893 // from internal hardware
8894 .de (hw2reg.ip[89].de),
8895 .d (hw2reg.ip[89].d),
8896
8897 // to internal hardware
8898 .qe (),
8899 .q (),
8900 .ds (),
8901
8902 // to register interface (read)
8903 .qs (ip_2_p_89_qs)
8904 );
8905
8906 // F[p_90]: 26:26
8907 prim_subreg #(
8908 .DW (1),
8909 .SwAccess(prim_subreg_pkg::SwAccessRO),
8910 .RESVAL (1'h0),
8911 .Mubi (1'b0)
8912 ) u_ip_2_p_90 (
8913 .clk_i (clk_i),
8914 .rst_ni (rst_ni),
8915
8916 // from register interface
8917 .we (1'b0),
8918 .wd ('0),
8919
8920 // from internal hardware
8921 .de (hw2reg.ip[90].de),
8922 .d (hw2reg.ip[90].d),
8923
8924 // to internal hardware
8925 .qe (),
8926 .q (),
8927 .ds (),
8928
8929 // to register interface (read)
8930 .qs (ip_2_p_90_qs)
8931 );
8932
8933 // F[p_91]: 27:27
8934 prim_subreg #(
8935 .DW (1),
8936 .SwAccess(prim_subreg_pkg::SwAccessRO),
8937 .RESVAL (1'h0),
8938 .Mubi (1'b0)
8939 ) u_ip_2_p_91 (
8940 .clk_i (clk_i),
8941 .rst_ni (rst_ni),
8942
8943 // from register interface
8944 .we (1'b0),
8945 .wd ('0),
8946
8947 // from internal hardware
8948 .de (hw2reg.ip[91].de),
8949 .d (hw2reg.ip[91].d),
8950
8951 // to internal hardware
8952 .qe (),
8953 .q (),
8954 .ds (),
8955
8956 // to register interface (read)
8957 .qs (ip_2_p_91_qs)
8958 );
8959
8960 // F[p_92]: 28:28
8961 prim_subreg #(
8962 .DW (1),
8963 .SwAccess(prim_subreg_pkg::SwAccessRO),
8964 .RESVAL (1'h0),
8965 .Mubi (1'b0)
8966 ) u_ip_2_p_92 (
8967 .clk_i (clk_i),
8968 .rst_ni (rst_ni),
8969
8970 // from register interface
8971 .we (1'b0),
8972 .wd ('0),
8973
8974 // from internal hardware
8975 .de (hw2reg.ip[92].de),
8976 .d (hw2reg.ip[92].d),
8977
8978 // to internal hardware
8979 .qe (),
8980 .q (),
8981 .ds (),
8982
8983 // to register interface (read)
8984 .qs (ip_2_p_92_qs)
8985 );
8986
8987 // F[p_93]: 29:29
8988 prim_subreg #(
8989 .DW (1),
8990 .SwAccess(prim_subreg_pkg::SwAccessRO),
8991 .RESVAL (1'h0),
8992 .Mubi (1'b0)
8993 ) u_ip_2_p_93 (
8994 .clk_i (clk_i),
8995 .rst_ni (rst_ni),
8996
8997 // from register interface
8998 .we (1'b0),
8999 .wd ('0),
9000
9001 // from internal hardware
9002 .de (hw2reg.ip[93].de),
9003 .d (hw2reg.ip[93].d),
9004
9005 // to internal hardware
9006 .qe (),
9007 .q (),
9008 .ds (),
9009
9010 // to register interface (read)
9011 .qs (ip_2_p_93_qs)
9012 );
9013
9014 // F[p_94]: 30:30
9015 prim_subreg #(
9016 .DW (1),
9017 .SwAccess(prim_subreg_pkg::SwAccessRO),
9018 .RESVAL (1'h0),
9019 .Mubi (1'b0)
9020 ) u_ip_2_p_94 (
9021 .clk_i (clk_i),
9022 .rst_ni (rst_ni),
9023
9024 // from register interface
9025 .we (1'b0),
9026 .wd ('0),
9027
9028 // from internal hardware
9029 .de (hw2reg.ip[94].de),
9030 .d (hw2reg.ip[94].d),
9031
9032 // to internal hardware
9033 .qe (),
9034 .q (),
9035 .ds (),
9036
9037 // to register interface (read)
9038 .qs (ip_2_p_94_qs)
9039 );
9040
9041 // F[p_95]: 31:31
9042 prim_subreg #(
9043 .DW (1),
9044 .SwAccess(prim_subreg_pkg::SwAccessRO),
9045 .RESVAL (1'h0),
9046 .Mubi (1'b0)
9047 ) u_ip_2_p_95 (
9048 .clk_i (clk_i),
9049 .rst_ni (rst_ni),
9050
9051 // from register interface
9052 .we (1'b0),
9053 .wd ('0),
9054
9055 // from internal hardware
9056 .de (hw2reg.ip[95].de),
9057 .d (hw2reg.ip[95].d),
9058
9059 // to internal hardware
9060 .qe (),
9061 .q (),
9062 .ds (),
9063
9064 // to register interface (read)
9065 .qs (ip_2_p_95_qs)
9066 );
9067
9068
9069 // Subregister 3 of Multireg ip
9070 // R[ip_3]: V(False)
9071 // F[p_96]: 0:0
9072 prim_subreg #(
9073 .DW (1),
9074 .SwAccess(prim_subreg_pkg::SwAccessRO),
9075 .RESVAL (1'h0),
9076 .Mubi (1'b0)
9077 ) u_ip_3_p_96 (
9078 .clk_i (clk_i),
9079 .rst_ni (rst_ni),
9080
9081 // from register interface
9082 .we (1'b0),
9083 .wd ('0),
9084
9085 // from internal hardware
9086 .de (hw2reg.ip[96].de),
9087 .d (hw2reg.ip[96].d),
9088
9089 // to internal hardware
9090 .qe (),
9091 .q (),
9092 .ds (),
9093
9094 // to register interface (read)
9095 .qs (ip_3_p_96_qs)
9096 );
9097
9098 // F[p_97]: 1:1
9099 prim_subreg #(
9100 .DW (1),
9101 .SwAccess(prim_subreg_pkg::SwAccessRO),
9102 .RESVAL (1'h0),
9103 .Mubi (1'b0)
9104 ) u_ip_3_p_97 (
9105 .clk_i (clk_i),
9106 .rst_ni (rst_ni),
9107
9108 // from register interface
9109 .we (1'b0),
9110 .wd ('0),
9111
9112 // from internal hardware
9113 .de (hw2reg.ip[97].de),
9114 .d (hw2reg.ip[97].d),
9115
9116 // to internal hardware
9117 .qe (),
9118 .q (),
9119 .ds (),
9120
9121 // to register interface (read)
9122 .qs (ip_3_p_97_qs)
9123 );
9124
9125 // F[p_98]: 2:2
9126 prim_subreg #(
9127 .DW (1),
9128 .SwAccess(prim_subreg_pkg::SwAccessRO),
9129 .RESVAL (1'h0),
9130 .Mubi (1'b0)
9131 ) u_ip_3_p_98 (
9132 .clk_i (clk_i),
9133 .rst_ni (rst_ni),
9134
9135 // from register interface
9136 .we (1'b0),
9137 .wd ('0),
9138
9139 // from internal hardware
9140 .de (hw2reg.ip[98].de),
9141 .d (hw2reg.ip[98].d),
9142
9143 // to internal hardware
9144 .qe (),
9145 .q (),
9146 .ds (),
9147
9148 // to register interface (read)
9149 .qs (ip_3_p_98_qs)
9150 );
9151
9152 // F[p_99]: 3:3
9153 prim_subreg #(
9154 .DW (1),
9155 .SwAccess(prim_subreg_pkg::SwAccessRO),
9156 .RESVAL (1'h0),
9157 .Mubi (1'b0)
9158 ) u_ip_3_p_99 (
9159 .clk_i (clk_i),
9160 .rst_ni (rst_ni),
9161
9162 // from register interface
9163 .we (1'b0),
9164 .wd ('0),
9165
9166 // from internal hardware
9167 .de (hw2reg.ip[99].de),
9168 .d (hw2reg.ip[99].d),
9169
9170 // to internal hardware
9171 .qe (),
9172 .q (),
9173 .ds (),
9174
9175 // to register interface (read)
9176 .qs (ip_3_p_99_qs)
9177 );
9178
9179 // F[p_100]: 4:4
9180 prim_subreg #(
9181 .DW (1),
9182 .SwAccess(prim_subreg_pkg::SwAccessRO),
9183 .RESVAL (1'h0),
9184 .Mubi (1'b0)
9185 ) u_ip_3_p_100 (
9186 .clk_i (clk_i),
9187 .rst_ni (rst_ni),
9188
9189 // from register interface
9190 .we (1'b0),
9191 .wd ('0),
9192
9193 // from internal hardware
9194 .de (hw2reg.ip[100].de),
9195 .d (hw2reg.ip[100].d),
9196
9197 // to internal hardware
9198 .qe (),
9199 .q (),
9200 .ds (),
9201
9202 // to register interface (read)
9203 .qs (ip_3_p_100_qs)
9204 );
9205
9206 // F[p_101]: 5:5
9207 prim_subreg #(
9208 .DW (1),
9209 .SwAccess(prim_subreg_pkg::SwAccessRO),
9210 .RESVAL (1'h0),
9211 .Mubi (1'b0)
9212 ) u_ip_3_p_101 (
9213 .clk_i (clk_i),
9214 .rst_ni (rst_ni),
9215
9216 // from register interface
9217 .we (1'b0),
9218 .wd ('0),
9219
9220 // from internal hardware
9221 .de (hw2reg.ip[101].de),
9222 .d (hw2reg.ip[101].d),
9223
9224 // to internal hardware
9225 .qe (),
9226 .q (),
9227 .ds (),
9228
9229 // to register interface (read)
9230 .qs (ip_3_p_101_qs)
9231 );
9232
9233 // F[p_102]: 6:6
9234 prim_subreg #(
9235 .DW (1),
9236 .SwAccess(prim_subreg_pkg::SwAccessRO),
9237 .RESVAL (1'h0),
9238 .Mubi (1'b0)
9239 ) u_ip_3_p_102 (
9240 .clk_i (clk_i),
9241 .rst_ni (rst_ni),
9242
9243 // from register interface
9244 .we (1'b0),
9245 .wd ('0),
9246
9247 // from internal hardware
9248 .de (hw2reg.ip[102].de),
9249 .d (hw2reg.ip[102].d),
9250
9251 // to internal hardware
9252 .qe (),
9253 .q (),
9254 .ds (),
9255
9256 // to register interface (read)
9257 .qs (ip_3_p_102_qs)
9258 );
9259
9260 // F[p_103]: 7:7
9261 prim_subreg #(
9262 .DW (1),
9263 .SwAccess(prim_subreg_pkg::SwAccessRO),
9264 .RESVAL (1'h0),
9265 .Mubi (1'b0)
9266 ) u_ip_3_p_103 (
9267 .clk_i (clk_i),
9268 .rst_ni (rst_ni),
9269
9270 // from register interface
9271 .we (1'b0),
9272 .wd ('0),
9273
9274 // from internal hardware
9275 .de (hw2reg.ip[103].de),
9276 .d (hw2reg.ip[103].d),
9277
9278 // to internal hardware
9279 .qe (),
9280 .q (),
9281 .ds (),
9282
9283 // to register interface (read)
9284 .qs (ip_3_p_103_qs)
9285 );
9286
9287 // F[p_104]: 8:8
9288 prim_subreg #(
9289 .DW (1),
9290 .SwAccess(prim_subreg_pkg::SwAccessRO),
9291 .RESVAL (1'h0),
9292 .Mubi (1'b0)
9293 ) u_ip_3_p_104 (
9294 .clk_i (clk_i),
9295 .rst_ni (rst_ni),
9296
9297 // from register interface
9298 .we (1'b0),
9299 .wd ('0),
9300
9301 // from internal hardware
9302 .de (hw2reg.ip[104].de),
9303 .d (hw2reg.ip[104].d),
9304
9305 // to internal hardware
9306 .qe (),
9307 .q (),
9308 .ds (),
9309
9310 // to register interface (read)
9311 .qs (ip_3_p_104_qs)
9312 );
9313
9314 // F[p_105]: 9:9
9315 prim_subreg #(
9316 .DW (1),
9317 .SwAccess(prim_subreg_pkg::SwAccessRO),
9318 .RESVAL (1'h0),
9319 .Mubi (1'b0)
9320 ) u_ip_3_p_105 (
9321 .clk_i (clk_i),
9322 .rst_ni (rst_ni),
9323
9324 // from register interface
9325 .we (1'b0),
9326 .wd ('0),
9327
9328 // from internal hardware
9329 .de (hw2reg.ip[105].de),
9330 .d (hw2reg.ip[105].d),
9331
9332 // to internal hardware
9333 .qe (),
9334 .q (),
9335 .ds (),
9336
9337 // to register interface (read)
9338 .qs (ip_3_p_105_qs)
9339 );
9340
9341 // F[p_106]: 10:10
9342 prim_subreg #(
9343 .DW (1),
9344 .SwAccess(prim_subreg_pkg::SwAccessRO),
9345 .RESVAL (1'h0),
9346 .Mubi (1'b0)
9347 ) u_ip_3_p_106 (
9348 .clk_i (clk_i),
9349 .rst_ni (rst_ni),
9350
9351 // from register interface
9352 .we (1'b0),
9353 .wd ('0),
9354
9355 // from internal hardware
9356 .de (hw2reg.ip[106].de),
9357 .d (hw2reg.ip[106].d),
9358
9359 // to internal hardware
9360 .qe (),
9361 .q (),
9362 .ds (),
9363
9364 // to register interface (read)
9365 .qs (ip_3_p_106_qs)
9366 );
9367
9368 // F[p_107]: 11:11
9369 prim_subreg #(
9370 .DW (1),
9371 .SwAccess(prim_subreg_pkg::SwAccessRO),
9372 .RESVAL (1'h0),
9373 .Mubi (1'b0)
9374 ) u_ip_3_p_107 (
9375 .clk_i (clk_i),
9376 .rst_ni (rst_ni),
9377
9378 // from register interface
9379 .we (1'b0),
9380 .wd ('0),
9381
9382 // from internal hardware
9383 .de (hw2reg.ip[107].de),
9384 .d (hw2reg.ip[107].d),
9385
9386 // to internal hardware
9387 .qe (),
9388 .q (),
9389 .ds (),
9390
9391 // to register interface (read)
9392 .qs (ip_3_p_107_qs)
9393 );
9394
9395 // F[p_108]: 12:12
9396 prim_subreg #(
9397 .DW (1),
9398 .SwAccess(prim_subreg_pkg::SwAccessRO),
9399 .RESVAL (1'h0),
9400 .Mubi (1'b0)
9401 ) u_ip_3_p_108 (
9402 .clk_i (clk_i),
9403 .rst_ni (rst_ni),
9404
9405 // from register interface
9406 .we (1'b0),
9407 .wd ('0),
9408
9409 // from internal hardware
9410 .de (hw2reg.ip[108].de),
9411 .d (hw2reg.ip[108].d),
9412
9413 // to internal hardware
9414 .qe (),
9415 .q (),
9416 .ds (),
9417
9418 // to register interface (read)
9419 .qs (ip_3_p_108_qs)
9420 );
9421
9422 // F[p_109]: 13:13
9423 prim_subreg #(
9424 .DW (1),
9425 .SwAccess(prim_subreg_pkg::SwAccessRO),
9426 .RESVAL (1'h0),
9427 .Mubi (1'b0)
9428 ) u_ip_3_p_109 (
9429 .clk_i (clk_i),
9430 .rst_ni (rst_ni),
9431
9432 // from register interface
9433 .we (1'b0),
9434 .wd ('0),
9435
9436 // from internal hardware
9437 .de (hw2reg.ip[109].de),
9438 .d (hw2reg.ip[109].d),
9439
9440 // to internal hardware
9441 .qe (),
9442 .q (),
9443 .ds (),
9444
9445 // to register interface (read)
9446 .qs (ip_3_p_109_qs)
9447 );
9448
9449 // F[p_110]: 14:14
9450 prim_subreg #(
9451 .DW (1),
9452 .SwAccess(prim_subreg_pkg::SwAccessRO),
9453 .RESVAL (1'h0),
9454 .Mubi (1'b0)
9455 ) u_ip_3_p_110 (
9456 .clk_i (clk_i),
9457 .rst_ni (rst_ni),
9458
9459 // from register interface
9460 .we (1'b0),
9461 .wd ('0),
9462
9463 // from internal hardware
9464 .de (hw2reg.ip[110].de),
9465 .d (hw2reg.ip[110].d),
9466
9467 // to internal hardware
9468 .qe (),
9469 .q (),
9470 .ds (),
9471
9472 // to register interface (read)
9473 .qs (ip_3_p_110_qs)
9474 );
9475
9476 // F[p_111]: 15:15
9477 prim_subreg #(
9478 .DW (1),
9479 .SwAccess(prim_subreg_pkg::SwAccessRO),
9480 .RESVAL (1'h0),
9481 .Mubi (1'b0)
9482 ) u_ip_3_p_111 (
9483 .clk_i (clk_i),
9484 .rst_ni (rst_ni),
9485
9486 // from register interface
9487 .we (1'b0),
9488 .wd ('0),
9489
9490 // from internal hardware
9491 .de (hw2reg.ip[111].de),
9492 .d (hw2reg.ip[111].d),
9493
9494 // to internal hardware
9495 .qe (),
9496 .q (),
9497 .ds (),
9498
9499 // to register interface (read)
9500 .qs (ip_3_p_111_qs)
9501 );
9502
9503 // F[p_112]: 16:16
9504 prim_subreg #(
9505 .DW (1),
9506 .SwAccess(prim_subreg_pkg::SwAccessRO),
9507 .RESVAL (1'h0),
9508 .Mubi (1'b0)
9509 ) u_ip_3_p_112 (
9510 .clk_i (clk_i),
9511 .rst_ni (rst_ni),
9512
9513 // from register interface
9514 .we (1'b0),
9515 .wd ('0),
9516
9517 // from internal hardware
9518 .de (hw2reg.ip[112].de),
9519 .d (hw2reg.ip[112].d),
9520
9521 // to internal hardware
9522 .qe (),
9523 .q (),
9524 .ds (),
9525
9526 // to register interface (read)
9527 .qs (ip_3_p_112_qs)
9528 );
9529
9530 // F[p_113]: 17:17
9531 prim_subreg #(
9532 .DW (1),
9533 .SwAccess(prim_subreg_pkg::SwAccessRO),
9534 .RESVAL (1'h0),
9535 .Mubi (1'b0)
9536 ) u_ip_3_p_113 (
9537 .clk_i (clk_i),
9538 .rst_ni (rst_ni),
9539
9540 // from register interface
9541 .we (1'b0),
9542 .wd ('0),
9543
9544 // from internal hardware
9545 .de (hw2reg.ip[113].de),
9546 .d (hw2reg.ip[113].d),
9547
9548 // to internal hardware
9549 .qe (),
9550 .q (),
9551 .ds (),
9552
9553 // to register interface (read)
9554 .qs (ip_3_p_113_qs)
9555 );
9556
9557 // F[p_114]: 18:18
9558 prim_subreg #(
9559 .DW (1),
9560 .SwAccess(prim_subreg_pkg::SwAccessRO),
9561 .RESVAL (1'h0),
9562 .Mubi (1'b0)
9563 ) u_ip_3_p_114 (
9564 .clk_i (clk_i),
9565 .rst_ni (rst_ni),
9566
9567 // from register interface
9568 .we (1'b0),
9569 .wd ('0),
9570
9571 // from internal hardware
9572 .de (hw2reg.ip[114].de),
9573 .d (hw2reg.ip[114].d),
9574
9575 // to internal hardware
9576 .qe (),
9577 .q (),
9578 .ds (),
9579
9580 // to register interface (read)
9581 .qs (ip_3_p_114_qs)
9582 );
9583
9584 // F[p_115]: 19:19
9585 prim_subreg #(
9586 .DW (1),
9587 .SwAccess(prim_subreg_pkg::SwAccessRO),
9588 .RESVAL (1'h0),
9589 .Mubi (1'b0)
9590 ) u_ip_3_p_115 (
9591 .clk_i (clk_i),
9592 .rst_ni (rst_ni),
9593
9594 // from register interface
9595 .we (1'b0),
9596 .wd ('0),
9597
9598 // from internal hardware
9599 .de (hw2reg.ip[115].de),
9600 .d (hw2reg.ip[115].d),
9601
9602 // to internal hardware
9603 .qe (),
9604 .q (),
9605 .ds (),
9606
9607 // to register interface (read)
9608 .qs (ip_3_p_115_qs)
9609 );
9610
9611 // F[p_116]: 20:20
9612 prim_subreg #(
9613 .DW (1),
9614 .SwAccess(prim_subreg_pkg::SwAccessRO),
9615 .RESVAL (1'h0),
9616 .Mubi (1'b0)
9617 ) u_ip_3_p_116 (
9618 .clk_i (clk_i),
9619 .rst_ni (rst_ni),
9620
9621 // from register interface
9622 .we (1'b0),
9623 .wd ('0),
9624
9625 // from internal hardware
9626 .de (hw2reg.ip[116].de),
9627 .d (hw2reg.ip[116].d),
9628
9629 // to internal hardware
9630 .qe (),
9631 .q (),
9632 .ds (),
9633
9634 // to register interface (read)
9635 .qs (ip_3_p_116_qs)
9636 );
9637
9638 // F[p_117]: 21:21
9639 prim_subreg #(
9640 .DW (1),
9641 .SwAccess(prim_subreg_pkg::SwAccessRO),
9642 .RESVAL (1'h0),
9643 .Mubi (1'b0)
9644 ) u_ip_3_p_117 (
9645 .clk_i (clk_i),
9646 .rst_ni (rst_ni),
9647
9648 // from register interface
9649 .we (1'b0),
9650 .wd ('0),
9651
9652 // from internal hardware
9653 .de (hw2reg.ip[117].de),
9654 .d (hw2reg.ip[117].d),
9655
9656 // to internal hardware
9657 .qe (),
9658 .q (),
9659 .ds (),
9660
9661 // to register interface (read)
9662 .qs (ip_3_p_117_qs)
9663 );
9664
9665 // F[p_118]: 22:22
9666 prim_subreg #(
9667 .DW (1),
9668 .SwAccess(prim_subreg_pkg::SwAccessRO),
9669 .RESVAL (1'h0),
9670 .Mubi (1'b0)
9671 ) u_ip_3_p_118 (
9672 .clk_i (clk_i),
9673 .rst_ni (rst_ni),
9674
9675 // from register interface
9676 .we (1'b0),
9677 .wd ('0),
9678
9679 // from internal hardware
9680 .de (hw2reg.ip[118].de),
9681 .d (hw2reg.ip[118].d),
9682
9683 // to internal hardware
9684 .qe (),
9685 .q (),
9686 .ds (),
9687
9688 // to register interface (read)
9689 .qs (ip_3_p_118_qs)
9690 );
9691
9692 // F[p_119]: 23:23
9693 prim_subreg #(
9694 .DW (1),
9695 .SwAccess(prim_subreg_pkg::SwAccessRO),
9696 .RESVAL (1'h0),
9697 .Mubi (1'b0)
9698 ) u_ip_3_p_119 (
9699 .clk_i (clk_i),
9700 .rst_ni (rst_ni),
9701
9702 // from register interface
9703 .we (1'b0),
9704 .wd ('0),
9705
9706 // from internal hardware
9707 .de (hw2reg.ip[119].de),
9708 .d (hw2reg.ip[119].d),
9709
9710 // to internal hardware
9711 .qe (),
9712 .q (),
9713 .ds (),
9714
9715 // to register interface (read)
9716 .qs (ip_3_p_119_qs)
9717 );
9718
9719 // F[p_120]: 24:24
9720 prim_subreg #(
9721 .DW (1),
9722 .SwAccess(prim_subreg_pkg::SwAccessRO),
9723 .RESVAL (1'h0),
9724 .Mubi (1'b0)
9725 ) u_ip_3_p_120 (
9726 .clk_i (clk_i),
9727 .rst_ni (rst_ni),
9728
9729 // from register interface
9730 .we (1'b0),
9731 .wd ('0),
9732
9733 // from internal hardware
9734 .de (hw2reg.ip[120].de),
9735 .d (hw2reg.ip[120].d),
9736
9737 // to internal hardware
9738 .qe (),
9739 .q (),
9740 .ds (),
9741
9742 // to register interface (read)
9743 .qs (ip_3_p_120_qs)
9744 );
9745
9746 // F[p_121]: 25:25
9747 prim_subreg #(
9748 .DW (1),
9749 .SwAccess(prim_subreg_pkg::SwAccessRO),
9750 .RESVAL (1'h0),
9751 .Mubi (1'b0)
9752 ) u_ip_3_p_121 (
9753 .clk_i (clk_i),
9754 .rst_ni (rst_ni),
9755
9756 // from register interface
9757 .we (1'b0),
9758 .wd ('0),
9759
9760 // from internal hardware
9761 .de (hw2reg.ip[121].de),
9762 .d (hw2reg.ip[121].d),
9763
9764 // to internal hardware
9765 .qe (),
9766 .q (),
9767 .ds (),
9768
9769 // to register interface (read)
9770 .qs (ip_3_p_121_qs)
9771 );
9772
9773 // F[p_122]: 26:26
9774 prim_subreg #(
9775 .DW (1),
9776 .SwAccess(prim_subreg_pkg::SwAccessRO),
9777 .RESVAL (1'h0),
9778 .Mubi (1'b0)
9779 ) u_ip_3_p_122 (
9780 .clk_i (clk_i),
9781 .rst_ni (rst_ni),
9782
9783 // from register interface
9784 .we (1'b0),
9785 .wd ('0),
9786
9787 // from internal hardware
9788 .de (hw2reg.ip[122].de),
9789 .d (hw2reg.ip[122].d),
9790
9791 // to internal hardware
9792 .qe (),
9793 .q (),
9794 .ds (),
9795
9796 // to register interface (read)
9797 .qs (ip_3_p_122_qs)
9798 );
9799
9800 // F[p_123]: 27:27
9801 prim_subreg #(
9802 .DW (1),
9803 .SwAccess(prim_subreg_pkg::SwAccessRO),
9804 .RESVAL (1'h0),
9805 .Mubi (1'b0)
9806 ) u_ip_3_p_123 (
9807 .clk_i (clk_i),
9808 .rst_ni (rst_ni),
9809
9810 // from register interface
9811 .we (1'b0),
9812 .wd ('0),
9813
9814 // from internal hardware
9815 .de (hw2reg.ip[123].de),
9816 .d (hw2reg.ip[123].d),
9817
9818 // to internal hardware
9819 .qe (),
9820 .q (),
9821 .ds (),
9822
9823 // to register interface (read)
9824 .qs (ip_3_p_123_qs)
9825 );
9826
9827 // F[p_124]: 28:28
9828 prim_subreg #(
9829 .DW (1),
9830 .SwAccess(prim_subreg_pkg::SwAccessRO),
9831 .RESVAL (1'h0),
9832 .Mubi (1'b0)
9833 ) u_ip_3_p_124 (
9834 .clk_i (clk_i),
9835 .rst_ni (rst_ni),
9836
9837 // from register interface
9838 .we (1'b0),
9839 .wd ('0),
9840
9841 // from internal hardware
9842 .de (hw2reg.ip[124].de),
9843 .d (hw2reg.ip[124].d),
9844
9845 // to internal hardware
9846 .qe (),
9847 .q (),
9848 .ds (),
9849
9850 // to register interface (read)
9851 .qs (ip_3_p_124_qs)
9852 );
9853
9854 // F[p_125]: 29:29
9855 prim_subreg #(
9856 .DW (1),
9857 .SwAccess(prim_subreg_pkg::SwAccessRO),
9858 .RESVAL (1'h0),
9859 .Mubi (1'b0)
9860 ) u_ip_3_p_125 (
9861 .clk_i (clk_i),
9862 .rst_ni (rst_ni),
9863
9864 // from register interface
9865 .we (1'b0),
9866 .wd ('0),
9867
9868 // from internal hardware
9869 .de (hw2reg.ip[125].de),
9870 .d (hw2reg.ip[125].d),
9871
9872 // to internal hardware
9873 .qe (),
9874 .q (),
9875 .ds (),
9876
9877 // to register interface (read)
9878 .qs (ip_3_p_125_qs)
9879 );
9880
9881 // F[p_126]: 30:30
9882 prim_subreg #(
9883 .DW (1),
9884 .SwAccess(prim_subreg_pkg::SwAccessRO),
9885 .RESVAL (1'h0),
9886 .Mubi (1'b0)
9887 ) u_ip_3_p_126 (
9888 .clk_i (clk_i),
9889 .rst_ni (rst_ni),
9890
9891 // from register interface
9892 .we (1'b0),
9893 .wd ('0),
9894
9895 // from internal hardware
9896 .de (hw2reg.ip[126].de),
9897 .d (hw2reg.ip[126].d),
9898
9899 // to internal hardware
9900 .qe (),
9901 .q (),
9902 .ds (),
9903
9904 // to register interface (read)
9905 .qs (ip_3_p_126_qs)
9906 );
9907
9908 // F[p_127]: 31:31
9909 prim_subreg #(
9910 .DW (1),
9911 .SwAccess(prim_subreg_pkg::SwAccessRO),
9912 .RESVAL (1'h0),
9913 .Mubi (1'b0)
9914 ) u_ip_3_p_127 (
9915 .clk_i (clk_i),
9916 .rst_ni (rst_ni),
9917
9918 // from register interface
9919 .we (1'b0),
9920 .wd ('0),
9921
9922 // from internal hardware
9923 .de (hw2reg.ip[127].de),
9924 .d (hw2reg.ip[127].d),
9925
9926 // to internal hardware
9927 .qe (),
9928 .q (),
9929 .ds (),
9930
9931 // to register interface (read)
9932 .qs (ip_3_p_127_qs)
9933 );
9934
9935
9936 // Subregister 4 of Multireg ip
9937 // R[ip_4]: V(False)
9938 // F[p_128]: 0:0
9939 prim_subreg #(
9940 .DW (1),
9941 .SwAccess(prim_subreg_pkg::SwAccessRO),
9942 .RESVAL (1'h0),
9943 .Mubi (1'b0)
9944 ) u_ip_4_p_128 (
9945 .clk_i (clk_i),
9946 .rst_ni (rst_ni),
9947
9948 // from register interface
9949 .we (1'b0),
9950 .wd ('0),
9951
9952 // from internal hardware
9953 .de (hw2reg.ip[128].de),
9954 .d (hw2reg.ip[128].d),
9955
9956 // to internal hardware
9957 .qe (),
9958 .q (),
9959 .ds (),
9960
9961 // to register interface (read)
9962 .qs (ip_4_p_128_qs)
9963 );
9964
9965 // F[p_129]: 1:1
9966 prim_subreg #(
9967 .DW (1),
9968 .SwAccess(prim_subreg_pkg::SwAccessRO),
9969 .RESVAL (1'h0),
9970 .Mubi (1'b0)
9971 ) u_ip_4_p_129 (
9972 .clk_i (clk_i),
9973 .rst_ni (rst_ni),
9974
9975 // from register interface
9976 .we (1'b0),
9977 .wd ('0),
9978
9979 // from internal hardware
9980 .de (hw2reg.ip[129].de),
9981 .d (hw2reg.ip[129].d),
9982
9983 // to internal hardware
9984 .qe (),
9985 .q (),
9986 .ds (),
9987
9988 // to register interface (read)
9989 .qs (ip_4_p_129_qs)
9990 );
9991
9992 // F[p_130]: 2:2
9993 prim_subreg #(
9994 .DW (1),
9995 .SwAccess(prim_subreg_pkg::SwAccessRO),
9996 .RESVAL (1'h0),
9997 .Mubi (1'b0)
9998 ) u_ip_4_p_130 (
9999 .clk_i (clk_i),
10000 .rst_ni (rst_ni),
10001
10002 // from register interface
10003 .we (1'b0),
10004 .wd ('0),
10005
10006 // from internal hardware
10007 .de (hw2reg.ip[130].de),
10008 .d (hw2reg.ip[130].d),
10009
10010 // to internal hardware
10011 .qe (),
10012 .q (),
10013 .ds (),
10014
10015 // to register interface (read)
10016 .qs (ip_4_p_130_qs)
10017 );
10018
10019 // F[p_131]: 3:3
10020 prim_subreg #(
10021 .DW (1),
10022 .SwAccess(prim_subreg_pkg::SwAccessRO),
10023 .RESVAL (1'h0),
10024 .Mubi (1'b0)
10025 ) u_ip_4_p_131 (
10026 .clk_i (clk_i),
10027 .rst_ni (rst_ni),
10028
10029 // from register interface
10030 .we (1'b0),
10031 .wd ('0),
10032
10033 // from internal hardware
10034 .de (hw2reg.ip[131].de),
10035 .d (hw2reg.ip[131].d),
10036
10037 // to internal hardware
10038 .qe (),
10039 .q (),
10040 .ds (),
10041
10042 // to register interface (read)
10043 .qs (ip_4_p_131_qs)
10044 );
10045
10046 // F[p_132]: 4:4
10047 prim_subreg #(
10048 .DW (1),
10049 .SwAccess(prim_subreg_pkg::SwAccessRO),
10050 .RESVAL (1'h0),
10051 .Mubi (1'b0)
10052 ) u_ip_4_p_132 (
10053 .clk_i (clk_i),
10054 .rst_ni (rst_ni),
10055
10056 // from register interface
10057 .we (1'b0),
10058 .wd ('0),
10059
10060 // from internal hardware
10061 .de (hw2reg.ip[132].de),
10062 .d (hw2reg.ip[132].d),
10063
10064 // to internal hardware
10065 .qe (),
10066 .q (),
10067 .ds (),
10068
10069 // to register interface (read)
10070 .qs (ip_4_p_132_qs)
10071 );
10072
10073 // F[p_133]: 5:5
10074 prim_subreg #(
10075 .DW (1),
10076 .SwAccess(prim_subreg_pkg::SwAccessRO),
10077 .RESVAL (1'h0),
10078 .Mubi (1'b0)
10079 ) u_ip_4_p_133 (
10080 .clk_i (clk_i),
10081 .rst_ni (rst_ni),
10082
10083 // from register interface
10084 .we (1'b0),
10085 .wd ('0),
10086
10087 // from internal hardware
10088 .de (hw2reg.ip[133].de),
10089 .d (hw2reg.ip[133].d),
10090
10091 // to internal hardware
10092 .qe (),
10093 .q (),
10094 .ds (),
10095
10096 // to register interface (read)
10097 .qs (ip_4_p_133_qs)
10098 );
10099
10100 // F[p_134]: 6:6
10101 prim_subreg #(
10102 .DW (1),
10103 .SwAccess(prim_subreg_pkg::SwAccessRO),
10104 .RESVAL (1'h0),
10105 .Mubi (1'b0)
10106 ) u_ip_4_p_134 (
10107 .clk_i (clk_i),
10108 .rst_ni (rst_ni),
10109
10110 // from register interface
10111 .we (1'b0),
10112 .wd ('0),
10113
10114 // from internal hardware
10115 .de (hw2reg.ip[134].de),
10116 .d (hw2reg.ip[134].d),
10117
10118 // to internal hardware
10119 .qe (),
10120 .q (),
10121 .ds (),
10122
10123 // to register interface (read)
10124 .qs (ip_4_p_134_qs)
10125 );
10126
10127 // F[p_135]: 7:7
10128 prim_subreg #(
10129 .DW (1),
10130 .SwAccess(prim_subreg_pkg::SwAccessRO),
10131 .RESVAL (1'h0),
10132 .Mubi (1'b0)
10133 ) u_ip_4_p_135 (
10134 .clk_i (clk_i),
10135 .rst_ni (rst_ni),
10136
10137 // from register interface
10138 .we (1'b0),
10139 .wd ('0),
10140
10141 // from internal hardware
10142 .de (hw2reg.ip[135].de),
10143 .d (hw2reg.ip[135].d),
10144
10145 // to internal hardware
10146 .qe (),
10147 .q (),
10148 .ds (),
10149
10150 // to register interface (read)
10151 .qs (ip_4_p_135_qs)
10152 );
10153
10154 // F[p_136]: 8:8
10155 prim_subreg #(
10156 .DW (1),
10157 .SwAccess(prim_subreg_pkg::SwAccessRO),
10158 .RESVAL (1'h0),
10159 .Mubi (1'b0)
10160 ) u_ip_4_p_136 (
10161 .clk_i (clk_i),
10162 .rst_ni (rst_ni),
10163
10164 // from register interface
10165 .we (1'b0),
10166 .wd ('0),
10167
10168 // from internal hardware
10169 .de (hw2reg.ip[136].de),
10170 .d (hw2reg.ip[136].d),
10171
10172 // to internal hardware
10173 .qe (),
10174 .q (),
10175 .ds (),
10176
10177 // to register interface (read)
10178 .qs (ip_4_p_136_qs)
10179 );
10180
10181 // F[p_137]: 9:9
10182 prim_subreg #(
10183 .DW (1),
10184 .SwAccess(prim_subreg_pkg::SwAccessRO),
10185 .RESVAL (1'h0),
10186 .Mubi (1'b0)
10187 ) u_ip_4_p_137 (
10188 .clk_i (clk_i),
10189 .rst_ni (rst_ni),
10190
10191 // from register interface
10192 .we (1'b0),
10193 .wd ('0),
10194
10195 // from internal hardware
10196 .de (hw2reg.ip[137].de),
10197 .d (hw2reg.ip[137].d),
10198
10199 // to internal hardware
10200 .qe (),
10201 .q (),
10202 .ds (),
10203
10204 // to register interface (read)
10205 .qs (ip_4_p_137_qs)
10206 );
10207
10208 // F[p_138]: 10:10
10209 prim_subreg #(
10210 .DW (1),
10211 .SwAccess(prim_subreg_pkg::SwAccessRO),
10212 .RESVAL (1'h0),
10213 .Mubi (1'b0)
10214 ) u_ip_4_p_138 (
10215 .clk_i (clk_i),
10216 .rst_ni (rst_ni),
10217
10218 // from register interface
10219 .we (1'b0),
10220 .wd ('0),
10221
10222 // from internal hardware
10223 .de (hw2reg.ip[138].de),
10224 .d (hw2reg.ip[138].d),
10225
10226 // to internal hardware
10227 .qe (),
10228 .q (),
10229 .ds (),
10230
10231 // to register interface (read)
10232 .qs (ip_4_p_138_qs)
10233 );
10234
10235 // F[p_139]: 11:11
10236 prim_subreg #(
10237 .DW (1),
10238 .SwAccess(prim_subreg_pkg::SwAccessRO),
10239 .RESVAL (1'h0),
10240 .Mubi (1'b0)
10241 ) u_ip_4_p_139 (
10242 .clk_i (clk_i),
10243 .rst_ni (rst_ni),
10244
10245 // from register interface
10246 .we (1'b0),
10247 .wd ('0),
10248
10249 // from internal hardware
10250 .de (hw2reg.ip[139].de),
10251 .d (hw2reg.ip[139].d),
10252
10253 // to internal hardware
10254 .qe (),
10255 .q (),
10256 .ds (),
10257
10258 // to register interface (read)
10259 .qs (ip_4_p_139_qs)
10260 );
10261
10262 // F[p_140]: 12:12
10263 prim_subreg #(
10264 .DW (1),
10265 .SwAccess(prim_subreg_pkg::SwAccessRO),
10266 .RESVAL (1'h0),
10267 .Mubi (1'b0)
10268 ) u_ip_4_p_140 (
10269 .clk_i (clk_i),
10270 .rst_ni (rst_ni),
10271
10272 // from register interface
10273 .we (1'b0),
10274 .wd ('0),
10275
10276 // from internal hardware
10277 .de (hw2reg.ip[140].de),
10278 .d (hw2reg.ip[140].d),
10279
10280 // to internal hardware
10281 .qe (),
10282 .q (),
10283 .ds (),
10284
10285 // to register interface (read)
10286 .qs (ip_4_p_140_qs)
10287 );
10288
10289 // F[p_141]: 13:13
10290 prim_subreg #(
10291 .DW (1),
10292 .SwAccess(prim_subreg_pkg::SwAccessRO),
10293 .RESVAL (1'h0),
10294 .Mubi (1'b0)
10295 ) u_ip_4_p_141 (
10296 .clk_i (clk_i),
10297 .rst_ni (rst_ni),
10298
10299 // from register interface
10300 .we (1'b0),
10301 .wd ('0),
10302
10303 // from internal hardware
10304 .de (hw2reg.ip[141].de),
10305 .d (hw2reg.ip[141].d),
10306
10307 // to internal hardware
10308 .qe (),
10309 .q (),
10310 .ds (),
10311
10312 // to register interface (read)
10313 .qs (ip_4_p_141_qs)
10314 );
10315
10316 // F[p_142]: 14:14
10317 prim_subreg #(
10318 .DW (1),
10319 .SwAccess(prim_subreg_pkg::SwAccessRO),
10320 .RESVAL (1'h0),
10321 .Mubi (1'b0)
10322 ) u_ip_4_p_142 (
10323 .clk_i (clk_i),
10324 .rst_ni (rst_ni),
10325
10326 // from register interface
10327 .we (1'b0),
10328 .wd ('0),
10329
10330 // from internal hardware
10331 .de (hw2reg.ip[142].de),
10332 .d (hw2reg.ip[142].d),
10333
10334 // to internal hardware
10335 .qe (),
10336 .q (),
10337 .ds (),
10338
10339 // to register interface (read)
10340 .qs (ip_4_p_142_qs)
10341 );
10342
10343 // F[p_143]: 15:15
10344 prim_subreg #(
10345 .DW (1),
10346 .SwAccess(prim_subreg_pkg::SwAccessRO),
10347 .RESVAL (1'h0),
10348 .Mubi (1'b0)
10349 ) u_ip_4_p_143 (
10350 .clk_i (clk_i),
10351 .rst_ni (rst_ni),
10352
10353 // from register interface
10354 .we (1'b0),
10355 .wd ('0),
10356
10357 // from internal hardware
10358 .de (hw2reg.ip[143].de),
10359 .d (hw2reg.ip[143].d),
10360
10361 // to internal hardware
10362 .qe (),
10363 .q (),
10364 .ds (),
10365
10366 // to register interface (read)
10367 .qs (ip_4_p_143_qs)
10368 );
10369
10370 // F[p_144]: 16:16
10371 prim_subreg #(
10372 .DW (1),
10373 .SwAccess(prim_subreg_pkg::SwAccessRO),
10374 .RESVAL (1'h0),
10375 .Mubi (1'b0)
10376 ) u_ip_4_p_144 (
10377 .clk_i (clk_i),
10378 .rst_ni (rst_ni),
10379
10380 // from register interface
10381 .we (1'b0),
10382 .wd ('0),
10383
10384 // from internal hardware
10385 .de (hw2reg.ip[144].de),
10386 .d (hw2reg.ip[144].d),
10387
10388 // to internal hardware
10389 .qe (),
10390 .q (),
10391 .ds (),
10392
10393 // to register interface (read)
10394 .qs (ip_4_p_144_qs)
10395 );
10396
10397 // F[p_145]: 17:17
10398 prim_subreg #(
10399 .DW (1),
10400 .SwAccess(prim_subreg_pkg::SwAccessRO),
10401 .RESVAL (1'h0),
10402 .Mubi (1'b0)
10403 ) u_ip_4_p_145 (
10404 .clk_i (clk_i),
10405 .rst_ni (rst_ni),
10406
10407 // from register interface
10408 .we (1'b0),
10409 .wd ('0),
10410
10411 // from internal hardware
10412 .de (hw2reg.ip[145].de),
10413 .d (hw2reg.ip[145].d),
10414
10415 // to internal hardware
10416 .qe (),
10417 .q (),
10418 .ds (),
10419
10420 // to register interface (read)
10421 .qs (ip_4_p_145_qs)
10422 );
10423
10424 // F[p_146]: 18:18
10425 prim_subreg #(
10426 .DW (1),
10427 .SwAccess(prim_subreg_pkg::SwAccessRO),
10428 .RESVAL (1'h0),
10429 .Mubi (1'b0)
10430 ) u_ip_4_p_146 (
10431 .clk_i (clk_i),
10432 .rst_ni (rst_ni),
10433
10434 // from register interface
10435 .we (1'b0),
10436 .wd ('0),
10437
10438 // from internal hardware
10439 .de (hw2reg.ip[146].de),
10440 .d (hw2reg.ip[146].d),
10441
10442 // to internal hardware
10443 .qe (),
10444 .q (),
10445 .ds (),
10446
10447 // to register interface (read)
10448 .qs (ip_4_p_146_qs)
10449 );
10450
10451 // F[p_147]: 19:19
10452 prim_subreg #(
10453 .DW (1),
10454 .SwAccess(prim_subreg_pkg::SwAccessRO),
10455 .RESVAL (1'h0),
10456 .Mubi (1'b0)
10457 ) u_ip_4_p_147 (
10458 .clk_i (clk_i),
10459 .rst_ni (rst_ni),
10460
10461 // from register interface
10462 .we (1'b0),
10463 .wd ('0),
10464
10465 // from internal hardware
10466 .de (hw2reg.ip[147].de),
10467 .d (hw2reg.ip[147].d),
10468
10469 // to internal hardware
10470 .qe (),
10471 .q (),
10472 .ds (),
10473
10474 // to register interface (read)
10475 .qs (ip_4_p_147_qs)
10476 );
10477
10478 // F[p_148]: 20:20
10479 prim_subreg #(
10480 .DW (1),
10481 .SwAccess(prim_subreg_pkg::SwAccessRO),
10482 .RESVAL (1'h0),
10483 .Mubi (1'b0)
10484 ) u_ip_4_p_148 (
10485 .clk_i (clk_i),
10486 .rst_ni (rst_ni),
10487
10488 // from register interface
10489 .we (1'b0),
10490 .wd ('0),
10491
10492 // from internal hardware
10493 .de (hw2reg.ip[148].de),
10494 .d (hw2reg.ip[148].d),
10495
10496 // to internal hardware
10497 .qe (),
10498 .q (),
10499 .ds (),
10500
10501 // to register interface (read)
10502 .qs (ip_4_p_148_qs)
10503 );
10504
10505 // F[p_149]: 21:21
10506 prim_subreg #(
10507 .DW (1),
10508 .SwAccess(prim_subreg_pkg::SwAccessRO),
10509 .RESVAL (1'h0),
10510 .Mubi (1'b0)
10511 ) u_ip_4_p_149 (
10512 .clk_i (clk_i),
10513 .rst_ni (rst_ni),
10514
10515 // from register interface
10516 .we (1'b0),
10517 .wd ('0),
10518
10519 // from internal hardware
10520 .de (hw2reg.ip[149].de),
10521 .d (hw2reg.ip[149].d),
10522
10523 // to internal hardware
10524 .qe (),
10525 .q (),
10526 .ds (),
10527
10528 // to register interface (read)
10529 .qs (ip_4_p_149_qs)
10530 );
10531
10532 // F[p_150]: 22:22
10533 prim_subreg #(
10534 .DW (1),
10535 .SwAccess(prim_subreg_pkg::SwAccessRO),
10536 .RESVAL (1'h0),
10537 .Mubi (1'b0)
10538 ) u_ip_4_p_150 (
10539 .clk_i (clk_i),
10540 .rst_ni (rst_ni),
10541
10542 // from register interface
10543 .we (1'b0),
10544 .wd ('0),
10545
10546 // from internal hardware
10547 .de (hw2reg.ip[150].de),
10548 .d (hw2reg.ip[150].d),
10549
10550 // to internal hardware
10551 .qe (),
10552 .q (),
10553 .ds (),
10554
10555 // to register interface (read)
10556 .qs (ip_4_p_150_qs)
10557 );
10558
10559 // F[p_151]: 23:23
10560 prim_subreg #(
10561 .DW (1),
10562 .SwAccess(prim_subreg_pkg::SwAccessRO),
10563 .RESVAL (1'h0),
10564 .Mubi (1'b0)
10565 ) u_ip_4_p_151 (
10566 .clk_i (clk_i),
10567 .rst_ni (rst_ni),
10568
10569 // from register interface
10570 .we (1'b0),
10571 .wd ('0),
10572
10573 // from internal hardware
10574 .de (hw2reg.ip[151].de),
10575 .d (hw2reg.ip[151].d),
10576
10577 // to internal hardware
10578 .qe (),
10579 .q (),
10580 .ds (),
10581
10582 // to register interface (read)
10583 .qs (ip_4_p_151_qs)
10584 );
10585
10586 // F[p_152]: 24:24
10587 prim_subreg #(
10588 .DW (1),
10589 .SwAccess(prim_subreg_pkg::SwAccessRO),
10590 .RESVAL (1'h0),
10591 .Mubi (1'b0)
10592 ) u_ip_4_p_152 (
10593 .clk_i (clk_i),
10594 .rst_ni (rst_ni),
10595
10596 // from register interface
10597 .we (1'b0),
10598 .wd ('0),
10599
10600 // from internal hardware
10601 .de (hw2reg.ip[152].de),
10602 .d (hw2reg.ip[152].d),
10603
10604 // to internal hardware
10605 .qe (),
10606 .q (),
10607 .ds (),
10608
10609 // to register interface (read)
10610 .qs (ip_4_p_152_qs)
10611 );
10612
10613 // F[p_153]: 25:25
10614 prim_subreg #(
10615 .DW (1),
10616 .SwAccess(prim_subreg_pkg::SwAccessRO),
10617 .RESVAL (1'h0),
10618 .Mubi (1'b0)
10619 ) u_ip_4_p_153 (
10620 .clk_i (clk_i),
10621 .rst_ni (rst_ni),
10622
10623 // from register interface
10624 .we (1'b0),
10625 .wd ('0),
10626
10627 // from internal hardware
10628 .de (hw2reg.ip[153].de),
10629 .d (hw2reg.ip[153].d),
10630
10631 // to internal hardware
10632 .qe (),
10633 .q (),
10634 .ds (),
10635
10636 // to register interface (read)
10637 .qs (ip_4_p_153_qs)
10638 );
10639
10640 // F[p_154]: 26:26
10641 prim_subreg #(
10642 .DW (1),
10643 .SwAccess(prim_subreg_pkg::SwAccessRO),
10644 .RESVAL (1'h0),
10645 .Mubi (1'b0)
10646 ) u_ip_4_p_154 (
10647 .clk_i (clk_i),
10648 .rst_ni (rst_ni),
10649
10650 // from register interface
10651 .we (1'b0),
10652 .wd ('0),
10653
10654 // from internal hardware
10655 .de (hw2reg.ip[154].de),
10656 .d (hw2reg.ip[154].d),
10657
10658 // to internal hardware
10659 .qe (),
10660 .q (),
10661 .ds (),
10662
10663 // to register interface (read)
10664 .qs (ip_4_p_154_qs)
10665 );
10666
10667 // F[p_155]: 27:27
10668 prim_subreg #(
10669 .DW (1),
10670 .SwAccess(prim_subreg_pkg::SwAccessRO),
10671 .RESVAL (1'h0),
10672 .Mubi (1'b0)
10673 ) u_ip_4_p_155 (
10674 .clk_i (clk_i),
10675 .rst_ni (rst_ni),
10676
10677 // from register interface
10678 .we (1'b0),
10679 .wd ('0),
10680
10681 // from internal hardware
10682 .de (hw2reg.ip[155].de),
10683 .d (hw2reg.ip[155].d),
10684
10685 // to internal hardware
10686 .qe (),
10687 .q (),
10688 .ds (),
10689
10690 // to register interface (read)
10691 .qs (ip_4_p_155_qs)
10692 );
10693
10694 // F[p_156]: 28:28
10695 prim_subreg #(
10696 .DW (1),
10697 .SwAccess(prim_subreg_pkg::SwAccessRO),
10698 .RESVAL (1'h0),
10699 .Mubi (1'b0)
10700 ) u_ip_4_p_156 (
10701 .clk_i (clk_i),
10702 .rst_ni (rst_ni),
10703
10704 // from register interface
10705 .we (1'b0),
10706 .wd ('0),
10707
10708 // from internal hardware
10709 .de (hw2reg.ip[156].de),
10710 .d (hw2reg.ip[156].d),
10711
10712 // to internal hardware
10713 .qe (),
10714 .q (),
10715 .ds (),
10716
10717 // to register interface (read)
10718 .qs (ip_4_p_156_qs)
10719 );
10720
10721 // F[p_157]: 29:29
10722 prim_subreg #(
10723 .DW (1),
10724 .SwAccess(prim_subreg_pkg::SwAccessRO),
10725 .RESVAL (1'h0),
10726 .Mubi (1'b0)
10727 ) u_ip_4_p_157 (
10728 .clk_i (clk_i),
10729 .rst_ni (rst_ni),
10730
10731 // from register interface
10732 .we (1'b0),
10733 .wd ('0),
10734
10735 // from internal hardware
10736 .de (hw2reg.ip[157].de),
10737 .d (hw2reg.ip[157].d),
10738
10739 // to internal hardware
10740 .qe (),
10741 .q (),
10742 .ds (),
10743
10744 // to register interface (read)
10745 .qs (ip_4_p_157_qs)
10746 );
10747
10748 // F[p_158]: 30:30
10749 prim_subreg #(
10750 .DW (1),
10751 .SwAccess(prim_subreg_pkg::SwAccessRO),
10752 .RESVAL (1'h0),
10753 .Mubi (1'b0)
10754 ) u_ip_4_p_158 (
10755 .clk_i (clk_i),
10756 .rst_ni (rst_ni),
10757
10758 // from register interface
10759 .we (1'b0),
10760 .wd ('0),
10761
10762 // from internal hardware
10763 .de (hw2reg.ip[158].de),
10764 .d (hw2reg.ip[158].d),
10765
10766 // to internal hardware
10767 .qe (),
10768 .q (),
10769 .ds (),
10770
10771 // to register interface (read)
10772 .qs (ip_4_p_158_qs)
10773 );
10774
10775 // F[p_159]: 31:31
10776 prim_subreg #(
10777 .DW (1),
10778 .SwAccess(prim_subreg_pkg::SwAccessRO),
10779 .RESVAL (1'h0),
10780 .Mubi (1'b0)
10781 ) u_ip_4_p_159 (
10782 .clk_i (clk_i),
10783 .rst_ni (rst_ni),
10784
10785 // from register interface
10786 .we (1'b0),
10787 .wd ('0),
10788
10789 // from internal hardware
10790 .de (hw2reg.ip[159].de),
10791 .d (hw2reg.ip[159].d),
10792
10793 // to internal hardware
10794 .qe (),
10795 .q (),
10796 .ds (),
10797
10798 // to register interface (read)
10799 .qs (ip_4_p_159_qs)
10800 );
10801
10802
10803 // Subregister 5 of Multireg ip
10804 // R[ip_5]: V(False)
10805 // F[p_160]: 0:0
10806 prim_subreg #(
10807 .DW (1),
10808 .SwAccess(prim_subreg_pkg::SwAccessRO),
10809 .RESVAL (1'h0),
10810 .Mubi (1'b0)
10811 ) u_ip_5_p_160 (
10812 .clk_i (clk_i),
10813 .rst_ni (rst_ni),
10814
10815 // from register interface
10816 .we (1'b0),
10817 .wd ('0),
10818
10819 // from internal hardware
10820 .de (hw2reg.ip[160].de),
10821 .d (hw2reg.ip[160].d),
10822
10823 // to internal hardware
10824 .qe (),
10825 .q (),
10826 .ds (),
10827
10828 // to register interface (read)
10829 .qs (ip_5_p_160_qs)
10830 );
10831
10832 // F[p_161]: 1:1
10833 prim_subreg #(
10834 .DW (1),
10835 .SwAccess(prim_subreg_pkg::SwAccessRO),
10836 .RESVAL (1'h0),
10837 .Mubi (1'b0)
10838 ) u_ip_5_p_161 (
10839 .clk_i (clk_i),
10840 .rst_ni (rst_ni),
10841
10842 // from register interface
10843 .we (1'b0),
10844 .wd ('0),
10845
10846 // from internal hardware
10847 .de (hw2reg.ip[161].de),
10848 .d (hw2reg.ip[161].d),
10849
10850 // to internal hardware
10851 .qe (),
10852 .q (),
10853 .ds (),
10854
10855 // to register interface (read)
10856 .qs (ip_5_p_161_qs)
10857 );
10858
10859 // F[p_162]: 2:2
10860 prim_subreg #(
10861 .DW (1),
10862 .SwAccess(prim_subreg_pkg::SwAccessRO),
10863 .RESVAL (1'h0),
10864 .Mubi (1'b0)
10865 ) u_ip_5_p_162 (
10866 .clk_i (clk_i),
10867 .rst_ni (rst_ni),
10868
10869 // from register interface
10870 .we (1'b0),
10871 .wd ('0),
10872
10873 // from internal hardware
10874 .de (hw2reg.ip[162].de),
10875 .d (hw2reg.ip[162].d),
10876
10877 // to internal hardware
10878 .qe (),
10879 .q (),
10880 .ds (),
10881
10882 // to register interface (read)
10883 .qs (ip_5_p_162_qs)
10884 );
10885
10886 // F[p_163]: 3:3
10887 prim_subreg #(
10888 .DW (1),
10889 .SwAccess(prim_subreg_pkg::SwAccessRO),
10890 .RESVAL (1'h0),
10891 .Mubi (1'b0)
10892 ) u_ip_5_p_163 (
10893 .clk_i (clk_i),
10894 .rst_ni (rst_ni),
10895
10896 // from register interface
10897 .we (1'b0),
10898 .wd ('0),
10899
10900 // from internal hardware
10901 .de (hw2reg.ip[163].de),
10902 .d (hw2reg.ip[163].d),
10903
10904 // to internal hardware
10905 .qe (),
10906 .q (),
10907 .ds (),
10908
10909 // to register interface (read)
10910 .qs (ip_5_p_163_qs)
10911 );
10912
10913 // F[p_164]: 4:4
10914 prim_subreg #(
10915 .DW (1),
10916 .SwAccess(prim_subreg_pkg::SwAccessRO),
10917 .RESVAL (1'h0),
10918 .Mubi (1'b0)
10919 ) u_ip_5_p_164 (
10920 .clk_i (clk_i),
10921 .rst_ni (rst_ni),
10922
10923 // from register interface
10924 .we (1'b0),
10925 .wd ('0),
10926
10927 // from internal hardware
10928 .de (hw2reg.ip[164].de),
10929 .d (hw2reg.ip[164].d),
10930
10931 // to internal hardware
10932 .qe (),
10933 .q (),
10934 .ds (),
10935
10936 // to register interface (read)
10937 .qs (ip_5_p_164_qs)
10938 );
10939
10940 // F[p_165]: 5:5
10941 prim_subreg #(
10942 .DW (1),
10943 .SwAccess(prim_subreg_pkg::SwAccessRO),
10944 .RESVAL (1'h0),
10945 .Mubi (1'b0)
10946 ) u_ip_5_p_165 (
10947 .clk_i (clk_i),
10948 .rst_ni (rst_ni),
10949
10950 // from register interface
10951 .we (1'b0),
10952 .wd ('0),
10953
10954 // from internal hardware
10955 .de (hw2reg.ip[165].de),
10956 .d (hw2reg.ip[165].d),
10957
10958 // to internal hardware
10959 .qe (),
10960 .q (),
10961 .ds (),
10962
10963 // to register interface (read)
10964 .qs (ip_5_p_165_qs)
10965 );
10966
10967 // F[p_166]: 6:6
10968 prim_subreg #(
10969 .DW (1),
10970 .SwAccess(prim_subreg_pkg::SwAccessRO),
10971 .RESVAL (1'h0),
10972 .Mubi (1'b0)
10973 ) u_ip_5_p_166 (
10974 .clk_i (clk_i),
10975 .rst_ni (rst_ni),
10976
10977 // from register interface
10978 .we (1'b0),
10979 .wd ('0),
10980
10981 // from internal hardware
10982 .de (hw2reg.ip[166].de),
10983 .d (hw2reg.ip[166].d),
10984
10985 // to internal hardware
10986 .qe (),
10987 .q (),
10988 .ds (),
10989
10990 // to register interface (read)
10991 .qs (ip_5_p_166_qs)
10992 );
10993
10994 // F[p_167]: 7:7
10995 prim_subreg #(
10996 .DW (1),
10997 .SwAccess(prim_subreg_pkg::SwAccessRO),
10998 .RESVAL (1'h0),
10999 .Mubi (1'b0)
11000 ) u_ip_5_p_167 (
11001 .clk_i (clk_i),
11002 .rst_ni (rst_ni),
11003
11004 // from register interface
11005 .we (1'b0),
11006 .wd ('0),
11007
11008 // from internal hardware
11009 .de (hw2reg.ip[167].de),
11010 .d (hw2reg.ip[167].d),
11011
11012 // to internal hardware
11013 .qe (),
11014 .q (),
11015 .ds (),
11016
11017 // to register interface (read)
11018 .qs (ip_5_p_167_qs)
11019 );
11020
11021 // F[p_168]: 8:8
11022 prim_subreg #(
11023 .DW (1),
11024 .SwAccess(prim_subreg_pkg::SwAccessRO),
11025 .RESVAL (1'h0),
11026 .Mubi (1'b0)
11027 ) u_ip_5_p_168 (
11028 .clk_i (clk_i),
11029 .rst_ni (rst_ni),
11030
11031 // from register interface
11032 .we (1'b0),
11033 .wd ('0),
11034
11035 // from internal hardware
11036 .de (hw2reg.ip[168].de),
11037 .d (hw2reg.ip[168].d),
11038
11039 // to internal hardware
11040 .qe (),
11041 .q (),
11042 .ds (),
11043
11044 // to register interface (read)
11045 .qs (ip_5_p_168_qs)
11046 );
11047
11048 // F[p_169]: 9:9
11049 prim_subreg #(
11050 .DW (1),
11051 .SwAccess(prim_subreg_pkg::SwAccessRO),
11052 .RESVAL (1'h0),
11053 .Mubi (1'b0)
11054 ) u_ip_5_p_169 (
11055 .clk_i (clk_i),
11056 .rst_ni (rst_ni),
11057
11058 // from register interface
11059 .we (1'b0),
11060 .wd ('0),
11061
11062 // from internal hardware
11063 .de (hw2reg.ip[169].de),
11064 .d (hw2reg.ip[169].d),
11065
11066 // to internal hardware
11067 .qe (),
11068 .q (),
11069 .ds (),
11070
11071 // to register interface (read)
11072 .qs (ip_5_p_169_qs)
11073 );
11074
11075 // F[p_170]: 10:10
11076 prim_subreg #(
11077 .DW (1),
11078 .SwAccess(prim_subreg_pkg::SwAccessRO),
11079 .RESVAL (1'h0),
11080 .Mubi (1'b0)
11081 ) u_ip_5_p_170 (
11082 .clk_i (clk_i),
11083 .rst_ni (rst_ni),
11084
11085 // from register interface
11086 .we (1'b0),
11087 .wd ('0),
11088
11089 // from internal hardware
11090 .de (hw2reg.ip[170].de),
11091 .d (hw2reg.ip[170].d),
11092
11093 // to internal hardware
11094 .qe (),
11095 .q (),
11096 .ds (),
11097
11098 // to register interface (read)
11099 .qs (ip_5_p_170_qs)
11100 );
11101
11102 // F[p_171]: 11:11
11103 prim_subreg #(
11104 .DW (1),
11105 .SwAccess(prim_subreg_pkg::SwAccessRO),
11106 .RESVAL (1'h0),
11107 .Mubi (1'b0)
11108 ) u_ip_5_p_171 (
11109 .clk_i (clk_i),
11110 .rst_ni (rst_ni),
11111
11112 // from register interface
11113 .we (1'b0),
11114 .wd ('0),
11115
11116 // from internal hardware
11117 .de (hw2reg.ip[171].de),
11118 .d (hw2reg.ip[171].d),
11119
11120 // to internal hardware
11121 .qe (),
11122 .q (),
11123 .ds (),
11124
11125 // to register interface (read)
11126 .qs (ip_5_p_171_qs)
11127 );
11128
11129 // F[p_172]: 12:12
11130 prim_subreg #(
11131 .DW (1),
11132 .SwAccess(prim_subreg_pkg::SwAccessRO),
11133 .RESVAL (1'h0),
11134 .Mubi (1'b0)
11135 ) u_ip_5_p_172 (
11136 .clk_i (clk_i),
11137 .rst_ni (rst_ni),
11138
11139 // from register interface
11140 .we (1'b0),
11141 .wd ('0),
11142
11143 // from internal hardware
11144 .de (hw2reg.ip[172].de),
11145 .d (hw2reg.ip[172].d),
11146
11147 // to internal hardware
11148 .qe (),
11149 .q (),
11150 .ds (),
11151
11152 // to register interface (read)
11153 .qs (ip_5_p_172_qs)
11154 );
11155
11156 // F[p_173]: 13:13
11157 prim_subreg #(
11158 .DW (1),
11159 .SwAccess(prim_subreg_pkg::SwAccessRO),
11160 .RESVAL (1'h0),
11161 .Mubi (1'b0)
11162 ) u_ip_5_p_173 (
11163 .clk_i (clk_i),
11164 .rst_ni (rst_ni),
11165
11166 // from register interface
11167 .we (1'b0),
11168 .wd ('0),
11169
11170 // from internal hardware
11171 .de (hw2reg.ip[173].de),
11172 .d (hw2reg.ip[173].d),
11173
11174 // to internal hardware
11175 .qe (),
11176 .q (),
11177 .ds (),
11178
11179 // to register interface (read)
11180 .qs (ip_5_p_173_qs)
11181 );
11182
11183 // F[p_174]: 14:14
11184 prim_subreg #(
11185 .DW (1),
11186 .SwAccess(prim_subreg_pkg::SwAccessRO),
11187 .RESVAL (1'h0),
11188 .Mubi (1'b0)
11189 ) u_ip_5_p_174 (
11190 .clk_i (clk_i),
11191 .rst_ni (rst_ni),
11192
11193 // from register interface
11194 .we (1'b0),
11195 .wd ('0),
11196
11197 // from internal hardware
11198 .de (hw2reg.ip[174].de),
11199 .d (hw2reg.ip[174].d),
11200
11201 // to internal hardware
11202 .qe (),
11203 .q (),
11204 .ds (),
11205
11206 // to register interface (read)
11207 .qs (ip_5_p_174_qs)
11208 );
11209
11210 // F[p_175]: 15:15
11211 prim_subreg #(
11212 .DW (1),
11213 .SwAccess(prim_subreg_pkg::SwAccessRO),
11214 .RESVAL (1'h0),
11215 .Mubi (1'b0)
11216 ) u_ip_5_p_175 (
11217 .clk_i (clk_i),
11218 .rst_ni (rst_ni),
11219
11220 // from register interface
11221 .we (1'b0),
11222 .wd ('0),
11223
11224 // from internal hardware
11225 .de (hw2reg.ip[175].de),
11226 .d (hw2reg.ip[175].d),
11227
11228 // to internal hardware
11229 .qe (),
11230 .q (),
11231 .ds (),
11232
11233 // to register interface (read)
11234 .qs (ip_5_p_175_qs)
11235 );
11236
11237 // F[p_176]: 16:16
11238 prim_subreg #(
11239 .DW (1),
11240 .SwAccess(prim_subreg_pkg::SwAccessRO),
11241 .RESVAL (1'h0),
11242 .Mubi (1'b0)
11243 ) u_ip_5_p_176 (
11244 .clk_i (clk_i),
11245 .rst_ni (rst_ni),
11246
11247 // from register interface
11248 .we (1'b0),
11249 .wd ('0),
11250
11251 // from internal hardware
11252 .de (hw2reg.ip[176].de),
11253 .d (hw2reg.ip[176].d),
11254
11255 // to internal hardware
11256 .qe (),
11257 .q (),
11258 .ds (),
11259
11260 // to register interface (read)
11261 .qs (ip_5_p_176_qs)
11262 );
11263
11264 // F[p_177]: 17:17
11265 prim_subreg #(
11266 .DW (1),
11267 .SwAccess(prim_subreg_pkg::SwAccessRO),
11268 .RESVAL (1'h0),
11269 .Mubi (1'b0)
11270 ) u_ip_5_p_177 (
11271 .clk_i (clk_i),
11272 .rst_ni (rst_ni),
11273
11274 // from register interface
11275 .we (1'b0),
11276 .wd ('0),
11277
11278 // from internal hardware
11279 .de (hw2reg.ip[177].de),
11280 .d (hw2reg.ip[177].d),
11281
11282 // to internal hardware
11283 .qe (),
11284 .q (),
11285 .ds (),
11286
11287 // to register interface (read)
11288 .qs (ip_5_p_177_qs)
11289 );
11290
11291 // F[p_178]: 18:18
11292 prim_subreg #(
11293 .DW (1),
11294 .SwAccess(prim_subreg_pkg::SwAccessRO),
11295 .RESVAL (1'h0),
11296 .Mubi (1'b0)
11297 ) u_ip_5_p_178 (
11298 .clk_i (clk_i),
11299 .rst_ni (rst_ni),
11300
11301 // from register interface
11302 .we (1'b0),
11303 .wd ('0),
11304
11305 // from internal hardware
11306 .de (hw2reg.ip[178].de),
11307 .d (hw2reg.ip[178].d),
11308
11309 // to internal hardware
11310 .qe (),
11311 .q (),
11312 .ds (),
11313
11314 // to register interface (read)
11315 .qs (ip_5_p_178_qs)
11316 );
11317
11318 // F[p_179]: 19:19
11319 prim_subreg #(
11320 .DW (1),
11321 .SwAccess(prim_subreg_pkg::SwAccessRO),
11322 .RESVAL (1'h0),
11323 .Mubi (1'b0)
11324 ) u_ip_5_p_179 (
11325 .clk_i (clk_i),
11326 .rst_ni (rst_ni),
11327
11328 // from register interface
11329 .we (1'b0),
11330 .wd ('0),
11331
11332 // from internal hardware
11333 .de (hw2reg.ip[179].de),
11334 .d (hw2reg.ip[179].d),
11335
11336 // to internal hardware
11337 .qe (),
11338 .q (),
11339 .ds (),
11340
11341 // to register interface (read)
11342 .qs (ip_5_p_179_qs)
11343 );
11344
11345 // F[p_180]: 20:20
11346 prim_subreg #(
11347 .DW (1),
11348 .SwAccess(prim_subreg_pkg::SwAccessRO),
11349 .RESVAL (1'h0),
11350 .Mubi (1'b0)
11351 ) u_ip_5_p_180 (
11352 .clk_i (clk_i),
11353 .rst_ni (rst_ni),
11354
11355 // from register interface
11356 .we (1'b0),
11357 .wd ('0),
11358
11359 // from internal hardware
11360 .de (hw2reg.ip[180].de),
11361 .d (hw2reg.ip[180].d),
11362
11363 // to internal hardware
11364 .qe (),
11365 .q (),
11366 .ds (),
11367
11368 // to register interface (read)
11369 .qs (ip_5_p_180_qs)
11370 );
11371
11372 // F[p_181]: 21:21
11373 prim_subreg #(
11374 .DW (1),
11375 .SwAccess(prim_subreg_pkg::SwAccessRO),
11376 .RESVAL (1'h0),
11377 .Mubi (1'b0)
11378 ) u_ip_5_p_181 (
11379 .clk_i (clk_i),
11380 .rst_ni (rst_ni),
11381
11382 // from register interface
11383 .we (1'b0),
11384 .wd ('0),
11385
11386 // from internal hardware
11387 .de (hw2reg.ip[181].de),
11388 .d (hw2reg.ip[181].d),
11389
11390 // to internal hardware
11391 .qe (),
11392 .q (),
11393 .ds (),
11394
11395 // to register interface (read)
11396 .qs (ip_5_p_181_qs)
11397 );
11398
11399 // F[p_182]: 22:22
11400 prim_subreg #(
11401 .DW (1),
11402 .SwAccess(prim_subreg_pkg::SwAccessRO),
11403 .RESVAL (1'h0),
11404 .Mubi (1'b0)
11405 ) u_ip_5_p_182 (
11406 .clk_i (clk_i),
11407 .rst_ni (rst_ni),
11408
11409 // from register interface
11410 .we (1'b0),
11411 .wd ('0),
11412
11413 // from internal hardware
11414 .de (hw2reg.ip[182].de),
11415 .d (hw2reg.ip[182].d),
11416
11417 // to internal hardware
11418 .qe (),
11419 .q (),
11420 .ds (),
11421
11422 // to register interface (read)
11423 .qs (ip_5_p_182_qs)
11424 );
11425
11426 // F[p_183]: 23:23
11427 prim_subreg #(
11428 .DW (1),
11429 .SwAccess(prim_subreg_pkg::SwAccessRO),
11430 .RESVAL (1'h0),
11431 .Mubi (1'b0)
11432 ) u_ip_5_p_183 (
11433 .clk_i (clk_i),
11434 .rst_ni (rst_ni),
11435
11436 // from register interface
11437 .we (1'b0),
11438 .wd ('0),
11439
11440 // from internal hardware
11441 .de (hw2reg.ip[183].de),
11442 .d (hw2reg.ip[183].d),
11443
11444 // to internal hardware
11445 .qe (),
11446 .q (),
11447 .ds (),
11448
11449 // to register interface (read)
11450 .qs (ip_5_p_183_qs)
11451 );
11452
11453 // F[p_184]: 24:24
11454 prim_subreg #(
11455 .DW (1),
11456 .SwAccess(prim_subreg_pkg::SwAccessRO),
11457 .RESVAL (1'h0),
11458 .Mubi (1'b0)
11459 ) u_ip_5_p_184 (
11460 .clk_i (clk_i),
11461 .rst_ni (rst_ni),
11462
11463 // from register interface
11464 .we (1'b0),
11465 .wd ('0),
11466
11467 // from internal hardware
11468 .de (hw2reg.ip[184].de),
11469 .d (hw2reg.ip[184].d),
11470
11471 // to internal hardware
11472 .qe (),
11473 .q (),
11474 .ds (),
11475
11476 // to register interface (read)
11477 .qs (ip_5_p_184_qs)
11478 );
11479
11480 // F[p_185]: 25:25
11481 prim_subreg #(
11482 .DW (1),
11483 .SwAccess(prim_subreg_pkg::SwAccessRO),
11484 .RESVAL (1'h0),
11485 .Mubi (1'b0)
11486 ) u_ip_5_p_185 (
11487 .clk_i (clk_i),
11488 .rst_ni (rst_ni),
11489
11490 // from register interface
11491 .we (1'b0),
11492 .wd ('0),
11493
11494 // from internal hardware
11495 .de (hw2reg.ip[185].de),
11496 .d (hw2reg.ip[185].d),
11497
11498 // to internal hardware
11499 .qe (),
11500 .q (),
11501 .ds (),
11502
11503 // to register interface (read)
11504 .qs (ip_5_p_185_qs)
11505 );
11506
11507
11508 // Subregister 0 of Multireg ie0
11509 // R[ie0_0]: V(False)
11510 // F[e_0]: 0:0
11511 prim_subreg #(
11512 .DW (1),
11513 .SwAccess(prim_subreg_pkg::SwAccessRW),
11514 .RESVAL (1'h0),
11515 .Mubi (1'b0)
11516 ) u_ie0_0_e_0 (
11517 .clk_i (clk_i),
11518 .rst_ni (rst_ni),
11519
11520 // from register interface
11521 .we (ie0_0_we),
11522 .wd (ie0_0_e_0_wd),
11523
11524 // from internal hardware
11525 .de (1'b0),
11526 .d ('0),
11527
11528 // to internal hardware
11529 .qe (),
11530 .q (reg2hw.ie0[0].q),
11531 .ds (),
11532
11533 // to register interface (read)
11534 .qs (ie0_0_e_0_qs)
11535 );
11536
11537 // F[e_1]: 1:1
11538 prim_subreg #(
11539 .DW (1),
11540 .SwAccess(prim_subreg_pkg::SwAccessRW),
11541 .RESVAL (1'h0),
11542 .Mubi (1'b0)
11543 ) u_ie0_0_e_1 (
11544 .clk_i (clk_i),
11545 .rst_ni (rst_ni),
11546
11547 // from register interface
11548 .we (ie0_0_we),
11549 .wd (ie0_0_e_1_wd),
11550
11551 // from internal hardware
11552 .de (1'b0),
11553 .d ('0),
11554
11555 // to internal hardware
11556 .qe (),
11557 .q (reg2hw.ie0[1].q),
11558 .ds (),
11559
11560 // to register interface (read)
11561 .qs (ie0_0_e_1_qs)
11562 );
11563
11564 // F[e_2]: 2:2
11565 prim_subreg #(
11566 .DW (1),
11567 .SwAccess(prim_subreg_pkg::SwAccessRW),
11568 .RESVAL (1'h0),
11569 .Mubi (1'b0)
11570 ) u_ie0_0_e_2 (
11571 .clk_i (clk_i),
11572 .rst_ni (rst_ni),
11573
11574 // from register interface
11575 .we (ie0_0_we),
11576 .wd (ie0_0_e_2_wd),
11577
11578 // from internal hardware
11579 .de (1'b0),
11580 .d ('0),
11581
11582 // to internal hardware
11583 .qe (),
11584 .q (reg2hw.ie0[2].q),
11585 .ds (),
11586
11587 // to register interface (read)
11588 .qs (ie0_0_e_2_qs)
11589 );
11590
11591 // F[e_3]: 3:3
11592 prim_subreg #(
11593 .DW (1),
11594 .SwAccess(prim_subreg_pkg::SwAccessRW),
11595 .RESVAL (1'h0),
11596 .Mubi (1'b0)
11597 ) u_ie0_0_e_3 (
11598 .clk_i (clk_i),
11599 .rst_ni (rst_ni),
11600
11601 // from register interface
11602 .we (ie0_0_we),
11603 .wd (ie0_0_e_3_wd),
11604
11605 // from internal hardware
11606 .de (1'b0),
11607 .d ('0),
11608
11609 // to internal hardware
11610 .qe (),
11611 .q (reg2hw.ie0[3].q),
11612 .ds (),
11613
11614 // to register interface (read)
11615 .qs (ie0_0_e_3_qs)
11616 );
11617
11618 // F[e_4]: 4:4
11619 prim_subreg #(
11620 .DW (1),
11621 .SwAccess(prim_subreg_pkg::SwAccessRW),
11622 .RESVAL (1'h0),
11623 .Mubi (1'b0)
11624 ) u_ie0_0_e_4 (
11625 .clk_i (clk_i),
11626 .rst_ni (rst_ni),
11627
11628 // from register interface
11629 .we (ie0_0_we),
11630 .wd (ie0_0_e_4_wd),
11631
11632 // from internal hardware
11633 .de (1'b0),
11634 .d ('0),
11635
11636 // to internal hardware
11637 .qe (),
11638 .q (reg2hw.ie0[4].q),
11639 .ds (),
11640
11641 // to register interface (read)
11642 .qs (ie0_0_e_4_qs)
11643 );
11644
11645 // F[e_5]: 5:5
11646 prim_subreg #(
11647 .DW (1),
11648 .SwAccess(prim_subreg_pkg::SwAccessRW),
11649 .RESVAL (1'h0),
11650 .Mubi (1'b0)
11651 ) u_ie0_0_e_5 (
11652 .clk_i (clk_i),
11653 .rst_ni (rst_ni),
11654
11655 // from register interface
11656 .we (ie0_0_we),
11657 .wd (ie0_0_e_5_wd),
11658
11659 // from internal hardware
11660 .de (1'b0),
11661 .d ('0),
11662
11663 // to internal hardware
11664 .qe (),
11665 .q (reg2hw.ie0[5].q),
11666 .ds (),
11667
11668 // to register interface (read)
11669 .qs (ie0_0_e_5_qs)
11670 );
11671
11672 // F[e_6]: 6:6
11673 prim_subreg #(
11674 .DW (1),
11675 .SwAccess(prim_subreg_pkg::SwAccessRW),
11676 .RESVAL (1'h0),
11677 .Mubi (1'b0)
11678 ) u_ie0_0_e_6 (
11679 .clk_i (clk_i),
11680 .rst_ni (rst_ni),
11681
11682 // from register interface
11683 .we (ie0_0_we),
11684 .wd (ie0_0_e_6_wd),
11685
11686 // from internal hardware
11687 .de (1'b0),
11688 .d ('0),
11689
11690 // to internal hardware
11691 .qe (),
11692 .q (reg2hw.ie0[6].q),
11693 .ds (),
11694
11695 // to register interface (read)
11696 .qs (ie0_0_e_6_qs)
11697 );
11698
11699 // F[e_7]: 7:7
11700 prim_subreg #(
11701 .DW (1),
11702 .SwAccess(prim_subreg_pkg::SwAccessRW),
11703 .RESVAL (1'h0),
11704 .Mubi (1'b0)
11705 ) u_ie0_0_e_7 (
11706 .clk_i (clk_i),
11707 .rst_ni (rst_ni),
11708
11709 // from register interface
11710 .we (ie0_0_we),
11711 .wd (ie0_0_e_7_wd),
11712
11713 // from internal hardware
11714 .de (1'b0),
11715 .d ('0),
11716
11717 // to internal hardware
11718 .qe (),
11719 .q (reg2hw.ie0[7].q),
11720 .ds (),
11721
11722 // to register interface (read)
11723 .qs (ie0_0_e_7_qs)
11724 );
11725
11726 // F[e_8]: 8:8
11727 prim_subreg #(
11728 .DW (1),
11729 .SwAccess(prim_subreg_pkg::SwAccessRW),
11730 .RESVAL (1'h0),
11731 .Mubi (1'b0)
11732 ) u_ie0_0_e_8 (
11733 .clk_i (clk_i),
11734 .rst_ni (rst_ni),
11735
11736 // from register interface
11737 .we (ie0_0_we),
11738 .wd (ie0_0_e_8_wd),
11739
11740 // from internal hardware
11741 .de (1'b0),
11742 .d ('0),
11743
11744 // to internal hardware
11745 .qe (),
11746 .q (reg2hw.ie0[8].q),
11747 .ds (),
11748
11749 // to register interface (read)
11750 .qs (ie0_0_e_8_qs)
11751 );
11752
11753 // F[e_9]: 9:9
11754 prim_subreg #(
11755 .DW (1),
11756 .SwAccess(prim_subreg_pkg::SwAccessRW),
11757 .RESVAL (1'h0),
11758 .Mubi (1'b0)
11759 ) u_ie0_0_e_9 (
11760 .clk_i (clk_i),
11761 .rst_ni (rst_ni),
11762
11763 // from register interface
11764 .we (ie0_0_we),
11765 .wd (ie0_0_e_9_wd),
11766
11767 // from internal hardware
11768 .de (1'b0),
11769 .d ('0),
11770
11771 // to internal hardware
11772 .qe (),
11773 .q (reg2hw.ie0[9].q),
11774 .ds (),
11775
11776 // to register interface (read)
11777 .qs (ie0_0_e_9_qs)
11778 );
11779
11780 // F[e_10]: 10:10
11781 prim_subreg #(
11782 .DW (1),
11783 .SwAccess(prim_subreg_pkg::SwAccessRW),
11784 .RESVAL (1'h0),
11785 .Mubi (1'b0)
11786 ) u_ie0_0_e_10 (
11787 .clk_i (clk_i),
11788 .rst_ni (rst_ni),
11789
11790 // from register interface
11791 .we (ie0_0_we),
11792 .wd (ie0_0_e_10_wd),
11793
11794 // from internal hardware
11795 .de (1'b0),
11796 .d ('0),
11797
11798 // to internal hardware
11799 .qe (),
11800 .q (reg2hw.ie0[10].q),
11801 .ds (),
11802
11803 // to register interface (read)
11804 .qs (ie0_0_e_10_qs)
11805 );
11806
11807 // F[e_11]: 11:11
11808 prim_subreg #(
11809 .DW (1),
11810 .SwAccess(prim_subreg_pkg::SwAccessRW),
11811 .RESVAL (1'h0),
11812 .Mubi (1'b0)
11813 ) u_ie0_0_e_11 (
11814 .clk_i (clk_i),
11815 .rst_ni (rst_ni),
11816
11817 // from register interface
11818 .we (ie0_0_we),
11819 .wd (ie0_0_e_11_wd),
11820
11821 // from internal hardware
11822 .de (1'b0),
11823 .d ('0),
11824
11825 // to internal hardware
11826 .qe (),
11827 .q (reg2hw.ie0[11].q),
11828 .ds (),
11829
11830 // to register interface (read)
11831 .qs (ie0_0_e_11_qs)
11832 );
11833
11834 // F[e_12]: 12:12
11835 prim_subreg #(
11836 .DW (1),
11837 .SwAccess(prim_subreg_pkg::SwAccessRW),
11838 .RESVAL (1'h0),
11839 .Mubi (1'b0)
11840 ) u_ie0_0_e_12 (
11841 .clk_i (clk_i),
11842 .rst_ni (rst_ni),
11843
11844 // from register interface
11845 .we (ie0_0_we),
11846 .wd (ie0_0_e_12_wd),
11847
11848 // from internal hardware
11849 .de (1'b0),
11850 .d ('0),
11851
11852 // to internal hardware
11853 .qe (),
11854 .q (reg2hw.ie0[12].q),
11855 .ds (),
11856
11857 // to register interface (read)
11858 .qs (ie0_0_e_12_qs)
11859 );
11860
11861 // F[e_13]: 13:13
11862 prim_subreg #(
11863 .DW (1),
11864 .SwAccess(prim_subreg_pkg::SwAccessRW),
11865 .RESVAL (1'h0),
11866 .Mubi (1'b0)
11867 ) u_ie0_0_e_13 (
11868 .clk_i (clk_i),
11869 .rst_ni (rst_ni),
11870
11871 // from register interface
11872 .we (ie0_0_we),
11873 .wd (ie0_0_e_13_wd),
11874
11875 // from internal hardware
11876 .de (1'b0),
11877 .d ('0),
11878
11879 // to internal hardware
11880 .qe (),
11881 .q (reg2hw.ie0[13].q),
11882 .ds (),
11883
11884 // to register interface (read)
11885 .qs (ie0_0_e_13_qs)
11886 );
11887
11888 // F[e_14]: 14:14
11889 prim_subreg #(
11890 .DW (1),
11891 .SwAccess(prim_subreg_pkg::SwAccessRW),
11892 .RESVAL (1'h0),
11893 .Mubi (1'b0)
11894 ) u_ie0_0_e_14 (
11895 .clk_i (clk_i),
11896 .rst_ni (rst_ni),
11897
11898 // from register interface
11899 .we (ie0_0_we),
11900 .wd (ie0_0_e_14_wd),
11901
11902 // from internal hardware
11903 .de (1'b0),
11904 .d ('0),
11905
11906 // to internal hardware
11907 .qe (),
11908 .q (reg2hw.ie0[14].q),
11909 .ds (),
11910
11911 // to register interface (read)
11912 .qs (ie0_0_e_14_qs)
11913 );
11914
11915 // F[e_15]: 15:15
11916 prim_subreg #(
11917 .DW (1),
11918 .SwAccess(prim_subreg_pkg::SwAccessRW),
11919 .RESVAL (1'h0),
11920 .Mubi (1'b0)
11921 ) u_ie0_0_e_15 (
11922 .clk_i (clk_i),
11923 .rst_ni (rst_ni),
11924
11925 // from register interface
11926 .we (ie0_0_we),
11927 .wd (ie0_0_e_15_wd),
11928
11929 // from internal hardware
11930 .de (1'b0),
11931 .d ('0),
11932
11933 // to internal hardware
11934 .qe (),
11935 .q (reg2hw.ie0[15].q),
11936 .ds (),
11937
11938 // to register interface (read)
11939 .qs (ie0_0_e_15_qs)
11940 );
11941
11942 // F[e_16]: 16:16
11943 prim_subreg #(
11944 .DW (1),
11945 .SwAccess(prim_subreg_pkg::SwAccessRW),
11946 .RESVAL (1'h0),
11947 .Mubi (1'b0)
11948 ) u_ie0_0_e_16 (
11949 .clk_i (clk_i),
11950 .rst_ni (rst_ni),
11951
11952 // from register interface
11953 .we (ie0_0_we),
11954 .wd (ie0_0_e_16_wd),
11955
11956 // from internal hardware
11957 .de (1'b0),
11958 .d ('0),
11959
11960 // to internal hardware
11961 .qe (),
11962 .q (reg2hw.ie0[16].q),
11963 .ds (),
11964
11965 // to register interface (read)
11966 .qs (ie0_0_e_16_qs)
11967 );
11968
11969 // F[e_17]: 17:17
11970 prim_subreg #(
11971 .DW (1),
11972 .SwAccess(prim_subreg_pkg::SwAccessRW),
11973 .RESVAL (1'h0),
11974 .Mubi (1'b0)
11975 ) u_ie0_0_e_17 (
11976 .clk_i (clk_i),
11977 .rst_ni (rst_ni),
11978
11979 // from register interface
11980 .we (ie0_0_we),
11981 .wd (ie0_0_e_17_wd),
11982
11983 // from internal hardware
11984 .de (1'b0),
11985 .d ('0),
11986
11987 // to internal hardware
11988 .qe (),
11989 .q (reg2hw.ie0[17].q),
11990 .ds (),
11991
11992 // to register interface (read)
11993 .qs (ie0_0_e_17_qs)
11994 );
11995
11996 // F[e_18]: 18:18
11997 prim_subreg #(
11998 .DW (1),
11999 .SwAccess(prim_subreg_pkg::SwAccessRW),
12000 .RESVAL (1'h0),
12001 .Mubi (1'b0)
12002 ) u_ie0_0_e_18 (
12003 .clk_i (clk_i),
12004 .rst_ni (rst_ni),
12005
12006 // from register interface
12007 .we (ie0_0_we),
12008 .wd (ie0_0_e_18_wd),
12009
12010 // from internal hardware
12011 .de (1'b0),
12012 .d ('0),
12013
12014 // to internal hardware
12015 .qe (),
12016 .q (reg2hw.ie0[18].q),
12017 .ds (),
12018
12019 // to register interface (read)
12020 .qs (ie0_0_e_18_qs)
12021 );
12022
12023 // F[e_19]: 19:19
12024 prim_subreg #(
12025 .DW (1),
12026 .SwAccess(prim_subreg_pkg::SwAccessRW),
12027 .RESVAL (1'h0),
12028 .Mubi (1'b0)
12029 ) u_ie0_0_e_19 (
12030 .clk_i (clk_i),
12031 .rst_ni (rst_ni),
12032
12033 // from register interface
12034 .we (ie0_0_we),
12035 .wd (ie0_0_e_19_wd),
12036
12037 // from internal hardware
12038 .de (1'b0),
12039 .d ('0),
12040
12041 // to internal hardware
12042 .qe (),
12043 .q (reg2hw.ie0[19].q),
12044 .ds (),
12045
12046 // to register interface (read)
12047 .qs (ie0_0_e_19_qs)
12048 );
12049
12050 // F[e_20]: 20:20
12051 prim_subreg #(
12052 .DW (1),
12053 .SwAccess(prim_subreg_pkg::SwAccessRW),
12054 .RESVAL (1'h0),
12055 .Mubi (1'b0)
12056 ) u_ie0_0_e_20 (
12057 .clk_i (clk_i),
12058 .rst_ni (rst_ni),
12059
12060 // from register interface
12061 .we (ie0_0_we),
12062 .wd (ie0_0_e_20_wd),
12063
12064 // from internal hardware
12065 .de (1'b0),
12066 .d ('0),
12067
12068 // to internal hardware
12069 .qe (),
12070 .q (reg2hw.ie0[20].q),
12071 .ds (),
12072
12073 // to register interface (read)
12074 .qs (ie0_0_e_20_qs)
12075 );
12076
12077 // F[e_21]: 21:21
12078 prim_subreg #(
12079 .DW (1),
12080 .SwAccess(prim_subreg_pkg::SwAccessRW),
12081 .RESVAL (1'h0),
12082 .Mubi (1'b0)
12083 ) u_ie0_0_e_21 (
12084 .clk_i (clk_i),
12085 .rst_ni (rst_ni),
12086
12087 // from register interface
12088 .we (ie0_0_we),
12089 .wd (ie0_0_e_21_wd),
12090
12091 // from internal hardware
12092 .de (1'b0),
12093 .d ('0),
12094
12095 // to internal hardware
12096 .qe (),
12097 .q (reg2hw.ie0[21].q),
12098 .ds (),
12099
12100 // to register interface (read)
12101 .qs (ie0_0_e_21_qs)
12102 );
12103
12104 // F[e_22]: 22:22
12105 prim_subreg #(
12106 .DW (1),
12107 .SwAccess(prim_subreg_pkg::SwAccessRW),
12108 .RESVAL (1'h0),
12109 .Mubi (1'b0)
12110 ) u_ie0_0_e_22 (
12111 .clk_i (clk_i),
12112 .rst_ni (rst_ni),
12113
12114 // from register interface
12115 .we (ie0_0_we),
12116 .wd (ie0_0_e_22_wd),
12117
12118 // from internal hardware
12119 .de (1'b0),
12120 .d ('0),
12121
12122 // to internal hardware
12123 .qe (),
12124 .q (reg2hw.ie0[22].q),
12125 .ds (),
12126
12127 // to register interface (read)
12128 .qs (ie0_0_e_22_qs)
12129 );
12130
12131 // F[e_23]: 23:23
12132 prim_subreg #(
12133 .DW (1),
12134 .SwAccess(prim_subreg_pkg::SwAccessRW),
12135 .RESVAL (1'h0),
12136 .Mubi (1'b0)
12137 ) u_ie0_0_e_23 (
12138 .clk_i (clk_i),
12139 .rst_ni (rst_ni),
12140
12141 // from register interface
12142 .we (ie0_0_we),
12143 .wd (ie0_0_e_23_wd),
12144
12145 // from internal hardware
12146 .de (1'b0),
12147 .d ('0),
12148
12149 // to internal hardware
12150 .qe (),
12151 .q (reg2hw.ie0[23].q),
12152 .ds (),
12153
12154 // to register interface (read)
12155 .qs (ie0_0_e_23_qs)
12156 );
12157
12158 // F[e_24]: 24:24
12159 prim_subreg #(
12160 .DW (1),
12161 .SwAccess(prim_subreg_pkg::SwAccessRW),
12162 .RESVAL (1'h0),
12163 .Mubi (1'b0)
12164 ) u_ie0_0_e_24 (
12165 .clk_i (clk_i),
12166 .rst_ni (rst_ni),
12167
12168 // from register interface
12169 .we (ie0_0_we),
12170 .wd (ie0_0_e_24_wd),
12171
12172 // from internal hardware
12173 .de (1'b0),
12174 .d ('0),
12175
12176 // to internal hardware
12177 .qe (),
12178 .q (reg2hw.ie0[24].q),
12179 .ds (),
12180
12181 // to register interface (read)
12182 .qs (ie0_0_e_24_qs)
12183 );
12184
12185 // F[e_25]: 25:25
12186 prim_subreg #(
12187 .DW (1),
12188 .SwAccess(prim_subreg_pkg::SwAccessRW),
12189 .RESVAL (1'h0),
12190 .Mubi (1'b0)
12191 ) u_ie0_0_e_25 (
12192 .clk_i (clk_i),
12193 .rst_ni (rst_ni),
12194
12195 // from register interface
12196 .we (ie0_0_we),
12197 .wd (ie0_0_e_25_wd),
12198
12199 // from internal hardware
12200 .de (1'b0),
12201 .d ('0),
12202
12203 // to internal hardware
12204 .qe (),
12205 .q (reg2hw.ie0[25].q),
12206 .ds (),
12207
12208 // to register interface (read)
12209 .qs (ie0_0_e_25_qs)
12210 );
12211
12212 // F[e_26]: 26:26
12213 prim_subreg #(
12214 .DW (1),
12215 .SwAccess(prim_subreg_pkg::SwAccessRW),
12216 .RESVAL (1'h0),
12217 .Mubi (1'b0)
12218 ) u_ie0_0_e_26 (
12219 .clk_i (clk_i),
12220 .rst_ni (rst_ni),
12221
12222 // from register interface
12223 .we (ie0_0_we),
12224 .wd (ie0_0_e_26_wd),
12225
12226 // from internal hardware
12227 .de (1'b0),
12228 .d ('0),
12229
12230 // to internal hardware
12231 .qe (),
12232 .q (reg2hw.ie0[26].q),
12233 .ds (),
12234
12235 // to register interface (read)
12236 .qs (ie0_0_e_26_qs)
12237 );
12238
12239 // F[e_27]: 27:27
12240 prim_subreg #(
12241 .DW (1),
12242 .SwAccess(prim_subreg_pkg::SwAccessRW),
12243 .RESVAL (1'h0),
12244 .Mubi (1'b0)
12245 ) u_ie0_0_e_27 (
12246 .clk_i (clk_i),
12247 .rst_ni (rst_ni),
12248
12249 // from register interface
12250 .we (ie0_0_we),
12251 .wd (ie0_0_e_27_wd),
12252
12253 // from internal hardware
12254 .de (1'b0),
12255 .d ('0),
12256
12257 // to internal hardware
12258 .qe (),
12259 .q (reg2hw.ie0[27].q),
12260 .ds (),
12261
12262 // to register interface (read)
12263 .qs (ie0_0_e_27_qs)
12264 );
12265
12266 // F[e_28]: 28:28
12267 prim_subreg #(
12268 .DW (1),
12269 .SwAccess(prim_subreg_pkg::SwAccessRW),
12270 .RESVAL (1'h0),
12271 .Mubi (1'b0)
12272 ) u_ie0_0_e_28 (
12273 .clk_i (clk_i),
12274 .rst_ni (rst_ni),
12275
12276 // from register interface
12277 .we (ie0_0_we),
12278 .wd (ie0_0_e_28_wd),
12279
12280 // from internal hardware
12281 .de (1'b0),
12282 .d ('0),
12283
12284 // to internal hardware
12285 .qe (),
12286 .q (reg2hw.ie0[28].q),
12287 .ds (),
12288
12289 // to register interface (read)
12290 .qs (ie0_0_e_28_qs)
12291 );
12292
12293 // F[e_29]: 29:29
12294 prim_subreg #(
12295 .DW (1),
12296 .SwAccess(prim_subreg_pkg::SwAccessRW),
12297 .RESVAL (1'h0),
12298 .Mubi (1'b0)
12299 ) u_ie0_0_e_29 (
12300 .clk_i (clk_i),
12301 .rst_ni (rst_ni),
12302
12303 // from register interface
12304 .we (ie0_0_we),
12305 .wd (ie0_0_e_29_wd),
12306
12307 // from internal hardware
12308 .de (1'b0),
12309 .d ('0),
12310
12311 // to internal hardware
12312 .qe (),
12313 .q (reg2hw.ie0[29].q),
12314 .ds (),
12315
12316 // to register interface (read)
12317 .qs (ie0_0_e_29_qs)
12318 );
12319
12320 // F[e_30]: 30:30
12321 prim_subreg #(
12322 .DW (1),
12323 .SwAccess(prim_subreg_pkg::SwAccessRW),
12324 .RESVAL (1'h0),
12325 .Mubi (1'b0)
12326 ) u_ie0_0_e_30 (
12327 .clk_i (clk_i),
12328 .rst_ni (rst_ni),
12329
12330 // from register interface
12331 .we (ie0_0_we),
12332 .wd (ie0_0_e_30_wd),
12333
12334 // from internal hardware
12335 .de (1'b0),
12336 .d ('0),
12337
12338 // to internal hardware
12339 .qe (),
12340 .q (reg2hw.ie0[30].q),
12341 .ds (),
12342
12343 // to register interface (read)
12344 .qs (ie0_0_e_30_qs)
12345 );
12346
12347 // F[e_31]: 31:31
12348 prim_subreg #(
12349 .DW (1),
12350 .SwAccess(prim_subreg_pkg::SwAccessRW),
12351 .RESVAL (1'h0),
12352 .Mubi (1'b0)
12353 ) u_ie0_0_e_31 (
12354 .clk_i (clk_i),
12355 .rst_ni (rst_ni),
12356
12357 // from register interface
12358 .we (ie0_0_we),
12359 .wd (ie0_0_e_31_wd),
12360
12361 // from internal hardware
12362 .de (1'b0),
12363 .d ('0),
12364
12365 // to internal hardware
12366 .qe (),
12367 .q (reg2hw.ie0[31].q),
12368 .ds (),
12369
12370 // to register interface (read)
12371 .qs (ie0_0_e_31_qs)
12372 );
12373
12374
12375 // Subregister 1 of Multireg ie0
12376 // R[ie0_1]: V(False)
12377 // F[e_32]: 0:0
12378 prim_subreg #(
12379 .DW (1),
12380 .SwAccess(prim_subreg_pkg::SwAccessRW),
12381 .RESVAL (1'h0),
12382 .Mubi (1'b0)
12383 ) u_ie0_1_e_32 (
12384 .clk_i (clk_i),
12385 .rst_ni (rst_ni),
12386
12387 // from register interface
12388 .we (ie0_1_we),
12389 .wd (ie0_1_e_32_wd),
12390
12391 // from internal hardware
12392 .de (1'b0),
12393 .d ('0),
12394
12395 // to internal hardware
12396 .qe (),
12397 .q (reg2hw.ie0[32].q),
12398 .ds (),
12399
12400 // to register interface (read)
12401 .qs (ie0_1_e_32_qs)
12402 );
12403
12404 // F[e_33]: 1:1
12405 prim_subreg #(
12406 .DW (1),
12407 .SwAccess(prim_subreg_pkg::SwAccessRW),
12408 .RESVAL (1'h0),
12409 .Mubi (1'b0)
12410 ) u_ie0_1_e_33 (
12411 .clk_i (clk_i),
12412 .rst_ni (rst_ni),
12413
12414 // from register interface
12415 .we (ie0_1_we),
12416 .wd (ie0_1_e_33_wd),
12417
12418 // from internal hardware
12419 .de (1'b0),
12420 .d ('0),
12421
12422 // to internal hardware
12423 .qe (),
12424 .q (reg2hw.ie0[33].q),
12425 .ds (),
12426
12427 // to register interface (read)
12428 .qs (ie0_1_e_33_qs)
12429 );
12430
12431 // F[e_34]: 2:2
12432 prim_subreg #(
12433 .DW (1),
12434 .SwAccess(prim_subreg_pkg::SwAccessRW),
12435 .RESVAL (1'h0),
12436 .Mubi (1'b0)
12437 ) u_ie0_1_e_34 (
12438 .clk_i (clk_i),
12439 .rst_ni (rst_ni),
12440
12441 // from register interface
12442 .we (ie0_1_we),
12443 .wd (ie0_1_e_34_wd),
12444
12445 // from internal hardware
12446 .de (1'b0),
12447 .d ('0),
12448
12449 // to internal hardware
12450 .qe (),
12451 .q (reg2hw.ie0[34].q),
12452 .ds (),
12453
12454 // to register interface (read)
12455 .qs (ie0_1_e_34_qs)
12456 );
12457
12458 // F[e_35]: 3:3
12459 prim_subreg #(
12460 .DW (1),
12461 .SwAccess(prim_subreg_pkg::SwAccessRW),
12462 .RESVAL (1'h0),
12463 .Mubi (1'b0)
12464 ) u_ie0_1_e_35 (
12465 .clk_i (clk_i),
12466 .rst_ni (rst_ni),
12467
12468 // from register interface
12469 .we (ie0_1_we),
12470 .wd (ie0_1_e_35_wd),
12471
12472 // from internal hardware
12473 .de (1'b0),
12474 .d ('0),
12475
12476 // to internal hardware
12477 .qe (),
12478 .q (reg2hw.ie0[35].q),
12479 .ds (),
12480
12481 // to register interface (read)
12482 .qs (ie0_1_e_35_qs)
12483 );
12484
12485 // F[e_36]: 4:4
12486 prim_subreg #(
12487 .DW (1),
12488 .SwAccess(prim_subreg_pkg::SwAccessRW),
12489 .RESVAL (1'h0),
12490 .Mubi (1'b0)
12491 ) u_ie0_1_e_36 (
12492 .clk_i (clk_i),
12493 .rst_ni (rst_ni),
12494
12495 // from register interface
12496 .we (ie0_1_we),
12497 .wd (ie0_1_e_36_wd),
12498
12499 // from internal hardware
12500 .de (1'b0),
12501 .d ('0),
12502
12503 // to internal hardware
12504 .qe (),
12505 .q (reg2hw.ie0[36].q),
12506 .ds (),
12507
12508 // to register interface (read)
12509 .qs (ie0_1_e_36_qs)
12510 );
12511
12512 // F[e_37]: 5:5
12513 prim_subreg #(
12514 .DW (1),
12515 .SwAccess(prim_subreg_pkg::SwAccessRW),
12516 .RESVAL (1'h0),
12517 .Mubi (1'b0)
12518 ) u_ie0_1_e_37 (
12519 .clk_i (clk_i),
12520 .rst_ni (rst_ni),
12521
12522 // from register interface
12523 .we (ie0_1_we),
12524 .wd (ie0_1_e_37_wd),
12525
12526 // from internal hardware
12527 .de (1'b0),
12528 .d ('0),
12529
12530 // to internal hardware
12531 .qe (),
12532 .q (reg2hw.ie0[37].q),
12533 .ds (),
12534
12535 // to register interface (read)
12536 .qs (ie0_1_e_37_qs)
12537 );
12538
12539 // F[e_38]: 6:6
12540 prim_subreg #(
12541 .DW (1),
12542 .SwAccess(prim_subreg_pkg::SwAccessRW),
12543 .RESVAL (1'h0),
12544 .Mubi (1'b0)
12545 ) u_ie0_1_e_38 (
12546 .clk_i (clk_i),
12547 .rst_ni (rst_ni),
12548
12549 // from register interface
12550 .we (ie0_1_we),
12551 .wd (ie0_1_e_38_wd),
12552
12553 // from internal hardware
12554 .de (1'b0),
12555 .d ('0),
12556
12557 // to internal hardware
12558 .qe (),
12559 .q (reg2hw.ie0[38].q),
12560 .ds (),
12561
12562 // to register interface (read)
12563 .qs (ie0_1_e_38_qs)
12564 );
12565
12566 // F[e_39]: 7:7
12567 prim_subreg #(
12568 .DW (1),
12569 .SwAccess(prim_subreg_pkg::SwAccessRW),
12570 .RESVAL (1'h0),
12571 .Mubi (1'b0)
12572 ) u_ie0_1_e_39 (
12573 .clk_i (clk_i),
12574 .rst_ni (rst_ni),
12575
12576 // from register interface
12577 .we (ie0_1_we),
12578 .wd (ie0_1_e_39_wd),
12579
12580 // from internal hardware
12581 .de (1'b0),
12582 .d ('0),
12583
12584 // to internal hardware
12585 .qe (),
12586 .q (reg2hw.ie0[39].q),
12587 .ds (),
12588
12589 // to register interface (read)
12590 .qs (ie0_1_e_39_qs)
12591 );
12592
12593 // F[e_40]: 8:8
12594 prim_subreg #(
12595 .DW (1),
12596 .SwAccess(prim_subreg_pkg::SwAccessRW),
12597 .RESVAL (1'h0),
12598 .Mubi (1'b0)
12599 ) u_ie0_1_e_40 (
12600 .clk_i (clk_i),
12601 .rst_ni (rst_ni),
12602
12603 // from register interface
12604 .we (ie0_1_we),
12605 .wd (ie0_1_e_40_wd),
12606
12607 // from internal hardware
12608 .de (1'b0),
12609 .d ('0),
12610
12611 // to internal hardware
12612 .qe (),
12613 .q (reg2hw.ie0[40].q),
12614 .ds (),
12615
12616 // to register interface (read)
12617 .qs (ie0_1_e_40_qs)
12618 );
12619
12620 // F[e_41]: 9:9
12621 prim_subreg #(
12622 .DW (1),
12623 .SwAccess(prim_subreg_pkg::SwAccessRW),
12624 .RESVAL (1'h0),
12625 .Mubi (1'b0)
12626 ) u_ie0_1_e_41 (
12627 .clk_i (clk_i),
12628 .rst_ni (rst_ni),
12629
12630 // from register interface
12631 .we (ie0_1_we),
12632 .wd (ie0_1_e_41_wd),
12633
12634 // from internal hardware
12635 .de (1'b0),
12636 .d ('0),
12637
12638 // to internal hardware
12639 .qe (),
12640 .q (reg2hw.ie0[41].q),
12641 .ds (),
12642
12643 // to register interface (read)
12644 .qs (ie0_1_e_41_qs)
12645 );
12646
12647 // F[e_42]: 10:10
12648 prim_subreg #(
12649 .DW (1),
12650 .SwAccess(prim_subreg_pkg::SwAccessRW),
12651 .RESVAL (1'h0),
12652 .Mubi (1'b0)
12653 ) u_ie0_1_e_42 (
12654 .clk_i (clk_i),
12655 .rst_ni (rst_ni),
12656
12657 // from register interface
12658 .we (ie0_1_we),
12659 .wd (ie0_1_e_42_wd),
12660
12661 // from internal hardware
12662 .de (1'b0),
12663 .d ('0),
12664
12665 // to internal hardware
12666 .qe (),
12667 .q (reg2hw.ie0[42].q),
12668 .ds (),
12669
12670 // to register interface (read)
12671 .qs (ie0_1_e_42_qs)
12672 );
12673
12674 // F[e_43]: 11:11
12675 prim_subreg #(
12676 .DW (1),
12677 .SwAccess(prim_subreg_pkg::SwAccessRW),
12678 .RESVAL (1'h0),
12679 .Mubi (1'b0)
12680 ) u_ie0_1_e_43 (
12681 .clk_i (clk_i),
12682 .rst_ni (rst_ni),
12683
12684 // from register interface
12685 .we (ie0_1_we),
12686 .wd (ie0_1_e_43_wd),
12687
12688 // from internal hardware
12689 .de (1'b0),
12690 .d ('0),
12691
12692 // to internal hardware
12693 .qe (),
12694 .q (reg2hw.ie0[43].q),
12695 .ds (),
12696
12697 // to register interface (read)
12698 .qs (ie0_1_e_43_qs)
12699 );
12700
12701 // F[e_44]: 12:12
12702 prim_subreg #(
12703 .DW (1),
12704 .SwAccess(prim_subreg_pkg::SwAccessRW),
12705 .RESVAL (1'h0),
12706 .Mubi (1'b0)
12707 ) u_ie0_1_e_44 (
12708 .clk_i (clk_i),
12709 .rst_ni (rst_ni),
12710
12711 // from register interface
12712 .we (ie0_1_we),
12713 .wd (ie0_1_e_44_wd),
12714
12715 // from internal hardware
12716 .de (1'b0),
12717 .d ('0),
12718
12719 // to internal hardware
12720 .qe (),
12721 .q (reg2hw.ie0[44].q),
12722 .ds (),
12723
12724 // to register interface (read)
12725 .qs (ie0_1_e_44_qs)
12726 );
12727
12728 // F[e_45]: 13:13
12729 prim_subreg #(
12730 .DW (1),
12731 .SwAccess(prim_subreg_pkg::SwAccessRW),
12732 .RESVAL (1'h0),
12733 .Mubi (1'b0)
12734 ) u_ie0_1_e_45 (
12735 .clk_i (clk_i),
12736 .rst_ni (rst_ni),
12737
12738 // from register interface
12739 .we (ie0_1_we),
12740 .wd (ie0_1_e_45_wd),
12741
12742 // from internal hardware
12743 .de (1'b0),
12744 .d ('0),
12745
12746 // to internal hardware
12747 .qe (),
12748 .q (reg2hw.ie0[45].q),
12749 .ds (),
12750
12751 // to register interface (read)
12752 .qs (ie0_1_e_45_qs)
12753 );
12754
12755 // F[e_46]: 14:14
12756 prim_subreg #(
12757 .DW (1),
12758 .SwAccess(prim_subreg_pkg::SwAccessRW),
12759 .RESVAL (1'h0),
12760 .Mubi (1'b0)
12761 ) u_ie0_1_e_46 (
12762 .clk_i (clk_i),
12763 .rst_ni (rst_ni),
12764
12765 // from register interface
12766 .we (ie0_1_we),
12767 .wd (ie0_1_e_46_wd),
12768
12769 // from internal hardware
12770 .de (1'b0),
12771 .d ('0),
12772
12773 // to internal hardware
12774 .qe (),
12775 .q (reg2hw.ie0[46].q),
12776 .ds (),
12777
12778 // to register interface (read)
12779 .qs (ie0_1_e_46_qs)
12780 );
12781
12782 // F[e_47]: 15:15
12783 prim_subreg #(
12784 .DW (1),
12785 .SwAccess(prim_subreg_pkg::SwAccessRW),
12786 .RESVAL (1'h0),
12787 .Mubi (1'b0)
12788 ) u_ie0_1_e_47 (
12789 .clk_i (clk_i),
12790 .rst_ni (rst_ni),
12791
12792 // from register interface
12793 .we (ie0_1_we),
12794 .wd (ie0_1_e_47_wd),
12795
12796 // from internal hardware
12797 .de (1'b0),
12798 .d ('0),
12799
12800 // to internal hardware
12801 .qe (),
12802 .q (reg2hw.ie0[47].q),
12803 .ds (),
12804
12805 // to register interface (read)
12806 .qs (ie0_1_e_47_qs)
12807 );
12808
12809 // F[e_48]: 16:16
12810 prim_subreg #(
12811 .DW (1),
12812 .SwAccess(prim_subreg_pkg::SwAccessRW),
12813 .RESVAL (1'h0),
12814 .Mubi (1'b0)
12815 ) u_ie0_1_e_48 (
12816 .clk_i (clk_i),
12817 .rst_ni (rst_ni),
12818
12819 // from register interface
12820 .we (ie0_1_we),
12821 .wd (ie0_1_e_48_wd),
12822
12823 // from internal hardware
12824 .de (1'b0),
12825 .d ('0),
12826
12827 // to internal hardware
12828 .qe (),
12829 .q (reg2hw.ie0[48].q),
12830 .ds (),
12831
12832 // to register interface (read)
12833 .qs (ie0_1_e_48_qs)
12834 );
12835
12836 // F[e_49]: 17:17
12837 prim_subreg #(
12838 .DW (1),
12839 .SwAccess(prim_subreg_pkg::SwAccessRW),
12840 .RESVAL (1'h0),
12841 .Mubi (1'b0)
12842 ) u_ie0_1_e_49 (
12843 .clk_i (clk_i),
12844 .rst_ni (rst_ni),
12845
12846 // from register interface
12847 .we (ie0_1_we),
12848 .wd (ie0_1_e_49_wd),
12849
12850 // from internal hardware
12851 .de (1'b0),
12852 .d ('0),
12853
12854 // to internal hardware
12855 .qe (),
12856 .q (reg2hw.ie0[49].q),
12857 .ds (),
12858
12859 // to register interface (read)
12860 .qs (ie0_1_e_49_qs)
12861 );
12862
12863 // F[e_50]: 18:18
12864 prim_subreg #(
12865 .DW (1),
12866 .SwAccess(prim_subreg_pkg::SwAccessRW),
12867 .RESVAL (1'h0),
12868 .Mubi (1'b0)
12869 ) u_ie0_1_e_50 (
12870 .clk_i (clk_i),
12871 .rst_ni (rst_ni),
12872
12873 // from register interface
12874 .we (ie0_1_we),
12875 .wd (ie0_1_e_50_wd),
12876
12877 // from internal hardware
12878 .de (1'b0),
12879 .d ('0),
12880
12881 // to internal hardware
12882 .qe (),
12883 .q (reg2hw.ie0[50].q),
12884 .ds (),
12885
12886 // to register interface (read)
12887 .qs (ie0_1_e_50_qs)
12888 );
12889
12890 // F[e_51]: 19:19
12891 prim_subreg #(
12892 .DW (1),
12893 .SwAccess(prim_subreg_pkg::SwAccessRW),
12894 .RESVAL (1'h0),
12895 .Mubi (1'b0)
12896 ) u_ie0_1_e_51 (
12897 .clk_i (clk_i),
12898 .rst_ni (rst_ni),
12899
12900 // from register interface
12901 .we (ie0_1_we),
12902 .wd (ie0_1_e_51_wd),
12903
12904 // from internal hardware
12905 .de (1'b0),
12906 .d ('0),
12907
12908 // to internal hardware
12909 .qe (),
12910 .q (reg2hw.ie0[51].q),
12911 .ds (),
12912
12913 // to register interface (read)
12914 .qs (ie0_1_e_51_qs)
12915 );
12916
12917 // F[e_52]: 20:20
12918 prim_subreg #(
12919 .DW (1),
12920 .SwAccess(prim_subreg_pkg::SwAccessRW),
12921 .RESVAL (1'h0),
12922 .Mubi (1'b0)
12923 ) u_ie0_1_e_52 (
12924 .clk_i (clk_i),
12925 .rst_ni (rst_ni),
12926
12927 // from register interface
12928 .we (ie0_1_we),
12929 .wd (ie0_1_e_52_wd),
12930
12931 // from internal hardware
12932 .de (1'b0),
12933 .d ('0),
12934
12935 // to internal hardware
12936 .qe (),
12937 .q (reg2hw.ie0[52].q),
12938 .ds (),
12939
12940 // to register interface (read)
12941 .qs (ie0_1_e_52_qs)
12942 );
12943
12944 // F[e_53]: 21:21
12945 prim_subreg #(
12946 .DW (1),
12947 .SwAccess(prim_subreg_pkg::SwAccessRW),
12948 .RESVAL (1'h0),
12949 .Mubi (1'b0)
12950 ) u_ie0_1_e_53 (
12951 .clk_i (clk_i),
12952 .rst_ni (rst_ni),
12953
12954 // from register interface
12955 .we (ie0_1_we),
12956 .wd (ie0_1_e_53_wd),
12957
12958 // from internal hardware
12959 .de (1'b0),
12960 .d ('0),
12961
12962 // to internal hardware
12963 .qe (),
12964 .q (reg2hw.ie0[53].q),
12965 .ds (),
12966
12967 // to register interface (read)
12968 .qs (ie0_1_e_53_qs)
12969 );
12970
12971 // F[e_54]: 22:22
12972 prim_subreg #(
12973 .DW (1),
12974 .SwAccess(prim_subreg_pkg::SwAccessRW),
12975 .RESVAL (1'h0),
12976 .Mubi (1'b0)
12977 ) u_ie0_1_e_54 (
12978 .clk_i (clk_i),
12979 .rst_ni (rst_ni),
12980
12981 // from register interface
12982 .we (ie0_1_we),
12983 .wd (ie0_1_e_54_wd),
12984
12985 // from internal hardware
12986 .de (1'b0),
12987 .d ('0),
12988
12989 // to internal hardware
12990 .qe (),
12991 .q (reg2hw.ie0[54].q),
12992 .ds (),
12993
12994 // to register interface (read)
12995 .qs (ie0_1_e_54_qs)
12996 );
12997
12998 // F[e_55]: 23:23
12999 prim_subreg #(
13000 .DW (1),
13001 .SwAccess(prim_subreg_pkg::SwAccessRW),
13002 .RESVAL (1'h0),
13003 .Mubi (1'b0)
13004 ) u_ie0_1_e_55 (
13005 .clk_i (clk_i),
13006 .rst_ni (rst_ni),
13007
13008 // from register interface
13009 .we (ie0_1_we),
13010 .wd (ie0_1_e_55_wd),
13011
13012 // from internal hardware
13013 .de (1'b0),
13014 .d ('0),
13015
13016 // to internal hardware
13017 .qe (),
13018 .q (reg2hw.ie0[55].q),
13019 .ds (),
13020
13021 // to register interface (read)
13022 .qs (ie0_1_e_55_qs)
13023 );
13024
13025 // F[e_56]: 24:24
13026 prim_subreg #(
13027 .DW (1),
13028 .SwAccess(prim_subreg_pkg::SwAccessRW),
13029 .RESVAL (1'h0),
13030 .Mubi (1'b0)
13031 ) u_ie0_1_e_56 (
13032 .clk_i (clk_i),
13033 .rst_ni (rst_ni),
13034
13035 // from register interface
13036 .we (ie0_1_we),
13037 .wd (ie0_1_e_56_wd),
13038
13039 // from internal hardware
13040 .de (1'b0),
13041 .d ('0),
13042
13043 // to internal hardware
13044 .qe (),
13045 .q (reg2hw.ie0[56].q),
13046 .ds (),
13047
13048 // to register interface (read)
13049 .qs (ie0_1_e_56_qs)
13050 );
13051
13052 // F[e_57]: 25:25
13053 prim_subreg #(
13054 .DW (1),
13055 .SwAccess(prim_subreg_pkg::SwAccessRW),
13056 .RESVAL (1'h0),
13057 .Mubi (1'b0)
13058 ) u_ie0_1_e_57 (
13059 .clk_i (clk_i),
13060 .rst_ni (rst_ni),
13061
13062 // from register interface
13063 .we (ie0_1_we),
13064 .wd (ie0_1_e_57_wd),
13065
13066 // from internal hardware
13067 .de (1'b0),
13068 .d ('0),
13069
13070 // to internal hardware
13071 .qe (),
13072 .q (reg2hw.ie0[57].q),
13073 .ds (),
13074
13075 // to register interface (read)
13076 .qs (ie0_1_e_57_qs)
13077 );
13078
13079 // F[e_58]: 26:26
13080 prim_subreg #(
13081 .DW (1),
13082 .SwAccess(prim_subreg_pkg::SwAccessRW),
13083 .RESVAL (1'h0),
13084 .Mubi (1'b0)
13085 ) u_ie0_1_e_58 (
13086 .clk_i (clk_i),
13087 .rst_ni (rst_ni),
13088
13089 // from register interface
13090 .we (ie0_1_we),
13091 .wd (ie0_1_e_58_wd),
13092
13093 // from internal hardware
13094 .de (1'b0),
13095 .d ('0),
13096
13097 // to internal hardware
13098 .qe (),
13099 .q (reg2hw.ie0[58].q),
13100 .ds (),
13101
13102 // to register interface (read)
13103 .qs (ie0_1_e_58_qs)
13104 );
13105
13106 // F[e_59]: 27:27
13107 prim_subreg #(
13108 .DW (1),
13109 .SwAccess(prim_subreg_pkg::SwAccessRW),
13110 .RESVAL (1'h0),
13111 .Mubi (1'b0)
13112 ) u_ie0_1_e_59 (
13113 .clk_i (clk_i),
13114 .rst_ni (rst_ni),
13115
13116 // from register interface
13117 .we (ie0_1_we),
13118 .wd (ie0_1_e_59_wd),
13119
13120 // from internal hardware
13121 .de (1'b0),
13122 .d ('0),
13123
13124 // to internal hardware
13125 .qe (),
13126 .q (reg2hw.ie0[59].q),
13127 .ds (),
13128
13129 // to register interface (read)
13130 .qs (ie0_1_e_59_qs)
13131 );
13132
13133 // F[e_60]: 28:28
13134 prim_subreg #(
13135 .DW (1),
13136 .SwAccess(prim_subreg_pkg::SwAccessRW),
13137 .RESVAL (1'h0),
13138 .Mubi (1'b0)
13139 ) u_ie0_1_e_60 (
13140 .clk_i (clk_i),
13141 .rst_ni (rst_ni),
13142
13143 // from register interface
13144 .we (ie0_1_we),
13145 .wd (ie0_1_e_60_wd),
13146
13147 // from internal hardware
13148 .de (1'b0),
13149 .d ('0),
13150
13151 // to internal hardware
13152 .qe (),
13153 .q (reg2hw.ie0[60].q),
13154 .ds (),
13155
13156 // to register interface (read)
13157 .qs (ie0_1_e_60_qs)
13158 );
13159
13160 // F[e_61]: 29:29
13161 prim_subreg #(
13162 .DW (1),
13163 .SwAccess(prim_subreg_pkg::SwAccessRW),
13164 .RESVAL (1'h0),
13165 .Mubi (1'b0)
13166 ) u_ie0_1_e_61 (
13167 .clk_i (clk_i),
13168 .rst_ni (rst_ni),
13169
13170 // from register interface
13171 .we (ie0_1_we),
13172 .wd (ie0_1_e_61_wd),
13173
13174 // from internal hardware
13175 .de (1'b0),
13176 .d ('0),
13177
13178 // to internal hardware
13179 .qe (),
13180 .q (reg2hw.ie0[61].q),
13181 .ds (),
13182
13183 // to register interface (read)
13184 .qs (ie0_1_e_61_qs)
13185 );
13186
13187 // F[e_62]: 30:30
13188 prim_subreg #(
13189 .DW (1),
13190 .SwAccess(prim_subreg_pkg::SwAccessRW),
13191 .RESVAL (1'h0),
13192 .Mubi (1'b0)
13193 ) u_ie0_1_e_62 (
13194 .clk_i (clk_i),
13195 .rst_ni (rst_ni),
13196
13197 // from register interface
13198 .we (ie0_1_we),
13199 .wd (ie0_1_e_62_wd),
13200
13201 // from internal hardware
13202 .de (1'b0),
13203 .d ('0),
13204
13205 // to internal hardware
13206 .qe (),
13207 .q (reg2hw.ie0[62].q),
13208 .ds (),
13209
13210 // to register interface (read)
13211 .qs (ie0_1_e_62_qs)
13212 );
13213
13214 // F[e_63]: 31:31
13215 prim_subreg #(
13216 .DW (1),
13217 .SwAccess(prim_subreg_pkg::SwAccessRW),
13218 .RESVAL (1'h0),
13219 .Mubi (1'b0)
13220 ) u_ie0_1_e_63 (
13221 .clk_i (clk_i),
13222 .rst_ni (rst_ni),
13223
13224 // from register interface
13225 .we (ie0_1_we),
13226 .wd (ie0_1_e_63_wd),
13227
13228 // from internal hardware
13229 .de (1'b0),
13230 .d ('0),
13231
13232 // to internal hardware
13233 .qe (),
13234 .q (reg2hw.ie0[63].q),
13235 .ds (),
13236
13237 // to register interface (read)
13238 .qs (ie0_1_e_63_qs)
13239 );
13240
13241
13242 // Subregister 2 of Multireg ie0
13243 // R[ie0_2]: V(False)
13244 // F[e_64]: 0:0
13245 prim_subreg #(
13246 .DW (1),
13247 .SwAccess(prim_subreg_pkg::SwAccessRW),
13248 .RESVAL (1'h0),
13249 .Mubi (1'b0)
13250 ) u_ie0_2_e_64 (
13251 .clk_i (clk_i),
13252 .rst_ni (rst_ni),
13253
13254 // from register interface
13255 .we (ie0_2_we),
13256 .wd (ie0_2_e_64_wd),
13257
13258 // from internal hardware
13259 .de (1'b0),
13260 .d ('0),
13261
13262 // to internal hardware
13263 .qe (),
13264 .q (reg2hw.ie0[64].q),
13265 .ds (),
13266
13267 // to register interface (read)
13268 .qs (ie0_2_e_64_qs)
13269 );
13270
13271 // F[e_65]: 1:1
13272 prim_subreg #(
13273 .DW (1),
13274 .SwAccess(prim_subreg_pkg::SwAccessRW),
13275 .RESVAL (1'h0),
13276 .Mubi (1'b0)
13277 ) u_ie0_2_e_65 (
13278 .clk_i (clk_i),
13279 .rst_ni (rst_ni),
13280
13281 // from register interface
13282 .we (ie0_2_we),
13283 .wd (ie0_2_e_65_wd),
13284
13285 // from internal hardware
13286 .de (1'b0),
13287 .d ('0),
13288
13289 // to internal hardware
13290 .qe (),
13291 .q (reg2hw.ie0[65].q),
13292 .ds (),
13293
13294 // to register interface (read)
13295 .qs (ie0_2_e_65_qs)
13296 );
13297
13298 // F[e_66]: 2:2
13299 prim_subreg #(
13300 .DW (1),
13301 .SwAccess(prim_subreg_pkg::SwAccessRW),
13302 .RESVAL (1'h0),
13303 .Mubi (1'b0)
13304 ) u_ie0_2_e_66 (
13305 .clk_i (clk_i),
13306 .rst_ni (rst_ni),
13307
13308 // from register interface
13309 .we (ie0_2_we),
13310 .wd (ie0_2_e_66_wd),
13311
13312 // from internal hardware
13313 .de (1'b0),
13314 .d ('0),
13315
13316 // to internal hardware
13317 .qe (),
13318 .q (reg2hw.ie0[66].q),
13319 .ds (),
13320
13321 // to register interface (read)
13322 .qs (ie0_2_e_66_qs)
13323 );
13324
13325 // F[e_67]: 3:3
13326 prim_subreg #(
13327 .DW (1),
13328 .SwAccess(prim_subreg_pkg::SwAccessRW),
13329 .RESVAL (1'h0),
13330 .Mubi (1'b0)
13331 ) u_ie0_2_e_67 (
13332 .clk_i (clk_i),
13333 .rst_ni (rst_ni),
13334
13335 // from register interface
13336 .we (ie0_2_we),
13337 .wd (ie0_2_e_67_wd),
13338
13339 // from internal hardware
13340 .de (1'b0),
13341 .d ('0),
13342
13343 // to internal hardware
13344 .qe (),
13345 .q (reg2hw.ie0[67].q),
13346 .ds (),
13347
13348 // to register interface (read)
13349 .qs (ie0_2_e_67_qs)
13350 );
13351
13352 // F[e_68]: 4:4
13353 prim_subreg #(
13354 .DW (1),
13355 .SwAccess(prim_subreg_pkg::SwAccessRW),
13356 .RESVAL (1'h0),
13357 .Mubi (1'b0)
13358 ) u_ie0_2_e_68 (
13359 .clk_i (clk_i),
13360 .rst_ni (rst_ni),
13361
13362 // from register interface
13363 .we (ie0_2_we),
13364 .wd (ie0_2_e_68_wd),
13365
13366 // from internal hardware
13367 .de (1'b0),
13368 .d ('0),
13369
13370 // to internal hardware
13371 .qe (),
13372 .q (reg2hw.ie0[68].q),
13373 .ds (),
13374
13375 // to register interface (read)
13376 .qs (ie0_2_e_68_qs)
13377 );
13378
13379 // F[e_69]: 5:5
13380 prim_subreg #(
13381 .DW (1),
13382 .SwAccess(prim_subreg_pkg::SwAccessRW),
13383 .RESVAL (1'h0),
13384 .Mubi (1'b0)
13385 ) u_ie0_2_e_69 (
13386 .clk_i (clk_i),
13387 .rst_ni (rst_ni),
13388
13389 // from register interface
13390 .we (ie0_2_we),
13391 .wd (ie0_2_e_69_wd),
13392
13393 // from internal hardware
13394 .de (1'b0),
13395 .d ('0),
13396
13397 // to internal hardware
13398 .qe (),
13399 .q (reg2hw.ie0[69].q),
13400 .ds (),
13401
13402 // to register interface (read)
13403 .qs (ie0_2_e_69_qs)
13404 );
13405
13406 // F[e_70]: 6:6
13407 prim_subreg #(
13408 .DW (1),
13409 .SwAccess(prim_subreg_pkg::SwAccessRW),
13410 .RESVAL (1'h0),
13411 .Mubi (1'b0)
13412 ) u_ie0_2_e_70 (
13413 .clk_i (clk_i),
13414 .rst_ni (rst_ni),
13415
13416 // from register interface
13417 .we (ie0_2_we),
13418 .wd (ie0_2_e_70_wd),
13419
13420 // from internal hardware
13421 .de (1'b0),
13422 .d ('0),
13423
13424 // to internal hardware
13425 .qe (),
13426 .q (reg2hw.ie0[70].q),
13427 .ds (),
13428
13429 // to register interface (read)
13430 .qs (ie0_2_e_70_qs)
13431 );
13432
13433 // F[e_71]: 7:7
13434 prim_subreg #(
13435 .DW (1),
13436 .SwAccess(prim_subreg_pkg::SwAccessRW),
13437 .RESVAL (1'h0),
13438 .Mubi (1'b0)
13439 ) u_ie0_2_e_71 (
13440 .clk_i (clk_i),
13441 .rst_ni (rst_ni),
13442
13443 // from register interface
13444 .we (ie0_2_we),
13445 .wd (ie0_2_e_71_wd),
13446
13447 // from internal hardware
13448 .de (1'b0),
13449 .d ('0),
13450
13451 // to internal hardware
13452 .qe (),
13453 .q (reg2hw.ie0[71].q),
13454 .ds (),
13455
13456 // to register interface (read)
13457 .qs (ie0_2_e_71_qs)
13458 );
13459
13460 // F[e_72]: 8:8
13461 prim_subreg #(
13462 .DW (1),
13463 .SwAccess(prim_subreg_pkg::SwAccessRW),
13464 .RESVAL (1'h0),
13465 .Mubi (1'b0)
13466 ) u_ie0_2_e_72 (
13467 .clk_i (clk_i),
13468 .rst_ni (rst_ni),
13469
13470 // from register interface
13471 .we (ie0_2_we),
13472 .wd (ie0_2_e_72_wd),
13473
13474 // from internal hardware
13475 .de (1'b0),
13476 .d ('0),
13477
13478 // to internal hardware
13479 .qe (),
13480 .q (reg2hw.ie0[72].q),
13481 .ds (),
13482
13483 // to register interface (read)
13484 .qs (ie0_2_e_72_qs)
13485 );
13486
13487 // F[e_73]: 9:9
13488 prim_subreg #(
13489 .DW (1),
13490 .SwAccess(prim_subreg_pkg::SwAccessRW),
13491 .RESVAL (1'h0),
13492 .Mubi (1'b0)
13493 ) u_ie0_2_e_73 (
13494 .clk_i (clk_i),
13495 .rst_ni (rst_ni),
13496
13497 // from register interface
13498 .we (ie0_2_we),
13499 .wd (ie0_2_e_73_wd),
13500
13501 // from internal hardware
13502 .de (1'b0),
13503 .d ('0),
13504
13505 // to internal hardware
13506 .qe (),
13507 .q (reg2hw.ie0[73].q),
13508 .ds (),
13509
13510 // to register interface (read)
13511 .qs (ie0_2_e_73_qs)
13512 );
13513
13514 // F[e_74]: 10:10
13515 prim_subreg #(
13516 .DW (1),
13517 .SwAccess(prim_subreg_pkg::SwAccessRW),
13518 .RESVAL (1'h0),
13519 .Mubi (1'b0)
13520 ) u_ie0_2_e_74 (
13521 .clk_i (clk_i),
13522 .rst_ni (rst_ni),
13523
13524 // from register interface
13525 .we (ie0_2_we),
13526 .wd (ie0_2_e_74_wd),
13527
13528 // from internal hardware
13529 .de (1'b0),
13530 .d ('0),
13531
13532 // to internal hardware
13533 .qe (),
13534 .q (reg2hw.ie0[74].q),
13535 .ds (),
13536
13537 // to register interface (read)
13538 .qs (ie0_2_e_74_qs)
13539 );
13540
13541 // F[e_75]: 11:11
13542 prim_subreg #(
13543 .DW (1),
13544 .SwAccess(prim_subreg_pkg::SwAccessRW),
13545 .RESVAL (1'h0),
13546 .Mubi (1'b0)
13547 ) u_ie0_2_e_75 (
13548 .clk_i (clk_i),
13549 .rst_ni (rst_ni),
13550
13551 // from register interface
13552 .we (ie0_2_we),
13553 .wd (ie0_2_e_75_wd),
13554
13555 // from internal hardware
13556 .de (1'b0),
13557 .d ('0),
13558
13559 // to internal hardware
13560 .qe (),
13561 .q (reg2hw.ie0[75].q),
13562 .ds (),
13563
13564 // to register interface (read)
13565 .qs (ie0_2_e_75_qs)
13566 );
13567
13568 // F[e_76]: 12:12
13569 prim_subreg #(
13570 .DW (1),
13571 .SwAccess(prim_subreg_pkg::SwAccessRW),
13572 .RESVAL (1'h0),
13573 .Mubi (1'b0)
13574 ) u_ie0_2_e_76 (
13575 .clk_i (clk_i),
13576 .rst_ni (rst_ni),
13577
13578 // from register interface
13579 .we (ie0_2_we),
13580 .wd (ie0_2_e_76_wd),
13581
13582 // from internal hardware
13583 .de (1'b0),
13584 .d ('0),
13585
13586 // to internal hardware
13587 .qe (),
13588 .q (reg2hw.ie0[76].q),
13589 .ds (),
13590
13591 // to register interface (read)
13592 .qs (ie0_2_e_76_qs)
13593 );
13594
13595 // F[e_77]: 13:13
13596 prim_subreg #(
13597 .DW (1),
13598 .SwAccess(prim_subreg_pkg::SwAccessRW),
13599 .RESVAL (1'h0),
13600 .Mubi (1'b0)
13601 ) u_ie0_2_e_77 (
13602 .clk_i (clk_i),
13603 .rst_ni (rst_ni),
13604
13605 // from register interface
13606 .we (ie0_2_we),
13607 .wd (ie0_2_e_77_wd),
13608
13609 // from internal hardware
13610 .de (1'b0),
13611 .d ('0),
13612
13613 // to internal hardware
13614 .qe (),
13615 .q (reg2hw.ie0[77].q),
13616 .ds (),
13617
13618 // to register interface (read)
13619 .qs (ie0_2_e_77_qs)
13620 );
13621
13622 // F[e_78]: 14:14
13623 prim_subreg #(
13624 .DW (1),
13625 .SwAccess(prim_subreg_pkg::SwAccessRW),
13626 .RESVAL (1'h0),
13627 .Mubi (1'b0)
13628 ) u_ie0_2_e_78 (
13629 .clk_i (clk_i),
13630 .rst_ni (rst_ni),
13631
13632 // from register interface
13633 .we (ie0_2_we),
13634 .wd (ie0_2_e_78_wd),
13635
13636 // from internal hardware
13637 .de (1'b0),
13638 .d ('0),
13639
13640 // to internal hardware
13641 .qe (),
13642 .q (reg2hw.ie0[78].q),
13643 .ds (),
13644
13645 // to register interface (read)
13646 .qs (ie0_2_e_78_qs)
13647 );
13648
13649 // F[e_79]: 15:15
13650 prim_subreg #(
13651 .DW (1),
13652 .SwAccess(prim_subreg_pkg::SwAccessRW),
13653 .RESVAL (1'h0),
13654 .Mubi (1'b0)
13655 ) u_ie0_2_e_79 (
13656 .clk_i (clk_i),
13657 .rst_ni (rst_ni),
13658
13659 // from register interface
13660 .we (ie0_2_we),
13661 .wd (ie0_2_e_79_wd),
13662
13663 // from internal hardware
13664 .de (1'b0),
13665 .d ('0),
13666
13667 // to internal hardware
13668 .qe (),
13669 .q (reg2hw.ie0[79].q),
13670 .ds (),
13671
13672 // to register interface (read)
13673 .qs (ie0_2_e_79_qs)
13674 );
13675
13676 // F[e_80]: 16:16
13677 prim_subreg #(
13678 .DW (1),
13679 .SwAccess(prim_subreg_pkg::SwAccessRW),
13680 .RESVAL (1'h0),
13681 .Mubi (1'b0)
13682 ) u_ie0_2_e_80 (
13683 .clk_i (clk_i),
13684 .rst_ni (rst_ni),
13685
13686 // from register interface
13687 .we (ie0_2_we),
13688 .wd (ie0_2_e_80_wd),
13689
13690 // from internal hardware
13691 .de (1'b0),
13692 .d ('0),
13693
13694 // to internal hardware
13695 .qe (),
13696 .q (reg2hw.ie0[80].q),
13697 .ds (),
13698
13699 // to register interface (read)
13700 .qs (ie0_2_e_80_qs)
13701 );
13702
13703 // F[e_81]: 17:17
13704 prim_subreg #(
13705 .DW (1),
13706 .SwAccess(prim_subreg_pkg::SwAccessRW),
13707 .RESVAL (1'h0),
13708 .Mubi (1'b0)
13709 ) u_ie0_2_e_81 (
13710 .clk_i (clk_i),
13711 .rst_ni (rst_ni),
13712
13713 // from register interface
13714 .we (ie0_2_we),
13715 .wd (ie0_2_e_81_wd),
13716
13717 // from internal hardware
13718 .de (1'b0),
13719 .d ('0),
13720
13721 // to internal hardware
13722 .qe (),
13723 .q (reg2hw.ie0[81].q),
13724 .ds (),
13725
13726 // to register interface (read)
13727 .qs (ie0_2_e_81_qs)
13728 );
13729
13730 // F[e_82]: 18:18
13731 prim_subreg #(
13732 .DW (1),
13733 .SwAccess(prim_subreg_pkg::SwAccessRW),
13734 .RESVAL (1'h0),
13735 .Mubi (1'b0)
13736 ) u_ie0_2_e_82 (
13737 .clk_i (clk_i),
13738 .rst_ni (rst_ni),
13739
13740 // from register interface
13741 .we (ie0_2_we),
13742 .wd (ie0_2_e_82_wd),
13743
13744 // from internal hardware
13745 .de (1'b0),
13746 .d ('0),
13747
13748 // to internal hardware
13749 .qe (),
13750 .q (reg2hw.ie0[82].q),
13751 .ds (),
13752
13753 // to register interface (read)
13754 .qs (ie0_2_e_82_qs)
13755 );
13756
13757 // F[e_83]: 19:19
13758 prim_subreg #(
13759 .DW (1),
13760 .SwAccess(prim_subreg_pkg::SwAccessRW),
13761 .RESVAL (1'h0),
13762 .Mubi (1'b0)
13763 ) u_ie0_2_e_83 (
13764 .clk_i (clk_i),
13765 .rst_ni (rst_ni),
13766
13767 // from register interface
13768 .we (ie0_2_we),
13769 .wd (ie0_2_e_83_wd),
13770
13771 // from internal hardware
13772 .de (1'b0),
13773 .d ('0),
13774
13775 // to internal hardware
13776 .qe (),
13777 .q (reg2hw.ie0[83].q),
13778 .ds (),
13779
13780 // to register interface (read)
13781 .qs (ie0_2_e_83_qs)
13782 );
13783
13784 // F[e_84]: 20:20
13785 prim_subreg #(
13786 .DW (1),
13787 .SwAccess(prim_subreg_pkg::SwAccessRW),
13788 .RESVAL (1'h0),
13789 .Mubi (1'b0)
13790 ) u_ie0_2_e_84 (
13791 .clk_i (clk_i),
13792 .rst_ni (rst_ni),
13793
13794 // from register interface
13795 .we (ie0_2_we),
13796 .wd (ie0_2_e_84_wd),
13797
13798 // from internal hardware
13799 .de (1'b0),
13800 .d ('0),
13801
13802 // to internal hardware
13803 .qe (),
13804 .q (reg2hw.ie0[84].q),
13805 .ds (),
13806
13807 // to register interface (read)
13808 .qs (ie0_2_e_84_qs)
13809 );
13810
13811 // F[e_85]: 21:21
13812 prim_subreg #(
13813 .DW (1),
13814 .SwAccess(prim_subreg_pkg::SwAccessRW),
13815 .RESVAL (1'h0),
13816 .Mubi (1'b0)
13817 ) u_ie0_2_e_85 (
13818 .clk_i (clk_i),
13819 .rst_ni (rst_ni),
13820
13821 // from register interface
13822 .we (ie0_2_we),
13823 .wd (ie0_2_e_85_wd),
13824
13825 // from internal hardware
13826 .de (1'b0),
13827 .d ('0),
13828
13829 // to internal hardware
13830 .qe (),
13831 .q (reg2hw.ie0[85].q),
13832 .ds (),
13833
13834 // to register interface (read)
13835 .qs (ie0_2_e_85_qs)
13836 );
13837
13838 // F[e_86]: 22:22
13839 prim_subreg #(
13840 .DW (1),
13841 .SwAccess(prim_subreg_pkg::SwAccessRW),
13842 .RESVAL (1'h0),
13843 .Mubi (1'b0)
13844 ) u_ie0_2_e_86 (
13845 .clk_i (clk_i),
13846 .rst_ni (rst_ni),
13847
13848 // from register interface
13849 .we (ie0_2_we),
13850 .wd (ie0_2_e_86_wd),
13851
13852 // from internal hardware
13853 .de (1'b0),
13854 .d ('0),
13855
13856 // to internal hardware
13857 .qe (),
13858 .q (reg2hw.ie0[86].q),
13859 .ds (),
13860
13861 // to register interface (read)
13862 .qs (ie0_2_e_86_qs)
13863 );
13864
13865 // F[e_87]: 23:23
13866 prim_subreg #(
13867 .DW (1),
13868 .SwAccess(prim_subreg_pkg::SwAccessRW),
13869 .RESVAL (1'h0),
13870 .Mubi (1'b0)
13871 ) u_ie0_2_e_87 (
13872 .clk_i (clk_i),
13873 .rst_ni (rst_ni),
13874
13875 // from register interface
13876 .we (ie0_2_we),
13877 .wd (ie0_2_e_87_wd),
13878
13879 // from internal hardware
13880 .de (1'b0),
13881 .d ('0),
13882
13883 // to internal hardware
13884 .qe (),
13885 .q (reg2hw.ie0[87].q),
13886 .ds (),
13887
13888 // to register interface (read)
13889 .qs (ie0_2_e_87_qs)
13890 );
13891
13892 // F[e_88]: 24:24
13893 prim_subreg #(
13894 .DW (1),
13895 .SwAccess(prim_subreg_pkg::SwAccessRW),
13896 .RESVAL (1'h0),
13897 .Mubi (1'b0)
13898 ) u_ie0_2_e_88 (
13899 .clk_i (clk_i),
13900 .rst_ni (rst_ni),
13901
13902 // from register interface
13903 .we (ie0_2_we),
13904 .wd (ie0_2_e_88_wd),
13905
13906 // from internal hardware
13907 .de (1'b0),
13908 .d ('0),
13909
13910 // to internal hardware
13911 .qe (),
13912 .q (reg2hw.ie0[88].q),
13913 .ds (),
13914
13915 // to register interface (read)
13916 .qs (ie0_2_e_88_qs)
13917 );
13918
13919 // F[e_89]: 25:25
13920 prim_subreg #(
13921 .DW (1),
13922 .SwAccess(prim_subreg_pkg::SwAccessRW),
13923 .RESVAL (1'h0),
13924 .Mubi (1'b0)
13925 ) u_ie0_2_e_89 (
13926 .clk_i (clk_i),
13927 .rst_ni (rst_ni),
13928
13929 // from register interface
13930 .we (ie0_2_we),
13931 .wd (ie0_2_e_89_wd),
13932
13933 // from internal hardware
13934 .de (1'b0),
13935 .d ('0),
13936
13937 // to internal hardware
13938 .qe (),
13939 .q (reg2hw.ie0[89].q),
13940 .ds (),
13941
13942 // to register interface (read)
13943 .qs (ie0_2_e_89_qs)
13944 );
13945
13946 // F[e_90]: 26:26
13947 prim_subreg #(
13948 .DW (1),
13949 .SwAccess(prim_subreg_pkg::SwAccessRW),
13950 .RESVAL (1'h0),
13951 .Mubi (1'b0)
13952 ) u_ie0_2_e_90 (
13953 .clk_i (clk_i),
13954 .rst_ni (rst_ni),
13955
13956 // from register interface
13957 .we (ie0_2_we),
13958 .wd (ie0_2_e_90_wd),
13959
13960 // from internal hardware
13961 .de (1'b0),
13962 .d ('0),
13963
13964 // to internal hardware
13965 .qe (),
13966 .q (reg2hw.ie0[90].q),
13967 .ds (),
13968
13969 // to register interface (read)
13970 .qs (ie0_2_e_90_qs)
13971 );
13972
13973 // F[e_91]: 27:27
13974 prim_subreg #(
13975 .DW (1),
13976 .SwAccess(prim_subreg_pkg::SwAccessRW),
13977 .RESVAL (1'h0),
13978 .Mubi (1'b0)
13979 ) u_ie0_2_e_91 (
13980 .clk_i (clk_i),
13981 .rst_ni (rst_ni),
13982
13983 // from register interface
13984 .we (ie0_2_we),
13985 .wd (ie0_2_e_91_wd),
13986
13987 // from internal hardware
13988 .de (1'b0),
13989 .d ('0),
13990
13991 // to internal hardware
13992 .qe (),
13993 .q (reg2hw.ie0[91].q),
13994 .ds (),
13995
13996 // to register interface (read)
13997 .qs (ie0_2_e_91_qs)
13998 );
13999
14000 // F[e_92]: 28:28
14001 prim_subreg #(
14002 .DW (1),
14003 .SwAccess(prim_subreg_pkg::SwAccessRW),
14004 .RESVAL (1'h0),
14005 .Mubi (1'b0)
14006 ) u_ie0_2_e_92 (
14007 .clk_i (clk_i),
14008 .rst_ni (rst_ni),
14009
14010 // from register interface
14011 .we (ie0_2_we),
14012 .wd (ie0_2_e_92_wd),
14013
14014 // from internal hardware
14015 .de (1'b0),
14016 .d ('0),
14017
14018 // to internal hardware
14019 .qe (),
14020 .q (reg2hw.ie0[92].q),
14021 .ds (),
14022
14023 // to register interface (read)
14024 .qs (ie0_2_e_92_qs)
14025 );
14026
14027 // F[e_93]: 29:29
14028 prim_subreg #(
14029 .DW (1),
14030 .SwAccess(prim_subreg_pkg::SwAccessRW),
14031 .RESVAL (1'h0),
14032 .Mubi (1'b0)
14033 ) u_ie0_2_e_93 (
14034 .clk_i (clk_i),
14035 .rst_ni (rst_ni),
14036
14037 // from register interface
14038 .we (ie0_2_we),
14039 .wd (ie0_2_e_93_wd),
14040
14041 // from internal hardware
14042 .de (1'b0),
14043 .d ('0),
14044
14045 // to internal hardware
14046 .qe (),
14047 .q (reg2hw.ie0[93].q),
14048 .ds (),
14049
14050 // to register interface (read)
14051 .qs (ie0_2_e_93_qs)
14052 );
14053
14054 // F[e_94]: 30:30
14055 prim_subreg #(
14056 .DW (1),
14057 .SwAccess(prim_subreg_pkg::SwAccessRW),
14058 .RESVAL (1'h0),
14059 .Mubi (1'b0)
14060 ) u_ie0_2_e_94 (
14061 .clk_i (clk_i),
14062 .rst_ni (rst_ni),
14063
14064 // from register interface
14065 .we (ie0_2_we),
14066 .wd (ie0_2_e_94_wd),
14067
14068 // from internal hardware
14069 .de (1'b0),
14070 .d ('0),
14071
14072 // to internal hardware
14073 .qe (),
14074 .q (reg2hw.ie0[94].q),
14075 .ds (),
14076
14077 // to register interface (read)
14078 .qs (ie0_2_e_94_qs)
14079 );
14080
14081 // F[e_95]: 31:31
14082 prim_subreg #(
14083 .DW (1),
14084 .SwAccess(prim_subreg_pkg::SwAccessRW),
14085 .RESVAL (1'h0),
14086 .Mubi (1'b0)
14087 ) u_ie0_2_e_95 (
14088 .clk_i (clk_i),
14089 .rst_ni (rst_ni),
14090
14091 // from register interface
14092 .we (ie0_2_we),
14093 .wd (ie0_2_e_95_wd),
14094
14095 // from internal hardware
14096 .de (1'b0),
14097 .d ('0),
14098
14099 // to internal hardware
14100 .qe (),
14101 .q (reg2hw.ie0[95].q),
14102 .ds (),
14103
14104 // to register interface (read)
14105 .qs (ie0_2_e_95_qs)
14106 );
14107
14108
14109 // Subregister 3 of Multireg ie0
14110 // R[ie0_3]: V(False)
14111 // F[e_96]: 0:0
14112 prim_subreg #(
14113 .DW (1),
14114 .SwAccess(prim_subreg_pkg::SwAccessRW),
14115 .RESVAL (1'h0),
14116 .Mubi (1'b0)
14117 ) u_ie0_3_e_96 (
14118 .clk_i (clk_i),
14119 .rst_ni (rst_ni),
14120
14121 // from register interface
14122 .we (ie0_3_we),
14123 .wd (ie0_3_e_96_wd),
14124
14125 // from internal hardware
14126 .de (1'b0),
14127 .d ('0),
14128
14129 // to internal hardware
14130 .qe (),
14131 .q (reg2hw.ie0[96].q),
14132 .ds (),
14133
14134 // to register interface (read)
14135 .qs (ie0_3_e_96_qs)
14136 );
14137
14138 // F[e_97]: 1:1
14139 prim_subreg #(
14140 .DW (1),
14141 .SwAccess(prim_subreg_pkg::SwAccessRW),
14142 .RESVAL (1'h0),
14143 .Mubi (1'b0)
14144 ) u_ie0_3_e_97 (
14145 .clk_i (clk_i),
14146 .rst_ni (rst_ni),
14147
14148 // from register interface
14149 .we (ie0_3_we),
14150 .wd (ie0_3_e_97_wd),
14151
14152 // from internal hardware
14153 .de (1'b0),
14154 .d ('0),
14155
14156 // to internal hardware
14157 .qe (),
14158 .q (reg2hw.ie0[97].q),
14159 .ds (),
14160
14161 // to register interface (read)
14162 .qs (ie0_3_e_97_qs)
14163 );
14164
14165 // F[e_98]: 2:2
14166 prim_subreg #(
14167 .DW (1),
14168 .SwAccess(prim_subreg_pkg::SwAccessRW),
14169 .RESVAL (1'h0),
14170 .Mubi (1'b0)
14171 ) u_ie0_3_e_98 (
14172 .clk_i (clk_i),
14173 .rst_ni (rst_ni),
14174
14175 // from register interface
14176 .we (ie0_3_we),
14177 .wd (ie0_3_e_98_wd),
14178
14179 // from internal hardware
14180 .de (1'b0),
14181 .d ('0),
14182
14183 // to internal hardware
14184 .qe (),
14185 .q (reg2hw.ie0[98].q),
14186 .ds (),
14187
14188 // to register interface (read)
14189 .qs (ie0_3_e_98_qs)
14190 );
14191
14192 // F[e_99]: 3:3
14193 prim_subreg #(
14194 .DW (1),
14195 .SwAccess(prim_subreg_pkg::SwAccessRW),
14196 .RESVAL (1'h0),
14197 .Mubi (1'b0)
14198 ) u_ie0_3_e_99 (
14199 .clk_i (clk_i),
14200 .rst_ni (rst_ni),
14201
14202 // from register interface
14203 .we (ie0_3_we),
14204 .wd (ie0_3_e_99_wd),
14205
14206 // from internal hardware
14207 .de (1'b0),
14208 .d ('0),
14209
14210 // to internal hardware
14211 .qe (),
14212 .q (reg2hw.ie0[99].q),
14213 .ds (),
14214
14215 // to register interface (read)
14216 .qs (ie0_3_e_99_qs)
14217 );
14218
14219 // F[e_100]: 4:4
14220 prim_subreg #(
14221 .DW (1),
14222 .SwAccess(prim_subreg_pkg::SwAccessRW),
14223 .RESVAL (1'h0),
14224 .Mubi (1'b0)
14225 ) u_ie0_3_e_100 (
14226 .clk_i (clk_i),
14227 .rst_ni (rst_ni),
14228
14229 // from register interface
14230 .we (ie0_3_we),
14231 .wd (ie0_3_e_100_wd),
14232
14233 // from internal hardware
14234 .de (1'b0),
14235 .d ('0),
14236
14237 // to internal hardware
14238 .qe (),
14239 .q (reg2hw.ie0[100].q),
14240 .ds (),
14241
14242 // to register interface (read)
14243 .qs (ie0_3_e_100_qs)
14244 );
14245
14246 // F[e_101]: 5:5
14247 prim_subreg #(
14248 .DW (1),
14249 .SwAccess(prim_subreg_pkg::SwAccessRW),
14250 .RESVAL (1'h0),
14251 .Mubi (1'b0)
14252 ) u_ie0_3_e_101 (
14253 .clk_i (clk_i),
14254 .rst_ni (rst_ni),
14255
14256 // from register interface
14257 .we (ie0_3_we),
14258 .wd (ie0_3_e_101_wd),
14259
14260 // from internal hardware
14261 .de (1'b0),
14262 .d ('0),
14263
14264 // to internal hardware
14265 .qe (),
14266 .q (reg2hw.ie0[101].q),
14267 .ds (),
14268
14269 // to register interface (read)
14270 .qs (ie0_3_e_101_qs)
14271 );
14272
14273 // F[e_102]: 6:6
14274 prim_subreg #(
14275 .DW (1),
14276 .SwAccess(prim_subreg_pkg::SwAccessRW),
14277 .RESVAL (1'h0),
14278 .Mubi (1'b0)
14279 ) u_ie0_3_e_102 (
14280 .clk_i (clk_i),
14281 .rst_ni (rst_ni),
14282
14283 // from register interface
14284 .we (ie0_3_we),
14285 .wd (ie0_3_e_102_wd),
14286
14287 // from internal hardware
14288 .de (1'b0),
14289 .d ('0),
14290
14291 // to internal hardware
14292 .qe (),
14293 .q (reg2hw.ie0[102].q),
14294 .ds (),
14295
14296 // to register interface (read)
14297 .qs (ie0_3_e_102_qs)
14298 );
14299
14300 // F[e_103]: 7:7
14301 prim_subreg #(
14302 .DW (1),
14303 .SwAccess(prim_subreg_pkg::SwAccessRW),
14304 .RESVAL (1'h0),
14305 .Mubi (1'b0)
14306 ) u_ie0_3_e_103 (
14307 .clk_i (clk_i),
14308 .rst_ni (rst_ni),
14309
14310 // from register interface
14311 .we (ie0_3_we),
14312 .wd (ie0_3_e_103_wd),
14313
14314 // from internal hardware
14315 .de (1'b0),
14316 .d ('0),
14317
14318 // to internal hardware
14319 .qe (),
14320 .q (reg2hw.ie0[103].q),
14321 .ds (),
14322
14323 // to register interface (read)
14324 .qs (ie0_3_e_103_qs)
14325 );
14326
14327 // F[e_104]: 8:8
14328 prim_subreg #(
14329 .DW (1),
14330 .SwAccess(prim_subreg_pkg::SwAccessRW),
14331 .RESVAL (1'h0),
14332 .Mubi (1'b0)
14333 ) u_ie0_3_e_104 (
14334 .clk_i (clk_i),
14335 .rst_ni (rst_ni),
14336
14337 // from register interface
14338 .we (ie0_3_we),
14339 .wd (ie0_3_e_104_wd),
14340
14341 // from internal hardware
14342 .de (1'b0),
14343 .d ('0),
14344
14345 // to internal hardware
14346 .qe (),
14347 .q (reg2hw.ie0[104].q),
14348 .ds (),
14349
14350 // to register interface (read)
14351 .qs (ie0_3_e_104_qs)
14352 );
14353
14354 // F[e_105]: 9:9
14355 prim_subreg #(
14356 .DW (1),
14357 .SwAccess(prim_subreg_pkg::SwAccessRW),
14358 .RESVAL (1'h0),
14359 .Mubi (1'b0)
14360 ) u_ie0_3_e_105 (
14361 .clk_i (clk_i),
14362 .rst_ni (rst_ni),
14363
14364 // from register interface
14365 .we (ie0_3_we),
14366 .wd (ie0_3_e_105_wd),
14367
14368 // from internal hardware
14369 .de (1'b0),
14370 .d ('0),
14371
14372 // to internal hardware
14373 .qe (),
14374 .q (reg2hw.ie0[105].q),
14375 .ds (),
14376
14377 // to register interface (read)
14378 .qs (ie0_3_e_105_qs)
14379 );
14380
14381 // F[e_106]: 10:10
14382 prim_subreg #(
14383 .DW (1),
14384 .SwAccess(prim_subreg_pkg::SwAccessRW),
14385 .RESVAL (1'h0),
14386 .Mubi (1'b0)
14387 ) u_ie0_3_e_106 (
14388 .clk_i (clk_i),
14389 .rst_ni (rst_ni),
14390
14391 // from register interface
14392 .we (ie0_3_we),
14393 .wd (ie0_3_e_106_wd),
14394
14395 // from internal hardware
14396 .de (1'b0),
14397 .d ('0),
14398
14399 // to internal hardware
14400 .qe (),
14401 .q (reg2hw.ie0[106].q),
14402 .ds (),
14403
14404 // to register interface (read)
14405 .qs (ie0_3_e_106_qs)
14406 );
14407
14408 // F[e_107]: 11:11
14409 prim_subreg #(
14410 .DW (1),
14411 .SwAccess(prim_subreg_pkg::SwAccessRW),
14412 .RESVAL (1'h0),
14413 .Mubi (1'b0)
14414 ) u_ie0_3_e_107 (
14415 .clk_i (clk_i),
14416 .rst_ni (rst_ni),
14417
14418 // from register interface
14419 .we (ie0_3_we),
14420 .wd (ie0_3_e_107_wd),
14421
14422 // from internal hardware
14423 .de (1'b0),
14424 .d ('0),
14425
14426 // to internal hardware
14427 .qe (),
14428 .q (reg2hw.ie0[107].q),
14429 .ds (),
14430
14431 // to register interface (read)
14432 .qs (ie0_3_e_107_qs)
14433 );
14434
14435 // F[e_108]: 12:12
14436 prim_subreg #(
14437 .DW (1),
14438 .SwAccess(prim_subreg_pkg::SwAccessRW),
14439 .RESVAL (1'h0),
14440 .Mubi (1'b0)
14441 ) u_ie0_3_e_108 (
14442 .clk_i (clk_i),
14443 .rst_ni (rst_ni),
14444
14445 // from register interface
14446 .we (ie0_3_we),
14447 .wd (ie0_3_e_108_wd),
14448
14449 // from internal hardware
14450 .de (1'b0),
14451 .d ('0),
14452
14453 // to internal hardware
14454 .qe (),
14455 .q (reg2hw.ie0[108].q),
14456 .ds (),
14457
14458 // to register interface (read)
14459 .qs (ie0_3_e_108_qs)
14460 );
14461
14462 // F[e_109]: 13:13
14463 prim_subreg #(
14464 .DW (1),
14465 .SwAccess(prim_subreg_pkg::SwAccessRW),
14466 .RESVAL (1'h0),
14467 .Mubi (1'b0)
14468 ) u_ie0_3_e_109 (
14469 .clk_i (clk_i),
14470 .rst_ni (rst_ni),
14471
14472 // from register interface
14473 .we (ie0_3_we),
14474 .wd (ie0_3_e_109_wd),
14475
14476 // from internal hardware
14477 .de (1'b0),
14478 .d ('0),
14479
14480 // to internal hardware
14481 .qe (),
14482 .q (reg2hw.ie0[109].q),
14483 .ds (),
14484
14485 // to register interface (read)
14486 .qs (ie0_3_e_109_qs)
14487 );
14488
14489 // F[e_110]: 14:14
14490 prim_subreg #(
14491 .DW (1),
14492 .SwAccess(prim_subreg_pkg::SwAccessRW),
14493 .RESVAL (1'h0),
14494 .Mubi (1'b0)
14495 ) u_ie0_3_e_110 (
14496 .clk_i (clk_i),
14497 .rst_ni (rst_ni),
14498
14499 // from register interface
14500 .we (ie0_3_we),
14501 .wd (ie0_3_e_110_wd),
14502
14503 // from internal hardware
14504 .de (1'b0),
14505 .d ('0),
14506
14507 // to internal hardware
14508 .qe (),
14509 .q (reg2hw.ie0[110].q),
14510 .ds (),
14511
14512 // to register interface (read)
14513 .qs (ie0_3_e_110_qs)
14514 );
14515
14516 // F[e_111]: 15:15
14517 prim_subreg #(
14518 .DW (1),
14519 .SwAccess(prim_subreg_pkg::SwAccessRW),
14520 .RESVAL (1'h0),
14521 .Mubi (1'b0)
14522 ) u_ie0_3_e_111 (
14523 .clk_i (clk_i),
14524 .rst_ni (rst_ni),
14525
14526 // from register interface
14527 .we (ie0_3_we),
14528 .wd (ie0_3_e_111_wd),
14529
14530 // from internal hardware
14531 .de (1'b0),
14532 .d ('0),
14533
14534 // to internal hardware
14535 .qe (),
14536 .q (reg2hw.ie0[111].q),
14537 .ds (),
14538
14539 // to register interface (read)
14540 .qs (ie0_3_e_111_qs)
14541 );
14542
14543 // F[e_112]: 16:16
14544 prim_subreg #(
14545 .DW (1),
14546 .SwAccess(prim_subreg_pkg::SwAccessRW),
14547 .RESVAL (1'h0),
14548 .Mubi (1'b0)
14549 ) u_ie0_3_e_112 (
14550 .clk_i (clk_i),
14551 .rst_ni (rst_ni),
14552
14553 // from register interface
14554 .we (ie0_3_we),
14555 .wd (ie0_3_e_112_wd),
14556
14557 // from internal hardware
14558 .de (1'b0),
14559 .d ('0),
14560
14561 // to internal hardware
14562 .qe (),
14563 .q (reg2hw.ie0[112].q),
14564 .ds (),
14565
14566 // to register interface (read)
14567 .qs (ie0_3_e_112_qs)
14568 );
14569
14570 // F[e_113]: 17:17
14571 prim_subreg #(
14572 .DW (1),
14573 .SwAccess(prim_subreg_pkg::SwAccessRW),
14574 .RESVAL (1'h0),
14575 .Mubi (1'b0)
14576 ) u_ie0_3_e_113 (
14577 .clk_i (clk_i),
14578 .rst_ni (rst_ni),
14579
14580 // from register interface
14581 .we (ie0_3_we),
14582 .wd (ie0_3_e_113_wd),
14583
14584 // from internal hardware
14585 .de (1'b0),
14586 .d ('0),
14587
14588 // to internal hardware
14589 .qe (),
14590 .q (reg2hw.ie0[113].q),
14591 .ds (),
14592
14593 // to register interface (read)
14594 .qs (ie0_3_e_113_qs)
14595 );
14596
14597 // F[e_114]: 18:18
14598 prim_subreg #(
14599 .DW (1),
14600 .SwAccess(prim_subreg_pkg::SwAccessRW),
14601 .RESVAL (1'h0),
14602 .Mubi (1'b0)
14603 ) u_ie0_3_e_114 (
14604 .clk_i (clk_i),
14605 .rst_ni (rst_ni),
14606
14607 // from register interface
14608 .we (ie0_3_we),
14609 .wd (ie0_3_e_114_wd),
14610
14611 // from internal hardware
14612 .de (1'b0),
14613 .d ('0),
14614
14615 // to internal hardware
14616 .qe (),
14617 .q (reg2hw.ie0[114].q),
14618 .ds (),
14619
14620 // to register interface (read)
14621 .qs (ie0_3_e_114_qs)
14622 );
14623
14624 // F[e_115]: 19:19
14625 prim_subreg #(
14626 .DW (1),
14627 .SwAccess(prim_subreg_pkg::SwAccessRW),
14628 .RESVAL (1'h0),
14629 .Mubi (1'b0)
14630 ) u_ie0_3_e_115 (
14631 .clk_i (clk_i),
14632 .rst_ni (rst_ni),
14633
14634 // from register interface
14635 .we (ie0_3_we),
14636 .wd (ie0_3_e_115_wd),
14637
14638 // from internal hardware
14639 .de (1'b0),
14640 .d ('0),
14641
14642 // to internal hardware
14643 .qe (),
14644 .q (reg2hw.ie0[115].q),
14645 .ds (),
14646
14647 // to register interface (read)
14648 .qs (ie0_3_e_115_qs)
14649 );
14650
14651 // F[e_116]: 20:20
14652 prim_subreg #(
14653 .DW (1),
14654 .SwAccess(prim_subreg_pkg::SwAccessRW),
14655 .RESVAL (1'h0),
14656 .Mubi (1'b0)
14657 ) u_ie0_3_e_116 (
14658 .clk_i (clk_i),
14659 .rst_ni (rst_ni),
14660
14661 // from register interface
14662 .we (ie0_3_we),
14663 .wd (ie0_3_e_116_wd),
14664
14665 // from internal hardware
14666 .de (1'b0),
14667 .d ('0),
14668
14669 // to internal hardware
14670 .qe (),
14671 .q (reg2hw.ie0[116].q),
14672 .ds (),
14673
14674 // to register interface (read)
14675 .qs (ie0_3_e_116_qs)
14676 );
14677
14678 // F[e_117]: 21:21
14679 prim_subreg #(
14680 .DW (1),
14681 .SwAccess(prim_subreg_pkg::SwAccessRW),
14682 .RESVAL (1'h0),
14683 .Mubi (1'b0)
14684 ) u_ie0_3_e_117 (
14685 .clk_i (clk_i),
14686 .rst_ni (rst_ni),
14687
14688 // from register interface
14689 .we (ie0_3_we),
14690 .wd (ie0_3_e_117_wd),
14691
14692 // from internal hardware
14693 .de (1'b0),
14694 .d ('0),
14695
14696 // to internal hardware
14697 .qe (),
14698 .q (reg2hw.ie0[117].q),
14699 .ds (),
14700
14701 // to register interface (read)
14702 .qs (ie0_3_e_117_qs)
14703 );
14704
14705 // F[e_118]: 22:22
14706 prim_subreg #(
14707 .DW (1),
14708 .SwAccess(prim_subreg_pkg::SwAccessRW),
14709 .RESVAL (1'h0),
14710 .Mubi (1'b0)
14711 ) u_ie0_3_e_118 (
14712 .clk_i (clk_i),
14713 .rst_ni (rst_ni),
14714
14715 // from register interface
14716 .we (ie0_3_we),
14717 .wd (ie0_3_e_118_wd),
14718
14719 // from internal hardware
14720 .de (1'b0),
14721 .d ('0),
14722
14723 // to internal hardware
14724 .qe (),
14725 .q (reg2hw.ie0[118].q),
14726 .ds (),
14727
14728 // to register interface (read)
14729 .qs (ie0_3_e_118_qs)
14730 );
14731
14732 // F[e_119]: 23:23
14733 prim_subreg #(
14734 .DW (1),
14735 .SwAccess(prim_subreg_pkg::SwAccessRW),
14736 .RESVAL (1'h0),
14737 .Mubi (1'b0)
14738 ) u_ie0_3_e_119 (
14739 .clk_i (clk_i),
14740 .rst_ni (rst_ni),
14741
14742 // from register interface
14743 .we (ie0_3_we),
14744 .wd (ie0_3_e_119_wd),
14745
14746 // from internal hardware
14747 .de (1'b0),
14748 .d ('0),
14749
14750 // to internal hardware
14751 .qe (),
14752 .q (reg2hw.ie0[119].q),
14753 .ds (),
14754
14755 // to register interface (read)
14756 .qs (ie0_3_e_119_qs)
14757 );
14758
14759 // F[e_120]: 24:24
14760 prim_subreg #(
14761 .DW (1),
14762 .SwAccess(prim_subreg_pkg::SwAccessRW),
14763 .RESVAL (1'h0),
14764 .Mubi (1'b0)
14765 ) u_ie0_3_e_120 (
14766 .clk_i (clk_i),
14767 .rst_ni (rst_ni),
14768
14769 // from register interface
14770 .we (ie0_3_we),
14771 .wd (ie0_3_e_120_wd),
14772
14773 // from internal hardware
14774 .de (1'b0),
14775 .d ('0),
14776
14777 // to internal hardware
14778 .qe (),
14779 .q (reg2hw.ie0[120].q),
14780 .ds (),
14781
14782 // to register interface (read)
14783 .qs (ie0_3_e_120_qs)
14784 );
14785
14786 // F[e_121]: 25:25
14787 prim_subreg #(
14788 .DW (1),
14789 .SwAccess(prim_subreg_pkg::SwAccessRW),
14790 .RESVAL (1'h0),
14791 .Mubi (1'b0)
14792 ) u_ie0_3_e_121 (
14793 .clk_i (clk_i),
14794 .rst_ni (rst_ni),
14795
14796 // from register interface
14797 .we (ie0_3_we),
14798 .wd (ie0_3_e_121_wd),
14799
14800 // from internal hardware
14801 .de (1'b0),
14802 .d ('0),
14803
14804 // to internal hardware
14805 .qe (),
14806 .q (reg2hw.ie0[121].q),
14807 .ds (),
14808
14809 // to register interface (read)
14810 .qs (ie0_3_e_121_qs)
14811 );
14812
14813 // F[e_122]: 26:26
14814 prim_subreg #(
14815 .DW (1),
14816 .SwAccess(prim_subreg_pkg::SwAccessRW),
14817 .RESVAL (1'h0),
14818 .Mubi (1'b0)
14819 ) u_ie0_3_e_122 (
14820 .clk_i (clk_i),
14821 .rst_ni (rst_ni),
14822
14823 // from register interface
14824 .we (ie0_3_we),
14825 .wd (ie0_3_e_122_wd),
14826
14827 // from internal hardware
14828 .de (1'b0),
14829 .d ('0),
14830
14831 // to internal hardware
14832 .qe (),
14833 .q (reg2hw.ie0[122].q),
14834 .ds (),
14835
14836 // to register interface (read)
14837 .qs (ie0_3_e_122_qs)
14838 );
14839
14840 // F[e_123]: 27:27
14841 prim_subreg #(
14842 .DW (1),
14843 .SwAccess(prim_subreg_pkg::SwAccessRW),
14844 .RESVAL (1'h0),
14845 .Mubi (1'b0)
14846 ) u_ie0_3_e_123 (
14847 .clk_i (clk_i),
14848 .rst_ni (rst_ni),
14849
14850 // from register interface
14851 .we (ie0_3_we),
14852 .wd (ie0_3_e_123_wd),
14853
14854 // from internal hardware
14855 .de (1'b0),
14856 .d ('0),
14857
14858 // to internal hardware
14859 .qe (),
14860 .q (reg2hw.ie0[123].q),
14861 .ds (),
14862
14863 // to register interface (read)
14864 .qs (ie0_3_e_123_qs)
14865 );
14866
14867 // F[e_124]: 28:28
14868 prim_subreg #(
14869 .DW (1),
14870 .SwAccess(prim_subreg_pkg::SwAccessRW),
14871 .RESVAL (1'h0),
14872 .Mubi (1'b0)
14873 ) u_ie0_3_e_124 (
14874 .clk_i (clk_i),
14875 .rst_ni (rst_ni),
14876
14877 // from register interface
14878 .we (ie0_3_we),
14879 .wd (ie0_3_e_124_wd),
14880
14881 // from internal hardware
14882 .de (1'b0),
14883 .d ('0),
14884
14885 // to internal hardware
14886 .qe (),
14887 .q (reg2hw.ie0[124].q),
14888 .ds (),
14889
14890 // to register interface (read)
14891 .qs (ie0_3_e_124_qs)
14892 );
14893
14894 // F[e_125]: 29:29
14895 prim_subreg #(
14896 .DW (1),
14897 .SwAccess(prim_subreg_pkg::SwAccessRW),
14898 .RESVAL (1'h0),
14899 .Mubi (1'b0)
14900 ) u_ie0_3_e_125 (
14901 .clk_i (clk_i),
14902 .rst_ni (rst_ni),
14903
14904 // from register interface
14905 .we (ie0_3_we),
14906 .wd (ie0_3_e_125_wd),
14907
14908 // from internal hardware
14909 .de (1'b0),
14910 .d ('0),
14911
14912 // to internal hardware
14913 .qe (),
14914 .q (reg2hw.ie0[125].q),
14915 .ds (),
14916
14917 // to register interface (read)
14918 .qs (ie0_3_e_125_qs)
14919 );
14920
14921 // F[e_126]: 30:30
14922 prim_subreg #(
14923 .DW (1),
14924 .SwAccess(prim_subreg_pkg::SwAccessRW),
14925 .RESVAL (1'h0),
14926 .Mubi (1'b0)
14927 ) u_ie0_3_e_126 (
14928 .clk_i (clk_i),
14929 .rst_ni (rst_ni),
14930
14931 // from register interface
14932 .we (ie0_3_we),
14933 .wd (ie0_3_e_126_wd),
14934
14935 // from internal hardware
14936 .de (1'b0),
14937 .d ('0),
14938
14939 // to internal hardware
14940 .qe (),
14941 .q (reg2hw.ie0[126].q),
14942 .ds (),
14943
14944 // to register interface (read)
14945 .qs (ie0_3_e_126_qs)
14946 );
14947
14948 // F[e_127]: 31:31
14949 prim_subreg #(
14950 .DW (1),
14951 .SwAccess(prim_subreg_pkg::SwAccessRW),
14952 .RESVAL (1'h0),
14953 .Mubi (1'b0)
14954 ) u_ie0_3_e_127 (
14955 .clk_i (clk_i),
14956 .rst_ni (rst_ni),
14957
14958 // from register interface
14959 .we (ie0_3_we),
14960 .wd (ie0_3_e_127_wd),
14961
14962 // from internal hardware
14963 .de (1'b0),
14964 .d ('0),
14965
14966 // to internal hardware
14967 .qe (),
14968 .q (reg2hw.ie0[127].q),
14969 .ds (),
14970
14971 // to register interface (read)
14972 .qs (ie0_3_e_127_qs)
14973 );
14974
14975
14976 // Subregister 4 of Multireg ie0
14977 // R[ie0_4]: V(False)
14978 // F[e_128]: 0:0
14979 prim_subreg #(
14980 .DW (1),
14981 .SwAccess(prim_subreg_pkg::SwAccessRW),
14982 .RESVAL (1'h0),
14983 .Mubi (1'b0)
14984 ) u_ie0_4_e_128 (
14985 .clk_i (clk_i),
14986 .rst_ni (rst_ni),
14987
14988 // from register interface
14989 .we (ie0_4_we),
14990 .wd (ie0_4_e_128_wd),
14991
14992 // from internal hardware
14993 .de (1'b0),
14994 .d ('0),
14995
14996 // to internal hardware
14997 .qe (),
14998 .q (reg2hw.ie0[128].q),
14999 .ds (),
15000
15001 // to register interface (read)
15002 .qs (ie0_4_e_128_qs)
15003 );
15004
15005 // F[e_129]: 1:1
15006 prim_subreg #(
15007 .DW (1),
15008 .SwAccess(prim_subreg_pkg::SwAccessRW),
15009 .RESVAL (1'h0),
15010 .Mubi (1'b0)
15011 ) u_ie0_4_e_129 (
15012 .clk_i (clk_i),
15013 .rst_ni (rst_ni),
15014
15015 // from register interface
15016 .we (ie0_4_we),
15017 .wd (ie0_4_e_129_wd),
15018
15019 // from internal hardware
15020 .de (1'b0),
15021 .d ('0),
15022
15023 // to internal hardware
15024 .qe (),
15025 .q (reg2hw.ie0[129].q),
15026 .ds (),
15027
15028 // to register interface (read)
15029 .qs (ie0_4_e_129_qs)
15030 );
15031
15032 // F[e_130]: 2:2
15033 prim_subreg #(
15034 .DW (1),
15035 .SwAccess(prim_subreg_pkg::SwAccessRW),
15036 .RESVAL (1'h0),
15037 .Mubi (1'b0)
15038 ) u_ie0_4_e_130 (
15039 .clk_i (clk_i),
15040 .rst_ni (rst_ni),
15041
15042 // from register interface
15043 .we (ie0_4_we),
15044 .wd (ie0_4_e_130_wd),
15045
15046 // from internal hardware
15047 .de (1'b0),
15048 .d ('0),
15049
15050 // to internal hardware
15051 .qe (),
15052 .q (reg2hw.ie0[130].q),
15053 .ds (),
15054
15055 // to register interface (read)
15056 .qs (ie0_4_e_130_qs)
15057 );
15058
15059 // F[e_131]: 3:3
15060 prim_subreg #(
15061 .DW (1),
15062 .SwAccess(prim_subreg_pkg::SwAccessRW),
15063 .RESVAL (1'h0),
15064 .Mubi (1'b0)
15065 ) u_ie0_4_e_131 (
15066 .clk_i (clk_i),
15067 .rst_ni (rst_ni),
15068
15069 // from register interface
15070 .we (ie0_4_we),
15071 .wd (ie0_4_e_131_wd),
15072
15073 // from internal hardware
15074 .de (1'b0),
15075 .d ('0),
15076
15077 // to internal hardware
15078 .qe (),
15079 .q (reg2hw.ie0[131].q),
15080 .ds (),
15081
15082 // to register interface (read)
15083 .qs (ie0_4_e_131_qs)
15084 );
15085
15086 // F[e_132]: 4:4
15087 prim_subreg #(
15088 .DW (1),
15089 .SwAccess(prim_subreg_pkg::SwAccessRW),
15090 .RESVAL (1'h0),
15091 .Mubi (1'b0)
15092 ) u_ie0_4_e_132 (
15093 .clk_i (clk_i),
15094 .rst_ni (rst_ni),
15095
15096 // from register interface
15097 .we (ie0_4_we),
15098 .wd (ie0_4_e_132_wd),
15099
15100 // from internal hardware
15101 .de (1'b0),
15102 .d ('0),
15103
15104 // to internal hardware
15105 .qe (),
15106 .q (reg2hw.ie0[132].q),
15107 .ds (),
15108
15109 // to register interface (read)
15110 .qs (ie0_4_e_132_qs)
15111 );
15112
15113 // F[e_133]: 5:5
15114 prim_subreg #(
15115 .DW (1),
15116 .SwAccess(prim_subreg_pkg::SwAccessRW),
15117 .RESVAL (1'h0),
15118 .Mubi (1'b0)
15119 ) u_ie0_4_e_133 (
15120 .clk_i (clk_i),
15121 .rst_ni (rst_ni),
15122
15123 // from register interface
15124 .we (ie0_4_we),
15125 .wd (ie0_4_e_133_wd),
15126
15127 // from internal hardware
15128 .de (1'b0),
15129 .d ('0),
15130
15131 // to internal hardware
15132 .qe (),
15133 .q (reg2hw.ie0[133].q),
15134 .ds (),
15135
15136 // to register interface (read)
15137 .qs (ie0_4_e_133_qs)
15138 );
15139
15140 // F[e_134]: 6:6
15141 prim_subreg #(
15142 .DW (1),
15143 .SwAccess(prim_subreg_pkg::SwAccessRW),
15144 .RESVAL (1'h0),
15145 .Mubi (1'b0)
15146 ) u_ie0_4_e_134 (
15147 .clk_i (clk_i),
15148 .rst_ni (rst_ni),
15149
15150 // from register interface
15151 .we (ie0_4_we),
15152 .wd (ie0_4_e_134_wd),
15153
15154 // from internal hardware
15155 .de (1'b0),
15156 .d ('0),
15157
15158 // to internal hardware
15159 .qe (),
15160 .q (reg2hw.ie0[134].q),
15161 .ds (),
15162
15163 // to register interface (read)
15164 .qs (ie0_4_e_134_qs)
15165 );
15166
15167 // F[e_135]: 7:7
15168 prim_subreg #(
15169 .DW (1),
15170 .SwAccess(prim_subreg_pkg::SwAccessRW),
15171 .RESVAL (1'h0),
15172 .Mubi (1'b0)
15173 ) u_ie0_4_e_135 (
15174 .clk_i (clk_i),
15175 .rst_ni (rst_ni),
15176
15177 // from register interface
15178 .we (ie0_4_we),
15179 .wd (ie0_4_e_135_wd),
15180
15181 // from internal hardware
15182 .de (1'b0),
15183 .d ('0),
15184
15185 // to internal hardware
15186 .qe (),
15187 .q (reg2hw.ie0[135].q),
15188 .ds (),
15189
15190 // to register interface (read)
15191 .qs (ie0_4_e_135_qs)
15192 );
15193
15194 // F[e_136]: 8:8
15195 prim_subreg #(
15196 .DW (1),
15197 .SwAccess(prim_subreg_pkg::SwAccessRW),
15198 .RESVAL (1'h0),
15199 .Mubi (1'b0)
15200 ) u_ie0_4_e_136 (
15201 .clk_i (clk_i),
15202 .rst_ni (rst_ni),
15203
15204 // from register interface
15205 .we (ie0_4_we),
15206 .wd (ie0_4_e_136_wd),
15207
15208 // from internal hardware
15209 .de (1'b0),
15210 .d ('0),
15211
15212 // to internal hardware
15213 .qe (),
15214 .q (reg2hw.ie0[136].q),
15215 .ds (),
15216
15217 // to register interface (read)
15218 .qs (ie0_4_e_136_qs)
15219 );
15220
15221 // F[e_137]: 9:9
15222 prim_subreg #(
15223 .DW (1),
15224 .SwAccess(prim_subreg_pkg::SwAccessRW),
15225 .RESVAL (1'h0),
15226 .Mubi (1'b0)
15227 ) u_ie0_4_e_137 (
15228 .clk_i (clk_i),
15229 .rst_ni (rst_ni),
15230
15231 // from register interface
15232 .we (ie0_4_we),
15233 .wd (ie0_4_e_137_wd),
15234
15235 // from internal hardware
15236 .de (1'b0),
15237 .d ('0),
15238
15239 // to internal hardware
15240 .qe (),
15241 .q (reg2hw.ie0[137].q),
15242 .ds (),
15243
15244 // to register interface (read)
15245 .qs (ie0_4_e_137_qs)
15246 );
15247
15248 // F[e_138]: 10:10
15249 prim_subreg #(
15250 .DW (1),
15251 .SwAccess(prim_subreg_pkg::SwAccessRW),
15252 .RESVAL (1'h0),
15253 .Mubi (1'b0)
15254 ) u_ie0_4_e_138 (
15255 .clk_i (clk_i),
15256 .rst_ni (rst_ni),
15257
15258 // from register interface
15259 .we (ie0_4_we),
15260 .wd (ie0_4_e_138_wd),
15261
15262 // from internal hardware
15263 .de (1'b0),
15264 .d ('0),
15265
15266 // to internal hardware
15267 .qe (),
15268 .q (reg2hw.ie0[138].q),
15269 .ds (),
15270
15271 // to register interface (read)
15272 .qs (ie0_4_e_138_qs)
15273 );
15274
15275 // F[e_139]: 11:11
15276 prim_subreg #(
15277 .DW (1),
15278 .SwAccess(prim_subreg_pkg::SwAccessRW),
15279 .RESVAL (1'h0),
15280 .Mubi (1'b0)
15281 ) u_ie0_4_e_139 (
15282 .clk_i (clk_i),
15283 .rst_ni (rst_ni),
15284
15285 // from register interface
15286 .we (ie0_4_we),
15287 .wd (ie0_4_e_139_wd),
15288
15289 // from internal hardware
15290 .de (1'b0),
15291 .d ('0),
15292
15293 // to internal hardware
15294 .qe (),
15295 .q (reg2hw.ie0[139].q),
15296 .ds (),
15297
15298 // to register interface (read)
15299 .qs (ie0_4_e_139_qs)
15300 );
15301
15302 // F[e_140]: 12:12
15303 prim_subreg #(
15304 .DW (1),
15305 .SwAccess(prim_subreg_pkg::SwAccessRW),
15306 .RESVAL (1'h0),
15307 .Mubi (1'b0)
15308 ) u_ie0_4_e_140 (
15309 .clk_i (clk_i),
15310 .rst_ni (rst_ni),
15311
15312 // from register interface
15313 .we (ie0_4_we),
15314 .wd (ie0_4_e_140_wd),
15315
15316 // from internal hardware
15317 .de (1'b0),
15318 .d ('0),
15319
15320 // to internal hardware
15321 .qe (),
15322 .q (reg2hw.ie0[140].q),
15323 .ds (),
15324
15325 // to register interface (read)
15326 .qs (ie0_4_e_140_qs)
15327 );
15328
15329 // F[e_141]: 13:13
15330 prim_subreg #(
15331 .DW (1),
15332 .SwAccess(prim_subreg_pkg::SwAccessRW),
15333 .RESVAL (1'h0),
15334 .Mubi (1'b0)
15335 ) u_ie0_4_e_141 (
15336 .clk_i (clk_i),
15337 .rst_ni (rst_ni),
15338
15339 // from register interface
15340 .we (ie0_4_we),
15341 .wd (ie0_4_e_141_wd),
15342
15343 // from internal hardware
15344 .de (1'b0),
15345 .d ('0),
15346
15347 // to internal hardware
15348 .qe (),
15349 .q (reg2hw.ie0[141].q),
15350 .ds (),
15351
15352 // to register interface (read)
15353 .qs (ie0_4_e_141_qs)
15354 );
15355
15356 // F[e_142]: 14:14
15357 prim_subreg #(
15358 .DW (1),
15359 .SwAccess(prim_subreg_pkg::SwAccessRW),
15360 .RESVAL (1'h0),
15361 .Mubi (1'b0)
15362 ) u_ie0_4_e_142 (
15363 .clk_i (clk_i),
15364 .rst_ni (rst_ni),
15365
15366 // from register interface
15367 .we (ie0_4_we),
15368 .wd (ie0_4_e_142_wd),
15369
15370 // from internal hardware
15371 .de (1'b0),
15372 .d ('0),
15373
15374 // to internal hardware
15375 .qe (),
15376 .q (reg2hw.ie0[142].q),
15377 .ds (),
15378
15379 // to register interface (read)
15380 .qs (ie0_4_e_142_qs)
15381 );
15382
15383 // F[e_143]: 15:15
15384 prim_subreg #(
15385 .DW (1),
15386 .SwAccess(prim_subreg_pkg::SwAccessRW),
15387 .RESVAL (1'h0),
15388 .Mubi (1'b0)
15389 ) u_ie0_4_e_143 (
15390 .clk_i (clk_i),
15391 .rst_ni (rst_ni),
15392
15393 // from register interface
15394 .we (ie0_4_we),
15395 .wd (ie0_4_e_143_wd),
15396
15397 // from internal hardware
15398 .de (1'b0),
15399 .d ('0),
15400
15401 // to internal hardware
15402 .qe (),
15403 .q (reg2hw.ie0[143].q),
15404 .ds (),
15405
15406 // to register interface (read)
15407 .qs (ie0_4_e_143_qs)
15408 );
15409
15410 // F[e_144]: 16:16
15411 prim_subreg #(
15412 .DW (1),
15413 .SwAccess(prim_subreg_pkg::SwAccessRW),
15414 .RESVAL (1'h0),
15415 .Mubi (1'b0)
15416 ) u_ie0_4_e_144 (
15417 .clk_i (clk_i),
15418 .rst_ni (rst_ni),
15419
15420 // from register interface
15421 .we (ie0_4_we),
15422 .wd (ie0_4_e_144_wd),
15423
15424 // from internal hardware
15425 .de (1'b0),
15426 .d ('0),
15427
15428 // to internal hardware
15429 .qe (),
15430 .q (reg2hw.ie0[144].q),
15431 .ds (),
15432
15433 // to register interface (read)
15434 .qs (ie0_4_e_144_qs)
15435 );
15436
15437 // F[e_145]: 17:17
15438 prim_subreg #(
15439 .DW (1),
15440 .SwAccess(prim_subreg_pkg::SwAccessRW),
15441 .RESVAL (1'h0),
15442 .Mubi (1'b0)
15443 ) u_ie0_4_e_145 (
15444 .clk_i (clk_i),
15445 .rst_ni (rst_ni),
15446
15447 // from register interface
15448 .we (ie0_4_we),
15449 .wd (ie0_4_e_145_wd),
15450
15451 // from internal hardware
15452 .de (1'b0),
15453 .d ('0),
15454
15455 // to internal hardware
15456 .qe (),
15457 .q (reg2hw.ie0[145].q),
15458 .ds (),
15459
15460 // to register interface (read)
15461 .qs (ie0_4_e_145_qs)
15462 );
15463
15464 // F[e_146]: 18:18
15465 prim_subreg #(
15466 .DW (1),
15467 .SwAccess(prim_subreg_pkg::SwAccessRW),
15468 .RESVAL (1'h0),
15469 .Mubi (1'b0)
15470 ) u_ie0_4_e_146 (
15471 .clk_i (clk_i),
15472 .rst_ni (rst_ni),
15473
15474 // from register interface
15475 .we (ie0_4_we),
15476 .wd (ie0_4_e_146_wd),
15477
15478 // from internal hardware
15479 .de (1'b0),
15480 .d ('0),
15481
15482 // to internal hardware
15483 .qe (),
15484 .q (reg2hw.ie0[146].q),
15485 .ds (),
15486
15487 // to register interface (read)
15488 .qs (ie0_4_e_146_qs)
15489 );
15490
15491 // F[e_147]: 19:19
15492 prim_subreg #(
15493 .DW (1),
15494 .SwAccess(prim_subreg_pkg::SwAccessRW),
15495 .RESVAL (1'h0),
15496 .Mubi (1'b0)
15497 ) u_ie0_4_e_147 (
15498 .clk_i (clk_i),
15499 .rst_ni (rst_ni),
15500
15501 // from register interface
15502 .we (ie0_4_we),
15503 .wd (ie0_4_e_147_wd),
15504
15505 // from internal hardware
15506 .de (1'b0),
15507 .d ('0),
15508
15509 // to internal hardware
15510 .qe (),
15511 .q (reg2hw.ie0[147].q),
15512 .ds (),
15513
15514 // to register interface (read)
15515 .qs (ie0_4_e_147_qs)
15516 );
15517
15518 // F[e_148]: 20:20
15519 prim_subreg #(
15520 .DW (1),
15521 .SwAccess(prim_subreg_pkg::SwAccessRW),
15522 .RESVAL (1'h0),
15523 .Mubi (1'b0)
15524 ) u_ie0_4_e_148 (
15525 .clk_i (clk_i),
15526 .rst_ni (rst_ni),
15527
15528 // from register interface
15529 .we (ie0_4_we),
15530 .wd (ie0_4_e_148_wd),
15531
15532 // from internal hardware
15533 .de (1'b0),
15534 .d ('0),
15535
15536 // to internal hardware
15537 .qe (),
15538 .q (reg2hw.ie0[148].q),
15539 .ds (),
15540
15541 // to register interface (read)
15542 .qs (ie0_4_e_148_qs)
15543 );
15544
15545 // F[e_149]: 21:21
15546 prim_subreg #(
15547 .DW (1),
15548 .SwAccess(prim_subreg_pkg::SwAccessRW),
15549 .RESVAL (1'h0),
15550 .Mubi (1'b0)
15551 ) u_ie0_4_e_149 (
15552 .clk_i (clk_i),
15553 .rst_ni (rst_ni),
15554
15555 // from register interface
15556 .we (ie0_4_we),
15557 .wd (ie0_4_e_149_wd),
15558
15559 // from internal hardware
15560 .de (1'b0),
15561 .d ('0),
15562
15563 // to internal hardware
15564 .qe (),
15565 .q (reg2hw.ie0[149].q),
15566 .ds (),
15567
15568 // to register interface (read)
15569 .qs (ie0_4_e_149_qs)
15570 );
15571
15572 // F[e_150]: 22:22
15573 prim_subreg #(
15574 .DW (1),
15575 .SwAccess(prim_subreg_pkg::SwAccessRW),
15576 .RESVAL (1'h0),
15577 .Mubi (1'b0)
15578 ) u_ie0_4_e_150 (
15579 .clk_i (clk_i),
15580 .rst_ni (rst_ni),
15581
15582 // from register interface
15583 .we (ie0_4_we),
15584 .wd (ie0_4_e_150_wd),
15585
15586 // from internal hardware
15587 .de (1'b0),
15588 .d ('0),
15589
15590 // to internal hardware
15591 .qe (),
15592 .q (reg2hw.ie0[150].q),
15593 .ds (),
15594
15595 // to register interface (read)
15596 .qs (ie0_4_e_150_qs)
15597 );
15598
15599 // F[e_151]: 23:23
15600 prim_subreg #(
15601 .DW (1),
15602 .SwAccess(prim_subreg_pkg::SwAccessRW),
15603 .RESVAL (1'h0),
15604 .Mubi (1'b0)
15605 ) u_ie0_4_e_151 (
15606 .clk_i (clk_i),
15607 .rst_ni (rst_ni),
15608
15609 // from register interface
15610 .we (ie0_4_we),
15611 .wd (ie0_4_e_151_wd),
15612
15613 // from internal hardware
15614 .de (1'b0),
15615 .d ('0),
15616
15617 // to internal hardware
15618 .qe (),
15619 .q (reg2hw.ie0[151].q),
15620 .ds (),
15621
15622 // to register interface (read)
15623 .qs (ie0_4_e_151_qs)
15624 );
15625
15626 // F[e_152]: 24:24
15627 prim_subreg #(
15628 .DW (1),
15629 .SwAccess(prim_subreg_pkg::SwAccessRW),
15630 .RESVAL (1'h0),
15631 .Mubi (1'b0)
15632 ) u_ie0_4_e_152 (
15633 .clk_i (clk_i),
15634 .rst_ni (rst_ni),
15635
15636 // from register interface
15637 .we (ie0_4_we),
15638 .wd (ie0_4_e_152_wd),
15639
15640 // from internal hardware
15641 .de (1'b0),
15642 .d ('0),
15643
15644 // to internal hardware
15645 .qe (),
15646 .q (reg2hw.ie0[152].q),
15647 .ds (),
15648
15649 // to register interface (read)
15650 .qs (ie0_4_e_152_qs)
15651 );
15652
15653 // F[e_153]: 25:25
15654 prim_subreg #(
15655 .DW (1),
15656 .SwAccess(prim_subreg_pkg::SwAccessRW),
15657 .RESVAL (1'h0),
15658 .Mubi (1'b0)
15659 ) u_ie0_4_e_153 (
15660 .clk_i (clk_i),
15661 .rst_ni (rst_ni),
15662
15663 // from register interface
15664 .we (ie0_4_we),
15665 .wd (ie0_4_e_153_wd),
15666
15667 // from internal hardware
15668 .de (1'b0),
15669 .d ('0),
15670
15671 // to internal hardware
15672 .qe (),
15673 .q (reg2hw.ie0[153].q),
15674 .ds (),
15675
15676 // to register interface (read)
15677 .qs (ie0_4_e_153_qs)
15678 );
15679
15680 // F[e_154]: 26:26
15681 prim_subreg #(
15682 .DW (1),
15683 .SwAccess(prim_subreg_pkg::SwAccessRW),
15684 .RESVAL (1'h0),
15685 .Mubi (1'b0)
15686 ) u_ie0_4_e_154 (
15687 .clk_i (clk_i),
15688 .rst_ni (rst_ni),
15689
15690 // from register interface
15691 .we (ie0_4_we),
15692 .wd (ie0_4_e_154_wd),
15693
15694 // from internal hardware
15695 .de (1'b0),
15696 .d ('0),
15697
15698 // to internal hardware
15699 .qe (),
15700 .q (reg2hw.ie0[154].q),
15701 .ds (),
15702
15703 // to register interface (read)
15704 .qs (ie0_4_e_154_qs)
15705 );
15706
15707 // F[e_155]: 27:27
15708 prim_subreg #(
15709 .DW (1),
15710 .SwAccess(prim_subreg_pkg::SwAccessRW),
15711 .RESVAL (1'h0),
15712 .Mubi (1'b0)
15713 ) u_ie0_4_e_155 (
15714 .clk_i (clk_i),
15715 .rst_ni (rst_ni),
15716
15717 // from register interface
15718 .we (ie0_4_we),
15719 .wd (ie0_4_e_155_wd),
15720
15721 // from internal hardware
15722 .de (1'b0),
15723 .d ('0),
15724
15725 // to internal hardware
15726 .qe (),
15727 .q (reg2hw.ie0[155].q),
15728 .ds (),
15729
15730 // to register interface (read)
15731 .qs (ie0_4_e_155_qs)
15732 );
15733
15734 // F[e_156]: 28:28
15735 prim_subreg #(
15736 .DW (1),
15737 .SwAccess(prim_subreg_pkg::SwAccessRW),
15738 .RESVAL (1'h0),
15739 .Mubi (1'b0)
15740 ) u_ie0_4_e_156 (
15741 .clk_i (clk_i),
15742 .rst_ni (rst_ni),
15743
15744 // from register interface
15745 .we (ie0_4_we),
15746 .wd (ie0_4_e_156_wd),
15747
15748 // from internal hardware
15749 .de (1'b0),
15750 .d ('0),
15751
15752 // to internal hardware
15753 .qe (),
15754 .q (reg2hw.ie0[156].q),
15755 .ds (),
15756
15757 // to register interface (read)
15758 .qs (ie0_4_e_156_qs)
15759 );
15760
15761 // F[e_157]: 29:29
15762 prim_subreg #(
15763 .DW (1),
15764 .SwAccess(prim_subreg_pkg::SwAccessRW),
15765 .RESVAL (1'h0),
15766 .Mubi (1'b0)
15767 ) u_ie0_4_e_157 (
15768 .clk_i (clk_i),
15769 .rst_ni (rst_ni),
15770
15771 // from register interface
15772 .we (ie0_4_we),
15773 .wd (ie0_4_e_157_wd),
15774
15775 // from internal hardware
15776 .de (1'b0),
15777 .d ('0),
15778
15779 // to internal hardware
15780 .qe (),
15781 .q (reg2hw.ie0[157].q),
15782 .ds (),
15783
15784 // to register interface (read)
15785 .qs (ie0_4_e_157_qs)
15786 );
15787
15788 // F[e_158]: 30:30
15789 prim_subreg #(
15790 .DW (1),
15791 .SwAccess(prim_subreg_pkg::SwAccessRW),
15792 .RESVAL (1'h0),
15793 .Mubi (1'b0)
15794 ) u_ie0_4_e_158 (
15795 .clk_i (clk_i),
15796 .rst_ni (rst_ni),
15797
15798 // from register interface
15799 .we (ie0_4_we),
15800 .wd (ie0_4_e_158_wd),
15801
15802 // from internal hardware
15803 .de (1'b0),
15804 .d ('0),
15805
15806 // to internal hardware
15807 .qe (),
15808 .q (reg2hw.ie0[158].q),
15809 .ds (),
15810
15811 // to register interface (read)
15812 .qs (ie0_4_e_158_qs)
15813 );
15814
15815 // F[e_159]: 31:31
15816 prim_subreg #(
15817 .DW (1),
15818 .SwAccess(prim_subreg_pkg::SwAccessRW),
15819 .RESVAL (1'h0),
15820 .Mubi (1'b0)
15821 ) u_ie0_4_e_159 (
15822 .clk_i (clk_i),
15823 .rst_ni (rst_ni),
15824
15825 // from register interface
15826 .we (ie0_4_we),
15827 .wd (ie0_4_e_159_wd),
15828
15829 // from internal hardware
15830 .de (1'b0),
15831 .d ('0),
15832
15833 // to internal hardware
15834 .qe (),
15835 .q (reg2hw.ie0[159].q),
15836 .ds (),
15837
15838 // to register interface (read)
15839 .qs (ie0_4_e_159_qs)
15840 );
15841
15842
15843 // Subregister 5 of Multireg ie0
15844 // R[ie0_5]: V(False)
15845 // F[e_160]: 0:0
15846 prim_subreg #(
15847 .DW (1),
15848 .SwAccess(prim_subreg_pkg::SwAccessRW),
15849 .RESVAL (1'h0),
15850 .Mubi (1'b0)
15851 ) u_ie0_5_e_160 (
15852 .clk_i (clk_i),
15853 .rst_ni (rst_ni),
15854
15855 // from register interface
15856 .we (ie0_5_we),
15857 .wd (ie0_5_e_160_wd),
15858
15859 // from internal hardware
15860 .de (1'b0),
15861 .d ('0),
15862
15863 // to internal hardware
15864 .qe (),
15865 .q (reg2hw.ie0[160].q),
15866 .ds (),
15867
15868 // to register interface (read)
15869 .qs (ie0_5_e_160_qs)
15870 );
15871
15872 // F[e_161]: 1:1
15873 prim_subreg #(
15874 .DW (1),
15875 .SwAccess(prim_subreg_pkg::SwAccessRW),
15876 .RESVAL (1'h0),
15877 .Mubi (1'b0)
15878 ) u_ie0_5_e_161 (
15879 .clk_i (clk_i),
15880 .rst_ni (rst_ni),
15881
15882 // from register interface
15883 .we (ie0_5_we),
15884 .wd (ie0_5_e_161_wd),
15885
15886 // from internal hardware
15887 .de (1'b0),
15888 .d ('0),
15889
15890 // to internal hardware
15891 .qe (),
15892 .q (reg2hw.ie0[161].q),
15893 .ds (),
15894
15895 // to register interface (read)
15896 .qs (ie0_5_e_161_qs)
15897 );
15898
15899 // F[e_162]: 2:2
15900 prim_subreg #(
15901 .DW (1),
15902 .SwAccess(prim_subreg_pkg::SwAccessRW),
15903 .RESVAL (1'h0),
15904 .Mubi (1'b0)
15905 ) u_ie0_5_e_162 (
15906 .clk_i (clk_i),
15907 .rst_ni (rst_ni),
15908
15909 // from register interface
15910 .we (ie0_5_we),
15911 .wd (ie0_5_e_162_wd),
15912
15913 // from internal hardware
15914 .de (1'b0),
15915 .d ('0),
15916
15917 // to internal hardware
15918 .qe (),
15919 .q (reg2hw.ie0[162].q),
15920 .ds (),
15921
15922 // to register interface (read)
15923 .qs (ie0_5_e_162_qs)
15924 );
15925
15926 // F[e_163]: 3:3
15927 prim_subreg #(
15928 .DW (1),
15929 .SwAccess(prim_subreg_pkg::SwAccessRW),
15930 .RESVAL (1'h0),
15931 .Mubi (1'b0)
15932 ) u_ie0_5_e_163 (
15933 .clk_i (clk_i),
15934 .rst_ni (rst_ni),
15935
15936 // from register interface
15937 .we (ie0_5_we),
15938 .wd (ie0_5_e_163_wd),
15939
15940 // from internal hardware
15941 .de (1'b0),
15942 .d ('0),
15943
15944 // to internal hardware
15945 .qe (),
15946 .q (reg2hw.ie0[163].q),
15947 .ds (),
15948
15949 // to register interface (read)
15950 .qs (ie0_5_e_163_qs)
15951 );
15952
15953 // F[e_164]: 4:4
15954 prim_subreg #(
15955 .DW (1),
15956 .SwAccess(prim_subreg_pkg::SwAccessRW),
15957 .RESVAL (1'h0),
15958 .Mubi (1'b0)
15959 ) u_ie0_5_e_164 (
15960 .clk_i (clk_i),
15961 .rst_ni (rst_ni),
15962
15963 // from register interface
15964 .we (ie0_5_we),
15965 .wd (ie0_5_e_164_wd),
15966
15967 // from internal hardware
15968 .de (1'b0),
15969 .d ('0),
15970
15971 // to internal hardware
15972 .qe (),
15973 .q (reg2hw.ie0[164].q),
15974 .ds (),
15975
15976 // to register interface (read)
15977 .qs (ie0_5_e_164_qs)
15978 );
15979
15980 // F[e_165]: 5:5
15981 prim_subreg #(
15982 .DW (1),
15983 .SwAccess(prim_subreg_pkg::SwAccessRW),
15984 .RESVAL (1'h0),
15985 .Mubi (1'b0)
15986 ) u_ie0_5_e_165 (
15987 .clk_i (clk_i),
15988 .rst_ni (rst_ni),
15989
15990 // from register interface
15991 .we (ie0_5_we),
15992 .wd (ie0_5_e_165_wd),
15993
15994 // from internal hardware
15995 .de (1'b0),
15996 .d ('0),
15997
15998 // to internal hardware
15999 .qe (),
16000 .q (reg2hw.ie0[165].q),
16001 .ds (),
16002
16003 // to register interface (read)
16004 .qs (ie0_5_e_165_qs)
16005 );
16006
16007 // F[e_166]: 6:6
16008 prim_subreg #(
16009 .DW (1),
16010 .SwAccess(prim_subreg_pkg::SwAccessRW),
16011 .RESVAL (1'h0),
16012 .Mubi (1'b0)
16013 ) u_ie0_5_e_166 (
16014 .clk_i (clk_i),
16015 .rst_ni (rst_ni),
16016
16017 // from register interface
16018 .we (ie0_5_we),
16019 .wd (ie0_5_e_166_wd),
16020
16021 // from internal hardware
16022 .de (1'b0),
16023 .d ('0),
16024
16025 // to internal hardware
16026 .qe (),
16027 .q (reg2hw.ie0[166].q),
16028 .ds (),
16029
16030 // to register interface (read)
16031 .qs (ie0_5_e_166_qs)
16032 );
16033
16034 // F[e_167]: 7:7
16035 prim_subreg #(
16036 .DW (1),
16037 .SwAccess(prim_subreg_pkg::SwAccessRW),
16038 .RESVAL (1'h0),
16039 .Mubi (1'b0)
16040 ) u_ie0_5_e_167 (
16041 .clk_i (clk_i),
16042 .rst_ni (rst_ni),
16043
16044 // from register interface
16045 .we (ie0_5_we),
16046 .wd (ie0_5_e_167_wd),
16047
16048 // from internal hardware
16049 .de (1'b0),
16050 .d ('0),
16051
16052 // to internal hardware
16053 .qe (),
16054 .q (reg2hw.ie0[167].q),
16055 .ds (),
16056
16057 // to register interface (read)
16058 .qs (ie0_5_e_167_qs)
16059 );
16060
16061 // F[e_168]: 8:8
16062 prim_subreg #(
16063 .DW (1),
16064 .SwAccess(prim_subreg_pkg::SwAccessRW),
16065 .RESVAL (1'h0),
16066 .Mubi (1'b0)
16067 ) u_ie0_5_e_168 (
16068 .clk_i (clk_i),
16069 .rst_ni (rst_ni),
16070
16071 // from register interface
16072 .we (ie0_5_we),
16073 .wd (ie0_5_e_168_wd),
16074
16075 // from internal hardware
16076 .de (1'b0),
16077 .d ('0),
16078
16079 // to internal hardware
16080 .qe (),
16081 .q (reg2hw.ie0[168].q),
16082 .ds (),
16083
16084 // to register interface (read)
16085 .qs (ie0_5_e_168_qs)
16086 );
16087
16088 // F[e_169]: 9:9
16089 prim_subreg #(
16090 .DW (1),
16091 .SwAccess(prim_subreg_pkg::SwAccessRW),
16092 .RESVAL (1'h0),
16093 .Mubi (1'b0)
16094 ) u_ie0_5_e_169 (
16095 .clk_i (clk_i),
16096 .rst_ni (rst_ni),
16097
16098 // from register interface
16099 .we (ie0_5_we),
16100 .wd (ie0_5_e_169_wd),
16101
16102 // from internal hardware
16103 .de (1'b0),
16104 .d ('0),
16105
16106 // to internal hardware
16107 .qe (),
16108 .q (reg2hw.ie0[169].q),
16109 .ds (),
16110
16111 // to register interface (read)
16112 .qs (ie0_5_e_169_qs)
16113 );
16114
16115 // F[e_170]: 10:10
16116 prim_subreg #(
16117 .DW (1),
16118 .SwAccess(prim_subreg_pkg::SwAccessRW),
16119 .RESVAL (1'h0),
16120 .Mubi (1'b0)
16121 ) u_ie0_5_e_170 (
16122 .clk_i (clk_i),
16123 .rst_ni (rst_ni),
16124
16125 // from register interface
16126 .we (ie0_5_we),
16127 .wd (ie0_5_e_170_wd),
16128
16129 // from internal hardware
16130 .de (1'b0),
16131 .d ('0),
16132
16133 // to internal hardware
16134 .qe (),
16135 .q (reg2hw.ie0[170].q),
16136 .ds (),
16137
16138 // to register interface (read)
16139 .qs (ie0_5_e_170_qs)
16140 );
16141
16142 // F[e_171]: 11:11
16143 prim_subreg #(
16144 .DW (1),
16145 .SwAccess(prim_subreg_pkg::SwAccessRW),
16146 .RESVAL (1'h0),
16147 .Mubi (1'b0)
16148 ) u_ie0_5_e_171 (
16149 .clk_i (clk_i),
16150 .rst_ni (rst_ni),
16151
16152 // from register interface
16153 .we (ie0_5_we),
16154 .wd (ie0_5_e_171_wd),
16155
16156 // from internal hardware
16157 .de (1'b0),
16158 .d ('0),
16159
16160 // to internal hardware
16161 .qe (),
16162 .q (reg2hw.ie0[171].q),
16163 .ds (),
16164
16165 // to register interface (read)
16166 .qs (ie0_5_e_171_qs)
16167 );
16168
16169 // F[e_172]: 12:12
16170 prim_subreg #(
16171 .DW (1),
16172 .SwAccess(prim_subreg_pkg::SwAccessRW),
16173 .RESVAL (1'h0),
16174 .Mubi (1'b0)
16175 ) u_ie0_5_e_172 (
16176 .clk_i (clk_i),
16177 .rst_ni (rst_ni),
16178
16179 // from register interface
16180 .we (ie0_5_we),
16181 .wd (ie0_5_e_172_wd),
16182
16183 // from internal hardware
16184 .de (1'b0),
16185 .d ('0),
16186
16187 // to internal hardware
16188 .qe (),
16189 .q (reg2hw.ie0[172].q),
16190 .ds (),
16191
16192 // to register interface (read)
16193 .qs (ie0_5_e_172_qs)
16194 );
16195
16196 // F[e_173]: 13:13
16197 prim_subreg #(
16198 .DW (1),
16199 .SwAccess(prim_subreg_pkg::SwAccessRW),
16200 .RESVAL (1'h0),
16201 .Mubi (1'b0)
16202 ) u_ie0_5_e_173 (
16203 .clk_i (clk_i),
16204 .rst_ni (rst_ni),
16205
16206 // from register interface
16207 .we (ie0_5_we),
16208 .wd (ie0_5_e_173_wd),
16209
16210 // from internal hardware
16211 .de (1'b0),
16212 .d ('0),
16213
16214 // to internal hardware
16215 .qe (),
16216 .q (reg2hw.ie0[173].q),
16217 .ds (),
16218
16219 // to register interface (read)
16220 .qs (ie0_5_e_173_qs)
16221 );
16222
16223 // F[e_174]: 14:14
16224 prim_subreg #(
16225 .DW (1),
16226 .SwAccess(prim_subreg_pkg::SwAccessRW),
16227 .RESVAL (1'h0),
16228 .Mubi (1'b0)
16229 ) u_ie0_5_e_174 (
16230 .clk_i (clk_i),
16231 .rst_ni (rst_ni),
16232
16233 // from register interface
16234 .we (ie0_5_we),
16235 .wd (ie0_5_e_174_wd),
16236
16237 // from internal hardware
16238 .de (1'b0),
16239 .d ('0),
16240
16241 // to internal hardware
16242 .qe (),
16243 .q (reg2hw.ie0[174].q),
16244 .ds (),
16245
16246 // to register interface (read)
16247 .qs (ie0_5_e_174_qs)
16248 );
16249
16250 // F[e_175]: 15:15
16251 prim_subreg #(
16252 .DW (1),
16253 .SwAccess(prim_subreg_pkg::SwAccessRW),
16254 .RESVAL (1'h0),
16255 .Mubi (1'b0)
16256 ) u_ie0_5_e_175 (
16257 .clk_i (clk_i),
16258 .rst_ni (rst_ni),
16259
16260 // from register interface
16261 .we (ie0_5_we),
16262 .wd (ie0_5_e_175_wd),
16263
16264 // from internal hardware
16265 .de (1'b0),
16266 .d ('0),
16267
16268 // to internal hardware
16269 .qe (),
16270 .q (reg2hw.ie0[175].q),
16271 .ds (),
16272
16273 // to register interface (read)
16274 .qs (ie0_5_e_175_qs)
16275 );
16276
16277 // F[e_176]: 16:16
16278 prim_subreg #(
16279 .DW (1),
16280 .SwAccess(prim_subreg_pkg::SwAccessRW),
16281 .RESVAL (1'h0),
16282 .Mubi (1'b0)
16283 ) u_ie0_5_e_176 (
16284 .clk_i (clk_i),
16285 .rst_ni (rst_ni),
16286
16287 // from register interface
16288 .we (ie0_5_we),
16289 .wd (ie0_5_e_176_wd),
16290
16291 // from internal hardware
16292 .de (1'b0),
16293 .d ('0),
16294
16295 // to internal hardware
16296 .qe (),
16297 .q (reg2hw.ie0[176].q),
16298 .ds (),
16299
16300 // to register interface (read)
16301 .qs (ie0_5_e_176_qs)
16302 );
16303
16304 // F[e_177]: 17:17
16305 prim_subreg #(
16306 .DW (1),
16307 .SwAccess(prim_subreg_pkg::SwAccessRW),
16308 .RESVAL (1'h0),
16309 .Mubi (1'b0)
16310 ) u_ie0_5_e_177 (
16311 .clk_i (clk_i),
16312 .rst_ni (rst_ni),
16313
16314 // from register interface
16315 .we (ie0_5_we),
16316 .wd (ie0_5_e_177_wd),
16317
16318 // from internal hardware
16319 .de (1'b0),
16320 .d ('0),
16321
16322 // to internal hardware
16323 .qe (),
16324 .q (reg2hw.ie0[177].q),
16325 .ds (),
16326
16327 // to register interface (read)
16328 .qs (ie0_5_e_177_qs)
16329 );
16330
16331 // F[e_178]: 18:18
16332 prim_subreg #(
16333 .DW (1),
16334 .SwAccess(prim_subreg_pkg::SwAccessRW),
16335 .RESVAL (1'h0),
16336 .Mubi (1'b0)
16337 ) u_ie0_5_e_178 (
16338 .clk_i (clk_i),
16339 .rst_ni (rst_ni),
16340
16341 // from register interface
16342 .we (ie0_5_we),
16343 .wd (ie0_5_e_178_wd),
16344
16345 // from internal hardware
16346 .de (1'b0),
16347 .d ('0),
16348
16349 // to internal hardware
16350 .qe (),
16351 .q (reg2hw.ie0[178].q),
16352 .ds (),
16353
16354 // to register interface (read)
16355 .qs (ie0_5_e_178_qs)
16356 );
16357
16358 // F[e_179]: 19:19
16359 prim_subreg #(
16360 .DW (1),
16361 .SwAccess(prim_subreg_pkg::SwAccessRW),
16362 .RESVAL (1'h0),
16363 .Mubi (1'b0)
16364 ) u_ie0_5_e_179 (
16365 .clk_i (clk_i),
16366 .rst_ni (rst_ni),
16367
16368 // from register interface
16369 .we (ie0_5_we),
16370 .wd (ie0_5_e_179_wd),
16371
16372 // from internal hardware
16373 .de (1'b0),
16374 .d ('0),
16375
16376 // to internal hardware
16377 .qe (),
16378 .q (reg2hw.ie0[179].q),
16379 .ds (),
16380
16381 // to register interface (read)
16382 .qs (ie0_5_e_179_qs)
16383 );
16384
16385 // F[e_180]: 20:20
16386 prim_subreg #(
16387 .DW (1),
16388 .SwAccess(prim_subreg_pkg::SwAccessRW),
16389 .RESVAL (1'h0),
16390 .Mubi (1'b0)
16391 ) u_ie0_5_e_180 (
16392 .clk_i (clk_i),
16393 .rst_ni (rst_ni),
16394
16395 // from register interface
16396 .we (ie0_5_we),
16397 .wd (ie0_5_e_180_wd),
16398
16399 // from internal hardware
16400 .de (1'b0),
16401 .d ('0),
16402
16403 // to internal hardware
16404 .qe (),
16405 .q (reg2hw.ie0[180].q),
16406 .ds (),
16407
16408 // to register interface (read)
16409 .qs (ie0_5_e_180_qs)
16410 );
16411
16412 // F[e_181]: 21:21
16413 prim_subreg #(
16414 .DW (1),
16415 .SwAccess(prim_subreg_pkg::SwAccessRW),
16416 .RESVAL (1'h0),
16417 .Mubi (1'b0)
16418 ) u_ie0_5_e_181 (
16419 .clk_i (clk_i),
16420 .rst_ni (rst_ni),
16421
16422 // from register interface
16423 .we (ie0_5_we),
16424 .wd (ie0_5_e_181_wd),
16425
16426 // from internal hardware
16427 .de (1'b0),
16428 .d ('0),
16429
16430 // to internal hardware
16431 .qe (),
16432 .q (reg2hw.ie0[181].q),
16433 .ds (),
16434
16435 // to register interface (read)
16436 .qs (ie0_5_e_181_qs)
16437 );
16438
16439 // F[e_182]: 22:22
16440 prim_subreg #(
16441 .DW (1),
16442 .SwAccess(prim_subreg_pkg::SwAccessRW),
16443 .RESVAL (1'h0),
16444 .Mubi (1'b0)
16445 ) u_ie0_5_e_182 (
16446 .clk_i (clk_i),
16447 .rst_ni (rst_ni),
16448
16449 // from register interface
16450 .we (ie0_5_we),
16451 .wd (ie0_5_e_182_wd),
16452
16453 // from internal hardware
16454 .de (1'b0),
16455 .d ('0),
16456
16457 // to internal hardware
16458 .qe (),
16459 .q (reg2hw.ie0[182].q),
16460 .ds (),
16461
16462 // to register interface (read)
16463 .qs (ie0_5_e_182_qs)
16464 );
16465
16466 // F[e_183]: 23:23
16467 prim_subreg #(
16468 .DW (1),
16469 .SwAccess(prim_subreg_pkg::SwAccessRW),
16470 .RESVAL (1'h0),
16471 .Mubi (1'b0)
16472 ) u_ie0_5_e_183 (
16473 .clk_i (clk_i),
16474 .rst_ni (rst_ni),
16475
16476 // from register interface
16477 .we (ie0_5_we),
16478 .wd (ie0_5_e_183_wd),
16479
16480 // from internal hardware
16481 .de (1'b0),
16482 .d ('0),
16483
16484 // to internal hardware
16485 .qe (),
16486 .q (reg2hw.ie0[183].q),
16487 .ds (),
16488
16489 // to register interface (read)
16490 .qs (ie0_5_e_183_qs)
16491 );
16492
16493 // F[e_184]: 24:24
16494 prim_subreg #(
16495 .DW (1),
16496 .SwAccess(prim_subreg_pkg::SwAccessRW),
16497 .RESVAL (1'h0),
16498 .Mubi (1'b0)
16499 ) u_ie0_5_e_184 (
16500 .clk_i (clk_i),
16501 .rst_ni (rst_ni),
16502
16503 // from register interface
16504 .we (ie0_5_we),
16505 .wd (ie0_5_e_184_wd),
16506
16507 // from internal hardware
16508 .de (1'b0),
16509 .d ('0),
16510
16511 // to internal hardware
16512 .qe (),
16513 .q (reg2hw.ie0[184].q),
16514 .ds (),
16515
16516 // to register interface (read)
16517 .qs (ie0_5_e_184_qs)
16518 );
16519
16520 // F[e_185]: 25:25
16521 prim_subreg #(
16522 .DW (1),
16523 .SwAccess(prim_subreg_pkg::SwAccessRW),
16524 .RESVAL (1'h0),
16525 .Mubi (1'b0)
16526 ) u_ie0_5_e_185 (
16527 .clk_i (clk_i),
16528 .rst_ni (rst_ni),
16529
16530 // from register interface
16531 .we (ie0_5_we),
16532 .wd (ie0_5_e_185_wd),
16533
16534 // from internal hardware
16535 .de (1'b0),
16536 .d ('0),
16537
16538 // to internal hardware
16539 .qe (),
16540 .q (reg2hw.ie0[185].q),
16541 .ds (),
16542
16543 // to register interface (read)
16544 .qs (ie0_5_e_185_qs)
16545 );
16546
16547
16548 // R[threshold0]: V(False)
16549 prim_subreg #(
16550 .DW (2),
16551 .SwAccess(prim_subreg_pkg::SwAccessRW),
16552 .RESVAL (2'h0),
16553 .Mubi (1'b0)
16554 ) u_threshold0 (
16555 .clk_i (clk_i),
16556 .rst_ni (rst_ni),
16557
16558 // from register interface
16559 .we (threshold0_we),
16560 .wd (threshold0_wd),
16561
16562 // from internal hardware
16563 .de (1'b0),
16564 .d ('0),
16565
16566 // to internal hardware
16567 .qe (),
16568 .q (reg2hw.threshold0.q),
16569 .ds (),
16570
16571 // to register interface (read)
16572 .qs (threshold0_qs)
16573 );
16574
16575
16576 // R[cc0]: V(True)
16577 logic cc0_qe;
16578 logic [0:0] cc0_flds_we;
16579 1/1 assign cc0_qe = &cc0_flds_we;
Tests: T4 T5 T6
16580 prim_subreg_ext #(
16581 .DW (8)
16582 ) u_cc0 (
16583 .re (cc0_re),
16584 .we (cc0_we),
16585 .wd (cc0_wd),
16586 .d (hw2reg.cc0.d),
16587 .qre (reg2hw.cc0.re),
16588 .qe (cc0_flds_we[0]),
16589 .q (reg2hw.cc0.q),
16590 .ds (),
16591 .qs (cc0_qs)
16592 );
16593 1/1 assign reg2hw.cc0.qe = cc0_qe;
Tests: T4 T5 T6
16594
16595
16596 // R[msip0]: V(False)
16597 prim_subreg #(
16598 .DW (1),
16599 .SwAccess(prim_subreg_pkg::SwAccessRW),
16600 .RESVAL (1'h0),
16601 .Mubi (1'b0)
16602 ) u_msip0 (
16603 .clk_i (clk_i),
16604 .rst_ni (rst_ni),
16605
16606 // from register interface
16607 .we (msip0_we),
16608 .wd (msip0_wd),
16609
16610 // from internal hardware
16611 .de (1'b0),
16612 .d ('0),
16613
16614 // to internal hardware
16615 .qe (),
16616 .q (reg2hw.msip0.q),
16617 .ds (),
16618
16619 // to register interface (read)
16620 .qs (msip0_qs)
16621 );
16622
16623
16624 // R[alert_test]: V(True)
16625 logic alert_test_qe;
16626 logic [0:0] alert_test_flds_we;
16627 1/1 assign alert_test_qe = &alert_test_flds_we;
Tests: T80 T81 T82
16628 prim_subreg_ext #(
16629 .DW (1)
16630 ) u_alert_test (
16631 .re (1'b0),
16632 .we (alert_test_we),
16633 .wd (alert_test_wd),
16634 .d ('0),
16635 .qre (),
16636 .qe (alert_test_flds_we[0]),
16637 .q (reg2hw.alert_test.q),
16638 .ds (),
16639 .qs ()
16640 );
16641 1/1 assign reg2hw.alert_test.qe = alert_test_qe;
Tests: T80 T81 T82
16642
16643
16644
16645 logic [201:0] addr_hit;
16646 always_comb begin
16647 1/1 addr_hit = '0;
Tests: T2 T4 T5
16648 1/1 addr_hit[ 0] = (reg_addr == RV_PLIC_PRIO0_OFFSET);
Tests: T2 T4 T5
16649 1/1 addr_hit[ 1] = (reg_addr == RV_PLIC_PRIO1_OFFSET);
Tests: T2 T4 T5
16650 1/1 addr_hit[ 2] = (reg_addr == RV_PLIC_PRIO2_OFFSET);
Tests: T2 T4 T5
16651 1/1 addr_hit[ 3] = (reg_addr == RV_PLIC_PRIO3_OFFSET);
Tests: T2 T4 T5
16652 1/1 addr_hit[ 4] = (reg_addr == RV_PLIC_PRIO4_OFFSET);
Tests: T2 T4 T5
16653 1/1 addr_hit[ 5] = (reg_addr == RV_PLIC_PRIO5_OFFSET);
Tests: T2 T4 T5
16654 1/1 addr_hit[ 6] = (reg_addr == RV_PLIC_PRIO6_OFFSET);
Tests: T2 T4 T5
16655 1/1 addr_hit[ 7] = (reg_addr == RV_PLIC_PRIO7_OFFSET);
Tests: T2 T4 T5
16656 1/1 addr_hit[ 8] = (reg_addr == RV_PLIC_PRIO8_OFFSET);
Tests: T2 T4 T5
16657 1/1 addr_hit[ 9] = (reg_addr == RV_PLIC_PRIO9_OFFSET);
Tests: T2 T4 T5
16658 1/1 addr_hit[ 10] = (reg_addr == RV_PLIC_PRIO10_OFFSET);
Tests: T2 T4 T5
16659 1/1 addr_hit[ 11] = (reg_addr == RV_PLIC_PRIO11_OFFSET);
Tests: T2 T4 T5
16660 1/1 addr_hit[ 12] = (reg_addr == RV_PLIC_PRIO12_OFFSET);
Tests: T2 T4 T5
16661 1/1 addr_hit[ 13] = (reg_addr == RV_PLIC_PRIO13_OFFSET);
Tests: T2 T4 T5
16662 1/1 addr_hit[ 14] = (reg_addr == RV_PLIC_PRIO14_OFFSET);
Tests: T2 T4 T5
16663 1/1 addr_hit[ 15] = (reg_addr == RV_PLIC_PRIO15_OFFSET);
Tests: T2 T4 T5
16664 1/1 addr_hit[ 16] = (reg_addr == RV_PLIC_PRIO16_OFFSET);
Tests: T2 T4 T5
16665 1/1 addr_hit[ 17] = (reg_addr == RV_PLIC_PRIO17_OFFSET);
Tests: T2 T4 T5
16666 1/1 addr_hit[ 18] = (reg_addr == RV_PLIC_PRIO18_OFFSET);
Tests: T2 T4 T5
16667 1/1 addr_hit[ 19] = (reg_addr == RV_PLIC_PRIO19_OFFSET);
Tests: T2 T4 T5
16668 1/1 addr_hit[ 20] = (reg_addr == RV_PLIC_PRIO20_OFFSET);
Tests: T2 T4 T5
16669 1/1 addr_hit[ 21] = (reg_addr == RV_PLIC_PRIO21_OFFSET);
Tests: T2 T4 T5
16670 1/1 addr_hit[ 22] = (reg_addr == RV_PLIC_PRIO22_OFFSET);
Tests: T2 T4 T5
16671 1/1 addr_hit[ 23] = (reg_addr == RV_PLIC_PRIO23_OFFSET);
Tests: T2 T4 T5
16672 1/1 addr_hit[ 24] = (reg_addr == RV_PLIC_PRIO24_OFFSET);
Tests: T2 T4 T5
16673 1/1 addr_hit[ 25] = (reg_addr == RV_PLIC_PRIO25_OFFSET);
Tests: T2 T4 T5
16674 1/1 addr_hit[ 26] = (reg_addr == RV_PLIC_PRIO26_OFFSET);
Tests: T2 T4 T5
16675 1/1 addr_hit[ 27] = (reg_addr == RV_PLIC_PRIO27_OFFSET);
Tests: T2 T4 T5
16676 1/1 addr_hit[ 28] = (reg_addr == RV_PLIC_PRIO28_OFFSET);
Tests: T2 T4 T5
16677 1/1 addr_hit[ 29] = (reg_addr == RV_PLIC_PRIO29_OFFSET);
Tests: T2 T4 T5
16678 1/1 addr_hit[ 30] = (reg_addr == RV_PLIC_PRIO30_OFFSET);
Tests: T2 T4 T5
16679 1/1 addr_hit[ 31] = (reg_addr == RV_PLIC_PRIO31_OFFSET);
Tests: T2 T4 T5
16680 1/1 addr_hit[ 32] = (reg_addr == RV_PLIC_PRIO32_OFFSET);
Tests: T2 T4 T5
16681 1/1 addr_hit[ 33] = (reg_addr == RV_PLIC_PRIO33_OFFSET);
Tests: T2 T4 T5
16682 1/1 addr_hit[ 34] = (reg_addr == RV_PLIC_PRIO34_OFFSET);
Tests: T2 T4 T5
16683 1/1 addr_hit[ 35] = (reg_addr == RV_PLIC_PRIO35_OFFSET);
Tests: T2 T4 T5
16684 1/1 addr_hit[ 36] = (reg_addr == RV_PLIC_PRIO36_OFFSET);
Tests: T2 T4 T5
16685 1/1 addr_hit[ 37] = (reg_addr == RV_PLIC_PRIO37_OFFSET);
Tests: T2 T4 T5
16686 1/1 addr_hit[ 38] = (reg_addr == RV_PLIC_PRIO38_OFFSET);
Tests: T2 T4 T5
16687 1/1 addr_hit[ 39] = (reg_addr == RV_PLIC_PRIO39_OFFSET);
Tests: T2 T4 T5
16688 1/1 addr_hit[ 40] = (reg_addr == RV_PLIC_PRIO40_OFFSET);
Tests: T2 T4 T5
16689 1/1 addr_hit[ 41] = (reg_addr == RV_PLIC_PRIO41_OFFSET);
Tests: T2 T4 T5
16690 1/1 addr_hit[ 42] = (reg_addr == RV_PLIC_PRIO42_OFFSET);
Tests: T2 T4 T5
16691 1/1 addr_hit[ 43] = (reg_addr == RV_PLIC_PRIO43_OFFSET);
Tests: T2 T4 T5
16692 1/1 addr_hit[ 44] = (reg_addr == RV_PLIC_PRIO44_OFFSET);
Tests: T2 T4 T5
16693 1/1 addr_hit[ 45] = (reg_addr == RV_PLIC_PRIO45_OFFSET);
Tests: T2 T4 T5
16694 1/1 addr_hit[ 46] = (reg_addr == RV_PLIC_PRIO46_OFFSET);
Tests: T2 T4 T5
16695 1/1 addr_hit[ 47] = (reg_addr == RV_PLIC_PRIO47_OFFSET);
Tests: T2 T4 T5
16696 1/1 addr_hit[ 48] = (reg_addr == RV_PLIC_PRIO48_OFFSET);
Tests: T2 T4 T5
16697 1/1 addr_hit[ 49] = (reg_addr == RV_PLIC_PRIO49_OFFSET);
Tests: T2 T4 T5
16698 1/1 addr_hit[ 50] = (reg_addr == RV_PLIC_PRIO50_OFFSET);
Tests: T2 T4 T5
16699 1/1 addr_hit[ 51] = (reg_addr == RV_PLIC_PRIO51_OFFSET);
Tests: T2 T4 T5
16700 1/1 addr_hit[ 52] = (reg_addr == RV_PLIC_PRIO52_OFFSET);
Tests: T2 T4 T5
16701 1/1 addr_hit[ 53] = (reg_addr == RV_PLIC_PRIO53_OFFSET);
Tests: T2 T4 T5
16702 1/1 addr_hit[ 54] = (reg_addr == RV_PLIC_PRIO54_OFFSET);
Tests: T2 T4 T5
16703 1/1 addr_hit[ 55] = (reg_addr == RV_PLIC_PRIO55_OFFSET);
Tests: T2 T4 T5
16704 1/1 addr_hit[ 56] = (reg_addr == RV_PLIC_PRIO56_OFFSET);
Tests: T2 T4 T5
16705 1/1 addr_hit[ 57] = (reg_addr == RV_PLIC_PRIO57_OFFSET);
Tests: T2 T4 T5
16706 1/1 addr_hit[ 58] = (reg_addr == RV_PLIC_PRIO58_OFFSET);
Tests: T2 T4 T5
16707 1/1 addr_hit[ 59] = (reg_addr == RV_PLIC_PRIO59_OFFSET);
Tests: T2 T4 T5
16708 1/1 addr_hit[ 60] = (reg_addr == RV_PLIC_PRIO60_OFFSET);
Tests: T2 T4 T5
16709 1/1 addr_hit[ 61] = (reg_addr == RV_PLIC_PRIO61_OFFSET);
Tests: T2 T4 T5
16710 1/1 addr_hit[ 62] = (reg_addr == RV_PLIC_PRIO62_OFFSET);
Tests: T2 T4 T5
16711 1/1 addr_hit[ 63] = (reg_addr == RV_PLIC_PRIO63_OFFSET);
Tests: T2 T4 T5
16712 1/1 addr_hit[ 64] = (reg_addr == RV_PLIC_PRIO64_OFFSET);
Tests: T2 T4 T5
16713 1/1 addr_hit[ 65] = (reg_addr == RV_PLIC_PRIO65_OFFSET);
Tests: T2 T4 T5
16714 1/1 addr_hit[ 66] = (reg_addr == RV_PLIC_PRIO66_OFFSET);
Tests: T2 T4 T5
16715 1/1 addr_hit[ 67] = (reg_addr == RV_PLIC_PRIO67_OFFSET);
Tests: T2 T4 T5
16716 1/1 addr_hit[ 68] = (reg_addr == RV_PLIC_PRIO68_OFFSET);
Tests: T2 T4 T5
16717 1/1 addr_hit[ 69] = (reg_addr == RV_PLIC_PRIO69_OFFSET);
Tests: T2 T4 T5
16718 1/1 addr_hit[ 70] = (reg_addr == RV_PLIC_PRIO70_OFFSET);
Tests: T2 T4 T5
16719 1/1 addr_hit[ 71] = (reg_addr == RV_PLIC_PRIO71_OFFSET);
Tests: T2 T4 T5
16720 1/1 addr_hit[ 72] = (reg_addr == RV_PLIC_PRIO72_OFFSET);
Tests: T2 T4 T5
16721 1/1 addr_hit[ 73] = (reg_addr == RV_PLIC_PRIO73_OFFSET);
Tests: T2 T4 T5
16722 1/1 addr_hit[ 74] = (reg_addr == RV_PLIC_PRIO74_OFFSET);
Tests: T2 T4 T5
16723 1/1 addr_hit[ 75] = (reg_addr == RV_PLIC_PRIO75_OFFSET);
Tests: T2 T4 T5
16724 1/1 addr_hit[ 76] = (reg_addr == RV_PLIC_PRIO76_OFFSET);
Tests: T2 T4 T5
16725 1/1 addr_hit[ 77] = (reg_addr == RV_PLIC_PRIO77_OFFSET);
Tests: T2 T4 T5
16726 1/1 addr_hit[ 78] = (reg_addr == RV_PLIC_PRIO78_OFFSET);
Tests: T2 T4 T5
16727 1/1 addr_hit[ 79] = (reg_addr == RV_PLIC_PRIO79_OFFSET);
Tests: T2 T4 T5
16728 1/1 addr_hit[ 80] = (reg_addr == RV_PLIC_PRIO80_OFFSET);
Tests: T2 T4 T5
16729 1/1 addr_hit[ 81] = (reg_addr == RV_PLIC_PRIO81_OFFSET);
Tests: T2 T4 T5
16730 1/1 addr_hit[ 82] = (reg_addr == RV_PLIC_PRIO82_OFFSET);
Tests: T2 T4 T5
16731 1/1 addr_hit[ 83] = (reg_addr == RV_PLIC_PRIO83_OFFSET);
Tests: T2 T4 T5
16732 1/1 addr_hit[ 84] = (reg_addr == RV_PLIC_PRIO84_OFFSET);
Tests: T2 T4 T5
16733 1/1 addr_hit[ 85] = (reg_addr == RV_PLIC_PRIO85_OFFSET);
Tests: T2 T4 T5
16734 1/1 addr_hit[ 86] = (reg_addr == RV_PLIC_PRIO86_OFFSET);
Tests: T2 T4 T5
16735 1/1 addr_hit[ 87] = (reg_addr == RV_PLIC_PRIO87_OFFSET);
Tests: T2 T4 T5
16736 1/1 addr_hit[ 88] = (reg_addr == RV_PLIC_PRIO88_OFFSET);
Tests: T2 T4 T5
16737 1/1 addr_hit[ 89] = (reg_addr == RV_PLIC_PRIO89_OFFSET);
Tests: T2 T4 T5
16738 1/1 addr_hit[ 90] = (reg_addr == RV_PLIC_PRIO90_OFFSET);
Tests: T2 T4 T5
16739 1/1 addr_hit[ 91] = (reg_addr == RV_PLIC_PRIO91_OFFSET);
Tests: T2 T4 T5
16740 1/1 addr_hit[ 92] = (reg_addr == RV_PLIC_PRIO92_OFFSET);
Tests: T2 T4 T5
16741 1/1 addr_hit[ 93] = (reg_addr == RV_PLIC_PRIO93_OFFSET);
Tests: T2 T4 T5
16742 1/1 addr_hit[ 94] = (reg_addr == RV_PLIC_PRIO94_OFFSET);
Tests: T2 T4 T5
16743 1/1 addr_hit[ 95] = (reg_addr == RV_PLIC_PRIO95_OFFSET);
Tests: T2 T4 T5
16744 1/1 addr_hit[ 96] = (reg_addr == RV_PLIC_PRIO96_OFFSET);
Tests: T2 T4 T5
16745 1/1 addr_hit[ 97] = (reg_addr == RV_PLIC_PRIO97_OFFSET);
Tests: T2 T4 T5
16746 1/1 addr_hit[ 98] = (reg_addr == RV_PLIC_PRIO98_OFFSET);
Tests: T2 T4 T5
16747 1/1 addr_hit[ 99] = (reg_addr == RV_PLIC_PRIO99_OFFSET);
Tests: T2 T4 T5
16748 1/1 addr_hit[100] = (reg_addr == RV_PLIC_PRIO100_OFFSET);
Tests: T2 T4 T5
16749 1/1 addr_hit[101] = (reg_addr == RV_PLIC_PRIO101_OFFSET);
Tests: T2 T4 T5
16750 1/1 addr_hit[102] = (reg_addr == RV_PLIC_PRIO102_OFFSET);
Tests: T2 T4 T5
16751 1/1 addr_hit[103] = (reg_addr == RV_PLIC_PRIO103_OFFSET);
Tests: T2 T4 T5
16752 1/1 addr_hit[104] = (reg_addr == RV_PLIC_PRIO104_OFFSET);
Tests: T2 T4 T5
16753 1/1 addr_hit[105] = (reg_addr == RV_PLIC_PRIO105_OFFSET);
Tests: T2 T4 T5
16754 1/1 addr_hit[106] = (reg_addr == RV_PLIC_PRIO106_OFFSET);
Tests: T2 T4 T5
16755 1/1 addr_hit[107] = (reg_addr == RV_PLIC_PRIO107_OFFSET);
Tests: T2 T4 T5
16756 1/1 addr_hit[108] = (reg_addr == RV_PLIC_PRIO108_OFFSET);
Tests: T2 T4 T5
16757 1/1 addr_hit[109] = (reg_addr == RV_PLIC_PRIO109_OFFSET);
Tests: T2 T4 T5
16758 1/1 addr_hit[110] = (reg_addr == RV_PLIC_PRIO110_OFFSET);
Tests: T2 T4 T5
16759 1/1 addr_hit[111] = (reg_addr == RV_PLIC_PRIO111_OFFSET);
Tests: T2 T4 T5
16760 1/1 addr_hit[112] = (reg_addr == RV_PLIC_PRIO112_OFFSET);
Tests: T2 T4 T5
16761 1/1 addr_hit[113] = (reg_addr == RV_PLIC_PRIO113_OFFSET);
Tests: T2 T4 T5
16762 1/1 addr_hit[114] = (reg_addr == RV_PLIC_PRIO114_OFFSET);
Tests: T2 T4 T5
16763 1/1 addr_hit[115] = (reg_addr == RV_PLIC_PRIO115_OFFSET);
Tests: T2 T4 T5
16764 1/1 addr_hit[116] = (reg_addr == RV_PLIC_PRIO116_OFFSET);
Tests: T2 T4 T5
16765 1/1 addr_hit[117] = (reg_addr == RV_PLIC_PRIO117_OFFSET);
Tests: T2 T4 T5
16766 1/1 addr_hit[118] = (reg_addr == RV_PLIC_PRIO118_OFFSET);
Tests: T2 T4 T5
16767 1/1 addr_hit[119] = (reg_addr == RV_PLIC_PRIO119_OFFSET);
Tests: T2 T4 T5
16768 1/1 addr_hit[120] = (reg_addr == RV_PLIC_PRIO120_OFFSET);
Tests: T2 T4 T5
16769 1/1 addr_hit[121] = (reg_addr == RV_PLIC_PRIO121_OFFSET);
Tests: T2 T4 T5
16770 1/1 addr_hit[122] = (reg_addr == RV_PLIC_PRIO122_OFFSET);
Tests: T2 T4 T5
16771 1/1 addr_hit[123] = (reg_addr == RV_PLIC_PRIO123_OFFSET);
Tests: T2 T4 T5
16772 1/1 addr_hit[124] = (reg_addr == RV_PLIC_PRIO124_OFFSET);
Tests: T2 T4 T5
16773 1/1 addr_hit[125] = (reg_addr == RV_PLIC_PRIO125_OFFSET);
Tests: T2 T4 T5
16774 1/1 addr_hit[126] = (reg_addr == RV_PLIC_PRIO126_OFFSET);
Tests: T2 T4 T5
16775 1/1 addr_hit[127] = (reg_addr == RV_PLIC_PRIO127_OFFSET);
Tests: T2 T4 T5
16776 1/1 addr_hit[128] = (reg_addr == RV_PLIC_PRIO128_OFFSET);
Tests: T2 T4 T5
16777 1/1 addr_hit[129] = (reg_addr == RV_PLIC_PRIO129_OFFSET);
Tests: T2 T4 T5
16778 1/1 addr_hit[130] = (reg_addr == RV_PLIC_PRIO130_OFFSET);
Tests: T2 T4 T5
16779 1/1 addr_hit[131] = (reg_addr == RV_PLIC_PRIO131_OFFSET);
Tests: T2 T4 T5
16780 1/1 addr_hit[132] = (reg_addr == RV_PLIC_PRIO132_OFFSET);
Tests: T2 T4 T5
16781 1/1 addr_hit[133] = (reg_addr == RV_PLIC_PRIO133_OFFSET);
Tests: T2 T4 T5
16782 1/1 addr_hit[134] = (reg_addr == RV_PLIC_PRIO134_OFFSET);
Tests: T2 T4 T5
16783 1/1 addr_hit[135] = (reg_addr == RV_PLIC_PRIO135_OFFSET);
Tests: T2 T4 T5
16784 1/1 addr_hit[136] = (reg_addr == RV_PLIC_PRIO136_OFFSET);
Tests: T2 T4 T5
16785 1/1 addr_hit[137] = (reg_addr == RV_PLIC_PRIO137_OFFSET);
Tests: T2 T4 T5
16786 1/1 addr_hit[138] = (reg_addr == RV_PLIC_PRIO138_OFFSET);
Tests: T2 T4 T5
16787 1/1 addr_hit[139] = (reg_addr == RV_PLIC_PRIO139_OFFSET);
Tests: T2 T4 T5
16788 1/1 addr_hit[140] = (reg_addr == RV_PLIC_PRIO140_OFFSET);
Tests: T2 T4 T5
16789 1/1 addr_hit[141] = (reg_addr == RV_PLIC_PRIO141_OFFSET);
Tests: T2 T4 T5
16790 1/1 addr_hit[142] = (reg_addr == RV_PLIC_PRIO142_OFFSET);
Tests: T2 T4 T5
16791 1/1 addr_hit[143] = (reg_addr == RV_PLIC_PRIO143_OFFSET);
Tests: T2 T4 T5
16792 1/1 addr_hit[144] = (reg_addr == RV_PLIC_PRIO144_OFFSET);
Tests: T2 T4 T5
16793 1/1 addr_hit[145] = (reg_addr == RV_PLIC_PRIO145_OFFSET);
Tests: T2 T4 T5
16794 1/1 addr_hit[146] = (reg_addr == RV_PLIC_PRIO146_OFFSET);
Tests: T2 T4 T5
16795 1/1 addr_hit[147] = (reg_addr == RV_PLIC_PRIO147_OFFSET);
Tests: T2 T4 T5
16796 1/1 addr_hit[148] = (reg_addr == RV_PLIC_PRIO148_OFFSET);
Tests: T2 T4 T5
16797 1/1 addr_hit[149] = (reg_addr == RV_PLIC_PRIO149_OFFSET);
Tests: T2 T4 T5
16798 1/1 addr_hit[150] = (reg_addr == RV_PLIC_PRIO150_OFFSET);
Tests: T2 T4 T5
16799 1/1 addr_hit[151] = (reg_addr == RV_PLIC_PRIO151_OFFSET);
Tests: T2 T4 T5
16800 1/1 addr_hit[152] = (reg_addr == RV_PLIC_PRIO152_OFFSET);
Tests: T2 T4 T5
16801 1/1 addr_hit[153] = (reg_addr == RV_PLIC_PRIO153_OFFSET);
Tests: T2 T4 T5
16802 1/1 addr_hit[154] = (reg_addr == RV_PLIC_PRIO154_OFFSET);
Tests: T2 T4 T5
16803 1/1 addr_hit[155] = (reg_addr == RV_PLIC_PRIO155_OFFSET);
Tests: T2 T4 T5
16804 1/1 addr_hit[156] = (reg_addr == RV_PLIC_PRIO156_OFFSET);
Tests: T2 T4 T5
16805 1/1 addr_hit[157] = (reg_addr == RV_PLIC_PRIO157_OFFSET);
Tests: T2 T4 T5
16806 1/1 addr_hit[158] = (reg_addr == RV_PLIC_PRIO158_OFFSET);
Tests: T2 T4 T5
16807 1/1 addr_hit[159] = (reg_addr == RV_PLIC_PRIO159_OFFSET);
Tests: T2 T4 T5
16808 1/1 addr_hit[160] = (reg_addr == RV_PLIC_PRIO160_OFFSET);
Tests: T2 T4 T5
16809 1/1 addr_hit[161] = (reg_addr == RV_PLIC_PRIO161_OFFSET);
Tests: T2 T4 T5
16810 1/1 addr_hit[162] = (reg_addr == RV_PLIC_PRIO162_OFFSET);
Tests: T2 T4 T5
16811 1/1 addr_hit[163] = (reg_addr == RV_PLIC_PRIO163_OFFSET);
Tests: T2 T4 T5
16812 1/1 addr_hit[164] = (reg_addr == RV_PLIC_PRIO164_OFFSET);
Tests: T2 T4 T5
16813 1/1 addr_hit[165] = (reg_addr == RV_PLIC_PRIO165_OFFSET);
Tests: T2 T4 T5
16814 1/1 addr_hit[166] = (reg_addr == RV_PLIC_PRIO166_OFFSET);
Tests: T2 T4 T5
16815 1/1 addr_hit[167] = (reg_addr == RV_PLIC_PRIO167_OFFSET);
Tests: T2 T4 T5
16816 1/1 addr_hit[168] = (reg_addr == RV_PLIC_PRIO168_OFFSET);
Tests: T2 T4 T5
16817 1/1 addr_hit[169] = (reg_addr == RV_PLIC_PRIO169_OFFSET);
Tests: T2 T4 T5
16818 1/1 addr_hit[170] = (reg_addr == RV_PLIC_PRIO170_OFFSET);
Tests: T2 T4 T5
16819 1/1 addr_hit[171] = (reg_addr == RV_PLIC_PRIO171_OFFSET);
Tests: T2 T4 T5
16820 1/1 addr_hit[172] = (reg_addr == RV_PLIC_PRIO172_OFFSET);
Tests: T2 T4 T5
16821 1/1 addr_hit[173] = (reg_addr == RV_PLIC_PRIO173_OFFSET);
Tests: T2 T4 T5
16822 1/1 addr_hit[174] = (reg_addr == RV_PLIC_PRIO174_OFFSET);
Tests: T2 T4 T5
16823 1/1 addr_hit[175] = (reg_addr == RV_PLIC_PRIO175_OFFSET);
Tests: T2 T4 T5
16824 1/1 addr_hit[176] = (reg_addr == RV_PLIC_PRIO176_OFFSET);
Tests: T2 T4 T5
16825 1/1 addr_hit[177] = (reg_addr == RV_PLIC_PRIO177_OFFSET);
Tests: T2 T4 T5
16826 1/1 addr_hit[178] = (reg_addr == RV_PLIC_PRIO178_OFFSET);
Tests: T2 T4 T5
16827 1/1 addr_hit[179] = (reg_addr == RV_PLIC_PRIO179_OFFSET);
Tests: T2 T4 T5
16828 1/1 addr_hit[180] = (reg_addr == RV_PLIC_PRIO180_OFFSET);
Tests: T2 T4 T5
16829 1/1 addr_hit[181] = (reg_addr == RV_PLIC_PRIO181_OFFSET);
Tests: T2 T4 T5
16830 1/1 addr_hit[182] = (reg_addr == RV_PLIC_PRIO182_OFFSET);
Tests: T2 T4 T5
16831 1/1 addr_hit[183] = (reg_addr == RV_PLIC_PRIO183_OFFSET);
Tests: T2 T4 T5
16832 1/1 addr_hit[184] = (reg_addr == RV_PLIC_PRIO184_OFFSET);
Tests: T2 T4 T5
16833 1/1 addr_hit[185] = (reg_addr == RV_PLIC_PRIO185_OFFSET);
Tests: T2 T4 T5
16834 1/1 addr_hit[186] = (reg_addr == RV_PLIC_IP_0_OFFSET);
Tests: T2 T4 T5
16835 1/1 addr_hit[187] = (reg_addr == RV_PLIC_IP_1_OFFSET);
Tests: T2 T4 T5
16836 1/1 addr_hit[188] = (reg_addr == RV_PLIC_IP_2_OFFSET);
Tests: T2 T4 T5
16837 1/1 addr_hit[189] = (reg_addr == RV_PLIC_IP_3_OFFSET);
Tests: T2 T4 T5
16838 1/1 addr_hit[190] = (reg_addr == RV_PLIC_IP_4_OFFSET);
Tests: T2 T4 T5
16839 1/1 addr_hit[191] = (reg_addr == RV_PLIC_IP_5_OFFSET);
Tests: T2 T4 T5
16840 1/1 addr_hit[192] = (reg_addr == RV_PLIC_IE0_0_OFFSET);
Tests: T2 T4 T5
16841 1/1 addr_hit[193] = (reg_addr == RV_PLIC_IE0_1_OFFSET);
Tests: T2 T4 T5
16842 1/1 addr_hit[194] = (reg_addr == RV_PLIC_IE0_2_OFFSET);
Tests: T2 T4 T5
16843 1/1 addr_hit[195] = (reg_addr == RV_PLIC_IE0_3_OFFSET);
Tests: T2 T4 T5
16844 1/1 addr_hit[196] = (reg_addr == RV_PLIC_IE0_4_OFFSET);
Tests: T2 T4 T5
16845 1/1 addr_hit[197] = (reg_addr == RV_PLIC_IE0_5_OFFSET);
Tests: T2 T4 T5
16846 1/1 addr_hit[198] = (reg_addr == RV_PLIC_THRESHOLD0_OFFSET);
Tests: T2 T4 T5
16847 1/1 addr_hit[199] = (reg_addr == RV_PLIC_CC0_OFFSET);
Tests: T2 T4 T5
16848 1/1 addr_hit[200] = (reg_addr == RV_PLIC_MSIP0_OFFSET);
Tests: T2 T4 T5
16849 1/1 addr_hit[201] = (reg_addr == RV_PLIC_ALERT_TEST_OFFSET);
Tests: T2 T4 T5
16850 end
16851
16852 1/1 assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
Tests: T2 T4 T5
16853
16854 // Check sub-word write is permitted
16855 always_comb begin
16856 1/1 wr_err = (reg_we &
Tests: T2 T4 T5
16857 ((addr_hit[ 0] & (|(RV_PLIC_PERMIT[ 0] & ~reg_be))) |
16858 (addr_hit[ 1] & (|(RV_PLIC_PERMIT[ 1] & ~reg_be))) |
16859 (addr_hit[ 2] & (|(RV_PLIC_PERMIT[ 2] & ~reg_be))) |
16860 (addr_hit[ 3] & (|(RV_PLIC_PERMIT[ 3] & ~reg_be))) |
16861 (addr_hit[ 4] & (|(RV_PLIC_PERMIT[ 4] & ~reg_be))) |
16862 (addr_hit[ 5] & (|(RV_PLIC_PERMIT[ 5] & ~reg_be))) |
16863 (addr_hit[ 6] & (|(RV_PLIC_PERMIT[ 6] & ~reg_be))) |
16864 (addr_hit[ 7] & (|(RV_PLIC_PERMIT[ 7] & ~reg_be))) |
16865 (addr_hit[ 8] & (|(RV_PLIC_PERMIT[ 8] & ~reg_be))) |
16866 (addr_hit[ 9] & (|(RV_PLIC_PERMIT[ 9] & ~reg_be))) |
16867 (addr_hit[ 10] & (|(RV_PLIC_PERMIT[ 10] & ~reg_be))) |
16868 (addr_hit[ 11] & (|(RV_PLIC_PERMIT[ 11] & ~reg_be))) |
16869 (addr_hit[ 12] & (|(RV_PLIC_PERMIT[ 12] & ~reg_be))) |
16870 (addr_hit[ 13] & (|(RV_PLIC_PERMIT[ 13] & ~reg_be))) |
16871 (addr_hit[ 14] & (|(RV_PLIC_PERMIT[ 14] & ~reg_be))) |
16872 (addr_hit[ 15] & (|(RV_PLIC_PERMIT[ 15] & ~reg_be))) |
16873 (addr_hit[ 16] & (|(RV_PLIC_PERMIT[ 16] & ~reg_be))) |
16874 (addr_hit[ 17] & (|(RV_PLIC_PERMIT[ 17] & ~reg_be))) |
16875 (addr_hit[ 18] & (|(RV_PLIC_PERMIT[ 18] & ~reg_be))) |
16876 (addr_hit[ 19] & (|(RV_PLIC_PERMIT[ 19] & ~reg_be))) |
16877 (addr_hit[ 20] & (|(RV_PLIC_PERMIT[ 20] & ~reg_be))) |
16878 (addr_hit[ 21] & (|(RV_PLIC_PERMIT[ 21] & ~reg_be))) |
16879 (addr_hit[ 22] & (|(RV_PLIC_PERMIT[ 22] & ~reg_be))) |
16880 (addr_hit[ 23] & (|(RV_PLIC_PERMIT[ 23] & ~reg_be))) |
16881 (addr_hit[ 24] & (|(RV_PLIC_PERMIT[ 24] & ~reg_be))) |
16882 (addr_hit[ 25] & (|(RV_PLIC_PERMIT[ 25] & ~reg_be))) |
16883 (addr_hit[ 26] & (|(RV_PLIC_PERMIT[ 26] & ~reg_be))) |
16884 (addr_hit[ 27] & (|(RV_PLIC_PERMIT[ 27] & ~reg_be))) |
16885 (addr_hit[ 28] & (|(RV_PLIC_PERMIT[ 28] & ~reg_be))) |
16886 (addr_hit[ 29] & (|(RV_PLIC_PERMIT[ 29] & ~reg_be))) |
16887 (addr_hit[ 30] & (|(RV_PLIC_PERMIT[ 30] & ~reg_be))) |
16888 (addr_hit[ 31] & (|(RV_PLIC_PERMIT[ 31] & ~reg_be))) |
16889 (addr_hit[ 32] & (|(RV_PLIC_PERMIT[ 32] & ~reg_be))) |
16890 (addr_hit[ 33] & (|(RV_PLIC_PERMIT[ 33] & ~reg_be))) |
16891 (addr_hit[ 34] & (|(RV_PLIC_PERMIT[ 34] & ~reg_be))) |
16892 (addr_hit[ 35] & (|(RV_PLIC_PERMIT[ 35] & ~reg_be))) |
16893 (addr_hit[ 36] & (|(RV_PLIC_PERMIT[ 36] & ~reg_be))) |
16894 (addr_hit[ 37] & (|(RV_PLIC_PERMIT[ 37] & ~reg_be))) |
16895 (addr_hit[ 38] & (|(RV_PLIC_PERMIT[ 38] & ~reg_be))) |
16896 (addr_hit[ 39] & (|(RV_PLIC_PERMIT[ 39] & ~reg_be))) |
16897 (addr_hit[ 40] & (|(RV_PLIC_PERMIT[ 40] & ~reg_be))) |
16898 (addr_hit[ 41] & (|(RV_PLIC_PERMIT[ 41] & ~reg_be))) |
16899 (addr_hit[ 42] & (|(RV_PLIC_PERMIT[ 42] & ~reg_be))) |
16900 (addr_hit[ 43] & (|(RV_PLIC_PERMIT[ 43] & ~reg_be))) |
16901 (addr_hit[ 44] & (|(RV_PLIC_PERMIT[ 44] & ~reg_be))) |
16902 (addr_hit[ 45] & (|(RV_PLIC_PERMIT[ 45] & ~reg_be))) |
16903 (addr_hit[ 46] & (|(RV_PLIC_PERMIT[ 46] & ~reg_be))) |
16904 (addr_hit[ 47] & (|(RV_PLIC_PERMIT[ 47] & ~reg_be))) |
16905 (addr_hit[ 48] & (|(RV_PLIC_PERMIT[ 48] & ~reg_be))) |
16906 (addr_hit[ 49] & (|(RV_PLIC_PERMIT[ 49] & ~reg_be))) |
16907 (addr_hit[ 50] & (|(RV_PLIC_PERMIT[ 50] & ~reg_be))) |
16908 (addr_hit[ 51] & (|(RV_PLIC_PERMIT[ 51] & ~reg_be))) |
16909 (addr_hit[ 52] & (|(RV_PLIC_PERMIT[ 52] & ~reg_be))) |
16910 (addr_hit[ 53] & (|(RV_PLIC_PERMIT[ 53] & ~reg_be))) |
16911 (addr_hit[ 54] & (|(RV_PLIC_PERMIT[ 54] & ~reg_be))) |
16912 (addr_hit[ 55] & (|(RV_PLIC_PERMIT[ 55] & ~reg_be))) |
16913 (addr_hit[ 56] & (|(RV_PLIC_PERMIT[ 56] & ~reg_be))) |
16914 (addr_hit[ 57] & (|(RV_PLIC_PERMIT[ 57] & ~reg_be))) |
16915 (addr_hit[ 58] & (|(RV_PLIC_PERMIT[ 58] & ~reg_be))) |
16916 (addr_hit[ 59] & (|(RV_PLIC_PERMIT[ 59] & ~reg_be))) |
16917 (addr_hit[ 60] & (|(RV_PLIC_PERMIT[ 60] & ~reg_be))) |
16918 (addr_hit[ 61] & (|(RV_PLIC_PERMIT[ 61] & ~reg_be))) |
16919 (addr_hit[ 62] & (|(RV_PLIC_PERMIT[ 62] & ~reg_be))) |
16920 (addr_hit[ 63] & (|(RV_PLIC_PERMIT[ 63] & ~reg_be))) |
16921 (addr_hit[ 64] & (|(RV_PLIC_PERMIT[ 64] & ~reg_be))) |
16922 (addr_hit[ 65] & (|(RV_PLIC_PERMIT[ 65] & ~reg_be))) |
16923 (addr_hit[ 66] & (|(RV_PLIC_PERMIT[ 66] & ~reg_be))) |
16924 (addr_hit[ 67] & (|(RV_PLIC_PERMIT[ 67] & ~reg_be))) |
16925 (addr_hit[ 68] & (|(RV_PLIC_PERMIT[ 68] & ~reg_be))) |
16926 (addr_hit[ 69] & (|(RV_PLIC_PERMIT[ 69] & ~reg_be))) |
16927 (addr_hit[ 70] & (|(RV_PLIC_PERMIT[ 70] & ~reg_be))) |
16928 (addr_hit[ 71] & (|(RV_PLIC_PERMIT[ 71] & ~reg_be))) |
16929 (addr_hit[ 72] & (|(RV_PLIC_PERMIT[ 72] & ~reg_be))) |
16930 (addr_hit[ 73] & (|(RV_PLIC_PERMIT[ 73] & ~reg_be))) |
16931 (addr_hit[ 74] & (|(RV_PLIC_PERMIT[ 74] & ~reg_be))) |
16932 (addr_hit[ 75] & (|(RV_PLIC_PERMIT[ 75] & ~reg_be))) |
16933 (addr_hit[ 76] & (|(RV_PLIC_PERMIT[ 76] & ~reg_be))) |
16934 (addr_hit[ 77] & (|(RV_PLIC_PERMIT[ 77] & ~reg_be))) |
16935 (addr_hit[ 78] & (|(RV_PLIC_PERMIT[ 78] & ~reg_be))) |
16936 (addr_hit[ 79] & (|(RV_PLIC_PERMIT[ 79] & ~reg_be))) |
16937 (addr_hit[ 80] & (|(RV_PLIC_PERMIT[ 80] & ~reg_be))) |
16938 (addr_hit[ 81] & (|(RV_PLIC_PERMIT[ 81] & ~reg_be))) |
16939 (addr_hit[ 82] & (|(RV_PLIC_PERMIT[ 82] & ~reg_be))) |
16940 (addr_hit[ 83] & (|(RV_PLIC_PERMIT[ 83] & ~reg_be))) |
16941 (addr_hit[ 84] & (|(RV_PLIC_PERMIT[ 84] & ~reg_be))) |
16942 (addr_hit[ 85] & (|(RV_PLIC_PERMIT[ 85] & ~reg_be))) |
16943 (addr_hit[ 86] & (|(RV_PLIC_PERMIT[ 86] & ~reg_be))) |
16944 (addr_hit[ 87] & (|(RV_PLIC_PERMIT[ 87] & ~reg_be))) |
16945 (addr_hit[ 88] & (|(RV_PLIC_PERMIT[ 88] & ~reg_be))) |
16946 (addr_hit[ 89] & (|(RV_PLIC_PERMIT[ 89] & ~reg_be))) |
16947 (addr_hit[ 90] & (|(RV_PLIC_PERMIT[ 90] & ~reg_be))) |
16948 (addr_hit[ 91] & (|(RV_PLIC_PERMIT[ 91] & ~reg_be))) |
16949 (addr_hit[ 92] & (|(RV_PLIC_PERMIT[ 92] & ~reg_be))) |
16950 (addr_hit[ 93] & (|(RV_PLIC_PERMIT[ 93] & ~reg_be))) |
16951 (addr_hit[ 94] & (|(RV_PLIC_PERMIT[ 94] & ~reg_be))) |
16952 (addr_hit[ 95] & (|(RV_PLIC_PERMIT[ 95] & ~reg_be))) |
16953 (addr_hit[ 96] & (|(RV_PLIC_PERMIT[ 96] & ~reg_be))) |
16954 (addr_hit[ 97] & (|(RV_PLIC_PERMIT[ 97] & ~reg_be))) |
16955 (addr_hit[ 98] & (|(RV_PLIC_PERMIT[ 98] & ~reg_be))) |
16956 (addr_hit[ 99] & (|(RV_PLIC_PERMIT[ 99] & ~reg_be))) |
16957 (addr_hit[100] & (|(RV_PLIC_PERMIT[100] & ~reg_be))) |
16958 (addr_hit[101] & (|(RV_PLIC_PERMIT[101] & ~reg_be))) |
16959 (addr_hit[102] & (|(RV_PLIC_PERMIT[102] & ~reg_be))) |
16960 (addr_hit[103] & (|(RV_PLIC_PERMIT[103] & ~reg_be))) |
16961 (addr_hit[104] & (|(RV_PLIC_PERMIT[104] & ~reg_be))) |
16962 (addr_hit[105] & (|(RV_PLIC_PERMIT[105] & ~reg_be))) |
16963 (addr_hit[106] & (|(RV_PLIC_PERMIT[106] & ~reg_be))) |
16964 (addr_hit[107] & (|(RV_PLIC_PERMIT[107] & ~reg_be))) |
16965 (addr_hit[108] & (|(RV_PLIC_PERMIT[108] & ~reg_be))) |
16966 (addr_hit[109] & (|(RV_PLIC_PERMIT[109] & ~reg_be))) |
16967 (addr_hit[110] & (|(RV_PLIC_PERMIT[110] & ~reg_be))) |
16968 (addr_hit[111] & (|(RV_PLIC_PERMIT[111] & ~reg_be))) |
16969 (addr_hit[112] & (|(RV_PLIC_PERMIT[112] & ~reg_be))) |
16970 (addr_hit[113] & (|(RV_PLIC_PERMIT[113] & ~reg_be))) |
16971 (addr_hit[114] & (|(RV_PLIC_PERMIT[114] & ~reg_be))) |
16972 (addr_hit[115] & (|(RV_PLIC_PERMIT[115] & ~reg_be))) |
16973 (addr_hit[116] & (|(RV_PLIC_PERMIT[116] & ~reg_be))) |
16974 (addr_hit[117] & (|(RV_PLIC_PERMIT[117] & ~reg_be))) |
16975 (addr_hit[118] & (|(RV_PLIC_PERMIT[118] & ~reg_be))) |
16976 (addr_hit[119] & (|(RV_PLIC_PERMIT[119] & ~reg_be))) |
16977 (addr_hit[120] & (|(RV_PLIC_PERMIT[120] & ~reg_be))) |
16978 (addr_hit[121] & (|(RV_PLIC_PERMIT[121] & ~reg_be))) |
16979 (addr_hit[122] & (|(RV_PLIC_PERMIT[122] & ~reg_be))) |
16980 (addr_hit[123] & (|(RV_PLIC_PERMIT[123] & ~reg_be))) |
16981 (addr_hit[124] & (|(RV_PLIC_PERMIT[124] & ~reg_be))) |
16982 (addr_hit[125] & (|(RV_PLIC_PERMIT[125] & ~reg_be))) |
16983 (addr_hit[126] & (|(RV_PLIC_PERMIT[126] & ~reg_be))) |
16984 (addr_hit[127] & (|(RV_PLIC_PERMIT[127] & ~reg_be))) |
16985 (addr_hit[128] & (|(RV_PLIC_PERMIT[128] & ~reg_be))) |
16986 (addr_hit[129] & (|(RV_PLIC_PERMIT[129] & ~reg_be))) |
16987 (addr_hit[130] & (|(RV_PLIC_PERMIT[130] & ~reg_be))) |
16988 (addr_hit[131] & (|(RV_PLIC_PERMIT[131] & ~reg_be))) |
16989 (addr_hit[132] & (|(RV_PLIC_PERMIT[132] & ~reg_be))) |
16990 (addr_hit[133] & (|(RV_PLIC_PERMIT[133] & ~reg_be))) |
16991 (addr_hit[134] & (|(RV_PLIC_PERMIT[134] & ~reg_be))) |
16992 (addr_hit[135] & (|(RV_PLIC_PERMIT[135] & ~reg_be))) |
16993 (addr_hit[136] & (|(RV_PLIC_PERMIT[136] & ~reg_be))) |
16994 (addr_hit[137] & (|(RV_PLIC_PERMIT[137] & ~reg_be))) |
16995 (addr_hit[138] & (|(RV_PLIC_PERMIT[138] & ~reg_be))) |
16996 (addr_hit[139] & (|(RV_PLIC_PERMIT[139] & ~reg_be))) |
16997 (addr_hit[140] & (|(RV_PLIC_PERMIT[140] & ~reg_be))) |
16998 (addr_hit[141] & (|(RV_PLIC_PERMIT[141] & ~reg_be))) |
16999 (addr_hit[142] & (|(RV_PLIC_PERMIT[142] & ~reg_be))) |
17000 (addr_hit[143] & (|(RV_PLIC_PERMIT[143] & ~reg_be))) |
17001 (addr_hit[144] & (|(RV_PLIC_PERMIT[144] & ~reg_be))) |
17002 (addr_hit[145] & (|(RV_PLIC_PERMIT[145] & ~reg_be))) |
17003 (addr_hit[146] & (|(RV_PLIC_PERMIT[146] & ~reg_be))) |
17004 (addr_hit[147] & (|(RV_PLIC_PERMIT[147] & ~reg_be))) |
17005 (addr_hit[148] & (|(RV_PLIC_PERMIT[148] & ~reg_be))) |
17006 (addr_hit[149] & (|(RV_PLIC_PERMIT[149] & ~reg_be))) |
17007 (addr_hit[150] & (|(RV_PLIC_PERMIT[150] & ~reg_be))) |
17008 (addr_hit[151] & (|(RV_PLIC_PERMIT[151] & ~reg_be))) |
17009 (addr_hit[152] & (|(RV_PLIC_PERMIT[152] & ~reg_be))) |
17010 (addr_hit[153] & (|(RV_PLIC_PERMIT[153] & ~reg_be))) |
17011 (addr_hit[154] & (|(RV_PLIC_PERMIT[154] & ~reg_be))) |
17012 (addr_hit[155] & (|(RV_PLIC_PERMIT[155] & ~reg_be))) |
17013 (addr_hit[156] & (|(RV_PLIC_PERMIT[156] & ~reg_be))) |
17014 (addr_hit[157] & (|(RV_PLIC_PERMIT[157] & ~reg_be))) |
17015 (addr_hit[158] & (|(RV_PLIC_PERMIT[158] & ~reg_be))) |
17016 (addr_hit[159] & (|(RV_PLIC_PERMIT[159] & ~reg_be))) |
17017 (addr_hit[160] & (|(RV_PLIC_PERMIT[160] & ~reg_be))) |
17018 (addr_hit[161] & (|(RV_PLIC_PERMIT[161] & ~reg_be))) |
17019 (addr_hit[162] & (|(RV_PLIC_PERMIT[162] & ~reg_be))) |
17020 (addr_hit[163] & (|(RV_PLIC_PERMIT[163] & ~reg_be))) |
17021 (addr_hit[164] & (|(RV_PLIC_PERMIT[164] & ~reg_be))) |
17022 (addr_hit[165] & (|(RV_PLIC_PERMIT[165] & ~reg_be))) |
17023 (addr_hit[166] & (|(RV_PLIC_PERMIT[166] & ~reg_be))) |
17024 (addr_hit[167] & (|(RV_PLIC_PERMIT[167] & ~reg_be))) |
17025 (addr_hit[168] & (|(RV_PLIC_PERMIT[168] & ~reg_be))) |
17026 (addr_hit[169] & (|(RV_PLIC_PERMIT[169] & ~reg_be))) |
17027 (addr_hit[170] & (|(RV_PLIC_PERMIT[170] & ~reg_be))) |
17028 (addr_hit[171] & (|(RV_PLIC_PERMIT[171] & ~reg_be))) |
17029 (addr_hit[172] & (|(RV_PLIC_PERMIT[172] & ~reg_be))) |
17030 (addr_hit[173] & (|(RV_PLIC_PERMIT[173] & ~reg_be))) |
17031 (addr_hit[174] & (|(RV_PLIC_PERMIT[174] & ~reg_be))) |
17032 (addr_hit[175] & (|(RV_PLIC_PERMIT[175] & ~reg_be))) |
17033 (addr_hit[176] & (|(RV_PLIC_PERMIT[176] & ~reg_be))) |
17034 (addr_hit[177] & (|(RV_PLIC_PERMIT[177] & ~reg_be))) |
17035 (addr_hit[178] & (|(RV_PLIC_PERMIT[178] & ~reg_be))) |
17036 (addr_hit[179] & (|(RV_PLIC_PERMIT[179] & ~reg_be))) |
17037 (addr_hit[180] & (|(RV_PLIC_PERMIT[180] & ~reg_be))) |
17038 (addr_hit[181] & (|(RV_PLIC_PERMIT[181] & ~reg_be))) |
17039 (addr_hit[182] & (|(RV_PLIC_PERMIT[182] & ~reg_be))) |
17040 (addr_hit[183] & (|(RV_PLIC_PERMIT[183] & ~reg_be))) |
17041 (addr_hit[184] & (|(RV_PLIC_PERMIT[184] & ~reg_be))) |
17042 (addr_hit[185] & (|(RV_PLIC_PERMIT[185] & ~reg_be))) |
17043 (addr_hit[186] & (|(RV_PLIC_PERMIT[186] & ~reg_be))) |
17044 (addr_hit[187] & (|(RV_PLIC_PERMIT[187] & ~reg_be))) |
17045 (addr_hit[188] & (|(RV_PLIC_PERMIT[188] & ~reg_be))) |
17046 (addr_hit[189] & (|(RV_PLIC_PERMIT[189] & ~reg_be))) |
17047 (addr_hit[190] & (|(RV_PLIC_PERMIT[190] & ~reg_be))) |
17048 (addr_hit[191] & (|(RV_PLIC_PERMIT[191] & ~reg_be))) |
17049 (addr_hit[192] & (|(RV_PLIC_PERMIT[192] & ~reg_be))) |
17050 (addr_hit[193] & (|(RV_PLIC_PERMIT[193] & ~reg_be))) |
17051 (addr_hit[194] & (|(RV_PLIC_PERMIT[194] & ~reg_be))) |
17052 (addr_hit[195] & (|(RV_PLIC_PERMIT[195] & ~reg_be))) |
17053 (addr_hit[196] & (|(RV_PLIC_PERMIT[196] & ~reg_be))) |
17054 (addr_hit[197] & (|(RV_PLIC_PERMIT[197] & ~reg_be))) |
17055 (addr_hit[198] & (|(RV_PLIC_PERMIT[198] & ~reg_be))) |
17056 (addr_hit[199] & (|(RV_PLIC_PERMIT[199] & ~reg_be))) |
17057 (addr_hit[200] & (|(RV_PLIC_PERMIT[200] & ~reg_be))) |
17058 (addr_hit[201] & (|(RV_PLIC_PERMIT[201] & ~reg_be)))));
17059 end
17060
17061 // Generate write-enables
17062 1/1 assign prio0_we = addr_hit[0] & reg_we & !reg_error;
Tests: T2 T4 T5
17063
17064 1/1 assign prio0_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17065 1/1 assign prio1_we = addr_hit[1] & reg_we & !reg_error;
Tests: T2 T4 T5
17066
17067 1/1 assign prio1_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17068 1/1 assign prio2_we = addr_hit[2] & reg_we & !reg_error;
Tests: T2 T4 T5
17069
17070 1/1 assign prio2_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17071 1/1 assign prio3_we = addr_hit[3] & reg_we & !reg_error;
Tests: T2 T4 T5
17072
17073 1/1 assign prio3_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17074 1/1 assign prio4_we = addr_hit[4] & reg_we & !reg_error;
Tests: T2 T4 T5
17075
17076 1/1 assign prio4_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17077 1/1 assign prio5_we = addr_hit[5] & reg_we & !reg_error;
Tests: T2 T4 T5
17078
17079 1/1 assign prio5_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17080 1/1 assign prio6_we = addr_hit[6] & reg_we & !reg_error;
Tests: T2 T4 T5
17081
17082 1/1 assign prio6_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17083 1/1 assign prio7_we = addr_hit[7] & reg_we & !reg_error;
Tests: T2 T4 T5
17084
17085 1/1 assign prio7_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17086 1/1 assign prio8_we = addr_hit[8] & reg_we & !reg_error;
Tests: T2 T4 T5
17087
17088 1/1 assign prio8_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17089 1/1 assign prio9_we = addr_hit[9] & reg_we & !reg_error;
Tests: T2 T4 T5
17090
17091 1/1 assign prio9_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17092 1/1 assign prio10_we = addr_hit[10] & reg_we & !reg_error;
Tests: T2 T4 T5
17093
17094 1/1 assign prio10_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17095 1/1 assign prio11_we = addr_hit[11] & reg_we & !reg_error;
Tests: T2 T4 T5
17096
17097 1/1 assign prio11_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17098 1/1 assign prio12_we = addr_hit[12] & reg_we & !reg_error;
Tests: T2 T4 T5
17099
17100 1/1 assign prio12_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17101 1/1 assign prio13_we = addr_hit[13] & reg_we & !reg_error;
Tests: T2 T4 T5
17102
17103 1/1 assign prio13_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17104 1/1 assign prio14_we = addr_hit[14] & reg_we & !reg_error;
Tests: T2 T4 T5
17105
17106 1/1 assign prio14_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17107 1/1 assign prio15_we = addr_hit[15] & reg_we & !reg_error;
Tests: T2 T4 T5
17108
17109 1/1 assign prio15_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17110 1/1 assign prio16_we = addr_hit[16] & reg_we & !reg_error;
Tests: T2 T4 T5
17111
17112 1/1 assign prio16_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17113 1/1 assign prio17_we = addr_hit[17] & reg_we & !reg_error;
Tests: T2 T4 T5
17114
17115 1/1 assign prio17_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17116 1/1 assign prio18_we = addr_hit[18] & reg_we & !reg_error;
Tests: T2 T4 T5
17117
17118 1/1 assign prio18_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17119 1/1 assign prio19_we = addr_hit[19] & reg_we & !reg_error;
Tests: T2 T4 T5
17120
17121 1/1 assign prio19_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17122 1/1 assign prio20_we = addr_hit[20] & reg_we & !reg_error;
Tests: T2 T4 T5
17123
17124 1/1 assign prio20_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17125 1/1 assign prio21_we = addr_hit[21] & reg_we & !reg_error;
Tests: T2 T4 T5
17126
17127 1/1 assign prio21_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17128 1/1 assign prio22_we = addr_hit[22] & reg_we & !reg_error;
Tests: T2 T4 T5
17129
17130 1/1 assign prio22_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17131 1/1 assign prio23_we = addr_hit[23] & reg_we & !reg_error;
Tests: T2 T4 T5
17132
17133 1/1 assign prio23_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17134 1/1 assign prio24_we = addr_hit[24] & reg_we & !reg_error;
Tests: T2 T4 T5
17135
17136 1/1 assign prio24_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17137 1/1 assign prio25_we = addr_hit[25] & reg_we & !reg_error;
Tests: T2 T4 T5
17138
17139 1/1 assign prio25_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17140 1/1 assign prio26_we = addr_hit[26] & reg_we & !reg_error;
Tests: T2 T4 T5
17141
17142 1/1 assign prio26_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17143 1/1 assign prio27_we = addr_hit[27] & reg_we & !reg_error;
Tests: T2 T4 T5
17144
17145 1/1 assign prio27_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17146 1/1 assign prio28_we = addr_hit[28] & reg_we & !reg_error;
Tests: T2 T4 T5
17147
17148 1/1 assign prio28_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17149 1/1 assign prio29_we = addr_hit[29] & reg_we & !reg_error;
Tests: T2 T4 T5
17150
17151 1/1 assign prio29_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17152 1/1 assign prio30_we = addr_hit[30] & reg_we & !reg_error;
Tests: T2 T4 T5
17153
17154 1/1 assign prio30_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17155 1/1 assign prio31_we = addr_hit[31] & reg_we & !reg_error;
Tests: T2 T4 T5
17156
17157 1/1 assign prio31_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17158 1/1 assign prio32_we = addr_hit[32] & reg_we & !reg_error;
Tests: T2 T4 T5
17159
17160 1/1 assign prio32_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17161 1/1 assign prio33_we = addr_hit[33] & reg_we & !reg_error;
Tests: T2 T4 T5
17162
17163 1/1 assign prio33_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17164 1/1 assign prio34_we = addr_hit[34] & reg_we & !reg_error;
Tests: T2 T4 T5
17165
17166 1/1 assign prio34_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17167 1/1 assign prio35_we = addr_hit[35] & reg_we & !reg_error;
Tests: T2 T4 T5
17168
17169 1/1 assign prio35_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17170 1/1 assign prio36_we = addr_hit[36] & reg_we & !reg_error;
Tests: T2 T4 T5
17171
17172 1/1 assign prio36_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17173 1/1 assign prio37_we = addr_hit[37] & reg_we & !reg_error;
Tests: T2 T4 T5
17174
17175 1/1 assign prio37_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17176 1/1 assign prio38_we = addr_hit[38] & reg_we & !reg_error;
Tests: T2 T4 T5
17177
17178 1/1 assign prio38_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17179 1/1 assign prio39_we = addr_hit[39] & reg_we & !reg_error;
Tests: T2 T4 T5
17180
17181 1/1 assign prio39_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17182 1/1 assign prio40_we = addr_hit[40] & reg_we & !reg_error;
Tests: T2 T4 T5
17183
17184 1/1 assign prio40_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17185 1/1 assign prio41_we = addr_hit[41] & reg_we & !reg_error;
Tests: T2 T4 T5
17186
17187 1/1 assign prio41_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17188 1/1 assign prio42_we = addr_hit[42] & reg_we & !reg_error;
Tests: T2 T4 T5
17189
17190 1/1 assign prio42_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17191 1/1 assign prio43_we = addr_hit[43] & reg_we & !reg_error;
Tests: T2 T4 T5
17192
17193 1/1 assign prio43_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17194 1/1 assign prio44_we = addr_hit[44] & reg_we & !reg_error;
Tests: T2 T4 T5
17195
17196 1/1 assign prio44_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17197 1/1 assign prio45_we = addr_hit[45] & reg_we & !reg_error;
Tests: T2 T4 T5
17198
17199 1/1 assign prio45_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17200 1/1 assign prio46_we = addr_hit[46] & reg_we & !reg_error;
Tests: T2 T4 T5
17201
17202 1/1 assign prio46_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17203 1/1 assign prio47_we = addr_hit[47] & reg_we & !reg_error;
Tests: T2 T4 T5
17204
17205 1/1 assign prio47_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17206 1/1 assign prio48_we = addr_hit[48] & reg_we & !reg_error;
Tests: T2 T4 T5
17207
17208 1/1 assign prio48_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17209 1/1 assign prio49_we = addr_hit[49] & reg_we & !reg_error;
Tests: T2 T4 T5
17210
17211 1/1 assign prio49_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17212 1/1 assign prio50_we = addr_hit[50] & reg_we & !reg_error;
Tests: T2 T4 T5
17213
17214 1/1 assign prio50_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17215 1/1 assign prio51_we = addr_hit[51] & reg_we & !reg_error;
Tests: T2 T4 T5
17216
17217 1/1 assign prio51_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17218 1/1 assign prio52_we = addr_hit[52] & reg_we & !reg_error;
Tests: T2 T4 T5
17219
17220 1/1 assign prio52_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17221 1/1 assign prio53_we = addr_hit[53] & reg_we & !reg_error;
Tests: T2 T4 T5
17222
17223 1/1 assign prio53_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17224 1/1 assign prio54_we = addr_hit[54] & reg_we & !reg_error;
Tests: T2 T4 T5
17225
17226 1/1 assign prio54_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17227 1/1 assign prio55_we = addr_hit[55] & reg_we & !reg_error;
Tests: T2 T4 T5
17228
17229 1/1 assign prio55_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17230 1/1 assign prio56_we = addr_hit[56] & reg_we & !reg_error;
Tests: T2 T4 T5
17231
17232 1/1 assign prio56_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17233 1/1 assign prio57_we = addr_hit[57] & reg_we & !reg_error;
Tests: T2 T4 T5
17234
17235 1/1 assign prio57_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17236 1/1 assign prio58_we = addr_hit[58] & reg_we & !reg_error;
Tests: T2 T4 T5
17237
17238 1/1 assign prio58_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17239 1/1 assign prio59_we = addr_hit[59] & reg_we & !reg_error;
Tests: T2 T4 T5
17240
17241 1/1 assign prio59_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17242 1/1 assign prio60_we = addr_hit[60] & reg_we & !reg_error;
Tests: T2 T4 T5
17243
17244 1/1 assign prio60_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17245 1/1 assign prio61_we = addr_hit[61] & reg_we & !reg_error;
Tests: T2 T4 T5
17246
17247 1/1 assign prio61_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17248 1/1 assign prio62_we = addr_hit[62] & reg_we & !reg_error;
Tests: T2 T4 T5
17249
17250 1/1 assign prio62_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17251 1/1 assign prio63_we = addr_hit[63] & reg_we & !reg_error;
Tests: T2 T4 T5
17252
17253 1/1 assign prio63_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17254 1/1 assign prio64_we = addr_hit[64] & reg_we & !reg_error;
Tests: T2 T4 T5
17255
17256 1/1 assign prio64_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17257 1/1 assign prio65_we = addr_hit[65] & reg_we & !reg_error;
Tests: T2 T4 T5
17258
17259 1/1 assign prio65_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17260 1/1 assign prio66_we = addr_hit[66] & reg_we & !reg_error;
Tests: T2 T4 T5
17261
17262 1/1 assign prio66_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17263 1/1 assign prio67_we = addr_hit[67] & reg_we & !reg_error;
Tests: T2 T4 T5
17264
17265 1/1 assign prio67_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17266 1/1 assign prio68_we = addr_hit[68] & reg_we & !reg_error;
Tests: T2 T4 T5
17267
17268 1/1 assign prio68_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17269 1/1 assign prio69_we = addr_hit[69] & reg_we & !reg_error;
Tests: T2 T4 T5
17270
17271 1/1 assign prio69_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17272 1/1 assign prio70_we = addr_hit[70] & reg_we & !reg_error;
Tests: T2 T4 T5
17273
17274 1/1 assign prio70_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17275 1/1 assign prio71_we = addr_hit[71] & reg_we & !reg_error;
Tests: T2 T4 T5
17276
17277 1/1 assign prio71_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17278 1/1 assign prio72_we = addr_hit[72] & reg_we & !reg_error;
Tests: T2 T4 T5
17279
17280 1/1 assign prio72_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17281 1/1 assign prio73_we = addr_hit[73] & reg_we & !reg_error;
Tests: T2 T4 T5
17282
17283 1/1 assign prio73_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17284 1/1 assign prio74_we = addr_hit[74] & reg_we & !reg_error;
Tests: T2 T4 T5
17285
17286 1/1 assign prio74_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17287 1/1 assign prio75_we = addr_hit[75] & reg_we & !reg_error;
Tests: T2 T4 T5
17288
17289 1/1 assign prio75_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17290 1/1 assign prio76_we = addr_hit[76] & reg_we & !reg_error;
Tests: T2 T4 T5
17291
17292 1/1 assign prio76_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17293 1/1 assign prio77_we = addr_hit[77] & reg_we & !reg_error;
Tests: T2 T4 T5
17294
17295 1/1 assign prio77_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17296 1/1 assign prio78_we = addr_hit[78] & reg_we & !reg_error;
Tests: T2 T4 T5
17297
17298 1/1 assign prio78_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17299 1/1 assign prio79_we = addr_hit[79] & reg_we & !reg_error;
Tests: T2 T4 T5
17300
17301 1/1 assign prio79_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17302 1/1 assign prio80_we = addr_hit[80] & reg_we & !reg_error;
Tests: T2 T4 T5
17303
17304 1/1 assign prio80_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17305 1/1 assign prio81_we = addr_hit[81] & reg_we & !reg_error;
Tests: T2 T4 T5
17306
17307 1/1 assign prio81_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17308 1/1 assign prio82_we = addr_hit[82] & reg_we & !reg_error;
Tests: T2 T4 T5
17309
17310 1/1 assign prio82_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17311 1/1 assign prio83_we = addr_hit[83] & reg_we & !reg_error;
Tests: T2 T4 T5
17312
17313 1/1 assign prio83_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17314 1/1 assign prio84_we = addr_hit[84] & reg_we & !reg_error;
Tests: T2 T4 T5
17315
17316 1/1 assign prio84_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17317 1/1 assign prio85_we = addr_hit[85] & reg_we & !reg_error;
Tests: T2 T4 T5
17318
17319 1/1 assign prio85_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17320 1/1 assign prio86_we = addr_hit[86] & reg_we & !reg_error;
Tests: T2 T4 T5
17321
17322 1/1 assign prio86_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17323 1/1 assign prio87_we = addr_hit[87] & reg_we & !reg_error;
Tests: T2 T4 T5
17324
17325 1/1 assign prio87_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17326 1/1 assign prio88_we = addr_hit[88] & reg_we & !reg_error;
Tests: T2 T4 T5
17327
17328 1/1 assign prio88_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17329 1/1 assign prio89_we = addr_hit[89] & reg_we & !reg_error;
Tests: T2 T4 T5
17330
17331 1/1 assign prio89_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17332 1/1 assign prio90_we = addr_hit[90] & reg_we & !reg_error;
Tests: T2 T4 T5
17333
17334 1/1 assign prio90_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17335 1/1 assign prio91_we = addr_hit[91] & reg_we & !reg_error;
Tests: T2 T4 T5
17336
17337 1/1 assign prio91_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17338 1/1 assign prio92_we = addr_hit[92] & reg_we & !reg_error;
Tests: T2 T4 T5
17339
17340 1/1 assign prio92_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17341 1/1 assign prio93_we = addr_hit[93] & reg_we & !reg_error;
Tests: T2 T4 T5
17342
17343 1/1 assign prio93_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17344 1/1 assign prio94_we = addr_hit[94] & reg_we & !reg_error;
Tests: T2 T4 T5
17345
17346 1/1 assign prio94_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17347 1/1 assign prio95_we = addr_hit[95] & reg_we & !reg_error;
Tests: T2 T4 T5
17348
17349 1/1 assign prio95_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17350 1/1 assign prio96_we = addr_hit[96] & reg_we & !reg_error;
Tests: T2 T4 T5
17351
17352 1/1 assign prio96_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17353 1/1 assign prio97_we = addr_hit[97] & reg_we & !reg_error;
Tests: T2 T4 T5
17354
17355 1/1 assign prio97_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17356 1/1 assign prio98_we = addr_hit[98] & reg_we & !reg_error;
Tests: T2 T4 T5
17357
17358 1/1 assign prio98_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17359 1/1 assign prio99_we = addr_hit[99] & reg_we & !reg_error;
Tests: T2 T4 T5
17360
17361 1/1 assign prio99_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17362 1/1 assign prio100_we = addr_hit[100] & reg_we & !reg_error;
Tests: T2 T4 T5
17363
17364 1/1 assign prio100_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17365 1/1 assign prio101_we = addr_hit[101] & reg_we & !reg_error;
Tests: T2 T4 T5
17366
17367 1/1 assign prio101_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17368 1/1 assign prio102_we = addr_hit[102] & reg_we & !reg_error;
Tests: T2 T4 T5
17369
17370 1/1 assign prio102_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17371 1/1 assign prio103_we = addr_hit[103] & reg_we & !reg_error;
Tests: T2 T4 T5
17372
17373 1/1 assign prio103_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17374 1/1 assign prio104_we = addr_hit[104] & reg_we & !reg_error;
Tests: T2 T4 T5
17375
17376 1/1 assign prio104_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17377 1/1 assign prio105_we = addr_hit[105] & reg_we & !reg_error;
Tests: T2 T4 T5
17378
17379 1/1 assign prio105_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17380 1/1 assign prio106_we = addr_hit[106] & reg_we & !reg_error;
Tests: T2 T4 T5
17381
17382 1/1 assign prio106_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17383 1/1 assign prio107_we = addr_hit[107] & reg_we & !reg_error;
Tests: T2 T4 T5
17384
17385 1/1 assign prio107_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17386 1/1 assign prio108_we = addr_hit[108] & reg_we & !reg_error;
Tests: T2 T4 T5
17387
17388 1/1 assign prio108_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17389 1/1 assign prio109_we = addr_hit[109] & reg_we & !reg_error;
Tests: T2 T4 T5
17390
17391 1/1 assign prio109_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17392 1/1 assign prio110_we = addr_hit[110] & reg_we & !reg_error;
Tests: T2 T4 T5
17393
17394 1/1 assign prio110_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17395 1/1 assign prio111_we = addr_hit[111] & reg_we & !reg_error;
Tests: T2 T4 T5
17396
17397 1/1 assign prio111_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17398 1/1 assign prio112_we = addr_hit[112] & reg_we & !reg_error;
Tests: T2 T4 T5
17399
17400 1/1 assign prio112_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17401 1/1 assign prio113_we = addr_hit[113] & reg_we & !reg_error;
Tests: T2 T4 T5
17402
17403 1/1 assign prio113_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17404 1/1 assign prio114_we = addr_hit[114] & reg_we & !reg_error;
Tests: T2 T4 T5
17405
17406 1/1 assign prio114_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17407 1/1 assign prio115_we = addr_hit[115] & reg_we & !reg_error;
Tests: T2 T4 T5
17408
17409 1/1 assign prio115_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17410 1/1 assign prio116_we = addr_hit[116] & reg_we & !reg_error;
Tests: T2 T4 T5
17411
17412 1/1 assign prio116_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17413 1/1 assign prio117_we = addr_hit[117] & reg_we & !reg_error;
Tests: T2 T4 T5
17414
17415 1/1 assign prio117_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17416 1/1 assign prio118_we = addr_hit[118] & reg_we & !reg_error;
Tests: T2 T4 T5
17417
17418 1/1 assign prio118_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17419 1/1 assign prio119_we = addr_hit[119] & reg_we & !reg_error;
Tests: T2 T4 T5
17420
17421 1/1 assign prio119_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17422 1/1 assign prio120_we = addr_hit[120] & reg_we & !reg_error;
Tests: T2 T4 T5
17423
17424 1/1 assign prio120_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17425 1/1 assign prio121_we = addr_hit[121] & reg_we & !reg_error;
Tests: T2 T4 T5
17426
17427 1/1 assign prio121_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17428 1/1 assign prio122_we = addr_hit[122] & reg_we & !reg_error;
Tests: T2 T4 T5
17429
17430 1/1 assign prio122_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17431 1/1 assign prio123_we = addr_hit[123] & reg_we & !reg_error;
Tests: T2 T4 T5
17432
17433 1/1 assign prio123_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17434 1/1 assign prio124_we = addr_hit[124] & reg_we & !reg_error;
Tests: T2 T4 T5
17435
17436 1/1 assign prio124_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17437 1/1 assign prio125_we = addr_hit[125] & reg_we & !reg_error;
Tests: T2 T4 T5
17438
17439 1/1 assign prio125_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17440 1/1 assign prio126_we = addr_hit[126] & reg_we & !reg_error;
Tests: T2 T4 T5
17441
17442 1/1 assign prio126_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17443 1/1 assign prio127_we = addr_hit[127] & reg_we & !reg_error;
Tests: T2 T4 T5
17444
17445 1/1 assign prio127_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17446 1/1 assign prio128_we = addr_hit[128] & reg_we & !reg_error;
Tests: T2 T4 T5
17447
17448 1/1 assign prio128_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17449 1/1 assign prio129_we = addr_hit[129] & reg_we & !reg_error;
Tests: T2 T4 T5
17450
17451 1/1 assign prio129_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17452 1/1 assign prio130_we = addr_hit[130] & reg_we & !reg_error;
Tests: T2 T4 T5
17453
17454 1/1 assign prio130_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17455 1/1 assign prio131_we = addr_hit[131] & reg_we & !reg_error;
Tests: T2 T4 T5
17456
17457 1/1 assign prio131_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17458 1/1 assign prio132_we = addr_hit[132] & reg_we & !reg_error;
Tests: T2 T4 T5
17459
17460 1/1 assign prio132_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17461 1/1 assign prio133_we = addr_hit[133] & reg_we & !reg_error;
Tests: T2 T4 T5
17462
17463 1/1 assign prio133_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17464 1/1 assign prio134_we = addr_hit[134] & reg_we & !reg_error;
Tests: T2 T4 T5
17465
17466 1/1 assign prio134_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17467 1/1 assign prio135_we = addr_hit[135] & reg_we & !reg_error;
Tests: T2 T4 T5
17468
17469 1/1 assign prio135_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17470 1/1 assign prio136_we = addr_hit[136] & reg_we & !reg_error;
Tests: T2 T4 T5
17471
17472 1/1 assign prio136_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17473 1/1 assign prio137_we = addr_hit[137] & reg_we & !reg_error;
Tests: T2 T4 T5
17474
17475 1/1 assign prio137_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17476 1/1 assign prio138_we = addr_hit[138] & reg_we & !reg_error;
Tests: T2 T4 T5
17477
17478 1/1 assign prio138_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17479 1/1 assign prio139_we = addr_hit[139] & reg_we & !reg_error;
Tests: T2 T4 T5
17480
17481 1/1 assign prio139_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17482 1/1 assign prio140_we = addr_hit[140] & reg_we & !reg_error;
Tests: T2 T4 T5
17483
17484 1/1 assign prio140_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17485 1/1 assign prio141_we = addr_hit[141] & reg_we & !reg_error;
Tests: T2 T4 T5
17486
17487 1/1 assign prio141_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17488 1/1 assign prio142_we = addr_hit[142] & reg_we & !reg_error;
Tests: T2 T4 T5
17489
17490 1/1 assign prio142_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17491 1/1 assign prio143_we = addr_hit[143] & reg_we & !reg_error;
Tests: T2 T4 T5
17492
17493 1/1 assign prio143_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17494 1/1 assign prio144_we = addr_hit[144] & reg_we & !reg_error;
Tests: T2 T4 T5
17495
17496 1/1 assign prio144_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17497 1/1 assign prio145_we = addr_hit[145] & reg_we & !reg_error;
Tests: T2 T4 T5
17498
17499 1/1 assign prio145_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17500 1/1 assign prio146_we = addr_hit[146] & reg_we & !reg_error;
Tests: T2 T4 T5
17501
17502 1/1 assign prio146_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17503 1/1 assign prio147_we = addr_hit[147] & reg_we & !reg_error;
Tests: T2 T4 T5
17504
17505 1/1 assign prio147_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17506 1/1 assign prio148_we = addr_hit[148] & reg_we & !reg_error;
Tests: T2 T4 T5
17507
17508 1/1 assign prio148_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17509 1/1 assign prio149_we = addr_hit[149] & reg_we & !reg_error;
Tests: T2 T4 T5
17510
17511 1/1 assign prio149_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17512 1/1 assign prio150_we = addr_hit[150] & reg_we & !reg_error;
Tests: T2 T4 T5
17513
17514 1/1 assign prio150_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17515 1/1 assign prio151_we = addr_hit[151] & reg_we & !reg_error;
Tests: T2 T4 T5
17516
17517 1/1 assign prio151_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17518 1/1 assign prio152_we = addr_hit[152] & reg_we & !reg_error;
Tests: T2 T4 T5
17519
17520 1/1 assign prio152_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17521 1/1 assign prio153_we = addr_hit[153] & reg_we & !reg_error;
Tests: T2 T4 T5
17522
17523 1/1 assign prio153_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17524 1/1 assign prio154_we = addr_hit[154] & reg_we & !reg_error;
Tests: T2 T4 T5
17525
17526 1/1 assign prio154_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17527 1/1 assign prio155_we = addr_hit[155] & reg_we & !reg_error;
Tests: T2 T4 T5
17528
17529 1/1 assign prio155_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17530 1/1 assign prio156_we = addr_hit[156] & reg_we & !reg_error;
Tests: T2 T4 T5
17531
17532 1/1 assign prio156_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17533 1/1 assign prio157_we = addr_hit[157] & reg_we & !reg_error;
Tests: T2 T4 T5
17534
17535 1/1 assign prio157_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17536 1/1 assign prio158_we = addr_hit[158] & reg_we & !reg_error;
Tests: T2 T4 T5
17537
17538 1/1 assign prio158_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17539 1/1 assign prio159_we = addr_hit[159] & reg_we & !reg_error;
Tests: T2 T4 T5
17540
17541 1/1 assign prio159_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17542 1/1 assign prio160_we = addr_hit[160] & reg_we & !reg_error;
Tests: T2 T4 T5
17543
17544 1/1 assign prio160_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17545 1/1 assign prio161_we = addr_hit[161] & reg_we & !reg_error;
Tests: T2 T4 T5
17546
17547 1/1 assign prio161_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17548 1/1 assign prio162_we = addr_hit[162] & reg_we & !reg_error;
Tests: T2 T4 T5
17549
17550 1/1 assign prio162_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17551 1/1 assign prio163_we = addr_hit[163] & reg_we & !reg_error;
Tests: T2 T4 T5
17552
17553 1/1 assign prio163_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17554 1/1 assign prio164_we = addr_hit[164] & reg_we & !reg_error;
Tests: T2 T4 T5
17555
17556 1/1 assign prio164_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17557 1/1 assign prio165_we = addr_hit[165] & reg_we & !reg_error;
Tests: T2 T4 T5
17558
17559 1/1 assign prio165_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17560 1/1 assign prio166_we = addr_hit[166] & reg_we & !reg_error;
Tests: T2 T4 T5
17561
17562 1/1 assign prio166_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17563 1/1 assign prio167_we = addr_hit[167] & reg_we & !reg_error;
Tests: T2 T4 T5
17564
17565 1/1 assign prio167_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17566 1/1 assign prio168_we = addr_hit[168] & reg_we & !reg_error;
Tests: T2 T4 T5
17567
17568 1/1 assign prio168_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17569 1/1 assign prio169_we = addr_hit[169] & reg_we & !reg_error;
Tests: T2 T4 T5
17570
17571 1/1 assign prio169_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17572 1/1 assign prio170_we = addr_hit[170] & reg_we & !reg_error;
Tests: T2 T4 T5
17573
17574 1/1 assign prio170_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17575 1/1 assign prio171_we = addr_hit[171] & reg_we & !reg_error;
Tests: T2 T4 T5
17576
17577 1/1 assign prio171_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17578 1/1 assign prio172_we = addr_hit[172] & reg_we & !reg_error;
Tests: T2 T4 T5
17579
17580 1/1 assign prio172_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17581 1/1 assign prio173_we = addr_hit[173] & reg_we & !reg_error;
Tests: T2 T4 T5
17582
17583 1/1 assign prio173_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17584 1/1 assign prio174_we = addr_hit[174] & reg_we & !reg_error;
Tests: T2 T4 T5
17585
17586 1/1 assign prio174_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17587 1/1 assign prio175_we = addr_hit[175] & reg_we & !reg_error;
Tests: T2 T4 T5
17588
17589 1/1 assign prio175_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17590 1/1 assign prio176_we = addr_hit[176] & reg_we & !reg_error;
Tests: T2 T4 T5
17591
17592 1/1 assign prio176_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17593 1/1 assign prio177_we = addr_hit[177] & reg_we & !reg_error;
Tests: T2 T4 T5
17594
17595 1/1 assign prio177_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17596 1/1 assign prio178_we = addr_hit[178] & reg_we & !reg_error;
Tests: T2 T4 T5
17597
17598 1/1 assign prio178_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17599 1/1 assign prio179_we = addr_hit[179] & reg_we & !reg_error;
Tests: T2 T4 T5
17600
17601 1/1 assign prio179_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17602 1/1 assign prio180_we = addr_hit[180] & reg_we & !reg_error;
Tests: T2 T4 T5
17603
17604 1/1 assign prio180_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17605 1/1 assign prio181_we = addr_hit[181] & reg_we & !reg_error;
Tests: T2 T4 T5
17606
17607 1/1 assign prio181_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17608 1/1 assign prio182_we = addr_hit[182] & reg_we & !reg_error;
Tests: T2 T4 T5
17609
17610 1/1 assign prio182_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17611 1/1 assign prio183_we = addr_hit[183] & reg_we & !reg_error;
Tests: T2 T4 T5
17612
17613 1/1 assign prio183_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17614 1/1 assign prio184_we = addr_hit[184] & reg_we & !reg_error;
Tests: T2 T4 T5
17615
17616 1/1 assign prio184_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17617 1/1 assign prio185_we = addr_hit[185] & reg_we & !reg_error;
Tests: T2 T4 T5
17618
17619 1/1 assign prio185_wd = reg_wdata[1:0];
Tests: T2 T4 T5
17620 1/1 assign ie0_0_we = addr_hit[192] & reg_we & !reg_error;
Tests: T2 T4 T5
17621
17622 1/1 assign ie0_0_e_0_wd = reg_wdata[0];
Tests: T4 T5 T6
17623
17624 1/1 assign ie0_0_e_1_wd = reg_wdata[1];
Tests: T2 T5 T25
17625
17626 1/1 assign ie0_0_e_2_wd = reg_wdata[2];
Tests: T124 T26 T45
17627
17628 1/1 assign ie0_0_e_3_wd = reg_wdata[3];
Tests: T4 T5 T6
17629
17630 1/1 assign ie0_0_e_4_wd = reg_wdata[4];
Tests: T4 T5 T6
17631
17632 1/1 assign ie0_0_e_5_wd = reg_wdata[5];
Tests: T5 T124 T12
17633
17634 1/1 assign ie0_0_e_6_wd = reg_wdata[6];
Tests: T5 T12 T27
17635
17636 1/1 assign ie0_0_e_7_wd = reg_wdata[7];
Tests: T4 T6 T25
17637
17638 1/1 assign ie0_0_e_8_wd = reg_wdata[8];
Tests: T12 T27 T10
17639
17640 1/1 assign ie0_0_e_9_wd = reg_wdata[9];
Tests: T12 T27 T10
17641
17642 1/1 assign ie0_0_e_10_wd = reg_wdata[10];
Tests: T12 T27 T134
17643
17644 1/1 assign ie0_0_e_11_wd = reg_wdata[11];
Tests: T27 T66 T134
17645
17646 1/1 assign ie0_0_e_12_wd = reg_wdata[12];
Tests: T27 T66 T134
17647
17648 1/1 assign ie0_0_e_13_wd = reg_wdata[13];
Tests: T27 T62 T134
17649
17650 1/1 assign ie0_0_e_14_wd = reg_wdata[14];
Tests: T27 T62 T66
17651
17652 1/1 assign ie0_0_e_15_wd = reg_wdata[15];
Tests: T27 T66 T134
17653
17654 1/1 assign ie0_0_e_16_wd = reg_wdata[16];
Tests: T27 T62 T66
17655
17656 1/1 assign ie0_0_e_17_wd = reg_wdata[17];
Tests: T27 T62 T66
17657
17658 1/1 assign ie0_0_e_18_wd = reg_wdata[18];
Tests: T27 T62 T66
17659
17660 1/1 assign ie0_0_e_19_wd = reg_wdata[19];
Tests: T27 T62 T68
17661
17662 1/1 assign ie0_0_e_20_wd = reg_wdata[20];
Tests: T27 T62 T66
17663
17664 1/1 assign ie0_0_e_21_wd = reg_wdata[21];
Tests: T27 T68 T249
17665
17666 1/1 assign ie0_0_e_22_wd = reg_wdata[22];
Tests: T27 T62 T68
17667
17668 1/1 assign ie0_0_e_23_wd = reg_wdata[23];
Tests: T27 T68 T249
17669
17670 1/1 assign ie0_0_e_24_wd = reg_wdata[24];
Tests: T27 T68 T249
17671
17672 1/1 assign ie0_0_e_25_wd = reg_wdata[25];
Tests: T2 T4 T6
17673
17674 1/1 assign ie0_0_e_26_wd = reg_wdata[26];
Tests: T5 T27 T68
17675
17676 1/1 assign ie0_0_e_27_wd = reg_wdata[27];
Tests: T5 T27 T68
17677
17678 1/1 assign ie0_0_e_28_wd = reg_wdata[28];
Tests: T26 T45 T27
17679
17680 1/1 assign ie0_0_e_29_wd = reg_wdata[29];
Tests: T26 T45 T146
17681
17682 1/1 assign ie0_0_e_30_wd = reg_wdata[30];
Tests: T26 T27 T70
17683
17684 1/1 assign ie0_0_e_31_wd = reg_wdata[31];
Tests: T26 T45 T27
17685 1/1 assign ie0_1_we = addr_hit[193] & reg_we & !reg_error;
Tests: T2 T4 T5
17686
17687 1/1 assign ie0_1_e_32_wd = reg_wdata[0];
Tests: T4 T5 T6
17688
17689 1/1 assign ie0_1_e_33_wd = reg_wdata[1];
Tests: T2 T5 T25
17690
17691 1/1 assign ie0_1_e_34_wd = reg_wdata[2];
Tests: T124 T26 T45
17692
17693 1/1 assign ie0_1_e_35_wd = reg_wdata[3];
Tests: T4 T5 T6
17694
17695 1/1 assign ie0_1_e_36_wd = reg_wdata[4];
Tests: T4 T5 T6
17696
17697 1/1 assign ie0_1_e_37_wd = reg_wdata[5];
Tests: T5 T124 T12
17698
17699 1/1 assign ie0_1_e_38_wd = reg_wdata[6];
Tests: T5 T12 T27
17700
17701 1/1 assign ie0_1_e_39_wd = reg_wdata[7];
Tests: T4 T6 T25
17702
17703 1/1 assign ie0_1_e_40_wd = reg_wdata[8];
Tests: T12 T27 T10
17704
17705 1/1 assign ie0_1_e_41_wd = reg_wdata[9];
Tests: T12 T27 T10
17706
17707 1/1 assign ie0_1_e_42_wd = reg_wdata[10];
Tests: T12 T27 T134
17708
17709 1/1 assign ie0_1_e_43_wd = reg_wdata[11];
Tests: T27 T66 T134
17710
17711 1/1 assign ie0_1_e_44_wd = reg_wdata[12];
Tests: T27 T66 T134
17712
17713 1/1 assign ie0_1_e_45_wd = reg_wdata[13];
Tests: T27 T62 T134
17714
17715 1/1 assign ie0_1_e_46_wd = reg_wdata[14];
Tests: T27 T62 T66
17716
17717 1/1 assign ie0_1_e_47_wd = reg_wdata[15];
Tests: T27 T66 T134
17718
17719 1/1 assign ie0_1_e_48_wd = reg_wdata[16];
Tests: T27 T62 T66
17720
17721 1/1 assign ie0_1_e_49_wd = reg_wdata[17];
Tests: T27 T62 T66
17722
17723 1/1 assign ie0_1_e_50_wd = reg_wdata[18];
Tests: T27 T62 T66
17724
17725 1/1 assign ie0_1_e_51_wd = reg_wdata[19];
Tests: T27 T62 T68
17726
17727 1/1 assign ie0_1_e_52_wd = reg_wdata[20];
Tests: T27 T62 T66
17728
17729 1/1 assign ie0_1_e_53_wd = reg_wdata[21];
Tests: T27 T68 T249
17730
17731 1/1 assign ie0_1_e_54_wd = reg_wdata[22];
Tests: T27 T62 T68
17732
17733 1/1 assign ie0_1_e_55_wd = reg_wdata[23];
Tests: T27 T68 T249
17734
17735 1/1 assign ie0_1_e_56_wd = reg_wdata[24];
Tests: T27 T68 T249
17736
17737 1/1 assign ie0_1_e_57_wd = reg_wdata[25];
Tests: T2 T4 T6
17738
17739 1/1 assign ie0_1_e_58_wd = reg_wdata[26];
Tests: T5 T27 T68
17740
17741 1/1 assign ie0_1_e_59_wd = reg_wdata[27];
Tests: T5 T27 T68
17742
17743 1/1 assign ie0_1_e_60_wd = reg_wdata[28];
Tests: T26 T45 T27
17744
17745 1/1 assign ie0_1_e_61_wd = reg_wdata[29];
Tests: T26 T45 T146
17746
17747 1/1 assign ie0_1_e_62_wd = reg_wdata[30];
Tests: T26 T27 T70
17748
17749 1/1 assign ie0_1_e_63_wd = reg_wdata[31];
Tests: T26 T45 T27
17750 1/1 assign ie0_2_we = addr_hit[194] & reg_we & !reg_error;
Tests: T2 T4 T5
17751
17752 1/1 assign ie0_2_e_64_wd = reg_wdata[0];
Tests: T4 T5 T6
17753
17754 1/1 assign ie0_2_e_65_wd = reg_wdata[1];
Tests: T2 T5 T25
17755
17756 1/1 assign ie0_2_e_66_wd = reg_wdata[2];
Tests: T124 T26 T45
17757
17758 1/1 assign ie0_2_e_67_wd = reg_wdata[3];
Tests: T4 T5 T6
17759
17760 1/1 assign ie0_2_e_68_wd = reg_wdata[4];
Tests: T4 T5 T6
17761
17762 1/1 assign ie0_2_e_69_wd = reg_wdata[5];
Tests: T5 T124 T12
17763
17764 1/1 assign ie0_2_e_70_wd = reg_wdata[6];
Tests: T5 T12 T27
17765
17766 1/1 assign ie0_2_e_71_wd = reg_wdata[7];
Tests: T4 T6 T25
17767
17768 1/1 assign ie0_2_e_72_wd = reg_wdata[8];
Tests: T12 T27 T10
17769
17770 1/1 assign ie0_2_e_73_wd = reg_wdata[9];
Tests: T12 T27 T10
17771
17772 1/1 assign ie0_2_e_74_wd = reg_wdata[10];
Tests: T12 T27 T134
17773
17774 1/1 assign ie0_2_e_75_wd = reg_wdata[11];
Tests: T27 T66 T134
17775
17776 1/1 assign ie0_2_e_76_wd = reg_wdata[12];
Tests: T27 T66 T134
17777
17778 1/1 assign ie0_2_e_77_wd = reg_wdata[13];
Tests: T27 T62 T134
17779
17780 1/1 assign ie0_2_e_78_wd = reg_wdata[14];
Tests: T27 T62 T66
17781
17782 1/1 assign ie0_2_e_79_wd = reg_wdata[15];
Tests: T27 T66 T134
17783
17784 1/1 assign ie0_2_e_80_wd = reg_wdata[16];
Tests: T27 T62 T66
17785
17786 1/1 assign ie0_2_e_81_wd = reg_wdata[17];
Tests: T27 T62 T66
17787
17788 1/1 assign ie0_2_e_82_wd = reg_wdata[18];
Tests: T27 T62 T66
17789
17790 1/1 assign ie0_2_e_83_wd = reg_wdata[19];
Tests: T27 T62 T68
17791
17792 1/1 assign ie0_2_e_84_wd = reg_wdata[20];
Tests: T27 T62 T66
17793
17794 1/1 assign ie0_2_e_85_wd = reg_wdata[21];
Tests: T27 T68 T249
17795
17796 1/1 assign ie0_2_e_86_wd = reg_wdata[22];
Tests: T27 T62 T68
17797
17798 1/1 assign ie0_2_e_87_wd = reg_wdata[23];
Tests: T27 T68 T249
17799
17800 1/1 assign ie0_2_e_88_wd = reg_wdata[24];
Tests: T27 T68 T249
17801
17802 1/1 assign ie0_2_e_89_wd = reg_wdata[25];
Tests: T2 T4 T6
17803
17804 1/1 assign ie0_2_e_90_wd = reg_wdata[26];
Tests: T5 T27 T68
17805
17806 1/1 assign ie0_2_e_91_wd = reg_wdata[27];
Tests: T5 T27 T68
17807
17808 1/1 assign ie0_2_e_92_wd = reg_wdata[28];
Tests: T26 T45 T27
17809
17810 1/1 assign ie0_2_e_93_wd = reg_wdata[29];
Tests: T26 T45 T146
17811
17812 1/1 assign ie0_2_e_94_wd = reg_wdata[30];
Tests: T26 T27 T70
17813
17814 1/1 assign ie0_2_e_95_wd = reg_wdata[31];
Tests: T26 T45 T27
17815 1/1 assign ie0_3_we = addr_hit[195] & reg_we & !reg_error;
Tests: T2 T4 T5
17816
17817 1/1 assign ie0_3_e_96_wd = reg_wdata[0];
Tests: T4 T5 T6
17818
17819 1/1 assign ie0_3_e_97_wd = reg_wdata[1];
Tests: T2 T5 T25
17820
17821 1/1 assign ie0_3_e_98_wd = reg_wdata[2];
Tests: T124 T26 T45
17822
17823 1/1 assign ie0_3_e_99_wd = reg_wdata[3];
Tests: T4 T5 T6
17824
17825 1/1 assign ie0_3_e_100_wd = reg_wdata[4];
Tests: T4 T5 T6
17826
17827 1/1 assign ie0_3_e_101_wd = reg_wdata[5];
Tests: T5 T124 T12
17828
17829 1/1 assign ie0_3_e_102_wd = reg_wdata[6];
Tests: T5 T12 T27
17830
17831 1/1 assign ie0_3_e_103_wd = reg_wdata[7];
Tests: T4 T6 T25
17832
17833 1/1 assign ie0_3_e_104_wd = reg_wdata[8];
Tests: T12 T27 T10
17834
17835 1/1 assign ie0_3_e_105_wd = reg_wdata[9];
Tests: T12 T27 T10
17836
17837 1/1 assign ie0_3_e_106_wd = reg_wdata[10];
Tests: T12 T27 T134
17838
17839 1/1 assign ie0_3_e_107_wd = reg_wdata[11];
Tests: T27 T66 T134
17840
17841 1/1 assign ie0_3_e_108_wd = reg_wdata[12];
Tests: T27 T66 T134
17842
17843 1/1 assign ie0_3_e_109_wd = reg_wdata[13];
Tests: T27 T62 T134
17844
17845 1/1 assign ie0_3_e_110_wd = reg_wdata[14];
Tests: T27 T62 T66
17846
17847 1/1 assign ie0_3_e_111_wd = reg_wdata[15];
Tests: T27 T66 T134
17848
17849 1/1 assign ie0_3_e_112_wd = reg_wdata[16];
Tests: T27 T62 T66
17850
17851 1/1 assign ie0_3_e_113_wd = reg_wdata[17];
Tests: T27 T62 T66
17852
17853 1/1 assign ie0_3_e_114_wd = reg_wdata[18];
Tests: T27 T62 T66
17854
17855 1/1 assign ie0_3_e_115_wd = reg_wdata[19];
Tests: T27 T62 T68
17856
17857 1/1 assign ie0_3_e_116_wd = reg_wdata[20];
Tests: T27 T62 T66
17858
17859 1/1 assign ie0_3_e_117_wd = reg_wdata[21];
Tests: T27 T68 T249
17860
17861 1/1 assign ie0_3_e_118_wd = reg_wdata[22];
Tests: T27 T62 T68
17862
17863 1/1 assign ie0_3_e_119_wd = reg_wdata[23];
Tests: T27 T68 T249
17864
17865 1/1 assign ie0_3_e_120_wd = reg_wdata[24];
Tests: T27 T68 T249
17866
17867 1/1 assign ie0_3_e_121_wd = reg_wdata[25];
Tests: T2 T4 T6
17868
17869 1/1 assign ie0_3_e_122_wd = reg_wdata[26];
Tests: T5 T27 T68
17870
17871 1/1 assign ie0_3_e_123_wd = reg_wdata[27];
Tests: T5 T27 T68
17872
17873 1/1 assign ie0_3_e_124_wd = reg_wdata[28];
Tests: T26 T45 T27
17874
17875 1/1 assign ie0_3_e_125_wd = reg_wdata[29];
Tests: T26 T45 T146
17876
17877 1/1 assign ie0_3_e_126_wd = reg_wdata[30];
Tests: T26 T27 T70
17878
17879 1/1 assign ie0_3_e_127_wd = reg_wdata[31];
Tests: T26 T45 T27
17880 1/1 assign ie0_4_we = addr_hit[196] & reg_we & !reg_error;
Tests: T2 T4 T5
17881
17882 1/1 assign ie0_4_e_128_wd = reg_wdata[0];
Tests: T4 T5 T6
17883
17884 1/1 assign ie0_4_e_129_wd = reg_wdata[1];
Tests: T2 T5 T25
17885
17886 1/1 assign ie0_4_e_130_wd = reg_wdata[2];
Tests: T124 T26 T45
17887
17888 1/1 assign ie0_4_e_131_wd = reg_wdata[3];
Tests: T4 T5 T6
17889
17890 1/1 assign ie0_4_e_132_wd = reg_wdata[4];
Tests: T4 T5 T6
17891
17892 1/1 assign ie0_4_e_133_wd = reg_wdata[5];
Tests: T5 T124 T12
17893
17894 1/1 assign ie0_4_e_134_wd = reg_wdata[6];
Tests: T5 T12 T27
17895
17896 1/1 assign ie0_4_e_135_wd = reg_wdata[7];
Tests: T4 T6 T25
17897
17898 1/1 assign ie0_4_e_136_wd = reg_wdata[8];
Tests: T12 T27 T10
17899
17900 1/1 assign ie0_4_e_137_wd = reg_wdata[9];
Tests: T12 T27 T10
17901
17902 1/1 assign ie0_4_e_138_wd = reg_wdata[10];
Tests: T12 T27 T134
17903
17904 1/1 assign ie0_4_e_139_wd = reg_wdata[11];
Tests: T27 T66 T134
17905
17906 1/1 assign ie0_4_e_140_wd = reg_wdata[12];
Tests: T27 T66 T134
17907
17908 1/1 assign ie0_4_e_141_wd = reg_wdata[13];
Tests: T27 T62 T134
17909
17910 1/1 assign ie0_4_e_142_wd = reg_wdata[14];
Tests: T27 T62 T66
17911
17912 1/1 assign ie0_4_e_143_wd = reg_wdata[15];
Tests: T27 T66 T134
17913
17914 1/1 assign ie0_4_e_144_wd = reg_wdata[16];
Tests: T27 T62 T66
17915
17916 1/1 assign ie0_4_e_145_wd = reg_wdata[17];
Tests: T27 T62 T66
17917
17918 1/1 assign ie0_4_e_146_wd = reg_wdata[18];
Tests: T27 T62 T66
17919
17920 1/1 assign ie0_4_e_147_wd = reg_wdata[19];
Tests: T27 T62 T68
17921
17922 1/1 assign ie0_4_e_148_wd = reg_wdata[20];
Tests: T27 T62 T66
17923
17924 1/1 assign ie0_4_e_149_wd = reg_wdata[21];
Tests: T27 T68 T249
17925
17926 1/1 assign ie0_4_e_150_wd = reg_wdata[22];
Tests: T27 T62 T68
17927
17928 1/1 assign ie0_4_e_151_wd = reg_wdata[23];
Tests: T27 T68 T249
17929
17930 1/1 assign ie0_4_e_152_wd = reg_wdata[24];
Tests: T27 T68 T249
17931
17932 1/1 assign ie0_4_e_153_wd = reg_wdata[25];
Tests: T2 T4 T6
17933
17934 1/1 assign ie0_4_e_154_wd = reg_wdata[26];
Tests: T5 T27 T68
17935
17936 1/1 assign ie0_4_e_155_wd = reg_wdata[27];
Tests: T5 T27 T68
17937
17938 1/1 assign ie0_4_e_156_wd = reg_wdata[28];
Tests: T26 T45 T27
17939
17940 1/1 assign ie0_4_e_157_wd = reg_wdata[29];
Tests: T26 T45 T146
17941
17942 1/1 assign ie0_4_e_158_wd = reg_wdata[30];
Tests: T26 T27 T70
17943
17944 1/1 assign ie0_4_e_159_wd = reg_wdata[31];
Tests: T26 T45 T27
17945 1/1 assign ie0_5_we = addr_hit[197] & reg_we & !reg_error;
Tests: T2 T4 T5
17946
17947 1/1 assign ie0_5_e_160_wd = reg_wdata[0];
Tests: T4 T5 T6
17948
17949 1/1 assign ie0_5_e_161_wd = reg_wdata[1];
Tests: T2 T5 T25
17950
17951 1/1 assign ie0_5_e_162_wd = reg_wdata[2];
Tests: T124 T26 T45
17952
17953 1/1 assign ie0_5_e_163_wd = reg_wdata[3];
Tests: T4 T5 T6
17954
17955 1/1 assign ie0_5_e_164_wd = reg_wdata[4];
Tests: T4 T5 T6
17956
17957 1/1 assign ie0_5_e_165_wd = reg_wdata[5];
Tests: T5 T124 T12
17958
17959 1/1 assign ie0_5_e_166_wd = reg_wdata[6];
Tests: T5 T12 T27
17960
17961 1/1 assign ie0_5_e_167_wd = reg_wdata[7];
Tests: T4 T6 T25
17962
17963 1/1 assign ie0_5_e_168_wd = reg_wdata[8];
Tests: T12 T27 T10
17964
17965 1/1 assign ie0_5_e_169_wd = reg_wdata[9];
Tests: T12 T27 T10
17966
17967 1/1 assign ie0_5_e_170_wd = reg_wdata[10];
Tests: T12 T27 T134
17968
17969 1/1 assign ie0_5_e_171_wd = reg_wdata[11];
Tests: T27 T66 T134
17970
17971 1/1 assign ie0_5_e_172_wd = reg_wdata[12];
Tests: T27 T66 T134
17972
17973 1/1 assign ie0_5_e_173_wd = reg_wdata[13];
Tests: T27 T62 T134
17974
17975 1/1 assign ie0_5_e_174_wd = reg_wdata[14];
Tests: T27 T62 T66
17976
17977 1/1 assign ie0_5_e_175_wd = reg_wdata[15];
Tests: T27 T66 T134
17978
17979 1/1 assign ie0_5_e_176_wd = reg_wdata[16];
Tests: T27 T62 T66
17980
17981 1/1 assign ie0_5_e_177_wd = reg_wdata[17];
Tests: T27 T62 T66
17982
17983 1/1 assign ie0_5_e_178_wd = reg_wdata[18];
Tests: T27 T62 T66
17984
17985 1/1 assign ie0_5_e_179_wd = reg_wdata[19];
Tests: T27 T62 T68
17986
17987 1/1 assign ie0_5_e_180_wd = reg_wdata[20];
Tests: T27 T62 T66
17988
17989 1/1 assign ie0_5_e_181_wd = reg_wdata[21];
Tests: T27 T68 T249
17990
17991 1/1 assign ie0_5_e_182_wd = reg_wdata[22];
Tests: T27 T62 T68
17992
17993 1/1 assign ie0_5_e_183_wd = reg_wdata[23];
Tests: T27 T68 T249
17994
17995 1/1 assign ie0_5_e_184_wd = reg_wdata[24];
Tests: T27 T68 T249
17996
17997 1/1 assign ie0_5_e_185_wd = reg_wdata[25];
Tests: T2 T4 T6
17998 1/1 assign threshold0_we = addr_hit[198] & reg_we & !reg_error;
Tests: T2 T4 T5
17999
18000 1/1 assign threshold0_wd = reg_wdata[1:0];
Tests: T2 T4 T5
18001 1/1 assign cc0_re = addr_hit[199] & reg_re & !reg_error;
Tests: T2 T4 T5
18002 1/1 assign cc0_we = addr_hit[199] & reg_we & !reg_error;
Tests: T2 T4 T5
18003
18004 1/1 assign cc0_wd = reg_wdata[7:0];
Tests: T2 T4 T5
18005 1/1 assign msip0_we = addr_hit[200] & reg_we & !reg_error;
Tests: T2 T4 T5
18006
18007 1/1 assign msip0_wd = reg_wdata[0];
Tests: T4 T5 T6
18008 1/1 assign alert_test_we = addr_hit[201] & reg_we & !reg_error;
Tests: T2 T4 T5
18009
18010 1/1 assign alert_test_wd = reg_wdata[0];
Tests: T4 T5 T6
18011
18012 // Assign write-enables to checker logic vector.
18013 always_comb begin
18014 1/1 reg_we_check = '0;
Tests: T2 T4 T5
18015 1/1 reg_we_check[0] = prio0_we;
Tests: T2 T4 T5
18016 1/1 reg_we_check[1] = prio1_we;
Tests: T2 T4 T5
18017 1/1 reg_we_check[2] = prio2_we;
Tests: T2 T4 T5
18018 1/1 reg_we_check[3] = prio3_we;
Tests: T2 T4 T5
18019 1/1 reg_we_check[4] = prio4_we;
Tests: T2 T4 T5
18020 1/1 reg_we_check[5] = prio5_we;
Tests: T2 T4 T5
18021 1/1 reg_we_check[6] = prio6_we;
Tests: T2 T4 T5
18022 1/1 reg_we_check[7] = prio7_we;
Tests: T2 T4 T5
18023 1/1 reg_we_check[8] = prio8_we;
Tests: T2 T4 T5
18024 1/1 reg_we_check[9] = prio9_we;
Tests: T2 T4 T5
18025 1/1 reg_we_check[10] = prio10_we;
Tests: T2 T4 T5
18026 1/1 reg_we_check[11] = prio11_we;
Tests: T2 T4 T5
18027 1/1 reg_we_check[12] = prio12_we;
Tests: T2 T4 T5
18028 1/1 reg_we_check[13] = prio13_we;
Tests: T2 T4 T5
18029 1/1 reg_we_check[14] = prio14_we;
Tests: T2 T4 T5
18030 1/1 reg_we_check[15] = prio15_we;
Tests: T2 T4 T5
18031 1/1 reg_we_check[16] = prio16_we;
Tests: T2 T4 T5
18032 1/1 reg_we_check[17] = prio17_we;
Tests: T2 T4 T5
18033 1/1 reg_we_check[18] = prio18_we;
Tests: T2 T4 T5
18034 1/1 reg_we_check[19] = prio19_we;
Tests: T2 T4 T5
18035 1/1 reg_we_check[20] = prio20_we;
Tests: T2 T4 T5
18036 1/1 reg_we_check[21] = prio21_we;
Tests: T2 T4 T5
18037 1/1 reg_we_check[22] = prio22_we;
Tests: T2 T4 T5
18038 1/1 reg_we_check[23] = prio23_we;
Tests: T2 T4 T5
18039 1/1 reg_we_check[24] = prio24_we;
Tests: T2 T4 T5
18040 1/1 reg_we_check[25] = prio25_we;
Tests: T2 T4 T5
18041 1/1 reg_we_check[26] = prio26_we;
Tests: T2 T4 T5
18042 1/1 reg_we_check[27] = prio27_we;
Tests: T2 T4 T5
18043 1/1 reg_we_check[28] = prio28_we;
Tests: T2 T4 T5
18044 1/1 reg_we_check[29] = prio29_we;
Tests: T2 T4 T5
18045 1/1 reg_we_check[30] = prio30_we;
Tests: T2 T4 T5
18046 1/1 reg_we_check[31] = prio31_we;
Tests: T2 T4 T5
18047 1/1 reg_we_check[32] = prio32_we;
Tests: T2 T4 T5
18048 1/1 reg_we_check[33] = prio33_we;
Tests: T2 T4 T5
18049 1/1 reg_we_check[34] = prio34_we;
Tests: T2 T4 T5
18050 1/1 reg_we_check[35] = prio35_we;
Tests: T2 T4 T5
18051 1/1 reg_we_check[36] = prio36_we;
Tests: T2 T4 T5
18052 1/1 reg_we_check[37] = prio37_we;
Tests: T2 T4 T5
18053 1/1 reg_we_check[38] = prio38_we;
Tests: T2 T4 T5
18054 1/1 reg_we_check[39] = prio39_we;
Tests: T2 T4 T5
18055 1/1 reg_we_check[40] = prio40_we;
Tests: T2 T4 T5
18056 1/1 reg_we_check[41] = prio41_we;
Tests: T2 T4 T5
18057 1/1 reg_we_check[42] = prio42_we;
Tests: T2 T4 T5
18058 1/1 reg_we_check[43] = prio43_we;
Tests: T2 T4 T5
18059 1/1 reg_we_check[44] = prio44_we;
Tests: T2 T4 T5
18060 1/1 reg_we_check[45] = prio45_we;
Tests: T2 T4 T5
18061 1/1 reg_we_check[46] = prio46_we;
Tests: T2 T4 T5
18062 1/1 reg_we_check[47] = prio47_we;
Tests: T2 T4 T5
18063 1/1 reg_we_check[48] = prio48_we;
Tests: T2 T4 T5
18064 1/1 reg_we_check[49] = prio49_we;
Tests: T2 T4 T5
18065 1/1 reg_we_check[50] = prio50_we;
Tests: T2 T4 T5
18066 1/1 reg_we_check[51] = prio51_we;
Tests: T2 T4 T5
18067 1/1 reg_we_check[52] = prio52_we;
Tests: T2 T4 T5
18068 1/1 reg_we_check[53] = prio53_we;
Tests: T2 T4 T5
18069 1/1 reg_we_check[54] = prio54_we;
Tests: T2 T4 T5
18070 1/1 reg_we_check[55] = prio55_we;
Tests: T2 T4 T5
18071 1/1 reg_we_check[56] = prio56_we;
Tests: T2 T4 T5
18072 1/1 reg_we_check[57] = prio57_we;
Tests: T2 T4 T5
18073 1/1 reg_we_check[58] = prio58_we;
Tests: T2 T4 T5
18074 1/1 reg_we_check[59] = prio59_we;
Tests: T2 T4 T5
18075 1/1 reg_we_check[60] = prio60_we;
Tests: T2 T4 T5
18076 1/1 reg_we_check[61] = prio61_we;
Tests: T2 T4 T5
18077 1/1 reg_we_check[62] = prio62_we;
Tests: T2 T4 T5
18078 1/1 reg_we_check[63] = prio63_we;
Tests: T2 T4 T5
18079 1/1 reg_we_check[64] = prio64_we;
Tests: T2 T4 T5
18080 1/1 reg_we_check[65] = prio65_we;
Tests: T2 T4 T5
18081 1/1 reg_we_check[66] = prio66_we;
Tests: T2 T4 T5
18082 1/1 reg_we_check[67] = prio67_we;
Tests: T2 T4 T5
18083 1/1 reg_we_check[68] = prio68_we;
Tests: T2 T4 T5
18084 1/1 reg_we_check[69] = prio69_we;
Tests: T2 T4 T5
18085 1/1 reg_we_check[70] = prio70_we;
Tests: T2 T4 T5
18086 1/1 reg_we_check[71] = prio71_we;
Tests: T2 T4 T5
18087 1/1 reg_we_check[72] = prio72_we;
Tests: T2 T4 T5
18088 1/1 reg_we_check[73] = prio73_we;
Tests: T2 T4 T5
18089 1/1 reg_we_check[74] = prio74_we;
Tests: T2 T4 T5
18090 1/1 reg_we_check[75] = prio75_we;
Tests: T2 T4 T5
18091 1/1 reg_we_check[76] = prio76_we;
Tests: T2 T4 T5
18092 1/1 reg_we_check[77] = prio77_we;
Tests: T2 T4 T5
18093 1/1 reg_we_check[78] = prio78_we;
Tests: T2 T4 T5
18094 1/1 reg_we_check[79] = prio79_we;
Tests: T2 T4 T5
18095 1/1 reg_we_check[80] = prio80_we;
Tests: T2 T4 T5
18096 1/1 reg_we_check[81] = prio81_we;
Tests: T2 T4 T5
18097 1/1 reg_we_check[82] = prio82_we;
Tests: T2 T4 T5
18098 1/1 reg_we_check[83] = prio83_we;
Tests: T2 T4 T5
18099 1/1 reg_we_check[84] = prio84_we;
Tests: T2 T4 T5
18100 1/1 reg_we_check[85] = prio85_we;
Tests: T2 T4 T5
18101 1/1 reg_we_check[86] = prio86_we;
Tests: T2 T4 T5
18102 1/1 reg_we_check[87] = prio87_we;
Tests: T2 T4 T5
18103 1/1 reg_we_check[88] = prio88_we;
Tests: T2 T4 T5
18104 1/1 reg_we_check[89] = prio89_we;
Tests: T2 T4 T5
18105 1/1 reg_we_check[90] = prio90_we;
Tests: T2 T4 T5
18106 1/1 reg_we_check[91] = prio91_we;
Tests: T2 T4 T5
18107 1/1 reg_we_check[92] = prio92_we;
Tests: T2 T4 T5
18108 1/1 reg_we_check[93] = prio93_we;
Tests: T2 T4 T5
18109 1/1 reg_we_check[94] = prio94_we;
Tests: T2 T4 T5
18110 1/1 reg_we_check[95] = prio95_we;
Tests: T2 T4 T5
18111 1/1 reg_we_check[96] = prio96_we;
Tests: T2 T4 T5
18112 1/1 reg_we_check[97] = prio97_we;
Tests: T2 T4 T5
18113 1/1 reg_we_check[98] = prio98_we;
Tests: T2 T4 T5
18114 1/1 reg_we_check[99] = prio99_we;
Tests: T2 T4 T5
18115 1/1 reg_we_check[100] = prio100_we;
Tests: T2 T4 T5
18116 1/1 reg_we_check[101] = prio101_we;
Tests: T2 T4 T5
18117 1/1 reg_we_check[102] = prio102_we;
Tests: T2 T4 T5
18118 1/1 reg_we_check[103] = prio103_we;
Tests: T2 T4 T5
18119 1/1 reg_we_check[104] = prio104_we;
Tests: T2 T4 T5
18120 1/1 reg_we_check[105] = prio105_we;
Tests: T2 T4 T5
18121 1/1 reg_we_check[106] = prio106_we;
Tests: T2 T4 T5
18122 1/1 reg_we_check[107] = prio107_we;
Tests: T2 T4 T5
18123 1/1 reg_we_check[108] = prio108_we;
Tests: T2 T4 T5
18124 1/1 reg_we_check[109] = prio109_we;
Tests: T2 T4 T5
18125 1/1 reg_we_check[110] = prio110_we;
Tests: T2 T4 T5
18126 1/1 reg_we_check[111] = prio111_we;
Tests: T2 T4 T5
18127 1/1 reg_we_check[112] = prio112_we;
Tests: T2 T4 T5
18128 1/1 reg_we_check[113] = prio113_we;
Tests: T2 T4 T5
18129 1/1 reg_we_check[114] = prio114_we;
Tests: T2 T4 T5
18130 1/1 reg_we_check[115] = prio115_we;
Tests: T2 T4 T5
18131 1/1 reg_we_check[116] = prio116_we;
Tests: T2 T4 T5
18132 1/1 reg_we_check[117] = prio117_we;
Tests: T2 T4 T5
18133 1/1 reg_we_check[118] = prio118_we;
Tests: T2 T4 T5
18134 1/1 reg_we_check[119] = prio119_we;
Tests: T2 T4 T5
18135 1/1 reg_we_check[120] = prio120_we;
Tests: T2 T4 T5
18136 1/1 reg_we_check[121] = prio121_we;
Tests: T2 T4 T5
18137 1/1 reg_we_check[122] = prio122_we;
Tests: T2 T4 T5
18138 1/1 reg_we_check[123] = prio123_we;
Tests: T2 T4 T5
18139 1/1 reg_we_check[124] = prio124_we;
Tests: T2 T4 T5
18140 1/1 reg_we_check[125] = prio125_we;
Tests: T2 T4 T5
18141 1/1 reg_we_check[126] = prio126_we;
Tests: T2 T4 T5
18142 1/1 reg_we_check[127] = prio127_we;
Tests: T2 T4 T5
18143 1/1 reg_we_check[128] = prio128_we;
Tests: T2 T4 T5
18144 1/1 reg_we_check[129] = prio129_we;
Tests: T2 T4 T5
18145 1/1 reg_we_check[130] = prio130_we;
Tests: T2 T4 T5
18146 1/1 reg_we_check[131] = prio131_we;
Tests: T2 T4 T5
18147 1/1 reg_we_check[132] = prio132_we;
Tests: T2 T4 T5
18148 1/1 reg_we_check[133] = prio133_we;
Tests: T2 T4 T5
18149 1/1 reg_we_check[134] = prio134_we;
Tests: T2 T4 T5
18150 1/1 reg_we_check[135] = prio135_we;
Tests: T2 T4 T5
18151 1/1 reg_we_check[136] = prio136_we;
Tests: T2 T4 T5
18152 1/1 reg_we_check[137] = prio137_we;
Tests: T2 T4 T5
18153 1/1 reg_we_check[138] = prio138_we;
Tests: T2 T4 T5
18154 1/1 reg_we_check[139] = prio139_we;
Tests: T2 T4 T5
18155 1/1 reg_we_check[140] = prio140_we;
Tests: T2 T4 T5
18156 1/1 reg_we_check[141] = prio141_we;
Tests: T2 T4 T5
18157 1/1 reg_we_check[142] = prio142_we;
Tests: T2 T4 T5
18158 1/1 reg_we_check[143] = prio143_we;
Tests: T2 T4 T5
18159 1/1 reg_we_check[144] = prio144_we;
Tests: T2 T4 T5
18160 1/1 reg_we_check[145] = prio145_we;
Tests: T2 T4 T5
18161 1/1 reg_we_check[146] = prio146_we;
Tests: T2 T4 T5
18162 1/1 reg_we_check[147] = prio147_we;
Tests: T2 T4 T5
18163 1/1 reg_we_check[148] = prio148_we;
Tests: T2 T4 T5
18164 1/1 reg_we_check[149] = prio149_we;
Tests: T2 T4 T5
18165 1/1 reg_we_check[150] = prio150_we;
Tests: T2 T4 T5
18166 1/1 reg_we_check[151] = prio151_we;
Tests: T2 T4 T5
18167 1/1 reg_we_check[152] = prio152_we;
Tests: T2 T4 T5
18168 1/1 reg_we_check[153] = prio153_we;
Tests: T2 T4 T5
18169 1/1 reg_we_check[154] = prio154_we;
Tests: T2 T4 T5
18170 1/1 reg_we_check[155] = prio155_we;
Tests: T2 T4 T5
18171 1/1 reg_we_check[156] = prio156_we;
Tests: T2 T4 T5
18172 1/1 reg_we_check[157] = prio157_we;
Tests: T2 T4 T5
18173 1/1 reg_we_check[158] = prio158_we;
Tests: T2 T4 T5
18174 1/1 reg_we_check[159] = prio159_we;
Tests: T2 T4 T5
18175 1/1 reg_we_check[160] = prio160_we;
Tests: T2 T4 T5
18176 1/1 reg_we_check[161] = prio161_we;
Tests: T2 T4 T5
18177 1/1 reg_we_check[162] = prio162_we;
Tests: T2 T4 T5
18178 1/1 reg_we_check[163] = prio163_we;
Tests: T2 T4 T5
18179 1/1 reg_we_check[164] = prio164_we;
Tests: T2 T4 T5
18180 1/1 reg_we_check[165] = prio165_we;
Tests: T2 T4 T5
18181 1/1 reg_we_check[166] = prio166_we;
Tests: T2 T4 T5
18182 1/1 reg_we_check[167] = prio167_we;
Tests: T2 T4 T5
18183 1/1 reg_we_check[168] = prio168_we;
Tests: T2 T4 T5
18184 1/1 reg_we_check[169] = prio169_we;
Tests: T2 T4 T5
18185 1/1 reg_we_check[170] = prio170_we;
Tests: T2 T4 T5
18186 1/1 reg_we_check[171] = prio171_we;
Tests: T2 T4 T5
18187 1/1 reg_we_check[172] = prio172_we;
Tests: T2 T4 T5
18188 1/1 reg_we_check[173] = prio173_we;
Tests: T2 T4 T5
18189 1/1 reg_we_check[174] = prio174_we;
Tests: T2 T4 T5
18190 1/1 reg_we_check[175] = prio175_we;
Tests: T2 T4 T5
18191 1/1 reg_we_check[176] = prio176_we;
Tests: T2 T4 T5
18192 1/1 reg_we_check[177] = prio177_we;
Tests: T2 T4 T5
18193 1/1 reg_we_check[178] = prio178_we;
Tests: T2 T4 T5
18194 1/1 reg_we_check[179] = prio179_we;
Tests: T2 T4 T5
18195 1/1 reg_we_check[180] = prio180_we;
Tests: T2 T4 T5
18196 1/1 reg_we_check[181] = prio181_we;
Tests: T2 T4 T5
18197 1/1 reg_we_check[182] = prio182_we;
Tests: T2 T4 T5
18198 1/1 reg_we_check[183] = prio183_we;
Tests: T2 T4 T5
18199 1/1 reg_we_check[184] = prio184_we;
Tests: T2 T4 T5
18200 1/1 reg_we_check[185] = prio185_we;
Tests: T2 T4 T5
18201 1/1 reg_we_check[186] = 1'b0;
Tests: T2 T4 T5
18202 1/1 reg_we_check[187] = 1'b0;
Tests: T2 T4 T5
18203 1/1 reg_we_check[188] = 1'b0;
Tests: T2 T4 T5
18204 1/1 reg_we_check[189] = 1'b0;
Tests: T2 T4 T5
18205 1/1 reg_we_check[190] = 1'b0;
Tests: T2 T4 T5
18206 1/1 reg_we_check[191] = 1'b0;
Tests: T2 T4 T5
18207 1/1 reg_we_check[192] = ie0_0_we;
Tests: T2 T4 T5
18208 1/1 reg_we_check[193] = ie0_1_we;
Tests: T2 T4 T5
18209 1/1 reg_we_check[194] = ie0_2_we;
Tests: T2 T4 T5
18210 1/1 reg_we_check[195] = ie0_3_we;
Tests: T2 T4 T5
18211 1/1 reg_we_check[196] = ie0_4_we;
Tests: T2 T4 T5
18212 1/1 reg_we_check[197] = ie0_5_we;
Tests: T2 T4 T5
18213 1/1 reg_we_check[198] = threshold0_we;
Tests: T2 T4 T5
18214 1/1 reg_we_check[199] = cc0_we;
Tests: T2 T4 T5
18215 1/1 reg_we_check[200] = msip0_we;
Tests: T2 T4 T5
18216 1/1 reg_we_check[201] = alert_test_we;
Tests: T2 T4 T5
18217 end
18218
18219 // Read data return
18220 always_comb begin
18221 1/1 reg_rdata_next = '0;
Tests: T2 T4 T5
18222 1/1 unique case (1'b1)
Tests: T2 T4 T5
18223 addr_hit[0]: begin
18224 1/1 reg_rdata_next[1:0] = prio0_qs;
Tests: T2 T4 T5
18225 end
18226
18227 addr_hit[1]: begin
18228 1/1 reg_rdata_next[1:0] = prio1_qs;
Tests: T133 T249 T131
18229 end
18230
18231 addr_hit[2]: begin
18232 1/1 reg_rdata_next[1:0] = prio2_qs;
Tests: T133 T249 T131
18233 end
18234
18235 addr_hit[3]: begin
18236 1/1 reg_rdata_next[1:0] = prio3_qs;
Tests: T133 T249 T131
18237 end
18238
18239 addr_hit[4]: begin
18240 1/1 reg_rdata_next[1:0] = prio4_qs;
Tests: T133 T249 T131
18241 end
18242
18243 addr_hit[5]: begin
18244 1/1 reg_rdata_next[1:0] = prio5_qs;
Tests: T133 T249 T131
18245 end
18246
18247 addr_hit[6]: begin
18248 1/1 reg_rdata_next[1:0] = prio6_qs;
Tests: T133 T249 T131
18249 end
18250
18251 addr_hit[7]: begin
18252 1/1 reg_rdata_next[1:0] = prio7_qs;
Tests: T133 T249 T131
18253 end
18254
18255 addr_hit[8]: begin
18256 1/1 reg_rdata_next[1:0] = prio8_qs;
Tests: T133 T249 T131
18257 end
18258
18259 addr_hit[9]: begin
18260 1/1 reg_rdata_next[1:0] = prio9_qs;
Tests: T133 T249 T131
18261 end
18262
18263 addr_hit[10]: begin
18264 1/1 reg_rdata_next[1:0] = prio10_qs;
Tests: T134 T135 T249
18265 end
18266
18267 addr_hit[11]: begin
18268 1/1 reg_rdata_next[1:0] = prio11_qs;
Tests: T134 T135 T249
18269 end
18270
18271 addr_hit[12]: begin
18272 1/1 reg_rdata_next[1:0] = prio12_qs;
Tests: T134 T135 T249
18273 end
18274
18275 addr_hit[13]: begin
18276 1/1 reg_rdata_next[1:0] = prio13_qs;
Tests: T134 T135 T249
18277 end
18278
18279 addr_hit[14]: begin
18280 1/1 reg_rdata_next[1:0] = prio14_qs;
Tests: T134 T135 T249
18281 end
18282
18283 addr_hit[15]: begin
18284 1/1 reg_rdata_next[1:0] = prio15_qs;
Tests: T134 T135 T249
18285 end
18286
18287 addr_hit[16]: begin
18288 1/1 reg_rdata_next[1:0] = prio16_qs;
Tests: T134 T135 T249
18289 end
18290
18291 addr_hit[17]: begin
18292 1/1 reg_rdata_next[1:0] = prio17_qs;
Tests: T134 T135 T249
18293 end
18294
18295 addr_hit[18]: begin
18296 1/1 reg_rdata_next[1:0] = prio18_qs;
Tests: T134 T135 T249
18297 end
18298
18299 addr_hit[19]: begin
18300 1/1 reg_rdata_next[1:0] = prio19_qs;
Tests: T68 T249 T131
18301 end
18302
18303 addr_hit[20]: begin
18304 1/1 reg_rdata_next[1:0] = prio20_qs;
Tests: T68 T249 T131
18305 end
18306
18307 addr_hit[21]: begin
18308 1/1 reg_rdata_next[1:0] = prio21_qs;
Tests: T68 T249 T131
18309 end
18310
18311 addr_hit[22]: begin
18312 1/1 reg_rdata_next[1:0] = prio22_qs;
Tests: T68 T249 T131
18313 end
18314
18315 addr_hit[23]: begin
18316 1/1 reg_rdata_next[1:0] = prio23_qs;
Tests: T68 T249 T131
18317 end
18318
18319 addr_hit[24]: begin
18320 1/1 reg_rdata_next[1:0] = prio24_qs;
Tests: T68 T249 T131
18321 end
18322
18323 addr_hit[25]: begin
18324 1/1 reg_rdata_next[1:0] = prio25_qs;
Tests: T68 T249 T131
18325 end
18326
18327 addr_hit[26]: begin
18328 1/1 reg_rdata_next[1:0] = prio26_qs;
Tests: T68 T249 T131
18329 end
18330
18331 addr_hit[27]: begin
18332 1/1 reg_rdata_next[1:0] = prio27_qs;
Tests: T68 T249 T131
18333 end
18334
18335 addr_hit[28]: begin
18336 1/1 reg_rdata_next[1:0] = prio28_qs;
Tests: T26 T70 T249
18337 end
18338
18339 addr_hit[29]: begin
18340 1/1 reg_rdata_next[1:0] = prio29_qs;
Tests: T26 T70 T249
18341 end
18342
18343 addr_hit[30]: begin
18344 1/1 reg_rdata_next[1:0] = prio30_qs;
Tests: T26 T70 T249
18345 end
18346
18347 addr_hit[31]: begin
18348 1/1 reg_rdata_next[1:0] = prio31_qs;
Tests: T26 T70 T249
18349 end
18350
18351 addr_hit[32]: begin
18352 1/1 reg_rdata_next[1:0] = prio32_qs;
Tests: T26 T70 T249
18353 end
18354
18355 addr_hit[33]: begin
18356 1/1 reg_rdata_next[1:0] = prio33_qs;
Tests: T26 T70 T249
18357 end
18358
18359 addr_hit[34]: begin
18360 1/1 reg_rdata_next[1:0] = prio34_qs;
Tests: T26 T70 T249
18361 end
18362
18363 addr_hit[35]: begin
18364 1/1 reg_rdata_next[1:0] = prio35_qs;
Tests: T26 T70 T249
18365 end
18366
18367 addr_hit[36]: begin
18368 1/1 reg_rdata_next[1:0] = prio36_qs;
Tests: T26 T70 T249
18369 end
18370
18371 addr_hit[37]: begin
18372 1/1 reg_rdata_next[1:0] = prio37_qs;
Tests: T27 T249 T131
18373 end
18374
18375 addr_hit[38]: begin
18376 1/1 reg_rdata_next[1:0] = prio38_qs;
Tests: T27 T249 T131
18377 end
18378
18379 addr_hit[39]: begin
18380 1/1 reg_rdata_next[1:0] = prio39_qs;
Tests: T27 T249 T131
18381 end
18382
18383 addr_hit[40]: begin
18384 1/1 reg_rdata_next[1:0] = prio40_qs;
Tests: T27 T249 T131
18385 end
18386
18387 addr_hit[41]: begin
18388 1/1 reg_rdata_next[1:0] = prio41_qs;
Tests: T27 T249 T131
18389 end
18390
18391 addr_hit[42]: begin
18392 1/1 reg_rdata_next[1:0] = prio42_qs;
Tests: T27 T249 T131
18393 end
18394
18395 addr_hit[43]: begin
18396 1/1 reg_rdata_next[1:0] = prio43_qs;
Tests: T27 T249 T131
18397 end
18398
18399 addr_hit[44]: begin
18400 1/1 reg_rdata_next[1:0] = prio44_qs;
Tests: T27 T249 T131
18401 end
18402
18403 addr_hit[45]: begin
18404 1/1 reg_rdata_next[1:0] = prio45_qs;
Tests: T27 T249 T131
18405 end
18406
18407 addr_hit[46]: begin
18408 1/1 reg_rdata_next[1:0] = prio46_qs;
Tests: T27 T249 T131
18409 end
18410
18411 addr_hit[47]: begin
18412 1/1 reg_rdata_next[1:0] = prio47_qs;
Tests: T27 T249 T131
18413 end
18414
18415 addr_hit[48]: begin
18416 1/1 reg_rdata_next[1:0] = prio48_qs;
Tests: T27 T249 T131
18417 end
18418
18419 addr_hit[49]: begin
18420 1/1 reg_rdata_next[1:0] = prio49_qs;
Tests: T27 T249 T131
18421 end
18422
18423 addr_hit[50]: begin
18424 1/1 reg_rdata_next[1:0] = prio50_qs;
Tests: T27 T249 T131
18425 end
18426
18427 addr_hit[51]: begin
18428 1/1 reg_rdata_next[1:0] = prio51_qs;
Tests: T27 T249 T131
18429 end
18430
18431 addr_hit[52]: begin
18432 1/1 reg_rdata_next[1:0] = prio52_qs;
Tests: T27 T249 T131
18433 end
18434
18435 addr_hit[53]: begin
18436 1/1 reg_rdata_next[1:0] = prio53_qs;
Tests: T27 T249 T131
18437 end
18438
18439 addr_hit[54]: begin
18440 1/1 reg_rdata_next[1:0] = prio54_qs;
Tests: T27 T249 T131
18441 end
18442
18443 addr_hit[55]: begin
18444 1/1 reg_rdata_next[1:0] = prio55_qs;
Tests: T27 T249 T131
18445 end
18446
18447 addr_hit[56]: begin
18448 1/1 reg_rdata_next[1:0] = prio56_qs;
Tests: T27 T249 T131
18449 end
18450
18451 addr_hit[57]: begin
18452 1/1 reg_rdata_next[1:0] = prio57_qs;
Tests: T27 T249 T131
18453 end
18454
18455 addr_hit[58]: begin
18456 1/1 reg_rdata_next[1:0] = prio58_qs;
Tests: T27 T249 T131
18457 end
18458
18459 addr_hit[59]: begin
18460 1/1 reg_rdata_next[1:0] = prio59_qs;
Tests: T27 T249 T131
18461 end
18462
18463 addr_hit[60]: begin
18464 1/1 reg_rdata_next[1:0] = prio60_qs;
Tests: T27 T249 T131
18465 end
18466
18467 addr_hit[61]: begin
18468 1/1 reg_rdata_next[1:0] = prio61_qs;
Tests: T27 T249 T131
18469 end
18470
18471 addr_hit[62]: begin
18472 1/1 reg_rdata_next[1:0] = prio62_qs;
Tests: T27 T249 T131
18473 end
18474
18475 addr_hit[63]: begin
18476 1/1 reg_rdata_next[1:0] = prio63_qs;
Tests: T27 T249 T131
18477 end
18478
18479 addr_hit[64]: begin
18480 1/1 reg_rdata_next[1:0] = prio64_qs;
Tests: T27 T249 T131
18481 end
18482
18483 addr_hit[65]: begin
18484 1/1 reg_rdata_next[1:0] = prio65_qs;
Tests: T27 T249 T131
18485 end
18486
18487 addr_hit[66]: begin
18488 1/1 reg_rdata_next[1:0] = prio66_qs;
Tests: T27 T249 T131
18489 end
18490
18491 addr_hit[67]: begin
18492 1/1 reg_rdata_next[1:0] = prio67_qs;
Tests: T27 T249 T131
18493 end
18494
18495 addr_hit[68]: begin
18496 1/1 reg_rdata_next[1:0] = prio68_qs;
Tests: T27 T249 T131
18497 end
18498
18499 addr_hit[69]: begin
18500 1/1 reg_rdata_next[1:0] = prio69_qs;
Tests: T12 T27 T10
18501 end
18502
18503 addr_hit[70]: begin
18504 1/1 reg_rdata_next[1:0] = prio70_qs;
Tests: T12 T249 T131
18505 end
18506
18507 addr_hit[71]: begin
18508 1/1 reg_rdata_next[1:0] = prio71_qs;
Tests: T12 T249 T131
18509 end
18510
18511 addr_hit[72]: begin
18512 1/1 reg_rdata_next[1:0] = prio72_qs;
Tests: T12 T10 T11
18513 end
18514
18515 addr_hit[73]: begin
18516 1/1 reg_rdata_next[1:0] = prio73_qs;
Tests: T12 T10 T11
18517 end
18518
18519 addr_hit[74]: begin
18520 1/1 reg_rdata_next[1:0] = prio74_qs;
Tests: T12 T249 T131
18521 end
18522
18523 addr_hit[75]: begin
18524 1/1 reg_rdata_next[1:0] = prio75_qs;
Tests: T249 T131 T252
18525 end
18526
18527 addr_hit[76]: begin
18528 1/1 reg_rdata_next[1:0] = prio76_qs;
Tests: T249 T131 T252
18529 end
18530
18531 addr_hit[77]: begin
18532 1/1 reg_rdata_next[1:0] = prio77_qs;
Tests: T62 T249 T131
18533 end
18534
18535 addr_hit[78]: begin
18536 1/1 reg_rdata_next[1:0] = prio78_qs;
Tests: T62 T249 T131
18537 end
18538
18539 addr_hit[79]: begin
18540 1/1 reg_rdata_next[1:0] = prio79_qs;
Tests: T249 T131 T252
18541 end
18542
18543 addr_hit[80]: begin
18544 1/1 reg_rdata_next[1:0] = prio80_qs;
Tests: T62 T249 T131
18545 end
18546
18547 addr_hit[81]: begin
18548 1/1 reg_rdata_next[1:0] = prio81_qs;
Tests: T62 T249 T131
18549 end
18550
18551 addr_hit[82]: begin
18552 1/1 reg_rdata_next[1:0] = prio82_qs;
Tests: T62 T249 T131
18553 end
18554
18555 addr_hit[83]: begin
18556 1/1 reg_rdata_next[1:0] = prio83_qs;
Tests: T62 T249 T131
18557 end
18558
18559 addr_hit[84]: begin
18560 1/1 reg_rdata_next[1:0] = prio84_qs;
Tests: T62 T249 T131
18561 end
18562
18563 addr_hit[85]: begin
18564 1/1 reg_rdata_next[1:0] = prio85_qs;
Tests: T249 T131 T252
18565 end
18566
18567 addr_hit[86]: begin
18568 1/1 reg_rdata_next[1:0] = prio86_qs;
Tests: T62 T249 T131
18569 end
18570
18571 addr_hit[87]: begin
18572 1/1 reg_rdata_next[1:0] = prio87_qs;
Tests: T249 T131 T252
18573 end
18574
18575 addr_hit[88]: begin
18576 1/1 reg_rdata_next[1:0] = prio88_qs;
Tests: T249 T131 T252
18577 end
18578
18579 addr_hit[89]: begin
18580 1/1 reg_rdata_next[1:0] = prio89_qs;
Tests: T249 T131 T252
18581 end
18582
18583 addr_hit[90]: begin
18584 1/1 reg_rdata_next[1:0] = prio90_qs;
Tests: T249 T131 T252
18585 end
18586
18587 addr_hit[91]: begin
18588 1/1 reg_rdata_next[1:0] = prio91_qs;
Tests: T249 T131 T252
18589 end
18590
18591 addr_hit[92]: begin
18592 1/1 reg_rdata_next[1:0] = prio92_qs;
Tests: T65 T249 T131
18593 end
18594
18595 addr_hit[93]: begin
18596 1/1 reg_rdata_next[1:0] = prio93_qs;
Tests: T65 T249 T131
18597 end
18598
18599 addr_hit[94]: begin
18600 1/1 reg_rdata_next[1:0] = prio94_qs;
Tests: T249 T131 T252
18601 end
18602
18603 addr_hit[95]: begin
18604 1/1 reg_rdata_next[1:0] = prio95_qs;
Tests: T65 T249 T131
18605 end
18606
18607 addr_hit[96]: begin
18608 1/1 reg_rdata_next[1:0] = prio96_qs;
Tests: T65 T249 T131
18609 end
18610
18611 addr_hit[97]: begin
18612 1/1 reg_rdata_next[1:0] = prio97_qs;
Tests: T65 T249 T131
18613 end
18614
18615 addr_hit[98]: begin
18616 1/1 reg_rdata_next[1:0] = prio98_qs;
Tests: T65 T249 T131
18617 end
18618
18619 addr_hit[99]: begin
18620 1/1 reg_rdata_next[1:0] = prio99_qs;
Tests: T65 T249 T131
18621 end
18622
18623 addr_hit[100]: begin
18624 1/1 reg_rdata_next[1:0] = prio100_qs;
Tests: T249 T131 T252
18625 end
18626
18627 addr_hit[101]: begin
18628 1/1 reg_rdata_next[1:0] = prio101_qs;
Tests: T64 T65 T249
18629 end
18630
18631 addr_hit[102]: begin
18632 1/1 reg_rdata_next[1:0] = prio102_qs;
Tests: T64 T249 T131
18633 end
18634
18635 addr_hit[103]: begin
18636 1/1 reg_rdata_next[1:0] = prio103_qs;
Tests: T249 T131 T252
18637 end
18638
18639 addr_hit[104]: begin
18640 1/1 reg_rdata_next[1:0] = prio104_qs;
Tests: T64 T249 T131
18641 end
18642
18643 addr_hit[105]: begin
18644 1/1 reg_rdata_next[1:0] = prio105_qs;
Tests: T64 T249 T131
18645 end
18646
18647 addr_hit[106]: begin
18648 1/1 reg_rdata_next[1:0] = prio106_qs;
Tests: T64 T249 T131
18649 end
18650
18651 addr_hit[107]: begin
18652 1/1 reg_rdata_next[1:0] = prio107_qs;
Tests: T66 T249 T131
18653 end
18654
18655 addr_hit[108]: begin
18656 1/1 reg_rdata_next[1:0] = prio108_qs;
Tests: T66 T249 T131
18657 end
18658
18659 addr_hit[109]: begin
18660 1/1 reg_rdata_next[1:0] = prio109_qs;
Tests: T249 T131 T252
18661 end
18662
18663 addr_hit[110]: begin
18664 1/1 reg_rdata_next[1:0] = prio110_qs;
Tests: T66 T249 T131
18665 end
18666
18667 addr_hit[111]: begin
18668 1/1 reg_rdata_next[1:0] = prio111_qs;
Tests: T66 T249 T131
18669 end
18670
18671 addr_hit[112]: begin
18672 1/1 reg_rdata_next[1:0] = prio112_qs;
Tests: T66 T249 T131
18673 end
18674
18675 addr_hit[113]: begin
18676 1/1 reg_rdata_next[1:0] = prio113_qs;
Tests: T66 T249 T131
18677 end
18678
18679 addr_hit[114]: begin
18680 1/1 reg_rdata_next[1:0] = prio114_qs;
Tests: T66 T249 T131
18681 end
18682
18683 addr_hit[115]: begin
18684 1/1 reg_rdata_next[1:0] = prio115_qs;
Tests: T249 T131 T252
18685 end
18686
18687 addr_hit[116]: begin
18688 1/1 reg_rdata_next[1:0] = prio116_qs;
Tests: T66 T249 T131
18689 end
18690
18691 addr_hit[117]: begin
18692 1/1 reg_rdata_next[1:0] = prio117_qs;
Tests: T249 T131 T252
18693 end
18694
18695 addr_hit[118]: begin
18696 1/1 reg_rdata_next[1:0] = prio118_qs;
Tests: T249 T131 T252
18697 end
18698
18699 addr_hit[119]: begin
18700 1/1 reg_rdata_next[1:0] = prio119_qs;
Tests: T249 T131 T252
18701 end
18702
18703 addr_hit[120]: begin
18704 1/1 reg_rdata_next[1:0] = prio120_qs;
Tests: T249 T131 T252
18705 end
18706
18707 addr_hit[121]: begin
18708 1/1 reg_rdata_next[1:0] = prio121_qs;
Tests: T249 T131 T252
18709 end
18710
18711 addr_hit[122]: begin
18712 1/1 reg_rdata_next[1:0] = prio122_qs;
Tests: T5 T249 T131
18713 end
18714
18715 addr_hit[123]: begin
18716 1/1 reg_rdata_next[1:0] = prio123_qs;
Tests: T5 T249 T131
18717 end
18718
18719 addr_hit[124]: begin
18720 1/1 reg_rdata_next[1:0] = prio124_qs;
Tests: T249 T131 T252
18721 end
18722
18723 addr_hit[125]: begin
18724 1/1 reg_rdata_next[1:0] = prio125_qs;
Tests: T249 T131 T252
18725 end
18726
18727 addr_hit[126]: begin
18728 1/1 reg_rdata_next[1:0] = prio126_qs;
Tests: T249 T131 T252
18729 end
18730
18731 addr_hit[127]: begin
18732 1/1 reg_rdata_next[1:0] = prio127_qs;
Tests: T45 T86 T87
18733 end
18734
18735 addr_hit[128]: begin
18736 1/1 reg_rdata_next[1:0] = prio128_qs;
Tests: T45 T86 T87
18737 end
18738
18739 addr_hit[129]: begin
18740 1/1 reg_rdata_next[1:0] = prio129_qs;
Tests: T45 T86 T87
18741 end
18742
18743 addr_hit[130]: begin
18744 1/1 reg_rdata_next[1:0] = prio130_qs;
Tests: T45 T86 T87
18745 end
18746
18747 addr_hit[131]: begin
18748 1/1 reg_rdata_next[1:0] = prio131_qs;
Tests: T10 T11 T249
18749 end
18750
18751 addr_hit[132]: begin
18752 1/1 reg_rdata_next[1:0] = prio132_qs;
Tests: T10 T11 T249
18753 end
18754
18755 addr_hit[133]: begin
18756 1/1 reg_rdata_next[1:0] = prio133_qs;
Tests: T249 T131 T252
18757 end
18758
18759 addr_hit[134]: begin
18760 1/1 reg_rdata_next[1:0] = prio134_qs;
Tests: T249 T131 T252
18761 end
18762
18763 addr_hit[135]: begin
18764 1/1 reg_rdata_next[1:0] = prio135_qs;
Tests: T249 T131 T252
18765 end
18766
18767 addr_hit[136]: begin
18768 1/1 reg_rdata_next[1:0] = prio136_qs;
Tests: T249 T131 T252
18769 end
18770
18771 addr_hit[137]: begin
18772 1/1 reg_rdata_next[1:0] = prio137_qs;
Tests: T249 T131 T252
18773 end
18774
18775 addr_hit[138]: begin
18776 1/1 reg_rdata_next[1:0] = prio138_qs;
Tests: T249 T131 T252
18777 end
18778
18779 addr_hit[139]: begin
18780 1/1 reg_rdata_next[1:0] = prio139_qs;
Tests: T249 T131 T252
18781 end
18782
18783 addr_hit[140]: begin
18784 1/1 reg_rdata_next[1:0] = prio140_qs;
Tests: T249 T131 T252
18785 end
18786
18787 addr_hit[141]: begin
18788 1/1 reg_rdata_next[1:0] = prio141_qs;
Tests: T249 T131 T252
18789 end
18790
18791 addr_hit[142]: begin
18792 1/1 reg_rdata_next[1:0] = prio142_qs;
Tests: T249 T131 T252
18793 end
18794
18795 addr_hit[143]: begin
18796 1/1 reg_rdata_next[1:0] = prio143_qs;
Tests: T249 T131 T252
18797 end
18798
18799 addr_hit[144]: begin
18800 1/1 reg_rdata_next[1:0] = prio144_qs;
Tests: T249 T131 T252
18801 end
18802
18803 addr_hit[145]: begin
18804 1/1 reg_rdata_next[1:0] = prio145_qs;
Tests: T249 T131 T252
18805 end
18806
18807 addr_hit[146]: begin
18808 1/1 reg_rdata_next[1:0] = prio146_qs;
Tests: T249 T131 T252
18809 end
18810
18811 addr_hit[147]: begin
18812 1/1 reg_rdata_next[1:0] = prio147_qs;
Tests: T249 T131 T252
18813 end
18814
18815 addr_hit[148]: begin
18816 1/1 reg_rdata_next[1:0] = prio148_qs;
Tests: T249 T131 T252
18817 end
18818
18819 addr_hit[149]: begin
18820 1/1 reg_rdata_next[1:0] = prio149_qs;
Tests: T249 T131 T252
18821 end
18822
18823 addr_hit[150]: begin
18824 1/1 reg_rdata_next[1:0] = prio150_qs;
Tests: T249 T131 T252
18825 end
18826
18827 addr_hit[151]: begin
18828 1/1 reg_rdata_next[1:0] = prio151_qs;
Tests: T249 T131 T252
18829 end
18830
18831 addr_hit[152]: begin
18832 1/1 reg_rdata_next[1:0] = prio152_qs;
Tests: T249 T131 T252
18833 end
18834
18835 addr_hit[153]: begin
18836 1/1 reg_rdata_next[1:0] = prio153_qs;
Tests: T2 T4 T6
18837 end
18838
18839 addr_hit[154]: begin
18840 1/1 reg_rdata_next[1:0] = prio154_qs;
Tests: T72 T249 T131
18841 end
18842
18843 addr_hit[155]: begin
18844 1/1 reg_rdata_next[1:0] = prio155_qs;
Tests: T145 T249 T131
18845 end
18846
18847 addr_hit[156]: begin
18848 1/1 reg_rdata_next[1:0] = prio156_qs;
Tests: T45 T86 T87
18849 end
18850
18851 addr_hit[157]: begin
18852 1/1 reg_rdata_next[1:0] = prio157_qs;
Tests: T45 T146 T86
18853 end
18854
18855 addr_hit[158]: begin
18856 1/1 reg_rdata_next[1:0] = prio158_qs;
Tests: T249 T186 T131
18857 end
18858
18859 addr_hit[159]: begin
18860 1/1 reg_rdata_next[1:0] = prio159_qs;
Tests: T249 T131 T252
18861 end
18862
18863 addr_hit[160]: begin
18864 1/1 reg_rdata_next[1:0] = prio160_qs;
Tests: T124 T153 T253
18865 end
18866
18867 addr_hit[161]: begin
18868 1/1 reg_rdata_next[1:0] = prio161_qs;
Tests: T124 T153 T253
18869 end
18870
18871 addr_hit[162]: begin
18872 1/1 reg_rdata_next[1:0] = prio162_qs;
Tests: T124 T153 T253
18873 end
18874
18875 addr_hit[163]: begin
18876 1/1 reg_rdata_next[1:0] = prio163_qs;
Tests: T124 T153 T253
18877 end
18878
18879 addr_hit[164]: begin
18880 1/1 reg_rdata_next[1:0] = prio164_qs;
Tests: T124 T153 T253
18881 end
18882
18883 addr_hit[165]: begin
18884 1/1 reg_rdata_next[1:0] = prio165_qs;
Tests: T249 T131 T252
18885 end
18886
18887 addr_hit[166]: begin
18888 1/1 reg_rdata_next[1:0] = prio166_qs;
Tests: T254 T255 T249
18889 end
18890
18891 addr_hit[167]: begin
18892 1/1 reg_rdata_next[1:0] = prio167_qs;
Tests: T254 T255 T249
18893 end
18894
18895 addr_hit[168]: begin
18896 1/1 reg_rdata_next[1:0] = prio168_qs;
Tests: T249 T131 T252
18897 end
18898
18899 addr_hit[169]: begin
18900 1/1 reg_rdata_next[1:0] = prio169_qs;
Tests: T249 T131 T252
18901 end
18902
18903 addr_hit[170]: begin
18904 1/1 reg_rdata_next[1:0] = prio170_qs;
Tests: T249 T131 T252
18905 end
18906
18907 addr_hit[171]: begin
18908 1/1 reg_rdata_next[1:0] = prio171_qs;
Tests: T249 T131 T252
18909 end
18910
18911 addr_hit[172]: begin
18912 1/1 reg_rdata_next[1:0] = prio172_qs;
Tests: T168 T249 T131
18913 end
18914
18915 addr_hit[173]: begin
18916 1/1 reg_rdata_next[1:0] = prio173_qs;
Tests: T249 T131 T252
18917 end
18918
18919 addr_hit[174]: begin
18920 1/1 reg_rdata_next[1:0] = prio174_qs;
Tests: T249 T131 T252
18921 end
18922
18923 addr_hit[175]: begin
18924 1/1 reg_rdata_next[1:0] = prio175_qs;
Tests: T249 T131 T252
18925 end
18926
18927 addr_hit[176]: begin
18928 1/1 reg_rdata_next[1:0] = prio176_qs;
Tests: T249 T131 T252
18929 end
18930
18931 addr_hit[177]: begin
18932 1/1 reg_rdata_next[1:0] = prio177_qs;
Tests: T249 T131 T252
18933 end
18934
18935 addr_hit[178]: begin
18936 1/1 reg_rdata_next[1:0] = prio178_qs;
Tests: T249 T131 T252
18937 end
18938
18939 addr_hit[179]: begin
18940 1/1 reg_rdata_next[1:0] = prio179_qs;
Tests: T249 T131 T252
18941 end
18942
18943 addr_hit[180]: begin
18944 1/1 reg_rdata_next[1:0] = prio180_qs;
Tests: T249 T131 T252
18945 end
18946
18947 addr_hit[181]: begin
18948 1/1 reg_rdata_next[1:0] = prio181_qs;
Tests: T249 T131 T252
18949 end
18950
18951 addr_hit[182]: begin
18952 1/1 reg_rdata_next[1:0] = prio182_qs;
Tests: T249 T131 T252
18953 end
18954
18955 addr_hit[183]: begin
18956 1/1 reg_rdata_next[1:0] = prio183_qs;
Tests: T249 T131 T252
18957 end
18958
18959 addr_hit[184]: begin
18960 1/1 reg_rdata_next[1:0] = prio184_qs;
Tests: T249 T131 T252
18961 end
18962
18963 addr_hit[185]: begin
18964 1/1 reg_rdata_next[1:0] = prio185_qs;
Tests: T249 T131 T252
18965 end
18966
18967 addr_hit[186]: begin
18968 1/1 reg_rdata_next[0] = ip_0_p_0_qs;
Tests: T410 T177 T179
18969 1/1 reg_rdata_next[1] = ip_0_p_1_qs;
Tests: T410 T177 T179
18970 1/1 reg_rdata_next[2] = ip_0_p_2_qs;
Tests: T410 T177 T179
18971 1/1 reg_rdata_next[3] = ip_0_p_3_qs;
Tests: T410 T177 T179
18972 1/1 reg_rdata_next[4] = ip_0_p_4_qs;
Tests: T410 T177 T179
18973 1/1 reg_rdata_next[5] = ip_0_p_5_qs;
Tests: T410 T177 T179
18974 1/1 reg_rdata_next[6] = ip_0_p_6_qs;
Tests: T410 T177 T179
18975 1/1 reg_rdata_next[7] = ip_0_p_7_qs;
Tests: T410 T177 T179
18976 1/1 reg_rdata_next[8] = ip_0_p_8_qs;
Tests: T410 T177 T179
18977 1/1 reg_rdata_next[9] = ip_0_p_9_qs;
Tests: T410 T177 T179
18978 1/1 reg_rdata_next[10] = ip_0_p_10_qs;
Tests: T410 T177 T179
18979 1/1 reg_rdata_next[11] = ip_0_p_11_qs;
Tests: T410 T177 T179
18980 1/1 reg_rdata_next[12] = ip_0_p_12_qs;
Tests: T410 T177 T179
18981 1/1 reg_rdata_next[13] = ip_0_p_13_qs;
Tests: T410 T177 T179
18982 1/1 reg_rdata_next[14] = ip_0_p_14_qs;
Tests: T410 T177 T179
18983 1/1 reg_rdata_next[15] = ip_0_p_15_qs;
Tests: T410 T177 T179
18984 1/1 reg_rdata_next[16] = ip_0_p_16_qs;
Tests: T410 T177 T179
18985 1/1 reg_rdata_next[17] = ip_0_p_17_qs;
Tests: T410 T177 T179
18986 1/1 reg_rdata_next[18] = ip_0_p_18_qs;
Tests: T410 T177 T179
18987 1/1 reg_rdata_next[19] = ip_0_p_19_qs;
Tests: T410 T177 T179
18988 1/1 reg_rdata_next[20] = ip_0_p_20_qs;
Tests: T410 T177 T179
18989 1/1 reg_rdata_next[21] = ip_0_p_21_qs;
Tests: T410 T177 T179
18990 1/1 reg_rdata_next[22] = ip_0_p_22_qs;
Tests: T410 T177 T179
18991 1/1 reg_rdata_next[23] = ip_0_p_23_qs;
Tests: T410 T177 T179
18992 1/1 reg_rdata_next[24] = ip_0_p_24_qs;
Tests: T410 T177 T179
18993 1/1 reg_rdata_next[25] = ip_0_p_25_qs;
Tests: T410 T177 T179
18994 1/1 reg_rdata_next[26] = ip_0_p_26_qs;
Tests: T410 T177 T179
18995 1/1 reg_rdata_next[27] = ip_0_p_27_qs;
Tests: T410 T177 T179
18996 1/1 reg_rdata_next[28] = ip_0_p_28_qs;
Tests: T410 T177 T179
18997 1/1 reg_rdata_next[29] = ip_0_p_29_qs;
Tests: T410 T177 T179
18998 1/1 reg_rdata_next[30] = ip_0_p_30_qs;
Tests: T410 T177 T179
18999 1/1 reg_rdata_next[31] = ip_0_p_31_qs;
Tests: T410 T177 T179
19000 end
19001
19002 addr_hit[187]: begin
19003 1/1 reg_rdata_next[0] = ip_1_p_32_qs;
Tests: T409 T410 T177
19004 1/1 reg_rdata_next[1] = ip_1_p_33_qs;
Tests: T409 T410 T177
19005 1/1 reg_rdata_next[2] = ip_1_p_34_qs;
Tests: T409 T410 T177
19006 1/1 reg_rdata_next[3] = ip_1_p_35_qs;
Tests: T409 T410 T177
19007 1/1 reg_rdata_next[4] = ip_1_p_36_qs;
Tests: T409 T410 T177
19008 1/1 reg_rdata_next[5] = ip_1_p_37_qs;
Tests: T409 T410 T177
19009 1/1 reg_rdata_next[6] = ip_1_p_38_qs;
Tests: T409 T410 T177
19010 1/1 reg_rdata_next[7] = ip_1_p_39_qs;
Tests: T409 T410 T177
19011 1/1 reg_rdata_next[8] = ip_1_p_40_qs;
Tests: T409 T410 T177
19012 1/1 reg_rdata_next[9] = ip_1_p_41_qs;
Tests: T409 T410 T177
19013 1/1 reg_rdata_next[10] = ip_1_p_42_qs;
Tests: T409 T410 T177
19014 1/1 reg_rdata_next[11] = ip_1_p_43_qs;
Tests: T409 T410 T177
19015 1/1 reg_rdata_next[12] = ip_1_p_44_qs;
Tests: T409 T410 T177
19016 1/1 reg_rdata_next[13] = ip_1_p_45_qs;
Tests: T409 T410 T177
19017 1/1 reg_rdata_next[14] = ip_1_p_46_qs;
Tests: T409 T410 T177
19018 1/1 reg_rdata_next[15] = ip_1_p_47_qs;
Tests: T409 T410 T177
19019 1/1 reg_rdata_next[16] = ip_1_p_48_qs;
Tests: T409 T410 T177
19020 1/1 reg_rdata_next[17] = ip_1_p_49_qs;
Tests: T409 T410 T177
19021 1/1 reg_rdata_next[18] = ip_1_p_50_qs;
Tests: T409 T410 T177
19022 1/1 reg_rdata_next[19] = ip_1_p_51_qs;
Tests: T409 T410 T177
19023 1/1 reg_rdata_next[20] = ip_1_p_52_qs;
Tests: T409 T410 T177
19024 1/1 reg_rdata_next[21] = ip_1_p_53_qs;
Tests: T409 T410 T177
19025 1/1 reg_rdata_next[22] = ip_1_p_54_qs;
Tests: T409 T410 T177
19026 1/1 reg_rdata_next[23] = ip_1_p_55_qs;
Tests: T409 T410 T177
19027 1/1 reg_rdata_next[24] = ip_1_p_56_qs;
Tests: T409 T410 T177
19028 1/1 reg_rdata_next[25] = ip_1_p_57_qs;
Tests: T409 T410 T177
19029 1/1 reg_rdata_next[26] = ip_1_p_58_qs;
Tests: T409 T410 T177
19030 1/1 reg_rdata_next[27] = ip_1_p_59_qs;
Tests: T409 T410 T177
19031 1/1 reg_rdata_next[28] = ip_1_p_60_qs;
Tests: T409 T410 T177
19032 1/1 reg_rdata_next[29] = ip_1_p_61_qs;
Tests: T409 T410 T177
19033 1/1 reg_rdata_next[30] = ip_1_p_62_qs;
Tests: T409 T410 T177
19034 1/1 reg_rdata_next[31] = ip_1_p_63_qs;
Tests: T409 T410 T177
19035 end
19036
19037 addr_hit[188]: begin
19038 1/1 reg_rdata_next[0] = ip_2_p_64_qs;
Tests: T409 T410 T177
19039 1/1 reg_rdata_next[1] = ip_2_p_65_qs;
Tests: T409 T410 T177
19040 1/1 reg_rdata_next[2] = ip_2_p_66_qs;
Tests: T409 T410 T177
19041 1/1 reg_rdata_next[3] = ip_2_p_67_qs;
Tests: T409 T410 T177
19042 1/1 reg_rdata_next[4] = ip_2_p_68_qs;
Tests: T409 T410 T177
19043 1/1 reg_rdata_next[5] = ip_2_p_69_qs;
Tests: T409 T410 T177
19044 1/1 reg_rdata_next[6] = ip_2_p_70_qs;
Tests: T409 T410 T177
19045 1/1 reg_rdata_next[7] = ip_2_p_71_qs;
Tests: T409 T410 T177
19046 1/1 reg_rdata_next[8] = ip_2_p_72_qs;
Tests: T409 T410 T177
19047 1/1 reg_rdata_next[9] = ip_2_p_73_qs;
Tests: T409 T410 T177
19048 1/1 reg_rdata_next[10] = ip_2_p_74_qs;
Tests: T409 T410 T177
19049 1/1 reg_rdata_next[11] = ip_2_p_75_qs;
Tests: T409 T410 T177
19050 1/1 reg_rdata_next[12] = ip_2_p_76_qs;
Tests: T409 T410 T177
19051 1/1 reg_rdata_next[13] = ip_2_p_77_qs;
Tests: T409 T410 T177
19052 1/1 reg_rdata_next[14] = ip_2_p_78_qs;
Tests: T409 T410 T177
19053 1/1 reg_rdata_next[15] = ip_2_p_79_qs;
Tests: T409 T410 T177
19054 1/1 reg_rdata_next[16] = ip_2_p_80_qs;
Tests: T409 T410 T177
19055 1/1 reg_rdata_next[17] = ip_2_p_81_qs;
Tests: T409 T410 T177
19056 1/1 reg_rdata_next[18] = ip_2_p_82_qs;
Tests: T409 T410 T177
19057 1/1 reg_rdata_next[19] = ip_2_p_83_qs;
Tests: T409 T410 T177
19058 1/1 reg_rdata_next[20] = ip_2_p_84_qs;
Tests: T409 T410 T177
19059 1/1 reg_rdata_next[21] = ip_2_p_85_qs;
Tests: T409 T410 T177
19060 1/1 reg_rdata_next[22] = ip_2_p_86_qs;
Tests: T409 T410 T177
19061 1/1 reg_rdata_next[23] = ip_2_p_87_qs;
Tests: T409 T410 T177
19062 1/1 reg_rdata_next[24] = ip_2_p_88_qs;
Tests: T409 T410 T177
19063 1/1 reg_rdata_next[25] = ip_2_p_89_qs;
Tests: T409 T410 T177
19064 1/1 reg_rdata_next[26] = ip_2_p_90_qs;
Tests: T409 T410 T177
19065 1/1 reg_rdata_next[27] = ip_2_p_91_qs;
Tests: T409 T410 T177
19066 1/1 reg_rdata_next[28] = ip_2_p_92_qs;
Tests: T409 T410 T177
19067 1/1 reg_rdata_next[29] = ip_2_p_93_qs;
Tests: T409 T410 T177
19068 1/1 reg_rdata_next[30] = ip_2_p_94_qs;
Tests: T409 T410 T177
19069 1/1 reg_rdata_next[31] = ip_2_p_95_qs;
Tests: T409 T410 T177
19070 end
19071
19072 addr_hit[189]: begin
19073 1/1 reg_rdata_next[0] = ip_3_p_96_qs;
Tests: T409 T410 T177
19074 1/1 reg_rdata_next[1] = ip_3_p_97_qs;
Tests: T409 T410 T177
19075 1/1 reg_rdata_next[2] = ip_3_p_98_qs;
Tests: T409 T410 T177
19076 1/1 reg_rdata_next[3] = ip_3_p_99_qs;
Tests: T409 T410 T177
19077 1/1 reg_rdata_next[4] = ip_3_p_100_qs;
Tests: T409 T410 T177
19078 1/1 reg_rdata_next[5] = ip_3_p_101_qs;
Tests: T409 T410 T177
19079 1/1 reg_rdata_next[6] = ip_3_p_102_qs;
Tests: T409 T410 T177
19080 1/1 reg_rdata_next[7] = ip_3_p_103_qs;
Tests: T409 T410 T177
19081 1/1 reg_rdata_next[8] = ip_3_p_104_qs;
Tests: T409 T410 T177
19082 1/1 reg_rdata_next[9] = ip_3_p_105_qs;
Tests: T409 T410 T177
19083 1/1 reg_rdata_next[10] = ip_3_p_106_qs;
Tests: T409 T410 T177
19084 1/1 reg_rdata_next[11] = ip_3_p_107_qs;
Tests: T409 T410 T177
19085 1/1 reg_rdata_next[12] = ip_3_p_108_qs;
Tests: T409 T410 T177
19086 1/1 reg_rdata_next[13] = ip_3_p_109_qs;
Tests: T409 T410 T177
19087 1/1 reg_rdata_next[14] = ip_3_p_110_qs;
Tests: T409 T410 T177
19088 1/1 reg_rdata_next[15] = ip_3_p_111_qs;
Tests: T409 T410 T177
19089 1/1 reg_rdata_next[16] = ip_3_p_112_qs;
Tests: T409 T410 T177
19090 1/1 reg_rdata_next[17] = ip_3_p_113_qs;
Tests: T409 T410 T177
19091 1/1 reg_rdata_next[18] = ip_3_p_114_qs;
Tests: T409 T410 T177
19092 1/1 reg_rdata_next[19] = ip_3_p_115_qs;
Tests: T409 T410 T177
19093 1/1 reg_rdata_next[20] = ip_3_p_116_qs;
Tests: T409 T410 T177
19094 1/1 reg_rdata_next[21] = ip_3_p_117_qs;
Tests: T409 T410 T177
19095 1/1 reg_rdata_next[22] = ip_3_p_118_qs;
Tests: T409 T410 T177
19096 1/1 reg_rdata_next[23] = ip_3_p_119_qs;
Tests: T409 T410 T177
19097 1/1 reg_rdata_next[24] = ip_3_p_120_qs;
Tests: T409 T410 T177
19098 1/1 reg_rdata_next[25] = ip_3_p_121_qs;
Tests: T409 T410 T177
19099 1/1 reg_rdata_next[26] = ip_3_p_122_qs;
Tests: T409 T410 T177
19100 1/1 reg_rdata_next[27] = ip_3_p_123_qs;
Tests: T409 T410 T177
19101 1/1 reg_rdata_next[28] = ip_3_p_124_qs;
Tests: T409 T410 T177
19102 1/1 reg_rdata_next[29] = ip_3_p_125_qs;
Tests: T409 T410 T177
19103 1/1 reg_rdata_next[30] = ip_3_p_126_qs;
Tests: T409 T410 T177
19104 1/1 reg_rdata_next[31] = ip_3_p_127_qs;
Tests: T409 T410 T177
19105 end
19106
19107 addr_hit[190]: begin
19108 1/1 reg_rdata_next[0] = ip_4_p_128_qs;
Tests: T269 T643 T644
19109 1/1 reg_rdata_next[1] = ip_4_p_129_qs;
Tests: T269 T643 T644
19110 1/1 reg_rdata_next[2] = ip_4_p_130_qs;
Tests: T269 T643 T644
19111 1/1 reg_rdata_next[3] = ip_4_p_131_qs;
Tests: T269 T643 T644
19112 1/1 reg_rdata_next[4] = ip_4_p_132_qs;
Tests: T269 T643 T644
19113 1/1 reg_rdata_next[5] = ip_4_p_133_qs;
Tests: T269 T643 T644
19114 1/1 reg_rdata_next[6] = ip_4_p_134_qs;
Tests: T269 T643 T644
19115 1/1 reg_rdata_next[7] = ip_4_p_135_qs;
Tests: T269 T643 T644
19116 1/1 reg_rdata_next[8] = ip_4_p_136_qs;
Tests: T269 T643 T644
19117 1/1 reg_rdata_next[9] = ip_4_p_137_qs;
Tests: T269 T643 T644
19118 1/1 reg_rdata_next[10] = ip_4_p_138_qs;
Tests: T269 T643 T644
19119 1/1 reg_rdata_next[11] = ip_4_p_139_qs;
Tests: T269 T643 T644
19120 1/1 reg_rdata_next[12] = ip_4_p_140_qs;
Tests: T269 T643 T644
19121 1/1 reg_rdata_next[13] = ip_4_p_141_qs;
Tests: T269 T643 T644
19122 1/1 reg_rdata_next[14] = ip_4_p_142_qs;
Tests: T269 T643 T644
19123 1/1 reg_rdata_next[15] = ip_4_p_143_qs;
Tests: T269 T643 T644
19124 1/1 reg_rdata_next[16] = ip_4_p_144_qs;
Tests: T269 T643 T644
19125 1/1 reg_rdata_next[17] = ip_4_p_145_qs;
Tests: T269 T643 T644
19126 1/1 reg_rdata_next[18] = ip_4_p_146_qs;
Tests: T269 T643 T644
19127 1/1 reg_rdata_next[19] = ip_4_p_147_qs;
Tests: T269 T643 T644
19128 1/1 reg_rdata_next[20] = ip_4_p_148_qs;
Tests: T269 T643 T644
19129 1/1 reg_rdata_next[21] = ip_4_p_149_qs;
Tests: T269 T643 T644
19130 1/1 reg_rdata_next[22] = ip_4_p_150_qs;
Tests: T269 T643 T644
19131 1/1 reg_rdata_next[23] = ip_4_p_151_qs;
Tests: T269 T643 T644
19132 1/1 reg_rdata_next[24] = ip_4_p_152_qs;
Tests: T269 T643 T644
19133 1/1 reg_rdata_next[25] = ip_4_p_153_qs;
Tests: T269 T643 T644
19134 1/1 reg_rdata_next[26] = ip_4_p_154_qs;
Tests: T269 T643 T644
19135 1/1 reg_rdata_next[27] = ip_4_p_155_qs;
Tests: T269 T643 T644
19136 1/1 reg_rdata_next[28] = ip_4_p_156_qs;
Tests: T269 T643 T644
19137 1/1 reg_rdata_next[29] = ip_4_p_157_qs;
Tests: T269 T643 T644
19138 1/1 reg_rdata_next[30] = ip_4_p_158_qs;
Tests: T269 T643 T644
19139 1/1 reg_rdata_next[31] = ip_4_p_159_qs;
Tests: T269 T643 T644
19140 end
19141
19142 addr_hit[191]: begin
19143 1/1 reg_rdata_next[0] = ip_5_p_160_qs;
Tests: T409 T410 T177
19144 1/1 reg_rdata_next[1] = ip_5_p_161_qs;
Tests: T409 T410 T177
19145 1/1 reg_rdata_next[2] = ip_5_p_162_qs;
Tests: T409 T410 T177
19146 1/1 reg_rdata_next[3] = ip_5_p_163_qs;
Tests: T409 T410 T177
19147 1/1 reg_rdata_next[4] = ip_5_p_164_qs;
Tests: T409 T410 T177
19148 1/1 reg_rdata_next[5] = ip_5_p_165_qs;
Tests: T409 T410 T177
19149 1/1 reg_rdata_next[6] = ip_5_p_166_qs;
Tests: T409 T410 T177
19150 1/1 reg_rdata_next[7] = ip_5_p_167_qs;
Tests: T409 T410 T177
19151 1/1 reg_rdata_next[8] = ip_5_p_168_qs;
Tests: T409 T410 T177
19152 1/1 reg_rdata_next[9] = ip_5_p_169_qs;
Tests: T409 T410 T177
19153 1/1 reg_rdata_next[10] = ip_5_p_170_qs;
Tests: T409 T410 T177
19154 1/1 reg_rdata_next[11] = ip_5_p_171_qs;
Tests: T409 T410 T177
19155 1/1 reg_rdata_next[12] = ip_5_p_172_qs;
Tests: T409 T410 T177
19156 1/1 reg_rdata_next[13] = ip_5_p_173_qs;
Tests: T409 T410 T177
19157 1/1 reg_rdata_next[14] = ip_5_p_174_qs;
Tests: T409 T410 T177
19158 1/1 reg_rdata_next[15] = ip_5_p_175_qs;
Tests: T409 T410 T177
19159 1/1 reg_rdata_next[16] = ip_5_p_176_qs;
Tests: T409 T410 T177
19160 1/1 reg_rdata_next[17] = ip_5_p_177_qs;
Tests: T409 T410 T177
19161 1/1 reg_rdata_next[18] = ip_5_p_178_qs;
Tests: T409 T410 T177
19162 1/1 reg_rdata_next[19] = ip_5_p_179_qs;
Tests: T409 T410 T177
19163 1/1 reg_rdata_next[20] = ip_5_p_180_qs;
Tests: T409 T410 T177
19164 1/1 reg_rdata_next[21] = ip_5_p_181_qs;
Tests: T409 T410 T177
19165 1/1 reg_rdata_next[22] = ip_5_p_182_qs;
Tests: T409 T410 T177
19166 1/1 reg_rdata_next[23] = ip_5_p_183_qs;
Tests: T409 T410 T177
19167 1/1 reg_rdata_next[24] = ip_5_p_184_qs;
Tests: T409 T410 T177
19168 1/1 reg_rdata_next[25] = ip_5_p_185_qs;
Tests: T409 T410 T177
19169 end
19170
19171 addr_hit[192]: begin
19172 1/1 reg_rdata_next[0] = ie0_0_e_0_qs;
Tests: T26 T134 T133
19173 1/1 reg_rdata_next[1] = ie0_0_e_1_qs;
Tests: T26 T134 T133
19174 1/1 reg_rdata_next[2] = ie0_0_e_2_qs;
Tests: T26 T134 T133
19175 1/1 reg_rdata_next[3] = ie0_0_e_3_qs;
Tests: T26 T134 T133
19176 1/1 reg_rdata_next[4] = ie0_0_e_4_qs;
Tests: T26 T134 T133
19177 1/1 reg_rdata_next[5] = ie0_0_e_5_qs;
Tests: T26 T134 T133
19178 1/1 reg_rdata_next[6] = ie0_0_e_6_qs;
Tests: T26 T134 T133
19179 1/1 reg_rdata_next[7] = ie0_0_e_7_qs;
Tests: T26 T134 T133
19180 1/1 reg_rdata_next[8] = ie0_0_e_8_qs;
Tests: T26 T134 T133
19181 1/1 reg_rdata_next[9] = ie0_0_e_9_qs;
Tests: T26 T134 T133
19182 1/1 reg_rdata_next[10] = ie0_0_e_10_qs;
Tests: T26 T134 T133
19183 1/1 reg_rdata_next[11] = ie0_0_e_11_qs;
Tests: T26 T134 T133
19184 1/1 reg_rdata_next[12] = ie0_0_e_12_qs;
Tests: T26 T134 T133
19185 1/1 reg_rdata_next[13] = ie0_0_e_13_qs;
Tests: T26 T134 T133
19186 1/1 reg_rdata_next[14] = ie0_0_e_14_qs;
Tests: T26 T134 T133
19187 1/1 reg_rdata_next[15] = ie0_0_e_15_qs;
Tests: T26 T134 T133
19188 1/1 reg_rdata_next[16] = ie0_0_e_16_qs;
Tests: T26 T134 T133
19189 1/1 reg_rdata_next[17] = ie0_0_e_17_qs;
Tests: T26 T134 T133
19190 1/1 reg_rdata_next[18] = ie0_0_e_18_qs;
Tests: T26 T134 T133
19191 1/1 reg_rdata_next[19] = ie0_0_e_19_qs;
Tests: T26 T134 T133
19192 1/1 reg_rdata_next[20] = ie0_0_e_20_qs;
Tests: T26 T134 T133
19193 1/1 reg_rdata_next[21] = ie0_0_e_21_qs;
Tests: T26 T134 T133
19194 1/1 reg_rdata_next[22] = ie0_0_e_22_qs;
Tests: T26 T134 T133
19195 1/1 reg_rdata_next[23] = ie0_0_e_23_qs;
Tests: T26 T134 T133
19196 1/1 reg_rdata_next[24] = ie0_0_e_24_qs;
Tests: T26 T134 T133
19197 1/1 reg_rdata_next[25] = ie0_0_e_25_qs;
Tests: T26 T134 T133
19198 1/1 reg_rdata_next[26] = ie0_0_e_26_qs;
Tests: T26 T134 T133
19199 1/1 reg_rdata_next[27] = ie0_0_e_27_qs;
Tests: T26 T134 T133
19200 1/1 reg_rdata_next[28] = ie0_0_e_28_qs;
Tests: T26 T134 T133
19201 1/1 reg_rdata_next[29] = ie0_0_e_29_qs;
Tests: T26 T134 T133
19202 1/1 reg_rdata_next[30] = ie0_0_e_30_qs;
Tests: T26 T134 T133
19203 1/1 reg_rdata_next[31] = ie0_0_e_31_qs;
Tests: T26 T134 T133
19204 end
19205
19206 addr_hit[193]: begin
19207 1/1 reg_rdata_next[0] = ie0_1_e_32_qs;
Tests: T26 T27 T70
19208 1/1 reg_rdata_next[1] = ie0_1_e_33_qs;
Tests: T26 T27 T70
19209 1/1 reg_rdata_next[2] = ie0_1_e_34_qs;
Tests: T26 T27 T70
19210 1/1 reg_rdata_next[3] = ie0_1_e_35_qs;
Tests: T26 T27 T70
19211 1/1 reg_rdata_next[4] = ie0_1_e_36_qs;
Tests: T26 T27 T70
19212 1/1 reg_rdata_next[5] = ie0_1_e_37_qs;
Tests: T26 T27 T70
19213 1/1 reg_rdata_next[6] = ie0_1_e_38_qs;
Tests: T26 T27 T70
19214 1/1 reg_rdata_next[7] = ie0_1_e_39_qs;
Tests: T26 T27 T70
19215 1/1 reg_rdata_next[8] = ie0_1_e_40_qs;
Tests: T26 T27 T70
19216 1/1 reg_rdata_next[9] = ie0_1_e_41_qs;
Tests: T26 T27 T70
19217 1/1 reg_rdata_next[10] = ie0_1_e_42_qs;
Tests: T26 T27 T70
19218 1/1 reg_rdata_next[11] = ie0_1_e_43_qs;
Tests: T26 T27 T70
19219 1/1 reg_rdata_next[12] = ie0_1_e_44_qs;
Tests: T26 T27 T70
19220 1/1 reg_rdata_next[13] = ie0_1_e_45_qs;
Tests: T26 T27 T70
19221 1/1 reg_rdata_next[14] = ie0_1_e_46_qs;
Tests: T26 T27 T70
19222 1/1 reg_rdata_next[15] = ie0_1_e_47_qs;
Tests: T26 T27 T70
19223 1/1 reg_rdata_next[16] = ie0_1_e_48_qs;
Tests: T26 T27 T70
19224 1/1 reg_rdata_next[17] = ie0_1_e_49_qs;
Tests: T26 T27 T70
19225 1/1 reg_rdata_next[18] = ie0_1_e_50_qs;
Tests: T26 T27 T70
19226 1/1 reg_rdata_next[19] = ie0_1_e_51_qs;
Tests: T26 T27 T70
19227 1/1 reg_rdata_next[20] = ie0_1_e_52_qs;
Tests: T26 T27 T70
19228 1/1 reg_rdata_next[21] = ie0_1_e_53_qs;
Tests: T26 T27 T70
19229 1/1 reg_rdata_next[22] = ie0_1_e_54_qs;
Tests: T26 T27 T70
19230 1/1 reg_rdata_next[23] = ie0_1_e_55_qs;
Tests: T26 T27 T70
19231 1/1 reg_rdata_next[24] = ie0_1_e_56_qs;
Tests: T26 T27 T70
19232 1/1 reg_rdata_next[25] = ie0_1_e_57_qs;
Tests: T26 T27 T70
19233 1/1 reg_rdata_next[26] = ie0_1_e_58_qs;
Tests: T26 T27 T70
19234 1/1 reg_rdata_next[27] = ie0_1_e_59_qs;
Tests: T26 T27 T70
19235 1/1 reg_rdata_next[28] = ie0_1_e_60_qs;
Tests: T26 T27 T70
19236 1/1 reg_rdata_next[29] = ie0_1_e_61_qs;
Tests: T26 T27 T70
19237 1/1 reg_rdata_next[30] = ie0_1_e_62_qs;
Tests: T26 T27 T70
19238 1/1 reg_rdata_next[31] = ie0_1_e_63_qs;
Tests: T26 T27 T70
19239 end
19240
19241 addr_hit[194]: begin
19242 1/1 reg_rdata_next[0] = ie0_2_e_64_qs;
Tests: T12 T27 T62
19243 1/1 reg_rdata_next[1] = ie0_2_e_65_qs;
Tests: T12 T27 T62
19244 1/1 reg_rdata_next[2] = ie0_2_e_66_qs;
Tests: T12 T27 T62
19245 1/1 reg_rdata_next[3] = ie0_2_e_67_qs;
Tests: T12 T27 T62
19246 1/1 reg_rdata_next[4] = ie0_2_e_68_qs;
Tests: T12 T27 T62
19247 1/1 reg_rdata_next[5] = ie0_2_e_69_qs;
Tests: T12 T27 T62
19248 1/1 reg_rdata_next[6] = ie0_2_e_70_qs;
Tests: T12 T27 T62
19249 1/1 reg_rdata_next[7] = ie0_2_e_71_qs;
Tests: T12 T27 T62
19250 1/1 reg_rdata_next[8] = ie0_2_e_72_qs;
Tests: T12 T27 T62
19251 1/1 reg_rdata_next[9] = ie0_2_e_73_qs;
Tests: T12 T27 T62
19252 1/1 reg_rdata_next[10] = ie0_2_e_74_qs;
Tests: T12 T27 T62
19253 1/1 reg_rdata_next[11] = ie0_2_e_75_qs;
Tests: T12 T27 T62
19254 1/1 reg_rdata_next[12] = ie0_2_e_76_qs;
Tests: T12 T27 T62
19255 1/1 reg_rdata_next[13] = ie0_2_e_77_qs;
Tests: T12 T27 T62
19256 1/1 reg_rdata_next[14] = ie0_2_e_78_qs;
Tests: T12 T27 T62
19257 1/1 reg_rdata_next[15] = ie0_2_e_79_qs;
Tests: T12 T27 T62
19258 1/1 reg_rdata_next[16] = ie0_2_e_80_qs;
Tests: T12 T27 T62
19259 1/1 reg_rdata_next[17] = ie0_2_e_81_qs;
Tests: T12 T27 T62
19260 1/1 reg_rdata_next[18] = ie0_2_e_82_qs;
Tests: T12 T27 T62
19261 1/1 reg_rdata_next[19] = ie0_2_e_83_qs;
Tests: T12 T27 T62
19262 1/1 reg_rdata_next[20] = ie0_2_e_84_qs;
Tests: T12 T27 T62
19263 1/1 reg_rdata_next[21] = ie0_2_e_85_qs;
Tests: T12 T27 T62
19264 1/1 reg_rdata_next[22] = ie0_2_e_86_qs;
Tests: T12 T27 T62
19265 1/1 reg_rdata_next[23] = ie0_2_e_87_qs;
Tests: T12 T27 T62
19266 1/1 reg_rdata_next[24] = ie0_2_e_88_qs;
Tests: T12 T27 T62
19267 1/1 reg_rdata_next[25] = ie0_2_e_89_qs;
Tests: T12 T27 T62
19268 1/1 reg_rdata_next[26] = ie0_2_e_90_qs;
Tests: T12 T27 T62
19269 1/1 reg_rdata_next[27] = ie0_2_e_91_qs;
Tests: T12 T27 T62
19270 1/1 reg_rdata_next[28] = ie0_2_e_92_qs;
Tests: T12 T27 T62
19271 1/1 reg_rdata_next[29] = ie0_2_e_93_qs;
Tests: T12 T27 T62
19272 1/1 reg_rdata_next[30] = ie0_2_e_94_qs;
Tests: T12 T27 T62
19273 1/1 reg_rdata_next[31] = ie0_2_e_95_qs;
Tests: T12 T27 T62
19274 end
19275
19276 addr_hit[195]: begin
19277 1/1 reg_rdata_next[0] = ie0_3_e_96_qs;
Tests: T5 T45 T66
19278 1/1 reg_rdata_next[1] = ie0_3_e_97_qs;
Tests: T5 T45 T66
19279 1/1 reg_rdata_next[2] = ie0_3_e_98_qs;
Tests: T5 T45 T66
19280 1/1 reg_rdata_next[3] = ie0_3_e_99_qs;
Tests: T5 T45 T66
19281 1/1 reg_rdata_next[4] = ie0_3_e_100_qs;
Tests: T5 T45 T66
19282 1/1 reg_rdata_next[5] = ie0_3_e_101_qs;
Tests: T5 T45 T66
19283 1/1 reg_rdata_next[6] = ie0_3_e_102_qs;
Tests: T5 T45 T66
19284 1/1 reg_rdata_next[7] = ie0_3_e_103_qs;
Tests: T5 T45 T66
19285 1/1 reg_rdata_next[8] = ie0_3_e_104_qs;
Tests: T5 T45 T66
19286 1/1 reg_rdata_next[9] = ie0_3_e_105_qs;
Tests: T5 T45 T66
19287 1/1 reg_rdata_next[10] = ie0_3_e_106_qs;
Tests: T5 T45 T66
19288 1/1 reg_rdata_next[11] = ie0_3_e_107_qs;
Tests: T5 T45 T66
19289 1/1 reg_rdata_next[12] = ie0_3_e_108_qs;
Tests: T5 T45 T66
19290 1/1 reg_rdata_next[13] = ie0_3_e_109_qs;
Tests: T5 T45 T66
19291 1/1 reg_rdata_next[14] = ie0_3_e_110_qs;
Tests: T5 T45 T66
19292 1/1 reg_rdata_next[15] = ie0_3_e_111_qs;
Tests: T5 T45 T66
19293 1/1 reg_rdata_next[16] = ie0_3_e_112_qs;
Tests: T5 T45 T66
19294 1/1 reg_rdata_next[17] = ie0_3_e_113_qs;
Tests: T5 T45 T66
19295 1/1 reg_rdata_next[18] = ie0_3_e_114_qs;
Tests: T5 T45 T66
19296 1/1 reg_rdata_next[19] = ie0_3_e_115_qs;
Tests: T5 T45 T66
19297 1/1 reg_rdata_next[20] = ie0_3_e_116_qs;
Tests: T5 T45 T66
19298 1/1 reg_rdata_next[21] = ie0_3_e_117_qs;
Tests: T5 T45 T66
19299 1/1 reg_rdata_next[22] = ie0_3_e_118_qs;
Tests: T5 T45 T66
19300 1/1 reg_rdata_next[23] = ie0_3_e_119_qs;
Tests: T5 T45 T66
19301 1/1 reg_rdata_next[24] = ie0_3_e_120_qs;
Tests: T5 T45 T66
19302 1/1 reg_rdata_next[25] = ie0_3_e_121_qs;
Tests: T5 T45 T66
19303 1/1 reg_rdata_next[26] = ie0_3_e_122_qs;
Tests: T5 T45 T66
19304 1/1 reg_rdata_next[27] = ie0_3_e_123_qs;
Tests: T5 T45 T66
19305 1/1 reg_rdata_next[28] = ie0_3_e_124_qs;
Tests: T5 T45 T66
19306 1/1 reg_rdata_next[29] = ie0_3_e_125_qs;
Tests: T5 T45 T66
19307 1/1 reg_rdata_next[30] = ie0_3_e_126_qs;
Tests: T5 T45 T66
19308 1/1 reg_rdata_next[31] = ie0_3_e_127_qs;
Tests: T5 T45 T66
19309 end
19310
19311 addr_hit[196]: begin
19312 1/1 reg_rdata_next[0] = ie0_4_e_128_qs;
Tests: T2 T4 T6
19313 1/1 reg_rdata_next[1] = ie0_4_e_129_qs;
Tests: T2 T4 T6
19314 1/1 reg_rdata_next[2] = ie0_4_e_130_qs;
Tests: T2 T4 T6
19315 1/1 reg_rdata_next[3] = ie0_4_e_131_qs;
Tests: T2 T4 T6
19316 1/1 reg_rdata_next[4] = ie0_4_e_132_qs;
Tests: T2 T4 T6
19317 1/1 reg_rdata_next[5] = ie0_4_e_133_qs;
Tests: T2 T4 T6
19318 1/1 reg_rdata_next[6] = ie0_4_e_134_qs;
Tests: T2 T4 T6
19319 1/1 reg_rdata_next[7] = ie0_4_e_135_qs;
Tests: T2 T4 T6
19320 1/1 reg_rdata_next[8] = ie0_4_e_136_qs;
Tests: T2 T4 T6
19321 1/1 reg_rdata_next[9] = ie0_4_e_137_qs;
Tests: T2 T4 T6
19322 1/1 reg_rdata_next[10] = ie0_4_e_138_qs;
Tests: T2 T4 T6
19323 1/1 reg_rdata_next[11] = ie0_4_e_139_qs;
Tests: T2 T4 T6
19324 1/1 reg_rdata_next[12] = ie0_4_e_140_qs;
Tests: T2 T4 T6
19325 1/1 reg_rdata_next[13] = ie0_4_e_141_qs;
Tests: T2 T4 T6
19326 1/1 reg_rdata_next[14] = ie0_4_e_142_qs;
Tests: T2 T4 T6
19327 1/1 reg_rdata_next[15] = ie0_4_e_143_qs;
Tests: T2 T4 T6
19328 1/1 reg_rdata_next[16] = ie0_4_e_144_qs;
Tests: T2 T4 T6
19329 1/1 reg_rdata_next[17] = ie0_4_e_145_qs;
Tests: T2 T4 T6
19330 1/1 reg_rdata_next[18] = ie0_4_e_146_qs;
Tests: T2 T4 T6
19331 1/1 reg_rdata_next[19] = ie0_4_e_147_qs;
Tests: T2 T4 T6
19332 1/1 reg_rdata_next[20] = ie0_4_e_148_qs;
Tests: T2 T4 T6
19333 1/1 reg_rdata_next[21] = ie0_4_e_149_qs;
Tests: T2 T4 T6
19334 1/1 reg_rdata_next[22] = ie0_4_e_150_qs;
Tests: T2 T4 T6
19335 1/1 reg_rdata_next[23] = ie0_4_e_151_qs;
Tests: T2 T4 T6
19336 1/1 reg_rdata_next[24] = ie0_4_e_152_qs;
Tests: T2 T4 T6
19337 1/1 reg_rdata_next[25] = ie0_4_e_153_qs;
Tests: T2 T4 T6
19338 1/1 reg_rdata_next[26] = ie0_4_e_154_qs;
Tests: T2 T4 T6
19339 1/1 reg_rdata_next[27] = ie0_4_e_155_qs;
Tests: T2 T4 T6
19340 1/1 reg_rdata_next[28] = ie0_4_e_156_qs;
Tests: T2 T4 T6
19341 1/1 reg_rdata_next[29] = ie0_4_e_157_qs;
Tests: T2 T4 T6
19342 1/1 reg_rdata_next[30] = ie0_4_e_158_qs;
Tests: T2 T4 T6
19343 1/1 reg_rdata_next[31] = ie0_4_e_159_qs;
Tests: T2 T4 T6
19344 end
19345
19346 addr_hit[197]: begin
19347 1/1 reg_rdata_next[0] = ie0_5_e_160_qs;
Tests: T124 T153 T253
19348 1/1 reg_rdata_next[1] = ie0_5_e_161_qs;
Tests: T124 T153 T253
19349 1/1 reg_rdata_next[2] = ie0_5_e_162_qs;
Tests: T124 T153 T253
19350 1/1 reg_rdata_next[3] = ie0_5_e_163_qs;
Tests: T124 T153 T253
19351 1/1 reg_rdata_next[4] = ie0_5_e_164_qs;
Tests: T124 T153 T253
19352 1/1 reg_rdata_next[5] = ie0_5_e_165_qs;
Tests: T124 T153 T253
19353 1/1 reg_rdata_next[6] = ie0_5_e_166_qs;
Tests: T124 T153 T253
19354 1/1 reg_rdata_next[7] = ie0_5_e_167_qs;
Tests: T124 T153 T253
19355 1/1 reg_rdata_next[8] = ie0_5_e_168_qs;
Tests: T124 T153 T253
19356 1/1 reg_rdata_next[9] = ie0_5_e_169_qs;
Tests: T124 T153 T253
19357 1/1 reg_rdata_next[10] = ie0_5_e_170_qs;
Tests: T124 T153 T253
19358 1/1 reg_rdata_next[11] = ie0_5_e_171_qs;
Tests: T124 T153 T253
19359 1/1 reg_rdata_next[12] = ie0_5_e_172_qs;
Tests: T124 T153 T253
19360 1/1 reg_rdata_next[13] = ie0_5_e_173_qs;
Tests: T124 T153 T253
19361 1/1 reg_rdata_next[14] = ie0_5_e_174_qs;
Tests: T124 T153 T253
19362 1/1 reg_rdata_next[15] = ie0_5_e_175_qs;
Tests: T124 T153 T253
19363 1/1 reg_rdata_next[16] = ie0_5_e_176_qs;
Tests: T124 T153 T253
19364 1/1 reg_rdata_next[17] = ie0_5_e_177_qs;
Tests: T124 T153 T253
19365 1/1 reg_rdata_next[18] = ie0_5_e_178_qs;
Tests: T124 T153 T253
19366 1/1 reg_rdata_next[19] = ie0_5_e_179_qs;
Tests: T124 T153 T253
19367 1/1 reg_rdata_next[20] = ie0_5_e_180_qs;
Tests: T124 T153 T253
19368 1/1 reg_rdata_next[21] = ie0_5_e_181_qs;
Tests: T124 T153 T253
19369 1/1 reg_rdata_next[22] = ie0_5_e_182_qs;
Tests: T124 T153 T253
19370 1/1 reg_rdata_next[23] = ie0_5_e_183_qs;
Tests: T124 T153 T253
19371 1/1 reg_rdata_next[24] = ie0_5_e_184_qs;
Tests: T124 T153 T253
19372 1/1 reg_rdata_next[25] = ie0_5_e_185_qs;
Tests: T124 T153 T253
19373 end
19374
19375 addr_hit[198]: begin
19376 1/1 reg_rdata_next[1:0] = threshold0_qs;
Tests: T2 T4 T5
19377 end
19378
19379 addr_hit[199]: begin
19380 1/1 reg_rdata_next[7:0] = cc0_qs;
Tests: T4 T5 T6
19381 end
19382
19383 addr_hit[200]: begin
19384 1/1 reg_rdata_next[0] = msip0_qs;
Tests: T249 T250 T251
19385 end
19386
19387 addr_hit[201]: begin
19388 1/1 reg_rdata_next[0] = '0;
Tests: T80 T81 T82
19389 end
19390
19391 default: begin
19392 reg_rdata_next = '1;
19393 end
19394 endcase
19395 end
19396
19397 // shadow busy
19398 logic shadow_busy;
19399 assign shadow_busy = 1'b0;
19400
19401 // register busy
19402 unreachable assign reg_busy = shadow_busy;
19403
19404 // Unused signal tieoff
19405
19406 // wdata / byte enable are not always fully used
19407 // add a blanket unused statement to handle lint waivers
19408 logic unused_wdata;
19409 logic unused_be;
19410 1/1 assign unused_wdata = ^reg_wdata;
Tests: T2 T4 T5
19411 1/1 assign unused_be = ^reg_be;
Tests: T2 T4 T5