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 LINE       60
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T98,T103,T169
1	1	Covered	T1,T2,T3

 LINE       72
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T108,T109,T110
1	0	Not Covered

 LINE       79
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T108,T109,T110
0	1	0	Covered	T276,T307,T466
1	0	0	Covered	T108,T109,T110

 LINE       121
 EXPRESSION (addrmiss | wr_err | intg_err)
             ----1---   ---2--   ----3---

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T276,T307,T466
0	1	0	Covered	T97,T98,T103
1	0	0	Covered	T98,T103,T169

 LINE       5866
 EXPRESSION (mio_periph_insel_0_we & mio_periph_insel_regwen_0_qs)
             ----------1----------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T189,T183,T184
1	1	Covered	T6,T25,T27

 LINE       5898
 EXPRESSION (mio_periph_insel_1_we & mio_periph_insel_regwen_1_qs)
             ----------1----------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T71,T188,T183
1	1	Covered	T25,T27,T42

 LINE       5930
 EXPRESSION (mio_periph_insel_2_we & mio_periph_insel_regwen_2_qs)
             ----------1----------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T71,T401,T180
1	1	Covered	T25,T27,T42

 LINE       5962
 EXPRESSION (mio_periph_insel_3_we & mio_periph_insel_regwen_3_qs)
             ----------1----------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T401,T180,T189
1	1	Covered	T25,T27,T42

 LINE       5994
 EXPRESSION (mio_periph_insel_4_we & mio_periph_insel_regwen_4_qs)
             ----------1----------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T189,T184,T413
1	1	Covered	T25,T27,T42

 LINE       6026
 EXPRESSION (mio_periph_insel_5_we & mio_periph_insel_regwen_5_qs)
             ----------1----------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T177,T401,T189
1	1	Covered	T25,T27,T42

 LINE       6058
 EXPRESSION (mio_periph_insel_6_we & mio_periph_insel_regwen_6_qs)
             ----------1----------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T426,T414,T467
1	1	Covered	T25,T27,T42

 LINE       6090
 EXPRESSION (mio_periph_insel_7_we & mio_periph_insel_regwen_7_qs)
             ----------1----------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T71,T188,T189
1	1	Covered	T25,T27,T42

 LINE       6122
 EXPRESSION (mio_periph_insel_8_we & mio_periph_insel_regwen_8_qs)
             ----------1----------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T177,T188,T189
1	1	Covered	T25,T27,T42

 LINE       6154
 EXPRESSION (mio_periph_insel_9_we & mio_periph_insel_regwen_9_qs)
             ----------1----------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T71,T177,T180
1	1	Covered	T27,T42,T43

 LINE       6186
 EXPRESSION (mio_periph_insel_10_we & mio_periph_insel_regwen_10_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T71,T189,T428
1	1	Covered	T27,T42,T43

 LINE       6218
 EXPRESSION (mio_periph_insel_11_we & mio_periph_insel_regwen_11_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T71,T188,T180
1	1	Covered	T27,T42,T43

 LINE       6250
 EXPRESSION (mio_periph_insel_12_we & mio_periph_insel_regwen_12_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T71,T188,T401
1	1	Covered	T27,T42,T43

 LINE       6282
 EXPRESSION (mio_periph_insel_13_we & mio_periph_insel_regwen_13_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T71,T179,T401
1	1	Covered	T27,T42,T43

 LINE       6314
 EXPRESSION (mio_periph_insel_14_we & mio_periph_insel_regwen_14_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T71,T183,T184
1	1	Covered	T27,T42,T43

 LINE       6346
 EXPRESSION (mio_periph_insel_15_we & mio_periph_insel_regwen_15_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T188,T189,T183
1	1	Covered	T27,T42,T43

 LINE       6378
 EXPRESSION (mio_periph_insel_16_we & mio_periph_insel_regwen_16_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T71,T180,T189
1	1	Covered	T27,T42,T43

 LINE       6410
 EXPRESSION (mio_periph_insel_17_we & mio_periph_insel_regwen_17_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T71,T180,T189
1	1	Covered	T27,T42,T43

 LINE       6442
 EXPRESSION (mio_periph_insel_18_we & mio_periph_insel_regwen_18_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T71,T189,T426
1	1	Covered	T27,T42,T43

 LINE       6474
 EXPRESSION (mio_periph_insel_19_we & mio_periph_insel_regwen_19_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T188,T189,T429
1	1	Covered	T27,T42,T43

 LINE       6506
 EXPRESSION (mio_periph_insel_20_we & mio_periph_insel_regwen_20_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T71,T188,T180
1	1	Covered	T27,T42,T43

 LINE       6538
 EXPRESSION (mio_periph_insel_21_we & mio_periph_insel_regwen_21_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T401,T184,T413
1	1	Covered	T27,T42,T43

 LINE       6570
 EXPRESSION (mio_periph_insel_22_we & mio_periph_insel_regwen_22_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T180,T189,T428
1	1	Covered	T1,T2,T3

 LINE       6602
 EXPRESSION (mio_periph_insel_23_we & mio_periph_insel_regwen_23_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T189,T427,T183
1	1	Covered	T1,T2,T3

 LINE       6634
 EXPRESSION (mio_periph_insel_24_we & mio_periph_insel_regwen_24_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T71,T177,T189
1	1	Covered	T1,T2,T3

 LINE       6666
 EXPRESSION (mio_periph_insel_25_we & mio_periph_insel_regwen_25_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T71,T179,T413
1	1	Covered	T27,T42,T43

 LINE       6698
 EXPRESSION (mio_periph_insel_26_we & mio_periph_insel_regwen_26_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T71,T189,T183
1	1	Covered	T27,T42,T43

 LINE       6730
 EXPRESSION (mio_periph_insel_27_we & mio_periph_insel_regwen_27_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T71,T180,T426
1	1	Covered	T27,T42,T43

 LINE       6762
 EXPRESSION (mio_periph_insel_28_we & mio_periph_insel_regwen_28_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T71,T188,T189
1	1	Covered	T27,T42,T43

 LINE       6794
 EXPRESSION (mio_periph_insel_29_we & mio_periph_insel_regwen_29_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T189,T413,T414
1	1	Covered	T27,T42,T43

 LINE       6826
 EXPRESSION (mio_periph_insel_30_we & mio_periph_insel_regwen_30_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T71,T189,T428
1	1	Covered	T27,T42,T43

 LINE       6858
 EXPRESSION (mio_periph_insel_31_we & mio_periph_insel_regwen_31_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T180,T183,T414
1	1	Covered	T27,T42,T43

 LINE       6890
 EXPRESSION (mio_periph_insel_32_we & mio_periph_insel_regwen_32_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T71,T177,T401
1	1	Covered	T62,T37,T63

 LINE       6922
 EXPRESSION (mio_periph_insel_33_we & mio_periph_insel_regwen_33_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T71,T179,T188
1	1	Covered	T62,T37,T63

 LINE       6954
 EXPRESSION (mio_periph_insel_34_we & mio_periph_insel_regwen_34_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T71,T188,T413
1	1	Covered	T64,T65,T37

 LINE       6986
 EXPRESSION (mio_periph_insel_35_we & mio_periph_insel_regwen_35_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T177,T188,T401
1	1	Covered	T64,T65,T37

 LINE       7018
 EXPRESSION (mio_periph_insel_36_we & mio_periph_insel_regwen_36_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T71,T188,T429
1	1	Covered	T66,T37,T67

 LINE       7050
 EXPRESSION (mio_periph_insel_37_we & mio_periph_insel_regwen_37_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T180,T189,T426
1	1	Covered	T66,T37,T67

 LINE       7082
 EXPRESSION (mio_periph_insel_38_we & mio_periph_insel_regwen_38_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T71,T188,T180
1	1	Covered	T9,T37,T47

 LINE       7114
 EXPRESSION (mio_periph_insel_39_we & mio_periph_insel_regwen_39_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T71,T189,T426
1	1	Covered	T9,T37,T47

 LINE       7146
 EXPRESSION (mio_periph_insel_40_we & mio_periph_insel_regwen_40_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T71,T177,T179
1	1	Covered	T9,T37,T47

 LINE       7178
 EXPRESSION (mio_periph_insel_41_we & mio_periph_insel_regwen_41_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T189,T414,T467
1	1	Covered	T9,T10,T11

 LINE       7210
 EXPRESSION (mio_periph_insel_42_we & mio_periph_insel_regwen_42_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T71,T177,T401
1	1	Covered	T1,T2,T3

 LINE       7242
 EXPRESSION (mio_periph_insel_43_we & mio_periph_insel_regwen_43_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T71,T189,T184
1	1	Covered	T1,T2,T3

 LINE       7274
 EXPRESSION (mio_periph_insel_44_we & mio_periph_insel_regwen_44_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T71,T180,T189
1	1	Covered	T68,T37,T69

 LINE       7306
 EXPRESSION (mio_periph_insel_45_we & mio_periph_insel_regwen_45_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T177,T188,T180
1	1	Covered	T26,T70,T37

 LINE       7338
 EXPRESSION (mio_periph_insel_46_we & mio_periph_insel_regwen_46_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T71,T179,T188
1	1	Covered	T12,T53,T54

 LINE       7370
 EXPRESSION (mio_periph_insel_47_we & mio_periph_insel_regwen_47_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T179,T180,T189
1	1	Covered	T71,T177,T188

 LINE       7402
 EXPRESSION (mio_periph_insel_48_we & mio_periph_insel_regwen_48_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T180,T189,T427
1	1	Covered	T71,T177,T432

 LINE       7434
 EXPRESSION (mio_periph_insel_49_we & mio_periph_insel_regwen_49_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T188,T189,T183
1	1	Covered	T71,T177,T179

 LINE       7466
 EXPRESSION (mio_periph_insel_50_we & mio_periph_insel_regwen_50_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T189,T183,T428
1	1	Covered	T28,T15,T72

 LINE       7498
 EXPRESSION (mio_periph_insel_51_we & mio_periph_insel_regwen_51_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T71,T177,T189
1	1	Covered	T28,T13,T72

 LINE       7530
 EXPRESSION (mio_periph_insel_52_we & mio_periph_insel_regwen_52_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T71,T426,T183
1	1	Covered	T28,T13,T72

 LINE       7562
 EXPRESSION (mio_periph_insel_53_we & mio_periph_insel_regwen_53_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T71,T188,T180
1	1	Covered	T28,T13,T72

 LINE       7594
 EXPRESSION (mio_periph_insel_54_we & mio_periph_insel_regwen_54_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T71,T177,T180
1	1	Covered	T28,T13,T15

 LINE       7626
 EXPRESSION (mio_periph_insel_55_we & mio_periph_insel_regwen_55_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T71,T180,T189
1	1	Covered	T28,T15,T72

 LINE       7658
 EXPRESSION (mio_periph_insel_56_we & mio_periph_insel_regwen_56_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T180,T189,T184
1	1	Covered	T7,T31,T8

 LINE       9053
 EXPRESSION (mio_outsel_0_we & mio_outsel_regwen_0_qs)
             -------1-------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T25,T27,T37

 LINE       9085
 EXPRESSION (mio_outsel_1_we & mio_outsel_regwen_1_qs)
             -------1-------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T25,T26,T27

 LINE       9117
 EXPRESSION (mio_outsel_2_we & mio_outsel_regwen_2_qs)
             -------1-------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T25,T27,T75

 LINE       9149
 EXPRESSION (mio_outsel_3_we & mio_outsel_regwen_3_qs)
             -------1-------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T25,T27,T42

 LINE       9181
 EXPRESSION (mio_outsel_4_we & mio_outsel_regwen_4_qs)
             -------1-------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T25,T27,T37

 LINE       9213
 EXPRESSION (mio_outsel_5_we & mio_outsel_regwen_5_qs)
             -------1-------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T25,T27

 LINE       9245
 EXPRESSION (mio_outsel_6_we & mio_outsel_regwen_6_qs)
             -------1-------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T25,T27,T42

 LINE       9277
 EXPRESSION (mio_outsel_7_we & mio_outsel_regwen_7_qs)
             -------1-------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T25,T27,T62

 LINE       9309
 EXPRESSION (mio_outsel_8_we & mio_outsel_regwen_8_qs)
             -------1-------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T27,T62,T37

 LINE       9341
 EXPRESSION (mio_outsel_9_we & mio_outsel_regwen_9_qs)
             -------1-------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T9,T10,T11

 LINE       9373
 EXPRESSION (mio_outsel_10_we & mio_outsel_regwen_10_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T9,T10,T11

 LINE       9405
 EXPRESSION (mio_outsel_11_we & mio_outsel_regwen_11_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T10,T11,T37

 LINE       9437
 EXPRESSION (mio_outsel_12_we & mio_outsel_regwen_12_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T9,T10,T11

 LINE       9469
 EXPRESSION (mio_outsel_13_we & mio_outsel_regwen_13_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       9501
 EXPRESSION (mio_outsel_14_we & mio_outsel_regwen_14_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       9533
 EXPRESSION (mio_outsel_15_we & mio_outsel_regwen_15_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T9,T27,T37

 LINE       9565
 EXPRESSION (mio_outsel_16_we & mio_outsel_regwen_16_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T27,T13,T15

 LINE       9597
 EXPRESSION (mio_outsel_17_we & mio_outsel_regwen_17_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T27,T37,T42

 LINE       9629
 EXPRESSION (mio_outsel_18_we & mio_outsel_regwen_18_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T5,T27,T64

 LINE       9661
 EXPRESSION (mio_outsel_19_we & mio_outsel_regwen_19_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T5,T27,T64

 LINE       9693
 EXPRESSION (mio_outsel_20_we & mio_outsel_regwen_20_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T5,T27,T66

 LINE       9725
 EXPRESSION (mio_outsel_21_we & mio_outsel_regwen_21_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T5,T27,T66

 LINE       9757
 EXPRESSION (mio_outsel_22_we & mio_outsel_regwen_22_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T432,T468,T469

 LINE       9789
 EXPRESSION (mio_outsel_23_we & mio_outsel_regwen_23_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T24,T470,T471

 LINE       9821
 EXPRESSION (mio_outsel_24_we & mio_outsel_regwen_24_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T450,T472,T470

 LINE       9853
 EXPRESSION (mio_outsel_25_we & mio_outsel_regwen_25_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       9885
 EXPRESSION (mio_outsel_26_we & mio_outsel_regwen_26_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       9917
 EXPRESSION (mio_outsel_27_we & mio_outsel_regwen_27_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T473,T474,T475

 LINE       9949
 EXPRESSION (mio_outsel_28_we & mio_outsel_regwen_28_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T472,T476,T477

 LINE       9981
 EXPRESSION (mio_outsel_29_we & mio_outsel_regwen_29_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       10013
 EXPRESSION (mio_outsel_30_we & mio_outsel_regwen_30_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T450,T478,T479

 LINE       10045
 EXPRESSION (mio_outsel_31_we & mio_outsel_regwen_31_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T27,T13,T41

 LINE       10077
 EXPRESSION (mio_outsel_32_we & mio_outsel_regwen_32_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T27,T35,T75

 LINE       10109
 EXPRESSION (mio_outsel_33_we & mio_outsel_regwen_33_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T27,T35,T75

 LINE       10141
 EXPRESSION (mio_outsel_34_we & mio_outsel_regwen_34_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T27,T35,T75

 LINE       10173
 EXPRESSION (mio_outsel_35_we & mio_outsel_regwen_35_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T27,T37,T42

 LINE       10205
 EXPRESSION (mio_outsel_36_we & mio_outsel_regwen_36_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T27,T37,T42

 LINE       10237
 EXPRESSION (mio_outsel_37_we & mio_outsel_regwen_37_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T27,T37,T42

 LINE       10269
 EXPRESSION (mio_outsel_38_we & mio_outsel_regwen_38_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T27,T37,T42

 LINE       10301
 EXPRESSION (mio_outsel_39_we & mio_outsel_regwen_39_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T27,T42,T43

 LINE       10333
 EXPRESSION (mio_outsel_40_we & mio_outsel_regwen_40_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T27,T13,T37

 LINE       10365
 EXPRESSION (mio_outsel_41_we & mio_outsel_regwen_41_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T27,T13,T37

 LINE       10397
 EXPRESSION (mio_outsel_42_we & mio_outsel_regwen_42_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T27,T37,T42

 LINE       10429
 EXPRESSION (mio_outsel_43_we & mio_outsel_regwen_43_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T27,T37,T42

 LINE       10461
 EXPRESSION (mio_outsel_44_we & mio_outsel_regwen_44_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T27,T37,T42

 LINE       10493
 EXPRESSION (mio_outsel_45_we & mio_outsel_regwen_45_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T27,T37,T42

 LINE       10525
 EXPRESSION (mio_outsel_46_we & mio_outsel_regwen_46_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T27,T37,T42

 LINE       11923
 EXPRESSION (mio_pad_attr_0_we & mio_pad_attr_regwen_0_qs)
             --------1--------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T480,T481,T478

 LINE       12092
 EXPRESSION (mio_pad_attr_1_we & mio_pad_attr_regwen_1_qs)
             --------1--------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T479,T482,T483