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 LINE       27621
 EXPRESSION (mio_pad_sleep_mode_14_we & mio_pad_sleep_regwen_14_qs)
             ------------1-----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T173,T179,T422
1	1	Covered	T21,T49,T169

 LINE       27653
 EXPRESSION (mio_pad_sleep_mode_15_we & mio_pad_sleep_regwen_15_qs)
             ------------1-----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T169,T421,T179
1	1	Covered	T21,T49,T457

 LINE       27685
 EXPRESSION (mio_pad_sleep_mode_16_we & mio_pad_sleep_regwen_16_qs)
             ------------1-----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T421,T179,T422
1	1	Covered	T21,T49,T100

 LINE       27717
 EXPRESSION (mio_pad_sleep_mode_17_we & mio_pad_sleep_regwen_17_qs)
             ------------1-----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T174,T176,T446
1	1	Covered	T21,T49,T169

 LINE       27749
 EXPRESSION (mio_pad_sleep_mode_18_we & mio_pad_sleep_regwen_18_qs)
             ------------1-----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T422,T176,T444
1	1	Covered	T21,T49,T169

 LINE       27781
 EXPRESSION (mio_pad_sleep_mode_19_we & mio_pad_sleep_regwen_19_qs)
             ------------1-----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T173,T422,T443
1	1	Covered	T21,T49,T169

 LINE       27813
 EXPRESSION (mio_pad_sleep_mode_20_we & mio_pad_sleep_regwen_20_qs)
             ------------1-----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T169,T421,T179
1	1	Covered	T21,T49,T173

 LINE       27845
 EXPRESSION (mio_pad_sleep_mode_21_we & mio_pad_sleep_regwen_21_qs)
             ------------1-----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T169,T422,T174
1	1	Covered	T21,T49,T421

 LINE       27877
 EXPRESSION (mio_pad_sleep_mode_22_we & mio_pad_sleep_regwen_22_qs)
             ------------1-----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T169,T422,T174
1	1	Covered	T21,T49,T421

 LINE       27909
 EXPRESSION (mio_pad_sleep_mode_23_we & mio_pad_sleep_regwen_23_qs)
             ------------1-----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T422,T443,T445
1	1	Covered	T21,T49,T100

 LINE       27941
 EXPRESSION (mio_pad_sleep_mode_24_we & mio_pad_sleep_regwen_24_qs)
             ------------1-----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T179,T422,T443
1	1	Covered	T21,T49,T169

 LINE       27973
 EXPRESSION (mio_pad_sleep_mode_25_we & mio_pad_sleep_regwen_25_qs)
             ------------1-----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T179,T174,T444
1	1	Covered	T21,T49,T169

 LINE       28005
 EXPRESSION (mio_pad_sleep_mode_26_we & mio_pad_sleep_regwen_26_qs)
             ------------1-----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T422,T176,T175
1	1	Covered	T21,T49,T169

 LINE       28037
 EXPRESSION (mio_pad_sleep_mode_27_we & mio_pad_sleep_regwen_27_qs)
             ------------1-----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T174,T443,T444
1	1	Covered	T21,T49,T169

 LINE       28069
 EXPRESSION (mio_pad_sleep_mode_28_we & mio_pad_sleep_regwen_28_qs)
             ------------1-----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T169,T421,T422
1	1	Covered	T21,T49,T173

 LINE       28101
 EXPRESSION (mio_pad_sleep_mode_29_we & mio_pad_sleep_regwen_29_qs)
             ------------1-----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T421,T422,T480
1	1	Covered	T21,T49,T169

 LINE       28133
 EXPRESSION (mio_pad_sleep_mode_30_we & mio_pad_sleep_regwen_30_qs)
             ------------1-----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T443,T444,T175
1	1	Covered	T21,T49,T169

 LINE       28165
 EXPRESSION (mio_pad_sleep_mode_31_we & mio_pad_sleep_regwen_31_qs)
             ------------1-----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T421,T179,T422
1	1	Covered	T21,T49,T169

 LINE       28197
 EXPRESSION (mio_pad_sleep_mode_32_we & mio_pad_sleep_regwen_32_qs)
             ------------1-----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T421,T174,T432
1	1	Covered	T21,T49,T169

 LINE       28229
 EXPRESSION (mio_pad_sleep_mode_33_we & mio_pad_sleep_regwen_33_qs)
             ------------1-----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T169,T173,T422
1	1	Covered	T21,T49,T421

 LINE       28261
 EXPRESSION (mio_pad_sleep_mode_34_we & mio_pad_sleep_regwen_34_qs)
             ------------1-----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T169,T179,T422
1	1	Covered	T21,T49,T421

 LINE       28293
 EXPRESSION (mio_pad_sleep_mode_35_we & mio_pad_sleep_regwen_35_qs)
             ------------1-----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T173,T422,T174
1	1	Covered	T21,T49,T169

 LINE       28325
 EXPRESSION (mio_pad_sleep_mode_36_we & mio_pad_sleep_regwen_36_qs)
             ------------1-----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T421,T179,T422
1	1	Covered	T21,T49,T169

 LINE       28357
 EXPRESSION (mio_pad_sleep_mode_37_we & mio_pad_sleep_regwen_37_qs)
             ------------1-----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T421,T422,T174
1	1	Covered	T21,T49,T169

 LINE       28389
 EXPRESSION (mio_pad_sleep_mode_38_we & mio_pad_sleep_regwen_38_qs)
             ------------1-----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T421,T173,T179
1	1	Covered	T21,T49,T169

 LINE       28421
 EXPRESSION (mio_pad_sleep_mode_39_we & mio_pad_sleep_regwen_39_qs)
             ------------1-----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T422,T444,T447
1	1	Covered	T21,T49,T169

 LINE       28453
 EXPRESSION (mio_pad_sleep_mode_40_we & mio_pad_sleep_regwen_40_qs)
             ------------1-----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T421,T422,T444
1	1	Covered	T21,T49,T169

 LINE       28485
 EXPRESSION (mio_pad_sleep_mode_41_we & mio_pad_sleep_regwen_41_qs)
             ------------1-----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T422,T174,T175
1	1	Covered	T21,T49,T100

 LINE       28517
 EXPRESSION (mio_pad_sleep_mode_42_we & mio_pad_sleep_regwen_42_qs)
             ------------1-----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T169,T422,T444
1	1	Covered	T21,T49,T421

 LINE       28549
 EXPRESSION (mio_pad_sleep_mode_43_we & mio_pad_sleep_regwen_43_qs)
             ------------1-----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T421,T179,T422
1	1	Covered	T21,T49,T559

 LINE       28581
 EXPRESSION (mio_pad_sleep_mode_44_we & mio_pad_sleep_regwen_44_qs)
             ------------1-----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T421,T422,T443
1	1	Covered	T21,T49,T169

 LINE       28613
 EXPRESSION (mio_pad_sleep_mode_45_we & mio_pad_sleep_regwen_45_qs)
             ------------1-----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T421,T422,T443
1	1	Covered	T21,T49,T169

 LINE       28645
 EXPRESSION (mio_pad_sleep_mode_46_we & mio_pad_sleep_regwen_46_qs)
             ------------1-----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T421,T173,T179
1	1	Covered	T21,T49,T169

 LINE       29576
 EXPRESSION (dio_pad_sleep_en_0_we & dio_pad_sleep_regwen_0_qs)
             ----------1----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T173,T422,T443
1	1	Covered	T21,T49,T448

 LINE       29608
 EXPRESSION (dio_pad_sleep_en_1_we & dio_pad_sleep_regwen_1_qs)
             ----------1----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T173,T444,T446
1	1	Covered	T21,T49,T169

 LINE       29640
 EXPRESSION (dio_pad_sleep_en_2_we & dio_pad_sleep_regwen_2_qs)
             ----------1----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T179,T174,T444
1	1	Covered	T21,T49,T169

 LINE       29672
 EXPRESSION (dio_pad_sleep_en_3_we & dio_pad_sleep_regwen_3_qs)
             ----------1----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T173,T422,T444
1	1	Covered	T21,T49,T169

 LINE       29704
 EXPRESSION (dio_pad_sleep_en_4_we & dio_pad_sleep_regwen_4_qs)
             ----------1----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T173,T179,T422
1	1	Covered	T21,T49,T169

 LINE       29736
 EXPRESSION (dio_pad_sleep_en_5_we & dio_pad_sleep_regwen_5_qs)
             ----------1----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T169,T179,T444
1	1	Covered	T21,T49,T421

 LINE       29768
 EXPRESSION (dio_pad_sleep_en_6_we & dio_pad_sleep_regwen_6_qs)
             ----------1----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T169,T176,T432
1	1	Covered	T6,T21,T67

 LINE       29800
 EXPRESSION (dio_pad_sleep_en_7_we & dio_pad_sleep_regwen_7_qs)
             ----------1----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T422,T443,T480
1	1	Covered	T6,T21,T67

 LINE       29832
 EXPRESSION (dio_pad_sleep_en_8_we & dio_pad_sleep_regwen_8_qs)
             ----------1----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T169,T421,T422
1	1	Covered	T6,T21,T67

 LINE       29864
 EXPRESSION (dio_pad_sleep_en_9_we & dio_pad_sleep_regwen_9_qs)
             ----------1----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T169,T421,T173
1	1	Covered	T6,T21,T67

 LINE       29896
 EXPRESSION (dio_pad_sleep_en_10_we & dio_pad_sleep_regwen_10_qs)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T179,T443,T482
1	1	Covered	T21,T49,T169

 LINE       29928
 EXPRESSION (dio_pad_sleep_en_11_we & dio_pad_sleep_regwen_11_qs)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T173,T179,T422
1	1	Covered	T21,T49,T448

 LINE       29960
 EXPRESSION (dio_pad_sleep_en_12_we & dio_pad_sleep_regwen_12_qs)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T421,T179,T174
1	1	Covered	T21,T49,T169

 LINE       29992
 EXPRESSION (dio_pad_sleep_en_13_we & dio_pad_sleep_regwen_13_qs)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T421,T173,T422
1	1	Covered	T21,T49,T169

 LINE       30024
 EXPRESSION (dio_pad_sleep_en_14_we & dio_pad_sleep_regwen_14_qs)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T173,T174,T176
1	1	Covered	T21,T49,T100

 LINE       30056
 EXPRESSION (dio_pad_sleep_en_15_we & dio_pad_sleep_regwen_15_qs)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T422,T174,T443
1	1	Covered	T21,T49,T169

 LINE       30088
 EXPRESSION (dio_pad_sleep_mode_0_we & dio_pad_sleep_regwen_0_qs)
             -----------1-----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T173,T422,T443
1	1	Covered	T21,T49,T169

 LINE       30120
 EXPRESSION (dio_pad_sleep_mode_1_we & dio_pad_sleep_regwen_1_qs)
             -----------1-----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T173,T444,T446
1	1	Covered	T21,T49,T185

 LINE       30152
 EXPRESSION (dio_pad_sleep_mode_2_we & dio_pad_sleep_regwen_2_qs)
             -----------1-----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T174,T176,T444
1	1	Covered	T21,T49,T448

 LINE       30184
 EXPRESSION (dio_pad_sleep_mode_3_we & dio_pad_sleep_regwen_3_qs)
             -----------1-----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T422,T444,T432
1	1	Covered	T21,T49,T169

 LINE       30216
 EXPRESSION (dio_pad_sleep_mode_4_we & dio_pad_sleep_regwen_4_qs)
             -----------1-----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T422,T174,T176
1	1	Covered	T21,T49,T524

 LINE       30248
 EXPRESSION (dio_pad_sleep_mode_5_we & dio_pad_sleep_regwen_5_qs)
             -----------1-----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T169,T179,T444
1	1	Covered	T21,T49,T457

 LINE       30280
 EXPRESSION (dio_pad_sleep_mode_6_we & dio_pad_sleep_regwen_6_qs)
             -----------1-----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T169,T179,T176
1	1	Covered	T6,T21,T67

 LINE       30312
 EXPRESSION (dio_pad_sleep_mode_7_we & dio_pad_sleep_regwen_7_qs)
             -----------1-----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T421,T422,T443
1	1	Covered	T6,T21,T67

 LINE       30344
 EXPRESSION (dio_pad_sleep_mode_8_we & dio_pad_sleep_regwen_8_qs)
             -----------1-----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T421,T422,T482
1	1	Covered	T6,T21,T67

 LINE       30376
 EXPRESSION (dio_pad_sleep_mode_9_we & dio_pad_sleep_regwen_9_qs)
             -----------1-----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T169,T173,T179
1	1	Covered	T6,T21,T67

 LINE       30408
 EXPRESSION (dio_pad_sleep_mode_10_we & dio_pad_sleep_regwen_10_qs)
             ------------1-----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T179,T443,T176
1	1	Covered	T21,T49,T169

 LINE       30440
 EXPRESSION (dio_pad_sleep_mode_11_we & dio_pad_sleep_regwen_11_qs)
             ------------1-----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T169,T173,T179
1	1	Covered	T21,T49,T421

 LINE       30472
 EXPRESSION (dio_pad_sleep_mode_12_we & dio_pad_sleep_regwen_12_qs)
             ------------1-----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T173,T179,T174
1	1	Covered	T21,T49,T169

 LINE       30504
 EXPRESSION (dio_pad_sleep_mode_13_we & dio_pad_sleep_regwen_13_qs)
             ------------1-----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T421,T173,T422
1	1	Covered	T21,T49,T169

 LINE       30536
 EXPRESSION (dio_pad_sleep_mode_14_we & dio_pad_sleep_regwen_14_qs)
             ------------1-----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T173,T176,T175
1	1	Covered	T21,T49,T169

 LINE       30568
 EXPRESSION (dio_pad_sleep_mode_15_we & dio_pad_sleep_regwen_15_qs)
             ------------1-----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T422,T174,T443
1	1	Covered	T21,T49,T169

 LINE       30832
 EXPRESSION (aon_wkup_detector_en_0_we & aon_wkup_detector_en_0_regwen)
             ------------1------------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T179,T443,T176
1	1	Covered	T6,T27,T79

 LINE       30865
 EXPRESSION (aon_wkup_detector_en_1_we & aon_wkup_detector_en_1_regwen)
             ------------1------------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T179,T422,T444
1	1	Covered	T169,T421,T173

 LINE       30898
 EXPRESSION (aon_wkup_detector_en_2_we & aon_wkup_detector_en_2_regwen)
             ------------1------------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T179,T422,T446
1	1	Covered	T169,T421,T173

 LINE       30931
 EXPRESSION (aon_wkup_detector_en_3_we & aon_wkup_detector_en_3_regwen)
             ------------1------------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T169,T179,T422
1	1	Covered	T421,T173,T179

 LINE       30964
 EXPRESSION (aon_wkup_detector_en_4_we & aon_wkup_detector_en_4_regwen)
             ------------1------------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T179,T422,T174
1	1	Covered	T25,T169,T421

 LINE       30997
 EXPRESSION (aon_wkup_detector_en_5_we & aon_wkup_detector_en_5_regwen)
             ------------1------------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T422,T174,T444
1	1	Covered	T80,T81,T82

 LINE       31030
 EXPRESSION (aon_wkup_detector_en_6_we & aon_wkup_detector_en_6_regwen)
             ------------1------------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T179,T443,T446
1	1	Covered	T169,T421,T173

 LINE       31063
 EXPRESSION (aon_wkup_detector_en_7_we & aon_wkup_detector_en_7_regwen)
             ------------1------------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T422,T174,T444
1	1	Covered	T5,T26,T169

 LINE       31096
 EXPRESSION (aon_wkup_detector_0_we & aon_wkup_detector_0_regwen)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T179,T443,T176
1	1	Covered	T6,T27,T79

 LINE       31183
 EXPRESSION (aon_wkup_detector_1_we & aon_wkup_detector_1_regwen)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T421,T422,T174
1	1	Covered	T169,T173,T179

 LINE       31270
 EXPRESSION (aon_wkup_detector_2_we & aon_wkup_detector_2_regwen)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T173,T179,T422
1	1	Covered	T169,T421,T179

 LINE       31357
 EXPRESSION (aon_wkup_detector_3_we & aon_wkup_detector_3_regwen)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T169,T179,T422
1	1	Covered	T421,T173,T179

 LINE       31444
 EXPRESSION (aon_wkup_detector_4_we & aon_wkup_detector_4_regwen)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T169,T179,T422
1	1	Covered	T25,T421,T173

 LINE       31531
 EXPRESSION (aon_wkup_detector_5_we & aon_wkup_detector_5_regwen)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T422,T174,T444
1	1	Covered	T80,T81,T82

 LINE       31618
 EXPRESSION (aon_wkup_detector_6_we & aon_wkup_detector_6_regwen)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T179,T176,T432
1	1	Covered	T169,T421,T173

 LINE       31705
 EXPRESSION (aon_wkup_detector_7_we & aon_wkup_detector_7_regwen)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T169,T422,T174
1	1	Covered	T5,T26,T421

 LINE       31792
 EXPRESSION (aon_wkup_detector_cnt_th_0_we & aon_wkup_detector_cnt_th_0_regwen)
             --------------1--------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T179,T443,T176
1	1	Covered	T169,T421,T173

 LINE       31825
 EXPRESSION (aon_wkup_detector_cnt_th_1_we & aon_wkup_detector_cnt_th_1_regwen)
             --------------1--------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T422,T444,T446
1	1	Covered	T93,T123,T124

 LINE       31858
 EXPRESSION (aon_wkup_detector_cnt_th_2_we & aon_wkup_detector_cnt_th_2_regwen)
             --------------1--------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T173,T422,T432
1	1	Covered	T169,T421,T179

 LINE       31891
 EXPRESSION (aon_wkup_detector_cnt_th_3_we & aon_wkup_detector_cnt_th_3_regwen)
             --------------1--------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T169,T179,T422
1	1	Covered	T421,T173,T179

 LINE       31924
 EXPRESSION (aon_wkup_detector_cnt_th_4_we & aon_wkup_detector_cnt_th_4_regwen)
             --------------1--------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T169,T422,T444
1	1	Covered	T421,T173,T179

 LINE       31957
 EXPRESSION (aon_wkup_detector_cnt_th_5_we & aon_wkup_detector_cnt_th_5_regwen)
             --------------1--------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T422,T174,T444
1	1	Covered	T169,T421,T173

 LINE       31990
 EXPRESSION (aon_wkup_detector_cnt_th_6_we & aon_wkup_detector_cnt_th_6_regwen)
             --------------1--------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T179,T443,T176
1	1	Covered	T169,T421,T173

 LINE       32023
 EXPRESSION (aon_wkup_detector_cnt_th_7_we & aon_wkup_detector_cnt_th_7_regwen)
             --------------1--------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T422,T174,T444
1	1	Covered	T169,T421,T173

 LINE       32056
 EXPRESSION (wkup_detector_padsel_0_we & wkup_detector_regwen_0_qs)
             ------------1------------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T179,T443,T444
1	1	Covered	T6,T27,T79

 LINE       32088
 EXPRESSION (wkup_detector_padsel_1_we & wkup_detector_regwen_1_qs)
             ------------1------------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T421,T422,T443
1	1	Covered	T169,T538,T173

 LINE       32120
 EXPRESSION (wkup_detector_padsel_2_we & wkup_detector_regwen_2_qs)
             ------------1------------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T179,T422,T445
1	1	Covered	T100,T169,T421

 LINE       32152
 EXPRESSION (wkup_detector_padsel_3_we & wkup_detector_regwen_3_qs)
             ------------1------------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T169,T173,T179
1	1	Covered	T421,T179,T174

 LINE       32184
 EXPRESSION (wkup_detector_padsel_4_we & wkup_detector_regwen_4_qs)
             ------------1------------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T169,T179,T422
1	1	Covered	T25,T421,T173

 LINE       32216
 EXPRESSION (wkup_detector_padsel_5_we & wkup_detector_regwen_5_qs)
             ------------1------------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T422,T174,T444
1	1	Covered	T80,T81,T82

 LINE       32248
 EXPRESSION (wkup_detector_padsel_6_we & wkup_detector_regwen_6_qs)
             ------------1------------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T179,T432,T445
1	1	Covered	T169,T421,T459

 LINE       32280
 EXPRESSION (wkup_detector_padsel_7_we & wkup_detector_regwen_7_qs)
             ------------1------------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T169,T422,T444
1	1	Covered	T5,T26,T421

 LINE       32533
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_ALERT_TEST_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       32534
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_0_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       32535
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_1_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       32536
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_2_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       32537
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_3_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       32538
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_4_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       32539
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_5_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       32540
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_6_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       32541
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_7_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       32542
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_8_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       32543
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_9_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       32544
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_10_OFFSET)
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       32545
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_11_OFFSET)
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       32546
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_12_OFFSET)
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       32547
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_13_OFFSET)
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3