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69 always_ff @(posedge clk_i or negedge rst_ni) begin
70 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
71 1/1 err_q <= '0;
Tests: T1 T2 T3
72 1/1 end else if (intg_err || reg_we_err) begin
Tests: T1 T2 T3
73 1/1 err_q <= 1'b1;
Tests: T108 T109 T110
74 end
MISSING_ELSE
75 end
76
77 // integrity error output is permanent and should be used for alert generation
78 // register errors are transactional
79 1/1 assign intg_err_o = err_q | intg_err | reg_we_err;
Tests: T1 T2 T3
80
81 // outgoing integrity generation
82 tlul_pkg::tl_d2h_t tl_o_pre;
83 tlul_rsp_intg_gen #(
84 .EnableRspIntgGen(1),
85 .EnableDataIntgGen(1)
86 ) u_rsp_intg_gen (
87 .tl_i(tl_o_pre),
88 .tl_o(tl_o)
89 );
90
91 1/1 assign tl_reg_h2d = tl_i;
Tests: T1 T2 T3
92 1/1 assign tl_o_pre = tl_reg_d2h;
Tests: T1 T2 T3
93
94 tlul_adapter_reg #(
95 .RegAw(AW),
96 .RegDw(DW),
97 .EnableDataIntgGen(0)
98 ) u_reg_if (
99 .clk_i (clk_i),
100 .rst_ni (rst_ni),
101
102 .tl_i (tl_reg_h2d),
103 .tl_o (tl_reg_d2h),
104
105 .en_ifetch_i(prim_mubi_pkg::MuBi4False),
106 .intg_error_o(),
107
108 .we_o (reg_we),
109 .re_o (reg_re),
110 .addr_o (reg_addr),
111 .wdata_o (reg_wdata),
112 .be_o (reg_be),
113 .busy_i (reg_busy),
114 .rdata_i (reg_rdata),
115 .error_i (reg_error)
116 );
117
118 // cdc oversampling signals
119
120 1/1 assign reg_rdata = reg_rdata_next ;
Tests: T1 T2 T3
121 1/1 assign reg_error = addrmiss | wr_err | intg_err;
Tests: T1 T2 T3
122
123 // Define SW related signals
124 // Format: <reg>_<field>_{wd|we|qs}
125 // or <reg>_{wd|we|qs} if field == 1 or 0
126 logic alert_test_we;
127 logic alert_test_wd;
128 logic mio_periph_insel_regwen_0_we;
129 logic mio_periph_insel_regwen_0_qs;
130 logic mio_periph_insel_regwen_0_wd;
131 logic mio_periph_insel_regwen_1_we;
132 logic mio_periph_insel_regwen_1_qs;
133 logic mio_periph_insel_regwen_1_wd;
134 logic mio_periph_insel_regwen_2_we;
135 logic mio_periph_insel_regwen_2_qs;
136 logic mio_periph_insel_regwen_2_wd;
137 logic mio_periph_insel_regwen_3_we;
138 logic mio_periph_insel_regwen_3_qs;
139 logic mio_periph_insel_regwen_3_wd;
140 logic mio_periph_insel_regwen_4_we;
141 logic mio_periph_insel_regwen_4_qs;
142 logic mio_periph_insel_regwen_4_wd;
143 logic mio_periph_insel_regwen_5_we;
144 logic mio_periph_insel_regwen_5_qs;
145 logic mio_periph_insel_regwen_5_wd;
146 logic mio_periph_insel_regwen_6_we;
147 logic mio_periph_insel_regwen_6_qs;
148 logic mio_periph_insel_regwen_6_wd;
149 logic mio_periph_insel_regwen_7_we;
150 logic mio_periph_insel_regwen_7_qs;
151 logic mio_periph_insel_regwen_7_wd;
152 logic mio_periph_insel_regwen_8_we;
153 logic mio_periph_insel_regwen_8_qs;
154 logic mio_periph_insel_regwen_8_wd;
155 logic mio_periph_insel_regwen_9_we;
156 logic mio_periph_insel_regwen_9_qs;
157 logic mio_periph_insel_regwen_9_wd;
158 logic mio_periph_insel_regwen_10_we;
159 logic mio_periph_insel_regwen_10_qs;
160 logic mio_periph_insel_regwen_10_wd;
161 logic mio_periph_insel_regwen_11_we;
162 logic mio_periph_insel_regwen_11_qs;
163 logic mio_periph_insel_regwen_11_wd;
164 logic mio_periph_insel_regwen_12_we;
165 logic mio_periph_insel_regwen_12_qs;
166 logic mio_periph_insel_regwen_12_wd;
167 logic mio_periph_insel_regwen_13_we;
168 logic mio_periph_insel_regwen_13_qs;
169 logic mio_periph_insel_regwen_13_wd;
170 logic mio_periph_insel_regwen_14_we;
171 logic mio_periph_insel_regwen_14_qs;
172 logic mio_periph_insel_regwen_14_wd;
173 logic mio_periph_insel_regwen_15_we;
174 logic mio_periph_insel_regwen_15_qs;
175 logic mio_periph_insel_regwen_15_wd;
176 logic mio_periph_insel_regwen_16_we;
177 logic mio_periph_insel_regwen_16_qs;
178 logic mio_periph_insel_regwen_16_wd;
179 logic mio_periph_insel_regwen_17_we;
180 logic mio_periph_insel_regwen_17_qs;
181 logic mio_periph_insel_regwen_17_wd;
182 logic mio_periph_insel_regwen_18_we;
183 logic mio_periph_insel_regwen_18_qs;
184 logic mio_periph_insel_regwen_18_wd;
185 logic mio_periph_insel_regwen_19_we;
186 logic mio_periph_insel_regwen_19_qs;
187 logic mio_periph_insel_regwen_19_wd;
188 logic mio_periph_insel_regwen_20_we;
189 logic mio_periph_insel_regwen_20_qs;
190 logic mio_periph_insel_regwen_20_wd;
191 logic mio_periph_insel_regwen_21_we;
192 logic mio_periph_insel_regwen_21_qs;
193 logic mio_periph_insel_regwen_21_wd;
194 logic mio_periph_insel_regwen_22_we;
195 logic mio_periph_insel_regwen_22_qs;
196 logic mio_periph_insel_regwen_22_wd;
197 logic mio_periph_insel_regwen_23_we;
198 logic mio_periph_insel_regwen_23_qs;
199 logic mio_periph_insel_regwen_23_wd;
200 logic mio_periph_insel_regwen_24_we;
201 logic mio_periph_insel_regwen_24_qs;
202 logic mio_periph_insel_regwen_24_wd;
203 logic mio_periph_insel_regwen_25_we;
204 logic mio_periph_insel_regwen_25_qs;
205 logic mio_periph_insel_regwen_25_wd;
206 logic mio_periph_insel_regwen_26_we;
207 logic mio_periph_insel_regwen_26_qs;
208 logic mio_periph_insel_regwen_26_wd;
209 logic mio_periph_insel_regwen_27_we;
210 logic mio_periph_insel_regwen_27_qs;
211 logic mio_periph_insel_regwen_27_wd;
212 logic mio_periph_insel_regwen_28_we;
213 logic mio_periph_insel_regwen_28_qs;
214 logic mio_periph_insel_regwen_28_wd;
215 logic mio_periph_insel_regwen_29_we;
216 logic mio_periph_insel_regwen_29_qs;
217 logic mio_periph_insel_regwen_29_wd;
218 logic mio_periph_insel_regwen_30_we;
219 logic mio_periph_insel_regwen_30_qs;
220 logic mio_periph_insel_regwen_30_wd;
221 logic mio_periph_insel_regwen_31_we;
222 logic mio_periph_insel_regwen_31_qs;
223 logic mio_periph_insel_regwen_31_wd;
224 logic mio_periph_insel_regwen_32_we;
225 logic mio_periph_insel_regwen_32_qs;
226 logic mio_periph_insel_regwen_32_wd;
227 logic mio_periph_insel_regwen_33_we;
228 logic mio_periph_insel_regwen_33_qs;
229 logic mio_periph_insel_regwen_33_wd;
230 logic mio_periph_insel_regwen_34_we;
231 logic mio_periph_insel_regwen_34_qs;
232 logic mio_periph_insel_regwen_34_wd;
233 logic mio_periph_insel_regwen_35_we;
234 logic mio_periph_insel_regwen_35_qs;
235 logic mio_periph_insel_regwen_35_wd;
236 logic mio_periph_insel_regwen_36_we;
237 logic mio_periph_insel_regwen_36_qs;
238 logic mio_periph_insel_regwen_36_wd;
239 logic mio_periph_insel_regwen_37_we;
240 logic mio_periph_insel_regwen_37_qs;
241 logic mio_periph_insel_regwen_37_wd;
242 logic mio_periph_insel_regwen_38_we;
243 logic mio_periph_insel_regwen_38_qs;
244 logic mio_periph_insel_regwen_38_wd;
245 logic mio_periph_insel_regwen_39_we;
246 logic mio_periph_insel_regwen_39_qs;
247 logic mio_periph_insel_regwen_39_wd;
248 logic mio_periph_insel_regwen_40_we;
249 logic mio_periph_insel_regwen_40_qs;
250 logic mio_periph_insel_regwen_40_wd;
251 logic mio_periph_insel_regwen_41_we;
252 logic mio_periph_insel_regwen_41_qs;
253 logic mio_periph_insel_regwen_41_wd;
254 logic mio_periph_insel_regwen_42_we;
255 logic mio_periph_insel_regwen_42_qs;
256 logic mio_periph_insel_regwen_42_wd;
257 logic mio_periph_insel_regwen_43_we;
258 logic mio_periph_insel_regwen_43_qs;
259 logic mio_periph_insel_regwen_43_wd;
260 logic mio_periph_insel_regwen_44_we;
261 logic mio_periph_insel_regwen_44_qs;
262 logic mio_periph_insel_regwen_44_wd;
263 logic mio_periph_insel_regwen_45_we;
264 logic mio_periph_insel_regwen_45_qs;
265 logic mio_periph_insel_regwen_45_wd;
266 logic mio_periph_insel_regwen_46_we;
267 logic mio_periph_insel_regwen_46_qs;
268 logic mio_periph_insel_regwen_46_wd;
269 logic mio_periph_insel_regwen_47_we;
270 logic mio_periph_insel_regwen_47_qs;
271 logic mio_periph_insel_regwen_47_wd;
272 logic mio_periph_insel_regwen_48_we;
273 logic mio_periph_insel_regwen_48_qs;
274 logic mio_periph_insel_regwen_48_wd;
275 logic mio_periph_insel_regwen_49_we;
276 logic mio_periph_insel_regwen_49_qs;
277 logic mio_periph_insel_regwen_49_wd;
278 logic mio_periph_insel_regwen_50_we;
279 logic mio_periph_insel_regwen_50_qs;
280 logic mio_periph_insel_regwen_50_wd;
281 logic mio_periph_insel_regwen_51_we;
282 logic mio_periph_insel_regwen_51_qs;
283 logic mio_periph_insel_regwen_51_wd;
284 logic mio_periph_insel_regwen_52_we;
285 logic mio_periph_insel_regwen_52_qs;
286 logic mio_periph_insel_regwen_52_wd;
287 logic mio_periph_insel_regwen_53_we;
288 logic mio_periph_insel_regwen_53_qs;
289 logic mio_periph_insel_regwen_53_wd;
290 logic mio_periph_insel_regwen_54_we;
291 logic mio_periph_insel_regwen_54_qs;
292 logic mio_periph_insel_regwen_54_wd;
293 logic mio_periph_insel_regwen_55_we;
294 logic mio_periph_insel_regwen_55_qs;
295 logic mio_periph_insel_regwen_55_wd;
296 logic mio_periph_insel_regwen_56_we;
297 logic mio_periph_insel_regwen_56_qs;
298 logic mio_periph_insel_regwen_56_wd;
299 logic mio_periph_insel_0_we;
300 logic [5:0] mio_periph_insel_0_qs;
301 logic [5:0] mio_periph_insel_0_wd;
302 logic mio_periph_insel_1_we;
303 logic [5:0] mio_periph_insel_1_qs;
304 logic [5:0] mio_periph_insel_1_wd;
305 logic mio_periph_insel_2_we;
306 logic [5:0] mio_periph_insel_2_qs;
307 logic [5:0] mio_periph_insel_2_wd;
308 logic mio_periph_insel_3_we;
309 logic [5:0] mio_periph_insel_3_qs;
310 logic [5:0] mio_periph_insel_3_wd;
311 logic mio_periph_insel_4_we;
312 logic [5:0] mio_periph_insel_4_qs;
313 logic [5:0] mio_periph_insel_4_wd;
314 logic mio_periph_insel_5_we;
315 logic [5:0] mio_periph_insel_5_qs;
316 logic [5:0] mio_periph_insel_5_wd;
317 logic mio_periph_insel_6_we;
318 logic [5:0] mio_periph_insel_6_qs;
319 logic [5:0] mio_periph_insel_6_wd;
320 logic mio_periph_insel_7_we;
321 logic [5:0] mio_periph_insel_7_qs;
322 logic [5:0] mio_periph_insel_7_wd;
323 logic mio_periph_insel_8_we;
324 logic [5:0] mio_periph_insel_8_qs;
325 logic [5:0] mio_periph_insel_8_wd;
326 logic mio_periph_insel_9_we;
327 logic [5:0] mio_periph_insel_9_qs;
328 logic [5:0] mio_periph_insel_9_wd;
329 logic mio_periph_insel_10_we;
330 logic [5:0] mio_periph_insel_10_qs;
331 logic [5:0] mio_periph_insel_10_wd;
332 logic mio_periph_insel_11_we;
333 logic [5:0] mio_periph_insel_11_qs;
334 logic [5:0] mio_periph_insel_11_wd;
335 logic mio_periph_insel_12_we;
336 logic [5:0] mio_periph_insel_12_qs;
337 logic [5:0] mio_periph_insel_12_wd;
338 logic mio_periph_insel_13_we;
339 logic [5:0] mio_periph_insel_13_qs;
340 logic [5:0] mio_periph_insel_13_wd;
341 logic mio_periph_insel_14_we;
342 logic [5:0] mio_periph_insel_14_qs;
343 logic [5:0] mio_periph_insel_14_wd;
344 logic mio_periph_insel_15_we;
345 logic [5:0] mio_periph_insel_15_qs;
346 logic [5:0] mio_periph_insel_15_wd;
347 logic mio_periph_insel_16_we;
348 logic [5:0] mio_periph_insel_16_qs;
349 logic [5:0] mio_periph_insel_16_wd;
350 logic mio_periph_insel_17_we;
351 logic [5:0] mio_periph_insel_17_qs;
352 logic [5:0] mio_periph_insel_17_wd;
353 logic mio_periph_insel_18_we;
354 logic [5:0] mio_periph_insel_18_qs;
355 logic [5:0] mio_periph_insel_18_wd;
356 logic mio_periph_insel_19_we;
357 logic [5:0] mio_periph_insel_19_qs;
358 logic [5:0] mio_periph_insel_19_wd;
359 logic mio_periph_insel_20_we;
360 logic [5:0] mio_periph_insel_20_qs;
361 logic [5:0] mio_periph_insel_20_wd;
362 logic mio_periph_insel_21_we;
363 logic [5:0] mio_periph_insel_21_qs;
364 logic [5:0] mio_periph_insel_21_wd;
365 logic mio_periph_insel_22_we;
366 logic [5:0] mio_periph_insel_22_qs;
367 logic [5:0] mio_periph_insel_22_wd;
368 logic mio_periph_insel_23_we;
369 logic [5:0] mio_periph_insel_23_qs;
370 logic [5:0] mio_periph_insel_23_wd;
371 logic mio_periph_insel_24_we;
372 logic [5:0] mio_periph_insel_24_qs;
373 logic [5:0] mio_periph_insel_24_wd;
374 logic mio_periph_insel_25_we;
375 logic [5:0] mio_periph_insel_25_qs;
376 logic [5:0] mio_periph_insel_25_wd;
377 logic mio_periph_insel_26_we;
378 logic [5:0] mio_periph_insel_26_qs;
379 logic [5:0] mio_periph_insel_26_wd;
380 logic mio_periph_insel_27_we;
381 logic [5:0] mio_periph_insel_27_qs;
382 logic [5:0] mio_periph_insel_27_wd;
383 logic mio_periph_insel_28_we;
384 logic [5:0] mio_periph_insel_28_qs;
385 logic [5:0] mio_periph_insel_28_wd;
386 logic mio_periph_insel_29_we;
387 logic [5:0] mio_periph_insel_29_qs;
388 logic [5:0] mio_periph_insel_29_wd;
389 logic mio_periph_insel_30_we;
390 logic [5:0] mio_periph_insel_30_qs;
391 logic [5:0] mio_periph_insel_30_wd;
392 logic mio_periph_insel_31_we;
393 logic [5:0] mio_periph_insel_31_qs;
394 logic [5:0] mio_periph_insel_31_wd;
395 logic mio_periph_insel_32_we;
396 logic [5:0] mio_periph_insel_32_qs;
397 logic [5:0] mio_periph_insel_32_wd;
398 logic mio_periph_insel_33_we;
399 logic [5:0] mio_periph_insel_33_qs;
400 logic [5:0] mio_periph_insel_33_wd;
401 logic mio_periph_insel_34_we;
402 logic [5:0] mio_periph_insel_34_qs;
403 logic [5:0] mio_periph_insel_34_wd;
404 logic mio_periph_insel_35_we;
405 logic [5:0] mio_periph_insel_35_qs;
406 logic [5:0] mio_periph_insel_35_wd;
407 logic mio_periph_insel_36_we;
408 logic [5:0] mio_periph_insel_36_qs;
409 logic [5:0] mio_periph_insel_36_wd;
410 logic mio_periph_insel_37_we;
411 logic [5:0] mio_periph_insel_37_qs;
412 logic [5:0] mio_periph_insel_37_wd;
413 logic mio_periph_insel_38_we;
414 logic [5:0] mio_periph_insel_38_qs;
415 logic [5:0] mio_periph_insel_38_wd;
416 logic mio_periph_insel_39_we;
417 logic [5:0] mio_periph_insel_39_qs;
418 logic [5:0] mio_periph_insel_39_wd;
419 logic mio_periph_insel_40_we;
420 logic [5:0] mio_periph_insel_40_qs;
421 logic [5:0] mio_periph_insel_40_wd;
422 logic mio_periph_insel_41_we;
423 logic [5:0] mio_periph_insel_41_qs;
424 logic [5:0] mio_periph_insel_41_wd;
425 logic mio_periph_insel_42_we;
426 logic [5:0] mio_periph_insel_42_qs;
427 logic [5:0] mio_periph_insel_42_wd;
428 logic mio_periph_insel_43_we;
429 logic [5:0] mio_periph_insel_43_qs;
430 logic [5:0] mio_periph_insel_43_wd;
431 logic mio_periph_insel_44_we;
432 logic [5:0] mio_periph_insel_44_qs;
433 logic [5:0] mio_periph_insel_44_wd;
434 logic mio_periph_insel_45_we;
435 logic [5:0] mio_periph_insel_45_qs;
436 logic [5:0] mio_periph_insel_45_wd;
437 logic mio_periph_insel_46_we;
438 logic [5:0] mio_periph_insel_46_qs;
439 logic [5:0] mio_periph_insel_46_wd;
440 logic mio_periph_insel_47_we;
441 logic [5:0] mio_periph_insel_47_qs;
442 logic [5:0] mio_periph_insel_47_wd;
443 logic mio_periph_insel_48_we;
444 logic [5:0] mio_periph_insel_48_qs;
445 logic [5:0] mio_periph_insel_48_wd;
446 logic mio_periph_insel_49_we;
447 logic [5:0] mio_periph_insel_49_qs;
448 logic [5:0] mio_periph_insel_49_wd;
449 logic mio_periph_insel_50_we;
450 logic [5:0] mio_periph_insel_50_qs;
451 logic [5:0] mio_periph_insel_50_wd;
452 logic mio_periph_insel_51_we;
453 logic [5:0] mio_periph_insel_51_qs;
454 logic [5:0] mio_periph_insel_51_wd;
455 logic mio_periph_insel_52_we;
456 logic [5:0] mio_periph_insel_52_qs;
457 logic [5:0] mio_periph_insel_52_wd;
458 logic mio_periph_insel_53_we;
459 logic [5:0] mio_periph_insel_53_qs;
460 logic [5:0] mio_periph_insel_53_wd;
461 logic mio_periph_insel_54_we;
462 logic [5:0] mio_periph_insel_54_qs;
463 logic [5:0] mio_periph_insel_54_wd;
464 logic mio_periph_insel_55_we;
465 logic [5:0] mio_periph_insel_55_qs;
466 logic [5:0] mio_periph_insel_55_wd;
467 logic mio_periph_insel_56_we;
468 logic [5:0] mio_periph_insel_56_qs;
469 logic [5:0] mio_periph_insel_56_wd;
470 logic mio_outsel_regwen_0_we;
471 logic mio_outsel_regwen_0_qs;
472 logic mio_outsel_regwen_0_wd;
473 logic mio_outsel_regwen_1_we;
474 logic mio_outsel_regwen_1_qs;
475 logic mio_outsel_regwen_1_wd;
476 logic mio_outsel_regwen_2_we;
477 logic mio_outsel_regwen_2_qs;
478 logic mio_outsel_regwen_2_wd;
479 logic mio_outsel_regwen_3_we;
480 logic mio_outsel_regwen_3_qs;
481 logic mio_outsel_regwen_3_wd;
482 logic mio_outsel_regwen_4_we;
483 logic mio_outsel_regwen_4_qs;
484 logic mio_outsel_regwen_4_wd;
485 logic mio_outsel_regwen_5_we;
486 logic mio_outsel_regwen_5_qs;
487 logic mio_outsel_regwen_5_wd;
488 logic mio_outsel_regwen_6_we;
489 logic mio_outsel_regwen_6_qs;
490 logic mio_outsel_regwen_6_wd;
491 logic mio_outsel_regwen_7_we;
492 logic mio_outsel_regwen_7_qs;
493 logic mio_outsel_regwen_7_wd;
494 logic mio_outsel_regwen_8_we;
495 logic mio_outsel_regwen_8_qs;
496 logic mio_outsel_regwen_8_wd;
497 logic mio_outsel_regwen_9_we;
498 logic mio_outsel_regwen_9_qs;
499 logic mio_outsel_regwen_9_wd;
500 logic mio_outsel_regwen_10_we;
501 logic mio_outsel_regwen_10_qs;
502 logic mio_outsel_regwen_10_wd;
503 logic mio_outsel_regwen_11_we;
504 logic mio_outsel_regwen_11_qs;
505 logic mio_outsel_regwen_11_wd;
506 logic mio_outsel_regwen_12_we;
507 logic mio_outsel_regwen_12_qs;
508 logic mio_outsel_regwen_12_wd;
509 logic mio_outsel_regwen_13_we;
510 logic mio_outsel_regwen_13_qs;
511 logic mio_outsel_regwen_13_wd;
512 logic mio_outsel_regwen_14_we;
513 logic mio_outsel_regwen_14_qs;
514 logic mio_outsel_regwen_14_wd;
515 logic mio_outsel_regwen_15_we;
516 logic mio_outsel_regwen_15_qs;
517 logic mio_outsel_regwen_15_wd;
518 logic mio_outsel_regwen_16_we;
519 logic mio_outsel_regwen_16_qs;
520 logic mio_outsel_regwen_16_wd;
521 logic mio_outsel_regwen_17_we;
522 logic mio_outsel_regwen_17_qs;
523 logic mio_outsel_regwen_17_wd;
524 logic mio_outsel_regwen_18_we;
525 logic mio_outsel_regwen_18_qs;
526 logic mio_outsel_regwen_18_wd;
527 logic mio_outsel_regwen_19_we;
528 logic mio_outsel_regwen_19_qs;
529 logic mio_outsel_regwen_19_wd;
530 logic mio_outsel_regwen_20_we;
531 logic mio_outsel_regwen_20_qs;
532 logic mio_outsel_regwen_20_wd;
533 logic mio_outsel_regwen_21_we;
534 logic mio_outsel_regwen_21_qs;
535 logic mio_outsel_regwen_21_wd;
536 logic mio_outsel_regwen_22_we;
537 logic mio_outsel_regwen_22_qs;
538 logic mio_outsel_regwen_22_wd;
539 logic mio_outsel_regwen_23_we;
540 logic mio_outsel_regwen_23_qs;
541 logic mio_outsel_regwen_23_wd;
542 logic mio_outsel_regwen_24_we;
543 logic mio_outsel_regwen_24_qs;
544 logic mio_outsel_regwen_24_wd;
545 logic mio_outsel_regwen_25_we;
546 logic mio_outsel_regwen_25_qs;
547 logic mio_outsel_regwen_25_wd;
548 logic mio_outsel_regwen_26_we;
549 logic mio_outsel_regwen_26_qs;
550 logic mio_outsel_regwen_26_wd;
551 logic mio_outsel_regwen_27_we;
552 logic mio_outsel_regwen_27_qs;
553 logic mio_outsel_regwen_27_wd;
554 logic mio_outsel_regwen_28_we;
555 logic mio_outsel_regwen_28_qs;
556 logic mio_outsel_regwen_28_wd;
557 logic mio_outsel_regwen_29_we;
558 logic mio_outsel_regwen_29_qs;
559 logic mio_outsel_regwen_29_wd;
560 logic mio_outsel_regwen_30_we;
561 logic mio_outsel_regwen_30_qs;
562 logic mio_outsel_regwen_30_wd;
563 logic mio_outsel_regwen_31_we;
564 logic mio_outsel_regwen_31_qs;
565 logic mio_outsel_regwen_31_wd;
566 logic mio_outsel_regwen_32_we;
567 logic mio_outsel_regwen_32_qs;
568 logic mio_outsel_regwen_32_wd;
569 logic mio_outsel_regwen_33_we;
570 logic mio_outsel_regwen_33_qs;
571 logic mio_outsel_regwen_33_wd;
572 logic mio_outsel_regwen_34_we;
573 logic mio_outsel_regwen_34_qs;
574 logic mio_outsel_regwen_34_wd;
575 logic mio_outsel_regwen_35_we;
576 logic mio_outsel_regwen_35_qs;
577 logic mio_outsel_regwen_35_wd;
578 logic mio_outsel_regwen_36_we;
579 logic mio_outsel_regwen_36_qs;
580 logic mio_outsel_regwen_36_wd;
581 logic mio_outsel_regwen_37_we;
582 logic mio_outsel_regwen_37_qs;
583 logic mio_outsel_regwen_37_wd;
584 logic mio_outsel_regwen_38_we;
585 logic mio_outsel_regwen_38_qs;
586 logic mio_outsel_regwen_38_wd;
587 logic mio_outsel_regwen_39_we;
588 logic mio_outsel_regwen_39_qs;
589 logic mio_outsel_regwen_39_wd;
590 logic mio_outsel_regwen_40_we;
591 logic mio_outsel_regwen_40_qs;
592 logic mio_outsel_regwen_40_wd;
593 logic mio_outsel_regwen_41_we;
594 logic mio_outsel_regwen_41_qs;
595 logic mio_outsel_regwen_41_wd;
596 logic mio_outsel_regwen_42_we;
597 logic mio_outsel_regwen_42_qs;
598 logic mio_outsel_regwen_42_wd;
599 logic mio_outsel_regwen_43_we;
600 logic mio_outsel_regwen_43_qs;
601 logic mio_outsel_regwen_43_wd;
602 logic mio_outsel_regwen_44_we;
603 logic mio_outsel_regwen_44_qs;
604 logic mio_outsel_regwen_44_wd;
605 logic mio_outsel_regwen_45_we;
606 logic mio_outsel_regwen_45_qs;
607 logic mio_outsel_regwen_45_wd;
608 logic mio_outsel_regwen_46_we;
609 logic mio_outsel_regwen_46_qs;
610 logic mio_outsel_regwen_46_wd;
611 logic mio_outsel_0_we;
612 logic [6:0] mio_outsel_0_qs;
613 logic [6:0] mio_outsel_0_wd;
614 logic mio_outsel_1_we;
615 logic [6:0] mio_outsel_1_qs;
616 logic [6:0] mio_outsel_1_wd;
617 logic mio_outsel_2_we;
618 logic [6:0] mio_outsel_2_qs;
619 logic [6:0] mio_outsel_2_wd;
620 logic mio_outsel_3_we;
621 logic [6:0] mio_outsel_3_qs;
622 logic [6:0] mio_outsel_3_wd;
623 logic mio_outsel_4_we;
624 logic [6:0] mio_outsel_4_qs;
625 logic [6:0] mio_outsel_4_wd;
626 logic mio_outsel_5_we;
627 logic [6:0] mio_outsel_5_qs;
628 logic [6:0] mio_outsel_5_wd;
629 logic mio_outsel_6_we;
630 logic [6:0] mio_outsel_6_qs;
631 logic [6:0] mio_outsel_6_wd;
632 logic mio_outsel_7_we;
633 logic [6:0] mio_outsel_7_qs;
634 logic [6:0] mio_outsel_7_wd;
635 logic mio_outsel_8_we;
636 logic [6:0] mio_outsel_8_qs;
637 logic [6:0] mio_outsel_8_wd;
638 logic mio_outsel_9_we;
639 logic [6:0] mio_outsel_9_qs;
640 logic [6:0] mio_outsel_9_wd;
641 logic mio_outsel_10_we;
642 logic [6:0] mio_outsel_10_qs;
643 logic [6:0] mio_outsel_10_wd;
644 logic mio_outsel_11_we;
645 logic [6:0] mio_outsel_11_qs;
646 logic [6:0] mio_outsel_11_wd;
647 logic mio_outsel_12_we;
648 logic [6:0] mio_outsel_12_qs;
649 logic [6:0] mio_outsel_12_wd;
650 logic mio_outsel_13_we;
651 logic [6:0] mio_outsel_13_qs;
652 logic [6:0] mio_outsel_13_wd;
653 logic mio_outsel_14_we;
654 logic [6:0] mio_outsel_14_qs;
655 logic [6:0] mio_outsel_14_wd;
656 logic mio_outsel_15_we;
657 logic [6:0] mio_outsel_15_qs;
658 logic [6:0] mio_outsel_15_wd;
659 logic mio_outsel_16_we;
660 logic [6:0] mio_outsel_16_qs;
661 logic [6:0] mio_outsel_16_wd;
662 logic mio_outsel_17_we;
663 logic [6:0] mio_outsel_17_qs;
664 logic [6:0] mio_outsel_17_wd;
665 logic mio_outsel_18_we;
666 logic [6:0] mio_outsel_18_qs;
667 logic [6:0] mio_outsel_18_wd;
668 logic mio_outsel_19_we;
669 logic [6:0] mio_outsel_19_qs;
670 logic [6:0] mio_outsel_19_wd;
671 logic mio_outsel_20_we;
672 logic [6:0] mio_outsel_20_qs;
673 logic [6:0] mio_outsel_20_wd;
674 logic mio_outsel_21_we;
675 logic [6:0] mio_outsel_21_qs;
676 logic [6:0] mio_outsel_21_wd;
677 logic mio_outsel_22_we;
678 logic [6:0] mio_outsel_22_qs;
679 logic [6:0] mio_outsel_22_wd;
680 logic mio_outsel_23_we;
681 logic [6:0] mio_outsel_23_qs;
682 logic [6:0] mio_outsel_23_wd;
683 logic mio_outsel_24_we;
684 logic [6:0] mio_outsel_24_qs;
685 logic [6:0] mio_outsel_24_wd;
686 logic mio_outsel_25_we;
687 logic [6:0] mio_outsel_25_qs;
688 logic [6:0] mio_outsel_25_wd;
689 logic mio_outsel_26_we;
690 logic [6:0] mio_outsel_26_qs;
691 logic [6:0] mio_outsel_26_wd;
692 logic mio_outsel_27_we;
693 logic [6:0] mio_outsel_27_qs;
694 logic [6:0] mio_outsel_27_wd;
695 logic mio_outsel_28_we;
696 logic [6:0] mio_outsel_28_qs;
697 logic [6:0] mio_outsel_28_wd;
698 logic mio_outsel_29_we;
699 logic [6:0] mio_outsel_29_qs;
700 logic [6:0] mio_outsel_29_wd;
701 logic mio_outsel_30_we;
702 logic [6:0] mio_outsel_30_qs;
703 logic [6:0] mio_outsel_30_wd;
704 logic mio_outsel_31_we;
705 logic [6:0] mio_outsel_31_qs;
706 logic [6:0] mio_outsel_31_wd;
707 logic mio_outsel_32_we;
708 logic [6:0] mio_outsel_32_qs;
709 logic [6:0] mio_outsel_32_wd;
710 logic mio_outsel_33_we;
711 logic [6:0] mio_outsel_33_qs;
712 logic [6:0] mio_outsel_33_wd;
713 logic mio_outsel_34_we;
714 logic [6:0] mio_outsel_34_qs;
715 logic [6:0] mio_outsel_34_wd;
716 logic mio_outsel_35_we;
717 logic [6:0] mio_outsel_35_qs;
718 logic [6:0] mio_outsel_35_wd;
719 logic mio_outsel_36_we;
720 logic [6:0] mio_outsel_36_qs;
721 logic [6:0] mio_outsel_36_wd;
722 logic mio_outsel_37_we;
723 logic [6:0] mio_outsel_37_qs;
724 logic [6:0] mio_outsel_37_wd;
725 logic mio_outsel_38_we;
726 logic [6:0] mio_outsel_38_qs;
727 logic [6:0] mio_outsel_38_wd;
728 logic mio_outsel_39_we;
729 logic [6:0] mio_outsel_39_qs;
730 logic [6:0] mio_outsel_39_wd;
731 logic mio_outsel_40_we;
732 logic [6:0] mio_outsel_40_qs;
733 logic [6:0] mio_outsel_40_wd;
734 logic mio_outsel_41_we;
735 logic [6:0] mio_outsel_41_qs;
736 logic [6:0] mio_outsel_41_wd;
737 logic mio_outsel_42_we;
738 logic [6:0] mio_outsel_42_qs;
739 logic [6:0] mio_outsel_42_wd;
740 logic mio_outsel_43_we;
741 logic [6:0] mio_outsel_43_qs;
742 logic [6:0] mio_outsel_43_wd;
743 logic mio_outsel_44_we;
744 logic [6:0] mio_outsel_44_qs;
745 logic [6:0] mio_outsel_44_wd;
746 logic mio_outsel_45_we;
747 logic [6:0] mio_outsel_45_qs;
748 logic [6:0] mio_outsel_45_wd;
749 logic mio_outsel_46_we;
750 logic [6:0] mio_outsel_46_qs;
751 logic [6:0] mio_outsel_46_wd;
752 logic mio_pad_attr_regwen_0_we;
753 logic mio_pad_attr_regwen_0_qs;
754 logic mio_pad_attr_regwen_0_wd;
755 logic mio_pad_attr_regwen_1_we;
756 logic mio_pad_attr_regwen_1_qs;
757 logic mio_pad_attr_regwen_1_wd;
758 logic mio_pad_attr_regwen_2_we;
759 logic mio_pad_attr_regwen_2_qs;
760 logic mio_pad_attr_regwen_2_wd;
761 logic mio_pad_attr_regwen_3_we;
762 logic mio_pad_attr_regwen_3_qs;
763 logic mio_pad_attr_regwen_3_wd;
764 logic mio_pad_attr_regwen_4_we;
765 logic mio_pad_attr_regwen_4_qs;
766 logic mio_pad_attr_regwen_4_wd;
767 logic mio_pad_attr_regwen_5_we;
768 logic mio_pad_attr_regwen_5_qs;
769 logic mio_pad_attr_regwen_5_wd;
770 logic mio_pad_attr_regwen_6_we;
771 logic mio_pad_attr_regwen_6_qs;
772 logic mio_pad_attr_regwen_6_wd;
773 logic mio_pad_attr_regwen_7_we;
774 logic mio_pad_attr_regwen_7_qs;
775 logic mio_pad_attr_regwen_7_wd;
776 logic mio_pad_attr_regwen_8_we;
777 logic mio_pad_attr_regwen_8_qs;
778 logic mio_pad_attr_regwen_8_wd;
779 logic mio_pad_attr_regwen_9_we;
780 logic mio_pad_attr_regwen_9_qs;
781 logic mio_pad_attr_regwen_9_wd;
782 logic mio_pad_attr_regwen_10_we;
783 logic mio_pad_attr_regwen_10_qs;
784 logic mio_pad_attr_regwen_10_wd;
785 logic mio_pad_attr_regwen_11_we;
786 logic mio_pad_attr_regwen_11_qs;
787 logic mio_pad_attr_regwen_11_wd;
788 logic mio_pad_attr_regwen_12_we;
789 logic mio_pad_attr_regwen_12_qs;
790 logic mio_pad_attr_regwen_12_wd;
791 logic mio_pad_attr_regwen_13_we;
792 logic mio_pad_attr_regwen_13_qs;
793 logic mio_pad_attr_regwen_13_wd;
794 logic mio_pad_attr_regwen_14_we;
795 logic mio_pad_attr_regwen_14_qs;
796 logic mio_pad_attr_regwen_14_wd;
797 logic mio_pad_attr_regwen_15_we;
798 logic mio_pad_attr_regwen_15_qs;
799 logic mio_pad_attr_regwen_15_wd;
800 logic mio_pad_attr_regwen_16_we;
801 logic mio_pad_attr_regwen_16_qs;
802 logic mio_pad_attr_regwen_16_wd;
803 logic mio_pad_attr_regwen_17_we;
804 logic mio_pad_attr_regwen_17_qs;
805 logic mio_pad_attr_regwen_17_wd;
806 logic mio_pad_attr_regwen_18_we;
807 logic mio_pad_attr_regwen_18_qs;
808 logic mio_pad_attr_regwen_18_wd;
809 logic mio_pad_attr_regwen_19_we;
810 logic mio_pad_attr_regwen_19_qs;
811 logic mio_pad_attr_regwen_19_wd;
812 logic mio_pad_attr_regwen_20_we;
813 logic mio_pad_attr_regwen_20_qs;
814 logic mio_pad_attr_regwen_20_wd;
815 logic mio_pad_attr_regwen_21_we;
816 logic mio_pad_attr_regwen_21_qs;
817 logic mio_pad_attr_regwen_21_wd;
818 logic mio_pad_attr_regwen_22_we;
819 logic mio_pad_attr_regwen_22_qs;
820 logic mio_pad_attr_regwen_22_wd;
821 logic mio_pad_attr_regwen_23_we;
822 logic mio_pad_attr_regwen_23_qs;
823 logic mio_pad_attr_regwen_23_wd;
824 logic mio_pad_attr_regwen_24_we;
825 logic mio_pad_attr_regwen_24_qs;
826 logic mio_pad_attr_regwen_24_wd;
827 logic mio_pad_attr_regwen_25_we;
828 logic mio_pad_attr_regwen_25_qs;
829 logic mio_pad_attr_regwen_25_wd;
830 logic mio_pad_attr_regwen_26_we;
831 logic mio_pad_attr_regwen_26_qs;
832 logic mio_pad_attr_regwen_26_wd;
833 logic mio_pad_attr_regwen_27_we;
834 logic mio_pad_attr_regwen_27_qs;
835 logic mio_pad_attr_regwen_27_wd;
836 logic mio_pad_attr_regwen_28_we;
837 logic mio_pad_attr_regwen_28_qs;
838 logic mio_pad_attr_regwen_28_wd;
839 logic mio_pad_attr_regwen_29_we;
840 logic mio_pad_attr_regwen_29_qs;
841 logic mio_pad_attr_regwen_29_wd;
842 logic mio_pad_attr_regwen_30_we;
843 logic mio_pad_attr_regwen_30_qs;
844 logic mio_pad_attr_regwen_30_wd;
845 logic mio_pad_attr_regwen_31_we;
846 logic mio_pad_attr_regwen_31_qs;
847 logic mio_pad_attr_regwen_31_wd;
848 logic mio_pad_attr_regwen_32_we;
849 logic mio_pad_attr_regwen_32_qs;
850 logic mio_pad_attr_regwen_32_wd;
851 logic mio_pad_attr_regwen_33_we;
852 logic mio_pad_attr_regwen_33_qs;
853 logic mio_pad_attr_regwen_33_wd;
854 logic mio_pad_attr_regwen_34_we;
855 logic mio_pad_attr_regwen_34_qs;
856 logic mio_pad_attr_regwen_34_wd;
857 logic mio_pad_attr_regwen_35_we;
858 logic mio_pad_attr_regwen_35_qs;
859 logic mio_pad_attr_regwen_35_wd;
860 logic mio_pad_attr_regwen_36_we;
861 logic mio_pad_attr_regwen_36_qs;
862 logic mio_pad_attr_regwen_36_wd;
863 logic mio_pad_attr_regwen_37_we;
864 logic mio_pad_attr_regwen_37_qs;
865 logic mio_pad_attr_regwen_37_wd;
866 logic mio_pad_attr_regwen_38_we;
867 logic mio_pad_attr_regwen_38_qs;
868 logic mio_pad_attr_regwen_38_wd;
869 logic mio_pad_attr_regwen_39_we;
870 logic mio_pad_attr_regwen_39_qs;
871 logic mio_pad_attr_regwen_39_wd;
872 logic mio_pad_attr_regwen_40_we;
873 logic mio_pad_attr_regwen_40_qs;
874 logic mio_pad_attr_regwen_40_wd;
875 logic mio_pad_attr_regwen_41_we;
876 logic mio_pad_attr_regwen_41_qs;
877 logic mio_pad_attr_regwen_41_wd;
878 logic mio_pad_attr_regwen_42_we;
879 logic mio_pad_attr_regwen_42_qs;
880 logic mio_pad_attr_regwen_42_wd;
881 logic mio_pad_attr_regwen_43_we;
882 logic mio_pad_attr_regwen_43_qs;
883 logic mio_pad_attr_regwen_43_wd;
884 logic mio_pad_attr_regwen_44_we;
885 logic mio_pad_attr_regwen_44_qs;
886 logic mio_pad_attr_regwen_44_wd;
887 logic mio_pad_attr_regwen_45_we;
888 logic mio_pad_attr_regwen_45_qs;
889 logic mio_pad_attr_regwen_45_wd;
890 logic mio_pad_attr_regwen_46_we;
891 logic mio_pad_attr_regwen_46_qs;
892 logic mio_pad_attr_regwen_46_wd;
893 logic mio_pad_attr_0_re;
894 logic mio_pad_attr_0_we;
895 logic mio_pad_attr_0_invert_0_qs;
896 logic mio_pad_attr_0_invert_0_wd;
897 logic mio_pad_attr_0_virtual_od_en_0_qs;
898 logic mio_pad_attr_0_virtual_od_en_0_wd;
899 logic mio_pad_attr_0_pull_en_0_qs;
900 logic mio_pad_attr_0_pull_en_0_wd;
901 logic mio_pad_attr_0_pull_select_0_qs;
902 logic mio_pad_attr_0_pull_select_0_wd;
903 logic mio_pad_attr_0_keeper_en_0_qs;
904 logic mio_pad_attr_0_keeper_en_0_wd;
905 logic mio_pad_attr_0_schmitt_en_0_qs;
906 logic mio_pad_attr_0_schmitt_en_0_wd;
907 logic mio_pad_attr_0_od_en_0_qs;
908 logic mio_pad_attr_0_od_en_0_wd;
909 logic mio_pad_attr_0_input_disable_0_qs;
910 logic mio_pad_attr_0_input_disable_0_wd;
911 logic [1:0] mio_pad_attr_0_slew_rate_0_qs;
912 logic [1:0] mio_pad_attr_0_slew_rate_0_wd;
913 logic [3:0] mio_pad_attr_0_drive_strength_0_qs;
914 logic [3:0] mio_pad_attr_0_drive_strength_0_wd;
915 logic mio_pad_attr_1_re;
916 logic mio_pad_attr_1_we;
917 logic mio_pad_attr_1_invert_1_qs;
918 logic mio_pad_attr_1_invert_1_wd;
919 logic mio_pad_attr_1_virtual_od_en_1_qs;
920 logic mio_pad_attr_1_virtual_od_en_1_wd;
921 logic mio_pad_attr_1_pull_en_1_qs;
922 logic mio_pad_attr_1_pull_en_1_wd;
923 logic mio_pad_attr_1_pull_select_1_qs;
924 logic mio_pad_attr_1_pull_select_1_wd;
925 logic mio_pad_attr_1_keeper_en_1_qs;
926 logic mio_pad_attr_1_keeper_en_1_wd;
927 logic mio_pad_attr_1_schmitt_en_1_qs;
928 logic mio_pad_attr_1_schmitt_en_1_wd;
929 logic mio_pad_attr_1_od_en_1_qs;
930 logic mio_pad_attr_1_od_en_1_wd;
931 logic mio_pad_attr_1_input_disable_1_qs;
932 logic mio_pad_attr_1_input_disable_1_wd;
933 logic [1:0] mio_pad_attr_1_slew_rate_1_qs;
934 logic [1:0] mio_pad_attr_1_slew_rate_1_wd;
935 logic [3:0] mio_pad_attr_1_drive_strength_1_qs;
936 logic [3:0] mio_pad_attr_1_drive_strength_1_wd;
937 logic mio_pad_attr_2_re;
938 logic mio_pad_attr_2_we;
939 logic mio_pad_attr_2_invert_2_qs;
940 logic mio_pad_attr_2_invert_2_wd;
941 logic mio_pad_attr_2_virtual_od_en_2_qs;
942 logic mio_pad_attr_2_virtual_od_en_2_wd;
943 logic mio_pad_attr_2_pull_en_2_qs;
944 logic mio_pad_attr_2_pull_en_2_wd;
945 logic mio_pad_attr_2_pull_select_2_qs;
946 logic mio_pad_attr_2_pull_select_2_wd;
947 logic mio_pad_attr_2_keeper_en_2_qs;
948 logic mio_pad_attr_2_keeper_en_2_wd;
949 logic mio_pad_attr_2_schmitt_en_2_qs;
950 logic mio_pad_attr_2_schmitt_en_2_wd;
951 logic mio_pad_attr_2_od_en_2_qs;
952 logic mio_pad_attr_2_od_en_2_wd;
953 logic mio_pad_attr_2_input_disable_2_qs;
954 logic mio_pad_attr_2_input_disable_2_wd;
955 logic [1:0] mio_pad_attr_2_slew_rate_2_qs;
956 logic [1:0] mio_pad_attr_2_slew_rate_2_wd;
957 logic [3:0] mio_pad_attr_2_drive_strength_2_qs;
958 logic [3:0] mio_pad_attr_2_drive_strength_2_wd;
959 logic mio_pad_attr_3_re;
960 logic mio_pad_attr_3_we;
961 logic mio_pad_attr_3_invert_3_qs;
962 logic mio_pad_attr_3_invert_3_wd;
963 logic mio_pad_attr_3_virtual_od_en_3_qs;
964 logic mio_pad_attr_3_virtual_od_en_3_wd;
965 logic mio_pad_attr_3_pull_en_3_qs;
966 logic mio_pad_attr_3_pull_en_3_wd;
967 logic mio_pad_attr_3_pull_select_3_qs;
968 logic mio_pad_attr_3_pull_select_3_wd;
969 logic mio_pad_attr_3_keeper_en_3_qs;
970 logic mio_pad_attr_3_keeper_en_3_wd;
971 logic mio_pad_attr_3_schmitt_en_3_qs;
972 logic mio_pad_attr_3_schmitt_en_3_wd;
973 logic mio_pad_attr_3_od_en_3_qs;
974 logic mio_pad_attr_3_od_en_3_wd;
975 logic mio_pad_attr_3_input_disable_3_qs;
976 logic mio_pad_attr_3_input_disable_3_wd;
977 logic [1:0] mio_pad_attr_3_slew_rate_3_qs;
978 logic [1:0] mio_pad_attr_3_slew_rate_3_wd;
979 logic [3:0] mio_pad_attr_3_drive_strength_3_qs;
980 logic [3:0] mio_pad_attr_3_drive_strength_3_wd;
981 logic mio_pad_attr_4_re;
982 logic mio_pad_attr_4_we;
983 logic mio_pad_attr_4_invert_4_qs;
984 logic mio_pad_attr_4_invert_4_wd;
985 logic mio_pad_attr_4_virtual_od_en_4_qs;
986 logic mio_pad_attr_4_virtual_od_en_4_wd;
987 logic mio_pad_attr_4_pull_en_4_qs;
988 logic mio_pad_attr_4_pull_en_4_wd;
989 logic mio_pad_attr_4_pull_select_4_qs;
990 logic mio_pad_attr_4_pull_select_4_wd;
991 logic mio_pad_attr_4_keeper_en_4_qs;
992 logic mio_pad_attr_4_keeper_en_4_wd;
993 logic mio_pad_attr_4_schmitt_en_4_qs;
994 logic mio_pad_attr_4_schmitt_en_4_wd;
995 logic mio_pad_attr_4_od_en_4_qs;
996 logic mio_pad_attr_4_od_en_4_wd;
997 logic mio_pad_attr_4_input_disable_4_qs;
998 logic mio_pad_attr_4_input_disable_4_wd;
999 logic [1:0] mio_pad_attr_4_slew_rate_4_qs;
1000 logic [1:0] mio_pad_attr_4_slew_rate_4_wd;
1001 logic [3:0] mio_pad_attr_4_drive_strength_4_qs;
1002 logic [3:0] mio_pad_attr_4_drive_strength_4_wd;
1003 logic mio_pad_attr_5_re;
1004 logic mio_pad_attr_5_we;
1005 logic mio_pad_attr_5_invert_5_qs;
1006 logic mio_pad_attr_5_invert_5_wd;
1007 logic mio_pad_attr_5_virtual_od_en_5_qs;
1008 logic mio_pad_attr_5_virtual_od_en_5_wd;
1009 logic mio_pad_attr_5_pull_en_5_qs;
1010 logic mio_pad_attr_5_pull_en_5_wd;
1011 logic mio_pad_attr_5_pull_select_5_qs;
1012 logic mio_pad_attr_5_pull_select_5_wd;
1013 logic mio_pad_attr_5_keeper_en_5_qs;
1014 logic mio_pad_attr_5_keeper_en_5_wd;
1015 logic mio_pad_attr_5_schmitt_en_5_qs;
1016 logic mio_pad_attr_5_schmitt_en_5_wd;
1017 logic mio_pad_attr_5_od_en_5_qs;
1018 logic mio_pad_attr_5_od_en_5_wd;
1019 logic mio_pad_attr_5_input_disable_5_qs;
1020 logic mio_pad_attr_5_input_disable_5_wd;
1021 logic [1:0] mio_pad_attr_5_slew_rate_5_qs;
1022 logic [1:0] mio_pad_attr_5_slew_rate_5_wd;
1023 logic [3:0] mio_pad_attr_5_drive_strength_5_qs;
1024 logic [3:0] mio_pad_attr_5_drive_strength_5_wd;
1025 logic mio_pad_attr_6_re;
1026 logic mio_pad_attr_6_we;
1027 logic mio_pad_attr_6_invert_6_qs;
1028 logic mio_pad_attr_6_invert_6_wd;
1029 logic mio_pad_attr_6_virtual_od_en_6_qs;
1030 logic mio_pad_attr_6_virtual_od_en_6_wd;
1031 logic mio_pad_attr_6_pull_en_6_qs;
1032 logic mio_pad_attr_6_pull_en_6_wd;
1033 logic mio_pad_attr_6_pull_select_6_qs;
1034 logic mio_pad_attr_6_pull_select_6_wd;
1035 logic mio_pad_attr_6_keeper_en_6_qs;
1036 logic mio_pad_attr_6_keeper_en_6_wd;
1037 logic mio_pad_attr_6_schmitt_en_6_qs;
1038 logic mio_pad_attr_6_schmitt_en_6_wd;
1039 logic mio_pad_attr_6_od_en_6_qs;
1040 logic mio_pad_attr_6_od_en_6_wd;
1041 logic mio_pad_attr_6_input_disable_6_qs;
1042 logic mio_pad_attr_6_input_disable_6_wd;
1043 logic [1:0] mio_pad_attr_6_slew_rate_6_qs;
1044 logic [1:0] mio_pad_attr_6_slew_rate_6_wd;
1045 logic [3:0] mio_pad_attr_6_drive_strength_6_qs;
1046 logic [3:0] mio_pad_attr_6_drive_strength_6_wd;
1047 logic mio_pad_attr_7_re;
1048 logic mio_pad_attr_7_we;
1049 logic mio_pad_attr_7_invert_7_qs;
1050 logic mio_pad_attr_7_invert_7_wd;
1051 logic mio_pad_attr_7_virtual_od_en_7_qs;
1052 logic mio_pad_attr_7_virtual_od_en_7_wd;
1053 logic mio_pad_attr_7_pull_en_7_qs;
1054 logic mio_pad_attr_7_pull_en_7_wd;
1055 logic mio_pad_attr_7_pull_select_7_qs;
1056 logic mio_pad_attr_7_pull_select_7_wd;
1057 logic mio_pad_attr_7_keeper_en_7_qs;
1058 logic mio_pad_attr_7_keeper_en_7_wd;
1059 logic mio_pad_attr_7_schmitt_en_7_qs;
1060 logic mio_pad_attr_7_schmitt_en_7_wd;
1061 logic mio_pad_attr_7_od_en_7_qs;
1062 logic mio_pad_attr_7_od_en_7_wd;
1063 logic mio_pad_attr_7_input_disable_7_qs;
1064 logic mio_pad_attr_7_input_disable_7_wd;
1065 logic [1:0] mio_pad_attr_7_slew_rate_7_qs;
1066 logic [1:0] mio_pad_attr_7_slew_rate_7_wd;
1067 logic [3:0] mio_pad_attr_7_drive_strength_7_qs;
1068 logic [3:0] mio_pad_attr_7_drive_strength_7_wd;
1069 logic mio_pad_attr_8_re;
1070 logic mio_pad_attr_8_we;
1071 logic mio_pad_attr_8_invert_8_qs;
1072 logic mio_pad_attr_8_invert_8_wd;
1073 logic mio_pad_attr_8_virtual_od_en_8_qs;
1074 logic mio_pad_attr_8_virtual_od_en_8_wd;
1075 logic mio_pad_attr_8_pull_en_8_qs;
1076 logic mio_pad_attr_8_pull_en_8_wd;
1077 logic mio_pad_attr_8_pull_select_8_qs;
1078 logic mio_pad_attr_8_pull_select_8_wd;
1079 logic mio_pad_attr_8_keeper_en_8_qs;
1080 logic mio_pad_attr_8_keeper_en_8_wd;
1081 logic mio_pad_attr_8_schmitt_en_8_qs;
1082 logic mio_pad_attr_8_schmitt_en_8_wd;
1083 logic mio_pad_attr_8_od_en_8_qs;
1084 logic mio_pad_attr_8_od_en_8_wd;
1085 logic mio_pad_attr_8_input_disable_8_qs;
1086 logic mio_pad_attr_8_input_disable_8_wd;
1087 logic [1:0] mio_pad_attr_8_slew_rate_8_qs;
1088 logic [1:0] mio_pad_attr_8_slew_rate_8_wd;
1089 logic [3:0] mio_pad_attr_8_drive_strength_8_qs;
1090 logic [3:0] mio_pad_attr_8_drive_strength_8_wd;
1091 logic mio_pad_attr_9_re;
1092 logic mio_pad_attr_9_we;
1093 logic mio_pad_attr_9_invert_9_qs;
1094 logic mio_pad_attr_9_invert_9_wd;
1095 logic mio_pad_attr_9_virtual_od_en_9_qs;
1096 logic mio_pad_attr_9_virtual_od_en_9_wd;
1097 logic mio_pad_attr_9_pull_en_9_qs;
1098 logic mio_pad_attr_9_pull_en_9_wd;
1099 logic mio_pad_attr_9_pull_select_9_qs;
1100 logic mio_pad_attr_9_pull_select_9_wd;
1101 logic mio_pad_attr_9_keeper_en_9_qs;
1102 logic mio_pad_attr_9_keeper_en_9_wd;
1103 logic mio_pad_attr_9_schmitt_en_9_qs;
1104 logic mio_pad_attr_9_schmitt_en_9_wd;
1105 logic mio_pad_attr_9_od_en_9_qs;
1106 logic mio_pad_attr_9_od_en_9_wd;
1107 logic mio_pad_attr_9_input_disable_9_qs;
1108 logic mio_pad_attr_9_input_disable_9_wd;
1109 logic [1:0] mio_pad_attr_9_slew_rate_9_qs;
1110 logic [1:0] mio_pad_attr_9_slew_rate_9_wd;
1111 logic [3:0] mio_pad_attr_9_drive_strength_9_qs;
1112 logic [3:0] mio_pad_attr_9_drive_strength_9_wd;
1113 logic mio_pad_attr_10_re;
1114 logic mio_pad_attr_10_we;
1115 logic mio_pad_attr_10_invert_10_qs;
1116 logic mio_pad_attr_10_invert_10_wd;
1117 logic mio_pad_attr_10_virtual_od_en_10_qs;
1118 logic mio_pad_attr_10_virtual_od_en_10_wd;
1119 logic mio_pad_attr_10_pull_en_10_qs;
1120 logic mio_pad_attr_10_pull_en_10_wd;
1121 logic mio_pad_attr_10_pull_select_10_qs;
1122 logic mio_pad_attr_10_pull_select_10_wd;
1123 logic mio_pad_attr_10_keeper_en_10_qs;
1124 logic mio_pad_attr_10_keeper_en_10_wd;
1125 logic mio_pad_attr_10_schmitt_en_10_qs;
1126 logic mio_pad_attr_10_schmitt_en_10_wd;
1127 logic mio_pad_attr_10_od_en_10_qs;
1128 logic mio_pad_attr_10_od_en_10_wd;
1129 logic mio_pad_attr_10_input_disable_10_qs;
1130 logic mio_pad_attr_10_input_disable_10_wd;
1131 logic [1:0] mio_pad_attr_10_slew_rate_10_qs;
1132 logic [1:0] mio_pad_attr_10_slew_rate_10_wd;
1133 logic [3:0] mio_pad_attr_10_drive_strength_10_qs;
1134 logic [3:0] mio_pad_attr_10_drive_strength_10_wd;
1135 logic mio_pad_attr_11_re;
1136 logic mio_pad_attr_11_we;
1137 logic mio_pad_attr_11_invert_11_qs;
1138 logic mio_pad_attr_11_invert_11_wd;
1139 logic mio_pad_attr_11_virtual_od_en_11_qs;
1140 logic mio_pad_attr_11_virtual_od_en_11_wd;
1141 logic mio_pad_attr_11_pull_en_11_qs;
1142 logic mio_pad_attr_11_pull_en_11_wd;
1143 logic mio_pad_attr_11_pull_select_11_qs;
1144 logic mio_pad_attr_11_pull_select_11_wd;
1145 logic mio_pad_attr_11_keeper_en_11_qs;
1146 logic mio_pad_attr_11_keeper_en_11_wd;
1147 logic mio_pad_attr_11_schmitt_en_11_qs;
1148 logic mio_pad_attr_11_schmitt_en_11_wd;
1149 logic mio_pad_attr_11_od_en_11_qs;
1150 logic mio_pad_attr_11_od_en_11_wd;
1151 logic mio_pad_attr_11_input_disable_11_qs;
1152 logic mio_pad_attr_11_input_disable_11_wd;
1153 logic [1:0] mio_pad_attr_11_slew_rate_11_qs;
1154 logic [1:0] mio_pad_attr_11_slew_rate_11_wd;
1155 logic [3:0] mio_pad_attr_11_drive_strength_11_qs;
1156 logic [3:0] mio_pad_attr_11_drive_strength_11_wd;
1157 logic mio_pad_attr_12_re;
1158 logic mio_pad_attr_12_we;
1159 logic mio_pad_attr_12_invert_12_qs;
1160 logic mio_pad_attr_12_invert_12_wd;
1161 logic mio_pad_attr_12_virtual_od_en_12_qs;
1162 logic mio_pad_attr_12_virtual_od_en_12_wd;
1163 logic mio_pad_attr_12_pull_en_12_qs;
1164 logic mio_pad_attr_12_pull_en_12_wd;
1165 logic mio_pad_attr_12_pull_select_12_qs;
1166 logic mio_pad_attr_12_pull_select_12_wd;
1167 logic mio_pad_attr_12_keeper_en_12_qs;
1168 logic mio_pad_attr_12_keeper_en_12_wd;
1169 logic mio_pad_attr_12_schmitt_en_12_qs;
1170 logic mio_pad_attr_12_schmitt_en_12_wd;
1171 logic mio_pad_attr_12_od_en_12_qs;
1172 logic mio_pad_attr_12_od_en_12_wd;
1173 logic mio_pad_attr_12_input_disable_12_qs;
1174 logic mio_pad_attr_12_input_disable_12_wd;
1175 logic [1:0] mio_pad_attr_12_slew_rate_12_qs;
1176 logic [1:0] mio_pad_attr_12_slew_rate_12_wd;
1177 logic [3:0] mio_pad_attr_12_drive_strength_12_qs;
1178 logic [3:0] mio_pad_attr_12_drive_strength_12_wd;
1179 logic mio_pad_attr_13_re;
1180 logic mio_pad_attr_13_we;
1181 logic mio_pad_attr_13_invert_13_qs;
1182 logic mio_pad_attr_13_invert_13_wd;
1183 logic mio_pad_attr_13_virtual_od_en_13_qs;
1184 logic mio_pad_attr_13_virtual_od_en_13_wd;
1185 logic mio_pad_attr_13_pull_en_13_qs;
1186 logic mio_pad_attr_13_pull_en_13_wd;
1187 logic mio_pad_attr_13_pull_select_13_qs;
1188 logic mio_pad_attr_13_pull_select_13_wd;
1189 logic mio_pad_attr_13_keeper_en_13_qs;
1190 logic mio_pad_attr_13_keeper_en_13_wd;
1191 logic mio_pad_attr_13_schmitt_en_13_qs;
1192 logic mio_pad_attr_13_schmitt_en_13_wd;
1193 logic mio_pad_attr_13_od_en_13_qs;
1194 logic mio_pad_attr_13_od_en_13_wd;
1195 logic mio_pad_attr_13_input_disable_13_qs;
1196 logic mio_pad_attr_13_input_disable_13_wd;
1197 logic [1:0] mio_pad_attr_13_slew_rate_13_qs;
1198 logic [1:0] mio_pad_attr_13_slew_rate_13_wd;
1199 logic [3:0] mio_pad_attr_13_drive_strength_13_qs;
1200 logic [3:0] mio_pad_attr_13_drive_strength_13_wd;
1201 logic mio_pad_attr_14_re;
1202 logic mio_pad_attr_14_we;
1203 logic mio_pad_attr_14_invert_14_qs;
1204 logic mio_pad_attr_14_invert_14_wd;
1205 logic mio_pad_attr_14_virtual_od_en_14_qs;
1206 logic mio_pad_attr_14_virtual_od_en_14_wd;
1207 logic mio_pad_attr_14_pull_en_14_qs;
1208 logic mio_pad_attr_14_pull_en_14_wd;
1209 logic mio_pad_attr_14_pull_select_14_qs;
1210 logic mio_pad_attr_14_pull_select_14_wd;
1211 logic mio_pad_attr_14_keeper_en_14_qs;
1212 logic mio_pad_attr_14_keeper_en_14_wd;
1213 logic mio_pad_attr_14_schmitt_en_14_qs;
1214 logic mio_pad_attr_14_schmitt_en_14_wd;
1215 logic mio_pad_attr_14_od_en_14_qs;
1216 logic mio_pad_attr_14_od_en_14_wd;
1217 logic mio_pad_attr_14_input_disable_14_qs;
1218 logic mio_pad_attr_14_input_disable_14_wd;
1219 logic [1:0] mio_pad_attr_14_slew_rate_14_qs;
1220 logic [1:0] mio_pad_attr_14_slew_rate_14_wd;
1221 logic [3:0] mio_pad_attr_14_drive_strength_14_qs;
1222 logic [3:0] mio_pad_attr_14_drive_strength_14_wd;
1223 logic mio_pad_attr_15_re;
1224 logic mio_pad_attr_15_we;
1225 logic mio_pad_attr_15_invert_15_qs;
1226 logic mio_pad_attr_15_invert_15_wd;
1227 logic mio_pad_attr_15_virtual_od_en_15_qs;
1228 logic mio_pad_attr_15_virtual_od_en_15_wd;
1229 logic mio_pad_attr_15_pull_en_15_qs;
1230 logic mio_pad_attr_15_pull_en_15_wd;
1231 logic mio_pad_attr_15_pull_select_15_qs;
1232 logic mio_pad_attr_15_pull_select_15_wd;
1233 logic mio_pad_attr_15_keeper_en_15_qs;
1234 logic mio_pad_attr_15_keeper_en_15_wd;
1235 logic mio_pad_attr_15_schmitt_en_15_qs;
1236 logic mio_pad_attr_15_schmitt_en_15_wd;
1237 logic mio_pad_attr_15_od_en_15_qs;
1238 logic mio_pad_attr_15_od_en_15_wd;
1239 logic mio_pad_attr_15_input_disable_15_qs;
1240 logic mio_pad_attr_15_input_disable_15_wd;
1241 logic [1:0] mio_pad_attr_15_slew_rate_15_qs;
1242 logic [1:0] mio_pad_attr_15_slew_rate_15_wd;
1243 logic [3:0] mio_pad_attr_15_drive_strength_15_qs;
1244 logic [3:0] mio_pad_attr_15_drive_strength_15_wd;
1245 logic mio_pad_attr_16_re;
1246 logic mio_pad_attr_16_we;
1247 logic mio_pad_attr_16_invert_16_qs;
1248 logic mio_pad_attr_16_invert_16_wd;
1249 logic mio_pad_attr_16_virtual_od_en_16_qs;
1250 logic mio_pad_attr_16_virtual_od_en_16_wd;
1251 logic mio_pad_attr_16_pull_en_16_qs;
1252 logic mio_pad_attr_16_pull_en_16_wd;
1253 logic mio_pad_attr_16_pull_select_16_qs;
1254 logic mio_pad_attr_16_pull_select_16_wd;
1255 logic mio_pad_attr_16_keeper_en_16_qs;
1256 logic mio_pad_attr_16_keeper_en_16_wd;
1257 logic mio_pad_attr_16_schmitt_en_16_qs;
1258 logic mio_pad_attr_16_schmitt_en_16_wd;
1259 logic mio_pad_attr_16_od_en_16_qs;
1260 logic mio_pad_attr_16_od_en_16_wd;
1261 logic mio_pad_attr_16_input_disable_16_qs;
1262 logic mio_pad_attr_16_input_disable_16_wd;
1263 logic [1:0] mio_pad_attr_16_slew_rate_16_qs;
1264 logic [1:0] mio_pad_attr_16_slew_rate_16_wd;
1265 logic [3:0] mio_pad_attr_16_drive_strength_16_qs;
1266 logic [3:0] mio_pad_attr_16_drive_strength_16_wd;
1267 logic mio_pad_attr_17_re;
1268 logic mio_pad_attr_17_we;
1269 logic mio_pad_attr_17_invert_17_qs;
1270 logic mio_pad_attr_17_invert_17_wd;
1271 logic mio_pad_attr_17_virtual_od_en_17_qs;
1272 logic mio_pad_attr_17_virtual_od_en_17_wd;
1273 logic mio_pad_attr_17_pull_en_17_qs;
1274 logic mio_pad_attr_17_pull_en_17_wd;
1275 logic mio_pad_attr_17_pull_select_17_qs;
1276 logic mio_pad_attr_17_pull_select_17_wd;
1277 logic mio_pad_attr_17_keeper_en_17_qs;
1278 logic mio_pad_attr_17_keeper_en_17_wd;
1279 logic mio_pad_attr_17_schmitt_en_17_qs;
1280 logic mio_pad_attr_17_schmitt_en_17_wd;
1281 logic mio_pad_attr_17_od_en_17_qs;
1282 logic mio_pad_attr_17_od_en_17_wd;
1283 logic mio_pad_attr_17_input_disable_17_qs;
1284 logic mio_pad_attr_17_input_disable_17_wd;
1285 logic [1:0] mio_pad_attr_17_slew_rate_17_qs;
1286 logic [1:0] mio_pad_attr_17_slew_rate_17_wd;
1287 logic [3:0] mio_pad_attr_17_drive_strength_17_qs;
1288 logic [3:0] mio_pad_attr_17_drive_strength_17_wd;
1289 logic mio_pad_attr_18_re;
1290 logic mio_pad_attr_18_we;
1291 logic mio_pad_attr_18_invert_18_qs;
1292 logic mio_pad_attr_18_invert_18_wd;
1293 logic mio_pad_attr_18_virtual_od_en_18_qs;
1294 logic mio_pad_attr_18_virtual_od_en_18_wd;
1295 logic mio_pad_attr_18_pull_en_18_qs;
1296 logic mio_pad_attr_18_pull_en_18_wd;
1297 logic mio_pad_attr_18_pull_select_18_qs;
1298 logic mio_pad_attr_18_pull_select_18_wd;
1299 logic mio_pad_attr_18_keeper_en_18_qs;
1300 logic mio_pad_attr_18_keeper_en_18_wd;
1301 logic mio_pad_attr_18_schmitt_en_18_qs;
1302 logic mio_pad_attr_18_schmitt_en_18_wd;
1303 logic mio_pad_attr_18_od_en_18_qs;
1304 logic mio_pad_attr_18_od_en_18_wd;
1305 logic mio_pad_attr_18_input_disable_18_qs;
1306 logic mio_pad_attr_18_input_disable_18_wd;
1307 logic [1:0] mio_pad_attr_18_slew_rate_18_qs;
1308 logic [1:0] mio_pad_attr_18_slew_rate_18_wd;
1309 logic [3:0] mio_pad_attr_18_drive_strength_18_qs;
1310 logic [3:0] mio_pad_attr_18_drive_strength_18_wd;
1311 logic mio_pad_attr_19_re;
1312 logic mio_pad_attr_19_we;
1313 logic mio_pad_attr_19_invert_19_qs;
1314 logic mio_pad_attr_19_invert_19_wd;
1315 logic mio_pad_attr_19_virtual_od_en_19_qs;
1316 logic mio_pad_attr_19_virtual_od_en_19_wd;
1317 logic mio_pad_attr_19_pull_en_19_qs;
1318 logic mio_pad_attr_19_pull_en_19_wd;
1319 logic mio_pad_attr_19_pull_select_19_qs;
1320 logic mio_pad_attr_19_pull_select_19_wd;
1321 logic mio_pad_attr_19_keeper_en_19_qs;
1322 logic mio_pad_attr_19_keeper_en_19_wd;
1323 logic mio_pad_attr_19_schmitt_en_19_qs;
1324 logic mio_pad_attr_19_schmitt_en_19_wd;
1325 logic mio_pad_attr_19_od_en_19_qs;
1326 logic mio_pad_attr_19_od_en_19_wd;
1327 logic mio_pad_attr_19_input_disable_19_qs;
1328 logic mio_pad_attr_19_input_disable_19_wd;
1329 logic [1:0] mio_pad_attr_19_slew_rate_19_qs;
1330 logic [1:0] mio_pad_attr_19_slew_rate_19_wd;
1331 logic [3:0] mio_pad_attr_19_drive_strength_19_qs;
1332 logic [3:0] mio_pad_attr_19_drive_strength_19_wd;
1333 logic mio_pad_attr_20_re;
1334 logic mio_pad_attr_20_we;
1335 logic mio_pad_attr_20_invert_20_qs;
1336 logic mio_pad_attr_20_invert_20_wd;
1337 logic mio_pad_attr_20_virtual_od_en_20_qs;
1338 logic mio_pad_attr_20_virtual_od_en_20_wd;
1339 logic mio_pad_attr_20_pull_en_20_qs;
1340 logic mio_pad_attr_20_pull_en_20_wd;
1341 logic mio_pad_attr_20_pull_select_20_qs;
1342 logic mio_pad_attr_20_pull_select_20_wd;
1343 logic mio_pad_attr_20_keeper_en_20_qs;
1344 logic mio_pad_attr_20_keeper_en_20_wd;
1345 logic mio_pad_attr_20_schmitt_en_20_qs;
1346 logic mio_pad_attr_20_schmitt_en_20_wd;
1347 logic mio_pad_attr_20_od_en_20_qs;
1348 logic mio_pad_attr_20_od_en_20_wd;
1349 logic mio_pad_attr_20_input_disable_20_qs;
1350 logic mio_pad_attr_20_input_disable_20_wd;
1351 logic [1:0] mio_pad_attr_20_slew_rate_20_qs;
1352 logic [1:0] mio_pad_attr_20_slew_rate_20_wd;
1353 logic [3:0] mio_pad_attr_20_drive_strength_20_qs;
1354 logic [3:0] mio_pad_attr_20_drive_strength_20_wd;
1355 logic mio_pad_attr_21_re;
1356 logic mio_pad_attr_21_we;
1357 logic mio_pad_attr_21_invert_21_qs;
1358 logic mio_pad_attr_21_invert_21_wd;
1359 logic mio_pad_attr_21_virtual_od_en_21_qs;
1360 logic mio_pad_attr_21_virtual_od_en_21_wd;
1361 logic mio_pad_attr_21_pull_en_21_qs;
1362 logic mio_pad_attr_21_pull_en_21_wd;
1363 logic mio_pad_attr_21_pull_select_21_qs;
1364 logic mio_pad_attr_21_pull_select_21_wd;
1365 logic mio_pad_attr_21_keeper_en_21_qs;
1366 logic mio_pad_attr_21_keeper_en_21_wd;
1367 logic mio_pad_attr_21_schmitt_en_21_qs;
1368 logic mio_pad_attr_21_schmitt_en_21_wd;
1369 logic mio_pad_attr_21_od_en_21_qs;
1370 logic mio_pad_attr_21_od_en_21_wd;
1371 logic mio_pad_attr_21_input_disable_21_qs;
1372 logic mio_pad_attr_21_input_disable_21_wd;
1373 logic [1:0] mio_pad_attr_21_slew_rate_21_qs;
1374 logic [1:0] mio_pad_attr_21_slew_rate_21_wd;
1375 logic [3:0] mio_pad_attr_21_drive_strength_21_qs;
1376 logic [3:0] mio_pad_attr_21_drive_strength_21_wd;
1377 logic mio_pad_attr_22_re;
1378 logic mio_pad_attr_22_we;
1379 logic mio_pad_attr_22_invert_22_qs;
1380 logic mio_pad_attr_22_invert_22_wd;
1381 logic mio_pad_attr_22_virtual_od_en_22_qs;
1382 logic mio_pad_attr_22_virtual_od_en_22_wd;
1383 logic mio_pad_attr_22_pull_en_22_qs;
1384 logic mio_pad_attr_22_pull_en_22_wd;
1385 logic mio_pad_attr_22_pull_select_22_qs;
1386 logic mio_pad_attr_22_pull_select_22_wd;
1387 logic mio_pad_attr_22_keeper_en_22_qs;
1388 logic mio_pad_attr_22_keeper_en_22_wd;
1389 logic mio_pad_attr_22_schmitt_en_22_qs;
1390 logic mio_pad_attr_22_schmitt_en_22_wd;
1391 logic mio_pad_attr_22_od_en_22_qs;
1392 logic mio_pad_attr_22_od_en_22_wd;
1393 logic mio_pad_attr_22_input_disable_22_qs;
1394 logic mio_pad_attr_22_input_disable_22_wd;
1395 logic [1:0] mio_pad_attr_22_slew_rate_22_qs;
1396 logic [1:0] mio_pad_attr_22_slew_rate_22_wd;
1397 logic [3:0] mio_pad_attr_22_drive_strength_22_qs;
1398 logic [3:0] mio_pad_attr_22_drive_strength_22_wd;
1399 logic mio_pad_attr_23_re;
1400 logic mio_pad_attr_23_we;
1401 logic mio_pad_attr_23_invert_23_qs;
1402 logic mio_pad_attr_23_invert_23_wd;
1403 logic mio_pad_attr_23_virtual_od_en_23_qs;
1404 logic mio_pad_attr_23_virtual_od_en_23_wd;
1405 logic mio_pad_attr_23_pull_en_23_qs;
1406 logic mio_pad_attr_23_pull_en_23_wd;
1407 logic mio_pad_attr_23_pull_select_23_qs;
1408 logic mio_pad_attr_23_pull_select_23_wd;
1409 logic mio_pad_attr_23_keeper_en_23_qs;
1410 logic mio_pad_attr_23_keeper_en_23_wd;
1411 logic mio_pad_attr_23_schmitt_en_23_qs;
1412 logic mio_pad_attr_23_schmitt_en_23_wd;
1413 logic mio_pad_attr_23_od_en_23_qs;
1414 logic mio_pad_attr_23_od_en_23_wd;
1415 logic mio_pad_attr_23_input_disable_23_qs;
1416 logic mio_pad_attr_23_input_disable_23_wd;
1417 logic [1:0] mio_pad_attr_23_slew_rate_23_qs;
1418 logic [1:0] mio_pad_attr_23_slew_rate_23_wd;
1419 logic [3:0] mio_pad_attr_23_drive_strength_23_qs;
1420 logic [3:0] mio_pad_attr_23_drive_strength_23_wd;
1421 logic mio_pad_attr_24_re;
1422 logic mio_pad_attr_24_we;
1423 logic mio_pad_attr_24_invert_24_qs;
1424 logic mio_pad_attr_24_invert_24_wd;
1425 logic mio_pad_attr_24_virtual_od_en_24_qs;
1426 logic mio_pad_attr_24_virtual_od_en_24_wd;
1427 logic mio_pad_attr_24_pull_en_24_qs;
1428 logic mio_pad_attr_24_pull_en_24_wd;
1429 logic mio_pad_attr_24_pull_select_24_qs;
1430 logic mio_pad_attr_24_pull_select_24_wd;
1431 logic mio_pad_attr_24_keeper_en_24_qs;
1432 logic mio_pad_attr_24_keeper_en_24_wd;
1433 logic mio_pad_attr_24_schmitt_en_24_qs;
1434 logic mio_pad_attr_24_schmitt_en_24_wd;
1435 logic mio_pad_attr_24_od_en_24_qs;
1436 logic mio_pad_attr_24_od_en_24_wd;
1437 logic mio_pad_attr_24_input_disable_24_qs;
1438 logic mio_pad_attr_24_input_disable_24_wd;
1439 logic [1:0] mio_pad_attr_24_slew_rate_24_qs;
1440 logic [1:0] mio_pad_attr_24_slew_rate_24_wd;
1441 logic [3:0] mio_pad_attr_24_drive_strength_24_qs;
1442 logic [3:0] mio_pad_attr_24_drive_strength_24_wd;
1443 logic mio_pad_attr_25_re;
1444 logic mio_pad_attr_25_we;
1445 logic mio_pad_attr_25_invert_25_qs;
1446 logic mio_pad_attr_25_invert_25_wd;
1447 logic mio_pad_attr_25_virtual_od_en_25_qs;
1448 logic mio_pad_attr_25_virtual_od_en_25_wd;
1449 logic mio_pad_attr_25_pull_en_25_qs;
1450 logic mio_pad_attr_25_pull_en_25_wd;
1451 logic mio_pad_attr_25_pull_select_25_qs;
1452 logic mio_pad_attr_25_pull_select_25_wd;
1453 logic mio_pad_attr_25_keeper_en_25_qs;
1454 logic mio_pad_attr_25_keeper_en_25_wd;
1455 logic mio_pad_attr_25_schmitt_en_25_qs;
1456 logic mio_pad_attr_25_schmitt_en_25_wd;
1457 logic mio_pad_attr_25_od_en_25_qs;
1458 logic mio_pad_attr_25_od_en_25_wd;
1459 logic mio_pad_attr_25_input_disable_25_qs;
1460 logic mio_pad_attr_25_input_disable_25_wd;
1461 logic [1:0] mio_pad_attr_25_slew_rate_25_qs;
1462 logic [1:0] mio_pad_attr_25_slew_rate_25_wd;
1463 logic [3:0] mio_pad_attr_25_drive_strength_25_qs;
1464 logic [3:0] mio_pad_attr_25_drive_strength_25_wd;
1465 logic mio_pad_attr_26_re;
1466 logic mio_pad_attr_26_we;
1467 logic mio_pad_attr_26_invert_26_qs;
1468 logic mio_pad_attr_26_invert_26_wd;
1469 logic mio_pad_attr_26_virtual_od_en_26_qs;
1470 logic mio_pad_attr_26_virtual_od_en_26_wd;
1471 logic mio_pad_attr_26_pull_en_26_qs;
1472 logic mio_pad_attr_26_pull_en_26_wd;
1473 logic mio_pad_attr_26_pull_select_26_qs;
1474 logic mio_pad_attr_26_pull_select_26_wd;
1475 logic mio_pad_attr_26_keeper_en_26_qs;
1476 logic mio_pad_attr_26_keeper_en_26_wd;
1477 logic mio_pad_attr_26_schmitt_en_26_qs;
1478 logic mio_pad_attr_26_schmitt_en_26_wd;
1479 logic mio_pad_attr_26_od_en_26_qs;
1480 logic mio_pad_attr_26_od_en_26_wd;
1481 logic mio_pad_attr_26_input_disable_26_qs;
1482 logic mio_pad_attr_26_input_disable_26_wd;
1483 logic [1:0] mio_pad_attr_26_slew_rate_26_qs;
1484 logic [1:0] mio_pad_attr_26_slew_rate_26_wd;
1485 logic [3:0] mio_pad_attr_26_drive_strength_26_qs;
1486 logic [3:0] mio_pad_attr_26_drive_strength_26_wd;
1487 logic mio_pad_attr_27_re;
1488 logic mio_pad_attr_27_we;
1489 logic mio_pad_attr_27_invert_27_qs;
1490 logic mio_pad_attr_27_invert_27_wd;
1491 logic mio_pad_attr_27_virtual_od_en_27_qs;
1492 logic mio_pad_attr_27_virtual_od_en_27_wd;
1493 logic mio_pad_attr_27_pull_en_27_qs;
1494 logic mio_pad_attr_27_pull_en_27_wd;
1495 logic mio_pad_attr_27_pull_select_27_qs;
1496 logic mio_pad_attr_27_pull_select_27_wd;
1497 logic mio_pad_attr_27_keeper_en_27_qs;
1498 logic mio_pad_attr_27_keeper_en_27_wd;
1499 logic mio_pad_attr_27_schmitt_en_27_qs;
1500 logic mio_pad_attr_27_schmitt_en_27_wd;
1501 logic mio_pad_attr_27_od_en_27_qs;
1502 logic mio_pad_attr_27_od_en_27_wd;
1503 logic mio_pad_attr_27_input_disable_27_qs;
1504 logic mio_pad_attr_27_input_disable_27_wd;
1505 logic [1:0] mio_pad_attr_27_slew_rate_27_qs;
1506 logic [1:0] mio_pad_attr_27_slew_rate_27_wd;
1507 logic [3:0] mio_pad_attr_27_drive_strength_27_qs;
1508 logic [3:0] mio_pad_attr_27_drive_strength_27_wd;
1509 logic mio_pad_attr_28_re;
1510 logic mio_pad_attr_28_we;
1511 logic mio_pad_attr_28_invert_28_qs;
1512 logic mio_pad_attr_28_invert_28_wd;
1513 logic mio_pad_attr_28_virtual_od_en_28_qs;
1514 logic mio_pad_attr_28_virtual_od_en_28_wd;
1515 logic mio_pad_attr_28_pull_en_28_qs;
1516 logic mio_pad_attr_28_pull_en_28_wd;
1517 logic mio_pad_attr_28_pull_select_28_qs;
1518 logic mio_pad_attr_28_pull_select_28_wd;
1519 logic mio_pad_attr_28_keeper_en_28_qs;
1520 logic mio_pad_attr_28_keeper_en_28_wd;
1521 logic mio_pad_attr_28_schmitt_en_28_qs;
1522 logic mio_pad_attr_28_schmitt_en_28_wd;
1523 logic mio_pad_attr_28_od_en_28_qs;
1524 logic mio_pad_attr_28_od_en_28_wd;
1525 logic mio_pad_attr_28_input_disable_28_qs;
1526 logic mio_pad_attr_28_input_disable_28_wd;
1527 logic [1:0] mio_pad_attr_28_slew_rate_28_qs;
1528 logic [1:0] mio_pad_attr_28_slew_rate_28_wd;
1529 logic [3:0] mio_pad_attr_28_drive_strength_28_qs;
1530 logic [3:0] mio_pad_attr_28_drive_strength_28_wd;
1531 logic mio_pad_attr_29_re;
1532 logic mio_pad_attr_29_we;
1533 logic mio_pad_attr_29_invert_29_qs;
1534 logic mio_pad_attr_29_invert_29_wd;
1535 logic mio_pad_attr_29_virtual_od_en_29_qs;
1536 logic mio_pad_attr_29_virtual_od_en_29_wd;
1537 logic mio_pad_attr_29_pull_en_29_qs;
1538 logic mio_pad_attr_29_pull_en_29_wd;
1539 logic mio_pad_attr_29_pull_select_29_qs;
1540 logic mio_pad_attr_29_pull_select_29_wd;
1541 logic mio_pad_attr_29_keeper_en_29_qs;
1542 logic mio_pad_attr_29_keeper_en_29_wd;
1543 logic mio_pad_attr_29_schmitt_en_29_qs;
1544 logic mio_pad_attr_29_schmitt_en_29_wd;
1545 logic mio_pad_attr_29_od_en_29_qs;
1546 logic mio_pad_attr_29_od_en_29_wd;
1547 logic mio_pad_attr_29_input_disable_29_qs;
1548 logic mio_pad_attr_29_input_disable_29_wd;
1549 logic [1:0] mio_pad_attr_29_slew_rate_29_qs;
1550 logic [1:0] mio_pad_attr_29_slew_rate_29_wd;
1551 logic [3:0] mio_pad_attr_29_drive_strength_29_qs;
1552 logic [3:0] mio_pad_attr_29_drive_strength_29_wd;
1553 logic mio_pad_attr_30_re;
1554 logic mio_pad_attr_30_we;
1555 logic mio_pad_attr_30_invert_30_qs;
1556 logic mio_pad_attr_30_invert_30_wd;
1557 logic mio_pad_attr_30_virtual_od_en_30_qs;
1558 logic mio_pad_attr_30_virtual_od_en_30_wd;
1559 logic mio_pad_attr_30_pull_en_30_qs;
1560 logic mio_pad_attr_30_pull_en_30_wd;
1561 logic mio_pad_attr_30_pull_select_30_qs;
1562 logic mio_pad_attr_30_pull_select_30_wd;
1563 logic mio_pad_attr_30_keeper_en_30_qs;
1564 logic mio_pad_attr_30_keeper_en_30_wd;
1565 logic mio_pad_attr_30_schmitt_en_30_qs;
1566 logic mio_pad_attr_30_schmitt_en_30_wd;
1567 logic mio_pad_attr_30_od_en_30_qs;
1568 logic mio_pad_attr_30_od_en_30_wd;
1569 logic mio_pad_attr_30_input_disable_30_qs;
1570 logic mio_pad_attr_30_input_disable_30_wd;
1571 logic [1:0] mio_pad_attr_30_slew_rate_30_qs;
1572 logic [1:0] mio_pad_attr_30_slew_rate_30_wd;
1573 logic [3:0] mio_pad_attr_30_drive_strength_30_qs;
1574 logic [3:0] mio_pad_attr_30_drive_strength_30_wd;
1575 logic mio_pad_attr_31_re;
1576 logic mio_pad_attr_31_we;
1577 logic mio_pad_attr_31_invert_31_qs;
1578 logic mio_pad_attr_31_invert_31_wd;
1579 logic mio_pad_attr_31_virtual_od_en_31_qs;
1580 logic mio_pad_attr_31_virtual_od_en_31_wd;
1581 logic mio_pad_attr_31_pull_en_31_qs;
1582 logic mio_pad_attr_31_pull_en_31_wd;
1583 logic mio_pad_attr_31_pull_select_31_qs;
1584 logic mio_pad_attr_31_pull_select_31_wd;
1585 logic mio_pad_attr_31_keeper_en_31_qs;
1586 logic mio_pad_attr_31_keeper_en_31_wd;
1587 logic mio_pad_attr_31_schmitt_en_31_qs;
1588 logic mio_pad_attr_31_schmitt_en_31_wd;
1589 logic mio_pad_attr_31_od_en_31_qs;
1590 logic mio_pad_attr_31_od_en_31_wd;
1591 logic mio_pad_attr_31_input_disable_31_qs;
1592 logic mio_pad_attr_31_input_disable_31_wd;
1593 logic [1:0] mio_pad_attr_31_slew_rate_31_qs;
1594 logic [1:0] mio_pad_attr_31_slew_rate_31_wd;
1595 logic [3:0] mio_pad_attr_31_drive_strength_31_qs;
1596 logic [3:0] mio_pad_attr_31_drive_strength_31_wd;
1597 logic mio_pad_attr_32_re;
1598 logic mio_pad_attr_32_we;
1599 logic mio_pad_attr_32_invert_32_qs;
1600 logic mio_pad_attr_32_invert_32_wd;
1601 logic mio_pad_attr_32_virtual_od_en_32_qs;
1602 logic mio_pad_attr_32_virtual_od_en_32_wd;
1603 logic mio_pad_attr_32_pull_en_32_qs;
1604 logic mio_pad_attr_32_pull_en_32_wd;
1605 logic mio_pad_attr_32_pull_select_32_qs;
1606 logic mio_pad_attr_32_pull_select_32_wd;
1607 logic mio_pad_attr_32_keeper_en_32_qs;
1608 logic mio_pad_attr_32_keeper_en_32_wd;
1609 logic mio_pad_attr_32_schmitt_en_32_qs;
1610 logic mio_pad_attr_32_schmitt_en_32_wd;
1611 logic mio_pad_attr_32_od_en_32_qs;
1612 logic mio_pad_attr_32_od_en_32_wd;
1613 logic mio_pad_attr_32_input_disable_32_qs;
1614 logic mio_pad_attr_32_input_disable_32_wd;
1615 logic [1:0] mio_pad_attr_32_slew_rate_32_qs;
1616 logic [1:0] mio_pad_attr_32_slew_rate_32_wd;
1617 logic [3:0] mio_pad_attr_32_drive_strength_32_qs;
1618 logic [3:0] mio_pad_attr_32_drive_strength_32_wd;
1619 logic mio_pad_attr_33_re;
1620 logic mio_pad_attr_33_we;
1621 logic mio_pad_attr_33_invert_33_qs;
1622 logic mio_pad_attr_33_invert_33_wd;
1623 logic mio_pad_attr_33_virtual_od_en_33_qs;
1624 logic mio_pad_attr_33_virtual_od_en_33_wd;
1625 logic mio_pad_attr_33_pull_en_33_qs;
1626 logic mio_pad_attr_33_pull_en_33_wd;
1627 logic mio_pad_attr_33_pull_select_33_qs;
1628 logic mio_pad_attr_33_pull_select_33_wd;
1629 logic mio_pad_attr_33_keeper_en_33_qs;
1630 logic mio_pad_attr_33_keeper_en_33_wd;
1631 logic mio_pad_attr_33_schmitt_en_33_qs;
1632 logic mio_pad_attr_33_schmitt_en_33_wd;
1633 logic mio_pad_attr_33_od_en_33_qs;
1634 logic mio_pad_attr_33_od_en_33_wd;
1635 logic mio_pad_attr_33_input_disable_33_qs;
1636 logic mio_pad_attr_33_input_disable_33_wd;
1637 logic [1:0] mio_pad_attr_33_slew_rate_33_qs;
1638 logic [1:0] mio_pad_attr_33_slew_rate_33_wd;
1639 logic [3:0] mio_pad_attr_33_drive_strength_33_qs;
1640 logic [3:0] mio_pad_attr_33_drive_strength_33_wd;
1641 logic mio_pad_attr_34_re;
1642 logic mio_pad_attr_34_we;
1643 logic mio_pad_attr_34_invert_34_qs;
1644 logic mio_pad_attr_34_invert_34_wd;
1645 logic mio_pad_attr_34_virtual_od_en_34_qs;
1646 logic mio_pad_attr_34_virtual_od_en_34_wd;
1647 logic mio_pad_attr_34_pull_en_34_qs;
1648 logic mio_pad_attr_34_pull_en_34_wd;
1649 logic mio_pad_attr_34_pull_select_34_qs;
1650 logic mio_pad_attr_34_pull_select_34_wd;
1651 logic mio_pad_attr_34_keeper_en_34_qs;
1652 logic mio_pad_attr_34_keeper_en_34_wd;
1653 logic mio_pad_attr_34_schmitt_en_34_qs;
1654 logic mio_pad_attr_34_schmitt_en_34_wd;
1655 logic mio_pad_attr_34_od_en_34_qs;
1656 logic mio_pad_attr_34_od_en_34_wd;
1657 logic mio_pad_attr_34_input_disable_34_qs;
1658 logic mio_pad_attr_34_input_disable_34_wd;
1659 logic [1:0] mio_pad_attr_34_slew_rate_34_qs;
1660 logic [1:0] mio_pad_attr_34_slew_rate_34_wd;
1661 logic [3:0] mio_pad_attr_34_drive_strength_34_qs;
1662 logic [3:0] mio_pad_attr_34_drive_strength_34_wd;
1663 logic mio_pad_attr_35_re;
1664 logic mio_pad_attr_35_we;
1665 logic mio_pad_attr_35_invert_35_qs;
1666 logic mio_pad_attr_35_invert_35_wd;
1667 logic mio_pad_attr_35_virtual_od_en_35_qs;
1668 logic mio_pad_attr_35_virtual_od_en_35_wd;
1669 logic mio_pad_attr_35_pull_en_35_qs;
1670 logic mio_pad_attr_35_pull_en_35_wd;
1671 logic mio_pad_attr_35_pull_select_35_qs;
1672 logic mio_pad_attr_35_pull_select_35_wd;
1673 logic mio_pad_attr_35_keeper_en_35_qs;
1674 logic mio_pad_attr_35_keeper_en_35_wd;
1675 logic mio_pad_attr_35_schmitt_en_35_qs;
1676 logic mio_pad_attr_35_schmitt_en_35_wd;
1677 logic mio_pad_attr_35_od_en_35_qs;
1678 logic mio_pad_attr_35_od_en_35_wd;
1679 logic mio_pad_attr_35_input_disable_35_qs;
1680 logic mio_pad_attr_35_input_disable_35_wd;
1681 logic [1:0] mio_pad_attr_35_slew_rate_35_qs;
1682 logic [1:0] mio_pad_attr_35_slew_rate_35_wd;
1683 logic [3:0] mio_pad_attr_35_drive_strength_35_qs;
1684 logic [3:0] mio_pad_attr_35_drive_strength_35_wd;
1685 logic mio_pad_attr_36_re;
1686 logic mio_pad_attr_36_we;
1687 logic mio_pad_attr_36_invert_36_qs;
1688 logic mio_pad_attr_36_invert_36_wd;
1689 logic mio_pad_attr_36_virtual_od_en_36_qs;
1690 logic mio_pad_attr_36_virtual_od_en_36_wd;
1691 logic mio_pad_attr_36_pull_en_36_qs;
1692 logic mio_pad_attr_36_pull_en_36_wd;
1693 logic mio_pad_attr_36_pull_select_36_qs;
1694 logic mio_pad_attr_36_pull_select_36_wd;
1695 logic mio_pad_attr_36_keeper_en_36_qs;
1696 logic mio_pad_attr_36_keeper_en_36_wd;
1697 logic mio_pad_attr_36_schmitt_en_36_qs;
1698 logic mio_pad_attr_36_schmitt_en_36_wd;
1699 logic mio_pad_attr_36_od_en_36_qs;
1700 logic mio_pad_attr_36_od_en_36_wd;
1701 logic mio_pad_attr_36_input_disable_36_qs;
1702 logic mio_pad_attr_36_input_disable_36_wd;
1703 logic [1:0] mio_pad_attr_36_slew_rate_36_qs;
1704 logic [1:0] mio_pad_attr_36_slew_rate_36_wd;
1705 logic [3:0] mio_pad_attr_36_drive_strength_36_qs;
1706 logic [3:0] mio_pad_attr_36_drive_strength_36_wd;
1707 logic mio_pad_attr_37_re;
1708 logic mio_pad_attr_37_we;
1709 logic mio_pad_attr_37_invert_37_qs;
1710 logic mio_pad_attr_37_invert_37_wd;
1711 logic mio_pad_attr_37_virtual_od_en_37_qs;
1712 logic mio_pad_attr_37_virtual_od_en_37_wd;
1713 logic mio_pad_attr_37_pull_en_37_qs;
1714 logic mio_pad_attr_37_pull_en_37_wd;
1715 logic mio_pad_attr_37_pull_select_37_qs;
1716 logic mio_pad_attr_37_pull_select_37_wd;
1717 logic mio_pad_attr_37_keeper_en_37_qs;
1718 logic mio_pad_attr_37_keeper_en_37_wd;
1719 logic mio_pad_attr_37_schmitt_en_37_qs;
1720 logic mio_pad_attr_37_schmitt_en_37_wd;
1721 logic mio_pad_attr_37_od_en_37_qs;
1722 logic mio_pad_attr_37_od_en_37_wd;
1723 logic mio_pad_attr_37_input_disable_37_qs;
1724 logic mio_pad_attr_37_input_disable_37_wd;
1725 logic [1:0] mio_pad_attr_37_slew_rate_37_qs;
1726 logic [1:0] mio_pad_attr_37_slew_rate_37_wd;
1727 logic [3:0] mio_pad_attr_37_drive_strength_37_qs;
1728 logic [3:0] mio_pad_attr_37_drive_strength_37_wd;
1729 logic mio_pad_attr_38_re;
1730 logic mio_pad_attr_38_we;
1731 logic mio_pad_attr_38_invert_38_qs;
1732 logic mio_pad_attr_38_invert_38_wd;
1733 logic mio_pad_attr_38_virtual_od_en_38_qs;
1734 logic mio_pad_attr_38_virtual_od_en_38_wd;
1735 logic mio_pad_attr_38_pull_en_38_qs;
1736 logic mio_pad_attr_38_pull_en_38_wd;
1737 logic mio_pad_attr_38_pull_select_38_qs;
1738 logic mio_pad_attr_38_pull_select_38_wd;
1739 logic mio_pad_attr_38_keeper_en_38_qs;
1740 logic mio_pad_attr_38_keeper_en_38_wd;
1741 logic mio_pad_attr_38_schmitt_en_38_qs;
1742 logic mio_pad_attr_38_schmitt_en_38_wd;
1743 logic mio_pad_attr_38_od_en_38_qs;
1744 logic mio_pad_attr_38_od_en_38_wd;
1745 logic mio_pad_attr_38_input_disable_38_qs;
1746 logic mio_pad_attr_38_input_disable_38_wd;
1747 logic [1:0] mio_pad_attr_38_slew_rate_38_qs;
1748 logic [1:0] mio_pad_attr_38_slew_rate_38_wd;
1749 logic [3:0] mio_pad_attr_38_drive_strength_38_qs;
1750 logic [3:0] mio_pad_attr_38_drive_strength_38_wd;
1751 logic mio_pad_attr_39_re;
1752 logic mio_pad_attr_39_we;
1753 logic mio_pad_attr_39_invert_39_qs;
1754 logic mio_pad_attr_39_invert_39_wd;
1755 logic mio_pad_attr_39_virtual_od_en_39_qs;
1756 logic mio_pad_attr_39_virtual_od_en_39_wd;
1757 logic mio_pad_attr_39_pull_en_39_qs;
1758 logic mio_pad_attr_39_pull_en_39_wd;
1759 logic mio_pad_attr_39_pull_select_39_qs;
1760 logic mio_pad_attr_39_pull_select_39_wd;
1761 logic mio_pad_attr_39_keeper_en_39_qs;
1762 logic mio_pad_attr_39_keeper_en_39_wd;
1763 logic mio_pad_attr_39_schmitt_en_39_qs;
1764 logic mio_pad_attr_39_schmitt_en_39_wd;
1765 logic mio_pad_attr_39_od_en_39_qs;
1766 logic mio_pad_attr_39_od_en_39_wd;
1767 logic mio_pad_attr_39_input_disable_39_qs;
1768 logic mio_pad_attr_39_input_disable_39_wd;
1769 logic [1:0] mio_pad_attr_39_slew_rate_39_qs;
1770 logic [1:0] mio_pad_attr_39_slew_rate_39_wd;
1771 logic [3:0] mio_pad_attr_39_drive_strength_39_qs;
1772 logic [3:0] mio_pad_attr_39_drive_strength_39_wd;
1773 logic mio_pad_attr_40_re;
1774 logic mio_pad_attr_40_we;
1775 logic mio_pad_attr_40_invert_40_qs;
1776 logic mio_pad_attr_40_invert_40_wd;
1777 logic mio_pad_attr_40_virtual_od_en_40_qs;
1778 logic mio_pad_attr_40_virtual_od_en_40_wd;
1779 logic mio_pad_attr_40_pull_en_40_qs;
1780 logic mio_pad_attr_40_pull_en_40_wd;
1781 logic mio_pad_attr_40_pull_select_40_qs;
1782 logic mio_pad_attr_40_pull_select_40_wd;
1783 logic mio_pad_attr_40_keeper_en_40_qs;
1784 logic mio_pad_attr_40_keeper_en_40_wd;
1785 logic mio_pad_attr_40_schmitt_en_40_qs;
1786 logic mio_pad_attr_40_schmitt_en_40_wd;
1787 logic mio_pad_attr_40_od_en_40_qs;
1788 logic mio_pad_attr_40_od_en_40_wd;
1789 logic mio_pad_attr_40_input_disable_40_qs;
1790 logic mio_pad_attr_40_input_disable_40_wd;
1791 logic [1:0] mio_pad_attr_40_slew_rate_40_qs;
1792 logic [1:0] mio_pad_attr_40_slew_rate_40_wd;
1793 logic [3:0] mio_pad_attr_40_drive_strength_40_qs;
1794 logic [3:0] mio_pad_attr_40_drive_strength_40_wd;
1795 logic mio_pad_attr_41_re;
1796 logic mio_pad_attr_41_we;
1797 logic mio_pad_attr_41_invert_41_qs;
1798 logic mio_pad_attr_41_invert_41_wd;
1799 logic mio_pad_attr_41_virtual_od_en_41_qs;
1800 logic mio_pad_attr_41_virtual_od_en_41_wd;
1801 logic mio_pad_attr_41_pull_en_41_qs;
1802 logic mio_pad_attr_41_pull_en_41_wd;
1803 logic mio_pad_attr_41_pull_select_41_qs;
1804 logic mio_pad_attr_41_pull_select_41_wd;
1805 logic mio_pad_attr_41_keeper_en_41_qs;
1806 logic mio_pad_attr_41_keeper_en_41_wd;
1807 logic mio_pad_attr_41_schmitt_en_41_qs;
1808 logic mio_pad_attr_41_schmitt_en_41_wd;
1809 logic mio_pad_attr_41_od_en_41_qs;
1810 logic mio_pad_attr_41_od_en_41_wd;
1811 logic mio_pad_attr_41_input_disable_41_qs;
1812 logic mio_pad_attr_41_input_disable_41_wd;
1813 logic [1:0] mio_pad_attr_41_slew_rate_41_qs;
1814 logic [1:0] mio_pad_attr_41_slew_rate_41_wd;
1815 logic [3:0] mio_pad_attr_41_drive_strength_41_qs;
1816 logic [3:0] mio_pad_attr_41_drive_strength_41_wd;
1817 logic mio_pad_attr_42_re;
1818 logic mio_pad_attr_42_we;
1819 logic mio_pad_attr_42_invert_42_qs;
1820 logic mio_pad_attr_42_invert_42_wd;
1821 logic mio_pad_attr_42_virtual_od_en_42_qs;
1822 logic mio_pad_attr_42_virtual_od_en_42_wd;
1823 logic mio_pad_attr_42_pull_en_42_qs;
1824 logic mio_pad_attr_42_pull_en_42_wd;
1825 logic mio_pad_attr_42_pull_select_42_qs;
1826 logic mio_pad_attr_42_pull_select_42_wd;
1827 logic mio_pad_attr_42_keeper_en_42_qs;
1828 logic mio_pad_attr_42_keeper_en_42_wd;
1829 logic mio_pad_attr_42_schmitt_en_42_qs;
1830 logic mio_pad_attr_42_schmitt_en_42_wd;
1831 logic mio_pad_attr_42_od_en_42_qs;
1832 logic mio_pad_attr_42_od_en_42_wd;
1833 logic mio_pad_attr_42_input_disable_42_qs;
1834 logic mio_pad_attr_42_input_disable_42_wd;
1835 logic [1:0] mio_pad_attr_42_slew_rate_42_qs;
1836 logic [1:0] mio_pad_attr_42_slew_rate_42_wd;
1837 logic [3:0] mio_pad_attr_42_drive_strength_42_qs;
1838 logic [3:0] mio_pad_attr_42_drive_strength_42_wd;
1839 logic mio_pad_attr_43_re;
1840 logic mio_pad_attr_43_we;
1841 logic mio_pad_attr_43_invert_43_qs;
1842 logic mio_pad_attr_43_invert_43_wd;
1843 logic mio_pad_attr_43_virtual_od_en_43_qs;
1844 logic mio_pad_attr_43_virtual_od_en_43_wd;
1845 logic mio_pad_attr_43_pull_en_43_qs;
1846 logic mio_pad_attr_43_pull_en_43_wd;
1847 logic mio_pad_attr_43_pull_select_43_qs;
1848 logic mio_pad_attr_43_pull_select_43_wd;
1849 logic mio_pad_attr_43_keeper_en_43_qs;
1850 logic mio_pad_attr_43_keeper_en_43_wd;
1851 logic mio_pad_attr_43_schmitt_en_43_qs;
1852 logic mio_pad_attr_43_schmitt_en_43_wd;
1853 logic mio_pad_attr_43_od_en_43_qs;
1854 logic mio_pad_attr_43_od_en_43_wd;
1855 logic mio_pad_attr_43_input_disable_43_qs;
1856 logic mio_pad_attr_43_input_disable_43_wd;
1857 logic [1:0] mio_pad_attr_43_slew_rate_43_qs;
1858 logic [1:0] mio_pad_attr_43_slew_rate_43_wd;
1859 logic [3:0] mio_pad_attr_43_drive_strength_43_qs;
1860 logic [3:0] mio_pad_attr_43_drive_strength_43_wd;
1861 logic mio_pad_attr_44_re;
1862 logic mio_pad_attr_44_we;
1863 logic mio_pad_attr_44_invert_44_qs;
1864 logic mio_pad_attr_44_invert_44_wd;
1865 logic mio_pad_attr_44_virtual_od_en_44_qs;
1866 logic mio_pad_attr_44_virtual_od_en_44_wd;
1867 logic mio_pad_attr_44_pull_en_44_qs;
1868 logic mio_pad_attr_44_pull_en_44_wd;
1869 logic mio_pad_attr_44_pull_select_44_qs;
1870 logic mio_pad_attr_44_pull_select_44_wd;
1871 logic mio_pad_attr_44_keeper_en_44_qs;
1872 logic mio_pad_attr_44_keeper_en_44_wd;
1873 logic mio_pad_attr_44_schmitt_en_44_qs;
1874 logic mio_pad_attr_44_schmitt_en_44_wd;
1875 logic mio_pad_attr_44_od_en_44_qs;
1876 logic mio_pad_attr_44_od_en_44_wd;
1877 logic mio_pad_attr_44_input_disable_44_qs;
1878 logic mio_pad_attr_44_input_disable_44_wd;
1879 logic [1:0] mio_pad_attr_44_slew_rate_44_qs;
1880 logic [1:0] mio_pad_attr_44_slew_rate_44_wd;
1881 logic [3:0] mio_pad_attr_44_drive_strength_44_qs;
1882 logic [3:0] mio_pad_attr_44_drive_strength_44_wd;
1883 logic mio_pad_attr_45_re;
1884 logic mio_pad_attr_45_we;
1885 logic mio_pad_attr_45_invert_45_qs;
1886 logic mio_pad_attr_45_invert_45_wd;
1887 logic mio_pad_attr_45_virtual_od_en_45_qs;
1888 logic mio_pad_attr_45_virtual_od_en_45_wd;
1889 logic mio_pad_attr_45_pull_en_45_qs;
1890 logic mio_pad_attr_45_pull_en_45_wd;
1891 logic mio_pad_attr_45_pull_select_45_qs;
1892 logic mio_pad_attr_45_pull_select_45_wd;
1893 logic mio_pad_attr_45_keeper_en_45_qs;
1894 logic mio_pad_attr_45_keeper_en_45_wd;
1895 logic mio_pad_attr_45_schmitt_en_45_qs;
1896 logic mio_pad_attr_45_schmitt_en_45_wd;
1897 logic mio_pad_attr_45_od_en_45_qs;
1898 logic mio_pad_attr_45_od_en_45_wd;
1899 logic mio_pad_attr_45_input_disable_45_qs;
1900 logic mio_pad_attr_45_input_disable_45_wd;
1901 logic [1:0] mio_pad_attr_45_slew_rate_45_qs;
1902 logic [1:0] mio_pad_attr_45_slew_rate_45_wd;
1903 logic [3:0] mio_pad_attr_45_drive_strength_45_qs;
1904 logic [3:0] mio_pad_attr_45_drive_strength_45_wd;
1905 logic mio_pad_attr_46_re;
1906 logic mio_pad_attr_46_we;
1907 logic mio_pad_attr_46_invert_46_qs;
1908 logic mio_pad_attr_46_invert_46_wd;
1909 logic mio_pad_attr_46_virtual_od_en_46_qs;
1910 logic mio_pad_attr_46_virtual_od_en_46_wd;
1911 logic mio_pad_attr_46_pull_en_46_qs;
1912 logic mio_pad_attr_46_pull_en_46_wd;
1913 logic mio_pad_attr_46_pull_select_46_qs;
1914 logic mio_pad_attr_46_pull_select_46_wd;
1915 logic mio_pad_attr_46_keeper_en_46_qs;
1916 logic mio_pad_attr_46_keeper_en_46_wd;
1917 logic mio_pad_attr_46_schmitt_en_46_qs;
1918 logic mio_pad_attr_46_schmitt_en_46_wd;
1919 logic mio_pad_attr_46_od_en_46_qs;
1920 logic mio_pad_attr_46_od_en_46_wd;
1921 logic mio_pad_attr_46_input_disable_46_qs;
1922 logic mio_pad_attr_46_input_disable_46_wd;
1923 logic [1:0] mio_pad_attr_46_slew_rate_46_qs;
1924 logic [1:0] mio_pad_attr_46_slew_rate_46_wd;
1925 logic [3:0] mio_pad_attr_46_drive_strength_46_qs;
1926 logic [3:0] mio_pad_attr_46_drive_strength_46_wd;
1927 logic dio_pad_attr_regwen_0_we;
1928 logic dio_pad_attr_regwen_0_qs;
1929 logic dio_pad_attr_regwen_0_wd;
1930 logic dio_pad_attr_regwen_1_we;
1931 logic dio_pad_attr_regwen_1_qs;
1932 logic dio_pad_attr_regwen_1_wd;
1933 logic dio_pad_attr_regwen_2_we;
1934 logic dio_pad_attr_regwen_2_qs;
1935 logic dio_pad_attr_regwen_2_wd;
1936 logic dio_pad_attr_regwen_3_we;
1937 logic dio_pad_attr_regwen_3_qs;
1938 logic dio_pad_attr_regwen_3_wd;
1939 logic dio_pad_attr_regwen_4_we;
1940 logic dio_pad_attr_regwen_4_qs;
1941 logic dio_pad_attr_regwen_4_wd;
1942 logic dio_pad_attr_regwen_5_we;
1943 logic dio_pad_attr_regwen_5_qs;
1944 logic dio_pad_attr_regwen_5_wd;
1945 logic dio_pad_attr_regwen_6_we;
1946 logic dio_pad_attr_regwen_6_qs;
1947 logic dio_pad_attr_regwen_6_wd;
1948 logic dio_pad_attr_regwen_7_we;
1949 logic dio_pad_attr_regwen_7_qs;
1950 logic dio_pad_attr_regwen_7_wd;
1951 logic dio_pad_attr_regwen_8_we;
1952 logic dio_pad_attr_regwen_8_qs;
1953 logic dio_pad_attr_regwen_8_wd;
1954 logic dio_pad_attr_regwen_9_we;
1955 logic dio_pad_attr_regwen_9_qs;
1956 logic dio_pad_attr_regwen_9_wd;
1957 logic dio_pad_attr_regwen_10_we;
1958 logic dio_pad_attr_regwen_10_qs;
1959 logic dio_pad_attr_regwen_10_wd;
1960 logic dio_pad_attr_regwen_11_we;
1961 logic dio_pad_attr_regwen_11_qs;
1962 logic dio_pad_attr_regwen_11_wd;
1963 logic dio_pad_attr_regwen_12_we;
1964 logic dio_pad_attr_regwen_12_qs;
1965 logic dio_pad_attr_regwen_12_wd;
1966 logic dio_pad_attr_regwen_13_we;
1967 logic dio_pad_attr_regwen_13_qs;
1968 logic dio_pad_attr_regwen_13_wd;
1969 logic dio_pad_attr_regwen_14_we;
1970 logic dio_pad_attr_regwen_14_qs;
1971 logic dio_pad_attr_regwen_14_wd;
1972 logic dio_pad_attr_regwen_15_we;
1973 logic dio_pad_attr_regwen_15_qs;
1974 logic dio_pad_attr_regwen_15_wd;
1975 logic dio_pad_attr_0_re;
1976 logic dio_pad_attr_0_we;
1977 logic dio_pad_attr_0_invert_0_qs;
1978 logic dio_pad_attr_0_invert_0_wd;
1979 logic dio_pad_attr_0_virtual_od_en_0_qs;
1980 logic dio_pad_attr_0_virtual_od_en_0_wd;
1981 logic dio_pad_attr_0_pull_en_0_qs;
1982 logic dio_pad_attr_0_pull_en_0_wd;
1983 logic dio_pad_attr_0_pull_select_0_qs;
1984 logic dio_pad_attr_0_pull_select_0_wd;
1985 logic dio_pad_attr_0_keeper_en_0_qs;
1986 logic dio_pad_attr_0_keeper_en_0_wd;
1987 logic dio_pad_attr_0_schmitt_en_0_qs;
1988 logic dio_pad_attr_0_schmitt_en_0_wd;
1989 logic dio_pad_attr_0_od_en_0_qs;
1990 logic dio_pad_attr_0_od_en_0_wd;
1991 logic dio_pad_attr_0_input_disable_0_qs;
1992 logic dio_pad_attr_0_input_disable_0_wd;
1993 logic [1:0] dio_pad_attr_0_slew_rate_0_qs;
1994 logic [1:0] dio_pad_attr_0_slew_rate_0_wd;
1995 logic [3:0] dio_pad_attr_0_drive_strength_0_qs;
1996 logic [3:0] dio_pad_attr_0_drive_strength_0_wd;
1997 logic dio_pad_attr_1_re;
1998 logic dio_pad_attr_1_we;
1999 logic dio_pad_attr_1_invert_1_qs;
2000 logic dio_pad_attr_1_invert_1_wd;
2001 logic dio_pad_attr_1_virtual_od_en_1_qs;
2002 logic dio_pad_attr_1_virtual_od_en_1_wd;
2003 logic dio_pad_attr_1_pull_en_1_qs;
2004 logic dio_pad_attr_1_pull_en_1_wd;
2005 logic dio_pad_attr_1_pull_select_1_qs;
2006 logic dio_pad_attr_1_pull_select_1_wd;
2007 logic dio_pad_attr_1_keeper_en_1_qs;
2008 logic dio_pad_attr_1_keeper_en_1_wd;
2009 logic dio_pad_attr_1_schmitt_en_1_qs;
2010 logic dio_pad_attr_1_schmitt_en_1_wd;
2011 logic dio_pad_attr_1_od_en_1_qs;
2012 logic dio_pad_attr_1_od_en_1_wd;
2013 logic dio_pad_attr_1_input_disable_1_qs;
2014 logic dio_pad_attr_1_input_disable_1_wd;
2015 logic [1:0] dio_pad_attr_1_slew_rate_1_qs;
2016 logic [1:0] dio_pad_attr_1_slew_rate_1_wd;
2017 logic [3:0] dio_pad_attr_1_drive_strength_1_qs;
2018 logic [3:0] dio_pad_attr_1_drive_strength_1_wd;
2019 logic dio_pad_attr_2_re;
2020 logic dio_pad_attr_2_we;
2021 logic dio_pad_attr_2_invert_2_qs;
2022 logic dio_pad_attr_2_invert_2_wd;
2023 logic dio_pad_attr_2_virtual_od_en_2_qs;
2024 logic dio_pad_attr_2_virtual_od_en_2_wd;
2025 logic dio_pad_attr_2_pull_en_2_qs;
2026 logic dio_pad_attr_2_pull_en_2_wd;
2027 logic dio_pad_attr_2_pull_select_2_qs;
2028 logic dio_pad_attr_2_pull_select_2_wd;
2029 logic dio_pad_attr_2_keeper_en_2_qs;
2030 logic dio_pad_attr_2_keeper_en_2_wd;
2031 logic dio_pad_attr_2_schmitt_en_2_qs;
2032 logic dio_pad_attr_2_schmitt_en_2_wd;
2033 logic dio_pad_attr_2_od_en_2_qs;
2034 logic dio_pad_attr_2_od_en_2_wd;
2035 logic dio_pad_attr_2_input_disable_2_qs;
2036 logic dio_pad_attr_2_input_disable_2_wd;
2037 logic [1:0] dio_pad_attr_2_slew_rate_2_qs;
2038 logic [1:0] dio_pad_attr_2_slew_rate_2_wd;
2039 logic [3:0] dio_pad_attr_2_drive_strength_2_qs;
2040 logic [3:0] dio_pad_attr_2_drive_strength_2_wd;
2041 logic dio_pad_attr_3_re;
2042 logic dio_pad_attr_3_we;
2043 logic dio_pad_attr_3_invert_3_qs;
2044 logic dio_pad_attr_3_invert_3_wd;
2045 logic dio_pad_attr_3_virtual_od_en_3_qs;
2046 logic dio_pad_attr_3_virtual_od_en_3_wd;
2047 logic dio_pad_attr_3_pull_en_3_qs;
2048 logic dio_pad_attr_3_pull_en_3_wd;
2049 logic dio_pad_attr_3_pull_select_3_qs;
2050 logic dio_pad_attr_3_pull_select_3_wd;
2051 logic dio_pad_attr_3_keeper_en_3_qs;
2052 logic dio_pad_attr_3_keeper_en_3_wd;
2053 logic dio_pad_attr_3_schmitt_en_3_qs;
2054 logic dio_pad_attr_3_schmitt_en_3_wd;
2055 logic dio_pad_attr_3_od_en_3_qs;
2056 logic dio_pad_attr_3_od_en_3_wd;
2057 logic dio_pad_attr_3_input_disable_3_qs;
2058 logic dio_pad_attr_3_input_disable_3_wd;
2059 logic [1:0] dio_pad_attr_3_slew_rate_3_qs;
2060 logic [1:0] dio_pad_attr_3_slew_rate_3_wd;
2061 logic [3:0] dio_pad_attr_3_drive_strength_3_qs;
2062 logic [3:0] dio_pad_attr_3_drive_strength_3_wd;
2063 logic dio_pad_attr_4_re;
2064 logic dio_pad_attr_4_we;
2065 logic dio_pad_attr_4_invert_4_qs;
2066 logic dio_pad_attr_4_invert_4_wd;
2067 logic dio_pad_attr_4_virtual_od_en_4_qs;
2068 logic dio_pad_attr_4_virtual_od_en_4_wd;
2069 logic dio_pad_attr_4_pull_en_4_qs;
2070 logic dio_pad_attr_4_pull_en_4_wd;
2071 logic dio_pad_attr_4_pull_select_4_qs;
2072 logic dio_pad_attr_4_pull_select_4_wd;
2073 logic dio_pad_attr_4_keeper_en_4_qs;
2074 logic dio_pad_attr_4_keeper_en_4_wd;
2075 logic dio_pad_attr_4_schmitt_en_4_qs;
2076 logic dio_pad_attr_4_schmitt_en_4_wd;
2077 logic dio_pad_attr_4_od_en_4_qs;
2078 logic dio_pad_attr_4_od_en_4_wd;
2079 logic dio_pad_attr_4_input_disable_4_qs;
2080 logic dio_pad_attr_4_input_disable_4_wd;
2081 logic [1:0] dio_pad_attr_4_slew_rate_4_qs;
2082 logic [1:0] dio_pad_attr_4_slew_rate_4_wd;
2083 logic [3:0] dio_pad_attr_4_drive_strength_4_qs;
2084 logic [3:0] dio_pad_attr_4_drive_strength_4_wd;
2085 logic dio_pad_attr_5_re;
2086 logic dio_pad_attr_5_we;
2087 logic dio_pad_attr_5_invert_5_qs;
2088 logic dio_pad_attr_5_invert_5_wd;
2089 logic dio_pad_attr_5_virtual_od_en_5_qs;
2090 logic dio_pad_attr_5_virtual_od_en_5_wd;
2091 logic dio_pad_attr_5_pull_en_5_qs;
2092 logic dio_pad_attr_5_pull_en_5_wd;
2093 logic dio_pad_attr_5_pull_select_5_qs;
2094 logic dio_pad_attr_5_pull_select_5_wd;
2095 logic dio_pad_attr_5_keeper_en_5_qs;
2096 logic dio_pad_attr_5_keeper_en_5_wd;
2097 logic dio_pad_attr_5_schmitt_en_5_qs;
2098 logic dio_pad_attr_5_schmitt_en_5_wd;
2099 logic dio_pad_attr_5_od_en_5_qs;
2100 logic dio_pad_attr_5_od_en_5_wd;
2101 logic dio_pad_attr_5_input_disable_5_qs;
2102 logic dio_pad_attr_5_input_disable_5_wd;
2103 logic [1:0] dio_pad_attr_5_slew_rate_5_qs;
2104 logic [1:0] dio_pad_attr_5_slew_rate_5_wd;
2105 logic [3:0] dio_pad_attr_5_drive_strength_5_qs;
2106 logic [3:0] dio_pad_attr_5_drive_strength_5_wd;
2107 logic dio_pad_attr_6_re;
2108 logic dio_pad_attr_6_we;
2109 logic dio_pad_attr_6_invert_6_qs;
2110 logic dio_pad_attr_6_invert_6_wd;
2111 logic dio_pad_attr_6_virtual_od_en_6_qs;
2112 logic dio_pad_attr_6_virtual_od_en_6_wd;
2113 logic dio_pad_attr_6_pull_en_6_qs;
2114 logic dio_pad_attr_6_pull_en_6_wd;
2115 logic dio_pad_attr_6_pull_select_6_qs;
2116 logic dio_pad_attr_6_pull_select_6_wd;
2117 logic dio_pad_attr_6_keeper_en_6_qs;
2118 logic dio_pad_attr_6_keeper_en_6_wd;
2119 logic dio_pad_attr_6_schmitt_en_6_qs;
2120 logic dio_pad_attr_6_schmitt_en_6_wd;
2121 logic dio_pad_attr_6_od_en_6_qs;
2122 logic dio_pad_attr_6_od_en_6_wd;
2123 logic dio_pad_attr_6_input_disable_6_qs;
2124 logic dio_pad_attr_6_input_disable_6_wd;
2125 logic [1:0] dio_pad_attr_6_slew_rate_6_qs;
2126 logic [1:0] dio_pad_attr_6_slew_rate_6_wd;
2127 logic [3:0] dio_pad_attr_6_drive_strength_6_qs;
2128 logic [3:0] dio_pad_attr_6_drive_strength_6_wd;
2129 logic dio_pad_attr_7_re;
2130 logic dio_pad_attr_7_we;
2131 logic dio_pad_attr_7_invert_7_qs;
2132 logic dio_pad_attr_7_invert_7_wd;
2133 logic dio_pad_attr_7_virtual_od_en_7_qs;
2134 logic dio_pad_attr_7_virtual_od_en_7_wd;
2135 logic dio_pad_attr_7_pull_en_7_qs;
2136 logic dio_pad_attr_7_pull_en_7_wd;
2137 logic dio_pad_attr_7_pull_select_7_qs;
2138 logic dio_pad_attr_7_pull_select_7_wd;
2139 logic dio_pad_attr_7_keeper_en_7_qs;
2140 logic dio_pad_attr_7_keeper_en_7_wd;
2141 logic dio_pad_attr_7_schmitt_en_7_qs;
2142 logic dio_pad_attr_7_schmitt_en_7_wd;
2143 logic dio_pad_attr_7_od_en_7_qs;
2144 logic dio_pad_attr_7_od_en_7_wd;
2145 logic dio_pad_attr_7_input_disable_7_qs;
2146 logic dio_pad_attr_7_input_disable_7_wd;
2147 logic [1:0] dio_pad_attr_7_slew_rate_7_qs;
2148 logic [1:0] dio_pad_attr_7_slew_rate_7_wd;
2149 logic [3:0] dio_pad_attr_7_drive_strength_7_qs;
2150 logic [3:0] dio_pad_attr_7_drive_strength_7_wd;
2151 logic dio_pad_attr_8_re;
2152 logic dio_pad_attr_8_we;
2153 logic dio_pad_attr_8_invert_8_qs;
2154 logic dio_pad_attr_8_invert_8_wd;
2155 logic dio_pad_attr_8_virtual_od_en_8_qs;
2156 logic dio_pad_attr_8_virtual_od_en_8_wd;
2157 logic dio_pad_attr_8_pull_en_8_qs;
2158 logic dio_pad_attr_8_pull_en_8_wd;
2159 logic dio_pad_attr_8_pull_select_8_qs;
2160 logic dio_pad_attr_8_pull_select_8_wd;
2161 logic dio_pad_attr_8_keeper_en_8_qs;
2162 logic dio_pad_attr_8_keeper_en_8_wd;
2163 logic dio_pad_attr_8_schmitt_en_8_qs;
2164 logic dio_pad_attr_8_schmitt_en_8_wd;
2165 logic dio_pad_attr_8_od_en_8_qs;
2166 logic dio_pad_attr_8_od_en_8_wd;
2167 logic dio_pad_attr_8_input_disable_8_qs;
2168 logic dio_pad_attr_8_input_disable_8_wd;
2169 logic [1:0] dio_pad_attr_8_slew_rate_8_qs;
2170 logic [1:0] dio_pad_attr_8_slew_rate_8_wd;
2171 logic [3:0] dio_pad_attr_8_drive_strength_8_qs;
2172 logic [3:0] dio_pad_attr_8_drive_strength_8_wd;
2173 logic dio_pad_attr_9_re;
2174 logic dio_pad_attr_9_we;
2175 logic dio_pad_attr_9_invert_9_qs;
2176 logic dio_pad_attr_9_invert_9_wd;
2177 logic dio_pad_attr_9_virtual_od_en_9_qs;
2178 logic dio_pad_attr_9_virtual_od_en_9_wd;
2179 logic dio_pad_attr_9_pull_en_9_qs;
2180 logic dio_pad_attr_9_pull_en_9_wd;
2181 logic dio_pad_attr_9_pull_select_9_qs;
2182 logic dio_pad_attr_9_pull_select_9_wd;
2183 logic dio_pad_attr_9_keeper_en_9_qs;
2184 logic dio_pad_attr_9_keeper_en_9_wd;
2185 logic dio_pad_attr_9_schmitt_en_9_qs;
2186 logic dio_pad_attr_9_schmitt_en_9_wd;
2187 logic dio_pad_attr_9_od_en_9_qs;
2188 logic dio_pad_attr_9_od_en_9_wd;
2189 logic dio_pad_attr_9_input_disable_9_qs;
2190 logic dio_pad_attr_9_input_disable_9_wd;
2191 logic [1:0] dio_pad_attr_9_slew_rate_9_qs;
2192 logic [1:0] dio_pad_attr_9_slew_rate_9_wd;
2193 logic [3:0] dio_pad_attr_9_drive_strength_9_qs;
2194 logic [3:0] dio_pad_attr_9_drive_strength_9_wd;
2195 logic dio_pad_attr_10_re;
2196 logic dio_pad_attr_10_we;
2197 logic dio_pad_attr_10_invert_10_qs;
2198 logic dio_pad_attr_10_invert_10_wd;
2199 logic dio_pad_attr_10_virtual_od_en_10_qs;
2200 logic dio_pad_attr_10_virtual_od_en_10_wd;
2201 logic dio_pad_attr_10_pull_en_10_qs;
2202 logic dio_pad_attr_10_pull_en_10_wd;
2203 logic dio_pad_attr_10_pull_select_10_qs;
2204 logic dio_pad_attr_10_pull_select_10_wd;
2205 logic dio_pad_attr_10_keeper_en_10_qs;
2206 logic dio_pad_attr_10_keeper_en_10_wd;
2207 logic dio_pad_attr_10_schmitt_en_10_qs;
2208 logic dio_pad_attr_10_schmitt_en_10_wd;
2209 logic dio_pad_attr_10_od_en_10_qs;
2210 logic dio_pad_attr_10_od_en_10_wd;
2211 logic dio_pad_attr_10_input_disable_10_qs;
2212 logic dio_pad_attr_10_input_disable_10_wd;
2213 logic [1:0] dio_pad_attr_10_slew_rate_10_qs;
2214 logic [1:0] dio_pad_attr_10_slew_rate_10_wd;
2215 logic [3:0] dio_pad_attr_10_drive_strength_10_qs;
2216 logic [3:0] dio_pad_attr_10_drive_strength_10_wd;
2217 logic dio_pad_attr_11_re;
2218 logic dio_pad_attr_11_we;
2219 logic dio_pad_attr_11_invert_11_qs;
2220 logic dio_pad_attr_11_invert_11_wd;
2221 logic dio_pad_attr_11_virtual_od_en_11_qs;
2222 logic dio_pad_attr_11_virtual_od_en_11_wd;
2223 logic dio_pad_attr_11_pull_en_11_qs;
2224 logic dio_pad_attr_11_pull_en_11_wd;
2225 logic dio_pad_attr_11_pull_select_11_qs;
2226 logic dio_pad_attr_11_pull_select_11_wd;
2227 logic dio_pad_attr_11_keeper_en_11_qs;
2228 logic dio_pad_attr_11_keeper_en_11_wd;
2229 logic dio_pad_attr_11_schmitt_en_11_qs;
2230 logic dio_pad_attr_11_schmitt_en_11_wd;
2231 logic dio_pad_attr_11_od_en_11_qs;
2232 logic dio_pad_attr_11_od_en_11_wd;
2233 logic dio_pad_attr_11_input_disable_11_qs;
2234 logic dio_pad_attr_11_input_disable_11_wd;
2235 logic [1:0] dio_pad_attr_11_slew_rate_11_qs;
2236 logic [1:0] dio_pad_attr_11_slew_rate_11_wd;
2237 logic [3:0] dio_pad_attr_11_drive_strength_11_qs;
2238 logic [3:0] dio_pad_attr_11_drive_strength_11_wd;
2239 logic dio_pad_attr_12_re;
2240 logic dio_pad_attr_12_we;
2241 logic dio_pad_attr_12_invert_12_qs;
2242 logic dio_pad_attr_12_invert_12_wd;
2243 logic dio_pad_attr_12_virtual_od_en_12_qs;
2244 logic dio_pad_attr_12_virtual_od_en_12_wd;
2245 logic dio_pad_attr_12_pull_en_12_qs;
2246 logic dio_pad_attr_12_pull_en_12_wd;
2247 logic dio_pad_attr_12_pull_select_12_qs;
2248 logic dio_pad_attr_12_pull_select_12_wd;
2249 logic dio_pad_attr_12_keeper_en_12_qs;
2250 logic dio_pad_attr_12_keeper_en_12_wd;
2251 logic dio_pad_attr_12_schmitt_en_12_qs;
2252 logic dio_pad_attr_12_schmitt_en_12_wd;
2253 logic dio_pad_attr_12_od_en_12_qs;
2254 logic dio_pad_attr_12_od_en_12_wd;
2255 logic dio_pad_attr_12_input_disable_12_qs;
2256 logic dio_pad_attr_12_input_disable_12_wd;
2257 logic [1:0] dio_pad_attr_12_slew_rate_12_qs;
2258 logic [1:0] dio_pad_attr_12_slew_rate_12_wd;
2259 logic [3:0] dio_pad_attr_12_drive_strength_12_qs;
2260 logic [3:0] dio_pad_attr_12_drive_strength_12_wd;
2261 logic dio_pad_attr_13_re;
2262 logic dio_pad_attr_13_we;
2263 logic dio_pad_attr_13_invert_13_qs;
2264 logic dio_pad_attr_13_invert_13_wd;
2265 logic dio_pad_attr_13_virtual_od_en_13_qs;
2266 logic dio_pad_attr_13_virtual_od_en_13_wd;
2267 logic dio_pad_attr_13_pull_en_13_qs;
2268 logic dio_pad_attr_13_pull_en_13_wd;
2269 logic dio_pad_attr_13_pull_select_13_qs;
2270 logic dio_pad_attr_13_pull_select_13_wd;
2271 logic dio_pad_attr_13_keeper_en_13_qs;
2272 logic dio_pad_attr_13_keeper_en_13_wd;
2273 logic dio_pad_attr_13_schmitt_en_13_qs;
2274 logic dio_pad_attr_13_schmitt_en_13_wd;
2275 logic dio_pad_attr_13_od_en_13_qs;
2276 logic dio_pad_attr_13_od_en_13_wd;
2277 logic dio_pad_attr_13_input_disable_13_qs;
2278 logic dio_pad_attr_13_input_disable_13_wd;
2279 logic [1:0] dio_pad_attr_13_slew_rate_13_qs;
2280 logic [1:0] dio_pad_attr_13_slew_rate_13_wd;
2281 logic [3:0] dio_pad_attr_13_drive_strength_13_qs;
2282 logic [3:0] dio_pad_attr_13_drive_strength_13_wd;
2283 logic dio_pad_attr_14_re;
2284 logic dio_pad_attr_14_we;
2285 logic dio_pad_attr_14_invert_14_qs;
2286 logic dio_pad_attr_14_invert_14_wd;
2287 logic dio_pad_attr_14_virtual_od_en_14_qs;
2288 logic dio_pad_attr_14_virtual_od_en_14_wd;
2289 logic dio_pad_attr_14_pull_en_14_qs;
2290 logic dio_pad_attr_14_pull_en_14_wd;
2291 logic dio_pad_attr_14_pull_select_14_qs;
2292 logic dio_pad_attr_14_pull_select_14_wd;
2293 logic dio_pad_attr_14_keeper_en_14_qs;
2294 logic dio_pad_attr_14_keeper_en_14_wd;
2295 logic dio_pad_attr_14_schmitt_en_14_qs;
2296 logic dio_pad_attr_14_schmitt_en_14_wd;
2297 logic dio_pad_attr_14_od_en_14_qs;
2298 logic dio_pad_attr_14_od_en_14_wd;
2299 logic dio_pad_attr_14_input_disable_14_qs;
2300 logic dio_pad_attr_14_input_disable_14_wd;
2301 logic [1:0] dio_pad_attr_14_slew_rate_14_qs;
2302 logic [1:0] dio_pad_attr_14_slew_rate_14_wd;
2303 logic [3:0] dio_pad_attr_14_drive_strength_14_qs;
2304 logic [3:0] dio_pad_attr_14_drive_strength_14_wd;
2305 logic dio_pad_attr_15_re;
2306 logic dio_pad_attr_15_we;
2307 logic dio_pad_attr_15_invert_15_qs;
2308 logic dio_pad_attr_15_invert_15_wd;
2309 logic dio_pad_attr_15_virtual_od_en_15_qs;
2310 logic dio_pad_attr_15_virtual_od_en_15_wd;
2311 logic dio_pad_attr_15_pull_en_15_qs;
2312 logic dio_pad_attr_15_pull_en_15_wd;
2313 logic dio_pad_attr_15_pull_select_15_qs;
2314 logic dio_pad_attr_15_pull_select_15_wd;
2315 logic dio_pad_attr_15_keeper_en_15_qs;
2316 logic dio_pad_attr_15_keeper_en_15_wd;
2317 logic dio_pad_attr_15_schmitt_en_15_qs;
2318 logic dio_pad_attr_15_schmitt_en_15_wd;
2319 logic dio_pad_attr_15_od_en_15_qs;
2320 logic dio_pad_attr_15_od_en_15_wd;
2321 logic dio_pad_attr_15_input_disable_15_qs;
2322 logic dio_pad_attr_15_input_disable_15_wd;
2323 logic [1:0] dio_pad_attr_15_slew_rate_15_qs;
2324 logic [1:0] dio_pad_attr_15_slew_rate_15_wd;
2325 logic [3:0] dio_pad_attr_15_drive_strength_15_qs;
2326 logic [3:0] dio_pad_attr_15_drive_strength_15_wd;
2327 logic mio_pad_sleep_status_0_we;
2328 logic mio_pad_sleep_status_0_en_0_qs;
2329 logic mio_pad_sleep_status_0_en_0_wd;
2330 logic mio_pad_sleep_status_0_en_1_qs;
2331 logic mio_pad_sleep_status_0_en_1_wd;
2332 logic mio_pad_sleep_status_0_en_2_qs;
2333 logic mio_pad_sleep_status_0_en_2_wd;
2334 logic mio_pad_sleep_status_0_en_3_qs;
2335 logic mio_pad_sleep_status_0_en_3_wd;
2336 logic mio_pad_sleep_status_0_en_4_qs;
2337 logic mio_pad_sleep_status_0_en_4_wd;
2338 logic mio_pad_sleep_status_0_en_5_qs;
2339 logic mio_pad_sleep_status_0_en_5_wd;
2340 logic mio_pad_sleep_status_0_en_6_qs;
2341 logic mio_pad_sleep_status_0_en_6_wd;
2342 logic mio_pad_sleep_status_0_en_7_qs;
2343 logic mio_pad_sleep_status_0_en_7_wd;
2344 logic mio_pad_sleep_status_0_en_8_qs;
2345 logic mio_pad_sleep_status_0_en_8_wd;
2346 logic mio_pad_sleep_status_0_en_9_qs;
2347 logic mio_pad_sleep_status_0_en_9_wd;
2348 logic mio_pad_sleep_status_0_en_10_qs;
2349 logic mio_pad_sleep_status_0_en_10_wd;
2350 logic mio_pad_sleep_status_0_en_11_qs;
2351 logic mio_pad_sleep_status_0_en_11_wd;
2352 logic mio_pad_sleep_status_0_en_12_qs;
2353 logic mio_pad_sleep_status_0_en_12_wd;
2354 logic mio_pad_sleep_status_0_en_13_qs;
2355 logic mio_pad_sleep_status_0_en_13_wd;
2356 logic mio_pad_sleep_status_0_en_14_qs;
2357 logic mio_pad_sleep_status_0_en_14_wd;
2358 logic mio_pad_sleep_status_0_en_15_qs;
2359 logic mio_pad_sleep_status_0_en_15_wd;
2360 logic mio_pad_sleep_status_0_en_16_qs;
2361 logic mio_pad_sleep_status_0_en_16_wd;
2362 logic mio_pad_sleep_status_0_en_17_qs;
2363 logic mio_pad_sleep_status_0_en_17_wd;
2364 logic mio_pad_sleep_status_0_en_18_qs;
2365 logic mio_pad_sleep_status_0_en_18_wd;
2366 logic mio_pad_sleep_status_0_en_19_qs;
2367 logic mio_pad_sleep_status_0_en_19_wd;
2368 logic mio_pad_sleep_status_0_en_20_qs;
2369 logic mio_pad_sleep_status_0_en_20_wd;
2370 logic mio_pad_sleep_status_0_en_21_qs;
2371 logic mio_pad_sleep_status_0_en_21_wd;
2372 logic mio_pad_sleep_status_0_en_22_qs;
2373 logic mio_pad_sleep_status_0_en_22_wd;
2374 logic mio_pad_sleep_status_0_en_23_qs;
2375 logic mio_pad_sleep_status_0_en_23_wd;
2376 logic mio_pad_sleep_status_0_en_24_qs;
2377 logic mio_pad_sleep_status_0_en_24_wd;
2378 logic mio_pad_sleep_status_0_en_25_qs;
2379 logic mio_pad_sleep_status_0_en_25_wd;
2380 logic mio_pad_sleep_status_0_en_26_qs;
2381 logic mio_pad_sleep_status_0_en_26_wd;
2382 logic mio_pad_sleep_status_0_en_27_qs;
2383 logic mio_pad_sleep_status_0_en_27_wd;
2384 logic mio_pad_sleep_status_0_en_28_qs;
2385 logic mio_pad_sleep_status_0_en_28_wd;
2386 logic mio_pad_sleep_status_0_en_29_qs;
2387 logic mio_pad_sleep_status_0_en_29_wd;
2388 logic mio_pad_sleep_status_0_en_30_qs;
2389 logic mio_pad_sleep_status_0_en_30_wd;
2390 logic mio_pad_sleep_status_0_en_31_qs;
2391 logic mio_pad_sleep_status_0_en_31_wd;
2392 logic mio_pad_sleep_status_1_we;
2393 logic mio_pad_sleep_status_1_en_32_qs;
2394 logic mio_pad_sleep_status_1_en_32_wd;
2395 logic mio_pad_sleep_status_1_en_33_qs;
2396 logic mio_pad_sleep_status_1_en_33_wd;
2397 logic mio_pad_sleep_status_1_en_34_qs;
2398 logic mio_pad_sleep_status_1_en_34_wd;
2399 logic mio_pad_sleep_status_1_en_35_qs;
2400 logic mio_pad_sleep_status_1_en_35_wd;
2401 logic mio_pad_sleep_status_1_en_36_qs;
2402 logic mio_pad_sleep_status_1_en_36_wd;
2403 logic mio_pad_sleep_status_1_en_37_qs;
2404 logic mio_pad_sleep_status_1_en_37_wd;
2405 logic mio_pad_sleep_status_1_en_38_qs;
2406 logic mio_pad_sleep_status_1_en_38_wd;
2407 logic mio_pad_sleep_status_1_en_39_qs;
2408 logic mio_pad_sleep_status_1_en_39_wd;
2409 logic mio_pad_sleep_status_1_en_40_qs;
2410 logic mio_pad_sleep_status_1_en_40_wd;
2411 logic mio_pad_sleep_status_1_en_41_qs;
2412 logic mio_pad_sleep_status_1_en_41_wd;
2413 logic mio_pad_sleep_status_1_en_42_qs;
2414 logic mio_pad_sleep_status_1_en_42_wd;
2415 logic mio_pad_sleep_status_1_en_43_qs;
2416 logic mio_pad_sleep_status_1_en_43_wd;
2417 logic mio_pad_sleep_status_1_en_44_qs;
2418 logic mio_pad_sleep_status_1_en_44_wd;
2419 logic mio_pad_sleep_status_1_en_45_qs;
2420 logic mio_pad_sleep_status_1_en_45_wd;
2421 logic mio_pad_sleep_status_1_en_46_qs;
2422 logic mio_pad_sleep_status_1_en_46_wd;
2423 logic mio_pad_sleep_regwen_0_we;
2424 logic mio_pad_sleep_regwen_0_qs;
2425 logic mio_pad_sleep_regwen_0_wd;
2426 logic mio_pad_sleep_regwen_1_we;
2427 logic mio_pad_sleep_regwen_1_qs;
2428 logic mio_pad_sleep_regwen_1_wd;
2429 logic mio_pad_sleep_regwen_2_we;
2430 logic mio_pad_sleep_regwen_2_qs;
2431 logic mio_pad_sleep_regwen_2_wd;
2432 logic mio_pad_sleep_regwen_3_we;
2433 logic mio_pad_sleep_regwen_3_qs;
2434 logic mio_pad_sleep_regwen_3_wd;
2435 logic mio_pad_sleep_regwen_4_we;
2436 logic mio_pad_sleep_regwen_4_qs;
2437 logic mio_pad_sleep_regwen_4_wd;
2438 logic mio_pad_sleep_regwen_5_we;
2439 logic mio_pad_sleep_regwen_5_qs;
2440 logic mio_pad_sleep_regwen_5_wd;
2441 logic mio_pad_sleep_regwen_6_we;
2442 logic mio_pad_sleep_regwen_6_qs;
2443 logic mio_pad_sleep_regwen_6_wd;
2444 logic mio_pad_sleep_regwen_7_we;
2445 logic mio_pad_sleep_regwen_7_qs;
2446 logic mio_pad_sleep_regwen_7_wd;
2447 logic mio_pad_sleep_regwen_8_we;
2448 logic mio_pad_sleep_regwen_8_qs;
2449 logic mio_pad_sleep_regwen_8_wd;
2450 logic mio_pad_sleep_regwen_9_we;
2451 logic mio_pad_sleep_regwen_9_qs;
2452 logic mio_pad_sleep_regwen_9_wd;
2453 logic mio_pad_sleep_regwen_10_we;
2454 logic mio_pad_sleep_regwen_10_qs;
2455 logic mio_pad_sleep_regwen_10_wd;
2456 logic mio_pad_sleep_regwen_11_we;
2457 logic mio_pad_sleep_regwen_11_qs;
2458 logic mio_pad_sleep_regwen_11_wd;
2459 logic mio_pad_sleep_regwen_12_we;
2460 logic mio_pad_sleep_regwen_12_qs;
2461 logic mio_pad_sleep_regwen_12_wd;
2462 logic mio_pad_sleep_regwen_13_we;
2463 logic mio_pad_sleep_regwen_13_qs;
2464 logic mio_pad_sleep_regwen_13_wd;
2465 logic mio_pad_sleep_regwen_14_we;
2466 logic mio_pad_sleep_regwen_14_qs;
2467 logic mio_pad_sleep_regwen_14_wd;
2468 logic mio_pad_sleep_regwen_15_we;
2469 logic mio_pad_sleep_regwen_15_qs;
2470 logic mio_pad_sleep_regwen_15_wd;
2471 logic mio_pad_sleep_regwen_16_we;
2472 logic mio_pad_sleep_regwen_16_qs;
2473 logic mio_pad_sleep_regwen_16_wd;
2474 logic mio_pad_sleep_regwen_17_we;
2475 logic mio_pad_sleep_regwen_17_qs;
2476 logic mio_pad_sleep_regwen_17_wd;
2477 logic mio_pad_sleep_regwen_18_we;
2478 logic mio_pad_sleep_regwen_18_qs;
2479 logic mio_pad_sleep_regwen_18_wd;
2480 logic mio_pad_sleep_regwen_19_we;
2481 logic mio_pad_sleep_regwen_19_qs;
2482 logic mio_pad_sleep_regwen_19_wd;
2483 logic mio_pad_sleep_regwen_20_we;
2484 logic mio_pad_sleep_regwen_20_qs;
2485 logic mio_pad_sleep_regwen_20_wd;
2486 logic mio_pad_sleep_regwen_21_we;
2487 logic mio_pad_sleep_regwen_21_qs;
2488 logic mio_pad_sleep_regwen_21_wd;
2489 logic mio_pad_sleep_regwen_22_we;
2490 logic mio_pad_sleep_regwen_22_qs;
2491 logic mio_pad_sleep_regwen_22_wd;
2492 logic mio_pad_sleep_regwen_23_we;
2493 logic mio_pad_sleep_regwen_23_qs;
2494 logic mio_pad_sleep_regwen_23_wd;
2495 logic mio_pad_sleep_regwen_24_we;
2496 logic mio_pad_sleep_regwen_24_qs;
2497 logic mio_pad_sleep_regwen_24_wd;
2498 logic mio_pad_sleep_regwen_25_we;
2499 logic mio_pad_sleep_regwen_25_qs;
2500 logic mio_pad_sleep_regwen_25_wd;
2501 logic mio_pad_sleep_regwen_26_we;
2502 logic mio_pad_sleep_regwen_26_qs;
2503 logic mio_pad_sleep_regwen_26_wd;
2504 logic mio_pad_sleep_regwen_27_we;
2505 logic mio_pad_sleep_regwen_27_qs;
2506 logic mio_pad_sleep_regwen_27_wd;
2507 logic mio_pad_sleep_regwen_28_we;
2508 logic mio_pad_sleep_regwen_28_qs;
2509 logic mio_pad_sleep_regwen_28_wd;
2510 logic mio_pad_sleep_regwen_29_we;
2511 logic mio_pad_sleep_regwen_29_qs;
2512 logic mio_pad_sleep_regwen_29_wd;
2513 logic mio_pad_sleep_regwen_30_we;
2514 logic mio_pad_sleep_regwen_30_qs;
2515 logic mio_pad_sleep_regwen_30_wd;
2516 logic mio_pad_sleep_regwen_31_we;
2517 logic mio_pad_sleep_regwen_31_qs;
2518 logic mio_pad_sleep_regwen_31_wd;
2519 logic mio_pad_sleep_regwen_32_we;
2520 logic mio_pad_sleep_regwen_32_qs;
2521 logic mio_pad_sleep_regwen_32_wd;
2522 logic mio_pad_sleep_regwen_33_we;
2523 logic mio_pad_sleep_regwen_33_qs;
2524 logic mio_pad_sleep_regwen_33_wd;
2525 logic mio_pad_sleep_regwen_34_we;
2526 logic mio_pad_sleep_regwen_34_qs;
2527 logic mio_pad_sleep_regwen_34_wd;
2528 logic mio_pad_sleep_regwen_35_we;
2529 logic mio_pad_sleep_regwen_35_qs;
2530 logic mio_pad_sleep_regwen_35_wd;
2531 logic mio_pad_sleep_regwen_36_we;
2532 logic mio_pad_sleep_regwen_36_qs;
2533 logic mio_pad_sleep_regwen_36_wd;
2534 logic mio_pad_sleep_regwen_37_we;
2535 logic mio_pad_sleep_regwen_37_qs;
2536 logic mio_pad_sleep_regwen_37_wd;
2537 logic mio_pad_sleep_regwen_38_we;
2538 logic mio_pad_sleep_regwen_38_qs;
2539 logic mio_pad_sleep_regwen_38_wd;
2540 logic mio_pad_sleep_regwen_39_we;
2541 logic mio_pad_sleep_regwen_39_qs;
2542 logic mio_pad_sleep_regwen_39_wd;
2543 logic mio_pad_sleep_regwen_40_we;
2544 logic mio_pad_sleep_regwen_40_qs;
2545 logic mio_pad_sleep_regwen_40_wd;
2546 logic mio_pad_sleep_regwen_41_we;
2547 logic mio_pad_sleep_regwen_41_qs;
2548 logic mio_pad_sleep_regwen_41_wd;
2549 logic mio_pad_sleep_regwen_42_we;
2550 logic mio_pad_sleep_regwen_42_qs;
2551 logic mio_pad_sleep_regwen_42_wd;
2552 logic mio_pad_sleep_regwen_43_we;
2553 logic mio_pad_sleep_regwen_43_qs;
2554 logic mio_pad_sleep_regwen_43_wd;
2555 logic mio_pad_sleep_regwen_44_we;
2556 logic mio_pad_sleep_regwen_44_qs;
2557 logic mio_pad_sleep_regwen_44_wd;
2558 logic mio_pad_sleep_regwen_45_we;
2559 logic mio_pad_sleep_regwen_45_qs;
2560 logic mio_pad_sleep_regwen_45_wd;
2561 logic mio_pad_sleep_regwen_46_we;
2562 logic mio_pad_sleep_regwen_46_qs;
2563 logic mio_pad_sleep_regwen_46_wd;
2564 logic mio_pad_sleep_en_0_we;
2565 logic mio_pad_sleep_en_0_qs;
2566 logic mio_pad_sleep_en_0_wd;
2567 logic mio_pad_sleep_en_1_we;
2568 logic mio_pad_sleep_en_1_qs;
2569 logic mio_pad_sleep_en_1_wd;
2570 logic mio_pad_sleep_en_2_we;
2571 logic mio_pad_sleep_en_2_qs;
2572 logic mio_pad_sleep_en_2_wd;
2573 logic mio_pad_sleep_en_3_we;
2574 logic mio_pad_sleep_en_3_qs;
2575 logic mio_pad_sleep_en_3_wd;
2576 logic mio_pad_sleep_en_4_we;
2577 logic mio_pad_sleep_en_4_qs;
2578 logic mio_pad_sleep_en_4_wd;
2579 logic mio_pad_sleep_en_5_we;
2580 logic mio_pad_sleep_en_5_qs;
2581 logic mio_pad_sleep_en_5_wd;
2582 logic mio_pad_sleep_en_6_we;
2583 logic mio_pad_sleep_en_6_qs;
2584 logic mio_pad_sleep_en_6_wd;
2585 logic mio_pad_sleep_en_7_we;
2586 logic mio_pad_sleep_en_7_qs;
2587 logic mio_pad_sleep_en_7_wd;
2588 logic mio_pad_sleep_en_8_we;
2589 logic mio_pad_sleep_en_8_qs;
2590 logic mio_pad_sleep_en_8_wd;
2591 logic mio_pad_sleep_en_9_we;
2592 logic mio_pad_sleep_en_9_qs;
2593 logic mio_pad_sleep_en_9_wd;
2594 logic mio_pad_sleep_en_10_we;
2595 logic mio_pad_sleep_en_10_qs;
2596 logic mio_pad_sleep_en_10_wd;
2597 logic mio_pad_sleep_en_11_we;
2598 logic mio_pad_sleep_en_11_qs;
2599 logic mio_pad_sleep_en_11_wd;
2600 logic mio_pad_sleep_en_12_we;
2601 logic mio_pad_sleep_en_12_qs;
2602 logic mio_pad_sleep_en_12_wd;
2603 logic mio_pad_sleep_en_13_we;
2604 logic mio_pad_sleep_en_13_qs;
2605 logic mio_pad_sleep_en_13_wd;
2606 logic mio_pad_sleep_en_14_we;
2607 logic mio_pad_sleep_en_14_qs;
2608 logic mio_pad_sleep_en_14_wd;
2609 logic mio_pad_sleep_en_15_we;
2610 logic mio_pad_sleep_en_15_qs;
2611 logic mio_pad_sleep_en_15_wd;
2612 logic mio_pad_sleep_en_16_we;
2613 logic mio_pad_sleep_en_16_qs;
2614 logic mio_pad_sleep_en_16_wd;
2615 logic mio_pad_sleep_en_17_we;
2616 logic mio_pad_sleep_en_17_qs;
2617 logic mio_pad_sleep_en_17_wd;
2618 logic mio_pad_sleep_en_18_we;
2619 logic mio_pad_sleep_en_18_qs;
2620 logic mio_pad_sleep_en_18_wd;
2621 logic mio_pad_sleep_en_19_we;
2622 logic mio_pad_sleep_en_19_qs;
2623 logic mio_pad_sleep_en_19_wd;
2624 logic mio_pad_sleep_en_20_we;
2625 logic mio_pad_sleep_en_20_qs;
2626 logic mio_pad_sleep_en_20_wd;
2627 logic mio_pad_sleep_en_21_we;
2628 logic mio_pad_sleep_en_21_qs;
2629 logic mio_pad_sleep_en_21_wd;
2630 logic mio_pad_sleep_en_22_we;
2631 logic mio_pad_sleep_en_22_qs;
2632 logic mio_pad_sleep_en_22_wd;
2633 logic mio_pad_sleep_en_23_we;
2634 logic mio_pad_sleep_en_23_qs;
2635 logic mio_pad_sleep_en_23_wd;
2636 logic mio_pad_sleep_en_24_we;
2637 logic mio_pad_sleep_en_24_qs;
2638 logic mio_pad_sleep_en_24_wd;
2639 logic mio_pad_sleep_en_25_we;
2640 logic mio_pad_sleep_en_25_qs;
2641 logic mio_pad_sleep_en_25_wd;
2642 logic mio_pad_sleep_en_26_we;
2643 logic mio_pad_sleep_en_26_qs;
2644 logic mio_pad_sleep_en_26_wd;
2645 logic mio_pad_sleep_en_27_we;
2646 logic mio_pad_sleep_en_27_qs;
2647 logic mio_pad_sleep_en_27_wd;
2648 logic mio_pad_sleep_en_28_we;
2649 logic mio_pad_sleep_en_28_qs;
2650 logic mio_pad_sleep_en_28_wd;
2651 logic mio_pad_sleep_en_29_we;
2652 logic mio_pad_sleep_en_29_qs;
2653 logic mio_pad_sleep_en_29_wd;
2654 logic mio_pad_sleep_en_30_we;
2655 logic mio_pad_sleep_en_30_qs;
2656 logic mio_pad_sleep_en_30_wd;
2657 logic mio_pad_sleep_en_31_we;
2658 logic mio_pad_sleep_en_31_qs;
2659 logic mio_pad_sleep_en_31_wd;
2660 logic mio_pad_sleep_en_32_we;
2661 logic mio_pad_sleep_en_32_qs;
2662 logic mio_pad_sleep_en_32_wd;
2663 logic mio_pad_sleep_en_33_we;
2664 logic mio_pad_sleep_en_33_qs;
2665 logic mio_pad_sleep_en_33_wd;
2666 logic mio_pad_sleep_en_34_we;
2667 logic mio_pad_sleep_en_34_qs;
2668 logic mio_pad_sleep_en_34_wd;
2669 logic mio_pad_sleep_en_35_we;
2670 logic mio_pad_sleep_en_35_qs;
2671 logic mio_pad_sleep_en_35_wd;
2672 logic mio_pad_sleep_en_36_we;
2673 logic mio_pad_sleep_en_36_qs;
2674 logic mio_pad_sleep_en_36_wd;
2675 logic mio_pad_sleep_en_37_we;
2676 logic mio_pad_sleep_en_37_qs;
2677 logic mio_pad_sleep_en_37_wd;
2678 logic mio_pad_sleep_en_38_we;
2679 logic mio_pad_sleep_en_38_qs;
2680 logic mio_pad_sleep_en_38_wd;
2681 logic mio_pad_sleep_en_39_we;
2682 logic mio_pad_sleep_en_39_qs;
2683 logic mio_pad_sleep_en_39_wd;
2684 logic mio_pad_sleep_en_40_we;
2685 logic mio_pad_sleep_en_40_qs;
2686 logic mio_pad_sleep_en_40_wd;
2687 logic mio_pad_sleep_en_41_we;
2688 logic mio_pad_sleep_en_41_qs;
2689 logic mio_pad_sleep_en_41_wd;
2690 logic mio_pad_sleep_en_42_we;
2691 logic mio_pad_sleep_en_42_qs;
2692 logic mio_pad_sleep_en_42_wd;
2693 logic mio_pad_sleep_en_43_we;
2694 logic mio_pad_sleep_en_43_qs;
2695 logic mio_pad_sleep_en_43_wd;
2696 logic mio_pad_sleep_en_44_we;
2697 logic mio_pad_sleep_en_44_qs;
2698 logic mio_pad_sleep_en_44_wd;
2699 logic mio_pad_sleep_en_45_we;
2700 logic mio_pad_sleep_en_45_qs;
2701 logic mio_pad_sleep_en_45_wd;
2702 logic mio_pad_sleep_en_46_we;
2703 logic mio_pad_sleep_en_46_qs;
2704 logic mio_pad_sleep_en_46_wd;
2705 logic mio_pad_sleep_mode_0_we;
2706 logic [1:0] mio_pad_sleep_mode_0_qs;
2707 logic [1:0] mio_pad_sleep_mode_0_wd;
2708 logic mio_pad_sleep_mode_1_we;
2709 logic [1:0] mio_pad_sleep_mode_1_qs;
2710 logic [1:0] mio_pad_sleep_mode_1_wd;
2711 logic mio_pad_sleep_mode_2_we;
2712 logic [1:0] mio_pad_sleep_mode_2_qs;
2713 logic [1:0] mio_pad_sleep_mode_2_wd;
2714 logic mio_pad_sleep_mode_3_we;
2715 logic [1:0] mio_pad_sleep_mode_3_qs;
2716 logic [1:0] mio_pad_sleep_mode_3_wd;
2717 logic mio_pad_sleep_mode_4_we;
2718 logic [1:0] mio_pad_sleep_mode_4_qs;
2719 logic [1:0] mio_pad_sleep_mode_4_wd;
2720 logic mio_pad_sleep_mode_5_we;
2721 logic [1:0] mio_pad_sleep_mode_5_qs;
2722 logic [1:0] mio_pad_sleep_mode_5_wd;
2723 logic mio_pad_sleep_mode_6_we;
2724 logic [1:0] mio_pad_sleep_mode_6_qs;
2725 logic [1:0] mio_pad_sleep_mode_6_wd;
2726 logic mio_pad_sleep_mode_7_we;
2727 logic [1:0] mio_pad_sleep_mode_7_qs;
2728 logic [1:0] mio_pad_sleep_mode_7_wd;
2729 logic mio_pad_sleep_mode_8_we;
2730 logic [1:0] mio_pad_sleep_mode_8_qs;
2731 logic [1:0] mio_pad_sleep_mode_8_wd;
2732 logic mio_pad_sleep_mode_9_we;
2733 logic [1:0] mio_pad_sleep_mode_9_qs;
2734 logic [1:0] mio_pad_sleep_mode_9_wd;
2735 logic mio_pad_sleep_mode_10_we;
2736 logic [1:0] mio_pad_sleep_mode_10_qs;
2737 logic [1:0] mio_pad_sleep_mode_10_wd;
2738 logic mio_pad_sleep_mode_11_we;
2739 logic [1:0] mio_pad_sleep_mode_11_qs;
2740 logic [1:0] mio_pad_sleep_mode_11_wd;
2741 logic mio_pad_sleep_mode_12_we;
2742 logic [1:0] mio_pad_sleep_mode_12_qs;
2743 logic [1:0] mio_pad_sleep_mode_12_wd;
2744 logic mio_pad_sleep_mode_13_we;
2745 logic [1:0] mio_pad_sleep_mode_13_qs;
2746 logic [1:0] mio_pad_sleep_mode_13_wd;
2747 logic mio_pad_sleep_mode_14_we;
2748 logic [1:0] mio_pad_sleep_mode_14_qs;
2749 logic [1:0] mio_pad_sleep_mode_14_wd;
2750 logic mio_pad_sleep_mode_15_we;
2751 logic [1:0] mio_pad_sleep_mode_15_qs;
2752 logic [1:0] mio_pad_sleep_mode_15_wd;
2753 logic mio_pad_sleep_mode_16_we;
2754 logic [1:0] mio_pad_sleep_mode_16_qs;
2755 logic [1:0] mio_pad_sleep_mode_16_wd;
2756 logic mio_pad_sleep_mode_17_we;
2757 logic [1:0] mio_pad_sleep_mode_17_qs;
2758 logic [1:0] mio_pad_sleep_mode_17_wd;
2759 logic mio_pad_sleep_mode_18_we;
2760 logic [1:0] mio_pad_sleep_mode_18_qs;
2761 logic [1:0] mio_pad_sleep_mode_18_wd;
2762 logic mio_pad_sleep_mode_19_we;
2763 logic [1:0] mio_pad_sleep_mode_19_qs;
2764 logic [1:0] mio_pad_sleep_mode_19_wd;
2765 logic mio_pad_sleep_mode_20_we;
2766 logic [1:0] mio_pad_sleep_mode_20_qs;
2767 logic [1:0] mio_pad_sleep_mode_20_wd;
2768 logic mio_pad_sleep_mode_21_we;
2769 logic [1:0] mio_pad_sleep_mode_21_qs;
2770 logic [1:0] mio_pad_sleep_mode_21_wd;
2771 logic mio_pad_sleep_mode_22_we;
2772 logic [1:0] mio_pad_sleep_mode_22_qs;
2773 logic [1:0] mio_pad_sleep_mode_22_wd;
2774 logic mio_pad_sleep_mode_23_we;
2775 logic [1:0] mio_pad_sleep_mode_23_qs;
2776 logic [1:0] mio_pad_sleep_mode_23_wd;
2777 logic mio_pad_sleep_mode_24_we;
2778 logic [1:0] mio_pad_sleep_mode_24_qs;
2779 logic [1:0] mio_pad_sleep_mode_24_wd;
2780 logic mio_pad_sleep_mode_25_we;
2781 logic [1:0] mio_pad_sleep_mode_25_qs;
2782 logic [1:0] mio_pad_sleep_mode_25_wd;
2783 logic mio_pad_sleep_mode_26_we;
2784 logic [1:0] mio_pad_sleep_mode_26_qs;
2785 logic [1:0] mio_pad_sleep_mode_26_wd;
2786 logic mio_pad_sleep_mode_27_we;
2787 logic [1:0] mio_pad_sleep_mode_27_qs;
2788 logic [1:0] mio_pad_sleep_mode_27_wd;
2789 logic mio_pad_sleep_mode_28_we;
2790 logic [1:0] mio_pad_sleep_mode_28_qs;
2791 logic [1:0] mio_pad_sleep_mode_28_wd;
2792 logic mio_pad_sleep_mode_29_we;
2793 logic [1:0] mio_pad_sleep_mode_29_qs;
2794 logic [1:0] mio_pad_sleep_mode_29_wd;
2795 logic mio_pad_sleep_mode_30_we;
2796 logic [1:0] mio_pad_sleep_mode_30_qs;
2797 logic [1:0] mio_pad_sleep_mode_30_wd;
2798 logic mio_pad_sleep_mode_31_we;
2799 logic [1:0] mio_pad_sleep_mode_31_qs;
2800 logic [1:0] mio_pad_sleep_mode_31_wd;
2801 logic mio_pad_sleep_mode_32_we;
2802 logic [1:0] mio_pad_sleep_mode_32_qs;
2803 logic [1:0] mio_pad_sleep_mode_32_wd;
2804 logic mio_pad_sleep_mode_33_we;
2805 logic [1:0] mio_pad_sleep_mode_33_qs;
2806 logic [1:0] mio_pad_sleep_mode_33_wd;
2807 logic mio_pad_sleep_mode_34_we;
2808 logic [1:0] mio_pad_sleep_mode_34_qs;
2809 logic [1:0] mio_pad_sleep_mode_34_wd;
2810 logic mio_pad_sleep_mode_35_we;
2811 logic [1:0] mio_pad_sleep_mode_35_qs;
2812 logic [1:0] mio_pad_sleep_mode_35_wd;
2813 logic mio_pad_sleep_mode_36_we;
2814 logic [1:0] mio_pad_sleep_mode_36_qs;
2815 logic [1:0] mio_pad_sleep_mode_36_wd;
2816 logic mio_pad_sleep_mode_37_we;
2817 logic [1:0] mio_pad_sleep_mode_37_qs;
2818 logic [1:0] mio_pad_sleep_mode_37_wd;
2819 logic mio_pad_sleep_mode_38_we;
2820 logic [1:0] mio_pad_sleep_mode_38_qs;
2821 logic [1:0] mio_pad_sleep_mode_38_wd;
2822 logic mio_pad_sleep_mode_39_we;
2823 logic [1:0] mio_pad_sleep_mode_39_qs;
2824 logic [1:0] mio_pad_sleep_mode_39_wd;
2825 logic mio_pad_sleep_mode_40_we;
2826 logic [1:0] mio_pad_sleep_mode_40_qs;
2827 logic [1:0] mio_pad_sleep_mode_40_wd;
2828 logic mio_pad_sleep_mode_41_we;
2829 logic [1:0] mio_pad_sleep_mode_41_qs;
2830 logic [1:0] mio_pad_sleep_mode_41_wd;
2831 logic mio_pad_sleep_mode_42_we;
2832 logic [1:0] mio_pad_sleep_mode_42_qs;
2833 logic [1:0] mio_pad_sleep_mode_42_wd;
2834 logic mio_pad_sleep_mode_43_we;
2835 logic [1:0] mio_pad_sleep_mode_43_qs;
2836 logic [1:0] mio_pad_sleep_mode_43_wd;
2837 logic mio_pad_sleep_mode_44_we;
2838 logic [1:0] mio_pad_sleep_mode_44_qs;
2839 logic [1:0] mio_pad_sleep_mode_44_wd;
2840 logic mio_pad_sleep_mode_45_we;
2841 logic [1:0] mio_pad_sleep_mode_45_qs;
2842 logic [1:0] mio_pad_sleep_mode_45_wd;
2843 logic mio_pad_sleep_mode_46_we;
2844 logic [1:0] mio_pad_sleep_mode_46_qs;
2845 logic [1:0] mio_pad_sleep_mode_46_wd;
2846 logic dio_pad_sleep_status_we;
2847 logic dio_pad_sleep_status_en_0_qs;
2848 logic dio_pad_sleep_status_en_0_wd;
2849 logic dio_pad_sleep_status_en_1_qs;
2850 logic dio_pad_sleep_status_en_1_wd;
2851 logic dio_pad_sleep_status_en_2_qs;
2852 logic dio_pad_sleep_status_en_2_wd;
2853 logic dio_pad_sleep_status_en_3_qs;
2854 logic dio_pad_sleep_status_en_3_wd;
2855 logic dio_pad_sleep_status_en_4_qs;
2856 logic dio_pad_sleep_status_en_4_wd;
2857 logic dio_pad_sleep_status_en_5_qs;
2858 logic dio_pad_sleep_status_en_5_wd;
2859 logic dio_pad_sleep_status_en_6_qs;
2860 logic dio_pad_sleep_status_en_6_wd;
2861 logic dio_pad_sleep_status_en_7_qs;
2862 logic dio_pad_sleep_status_en_7_wd;
2863 logic dio_pad_sleep_status_en_8_qs;
2864 logic dio_pad_sleep_status_en_8_wd;
2865 logic dio_pad_sleep_status_en_9_qs;
2866 logic dio_pad_sleep_status_en_9_wd;
2867 logic dio_pad_sleep_status_en_10_qs;
2868 logic dio_pad_sleep_status_en_10_wd;
2869 logic dio_pad_sleep_status_en_11_qs;
2870 logic dio_pad_sleep_status_en_11_wd;
2871 logic dio_pad_sleep_status_en_12_qs;
2872 logic dio_pad_sleep_status_en_12_wd;
2873 logic dio_pad_sleep_status_en_13_qs;
2874 logic dio_pad_sleep_status_en_13_wd;
2875 logic dio_pad_sleep_status_en_14_qs;
2876 logic dio_pad_sleep_status_en_14_wd;
2877 logic dio_pad_sleep_status_en_15_qs;
2878 logic dio_pad_sleep_status_en_15_wd;
2879 logic dio_pad_sleep_regwen_0_we;
2880 logic dio_pad_sleep_regwen_0_qs;
2881 logic dio_pad_sleep_regwen_0_wd;
2882 logic dio_pad_sleep_regwen_1_we;
2883 logic dio_pad_sleep_regwen_1_qs;
2884 logic dio_pad_sleep_regwen_1_wd;
2885 logic dio_pad_sleep_regwen_2_we;
2886 logic dio_pad_sleep_regwen_2_qs;
2887 logic dio_pad_sleep_regwen_2_wd;
2888 logic dio_pad_sleep_regwen_3_we;
2889 logic dio_pad_sleep_regwen_3_qs;
2890 logic dio_pad_sleep_regwen_3_wd;
2891 logic dio_pad_sleep_regwen_4_we;
2892 logic dio_pad_sleep_regwen_4_qs;
2893 logic dio_pad_sleep_regwen_4_wd;
2894 logic dio_pad_sleep_regwen_5_we;
2895 logic dio_pad_sleep_regwen_5_qs;
2896 logic dio_pad_sleep_regwen_5_wd;
2897 logic dio_pad_sleep_regwen_6_we;
2898 logic dio_pad_sleep_regwen_6_qs;
2899 logic dio_pad_sleep_regwen_6_wd;
2900 logic dio_pad_sleep_regwen_7_we;
2901 logic dio_pad_sleep_regwen_7_qs;
2902 logic dio_pad_sleep_regwen_7_wd;
2903 logic dio_pad_sleep_regwen_8_we;
2904 logic dio_pad_sleep_regwen_8_qs;
2905 logic dio_pad_sleep_regwen_8_wd;
2906 logic dio_pad_sleep_regwen_9_we;
2907 logic dio_pad_sleep_regwen_9_qs;
2908 logic dio_pad_sleep_regwen_9_wd;
2909 logic dio_pad_sleep_regwen_10_we;
2910 logic dio_pad_sleep_regwen_10_qs;
2911 logic dio_pad_sleep_regwen_10_wd;
2912 logic dio_pad_sleep_regwen_11_we;
2913 logic dio_pad_sleep_regwen_11_qs;
2914 logic dio_pad_sleep_regwen_11_wd;
2915 logic dio_pad_sleep_regwen_12_we;
2916 logic dio_pad_sleep_regwen_12_qs;
2917 logic dio_pad_sleep_regwen_12_wd;
2918 logic dio_pad_sleep_regwen_13_we;
2919 logic dio_pad_sleep_regwen_13_qs;
2920 logic dio_pad_sleep_regwen_13_wd;
2921 logic dio_pad_sleep_regwen_14_we;
2922 logic dio_pad_sleep_regwen_14_qs;
2923 logic dio_pad_sleep_regwen_14_wd;
2924 logic dio_pad_sleep_regwen_15_we;
2925 logic dio_pad_sleep_regwen_15_qs;
2926 logic dio_pad_sleep_regwen_15_wd;
2927 logic dio_pad_sleep_en_0_we;
2928 logic dio_pad_sleep_en_0_qs;
2929 logic dio_pad_sleep_en_0_wd;
2930 logic dio_pad_sleep_en_1_we;
2931 logic dio_pad_sleep_en_1_qs;
2932 logic dio_pad_sleep_en_1_wd;
2933 logic dio_pad_sleep_en_2_we;
2934 logic dio_pad_sleep_en_2_qs;
2935 logic dio_pad_sleep_en_2_wd;
2936 logic dio_pad_sleep_en_3_we;
2937 logic dio_pad_sleep_en_3_qs;
2938 logic dio_pad_sleep_en_3_wd;
2939 logic dio_pad_sleep_en_4_we;
2940 logic dio_pad_sleep_en_4_qs;
2941 logic dio_pad_sleep_en_4_wd;
2942 logic dio_pad_sleep_en_5_we;
2943 logic dio_pad_sleep_en_5_qs;
2944 logic dio_pad_sleep_en_5_wd;
2945 logic dio_pad_sleep_en_6_we;
2946 logic dio_pad_sleep_en_6_qs;
2947 logic dio_pad_sleep_en_6_wd;
2948 logic dio_pad_sleep_en_7_we;
2949 logic dio_pad_sleep_en_7_qs;
2950 logic dio_pad_sleep_en_7_wd;
2951 logic dio_pad_sleep_en_8_we;
2952 logic dio_pad_sleep_en_8_qs;
2953 logic dio_pad_sleep_en_8_wd;
2954 logic dio_pad_sleep_en_9_we;
2955 logic dio_pad_sleep_en_9_qs;
2956 logic dio_pad_sleep_en_9_wd;
2957 logic dio_pad_sleep_en_10_we;
2958 logic dio_pad_sleep_en_10_qs;
2959 logic dio_pad_sleep_en_10_wd;
2960 logic dio_pad_sleep_en_11_we;
2961 logic dio_pad_sleep_en_11_qs;
2962 logic dio_pad_sleep_en_11_wd;
2963 logic dio_pad_sleep_en_12_we;
2964 logic dio_pad_sleep_en_12_qs;
2965 logic dio_pad_sleep_en_12_wd;
2966 logic dio_pad_sleep_en_13_we;
2967 logic dio_pad_sleep_en_13_qs;
2968 logic dio_pad_sleep_en_13_wd;
2969 logic dio_pad_sleep_en_14_we;
2970 logic dio_pad_sleep_en_14_qs;
2971 logic dio_pad_sleep_en_14_wd;
2972 logic dio_pad_sleep_en_15_we;
2973 logic dio_pad_sleep_en_15_qs;
2974 logic dio_pad_sleep_en_15_wd;
2975 logic dio_pad_sleep_mode_0_we;
2976 logic [1:0] dio_pad_sleep_mode_0_qs;
2977 logic [1:0] dio_pad_sleep_mode_0_wd;
2978 logic dio_pad_sleep_mode_1_we;
2979 logic [1:0] dio_pad_sleep_mode_1_qs;
2980 logic [1:0] dio_pad_sleep_mode_1_wd;
2981 logic dio_pad_sleep_mode_2_we;
2982 logic [1:0] dio_pad_sleep_mode_2_qs;
2983 logic [1:0] dio_pad_sleep_mode_2_wd;
2984 logic dio_pad_sleep_mode_3_we;
2985 logic [1:0] dio_pad_sleep_mode_3_qs;
2986 logic [1:0] dio_pad_sleep_mode_3_wd;
2987 logic dio_pad_sleep_mode_4_we;
2988 logic [1:0] dio_pad_sleep_mode_4_qs;
2989 logic [1:0] dio_pad_sleep_mode_4_wd;
2990 logic dio_pad_sleep_mode_5_we;
2991 logic [1:0] dio_pad_sleep_mode_5_qs;
2992 logic [1:0] dio_pad_sleep_mode_5_wd;
2993 logic dio_pad_sleep_mode_6_we;
2994 logic [1:0] dio_pad_sleep_mode_6_qs;
2995 logic [1:0] dio_pad_sleep_mode_6_wd;
2996 logic dio_pad_sleep_mode_7_we;
2997 logic [1:0] dio_pad_sleep_mode_7_qs;
2998 logic [1:0] dio_pad_sleep_mode_7_wd;
2999 logic dio_pad_sleep_mode_8_we;
3000 logic [1:0] dio_pad_sleep_mode_8_qs;
3001 logic [1:0] dio_pad_sleep_mode_8_wd;
3002 logic dio_pad_sleep_mode_9_we;
3003 logic [1:0] dio_pad_sleep_mode_9_qs;
3004 logic [1:0] dio_pad_sleep_mode_9_wd;
3005 logic dio_pad_sleep_mode_10_we;
3006 logic [1:0] dio_pad_sleep_mode_10_qs;
3007 logic [1:0] dio_pad_sleep_mode_10_wd;
3008 logic dio_pad_sleep_mode_11_we;
3009 logic [1:0] dio_pad_sleep_mode_11_qs;
3010 logic [1:0] dio_pad_sleep_mode_11_wd;
3011 logic dio_pad_sleep_mode_12_we;
3012 logic [1:0] dio_pad_sleep_mode_12_qs;
3013 logic [1:0] dio_pad_sleep_mode_12_wd;
3014 logic dio_pad_sleep_mode_13_we;
3015 logic [1:0] dio_pad_sleep_mode_13_qs;
3016 logic [1:0] dio_pad_sleep_mode_13_wd;
3017 logic dio_pad_sleep_mode_14_we;
3018 logic [1:0] dio_pad_sleep_mode_14_qs;
3019 logic [1:0] dio_pad_sleep_mode_14_wd;
3020 logic dio_pad_sleep_mode_15_we;
3021 logic [1:0] dio_pad_sleep_mode_15_qs;
3022 logic [1:0] dio_pad_sleep_mode_15_wd;
3023 logic wkup_detector_regwen_0_we;
3024 logic wkup_detector_regwen_0_qs;
3025 logic wkup_detector_regwen_0_wd;
3026 logic wkup_detector_regwen_1_we;
3027 logic wkup_detector_regwen_1_qs;
3028 logic wkup_detector_regwen_1_wd;
3029 logic wkup_detector_regwen_2_we;
3030 logic wkup_detector_regwen_2_qs;
3031 logic wkup_detector_regwen_2_wd;
3032 logic wkup_detector_regwen_3_we;
3033 logic wkup_detector_regwen_3_qs;
3034 logic wkup_detector_regwen_3_wd;
3035 logic wkup_detector_regwen_4_we;
3036 logic wkup_detector_regwen_4_qs;
3037 logic wkup_detector_regwen_4_wd;
3038 logic wkup_detector_regwen_5_we;
3039 logic wkup_detector_regwen_5_qs;
3040 logic wkup_detector_regwen_5_wd;
3041 logic wkup_detector_regwen_6_we;
3042 logic wkup_detector_regwen_6_qs;
3043 logic wkup_detector_regwen_6_wd;
3044 logic wkup_detector_regwen_7_we;
3045 logic wkup_detector_regwen_7_qs;
3046 logic wkup_detector_regwen_7_wd;
3047 logic wkup_detector_en_0_we;
3048 logic [0:0] wkup_detector_en_0_qs;
3049 logic wkup_detector_en_0_busy;
3050 logic wkup_detector_en_1_we;
3051 logic [0:0] wkup_detector_en_1_qs;
3052 logic wkup_detector_en_1_busy;
3053 logic wkup_detector_en_2_we;
3054 logic [0:0] wkup_detector_en_2_qs;
3055 logic wkup_detector_en_2_busy;
3056 logic wkup_detector_en_3_we;
3057 logic [0:0] wkup_detector_en_3_qs;
3058 logic wkup_detector_en_3_busy;
3059 logic wkup_detector_en_4_we;
3060 logic [0:0] wkup_detector_en_4_qs;
3061 logic wkup_detector_en_4_busy;
3062 logic wkup_detector_en_5_we;
3063 logic [0:0] wkup_detector_en_5_qs;
3064 logic wkup_detector_en_5_busy;
3065 logic wkup_detector_en_6_we;
3066 logic [0:0] wkup_detector_en_6_qs;
3067 logic wkup_detector_en_6_busy;
3068 logic wkup_detector_en_7_we;
3069 logic [0:0] wkup_detector_en_7_qs;
3070 logic wkup_detector_en_7_busy;
3071 logic wkup_detector_0_we;
3072 logic [4:0] wkup_detector_0_qs;
3073 logic wkup_detector_0_busy;
3074 logic wkup_detector_1_we;
3075 logic [4:0] wkup_detector_1_qs;
3076 logic wkup_detector_1_busy;
3077 logic wkup_detector_2_we;
3078 logic [4:0] wkup_detector_2_qs;
3079 logic wkup_detector_2_busy;
3080 logic wkup_detector_3_we;
3081 logic [4:0] wkup_detector_3_qs;
3082 logic wkup_detector_3_busy;
3083 logic wkup_detector_4_we;
3084 logic [4:0] wkup_detector_4_qs;
3085 logic wkup_detector_4_busy;
3086 logic wkup_detector_5_we;
3087 logic [4:0] wkup_detector_5_qs;
3088 logic wkup_detector_5_busy;
3089 logic wkup_detector_6_we;
3090 logic [4:0] wkup_detector_6_qs;
3091 logic wkup_detector_6_busy;
3092 logic wkup_detector_7_we;
3093 logic [4:0] wkup_detector_7_qs;
3094 logic wkup_detector_7_busy;
3095 logic wkup_detector_cnt_th_0_we;
3096 logic [7:0] wkup_detector_cnt_th_0_qs;
3097 logic wkup_detector_cnt_th_0_busy;
3098 logic wkup_detector_cnt_th_1_we;
3099 logic [7:0] wkup_detector_cnt_th_1_qs;
3100 logic wkup_detector_cnt_th_1_busy;
3101 logic wkup_detector_cnt_th_2_we;
3102 logic [7:0] wkup_detector_cnt_th_2_qs;
3103 logic wkup_detector_cnt_th_2_busy;
3104 logic wkup_detector_cnt_th_3_we;
3105 logic [7:0] wkup_detector_cnt_th_3_qs;
3106 logic wkup_detector_cnt_th_3_busy;
3107 logic wkup_detector_cnt_th_4_we;
3108 logic [7:0] wkup_detector_cnt_th_4_qs;
3109 logic wkup_detector_cnt_th_4_busy;
3110 logic wkup_detector_cnt_th_5_we;
3111 logic [7:0] wkup_detector_cnt_th_5_qs;
3112 logic wkup_detector_cnt_th_5_busy;
3113 logic wkup_detector_cnt_th_6_we;
3114 logic [7:0] wkup_detector_cnt_th_6_qs;
3115 logic wkup_detector_cnt_th_6_busy;
3116 logic wkup_detector_cnt_th_7_we;
3117 logic [7:0] wkup_detector_cnt_th_7_qs;
3118 logic wkup_detector_cnt_th_7_busy;
3119 logic wkup_detector_padsel_0_we;
3120 logic [5:0] wkup_detector_padsel_0_qs;
3121 logic [5:0] wkup_detector_padsel_0_wd;
3122 logic wkup_detector_padsel_1_we;
3123 logic [5:0] wkup_detector_padsel_1_qs;
3124 logic [5:0] wkup_detector_padsel_1_wd;
3125 logic wkup_detector_padsel_2_we;
3126 logic [5:0] wkup_detector_padsel_2_qs;
3127 logic [5:0] wkup_detector_padsel_2_wd;
3128 logic wkup_detector_padsel_3_we;
3129 logic [5:0] wkup_detector_padsel_3_qs;
3130 logic [5:0] wkup_detector_padsel_3_wd;
3131 logic wkup_detector_padsel_4_we;
3132 logic [5:0] wkup_detector_padsel_4_qs;
3133 logic [5:0] wkup_detector_padsel_4_wd;
3134 logic wkup_detector_padsel_5_we;
3135 logic [5:0] wkup_detector_padsel_5_qs;
3136 logic [5:0] wkup_detector_padsel_5_wd;
3137 logic wkup_detector_padsel_6_we;
3138 logic [5:0] wkup_detector_padsel_6_qs;
3139 logic [5:0] wkup_detector_padsel_6_wd;
3140 logic wkup_detector_padsel_7_we;
3141 logic [5:0] wkup_detector_padsel_7_qs;
3142 logic [5:0] wkup_detector_padsel_7_wd;
3143 logic wkup_cause_we;
3144 logic [7:0] wkup_cause_qs;
3145 logic wkup_cause_busy;
3146 // Define register CDC handling.
3147 // CDC handling is done on a per-reg instead of per-field boundary.
3148
3149 logic aon_wkup_detector_en_0_qs_int;
3150 logic [0:0] aon_wkup_detector_en_0_qs;
3151 logic [0:0] aon_wkup_detector_en_0_wdata;
3152 logic aon_wkup_detector_en_0_we;
3153 logic unused_aon_wkup_detector_en_0_wdata;
3154 logic aon_wkup_detector_en_0_regwen;
3155
3156 always_comb begin
3157 1/1 aon_wkup_detector_en_0_qs = 1'h0;
Tests: T6 T25 T76
3158 1/1 aon_wkup_detector_en_0_qs = aon_wkup_detector_en_0_qs_int;
Tests: T6 T25 T76
3159 end
3160
3161 prim_reg_cdc #(
3162 .DataWidth(1),
3163 .ResetVal(1'h0),
3164 .BitMask(1'h1),
3165 .DstWrReq(0)
3166 ) u_wkup_detector_en_0_cdc (
3167 .clk_src_i (clk_i),
3168 .rst_src_ni (rst_ni),
3169 .clk_dst_i (clk_aon_i),
3170 .rst_dst_ni (rst_aon_ni),
3171 .src_regwen_i (wkup_detector_regwen_0_qs),
3172 .src_we_i (wkup_detector_en_0_we),
3173 .src_re_i ('0),
3174 .src_wd_i (reg_wdata[0:0]),
3175 .src_busy_o (wkup_detector_en_0_busy),
3176 .src_qs_o (wkup_detector_en_0_qs), // for software read back
3177 .dst_update_i ('0),
3178 .dst_ds_i ('0),
3179 .dst_qs_i (aon_wkup_detector_en_0_qs),
3180 .dst_we_o (aon_wkup_detector_en_0_we),
3181 .dst_re_o (),
3182 .dst_regwen_o (aon_wkup_detector_en_0_regwen),
3183 .dst_wd_o (aon_wkup_detector_en_0_wdata)
3184 );
3185 1/1 assign unused_aon_wkup_detector_en_0_wdata =
Tests: T6 T25 T76
3186 ^aon_wkup_detector_en_0_wdata;
3187
3188 logic aon_wkup_detector_en_1_qs_int;
3189 logic [0:0] aon_wkup_detector_en_1_qs;
3190 logic [0:0] aon_wkup_detector_en_1_wdata;
3191 logic aon_wkup_detector_en_1_we;
3192 logic unused_aon_wkup_detector_en_1_wdata;
3193 logic aon_wkup_detector_en_1_regwen;
3194
3195 always_comb begin
3196 0/1 ==> aon_wkup_detector_en_1_qs = 1'h0;
3197 0/1 ==> aon_wkup_detector_en_1_qs = aon_wkup_detector_en_1_qs_int;
3198 end
3199
3200 prim_reg_cdc #(
3201 .DataWidth(1),
3202 .ResetVal(1'h0),
3203 .BitMask(1'h1),
3204 .DstWrReq(0)
3205 ) u_wkup_detector_en_1_cdc (
3206 .clk_src_i (clk_i),
3207 .rst_src_ni (rst_ni),
3208 .clk_dst_i (clk_aon_i),
3209 .rst_dst_ni (rst_aon_ni),
3210 .src_regwen_i (wkup_detector_regwen_1_qs),
3211 .src_we_i (wkup_detector_en_1_we),
3212 .src_re_i ('0),
3213 .src_wd_i (reg_wdata[0:0]),
3214 .src_busy_o (wkup_detector_en_1_busy),
3215 .src_qs_o (wkup_detector_en_1_qs), // for software read back
3216 .dst_update_i ('0),
3217 .dst_ds_i ('0),
3218 .dst_qs_i (aon_wkup_detector_en_1_qs),
3219 .dst_we_o (aon_wkup_detector_en_1_we),
3220 .dst_re_o (),
3221 .dst_regwen_o (aon_wkup_detector_en_1_regwen),
3222 .dst_wd_o (aon_wkup_detector_en_1_wdata)
3223 );
3224 0/1 ==> assign unused_aon_wkup_detector_en_1_wdata =
3225 ^aon_wkup_detector_en_1_wdata;
3226
3227 logic aon_wkup_detector_en_2_qs_int;
3228 logic [0:0] aon_wkup_detector_en_2_qs;
3229 logic [0:0] aon_wkup_detector_en_2_wdata;
3230 logic aon_wkup_detector_en_2_we;
3231 logic unused_aon_wkup_detector_en_2_wdata;
3232 logic aon_wkup_detector_en_2_regwen;
3233
3234 always_comb begin
3235 0/1 ==> aon_wkup_detector_en_2_qs = 1'h0;
3236 0/1 ==> aon_wkup_detector_en_2_qs = aon_wkup_detector_en_2_qs_int;
3237 end
3238
3239 prim_reg_cdc #(
3240 .DataWidth(1),
3241 .ResetVal(1'h0),
3242 .BitMask(1'h1),
3243 .DstWrReq(0)
3244 ) u_wkup_detector_en_2_cdc (
3245 .clk_src_i (clk_i),
3246 .rst_src_ni (rst_ni),
3247 .clk_dst_i (clk_aon_i),
3248 .rst_dst_ni (rst_aon_ni),
3249 .src_regwen_i (wkup_detector_regwen_2_qs),
3250 .src_we_i (wkup_detector_en_2_we),
3251 .src_re_i ('0),
3252 .src_wd_i (reg_wdata[0:0]),
3253 .src_busy_o (wkup_detector_en_2_busy),
3254 .src_qs_o (wkup_detector_en_2_qs), // for software read back
3255 .dst_update_i ('0),
3256 .dst_ds_i ('0),
3257 .dst_qs_i (aon_wkup_detector_en_2_qs),
3258 .dst_we_o (aon_wkup_detector_en_2_we),
3259 .dst_re_o (),
3260 .dst_regwen_o (aon_wkup_detector_en_2_regwen),
3261 .dst_wd_o (aon_wkup_detector_en_2_wdata)
3262 );
3263 0/1 ==> assign unused_aon_wkup_detector_en_2_wdata =
3264 ^aon_wkup_detector_en_2_wdata;
3265
3266 logic aon_wkup_detector_en_3_qs_int;
3267 logic [0:0] aon_wkup_detector_en_3_qs;
3268 logic [0:0] aon_wkup_detector_en_3_wdata;
3269 logic aon_wkup_detector_en_3_we;
3270 logic unused_aon_wkup_detector_en_3_wdata;
3271 logic aon_wkup_detector_en_3_regwen;
3272
3273 always_comb begin
3274 1/1 aon_wkup_detector_en_3_qs = 1'h0;
Tests: T23
3275 1/1 aon_wkup_detector_en_3_qs = aon_wkup_detector_en_3_qs_int;
Tests: T23
3276 end
3277
3278 prim_reg_cdc #(
3279 .DataWidth(1),
3280 .ResetVal(1'h0),
3281 .BitMask(1'h1),
3282 .DstWrReq(0)
3283 ) u_wkup_detector_en_3_cdc (
3284 .clk_src_i (clk_i),
3285 .rst_src_ni (rst_ni),
3286 .clk_dst_i (clk_aon_i),
3287 .rst_dst_ni (rst_aon_ni),
3288 .src_regwen_i (wkup_detector_regwen_3_qs),
3289 .src_we_i (wkup_detector_en_3_we),
3290 .src_re_i ('0),
3291 .src_wd_i (reg_wdata[0:0]),
3292 .src_busy_o (wkup_detector_en_3_busy),
3293 .src_qs_o (wkup_detector_en_3_qs), // for software read back
3294 .dst_update_i ('0),
3295 .dst_ds_i ('0),
3296 .dst_qs_i (aon_wkup_detector_en_3_qs),
3297 .dst_we_o (aon_wkup_detector_en_3_we),
3298 .dst_re_o (),
3299 .dst_regwen_o (aon_wkup_detector_en_3_regwen),
3300 .dst_wd_o (aon_wkup_detector_en_3_wdata)
3301 );
3302 1/1 assign unused_aon_wkup_detector_en_3_wdata =
Tests: T23
3303 ^aon_wkup_detector_en_3_wdata;
3304
3305 logic aon_wkup_detector_en_4_qs_int;
3306 logic [0:0] aon_wkup_detector_en_4_qs;
3307 logic [0:0] aon_wkup_detector_en_4_wdata;
3308 logic aon_wkup_detector_en_4_we;
3309 logic unused_aon_wkup_detector_en_4_wdata;
3310 logic aon_wkup_detector_en_4_regwen;
3311
3312 always_comb begin
3313 0/1 ==> aon_wkup_detector_en_4_qs = 1'h0;
3314 0/1 ==> aon_wkup_detector_en_4_qs = aon_wkup_detector_en_4_qs_int;
3315 end
3316
3317 prim_reg_cdc #(
3318 .DataWidth(1),
3319 .ResetVal(1'h0),
3320 .BitMask(1'h1),
3321 .DstWrReq(0)
3322 ) u_wkup_detector_en_4_cdc (
3323 .clk_src_i (clk_i),
3324 .rst_src_ni (rst_ni),
3325 .clk_dst_i (clk_aon_i),
3326 .rst_dst_ni (rst_aon_ni),
3327 .src_regwen_i (wkup_detector_regwen_4_qs),
3328 .src_we_i (wkup_detector_en_4_we),
3329 .src_re_i ('0),
3330 .src_wd_i (reg_wdata[0:0]),
3331 .src_busy_o (wkup_detector_en_4_busy),
3332 .src_qs_o (wkup_detector_en_4_qs), // for software read back
3333 .dst_update_i ('0),
3334 .dst_ds_i ('0),
3335 .dst_qs_i (aon_wkup_detector_en_4_qs),
3336 .dst_we_o (aon_wkup_detector_en_4_we),
3337 .dst_re_o (),
3338 .dst_regwen_o (aon_wkup_detector_en_4_regwen),
3339 .dst_wd_o (aon_wkup_detector_en_4_wdata)
3340 );
3341 0/1 ==> assign unused_aon_wkup_detector_en_4_wdata =
3342 ^aon_wkup_detector_en_4_wdata;
3343
3344 logic aon_wkup_detector_en_5_qs_int;
3345 logic [0:0] aon_wkup_detector_en_5_qs;
3346 logic [0:0] aon_wkup_detector_en_5_wdata;
3347 logic aon_wkup_detector_en_5_we;
3348 logic unused_aon_wkup_detector_en_5_wdata;
3349 logic aon_wkup_detector_en_5_regwen;
3350
3351 always_comb begin
3352 1/1 aon_wkup_detector_en_5_qs = 1'h0;
Tests: T77 T78 T79
3353 1/1 aon_wkup_detector_en_5_qs = aon_wkup_detector_en_5_qs_int;
Tests: T77 T78 T79
3354 end
3355
3356 prim_reg_cdc #(
3357 .DataWidth(1),
3358 .ResetVal(1'h0),
3359 .BitMask(1'h1),
3360 .DstWrReq(0)
3361 ) u_wkup_detector_en_5_cdc (
3362 .clk_src_i (clk_i),
3363 .rst_src_ni (rst_ni),
3364 .clk_dst_i (clk_aon_i),
3365 .rst_dst_ni (rst_aon_ni),
3366 .src_regwen_i (wkup_detector_regwen_5_qs),
3367 .src_we_i (wkup_detector_en_5_we),
3368 .src_re_i ('0),
3369 .src_wd_i (reg_wdata[0:0]),
3370 .src_busy_o (wkup_detector_en_5_busy),
3371 .src_qs_o (wkup_detector_en_5_qs), // for software read back
3372 .dst_update_i ('0),
3373 .dst_ds_i ('0),
3374 .dst_qs_i (aon_wkup_detector_en_5_qs),
3375 .dst_we_o (aon_wkup_detector_en_5_we),
3376 .dst_re_o (),
3377 .dst_regwen_o (aon_wkup_detector_en_5_regwen),
3378 .dst_wd_o (aon_wkup_detector_en_5_wdata)
3379 );
3380 1/1 assign unused_aon_wkup_detector_en_5_wdata =
Tests: T77 T78 T79
3381 ^aon_wkup_detector_en_5_wdata;
3382
3383 logic aon_wkup_detector_en_6_qs_int;
3384 logic [0:0] aon_wkup_detector_en_6_qs;
3385 logic [0:0] aon_wkup_detector_en_6_wdata;
3386 logic aon_wkup_detector_en_6_we;
3387 logic unused_aon_wkup_detector_en_6_wdata;
3388 logic aon_wkup_detector_en_6_regwen;
3389
3390 always_comb begin
3391 0/1 ==> aon_wkup_detector_en_6_qs = 1'h0;
3392 0/1 ==> aon_wkup_detector_en_6_qs = aon_wkup_detector_en_6_qs_int;
3393 end
3394
3395 prim_reg_cdc #(
3396 .DataWidth(1),
3397 .ResetVal(1'h0),
3398 .BitMask(1'h1),
3399 .DstWrReq(0)
3400 ) u_wkup_detector_en_6_cdc (
3401 .clk_src_i (clk_i),
3402 .rst_src_ni (rst_ni),
3403 .clk_dst_i (clk_aon_i),
3404 .rst_dst_ni (rst_aon_ni),
3405 .src_regwen_i (wkup_detector_regwen_6_qs),
3406 .src_we_i (wkup_detector_en_6_we),
3407 .src_re_i ('0),
3408 .src_wd_i (reg_wdata[0:0]),
3409 .src_busy_o (wkup_detector_en_6_busy),
3410 .src_qs_o (wkup_detector_en_6_qs), // for software read back
3411 .dst_update_i ('0),
3412 .dst_ds_i ('0),
3413 .dst_qs_i (aon_wkup_detector_en_6_qs),
3414 .dst_we_o (aon_wkup_detector_en_6_we),
3415 .dst_re_o (),
3416 .dst_regwen_o (aon_wkup_detector_en_6_regwen),
3417 .dst_wd_o (aon_wkup_detector_en_6_wdata)
3418 );
3419 0/1 ==> assign unused_aon_wkup_detector_en_6_wdata =
3420 ^aon_wkup_detector_en_6_wdata;
3421
3422 logic aon_wkup_detector_en_7_qs_int;
3423 logic [0:0] aon_wkup_detector_en_7_qs;
3424 logic [0:0] aon_wkup_detector_en_7_wdata;
3425 logic aon_wkup_detector_en_7_we;
3426 logic unused_aon_wkup_detector_en_7_wdata;
3427 logic aon_wkup_detector_en_7_regwen;
3428
3429 always_comb begin
3430 1/1 aon_wkup_detector_en_7_qs = 1'h0;
Tests: T4 T24
3431 1/1 aon_wkup_detector_en_7_qs = aon_wkup_detector_en_7_qs_int;
Tests: T4 T24
3432 end
3433
3434 prim_reg_cdc #(
3435 .DataWidth(1),
3436 .ResetVal(1'h0),
3437 .BitMask(1'h1),
3438 .DstWrReq(0)
3439 ) u_wkup_detector_en_7_cdc (
3440 .clk_src_i (clk_i),
3441 .rst_src_ni (rst_ni),
3442 .clk_dst_i (clk_aon_i),
3443 .rst_dst_ni (rst_aon_ni),
3444 .src_regwen_i (wkup_detector_regwen_7_qs),
3445 .src_we_i (wkup_detector_en_7_we),
3446 .src_re_i ('0),
3447 .src_wd_i (reg_wdata[0:0]),
3448 .src_busy_o (wkup_detector_en_7_busy),
3449 .src_qs_o (wkup_detector_en_7_qs), // for software read back
3450 .dst_update_i ('0),
3451 .dst_ds_i ('0),
3452 .dst_qs_i (aon_wkup_detector_en_7_qs),
3453 .dst_we_o (aon_wkup_detector_en_7_we),
3454 .dst_re_o (),
3455 .dst_regwen_o (aon_wkup_detector_en_7_regwen),
3456 .dst_wd_o (aon_wkup_detector_en_7_wdata)
3457 );
3458 1/1 assign unused_aon_wkup_detector_en_7_wdata =
Tests: T4 T24
3459 ^aon_wkup_detector_en_7_wdata;
3460
3461 logic [2:0] aon_wkup_detector_0_mode_0_qs_int;
3462 logic aon_wkup_detector_0_filter_0_qs_int;
3463 logic aon_wkup_detector_0_miodio_0_qs_int;
3464 logic [4:0] aon_wkup_detector_0_qs;
3465 logic [4:0] aon_wkup_detector_0_wdata;
3466 logic aon_wkup_detector_0_we;
3467 logic unused_aon_wkup_detector_0_wdata;
3468 logic aon_wkup_detector_0_regwen;
3469
3470 always_comb begin
3471 1/1 aon_wkup_detector_0_qs = 5'h0;
Tests: T6 T84 T85
3472 1/1 aon_wkup_detector_0_qs[2:0] = aon_wkup_detector_0_mode_0_qs_int;
Tests: T6 T84 T85
3473 1/1 aon_wkup_detector_0_qs[3] = aon_wkup_detector_0_filter_0_qs_int;
Tests: T6 T84 T85
3474 1/1 aon_wkup_detector_0_qs[4] = aon_wkup_detector_0_miodio_0_qs_int;
Tests: T6 T84 T85
3475 end
3476
3477 prim_reg_cdc #(
3478 .DataWidth(5),
3479 .ResetVal(5'h0),
3480 .BitMask(5'h1f),
3481 .DstWrReq(0)
3482 ) u_wkup_detector_0_cdc (
3483 .clk_src_i (clk_i),
3484 .rst_src_ni (rst_ni),
3485 .clk_dst_i (clk_aon_i),
3486 .rst_dst_ni (rst_aon_ni),
3487 .src_regwen_i (wkup_detector_regwen_0_qs),
3488 .src_we_i (wkup_detector_0_we),
3489 .src_re_i ('0),
3490 .src_wd_i (reg_wdata[4:0]),
3491 .src_busy_o (wkup_detector_0_busy),
3492 .src_qs_o (wkup_detector_0_qs), // for software read back
3493 .dst_update_i ('0),
3494 .dst_ds_i ('0),
3495 .dst_qs_i (aon_wkup_detector_0_qs),
3496 .dst_we_o (aon_wkup_detector_0_we),
3497 .dst_re_o (),
3498 .dst_regwen_o (aon_wkup_detector_0_regwen),
3499 .dst_wd_o (aon_wkup_detector_0_wdata)
3500 );
3501 1/1 assign unused_aon_wkup_detector_0_wdata =
Tests: T6 T84 T85
3502 ^aon_wkup_detector_0_wdata;
3503
3504 logic [2:0] aon_wkup_detector_1_mode_1_qs_int;
3505 logic aon_wkup_detector_1_filter_1_qs_int;
3506 logic aon_wkup_detector_1_miodio_1_qs_int;
3507 logic [4:0] aon_wkup_detector_1_qs;
3508 logic [4:0] aon_wkup_detector_1_wdata;
3509 logic aon_wkup_detector_1_we;
3510 logic unused_aon_wkup_detector_1_wdata;
3511 logic aon_wkup_detector_1_regwen;
3512
3513 always_comb begin
3514 1/1 aon_wkup_detector_1_qs = 5'h0;
Tests: T177 T188 T401
3515 1/1 aon_wkup_detector_1_qs[2:0] = aon_wkup_detector_1_mode_1_qs_int;
Tests: T177 T188 T401
3516 1/1 aon_wkup_detector_1_qs[3] = aon_wkup_detector_1_filter_1_qs_int;
Tests: T177 T188 T401
3517 1/1 aon_wkup_detector_1_qs[4] = aon_wkup_detector_1_miodio_1_qs_int;
Tests: T177 T188 T401
3518 end
3519
3520 prim_reg_cdc #(
3521 .DataWidth(5),
3522 .ResetVal(5'h0),
3523 .BitMask(5'h1f),
3524 .DstWrReq(0)
3525 ) u_wkup_detector_1_cdc (
3526 .clk_src_i (clk_i),
3527 .rst_src_ni (rst_ni),
3528 .clk_dst_i (clk_aon_i),
3529 .rst_dst_ni (rst_aon_ni),
3530 .src_regwen_i (wkup_detector_regwen_1_qs),
3531 .src_we_i (wkup_detector_1_we),
3532 .src_re_i ('0),
3533 .src_wd_i (reg_wdata[4:0]),
3534 .src_busy_o (wkup_detector_1_busy),
3535 .src_qs_o (wkup_detector_1_qs), // for software read back
3536 .dst_update_i ('0),
3537 .dst_ds_i ('0),
3538 .dst_qs_i (aon_wkup_detector_1_qs),
3539 .dst_we_o (aon_wkup_detector_1_we),
3540 .dst_re_o (),
3541 .dst_regwen_o (aon_wkup_detector_1_regwen),
3542 .dst_wd_o (aon_wkup_detector_1_wdata)
3543 );
3544 1/1 assign unused_aon_wkup_detector_1_wdata =
Tests: T177 T179 T188
3545 ^aon_wkup_detector_1_wdata;
3546
3547 logic [2:0] aon_wkup_detector_2_mode_2_qs_int;
3548 logic aon_wkup_detector_2_filter_2_qs_int;
3549 logic aon_wkup_detector_2_miodio_2_qs_int;
3550 logic [4:0] aon_wkup_detector_2_qs;
3551 logic [4:0] aon_wkup_detector_2_wdata;
3552 logic aon_wkup_detector_2_we;
3553 logic unused_aon_wkup_detector_2_wdata;
3554 logic aon_wkup_detector_2_regwen;
3555
3556 always_comb begin
3557 1/1 aon_wkup_detector_2_qs = 5'h0;
Tests: T188 T401 T180
3558 1/1 aon_wkup_detector_2_qs[2:0] = aon_wkup_detector_2_mode_2_qs_int;
Tests: T188 T401 T180
3559 1/1 aon_wkup_detector_2_qs[3] = aon_wkup_detector_2_filter_2_qs_int;
Tests: T188 T401 T180
3560 1/1 aon_wkup_detector_2_qs[4] = aon_wkup_detector_2_miodio_2_qs_int;
Tests: T188 T401 T180
3561 end
3562
3563 prim_reg_cdc #(
3564 .DataWidth(5),
3565 .ResetVal(5'h0),
3566 .BitMask(5'h1f),
3567 .DstWrReq(0)
3568 ) u_wkup_detector_2_cdc (
3569 .clk_src_i (clk_i),
3570 .rst_src_ni (rst_ni),
3571 .clk_dst_i (clk_aon_i),
3572 .rst_dst_ni (rst_aon_ni),
3573 .src_regwen_i (wkup_detector_regwen_2_qs),
3574 .src_we_i (wkup_detector_2_we),
3575 .src_re_i ('0),
3576 .src_wd_i (reg_wdata[4:0]),
3577 .src_busy_o (wkup_detector_2_busy),
3578 .src_qs_o (wkup_detector_2_qs), // for software read back
3579 .dst_update_i ('0),
3580 .dst_ds_i ('0),
3581 .dst_qs_i (aon_wkup_detector_2_qs),
3582 .dst_we_o (aon_wkup_detector_2_we),
3583 .dst_re_o (),
3584 .dst_regwen_o (aon_wkup_detector_2_regwen),
3585 .dst_wd_o (aon_wkup_detector_2_wdata)
3586 );
3587 1/1 assign unused_aon_wkup_detector_2_wdata =
Tests: T177 T179 T188
3588 ^aon_wkup_detector_2_wdata;
3589
3590 logic [2:0] aon_wkup_detector_3_mode_3_qs_int;
3591 logic aon_wkup_detector_3_filter_3_qs_int;
3592 logic aon_wkup_detector_3_miodio_3_qs_int;
3593 logic [4:0] aon_wkup_detector_3_qs;
3594 logic [4:0] aon_wkup_detector_3_wdata;
3595 logic aon_wkup_detector_3_we;
3596 logic unused_aon_wkup_detector_3_wdata;
3597 logic aon_wkup_detector_3_regwen;
3598
3599 always_comb begin
3600 1/1 aon_wkup_detector_3_qs = 5'h0;
Tests: T23 T177 T188
3601 1/1 aon_wkup_detector_3_qs[2:0] = aon_wkup_detector_3_mode_3_qs_int;
Tests: T23 T177 T188
3602 1/1 aon_wkup_detector_3_qs[3] = aon_wkup_detector_3_filter_3_qs_int;
Tests: T23 T177 T188
3603 1/1 aon_wkup_detector_3_qs[4] = aon_wkup_detector_3_miodio_3_qs_int;
Tests: T23 T177 T188
3604 end
3605
3606 prim_reg_cdc #(
3607 .DataWidth(5),
3608 .ResetVal(5'h0),
3609 .BitMask(5'h1f),
3610 .DstWrReq(0)
3611 ) u_wkup_detector_3_cdc (
3612 .clk_src_i (clk_i),
3613 .rst_src_ni (rst_ni),
3614 .clk_dst_i (clk_aon_i),
3615 .rst_dst_ni (rst_aon_ni),
3616 .src_regwen_i (wkup_detector_regwen_3_qs),
3617 .src_we_i (wkup_detector_3_we),
3618 .src_re_i ('0),
3619 .src_wd_i (reg_wdata[4:0]),
3620 .src_busy_o (wkup_detector_3_busy),
3621 .src_qs_o (wkup_detector_3_qs), // for software read back
3622 .dst_update_i ('0),
3623 .dst_ds_i ('0),
3624 .dst_qs_i (aon_wkup_detector_3_qs),
3625 .dst_we_o (aon_wkup_detector_3_we),
3626 .dst_re_o (),
3627 .dst_regwen_o (aon_wkup_detector_3_regwen),
3628 .dst_wd_o (aon_wkup_detector_3_wdata)
3629 );
3630 1/1 assign unused_aon_wkup_detector_3_wdata =
Tests: T23 T177 T179
3631 ^aon_wkup_detector_3_wdata;
3632
3633 logic [2:0] aon_wkup_detector_4_mode_4_qs_int;
3634 logic aon_wkup_detector_4_filter_4_qs_int;
3635 logic aon_wkup_detector_4_miodio_4_qs_int;
3636 logic [4:0] aon_wkup_detector_4_qs;
3637 logic [4:0] aon_wkup_detector_4_wdata;
3638 logic aon_wkup_detector_4_we;
3639 logic unused_aon_wkup_detector_4_wdata;
3640 logic aon_wkup_detector_4_regwen;
3641
3642 always_comb begin
3643 1/1 aon_wkup_detector_4_qs = 5'h0;
Tests: T177 T188 T401
3644 1/1 aon_wkup_detector_4_qs[2:0] = aon_wkup_detector_4_mode_4_qs_int;
Tests: T177 T188 T401
3645 1/1 aon_wkup_detector_4_qs[3] = aon_wkup_detector_4_filter_4_qs_int;
Tests: T177 T188 T401
3646 1/1 aon_wkup_detector_4_qs[4] = aon_wkup_detector_4_miodio_4_qs_int;
Tests: T177 T188 T401
3647 end
3648
3649 prim_reg_cdc #(
3650 .DataWidth(5),
3651 .ResetVal(5'h0),
3652 .BitMask(5'h1f),
3653 .DstWrReq(0)
3654 ) u_wkup_detector_4_cdc (
3655 .clk_src_i (clk_i),
3656 .rst_src_ni (rst_ni),
3657 .clk_dst_i (clk_aon_i),
3658 .rst_dst_ni (rst_aon_ni),
3659 .src_regwen_i (wkup_detector_regwen_4_qs),
3660 .src_we_i (wkup_detector_4_we),
3661 .src_re_i ('0),
3662 .src_wd_i (reg_wdata[4:0]),
3663 .src_busy_o (wkup_detector_4_busy),
3664 .src_qs_o (wkup_detector_4_qs), // for software read back
3665 .dst_update_i ('0),
3666 .dst_ds_i ('0),
3667 .dst_qs_i (aon_wkup_detector_4_qs),
3668 .dst_we_o (aon_wkup_detector_4_we),
3669 .dst_re_o (),
3670 .dst_regwen_o (aon_wkup_detector_4_regwen),
3671 .dst_wd_o (aon_wkup_detector_4_wdata)
3672 );
3673 1/1 assign unused_aon_wkup_detector_4_wdata =
Tests: T177 T179 T188
3674 ^aon_wkup_detector_4_wdata;
3675
3676 logic [2:0] aon_wkup_detector_5_mode_5_qs_int;
3677 logic aon_wkup_detector_5_filter_5_qs_int;
3678 logic aon_wkup_detector_5_miodio_5_qs_int;
3679 logic [4:0] aon_wkup_detector_5_qs;
3680 logic [4:0] aon_wkup_detector_5_wdata;
3681 logic aon_wkup_detector_5_we;
3682 logic unused_aon_wkup_detector_5_wdata;
3683 logic aon_wkup_detector_5_regwen;
3684
3685 always_comb begin
3686 1/1 aon_wkup_detector_5_qs = 5'h0;
Tests: T177 T179 T188
3687 1/1 aon_wkup_detector_5_qs[2:0] = aon_wkup_detector_5_mode_5_qs_int;
Tests: T177 T179 T188
3688 1/1 aon_wkup_detector_5_qs[3] = aon_wkup_detector_5_filter_5_qs_int;
Tests: T177 T179 T188
3689 1/1 aon_wkup_detector_5_qs[4] = aon_wkup_detector_5_miodio_5_qs_int;
Tests: T177 T179 T188
3690 end
3691
3692 prim_reg_cdc #(
3693 .DataWidth(5),
3694 .ResetVal(5'h0),
3695 .BitMask(5'h1f),
3696 .DstWrReq(0)
3697 ) u_wkup_detector_5_cdc (
3698 .clk_src_i (clk_i),
3699 .rst_src_ni (rst_ni),
3700 .clk_dst_i (clk_aon_i),
3701 .rst_dst_ni (rst_aon_ni),
3702 .src_regwen_i (wkup_detector_regwen_5_qs),
3703 .src_we_i (wkup_detector_5_we),
3704 .src_re_i ('0),
3705 .src_wd_i (reg_wdata[4:0]),
3706 .src_busy_o (wkup_detector_5_busy),
3707 .src_qs_o (wkup_detector_5_qs), // for software read back
3708 .dst_update_i ('0),
3709 .dst_ds_i ('0),
3710 .dst_qs_i (aon_wkup_detector_5_qs),
3711 .dst_we_o (aon_wkup_detector_5_we),
3712 .dst_re_o (),
3713 .dst_regwen_o (aon_wkup_detector_5_regwen),
3714 .dst_wd_o (aon_wkup_detector_5_wdata)
3715 );
3716 1/1 assign unused_aon_wkup_detector_5_wdata =
Tests: T177 T179 T188
3717 ^aon_wkup_detector_5_wdata;
3718
3719 logic [2:0] aon_wkup_detector_6_mode_6_qs_int;
3720 logic aon_wkup_detector_6_filter_6_qs_int;
3721 logic aon_wkup_detector_6_miodio_6_qs_int;
3722 logic [4:0] aon_wkup_detector_6_qs;
3723 logic [4:0] aon_wkup_detector_6_wdata;
3724 logic aon_wkup_detector_6_we;
3725 logic unused_aon_wkup_detector_6_wdata;
3726 logic aon_wkup_detector_6_regwen;
3727
3728 always_comb begin
3729 1/1 aon_wkup_detector_6_qs = 5'h0;
Tests: T177 T179 T188
3730 1/1 aon_wkup_detector_6_qs[2:0] = aon_wkup_detector_6_mode_6_qs_int;
Tests: T177 T179 T188
3731 1/1 aon_wkup_detector_6_qs[3] = aon_wkup_detector_6_filter_6_qs_int;
Tests: T177 T179 T188
3732 1/1 aon_wkup_detector_6_qs[4] = aon_wkup_detector_6_miodio_6_qs_int;
Tests: T177 T179 T188
3733 end
3734
3735 prim_reg_cdc #(
3736 .DataWidth(5),
3737 .ResetVal(5'h0),
3738 .BitMask(5'h1f),
3739 .DstWrReq(0)
3740 ) u_wkup_detector_6_cdc (
3741 .clk_src_i (clk_i),
3742 .rst_src_ni (rst_ni),
3743 .clk_dst_i (clk_aon_i),
3744 .rst_dst_ni (rst_aon_ni),
3745 .src_regwen_i (wkup_detector_regwen_6_qs),
3746 .src_we_i (wkup_detector_6_we),
3747 .src_re_i ('0),
3748 .src_wd_i (reg_wdata[4:0]),
3749 .src_busy_o (wkup_detector_6_busy),
3750 .src_qs_o (wkup_detector_6_qs), // for software read back
3751 .dst_update_i ('0),
3752 .dst_ds_i ('0),
3753 .dst_qs_i (aon_wkup_detector_6_qs),
3754 .dst_we_o (aon_wkup_detector_6_we),
3755 .dst_re_o (),
3756 .dst_regwen_o (aon_wkup_detector_6_regwen),
3757 .dst_wd_o (aon_wkup_detector_6_wdata)
3758 );
3759 1/1 assign unused_aon_wkup_detector_6_wdata =
Tests: T177 T179 T188
3760 ^aon_wkup_detector_6_wdata;
3761
3762 logic [2:0] aon_wkup_detector_7_mode_7_qs_int;
3763 logic aon_wkup_detector_7_filter_7_qs_int;
3764 logic aon_wkup_detector_7_miodio_7_qs_int;
3765 logic [4:0] aon_wkup_detector_7_qs;
3766 logic [4:0] aon_wkup_detector_7_wdata;
3767 logic aon_wkup_detector_7_we;
3768 logic unused_aon_wkup_detector_7_wdata;
3769 logic aon_wkup_detector_7_regwen;
3770
3771 always_comb begin
3772 1/1 aon_wkup_detector_7_qs = 5'h0;
Tests: T177 T179 T188
3773 1/1 aon_wkup_detector_7_qs[2:0] = aon_wkup_detector_7_mode_7_qs_int;
Tests: T177 T179 T188
3774 1/1 aon_wkup_detector_7_qs[3] = aon_wkup_detector_7_filter_7_qs_int;
Tests: T177 T179 T188
3775 1/1 aon_wkup_detector_7_qs[4] = aon_wkup_detector_7_miodio_7_qs_int;
Tests: T177 T179 T188
3776 end
3777
3778 prim_reg_cdc #(
3779 .DataWidth(5),
3780 .ResetVal(5'h0),
3781 .BitMask(5'h1f),
3782 .DstWrReq(0)
3783 ) u_wkup_detector_7_cdc (
3784 .clk_src_i (clk_i),
3785 .rst_src_ni (rst_ni),
3786 .clk_dst_i (clk_aon_i),
3787 .rst_dst_ni (rst_aon_ni),
3788 .src_regwen_i (wkup_detector_regwen_7_qs),
3789 .src_we_i (wkup_detector_7_we),
3790 .src_re_i ('0),
3791 .src_wd_i (reg_wdata[4:0]),
3792 .src_busy_o (wkup_detector_7_busy),
3793 .src_qs_o (wkup_detector_7_qs), // for software read back
3794 .dst_update_i ('0),
3795 .dst_ds_i ('0),
3796 .dst_qs_i (aon_wkup_detector_7_qs),
3797 .dst_we_o (aon_wkup_detector_7_we),
3798 .dst_re_o (),
3799 .dst_regwen_o (aon_wkup_detector_7_regwen),
3800 .dst_wd_o (aon_wkup_detector_7_wdata)
3801 );
3802 1/1 assign unused_aon_wkup_detector_7_wdata =
Tests: T177 T179 T188
3803 ^aon_wkup_detector_7_wdata;
3804
3805 logic [7:0] aon_wkup_detector_cnt_th_0_qs_int;
3806 logic [7:0] aon_wkup_detector_cnt_th_0_qs;
3807 logic [7:0] aon_wkup_detector_cnt_th_0_wdata;
3808 logic aon_wkup_detector_cnt_th_0_we;
3809 logic unused_aon_wkup_detector_cnt_th_0_wdata;
3810 logic aon_wkup_detector_cnt_th_0_regwen;
3811
3812 always_comb begin
3813 1/1 aon_wkup_detector_cnt_th_0_qs = 8'h0;
Tests: T177 T179 T188
3814 1/1 aon_wkup_detector_cnt_th_0_qs = aon_wkup_detector_cnt_th_0_qs_int;
Tests: T177 T179 T188
3815 end
3816
3817 prim_reg_cdc #(
3818 .DataWidth(8),
3819 .ResetVal(8'h0),
3820 .BitMask(8'hff),
3821 .DstWrReq(0)
3822 ) u_wkup_detector_cnt_th_0_cdc (
3823 .clk_src_i (clk_i),
3824 .rst_src_ni (rst_ni),
3825 .clk_dst_i (clk_aon_i),
3826 .rst_dst_ni (rst_aon_ni),
3827 .src_regwen_i (wkup_detector_regwen_0_qs),
3828 .src_we_i (wkup_detector_cnt_th_0_we),
3829 .src_re_i ('0),
3830 .src_wd_i (reg_wdata[7:0]),
3831 .src_busy_o (wkup_detector_cnt_th_0_busy),
3832 .src_qs_o (wkup_detector_cnt_th_0_qs), // for software read back
3833 .dst_update_i ('0),
3834 .dst_ds_i ('0),
3835 .dst_qs_i (aon_wkup_detector_cnt_th_0_qs),
3836 .dst_we_o (aon_wkup_detector_cnt_th_0_we),
3837 .dst_re_o (),
3838 .dst_regwen_o (aon_wkup_detector_cnt_th_0_regwen),
3839 .dst_wd_o (aon_wkup_detector_cnt_th_0_wdata)
3840 );
3841 1/1 assign unused_aon_wkup_detector_cnt_th_0_wdata =
Tests: T177 T179 T188
3842 ^aon_wkup_detector_cnt_th_0_wdata;
3843
3844 logic [7:0] aon_wkup_detector_cnt_th_1_qs_int;
3845 logic [7:0] aon_wkup_detector_cnt_th_1_qs;
3846 logic [7:0] aon_wkup_detector_cnt_th_1_wdata;
3847 logic aon_wkup_detector_cnt_th_1_we;
3848 logic unused_aon_wkup_detector_cnt_th_1_wdata;
3849 logic aon_wkup_detector_cnt_th_1_regwen;
3850
3851 always_comb begin
3852 1/1 aon_wkup_detector_cnt_th_1_qs = 8'h0;
Tests: T91 T126 T127
3853 1/1 aon_wkup_detector_cnt_th_1_qs = aon_wkup_detector_cnt_th_1_qs_int;
Tests: T91 T126 T127
3854 end
3855
3856 prim_reg_cdc #(
3857 .DataWidth(8),
3858 .ResetVal(8'h0),
3859 .BitMask(8'hff),
3860 .DstWrReq(0)
3861 ) u_wkup_detector_cnt_th_1_cdc (
3862 .clk_src_i (clk_i),
3863 .rst_src_ni (rst_ni),
3864 .clk_dst_i (clk_aon_i),
3865 .rst_dst_ni (rst_aon_ni),
3866 .src_regwen_i (wkup_detector_regwen_1_qs),
3867 .src_we_i (wkup_detector_cnt_th_1_we),
3868 .src_re_i ('0),
3869 .src_wd_i (reg_wdata[7:0]),
3870 .src_busy_o (wkup_detector_cnt_th_1_busy),
3871 .src_qs_o (wkup_detector_cnt_th_1_qs), // for software read back
3872 .dst_update_i ('0),
3873 .dst_ds_i ('0),
3874 .dst_qs_i (aon_wkup_detector_cnt_th_1_qs),
3875 .dst_we_o (aon_wkup_detector_cnt_th_1_we),
3876 .dst_re_o (),
3877 .dst_regwen_o (aon_wkup_detector_cnt_th_1_regwen),
3878 .dst_wd_o (aon_wkup_detector_cnt_th_1_wdata)
3879 );
3880 1/1 assign unused_aon_wkup_detector_cnt_th_1_wdata =
Tests: T91 T126 T127
3881 ^aon_wkup_detector_cnt_th_1_wdata;
3882
3883 logic [7:0] aon_wkup_detector_cnt_th_2_qs_int;
3884 logic [7:0] aon_wkup_detector_cnt_th_2_qs;
3885 logic [7:0] aon_wkup_detector_cnt_th_2_wdata;
3886 logic aon_wkup_detector_cnt_th_2_we;
3887 logic unused_aon_wkup_detector_cnt_th_2_wdata;
3888 logic aon_wkup_detector_cnt_th_2_regwen;
3889
3890 always_comb begin
3891 1/1 aon_wkup_detector_cnt_th_2_qs = 8'h0;
Tests: T401 T180 T189
3892 1/1 aon_wkup_detector_cnt_th_2_qs = aon_wkup_detector_cnt_th_2_qs_int;
Tests: T401 T180 T189
3893 end
3894
3895 prim_reg_cdc #(
3896 .DataWidth(8),
3897 .ResetVal(8'h0),
3898 .BitMask(8'hff),
3899 .DstWrReq(0)
3900 ) u_wkup_detector_cnt_th_2_cdc (
3901 .clk_src_i (clk_i),
3902 .rst_src_ni (rst_ni),
3903 .clk_dst_i (clk_aon_i),
3904 .rst_dst_ni (rst_aon_ni),
3905 .src_regwen_i (wkup_detector_regwen_2_qs),
3906 .src_we_i (wkup_detector_cnt_th_2_we),
3907 .src_re_i ('0),
3908 .src_wd_i (reg_wdata[7:0]),
3909 .src_busy_o (wkup_detector_cnt_th_2_busy),
3910 .src_qs_o (wkup_detector_cnt_th_2_qs), // for software read back
3911 .dst_update_i ('0),
3912 .dst_ds_i ('0),
3913 .dst_qs_i (aon_wkup_detector_cnt_th_2_qs),
3914 .dst_we_o (aon_wkup_detector_cnt_th_2_we),
3915 .dst_re_o (),
3916 .dst_regwen_o (aon_wkup_detector_cnt_th_2_regwen),
3917 .dst_wd_o (aon_wkup_detector_cnt_th_2_wdata)
3918 );
3919 1/1 assign unused_aon_wkup_detector_cnt_th_2_wdata =
Tests: T177 T179 T188
3920 ^aon_wkup_detector_cnt_th_2_wdata;
3921
3922 logic [7:0] aon_wkup_detector_cnt_th_3_qs_int;
3923 logic [7:0] aon_wkup_detector_cnt_th_3_qs;
3924 logic [7:0] aon_wkup_detector_cnt_th_3_wdata;
3925 logic aon_wkup_detector_cnt_th_3_we;
3926 logic unused_aon_wkup_detector_cnt_th_3_wdata;
3927 logic aon_wkup_detector_cnt_th_3_regwen;
3928
3929 always_comb begin
3930 1/1 aon_wkup_detector_cnt_th_3_qs = 8'h0;
Tests: T177 T188 T401
3931 1/1 aon_wkup_detector_cnt_th_3_qs = aon_wkup_detector_cnt_th_3_qs_int;
Tests: T177 T188 T401
3932 end
3933
3934 prim_reg_cdc #(
3935 .DataWidth(8),
3936 .ResetVal(8'h0),
3937 .BitMask(8'hff),
3938 .DstWrReq(0)
3939 ) u_wkup_detector_cnt_th_3_cdc (
3940 .clk_src_i (clk_i),
3941 .rst_src_ni (rst_ni),
3942 .clk_dst_i (clk_aon_i),
3943 .rst_dst_ni (rst_aon_ni),
3944 .src_regwen_i (wkup_detector_regwen_3_qs),
3945 .src_we_i (wkup_detector_cnt_th_3_we),
3946 .src_re_i ('0),
3947 .src_wd_i (reg_wdata[7:0]),
3948 .src_busy_o (wkup_detector_cnt_th_3_busy),
3949 .src_qs_o (wkup_detector_cnt_th_3_qs), // for software read back
3950 .dst_update_i ('0),
3951 .dst_ds_i ('0),
3952 .dst_qs_i (aon_wkup_detector_cnt_th_3_qs),
3953 .dst_we_o (aon_wkup_detector_cnt_th_3_we),
3954 .dst_re_o (),
3955 .dst_regwen_o (aon_wkup_detector_cnt_th_3_regwen),
3956 .dst_wd_o (aon_wkup_detector_cnt_th_3_wdata)
3957 );
3958 1/1 assign unused_aon_wkup_detector_cnt_th_3_wdata =
Tests: T177 T179 T188
3959 ^aon_wkup_detector_cnt_th_3_wdata;
3960
3961 logic [7:0] aon_wkup_detector_cnt_th_4_qs_int;
3962 logic [7:0] aon_wkup_detector_cnt_th_4_qs;
3963 logic [7:0] aon_wkup_detector_cnt_th_4_wdata;
3964 logic aon_wkup_detector_cnt_th_4_we;
3965 logic unused_aon_wkup_detector_cnt_th_4_wdata;
3966 logic aon_wkup_detector_cnt_th_4_regwen;
3967
3968 always_comb begin
3969 1/1 aon_wkup_detector_cnt_th_4_qs = 8'h0;
Tests: T177 T179 T188
3970 1/1 aon_wkup_detector_cnt_th_4_qs = aon_wkup_detector_cnt_th_4_qs_int;
Tests: T177 T179 T188
3971 end
3972
3973 prim_reg_cdc #(
3974 .DataWidth(8),
3975 .ResetVal(8'h0),
3976 .BitMask(8'hff),
3977 .DstWrReq(0)
3978 ) u_wkup_detector_cnt_th_4_cdc (
3979 .clk_src_i (clk_i),
3980 .rst_src_ni (rst_ni),
3981 .clk_dst_i (clk_aon_i),
3982 .rst_dst_ni (rst_aon_ni),
3983 .src_regwen_i (wkup_detector_regwen_4_qs),
3984 .src_we_i (wkup_detector_cnt_th_4_we),
3985 .src_re_i ('0),
3986 .src_wd_i (reg_wdata[7:0]),
3987 .src_busy_o (wkup_detector_cnt_th_4_busy),
3988 .src_qs_o (wkup_detector_cnt_th_4_qs), // for software read back
3989 .dst_update_i ('0),
3990 .dst_ds_i ('0),
3991 .dst_qs_i (aon_wkup_detector_cnt_th_4_qs),
3992 .dst_we_o (aon_wkup_detector_cnt_th_4_we),
3993 .dst_re_o (),
3994 .dst_regwen_o (aon_wkup_detector_cnt_th_4_regwen),
3995 .dst_wd_o (aon_wkup_detector_cnt_th_4_wdata)
3996 );
3997 1/1 assign unused_aon_wkup_detector_cnt_th_4_wdata =
Tests: T177 T179 T188
3998 ^aon_wkup_detector_cnt_th_4_wdata;
3999
4000 logic [7:0] aon_wkup_detector_cnt_th_5_qs_int;
4001 logic [7:0] aon_wkup_detector_cnt_th_5_qs;
4002 logic [7:0] aon_wkup_detector_cnt_th_5_wdata;
4003 logic aon_wkup_detector_cnt_th_5_we;
4004 logic unused_aon_wkup_detector_cnt_th_5_wdata;
4005 logic aon_wkup_detector_cnt_th_5_regwen;
4006
4007 always_comb begin
4008 1/1 aon_wkup_detector_cnt_th_5_qs = 8'h0;
Tests: T177 T179 T188
4009 1/1 aon_wkup_detector_cnt_th_5_qs = aon_wkup_detector_cnt_th_5_qs_int;
Tests: T177 T179 T188
4010 end
4011
4012 prim_reg_cdc #(
4013 .DataWidth(8),
4014 .ResetVal(8'h0),
4015 .BitMask(8'hff),
4016 .DstWrReq(0)
4017 ) u_wkup_detector_cnt_th_5_cdc (
4018 .clk_src_i (clk_i),
4019 .rst_src_ni (rst_ni),
4020 .clk_dst_i (clk_aon_i),
4021 .rst_dst_ni (rst_aon_ni),
4022 .src_regwen_i (wkup_detector_regwen_5_qs),
4023 .src_we_i (wkup_detector_cnt_th_5_we),
4024 .src_re_i ('0),
4025 .src_wd_i (reg_wdata[7:0]),
4026 .src_busy_o (wkup_detector_cnt_th_5_busy),
4027 .src_qs_o (wkup_detector_cnt_th_5_qs), // for software read back
4028 .dst_update_i ('0),
4029 .dst_ds_i ('0),
4030 .dst_qs_i (aon_wkup_detector_cnt_th_5_qs),
4031 .dst_we_o (aon_wkup_detector_cnt_th_5_we),
4032 .dst_re_o (),
4033 .dst_regwen_o (aon_wkup_detector_cnt_th_5_regwen),
4034 .dst_wd_o (aon_wkup_detector_cnt_th_5_wdata)
4035 );
4036 1/1 assign unused_aon_wkup_detector_cnt_th_5_wdata =
Tests: T177 T179 T188
4037 ^aon_wkup_detector_cnt_th_5_wdata;
4038
4039 logic [7:0] aon_wkup_detector_cnt_th_6_qs_int;
4040 logic [7:0] aon_wkup_detector_cnt_th_6_qs;
4041 logic [7:0] aon_wkup_detector_cnt_th_6_wdata;
4042 logic aon_wkup_detector_cnt_th_6_we;
4043 logic unused_aon_wkup_detector_cnt_th_6_wdata;
4044 logic aon_wkup_detector_cnt_th_6_regwen;
4045
4046 always_comb begin
4047 1/1 aon_wkup_detector_cnt_th_6_qs = 8'h0;
Tests: T177 T179 T188
4048 1/1 aon_wkup_detector_cnt_th_6_qs = aon_wkup_detector_cnt_th_6_qs_int;
Tests: T177 T179 T188
4049 end
4050
4051 prim_reg_cdc #(
4052 .DataWidth(8),
4053 .ResetVal(8'h0),
4054 .BitMask(8'hff),
4055 .DstWrReq(0)
4056 ) u_wkup_detector_cnt_th_6_cdc (
4057 .clk_src_i (clk_i),
4058 .rst_src_ni (rst_ni),
4059 .clk_dst_i (clk_aon_i),
4060 .rst_dst_ni (rst_aon_ni),
4061 .src_regwen_i (wkup_detector_regwen_6_qs),
4062 .src_we_i (wkup_detector_cnt_th_6_we),
4063 .src_re_i ('0),
4064 .src_wd_i (reg_wdata[7:0]),
4065 .src_busy_o (wkup_detector_cnt_th_6_busy),
4066 .src_qs_o (wkup_detector_cnt_th_6_qs), // for software read back
4067 .dst_update_i ('0),
4068 .dst_ds_i ('0),
4069 .dst_qs_i (aon_wkup_detector_cnt_th_6_qs),
4070 .dst_we_o (aon_wkup_detector_cnt_th_6_we),
4071 .dst_re_o (),
4072 .dst_regwen_o (aon_wkup_detector_cnt_th_6_regwen),
4073 .dst_wd_o (aon_wkup_detector_cnt_th_6_wdata)
4074 );
4075 1/1 assign unused_aon_wkup_detector_cnt_th_6_wdata =
Tests: T177 T179 T188
4076 ^aon_wkup_detector_cnt_th_6_wdata;
4077
4078 logic [7:0] aon_wkup_detector_cnt_th_7_qs_int;
4079 logic [7:0] aon_wkup_detector_cnt_th_7_qs;
4080 logic [7:0] aon_wkup_detector_cnt_th_7_wdata;
4081 logic aon_wkup_detector_cnt_th_7_we;
4082 logic unused_aon_wkup_detector_cnt_th_7_wdata;
4083 logic aon_wkup_detector_cnt_th_7_regwen;
4084
4085 always_comb begin
4086 1/1 aon_wkup_detector_cnt_th_7_qs = 8'h0;
Tests: T177 T179 T188
4087 1/1 aon_wkup_detector_cnt_th_7_qs = aon_wkup_detector_cnt_th_7_qs_int;
Tests: T177 T179 T188
4088 end
4089
4090 prim_reg_cdc #(
4091 .DataWidth(8),
4092 .ResetVal(8'h0),
4093 .BitMask(8'hff),
4094 .DstWrReq(0)
4095 ) u_wkup_detector_cnt_th_7_cdc (
4096 .clk_src_i (clk_i),
4097 .rst_src_ni (rst_ni),
4098 .clk_dst_i (clk_aon_i),
4099 .rst_dst_ni (rst_aon_ni),
4100 .src_regwen_i (wkup_detector_regwen_7_qs),
4101 .src_we_i (wkup_detector_cnt_th_7_we),
4102 .src_re_i ('0),
4103 .src_wd_i (reg_wdata[7:0]),
4104 .src_busy_o (wkup_detector_cnt_th_7_busy),
4105 .src_qs_o (wkup_detector_cnt_th_7_qs), // for software read back
4106 .dst_update_i ('0),
4107 .dst_ds_i ('0),
4108 .dst_qs_i (aon_wkup_detector_cnt_th_7_qs),
4109 .dst_we_o (aon_wkup_detector_cnt_th_7_we),
4110 .dst_re_o (),
4111 .dst_regwen_o (aon_wkup_detector_cnt_th_7_regwen),
4112 .dst_wd_o (aon_wkup_detector_cnt_th_7_wdata)
4113 );
4114 1/1 assign unused_aon_wkup_detector_cnt_th_7_wdata =
Tests: T177 T179 T188
4115 ^aon_wkup_detector_cnt_th_7_wdata;
4116
4117 logic aon_wkup_cause_cause_0_ds_int;
4118 logic aon_wkup_cause_cause_0_qs_int;
4119 logic aon_wkup_cause_cause_1_ds_int;
4120 logic aon_wkup_cause_cause_1_qs_int;
4121 logic aon_wkup_cause_cause_2_ds_int;
4122 logic aon_wkup_cause_cause_2_qs_int;
4123 logic aon_wkup_cause_cause_3_ds_int;
4124 logic aon_wkup_cause_cause_3_qs_int;
4125 logic aon_wkup_cause_cause_4_ds_int;
4126 logic aon_wkup_cause_cause_4_qs_int;
4127 logic aon_wkup_cause_cause_5_ds_int;
4128 logic aon_wkup_cause_cause_5_qs_int;
4129 logic aon_wkup_cause_cause_6_ds_int;
4130 logic aon_wkup_cause_cause_6_qs_int;
4131 logic aon_wkup_cause_cause_7_ds_int;
4132 logic aon_wkup_cause_cause_7_qs_int;
4133 logic [7:0] aon_wkup_cause_ds;
4134 logic aon_wkup_cause_qe;
4135 logic [7:0] aon_wkup_cause_qs;
4136 logic [7:0] aon_wkup_cause_wdata;
4137 logic aon_wkup_cause_we;
4138 logic unused_aon_wkup_cause_wdata;
4139
4140 always_comb begin
4141 1/1 aon_wkup_cause_qs = 8'h0;
Tests: T4 T6 T25
4142 1/1 aon_wkup_cause_ds = 8'h0;
Tests: T4 T6 T25
4143 1/1 aon_wkup_cause_ds[0] = aon_wkup_cause_cause_0_ds_int;
Tests: T4 T6 T25
4144 1/1 aon_wkup_cause_qs[0] = aon_wkup_cause_cause_0_qs_int;
Tests: T4 T6 T25
4145 1/1 aon_wkup_cause_ds[1] = aon_wkup_cause_cause_1_ds_int;
Tests: T4 T6 T25
4146 1/1 aon_wkup_cause_qs[1] = aon_wkup_cause_cause_1_qs_int;
Tests: T4 T6 T25
4147 1/1 aon_wkup_cause_ds[2] = aon_wkup_cause_cause_2_ds_int;
Tests: T4 T6 T25
4148 1/1 aon_wkup_cause_qs[2] = aon_wkup_cause_cause_2_qs_int;
Tests: T4 T6 T25
4149 1/1 aon_wkup_cause_ds[3] = aon_wkup_cause_cause_3_ds_int;
Tests: T4 T6 T25
4150 1/1 aon_wkup_cause_qs[3] = aon_wkup_cause_cause_3_qs_int;
Tests: T4 T6 T25
4151 1/1 aon_wkup_cause_ds[4] = aon_wkup_cause_cause_4_ds_int;
Tests: T4 T6 T25
4152 1/1 aon_wkup_cause_qs[4] = aon_wkup_cause_cause_4_qs_int;
Tests: T4 T6 T25
4153 1/1 aon_wkup_cause_ds[5] = aon_wkup_cause_cause_5_ds_int;
Tests: T4 T6 T25
4154 1/1 aon_wkup_cause_qs[5] = aon_wkup_cause_cause_5_qs_int;
Tests: T4 T6 T25
4155 1/1 aon_wkup_cause_ds[6] = aon_wkup_cause_cause_6_ds_int;
Tests: T4 T6 T25
4156 1/1 aon_wkup_cause_qs[6] = aon_wkup_cause_cause_6_qs_int;
Tests: T4 T6 T25
4157 1/1 aon_wkup_cause_ds[7] = aon_wkup_cause_cause_7_ds_int;
Tests: T4 T6 T25
4158 1/1 aon_wkup_cause_qs[7] = aon_wkup_cause_cause_7_qs_int;
Tests: T4 T6 T25
4159 end
4160
4161 prim_reg_cdc #(
4162 .DataWidth(8),
4163 .ResetVal(8'h0),
4164 .BitMask(8'hff),
4165 .DstWrReq(1)
4166 ) u_wkup_cause_cdc (
4167 .clk_src_i (clk_i),
4168 .rst_src_ni (rst_ni),
4169 .clk_dst_i (clk_aon_i),
4170 .rst_dst_ni (rst_aon_ni),
4171 .src_regwen_i ('0),
4172 .src_we_i (wkup_cause_we),
4173 .src_re_i ('0),
4174 .src_wd_i (reg_wdata[7:0]),
4175 .src_busy_o (wkup_cause_busy),
4176 .src_qs_o (wkup_cause_qs), // for software read back
4177 .dst_update_i (aon_wkup_cause_qe),
4178 .dst_ds_i (aon_wkup_cause_ds),
4179 .dst_qs_i (aon_wkup_cause_qs),
4180 .dst_we_o (aon_wkup_cause_we),
4181 .dst_re_o (),
4182 .dst_regwen_o (),
4183 .dst_wd_o (aon_wkup_cause_wdata)
4184 );
4185 1/1 assign unused_aon_wkup_cause_wdata =
Tests: T4 T6 T25
4186 ^aon_wkup_cause_wdata;
4187
4188 // Register instances
4189 // R[alert_test]: V(True)
4190 logic alert_test_qe;
4191 logic [0:0] alert_test_flds_we;
4192 1/1 assign alert_test_qe = &alert_test_flds_we;
Tests: T80 T81 T82
4193 prim_subreg_ext #(
4194 .DW (1)
4195 ) u_alert_test (
4196 .re (1'b0),
4197 .we (alert_test_we),
4198 .wd (alert_test_wd),
4199 .d ('0),
4200 .qre (),
4201 .qe (alert_test_flds_we[0]),
4202 .q (reg2hw.alert_test.q),
4203 .ds (),
4204 .qs ()
4205 );
4206 1/1 assign reg2hw.alert_test.qe = alert_test_qe;
Tests: T80 T81 T82
4207
4208
4209 // Subregister 0 of Multireg mio_periph_insel_regwen
4210 // R[mio_periph_insel_regwen_0]: V(False)
4211 prim_subreg #(
4212 .DW (1),
4213 .SwAccess(prim_subreg_pkg::SwAccessW0C),
4214 .RESVAL (1'h1),
4215 .Mubi (1'b0)
4216 ) u_mio_periph_insel_regwen_0 (
4217 .clk_i (clk_i),
4218 .rst_ni (rst_ni),
4219
4220 // from register interface
4221 .we (mio_periph_insel_regwen_0_we),
4222 .wd (mio_periph_insel_regwen_0_wd),
4223
4224 // from internal hardware
4225 .de (1'b0),
4226 .d ('0),
4227
4228 // to internal hardware
4229 .qe (),
4230 .q (),
4231 .ds (),
4232
4233 // to register interface (read)
4234 .qs (mio_periph_insel_regwen_0_qs)
4235 );
4236
4237
4238 // Subregister 1 of Multireg mio_periph_insel_regwen
4239 // R[mio_periph_insel_regwen_1]: V(False)
4240 prim_subreg #(
4241 .DW (1),
4242 .SwAccess(prim_subreg_pkg::SwAccessW0C),
4243 .RESVAL (1'h1),
4244 .Mubi (1'b0)
4245 ) u_mio_periph_insel_regwen_1 (
4246 .clk_i (clk_i),
4247 .rst_ni (rst_ni),
4248
4249 // from register interface
4250 .we (mio_periph_insel_regwen_1_we),
4251 .wd (mio_periph_insel_regwen_1_wd),
4252
4253 // from internal hardware
4254 .de (1'b0),
4255 .d ('0),
4256
4257 // to internal hardware
4258 .qe (),
4259 .q (),
4260 .ds (),
4261
4262 // to register interface (read)
4263 .qs (mio_periph_insel_regwen_1_qs)
4264 );
4265
4266
4267 // Subregister 2 of Multireg mio_periph_insel_regwen
4268 // R[mio_periph_insel_regwen_2]: V(False)
4269 prim_subreg #(
4270 .DW (1),
4271 .SwAccess(prim_subreg_pkg::SwAccessW0C),
4272 .RESVAL (1'h1),
4273 .Mubi (1'b0)
4274 ) u_mio_periph_insel_regwen_2 (
4275 .clk_i (clk_i),
4276 .rst_ni (rst_ni),
4277
4278 // from register interface
4279 .we (mio_periph_insel_regwen_2_we),
4280 .wd (mio_periph_insel_regwen_2_wd),
4281
4282 // from internal hardware
4283 .de (1'b0),
4284 .d ('0),
4285
4286 // to internal hardware
4287 .qe (),
4288 .q (),
4289 .ds (),
4290
4291 // to register interface (read)
4292 .qs (mio_periph_insel_regwen_2_qs)
4293 );
4294
4295
4296 // Subregister 3 of Multireg mio_periph_insel_regwen
4297 // R[mio_periph_insel_regwen_3]: V(False)
4298 prim_subreg #(
4299 .DW (1),
4300 .SwAccess(prim_subreg_pkg::SwAccessW0C),
4301 .RESVAL (1'h1),
4302 .Mubi (1'b0)
4303 ) u_mio_periph_insel_regwen_3 (
4304 .clk_i (clk_i),
4305 .rst_ni (rst_ni),
4306
4307 // from register interface
4308 .we (mio_periph_insel_regwen_3_we),
4309 .wd (mio_periph_insel_regwen_3_wd),
4310
4311 // from internal hardware
4312 .de (1'b0),
4313 .d ('0),
4314
4315 // to internal hardware
4316 .qe (),
4317 .q (),
4318 .ds (),
4319
4320 // to register interface (read)
4321 .qs (mio_periph_insel_regwen_3_qs)
4322 );
4323
4324
4325 // Subregister 4 of Multireg mio_periph_insel_regwen
4326 // R[mio_periph_insel_regwen_4]: V(False)
4327 prim_subreg #(
4328 .DW (1),
4329 .SwAccess(prim_subreg_pkg::SwAccessW0C),
4330 .RESVAL (1'h1),
4331 .Mubi (1'b0)
4332 ) u_mio_periph_insel_regwen_4 (
4333 .clk_i (clk_i),
4334 .rst_ni (rst_ni),
4335
4336 // from register interface
4337 .we (mio_periph_insel_regwen_4_we),
4338 .wd (mio_periph_insel_regwen_4_wd),
4339
4340 // from internal hardware
4341 .de (1'b0),
4342 .d ('0),
4343
4344 // to internal hardware
4345 .qe (),
4346 .q (),
4347 .ds (),
4348
4349 // to register interface (read)
4350 .qs (mio_periph_insel_regwen_4_qs)
4351 );
4352
4353
4354 // Subregister 5 of Multireg mio_periph_insel_regwen
4355 // R[mio_periph_insel_regwen_5]: V(False)
4356 prim_subreg #(
4357 .DW (1),
4358 .SwAccess(prim_subreg_pkg::SwAccessW0C),
4359 .RESVAL (1'h1),
4360 .Mubi (1'b0)
4361 ) u_mio_periph_insel_regwen_5 (
4362 .clk_i (clk_i),
4363 .rst_ni (rst_ni),
4364
4365 // from register interface
4366 .we (mio_periph_insel_regwen_5_we),
4367 .wd (mio_periph_insel_regwen_5_wd),
4368
4369 // from internal hardware
4370 .de (1'b0),
4371 .d ('0),
4372
4373 // to internal hardware
4374 .qe (),
4375 .q (),
4376 .ds (),
4377
4378 // to register interface (read)
4379 .qs (mio_periph_insel_regwen_5_qs)
4380 );
4381
4382
4383 // Subregister 6 of Multireg mio_periph_insel_regwen
4384 // R[mio_periph_insel_regwen_6]: V(False)
4385 prim_subreg #(
4386 .DW (1),
4387 .SwAccess(prim_subreg_pkg::SwAccessW0C),
4388 .RESVAL (1'h1),
4389 .Mubi (1'b0)
4390 ) u_mio_periph_insel_regwen_6 (
4391 .clk_i (clk_i),
4392 .rst_ni (rst_ni),
4393
4394 // from register interface
4395 .we (mio_periph_insel_regwen_6_we),
4396 .wd (mio_periph_insel_regwen_6_wd),
4397
4398 // from internal hardware
4399 .de (1'b0),
4400 .d ('0),
4401
4402 // to internal hardware
4403 .qe (),
4404 .q (),
4405 .ds (),
4406
4407 // to register interface (read)
4408 .qs (mio_periph_insel_regwen_6_qs)
4409 );
4410
4411
4412 // Subregister 7 of Multireg mio_periph_insel_regwen
4413 // R[mio_periph_insel_regwen_7]: V(False)
4414 prim_subreg #(
4415 .DW (1),
4416 .SwAccess(prim_subreg_pkg::SwAccessW0C),
4417 .RESVAL (1'h1),
4418 .Mubi (1'b0)
4419 ) u_mio_periph_insel_regwen_7 (
4420 .clk_i (clk_i),
4421 .rst_ni (rst_ni),
4422
4423 // from register interface
4424 .we (mio_periph_insel_regwen_7_we),
4425 .wd (mio_periph_insel_regwen_7_wd),
4426
4427 // from internal hardware
4428 .de (1'b0),
4429 .d ('0),
4430
4431 // to internal hardware
4432 .qe (),
4433 .q (),
4434 .ds (),
4435
4436 // to register interface (read)
4437 .qs (mio_periph_insel_regwen_7_qs)
4438 );
4439
4440
4441 // Subregister 8 of Multireg mio_periph_insel_regwen
4442 // R[mio_periph_insel_regwen_8]: V(False)
4443 prim_subreg #(
4444 .DW (1),
4445 .SwAccess(prim_subreg_pkg::SwAccessW0C),
4446 .RESVAL (1'h1),
4447 .Mubi (1'b0)
4448 ) u_mio_periph_insel_regwen_8 (
4449 .clk_i (clk_i),
4450 .rst_ni (rst_ni),
4451
4452 // from register interface
4453 .we (mio_periph_insel_regwen_8_we),
4454 .wd (mio_periph_insel_regwen_8_wd),
4455
4456 // from internal hardware
4457 .de (1'b0),
4458 .d ('0),
4459
4460 // to internal hardware
4461 .qe (),
4462 .q (),
4463 .ds (),
4464
4465 // to register interface (read)
4466 .qs (mio_periph_insel_regwen_8_qs)
4467 );
4468
4469
4470 // Subregister 9 of Multireg mio_periph_insel_regwen
4471 // R[mio_periph_insel_regwen_9]: V(False)
4472 prim_subreg #(
4473 .DW (1),
4474 .SwAccess(prim_subreg_pkg::SwAccessW0C),
4475 .RESVAL (1'h1),
4476 .Mubi (1'b0)
4477 ) u_mio_periph_insel_regwen_9 (
4478 .clk_i (clk_i),
4479 .rst_ni (rst_ni),
4480
4481 // from register interface
4482 .we (mio_periph_insel_regwen_9_we),
4483 .wd (mio_periph_insel_regwen_9_wd),
4484
4485 // from internal hardware
4486 .de (1'b0),
4487 .d ('0),
4488
4489 // to internal hardware
4490 .qe (),
4491 .q (),
4492 .ds (),
4493
4494 // to register interface (read)
4495 .qs (mio_periph_insel_regwen_9_qs)
4496 );
4497
4498
4499 // Subregister 10 of Multireg mio_periph_insel_regwen
4500 // R[mio_periph_insel_regwen_10]: V(False)
4501 prim_subreg #(
4502 .DW (1),
4503 .SwAccess(prim_subreg_pkg::SwAccessW0C),
4504 .RESVAL (1'h1),
4505 .Mubi (1'b0)
4506 ) u_mio_periph_insel_regwen_10 (
4507 .clk_i (clk_i),
4508 .rst_ni (rst_ni),
4509
4510 // from register interface
4511 .we (mio_periph_insel_regwen_10_we),
4512 .wd (mio_periph_insel_regwen_10_wd),
4513
4514 // from internal hardware
4515 .de (1'b0),
4516 .d ('0),
4517
4518 // to internal hardware
4519 .qe (),
4520 .q (),
4521 .ds (),
4522
4523 // to register interface (read)
4524 .qs (mio_periph_insel_regwen_10_qs)
4525 );
4526
4527
4528 // Subregister 11 of Multireg mio_periph_insel_regwen
4529 // R[mio_periph_insel_regwen_11]: V(False)
4530 prim_subreg #(
4531 .DW (1),
4532 .SwAccess(prim_subreg_pkg::SwAccessW0C),
4533 .RESVAL (1'h1),
4534 .Mubi (1'b0)
4535 ) u_mio_periph_insel_regwen_11 (
4536 .clk_i (clk_i),
4537 .rst_ni (rst_ni),
4538
4539 // from register interface
4540 .we (mio_periph_insel_regwen_11_we),
4541 .wd (mio_periph_insel_regwen_11_wd),
4542
4543 // from internal hardware
4544 .de (1'b0),
4545 .d ('0),
4546
4547 // to internal hardware
4548 .qe (),
4549 .q (),
4550 .ds (),
4551
4552 // to register interface (read)
4553 .qs (mio_periph_insel_regwen_11_qs)
4554 );
4555
4556
4557 // Subregister 12 of Multireg mio_periph_insel_regwen
4558 // R[mio_periph_insel_regwen_12]: V(False)
4559 prim_subreg #(
4560 .DW (1),
4561 .SwAccess(prim_subreg_pkg::SwAccessW0C),
4562 .RESVAL (1'h1),
4563 .Mubi (1'b0)
4564 ) u_mio_periph_insel_regwen_12 (
4565 .clk_i (clk_i),
4566 .rst_ni (rst_ni),
4567
4568 // from register interface
4569 .we (mio_periph_insel_regwen_12_we),
4570 .wd (mio_periph_insel_regwen_12_wd),
4571
4572 // from internal hardware
4573 .de (1'b0),
4574 .d ('0),
4575
4576 // to internal hardware
4577 .qe (),
4578 .q (),
4579 .ds (),
4580
4581 // to register interface (read)
4582 .qs (mio_periph_insel_regwen_12_qs)
4583 );
4584
4585
4586 // Subregister 13 of Multireg mio_periph_insel_regwen
4587 // R[mio_periph_insel_regwen_13]: V(False)
4588 prim_subreg #(
4589 .DW (1),
4590 .SwAccess(prim_subreg_pkg::SwAccessW0C),
4591 .RESVAL (1'h1),
4592 .Mubi (1'b0)
4593 ) u_mio_periph_insel_regwen_13 (
4594 .clk_i (clk_i),
4595 .rst_ni (rst_ni),
4596
4597 // from register interface
4598 .we (mio_periph_insel_regwen_13_we),
4599 .wd (mio_periph_insel_regwen_13_wd),
4600
4601 // from internal hardware
4602 .de (1'b0),
4603 .d ('0),
4604
4605 // to internal hardware
4606 .qe (),
4607 .q (),
4608 .ds (),
4609
4610 // to register interface (read)
4611 .qs (mio_periph_insel_regwen_13_qs)
4612 );
4613
4614
4615 // Subregister 14 of Multireg mio_periph_insel_regwen
4616 // R[mio_periph_insel_regwen_14]: V(False)
4617 prim_subreg #(
4618 .DW (1),
4619 .SwAccess(prim_subreg_pkg::SwAccessW0C),
4620 .RESVAL (1'h1),
4621 .Mubi (1'b0)
4622 ) u_mio_periph_insel_regwen_14 (
4623 .clk_i (clk_i),
4624 .rst_ni (rst_ni),
4625
4626 // from register interface
4627 .we (mio_periph_insel_regwen_14_we),
4628 .wd (mio_periph_insel_regwen_14_wd),
4629
4630 // from internal hardware
4631 .de (1'b0),
4632 .d ('0),
4633
4634 // to internal hardware
4635 .qe (),
4636 .q (),
4637 .ds (),
4638
4639 // to register interface (read)
4640 .qs (mio_periph_insel_regwen_14_qs)
4641 );
4642
4643
4644 // Subregister 15 of Multireg mio_periph_insel_regwen
4645 // R[mio_periph_insel_regwen_15]: V(False)
4646 prim_subreg #(
4647 .DW (1),
4648 .SwAccess(prim_subreg_pkg::SwAccessW0C),
4649 .RESVAL (1'h1),
4650 .Mubi (1'b0)
4651 ) u_mio_periph_insel_regwen_15 (
4652 .clk_i (clk_i),
4653 .rst_ni (rst_ni),
4654
4655 // from register interface
4656 .we (mio_periph_insel_regwen_15_we),
4657 .wd (mio_periph_insel_regwen_15_wd),
4658
4659 // from internal hardware
4660 .de (1'b0),
4661 .d ('0),
4662
4663 // to internal hardware
4664 .qe (),
4665 .q (),
4666 .ds (),
4667
4668 // to register interface (read)
4669 .qs (mio_periph_insel_regwen_15_qs)
4670 );
4671
4672
4673 // Subregister 16 of Multireg mio_periph_insel_regwen
4674 // R[mio_periph_insel_regwen_16]: V(False)
4675 prim_subreg #(
4676 .DW (1),
4677 .SwAccess(prim_subreg_pkg::SwAccessW0C),
4678 .RESVAL (1'h1),
4679 .Mubi (1'b0)
4680 ) u_mio_periph_insel_regwen_16 (
4681 .clk_i (clk_i),
4682 .rst_ni (rst_ni),
4683
4684 // from register interface
4685 .we (mio_periph_insel_regwen_16_we),
4686 .wd (mio_periph_insel_regwen_16_wd),
4687
4688 // from internal hardware
4689 .de (1'b0),
4690 .d ('0),
4691
4692 // to internal hardware
4693 .qe (),
4694 .q (),
4695 .ds (),
4696
4697 // to register interface (read)
4698 .qs (mio_periph_insel_regwen_16_qs)
4699 );
4700
4701
4702 // Subregister 17 of Multireg mio_periph_insel_regwen
4703 // R[mio_periph_insel_regwen_17]: V(False)
4704 prim_subreg #(
4705 .DW (1),
4706 .SwAccess(prim_subreg_pkg::SwAccessW0C),
4707 .RESVAL (1'h1),
4708 .Mubi (1'b0)
4709 ) u_mio_periph_insel_regwen_17 (
4710 .clk_i (clk_i),
4711 .rst_ni (rst_ni),
4712
4713 // from register interface
4714 .we (mio_periph_insel_regwen_17_we),
4715 .wd (mio_periph_insel_regwen_17_wd),
4716
4717 // from internal hardware
4718 .de (1'b0),
4719 .d ('0),
4720
4721 // to internal hardware
4722 .qe (),
4723 .q (),
4724 .ds (),
4725
4726 // to register interface (read)
4727 .qs (mio_periph_insel_regwen_17_qs)
4728 );
4729
4730
4731 // Subregister 18 of Multireg mio_periph_insel_regwen
4732 // R[mio_periph_insel_regwen_18]: V(False)
4733 prim_subreg #(
4734 .DW (1),
4735 .SwAccess(prim_subreg_pkg::SwAccessW0C),
4736 .RESVAL (1'h1),
4737 .Mubi (1'b0)
4738 ) u_mio_periph_insel_regwen_18 (
4739 .clk_i (clk_i),
4740 .rst_ni (rst_ni),
4741
4742 // from register interface
4743 .we (mio_periph_insel_regwen_18_we),
4744 .wd (mio_periph_insel_regwen_18_wd),
4745
4746 // from internal hardware
4747 .de (1'b0),
4748 .d ('0),
4749
4750 // to internal hardware
4751 .qe (),
4752 .q (),
4753 .ds (),
4754
4755 // to register interface (read)
4756 .qs (mio_periph_insel_regwen_18_qs)
4757 );
4758
4759
4760 // Subregister 19 of Multireg mio_periph_insel_regwen
4761 // R[mio_periph_insel_regwen_19]: V(False)
4762 prim_subreg #(
4763 .DW (1),
4764 .SwAccess(prim_subreg_pkg::SwAccessW0C),
4765 .RESVAL (1'h1),
4766 .Mubi (1'b0)
4767 ) u_mio_periph_insel_regwen_19 (
4768 .clk_i (clk_i),
4769 .rst_ni (rst_ni),
4770
4771 // from register interface
4772 .we (mio_periph_insel_regwen_19_we),
4773 .wd (mio_periph_insel_regwen_19_wd),
4774
4775 // from internal hardware
4776 .de (1'b0),
4777 .d ('0),
4778
4779 // to internal hardware
4780 .qe (),
4781 .q (),
4782 .ds (),
4783
4784 // to register interface (read)
4785 .qs (mio_periph_insel_regwen_19_qs)
4786 );
4787
4788
4789 // Subregister 20 of Multireg mio_periph_insel_regwen
4790 // R[mio_periph_insel_regwen_20]: V(False)
4791 prim_subreg #(
4792 .DW (1),
4793 .SwAccess(prim_subreg_pkg::SwAccessW0C),
4794 .RESVAL (1'h1),
4795 .Mubi (1'b0)
4796 ) u_mio_periph_insel_regwen_20 (
4797 .clk_i (clk_i),
4798 .rst_ni (rst_ni),
4799
4800 // from register interface
4801 .we (mio_periph_insel_regwen_20_we),
4802 .wd (mio_periph_insel_regwen_20_wd),
4803
4804 // from internal hardware
4805 .de (1'b0),
4806 .d ('0),
4807
4808 // to internal hardware
4809 .qe (),
4810 .q (),
4811 .ds (),
4812
4813 // to register interface (read)
4814 .qs (mio_periph_insel_regwen_20_qs)
4815 );
4816
4817
4818 // Subregister 21 of Multireg mio_periph_insel_regwen
4819 // R[mio_periph_insel_regwen_21]: V(False)
4820 prim_subreg #(
4821 .DW (1),
4822 .SwAccess(prim_subreg_pkg::SwAccessW0C),
4823 .RESVAL (1'h1),
4824 .Mubi (1'b0)
4825 ) u_mio_periph_insel_regwen_21 (
4826 .clk_i (clk_i),
4827 .rst_ni (rst_ni),
4828
4829 // from register interface
4830 .we (mio_periph_insel_regwen_21_we),
4831 .wd (mio_periph_insel_regwen_21_wd),
4832
4833 // from internal hardware
4834 .de (1'b0),
4835 .d ('0),
4836
4837 // to internal hardware
4838 .qe (),
4839 .q (),
4840 .ds (),
4841
4842 // to register interface (read)
4843 .qs (mio_periph_insel_regwen_21_qs)
4844 );
4845
4846
4847 // Subregister 22 of Multireg mio_periph_insel_regwen
4848 // R[mio_periph_insel_regwen_22]: V(False)
4849 prim_subreg #(
4850 .DW (1),
4851 .SwAccess(prim_subreg_pkg::SwAccessW0C),
4852 .RESVAL (1'h1),
4853 .Mubi (1'b0)
4854 ) u_mio_periph_insel_regwen_22 (
4855 .clk_i (clk_i),
4856 .rst_ni (rst_ni),
4857
4858 // from register interface
4859 .we (mio_periph_insel_regwen_22_we),
4860 .wd (mio_periph_insel_regwen_22_wd),
4861
4862 // from internal hardware
4863 .de (1'b0),
4864 .d ('0),
4865
4866 // to internal hardware
4867 .qe (),
4868 .q (),
4869 .ds (),
4870
4871 // to register interface (read)
4872 .qs (mio_periph_insel_regwen_22_qs)
4873 );
4874
4875
4876 // Subregister 23 of Multireg mio_periph_insel_regwen
4877 // R[mio_periph_insel_regwen_23]: V(False)
4878 prim_subreg #(
4879 .DW (1),
4880 .SwAccess(prim_subreg_pkg::SwAccessW0C),
4881 .RESVAL (1'h1),
4882 .Mubi (1'b0)
4883 ) u_mio_periph_insel_regwen_23 (
4884 .clk_i (clk_i),
4885 .rst_ni (rst_ni),
4886
4887 // from register interface
4888 .we (mio_periph_insel_regwen_23_we),
4889 .wd (mio_periph_insel_regwen_23_wd),
4890
4891 // from internal hardware
4892 .de (1'b0),
4893 .d ('0),
4894
4895 // to internal hardware
4896 .qe (),
4897 .q (),
4898 .ds (),
4899
4900 // to register interface (read)
4901 .qs (mio_periph_insel_regwen_23_qs)
4902 );
4903
4904
4905 // Subregister 24 of Multireg mio_periph_insel_regwen
4906 // R[mio_periph_insel_regwen_24]: V(False)
4907 prim_subreg #(
4908 .DW (1),
4909 .SwAccess(prim_subreg_pkg::SwAccessW0C),
4910 .RESVAL (1'h1),
4911 .Mubi (1'b0)
4912 ) u_mio_periph_insel_regwen_24 (
4913 .clk_i (clk_i),
4914 .rst_ni (rst_ni),
4915
4916 // from register interface
4917 .we (mio_periph_insel_regwen_24_we),
4918 .wd (mio_periph_insel_regwen_24_wd),
4919
4920 // from internal hardware
4921 .de (1'b0),
4922 .d ('0),
4923
4924 // to internal hardware
4925 .qe (),
4926 .q (),
4927 .ds (),
4928
4929 // to register interface (read)
4930 .qs (mio_periph_insel_regwen_24_qs)
4931 );
4932
4933
4934 // Subregister 25 of Multireg mio_periph_insel_regwen
4935 // R[mio_periph_insel_regwen_25]: V(False)
4936 prim_subreg #(
4937 .DW (1),
4938 .SwAccess(prim_subreg_pkg::SwAccessW0C),
4939 .RESVAL (1'h1),
4940 .Mubi (1'b0)
4941 ) u_mio_periph_insel_regwen_25 (
4942 .clk_i (clk_i),
4943 .rst_ni (rst_ni),
4944
4945 // from register interface
4946 .we (mio_periph_insel_regwen_25_we),
4947 .wd (mio_periph_insel_regwen_25_wd),
4948
4949 // from internal hardware
4950 .de (1'b0),
4951 .d ('0),
4952
4953 // to internal hardware
4954 .qe (),
4955 .q (),
4956 .ds (),
4957
4958 // to register interface (read)
4959 .qs (mio_periph_insel_regwen_25_qs)
4960 );
4961
4962
4963 // Subregister 26 of Multireg mio_periph_insel_regwen
4964 // R[mio_periph_insel_regwen_26]: V(False)
4965 prim_subreg #(
4966 .DW (1),
4967 .SwAccess(prim_subreg_pkg::SwAccessW0C),
4968 .RESVAL (1'h1),
4969 .Mubi (1'b0)
4970 ) u_mio_periph_insel_regwen_26 (
4971 .clk_i (clk_i),
4972 .rst_ni (rst_ni),
4973
4974 // from register interface
4975 .we (mio_periph_insel_regwen_26_we),
4976 .wd (mio_periph_insel_regwen_26_wd),
4977
4978 // from internal hardware
4979 .de (1'b0),
4980 .d ('0),
4981
4982 // to internal hardware
4983 .qe (),
4984 .q (),
4985 .ds (),
4986
4987 // to register interface (read)
4988 .qs (mio_periph_insel_regwen_26_qs)
4989 );
4990
4991
4992 // Subregister 27 of Multireg mio_periph_insel_regwen
4993 // R[mio_periph_insel_regwen_27]: V(False)
4994 prim_subreg #(
4995 .DW (1),
4996 .SwAccess(prim_subreg_pkg::SwAccessW0C),
4997 .RESVAL (1'h1),
4998 .Mubi (1'b0)
4999 ) u_mio_periph_insel_regwen_27 (
5000 .clk_i (clk_i),
5001 .rst_ni (rst_ni),
5002
5003 // from register interface
5004 .we (mio_periph_insel_regwen_27_we),
5005 .wd (mio_periph_insel_regwen_27_wd),
5006
5007 // from internal hardware
5008 .de (1'b0),
5009 .d ('0),
5010
5011 // to internal hardware
5012 .qe (),
5013 .q (),
5014 .ds (),
5015
5016 // to register interface (read)
5017 .qs (mio_periph_insel_regwen_27_qs)
5018 );
5019
5020
5021 // Subregister 28 of Multireg mio_periph_insel_regwen
5022 // R[mio_periph_insel_regwen_28]: V(False)
5023 prim_subreg #(
5024 .DW (1),
5025 .SwAccess(prim_subreg_pkg::SwAccessW0C),
5026 .RESVAL (1'h1),
5027 .Mubi (1'b0)
5028 ) u_mio_periph_insel_regwen_28 (
5029 .clk_i (clk_i),
5030 .rst_ni (rst_ni),
5031
5032 // from register interface
5033 .we (mio_periph_insel_regwen_28_we),
5034 .wd (mio_periph_insel_regwen_28_wd),
5035
5036 // from internal hardware
5037 .de (1'b0),
5038 .d ('0),
5039
5040 // to internal hardware
5041 .qe (),
5042 .q (),
5043 .ds (),
5044
5045 // to register interface (read)
5046 .qs (mio_periph_insel_regwen_28_qs)
5047 );
5048
5049
5050 // Subregister 29 of Multireg mio_periph_insel_regwen
5051 // R[mio_periph_insel_regwen_29]: V(False)
5052 prim_subreg #(
5053 .DW (1),
5054 .SwAccess(prim_subreg_pkg::SwAccessW0C),
5055 .RESVAL (1'h1),
5056 .Mubi (1'b0)
5057 ) u_mio_periph_insel_regwen_29 (
5058 .clk_i (clk_i),
5059 .rst_ni (rst_ni),
5060
5061 // from register interface
5062 .we (mio_periph_insel_regwen_29_we),
5063 .wd (mio_periph_insel_regwen_29_wd),
5064
5065 // from internal hardware
5066 .de (1'b0),
5067 .d ('0),
5068
5069 // to internal hardware
5070 .qe (),
5071 .q (),
5072 .ds (),
5073
5074 // to register interface (read)
5075 .qs (mio_periph_insel_regwen_29_qs)
5076 );
5077
5078
5079 // Subregister 30 of Multireg mio_periph_insel_regwen
5080 // R[mio_periph_insel_regwen_30]: V(False)
5081 prim_subreg #(
5082 .DW (1),
5083 .SwAccess(prim_subreg_pkg::SwAccessW0C),
5084 .RESVAL (1'h1),
5085 .Mubi (1'b0)
5086 ) u_mio_periph_insel_regwen_30 (
5087 .clk_i (clk_i),
5088 .rst_ni (rst_ni),
5089
5090 // from register interface
5091 .we (mio_periph_insel_regwen_30_we),
5092 .wd (mio_periph_insel_regwen_30_wd),
5093
5094 // from internal hardware
5095 .de (1'b0),
5096 .d ('0),
5097
5098 // to internal hardware
5099 .qe (),
5100 .q (),
5101 .ds (),
5102
5103 // to register interface (read)
5104 .qs (mio_periph_insel_regwen_30_qs)
5105 );
5106
5107
5108 // Subregister 31 of Multireg mio_periph_insel_regwen
5109 // R[mio_periph_insel_regwen_31]: V(False)
5110 prim_subreg #(
5111 .DW (1),
5112 .SwAccess(prim_subreg_pkg::SwAccessW0C),
5113 .RESVAL (1'h1),
5114 .Mubi (1'b0)
5115 ) u_mio_periph_insel_regwen_31 (
5116 .clk_i (clk_i),
5117 .rst_ni (rst_ni),
5118
5119 // from register interface
5120 .we (mio_periph_insel_regwen_31_we),
5121 .wd (mio_periph_insel_regwen_31_wd),
5122
5123 // from internal hardware
5124 .de (1'b0),
5125 .d ('0),
5126
5127 // to internal hardware
5128 .qe (),
5129 .q (),
5130 .ds (),
5131
5132 // to register interface (read)
5133 .qs (mio_periph_insel_regwen_31_qs)
5134 );
5135
5136
5137 // Subregister 32 of Multireg mio_periph_insel_regwen
5138 // R[mio_periph_insel_regwen_32]: V(False)
5139 prim_subreg #(
5140 .DW (1),
5141 .SwAccess(prim_subreg_pkg::SwAccessW0C),
5142 .RESVAL (1'h1),
5143 .Mubi (1'b0)
5144 ) u_mio_periph_insel_regwen_32 (
5145 .clk_i (clk_i),
5146 .rst_ni (rst_ni),
5147
5148 // from register interface
5149 .we (mio_periph_insel_regwen_32_we),
5150 .wd (mio_periph_insel_regwen_32_wd),
5151
5152 // from internal hardware
5153 .de (1'b0),
5154 .d ('0),
5155
5156 // to internal hardware
5157 .qe (),
5158 .q (),
5159 .ds (),
5160
5161 // to register interface (read)
5162 .qs (mio_periph_insel_regwen_32_qs)
5163 );
5164
5165
5166 // Subregister 33 of Multireg mio_periph_insel_regwen
5167 // R[mio_periph_insel_regwen_33]: V(False)
5168 prim_subreg #(
5169 .DW (1),
5170 .SwAccess(prim_subreg_pkg::SwAccessW0C),
5171 .RESVAL (1'h1),
5172 .Mubi (1'b0)
5173 ) u_mio_periph_insel_regwen_33 (
5174 .clk_i (clk_i),
5175 .rst_ni (rst_ni),
5176
5177 // from register interface
5178 .we (mio_periph_insel_regwen_33_we),
5179 .wd (mio_periph_insel_regwen_33_wd),
5180
5181 // from internal hardware
5182 .de (1'b0),
5183 .d ('0),
5184
5185 // to internal hardware
5186 .qe (),
5187 .q (),
5188 .ds (),
5189
5190 // to register interface (read)
5191 .qs (mio_periph_insel_regwen_33_qs)
5192 );
5193
5194
5195 // Subregister 34 of Multireg mio_periph_insel_regwen
5196 // R[mio_periph_insel_regwen_34]: V(False)
5197 prim_subreg #(
5198 .DW (1),
5199 .SwAccess(prim_subreg_pkg::SwAccessW0C),
5200 .RESVAL (1'h1),
5201 .Mubi (1'b0)
5202 ) u_mio_periph_insel_regwen_34 (
5203 .clk_i (clk_i),
5204 .rst_ni (rst_ni),
5205
5206 // from register interface
5207 .we (mio_periph_insel_regwen_34_we),
5208 .wd (mio_periph_insel_regwen_34_wd),
5209
5210 // from internal hardware
5211 .de (1'b0),
5212 .d ('0),
5213
5214 // to internal hardware
5215 .qe (),
5216 .q (),
5217 .ds (),
5218
5219 // to register interface (read)
5220 .qs (mio_periph_insel_regwen_34_qs)
5221 );
5222
5223
5224 // Subregister 35 of Multireg mio_periph_insel_regwen
5225 // R[mio_periph_insel_regwen_35]: V(False)
5226 prim_subreg #(
5227 .DW (1),
5228 .SwAccess(prim_subreg_pkg::SwAccessW0C),
5229 .RESVAL (1'h1),
5230 .Mubi (1'b0)
5231 ) u_mio_periph_insel_regwen_35 (
5232 .clk_i (clk_i),
5233 .rst_ni (rst_ni),
5234
5235 // from register interface
5236 .we (mio_periph_insel_regwen_35_we),
5237 .wd (mio_periph_insel_regwen_35_wd),
5238
5239 // from internal hardware
5240 .de (1'b0),
5241 .d ('0),
5242
5243 // to internal hardware
5244 .qe (),
5245 .q (),
5246 .ds (),
5247
5248 // to register interface (read)
5249 .qs (mio_periph_insel_regwen_35_qs)
5250 );
5251
5252
5253 // Subregister 36 of Multireg mio_periph_insel_regwen
5254 // R[mio_periph_insel_regwen_36]: V(False)
5255 prim_subreg #(
5256 .DW (1),
5257 .SwAccess(prim_subreg_pkg::SwAccessW0C),
5258 .RESVAL (1'h1),
5259 .Mubi (1'b0)
5260 ) u_mio_periph_insel_regwen_36 (
5261 .clk_i (clk_i),
5262 .rst_ni (rst_ni),
5263
5264 // from register interface
5265 .we (mio_periph_insel_regwen_36_we),
5266 .wd (mio_periph_insel_regwen_36_wd),
5267
5268 // from internal hardware
5269 .de (1'b0),
5270 .d ('0),
5271
5272 // to internal hardware
5273 .qe (),
5274 .q (),
5275 .ds (),
5276
5277 // to register interface (read)
5278 .qs (mio_periph_insel_regwen_36_qs)
5279 );
5280
5281
5282 // Subregister 37 of Multireg mio_periph_insel_regwen
5283 // R[mio_periph_insel_regwen_37]: V(False)
5284 prim_subreg #(
5285 .DW (1),
5286 .SwAccess(prim_subreg_pkg::SwAccessW0C),
5287 .RESVAL (1'h1),
5288 .Mubi (1'b0)
5289 ) u_mio_periph_insel_regwen_37 (
5290 .clk_i (clk_i),
5291 .rst_ni (rst_ni),
5292
5293 // from register interface
5294 .we (mio_periph_insel_regwen_37_we),
5295 .wd (mio_periph_insel_regwen_37_wd),
5296
5297 // from internal hardware
5298 .de (1'b0),
5299 .d ('0),
5300
5301 // to internal hardware
5302 .qe (),
5303 .q (),
5304 .ds (),
5305
5306 // to register interface (read)
5307 .qs (mio_periph_insel_regwen_37_qs)
5308 );
5309
5310
5311 // Subregister 38 of Multireg mio_periph_insel_regwen
5312 // R[mio_periph_insel_regwen_38]: V(False)
5313 prim_subreg #(
5314 .DW (1),
5315 .SwAccess(prim_subreg_pkg::SwAccessW0C),
5316 .RESVAL (1'h1),
5317 .Mubi (1'b0)
5318 ) u_mio_periph_insel_regwen_38 (
5319 .clk_i (clk_i),
5320 .rst_ni (rst_ni),
5321
5322 // from register interface
5323 .we (mio_periph_insel_regwen_38_we),
5324 .wd (mio_periph_insel_regwen_38_wd),
5325
5326 // from internal hardware
5327 .de (1'b0),
5328 .d ('0),
5329
5330 // to internal hardware
5331 .qe (),
5332 .q (),
5333 .ds (),
5334
5335 // to register interface (read)
5336 .qs (mio_periph_insel_regwen_38_qs)
5337 );
5338
5339
5340 // Subregister 39 of Multireg mio_periph_insel_regwen
5341 // R[mio_periph_insel_regwen_39]: V(False)
5342 prim_subreg #(
5343 .DW (1),
5344 .SwAccess(prim_subreg_pkg::SwAccessW0C),
5345 .RESVAL (1'h1),
5346 .Mubi (1'b0)
5347 ) u_mio_periph_insel_regwen_39 (
5348 .clk_i (clk_i),
5349 .rst_ni (rst_ni),
5350
5351 // from register interface
5352 .we (mio_periph_insel_regwen_39_we),
5353 .wd (mio_periph_insel_regwen_39_wd),
5354
5355 // from internal hardware
5356 .de (1'b0),
5357 .d ('0),
5358
5359 // to internal hardware
5360 .qe (),
5361 .q (),
5362 .ds (),
5363
5364 // to register interface (read)
5365 .qs (mio_periph_insel_regwen_39_qs)
5366 );
5367
5368
5369 // Subregister 40 of Multireg mio_periph_insel_regwen
5370 // R[mio_periph_insel_regwen_40]: V(False)
5371 prim_subreg #(
5372 .DW (1),
5373 .SwAccess(prim_subreg_pkg::SwAccessW0C),
5374 .RESVAL (1'h1),
5375 .Mubi (1'b0)
5376 ) u_mio_periph_insel_regwen_40 (
5377 .clk_i (clk_i),
5378 .rst_ni (rst_ni),
5379
5380 // from register interface
5381 .we (mio_periph_insel_regwen_40_we),
5382 .wd (mio_periph_insel_regwen_40_wd),
5383
5384 // from internal hardware
5385 .de (1'b0),
5386 .d ('0),
5387
5388 // to internal hardware
5389 .qe (),
5390 .q (),
5391 .ds (),
5392
5393 // to register interface (read)
5394 .qs (mio_periph_insel_regwen_40_qs)
5395 );
5396
5397
5398 // Subregister 41 of Multireg mio_periph_insel_regwen
5399 // R[mio_periph_insel_regwen_41]: V(False)
5400 prim_subreg #(
5401 .DW (1),
5402 .SwAccess(prim_subreg_pkg::SwAccessW0C),
5403 .RESVAL (1'h1),
5404 .Mubi (1'b0)
5405 ) u_mio_periph_insel_regwen_41 (
5406 .clk_i (clk_i),
5407 .rst_ni (rst_ni),
5408
5409 // from register interface
5410 .we (mio_periph_insel_regwen_41_we),
5411 .wd (mio_periph_insel_regwen_41_wd),
5412
5413 // from internal hardware
5414 .de (1'b0),
5415 .d ('0),
5416
5417 // to internal hardware
5418 .qe (),
5419 .q (),
5420 .ds (),
5421
5422 // to register interface (read)
5423 .qs (mio_periph_insel_regwen_41_qs)
5424 );
5425
5426
5427 // Subregister 42 of Multireg mio_periph_insel_regwen
5428 // R[mio_periph_insel_regwen_42]: V(False)
5429 prim_subreg #(
5430 .DW (1),
5431 .SwAccess(prim_subreg_pkg::SwAccessW0C),
5432 .RESVAL (1'h1),
5433 .Mubi (1'b0)
5434 ) u_mio_periph_insel_regwen_42 (
5435 .clk_i (clk_i),
5436 .rst_ni (rst_ni),
5437
5438 // from register interface
5439 .we (mio_periph_insel_regwen_42_we),
5440 .wd (mio_periph_insel_regwen_42_wd),
5441
5442 // from internal hardware
5443 .de (1'b0),
5444 .d ('0),
5445
5446 // to internal hardware
5447 .qe (),
5448 .q (),
5449 .ds (),
5450
5451 // to register interface (read)
5452 .qs (mio_periph_insel_regwen_42_qs)
5453 );
5454
5455
5456 // Subregister 43 of Multireg mio_periph_insel_regwen
5457 // R[mio_periph_insel_regwen_43]: V(False)
5458 prim_subreg #(
5459 .DW (1),
5460 .SwAccess(prim_subreg_pkg::SwAccessW0C),
5461 .RESVAL (1'h1),
5462 .Mubi (1'b0)
5463 ) u_mio_periph_insel_regwen_43 (
5464 .clk_i (clk_i),
5465 .rst_ni (rst_ni),
5466
5467 // from register interface
5468 .we (mio_periph_insel_regwen_43_we),
5469 .wd (mio_periph_insel_regwen_43_wd),
5470
5471 // from internal hardware
5472 .de (1'b0),
5473 .d ('0),
5474
5475 // to internal hardware
5476 .qe (),
5477 .q (),
5478 .ds (),
5479
5480 // to register interface (read)
5481 .qs (mio_periph_insel_regwen_43_qs)
5482 );
5483
5484
5485 // Subregister 44 of Multireg mio_periph_insel_regwen
5486 // R[mio_periph_insel_regwen_44]: V(False)
5487 prim_subreg #(
5488 .DW (1),
5489 .SwAccess(prim_subreg_pkg::SwAccessW0C),
5490 .RESVAL (1'h1),
5491 .Mubi (1'b0)
5492 ) u_mio_periph_insel_regwen_44 (
5493 .clk_i (clk_i),
5494 .rst_ni (rst_ni),
5495
5496 // from register interface
5497 .we (mio_periph_insel_regwen_44_we),
5498 .wd (mio_periph_insel_regwen_44_wd),
5499
5500 // from internal hardware
5501 .de (1'b0),
5502 .d ('0),
5503
5504 // to internal hardware
5505 .qe (),
5506 .q (),
5507 .ds (),
5508
5509 // to register interface (read)
5510 .qs (mio_periph_insel_regwen_44_qs)
5511 );
5512
5513
5514 // Subregister 45 of Multireg mio_periph_insel_regwen
5515 // R[mio_periph_insel_regwen_45]: V(False)
5516 prim_subreg #(
5517 .DW (1),
5518 .SwAccess(prim_subreg_pkg::SwAccessW0C),
5519 .RESVAL (1'h1),
5520 .Mubi (1'b0)
5521 ) u_mio_periph_insel_regwen_45 (
5522 .clk_i (clk_i),
5523 .rst_ni (rst_ni),
5524
5525 // from register interface
5526 .we (mio_periph_insel_regwen_45_we),
5527 .wd (mio_periph_insel_regwen_45_wd),
5528
5529 // from internal hardware
5530 .de (1'b0),
5531 .d ('0),
5532
5533 // to internal hardware
5534 .qe (),
5535 .q (),
5536 .ds (),
5537
5538 // to register interface (read)
5539 .qs (mio_periph_insel_regwen_45_qs)
5540 );
5541
5542
5543 // Subregister 46 of Multireg mio_periph_insel_regwen
5544 // R[mio_periph_insel_regwen_46]: V(False)
5545 prim_subreg #(
5546 .DW (1),
5547 .SwAccess(prim_subreg_pkg::SwAccessW0C),
5548 .RESVAL (1'h1),
5549 .Mubi (1'b0)
5550 ) u_mio_periph_insel_regwen_46 (
5551 .clk_i (clk_i),
5552 .rst_ni (rst_ni),
5553
5554 // from register interface
5555 .we (mio_periph_insel_regwen_46_we),
5556 .wd (mio_periph_insel_regwen_46_wd),
5557
5558 // from internal hardware
5559 .de (1'b0),
5560 .d ('0),
5561
5562 // to internal hardware
5563 .qe (),
5564 .q (),
5565 .ds (),
5566
5567 // to register interface (read)
5568 .qs (mio_periph_insel_regwen_46_qs)
5569 );
5570
5571
5572 // Subregister 47 of Multireg mio_periph_insel_regwen
5573 // R[mio_periph_insel_regwen_47]: V(False)
5574 prim_subreg #(
5575 .DW (1),
5576 .SwAccess(prim_subreg_pkg::SwAccessW0C),
5577 .RESVAL (1'h1),
5578 .Mubi (1'b0)
5579 ) u_mio_periph_insel_regwen_47 (
5580 .clk_i (clk_i),
5581 .rst_ni (rst_ni),
5582
5583 // from register interface
5584 .we (mio_periph_insel_regwen_47_we),
5585 .wd (mio_periph_insel_regwen_47_wd),
5586
5587 // from internal hardware
5588 .de (1'b0),
5589 .d ('0),
5590
5591 // to internal hardware
5592 .qe (),
5593 .q (),
5594 .ds (),
5595
5596 // to register interface (read)
5597 .qs (mio_periph_insel_regwen_47_qs)
5598 );
5599
5600
5601 // Subregister 48 of Multireg mio_periph_insel_regwen
5602 // R[mio_periph_insel_regwen_48]: V(False)
5603 prim_subreg #(
5604 .DW (1),
5605 .SwAccess(prim_subreg_pkg::SwAccessW0C),
5606 .RESVAL (1'h1),
5607 .Mubi (1'b0)
5608 ) u_mio_periph_insel_regwen_48 (
5609 .clk_i (clk_i),
5610 .rst_ni (rst_ni),
5611
5612 // from register interface
5613 .we (mio_periph_insel_regwen_48_we),
5614 .wd (mio_periph_insel_regwen_48_wd),
5615
5616 // from internal hardware
5617 .de (1'b0),
5618 .d ('0),
5619
5620 // to internal hardware
5621 .qe (),
5622 .q (),
5623 .ds (),
5624
5625 // to register interface (read)
5626 .qs (mio_periph_insel_regwen_48_qs)
5627 );
5628
5629
5630 // Subregister 49 of Multireg mio_periph_insel_regwen
5631 // R[mio_periph_insel_regwen_49]: V(False)
5632 prim_subreg #(
5633 .DW (1),
5634 .SwAccess(prim_subreg_pkg::SwAccessW0C),
5635 .RESVAL (1'h1),
5636 .Mubi (1'b0)
5637 ) u_mio_periph_insel_regwen_49 (
5638 .clk_i (clk_i),
5639 .rst_ni (rst_ni),
5640
5641 // from register interface
5642 .we (mio_periph_insel_regwen_49_we),
5643 .wd (mio_periph_insel_regwen_49_wd),
5644
5645 // from internal hardware
5646 .de (1'b0),
5647 .d ('0),
5648
5649 // to internal hardware
5650 .qe (),
5651 .q (),
5652 .ds (),
5653
5654 // to register interface (read)
5655 .qs (mio_periph_insel_regwen_49_qs)
5656 );
5657
5658
5659 // Subregister 50 of Multireg mio_periph_insel_regwen
5660 // R[mio_periph_insel_regwen_50]: V(False)
5661 prim_subreg #(
5662 .DW (1),
5663 .SwAccess(prim_subreg_pkg::SwAccessW0C),
5664 .RESVAL (1'h1),
5665 .Mubi (1'b0)
5666 ) u_mio_periph_insel_regwen_50 (
5667 .clk_i (clk_i),
5668 .rst_ni (rst_ni),
5669
5670 // from register interface
5671 .we (mio_periph_insel_regwen_50_we),
5672 .wd (mio_periph_insel_regwen_50_wd),
5673
5674 // from internal hardware
5675 .de (1'b0),
5676 .d ('0),
5677
5678 // to internal hardware
5679 .qe (),
5680 .q (),
5681 .ds (),
5682
5683 // to register interface (read)
5684 .qs (mio_periph_insel_regwen_50_qs)
5685 );
5686
5687
5688 // Subregister 51 of Multireg mio_periph_insel_regwen
5689 // R[mio_periph_insel_regwen_51]: V(False)
5690 prim_subreg #(
5691 .DW (1),
5692 .SwAccess(prim_subreg_pkg::SwAccessW0C),
5693 .RESVAL (1'h1),
5694 .Mubi (1'b0)
5695 ) u_mio_periph_insel_regwen_51 (
5696 .clk_i (clk_i),
5697 .rst_ni (rst_ni),
5698
5699 // from register interface
5700 .we (mio_periph_insel_regwen_51_we),
5701 .wd (mio_periph_insel_regwen_51_wd),
5702
5703 // from internal hardware
5704 .de (1'b0),
5705 .d ('0),
5706
5707 // to internal hardware
5708 .qe (),
5709 .q (),
5710 .ds (),
5711
5712 // to register interface (read)
5713 .qs (mio_periph_insel_regwen_51_qs)
5714 );
5715
5716
5717 // Subregister 52 of Multireg mio_periph_insel_regwen
5718 // R[mio_periph_insel_regwen_52]: V(False)
5719 prim_subreg #(
5720 .DW (1),
5721 .SwAccess(prim_subreg_pkg::SwAccessW0C),
5722 .RESVAL (1'h1),
5723 .Mubi (1'b0)
5724 ) u_mio_periph_insel_regwen_52 (
5725 .clk_i (clk_i),
5726 .rst_ni (rst_ni),
5727
5728 // from register interface
5729 .we (mio_periph_insel_regwen_52_we),
5730 .wd (mio_periph_insel_regwen_52_wd),
5731
5732 // from internal hardware
5733 .de (1'b0),
5734 .d ('0),
5735
5736 // to internal hardware
5737 .qe (),
5738 .q (),
5739 .ds (),
5740
5741 // to register interface (read)
5742 .qs (mio_periph_insel_regwen_52_qs)
5743 );
5744
5745
5746 // Subregister 53 of Multireg mio_periph_insel_regwen
5747 // R[mio_periph_insel_regwen_53]: V(False)
5748 prim_subreg #(
5749 .DW (1),
5750 .SwAccess(prim_subreg_pkg::SwAccessW0C),
5751 .RESVAL (1'h1),
5752 .Mubi (1'b0)
5753 ) u_mio_periph_insel_regwen_53 (
5754 .clk_i (clk_i),
5755 .rst_ni (rst_ni),
5756
5757 // from register interface
5758 .we (mio_periph_insel_regwen_53_we),
5759 .wd (mio_periph_insel_regwen_53_wd),
5760
5761 // from internal hardware
5762 .de (1'b0),
5763 .d ('0),
5764
5765 // to internal hardware
5766 .qe (),
5767 .q (),
5768 .ds (),
5769
5770 // to register interface (read)
5771 .qs (mio_periph_insel_regwen_53_qs)
5772 );
5773
5774
5775 // Subregister 54 of Multireg mio_periph_insel_regwen
5776 // R[mio_periph_insel_regwen_54]: V(False)
5777 prim_subreg #(
5778 .DW (1),
5779 .SwAccess(prim_subreg_pkg::SwAccessW0C),
5780 .RESVAL (1'h1),
5781 .Mubi (1'b0)
5782 ) u_mio_periph_insel_regwen_54 (
5783 .clk_i (clk_i),
5784 .rst_ni (rst_ni),
5785
5786 // from register interface
5787 .we (mio_periph_insel_regwen_54_we),
5788 .wd (mio_periph_insel_regwen_54_wd),
5789
5790 // from internal hardware
5791 .de (1'b0),
5792 .d ('0),
5793
5794 // to internal hardware
5795 .qe (),
5796 .q (),
5797 .ds (),
5798
5799 // to register interface (read)
5800 .qs (mio_periph_insel_regwen_54_qs)
5801 );
5802
5803
5804 // Subregister 55 of Multireg mio_periph_insel_regwen
5805 // R[mio_periph_insel_regwen_55]: V(False)
5806 prim_subreg #(
5807 .DW (1),
5808 .SwAccess(prim_subreg_pkg::SwAccessW0C),
5809 .RESVAL (1'h1),
5810 .Mubi (1'b0)
5811 ) u_mio_periph_insel_regwen_55 (
5812 .clk_i (clk_i),
5813 .rst_ni (rst_ni),
5814
5815 // from register interface
5816 .we (mio_periph_insel_regwen_55_we),
5817 .wd (mio_periph_insel_regwen_55_wd),
5818
5819 // from internal hardware
5820 .de (1'b0),
5821 .d ('0),
5822
5823 // to internal hardware
5824 .qe (),
5825 .q (),
5826 .ds (),
5827
5828 // to register interface (read)
5829 .qs (mio_periph_insel_regwen_55_qs)
5830 );
5831
5832
5833 // Subregister 56 of Multireg mio_periph_insel_regwen
5834 // R[mio_periph_insel_regwen_56]: V(False)
5835 prim_subreg #(
5836 .DW (1),
5837 .SwAccess(prim_subreg_pkg::SwAccessW0C),
5838 .RESVAL (1'h1),
5839 .Mubi (1'b0)
5840 ) u_mio_periph_insel_regwen_56 (
5841 .clk_i (clk_i),
5842 .rst_ni (rst_ni),
5843
5844 // from register interface
5845 .we (mio_periph_insel_regwen_56_we),
5846 .wd (mio_periph_insel_regwen_56_wd),
5847
5848 // from internal hardware
5849 .de (1'b0),
5850 .d ('0),
5851
5852 // to internal hardware
5853 .qe (),
5854 .q (),
5855 .ds (),
5856
5857 // to register interface (read)
5858 .qs (mio_periph_insel_regwen_56_qs)
5859 );
5860
5861
5862 // Subregister 0 of Multireg mio_periph_insel
5863 // R[mio_periph_insel_0]: V(False)
5864 // Create REGWEN-gated WE signal
5865 logic mio_periph_insel_0_gated_we;
5866 1/1 assign mio_periph_insel_0_gated_we = mio_periph_insel_0_we & mio_periph_insel_regwen_0_qs;
Tests: T6 T25 T27
5867 prim_subreg #(
5868 .DW (6),
5869 .SwAccess(prim_subreg_pkg::SwAccessRW),
5870 .RESVAL (6'h0),
5871 .Mubi (1'b0)
5872 ) u_mio_periph_insel_0 (
5873 .clk_i (clk_i),
5874 .rst_ni (rst_ni),
5875
5876 // from register interface
5877 .we (mio_periph_insel_0_gated_we),
5878 .wd (mio_periph_insel_0_wd),
5879
5880 // from internal hardware
5881 .de (1'b0),
5882 .d ('0),
5883
5884 // to internal hardware
5885 .qe (),
5886 .q (reg2hw.mio_periph_insel[0].q),
5887 .ds (),
5888
5889 // to register interface (read)
5890 .qs (mio_periph_insel_0_qs)
5891 );
5892
5893
5894 // Subregister 1 of Multireg mio_periph_insel
5895 // R[mio_periph_insel_1]: V(False)
5896 // Create REGWEN-gated WE signal
5897 logic mio_periph_insel_1_gated_we;
5898 1/1 assign mio_periph_insel_1_gated_we = mio_periph_insel_1_we & mio_periph_insel_regwen_1_qs;
Tests: T25 T27 T42
5899 prim_subreg #(
5900 .DW (6),
5901 .SwAccess(prim_subreg_pkg::SwAccessRW),
5902 .RESVAL (6'h0),
5903 .Mubi (1'b0)
5904 ) u_mio_periph_insel_1 (
5905 .clk_i (clk_i),
5906 .rst_ni (rst_ni),
5907
5908 // from register interface
5909 .we (mio_periph_insel_1_gated_we),
5910 .wd (mio_periph_insel_1_wd),
5911
5912 // from internal hardware
5913 .de (1'b0),
5914 .d ('0),
5915
5916 // to internal hardware
5917 .qe (),
5918 .q (reg2hw.mio_periph_insel[1].q),
5919 .ds (),
5920
5921 // to register interface (read)
5922 .qs (mio_periph_insel_1_qs)
5923 );
5924
5925
5926 // Subregister 2 of Multireg mio_periph_insel
5927 // R[mio_periph_insel_2]: V(False)
5928 // Create REGWEN-gated WE signal
5929 logic mio_periph_insel_2_gated_we;
5930 1/1 assign mio_periph_insel_2_gated_we = mio_periph_insel_2_we & mio_periph_insel_regwen_2_qs;
Tests: T25 T27 T42
5931 prim_subreg #(
5932 .DW (6),
5933 .SwAccess(prim_subreg_pkg::SwAccessRW),
5934 .RESVAL (6'h0),
5935 .Mubi (1'b0)
5936 ) u_mio_periph_insel_2 (
5937 .clk_i (clk_i),
5938 .rst_ni (rst_ni),
5939
5940 // from register interface
5941 .we (mio_periph_insel_2_gated_we),
5942 .wd (mio_periph_insel_2_wd),
5943
5944 // from internal hardware
5945 .de (1'b0),
5946 .d ('0),
5947
5948 // to internal hardware
5949 .qe (),
5950 .q (reg2hw.mio_periph_insel[2].q),
5951 .ds (),
5952
5953 // to register interface (read)
5954 .qs (mio_periph_insel_2_qs)
5955 );
5956
5957
5958 // Subregister 3 of Multireg mio_periph_insel
5959 // R[mio_periph_insel_3]: V(False)
5960 // Create REGWEN-gated WE signal
5961 logic mio_periph_insel_3_gated_we;
5962 1/1 assign mio_periph_insel_3_gated_we = mio_periph_insel_3_we & mio_periph_insel_regwen_3_qs;
Tests: T25 T27 T42
5963 prim_subreg #(
5964 .DW (6),
5965 .SwAccess(prim_subreg_pkg::SwAccessRW),
5966 .RESVAL (6'h0),
5967 .Mubi (1'b0)
5968 ) u_mio_periph_insel_3 (
5969 .clk_i (clk_i),
5970 .rst_ni (rst_ni),
5971
5972 // from register interface
5973 .we (mio_periph_insel_3_gated_we),
5974 .wd (mio_periph_insel_3_wd),
5975
5976 // from internal hardware
5977 .de (1'b0),
5978 .d ('0),
5979
5980 // to internal hardware
5981 .qe (),
5982 .q (reg2hw.mio_periph_insel[3].q),
5983 .ds (),
5984
5985 // to register interface (read)
5986 .qs (mio_periph_insel_3_qs)
5987 );
5988
5989
5990 // Subregister 4 of Multireg mio_periph_insel
5991 // R[mio_periph_insel_4]: V(False)
5992 // Create REGWEN-gated WE signal
5993 logic mio_periph_insel_4_gated_we;
5994 1/1 assign mio_periph_insel_4_gated_we = mio_periph_insel_4_we & mio_periph_insel_regwen_4_qs;
Tests: T25 T27 T42
5995 prim_subreg #(
5996 .DW (6),
5997 .SwAccess(prim_subreg_pkg::SwAccessRW),
5998 .RESVAL (6'h0),
5999 .Mubi (1'b0)
6000 ) u_mio_periph_insel_4 (
6001 .clk_i (clk_i),
6002 .rst_ni (rst_ni),
6003
6004 // from register interface
6005 .we (mio_periph_insel_4_gated_we),
6006 .wd (mio_periph_insel_4_wd),
6007
6008 // from internal hardware
6009 .de (1'b0),
6010 .d ('0),
6011
6012 // to internal hardware
6013 .qe (),
6014 .q (reg2hw.mio_periph_insel[4].q),
6015 .ds (),
6016
6017 // to register interface (read)
6018 .qs (mio_periph_insel_4_qs)
6019 );
6020
6021
6022 // Subregister 5 of Multireg mio_periph_insel
6023 // R[mio_periph_insel_5]: V(False)
6024 // Create REGWEN-gated WE signal
6025 logic mio_periph_insel_5_gated_we;
6026 1/1 assign mio_periph_insel_5_gated_we = mio_periph_insel_5_we & mio_periph_insel_regwen_5_qs;
Tests: T25 T27 T42
6027 prim_subreg #(
6028 .DW (6),
6029 .SwAccess(prim_subreg_pkg::SwAccessRW),
6030 .RESVAL (6'h0),
6031 .Mubi (1'b0)
6032 ) u_mio_periph_insel_5 (
6033 .clk_i (clk_i),
6034 .rst_ni (rst_ni),
6035
6036 // from register interface
6037 .we (mio_periph_insel_5_gated_we),
6038 .wd (mio_periph_insel_5_wd),
6039
6040 // from internal hardware
6041 .de (1'b0),
6042 .d ('0),
6043
6044 // to internal hardware
6045 .qe (),
6046 .q (reg2hw.mio_periph_insel[5].q),
6047 .ds (),
6048
6049 // to register interface (read)
6050 .qs (mio_periph_insel_5_qs)
6051 );
6052
6053
6054 // Subregister 6 of Multireg mio_periph_insel
6055 // R[mio_periph_insel_6]: V(False)
6056 // Create REGWEN-gated WE signal
6057 logic mio_periph_insel_6_gated_we;
6058 1/1 assign mio_periph_insel_6_gated_we = mio_periph_insel_6_we & mio_periph_insel_regwen_6_qs;
Tests: T25 T27 T42
6059 prim_subreg #(
6060 .DW (6),
6061 .SwAccess(prim_subreg_pkg::SwAccessRW),
6062 .RESVAL (6'h0),
6063 .Mubi (1'b0)
6064 ) u_mio_periph_insel_6 (
6065 .clk_i (clk_i),
6066 .rst_ni (rst_ni),
6067
6068 // from register interface
6069 .we (mio_periph_insel_6_gated_we),
6070 .wd (mio_periph_insel_6_wd),
6071
6072 // from internal hardware
6073 .de (1'b0),
6074 .d ('0),
6075
6076 // to internal hardware
6077 .qe (),
6078 .q (reg2hw.mio_periph_insel[6].q),
6079 .ds (),
6080
6081 // to register interface (read)
6082 .qs (mio_periph_insel_6_qs)
6083 );
6084
6085
6086 // Subregister 7 of Multireg mio_periph_insel
6087 // R[mio_periph_insel_7]: V(False)
6088 // Create REGWEN-gated WE signal
6089 logic mio_periph_insel_7_gated_we;
6090 1/1 assign mio_periph_insel_7_gated_we = mio_periph_insel_7_we & mio_periph_insel_regwen_7_qs;
Tests: T25 T27 T42
6091 prim_subreg #(
6092 .DW (6),
6093 .SwAccess(prim_subreg_pkg::SwAccessRW),
6094 .RESVAL (6'h0),
6095 .Mubi (1'b0)
6096 ) u_mio_periph_insel_7 (
6097 .clk_i (clk_i),
6098 .rst_ni (rst_ni),
6099
6100 // from register interface
6101 .we (mio_periph_insel_7_gated_we),
6102 .wd (mio_periph_insel_7_wd),
6103
6104 // from internal hardware
6105 .de (1'b0),
6106 .d ('0),
6107
6108 // to internal hardware
6109 .qe (),
6110 .q (reg2hw.mio_periph_insel[7].q),
6111 .ds (),
6112
6113 // to register interface (read)
6114 .qs (mio_periph_insel_7_qs)
6115 );
6116
6117
6118 // Subregister 8 of Multireg mio_periph_insel
6119 // R[mio_periph_insel_8]: V(False)
6120 // Create REGWEN-gated WE signal
6121 logic mio_periph_insel_8_gated_we;
6122 1/1 assign mio_periph_insel_8_gated_we = mio_periph_insel_8_we & mio_periph_insel_regwen_8_qs;
Tests: T25 T27 T42
6123 prim_subreg #(
6124 .DW (6),
6125 .SwAccess(prim_subreg_pkg::SwAccessRW),
6126 .RESVAL (6'h0),
6127 .Mubi (1'b0)
6128 ) u_mio_periph_insel_8 (
6129 .clk_i (clk_i),
6130 .rst_ni (rst_ni),
6131
6132 // from register interface
6133 .we (mio_periph_insel_8_gated_we),
6134 .wd (mio_periph_insel_8_wd),
6135
6136 // from internal hardware
6137 .de (1'b0),
6138 .d ('0),
6139
6140 // to internal hardware
6141 .qe (),
6142 .q (reg2hw.mio_periph_insel[8].q),
6143 .ds (),
6144
6145 // to register interface (read)
6146 .qs (mio_periph_insel_8_qs)
6147 );
6148
6149
6150 // Subregister 9 of Multireg mio_periph_insel
6151 // R[mio_periph_insel_9]: V(False)
6152 // Create REGWEN-gated WE signal
6153 logic mio_periph_insel_9_gated_we;
6154 1/1 assign mio_periph_insel_9_gated_we = mio_periph_insel_9_we & mio_periph_insel_regwen_9_qs;
Tests: T27 T42 T43
6155 prim_subreg #(
6156 .DW (6),
6157 .SwAccess(prim_subreg_pkg::SwAccessRW),
6158 .RESVAL (6'h0),
6159 .Mubi (1'b0)
6160 ) u_mio_periph_insel_9 (
6161 .clk_i (clk_i),
6162 .rst_ni (rst_ni),
6163
6164 // from register interface
6165 .we (mio_periph_insel_9_gated_we),
6166 .wd (mio_periph_insel_9_wd),
6167
6168 // from internal hardware
6169 .de (1'b0),
6170 .d ('0),
6171
6172 // to internal hardware
6173 .qe (),
6174 .q (reg2hw.mio_periph_insel[9].q),
6175 .ds (),
6176
6177 // to register interface (read)
6178 .qs (mio_periph_insel_9_qs)
6179 );
6180
6181
6182 // Subregister 10 of Multireg mio_periph_insel
6183 // R[mio_periph_insel_10]: V(False)
6184 // Create REGWEN-gated WE signal
6185 logic mio_periph_insel_10_gated_we;
6186 1/1 assign mio_periph_insel_10_gated_we = mio_periph_insel_10_we & mio_periph_insel_regwen_10_qs;
Tests: T27 T42 T43
6187 prim_subreg #(
6188 .DW (6),
6189 .SwAccess(prim_subreg_pkg::SwAccessRW),
6190 .RESVAL (6'h0),
6191 .Mubi (1'b0)
6192 ) u_mio_periph_insel_10 (
6193 .clk_i (clk_i),
6194 .rst_ni (rst_ni),
6195
6196 // from register interface
6197 .we (mio_periph_insel_10_gated_we),
6198 .wd (mio_periph_insel_10_wd),
6199
6200 // from internal hardware
6201 .de (1'b0),
6202 .d ('0),
6203
6204 // to internal hardware
6205 .qe (),
6206 .q (reg2hw.mio_periph_insel[10].q),
6207 .ds (),
6208
6209 // to register interface (read)
6210 .qs (mio_periph_insel_10_qs)
6211 );
6212
6213
6214 // Subregister 11 of Multireg mio_periph_insel
6215 // R[mio_periph_insel_11]: V(False)
6216 // Create REGWEN-gated WE signal
6217 logic mio_periph_insel_11_gated_we;
6218 1/1 assign mio_periph_insel_11_gated_we = mio_periph_insel_11_we & mio_periph_insel_regwen_11_qs;
Tests: T27 T42 T43
6219 prim_subreg #(
6220 .DW (6),
6221 .SwAccess(prim_subreg_pkg::SwAccessRW),
6222 .RESVAL (6'h0),
6223 .Mubi (1'b0)
6224 ) u_mio_periph_insel_11 (
6225 .clk_i (clk_i),
6226 .rst_ni (rst_ni),
6227
6228 // from register interface
6229 .we (mio_periph_insel_11_gated_we),
6230 .wd (mio_periph_insel_11_wd),
6231
6232 // from internal hardware
6233 .de (1'b0),
6234 .d ('0),
6235
6236 // to internal hardware
6237 .qe (),
6238 .q (reg2hw.mio_periph_insel[11].q),
6239 .ds (),
6240
6241 // to register interface (read)
6242 .qs (mio_periph_insel_11_qs)
6243 );
6244
6245
6246 // Subregister 12 of Multireg mio_periph_insel
6247 // R[mio_periph_insel_12]: V(False)
6248 // Create REGWEN-gated WE signal
6249 logic mio_periph_insel_12_gated_we;
6250 1/1 assign mio_periph_insel_12_gated_we = mio_periph_insel_12_we & mio_periph_insel_regwen_12_qs;
Tests: T27 T42 T43
6251 prim_subreg #(
6252 .DW (6),
6253 .SwAccess(prim_subreg_pkg::SwAccessRW),
6254 .RESVAL (6'h0),
6255 .Mubi (1'b0)
6256 ) u_mio_periph_insel_12 (
6257 .clk_i (clk_i),
6258 .rst_ni (rst_ni),
6259
6260 // from register interface
6261 .we (mio_periph_insel_12_gated_we),
6262 .wd (mio_periph_insel_12_wd),
6263
6264 // from internal hardware
6265 .de (1'b0),
6266 .d ('0),
6267
6268 // to internal hardware
6269 .qe (),
6270 .q (reg2hw.mio_periph_insel[12].q),
6271 .ds (),
6272
6273 // to register interface (read)
6274 .qs (mio_periph_insel_12_qs)
6275 );
6276
6277
6278 // Subregister 13 of Multireg mio_periph_insel
6279 // R[mio_periph_insel_13]: V(False)
6280 // Create REGWEN-gated WE signal
6281 logic mio_periph_insel_13_gated_we;
6282 1/1 assign mio_periph_insel_13_gated_we = mio_periph_insel_13_we & mio_periph_insel_regwen_13_qs;
Tests: T27 T42 T43
6283 prim_subreg #(
6284 .DW (6),
6285 .SwAccess(prim_subreg_pkg::SwAccessRW),
6286 .RESVAL (6'h0),
6287 .Mubi (1'b0)
6288 ) u_mio_periph_insel_13 (
6289 .clk_i (clk_i),
6290 .rst_ni (rst_ni),
6291
6292 // from register interface
6293 .we (mio_periph_insel_13_gated_we),
6294 .wd (mio_periph_insel_13_wd),
6295
6296 // from internal hardware
6297 .de (1'b0),
6298 .d ('0),
6299
6300 // to internal hardware
6301 .qe (),
6302 .q (reg2hw.mio_periph_insel[13].q),
6303 .ds (),
6304
6305 // to register interface (read)
6306 .qs (mio_periph_insel_13_qs)
6307 );
6308
6309
6310 // Subregister 14 of Multireg mio_periph_insel
6311 // R[mio_periph_insel_14]: V(False)
6312 // Create REGWEN-gated WE signal
6313 logic mio_periph_insel_14_gated_we;
6314 1/1 assign mio_periph_insel_14_gated_we = mio_periph_insel_14_we & mio_periph_insel_regwen_14_qs;
Tests: T27 T42 T43
6315 prim_subreg #(
6316 .DW (6),
6317 .SwAccess(prim_subreg_pkg::SwAccessRW),
6318 .RESVAL (6'h0),
6319 .Mubi (1'b0)
6320 ) u_mio_periph_insel_14 (
6321 .clk_i (clk_i),
6322 .rst_ni (rst_ni),
6323
6324 // from register interface
6325 .we (mio_periph_insel_14_gated_we),
6326 .wd (mio_periph_insel_14_wd),
6327
6328 // from internal hardware
6329 .de (1'b0),
6330 .d ('0),
6331
6332 // to internal hardware
6333 .qe (),
6334 .q (reg2hw.mio_periph_insel[14].q),
6335 .ds (),
6336
6337 // to register interface (read)
6338 .qs (mio_periph_insel_14_qs)
6339 );
6340
6341
6342 // Subregister 15 of Multireg mio_periph_insel
6343 // R[mio_periph_insel_15]: V(False)
6344 // Create REGWEN-gated WE signal
6345 logic mio_periph_insel_15_gated_we;
6346 1/1 assign mio_periph_insel_15_gated_we = mio_periph_insel_15_we & mio_periph_insel_regwen_15_qs;
Tests: T27 T42 T43
6347 prim_subreg #(
6348 .DW (6),
6349 .SwAccess(prim_subreg_pkg::SwAccessRW),
6350 .RESVAL (6'h0),
6351 .Mubi (1'b0)
6352 ) u_mio_periph_insel_15 (
6353 .clk_i (clk_i),
6354 .rst_ni (rst_ni),
6355
6356 // from register interface
6357 .we (mio_periph_insel_15_gated_we),
6358 .wd (mio_periph_insel_15_wd),
6359
6360 // from internal hardware
6361 .de (1'b0),
6362 .d ('0),
6363
6364 // to internal hardware
6365 .qe (),
6366 .q (reg2hw.mio_periph_insel[15].q),
6367 .ds (),
6368
6369 // to register interface (read)
6370 .qs (mio_periph_insel_15_qs)
6371 );
6372
6373
6374 // Subregister 16 of Multireg mio_periph_insel
6375 // R[mio_periph_insel_16]: V(False)
6376 // Create REGWEN-gated WE signal
6377 logic mio_periph_insel_16_gated_we;
6378 1/1 assign mio_periph_insel_16_gated_we = mio_periph_insel_16_we & mio_periph_insel_regwen_16_qs;
Tests: T27 T42 T43
6379 prim_subreg #(
6380 .DW (6),
6381 .SwAccess(prim_subreg_pkg::SwAccessRW),
6382 .RESVAL (6'h0),
6383 .Mubi (1'b0)
6384 ) u_mio_periph_insel_16 (
6385 .clk_i (clk_i),
6386 .rst_ni (rst_ni),
6387
6388 // from register interface
6389 .we (mio_periph_insel_16_gated_we),
6390 .wd (mio_periph_insel_16_wd),
6391
6392 // from internal hardware
6393 .de (1'b0),
6394 .d ('0),
6395
6396 // to internal hardware
6397 .qe (),
6398 .q (reg2hw.mio_periph_insel[16].q),
6399 .ds (),
6400
6401 // to register interface (read)
6402 .qs (mio_periph_insel_16_qs)
6403 );
6404
6405
6406 // Subregister 17 of Multireg mio_periph_insel
6407 // R[mio_periph_insel_17]: V(False)
6408 // Create REGWEN-gated WE signal
6409 logic mio_periph_insel_17_gated_we;
6410 1/1 assign mio_periph_insel_17_gated_we = mio_periph_insel_17_we & mio_periph_insel_regwen_17_qs;
Tests: T27 T42 T43
6411 prim_subreg #(
6412 .DW (6),
6413 .SwAccess(prim_subreg_pkg::SwAccessRW),
6414 .RESVAL (6'h0),
6415 .Mubi (1'b0)
6416 ) u_mio_periph_insel_17 (
6417 .clk_i (clk_i),
6418 .rst_ni (rst_ni),
6419
6420 // from register interface
6421 .we (mio_periph_insel_17_gated_we),
6422 .wd (mio_periph_insel_17_wd),
6423
6424 // from internal hardware
6425 .de (1'b0),
6426 .d ('0),
6427
6428 // to internal hardware
6429 .qe (),
6430 .q (reg2hw.mio_periph_insel[17].q),
6431 .ds (),
6432
6433 // to register interface (read)
6434 .qs (mio_periph_insel_17_qs)
6435 );
6436
6437
6438 // Subregister 18 of Multireg mio_periph_insel
6439 // R[mio_periph_insel_18]: V(False)
6440 // Create REGWEN-gated WE signal
6441 logic mio_periph_insel_18_gated_we;
6442 1/1 assign mio_periph_insel_18_gated_we = mio_periph_insel_18_we & mio_periph_insel_regwen_18_qs;
Tests: T27 T42 T43
6443 prim_subreg #(
6444 .DW (6),
6445 .SwAccess(prim_subreg_pkg::SwAccessRW),
6446 .RESVAL (6'h0),
6447 .Mubi (1'b0)
6448 ) u_mio_periph_insel_18 (
6449 .clk_i (clk_i),
6450 .rst_ni (rst_ni),
6451
6452 // from register interface
6453 .we (mio_periph_insel_18_gated_we),
6454 .wd (mio_periph_insel_18_wd),
6455
6456 // from internal hardware
6457 .de (1'b0),
6458 .d ('0),
6459
6460 // to internal hardware
6461 .qe (),
6462 .q (reg2hw.mio_periph_insel[18].q),
6463 .ds (),
6464
6465 // to register interface (read)
6466 .qs (mio_periph_insel_18_qs)
6467 );
6468
6469
6470 // Subregister 19 of Multireg mio_periph_insel
6471 // R[mio_periph_insel_19]: V(False)
6472 // Create REGWEN-gated WE signal
6473 logic mio_periph_insel_19_gated_we;
6474 1/1 assign mio_periph_insel_19_gated_we = mio_periph_insel_19_we & mio_periph_insel_regwen_19_qs;
Tests: T27 T42 T43
6475 prim_subreg #(
6476 .DW (6),
6477 .SwAccess(prim_subreg_pkg::SwAccessRW),
6478 .RESVAL (6'h0),
6479 .Mubi (1'b0)
6480 ) u_mio_periph_insel_19 (
6481 .clk_i (clk_i),
6482 .rst_ni (rst_ni),
6483
6484 // from register interface
6485 .we (mio_periph_insel_19_gated_we),
6486 .wd (mio_periph_insel_19_wd),
6487
6488 // from internal hardware
6489 .de (1'b0),
6490 .d ('0),
6491
6492 // to internal hardware
6493 .qe (),
6494 .q (reg2hw.mio_periph_insel[19].q),
6495 .ds (),
6496
6497 // to register interface (read)
6498 .qs (mio_periph_insel_19_qs)
6499 );
6500
6501
6502 // Subregister 20 of Multireg mio_periph_insel
6503 // R[mio_periph_insel_20]: V(False)
6504 // Create REGWEN-gated WE signal
6505 logic mio_periph_insel_20_gated_we;
6506 1/1 assign mio_periph_insel_20_gated_we = mio_periph_insel_20_we & mio_periph_insel_regwen_20_qs;
Tests: T27 T42 T43
6507 prim_subreg #(
6508 .DW (6),
6509 .SwAccess(prim_subreg_pkg::SwAccessRW),
6510 .RESVAL (6'h0),
6511 .Mubi (1'b0)
6512 ) u_mio_periph_insel_20 (
6513 .clk_i (clk_i),
6514 .rst_ni (rst_ni),
6515
6516 // from register interface
6517 .we (mio_periph_insel_20_gated_we),
6518 .wd (mio_periph_insel_20_wd),
6519
6520 // from internal hardware
6521 .de (1'b0),
6522 .d ('0),
6523
6524 // to internal hardware
6525 .qe (),
6526 .q (reg2hw.mio_periph_insel[20].q),
6527 .ds (),
6528
6529 // to register interface (read)
6530 .qs (mio_periph_insel_20_qs)
6531 );
6532
6533
6534 // Subregister 21 of Multireg mio_periph_insel
6535 // R[mio_periph_insel_21]: V(False)
6536 // Create REGWEN-gated WE signal
6537 logic mio_periph_insel_21_gated_we;
6538 1/1 assign mio_periph_insel_21_gated_we = mio_periph_insel_21_we & mio_periph_insel_regwen_21_qs;
Tests: T27 T42 T43
6539 prim_subreg #(
6540 .DW (6),
6541 .SwAccess(prim_subreg_pkg::SwAccessRW),
6542 .RESVAL (6'h0),
6543 .Mubi (1'b0)
6544 ) u_mio_periph_insel_21 (
6545 .clk_i (clk_i),
6546 .rst_ni (rst_ni),
6547
6548 // from register interface
6549 .we (mio_periph_insel_21_gated_we),
6550 .wd (mio_periph_insel_21_wd),
6551
6552 // from internal hardware
6553 .de (1'b0),
6554 .d ('0),
6555
6556 // to internal hardware
6557 .qe (),
6558 .q (reg2hw.mio_periph_insel[21].q),
6559 .ds (),
6560
6561 // to register interface (read)
6562 .qs (mio_periph_insel_21_qs)
6563 );
6564
6565
6566 // Subregister 22 of Multireg mio_periph_insel
6567 // R[mio_periph_insel_22]: V(False)
6568 // Create REGWEN-gated WE signal
6569 logic mio_periph_insel_22_gated_we;
6570 1/1 assign mio_periph_insel_22_gated_we = mio_periph_insel_22_we & mio_periph_insel_regwen_22_qs;
Tests: T1 T2 T3
6571 prim_subreg #(
6572 .DW (6),
6573 .SwAccess(prim_subreg_pkg::SwAccessRW),
6574 .RESVAL (6'h0),
6575 .Mubi (1'b0)
6576 ) u_mio_periph_insel_22 (
6577 .clk_i (clk_i),
6578 .rst_ni (rst_ni),
6579
6580 // from register interface
6581 .we (mio_periph_insel_22_gated_we),
6582 .wd (mio_periph_insel_22_wd),
6583
6584 // from internal hardware
6585 .de (1'b0),
6586 .d ('0),
6587
6588 // to internal hardware
6589 .qe (),
6590 .q (reg2hw.mio_periph_insel[22].q),
6591 .ds (),
6592
6593 // to register interface (read)
6594 .qs (mio_periph_insel_22_qs)
6595 );
6596
6597
6598 // Subregister 23 of Multireg mio_periph_insel
6599 // R[mio_periph_insel_23]: V(False)
6600 // Create REGWEN-gated WE signal
6601 logic mio_periph_insel_23_gated_we;
6602 1/1 assign mio_periph_insel_23_gated_we = mio_periph_insel_23_we & mio_periph_insel_regwen_23_qs;
Tests: T1 T2 T3
6603 prim_subreg #(
6604 .DW (6),
6605 .SwAccess(prim_subreg_pkg::SwAccessRW),
6606 .RESVAL (6'h0),
6607 .Mubi (1'b0)
6608 ) u_mio_periph_insel_23 (
6609 .clk_i (clk_i),
6610 .rst_ni (rst_ni),
6611
6612 // from register interface
6613 .we (mio_periph_insel_23_gated_we),
6614 .wd (mio_periph_insel_23_wd),
6615
6616 // from internal hardware
6617 .de (1'b0),
6618 .d ('0),
6619
6620 // to internal hardware
6621 .qe (),
6622 .q (reg2hw.mio_periph_insel[23].q),
6623 .ds (),
6624
6625 // to register interface (read)
6626 .qs (mio_periph_insel_23_qs)
6627 );
6628
6629
6630 // Subregister 24 of Multireg mio_periph_insel
6631 // R[mio_periph_insel_24]: V(False)
6632 // Create REGWEN-gated WE signal
6633 logic mio_periph_insel_24_gated_we;
6634 1/1 assign mio_periph_insel_24_gated_we = mio_periph_insel_24_we & mio_periph_insel_regwen_24_qs;
Tests: T1 T2 T3
6635 prim_subreg #(
6636 .DW (6),
6637 .SwAccess(prim_subreg_pkg::SwAccessRW),
6638 .RESVAL (6'h0),
6639 .Mubi (1'b0)
6640 ) u_mio_periph_insel_24 (
6641 .clk_i (clk_i),
6642 .rst_ni (rst_ni),
6643
6644 // from register interface
6645 .we (mio_periph_insel_24_gated_we),
6646 .wd (mio_periph_insel_24_wd),
6647
6648 // from internal hardware
6649 .de (1'b0),
6650 .d ('0),
6651
6652 // to internal hardware
6653 .qe (),
6654 .q (reg2hw.mio_periph_insel[24].q),
6655 .ds (),
6656
6657 // to register interface (read)
6658 .qs (mio_periph_insel_24_qs)
6659 );
6660
6661
6662 // Subregister 25 of Multireg mio_periph_insel
6663 // R[mio_periph_insel_25]: V(False)
6664 // Create REGWEN-gated WE signal
6665 logic mio_periph_insel_25_gated_we;
6666 1/1 assign mio_periph_insel_25_gated_we = mio_periph_insel_25_we & mio_periph_insel_regwen_25_qs;
Tests: T27 T42 T43
6667 prim_subreg #(
6668 .DW (6),
6669 .SwAccess(prim_subreg_pkg::SwAccessRW),
6670 .RESVAL (6'h0),
6671 .Mubi (1'b0)
6672 ) u_mio_periph_insel_25 (
6673 .clk_i (clk_i),
6674 .rst_ni (rst_ni),
6675
6676 // from register interface
6677 .we (mio_periph_insel_25_gated_we),
6678 .wd (mio_periph_insel_25_wd),
6679
6680 // from internal hardware
6681 .de (1'b0),
6682 .d ('0),
6683
6684 // to internal hardware
6685 .qe (),
6686 .q (reg2hw.mio_periph_insel[25].q),
6687 .ds (),
6688
6689 // to register interface (read)
6690 .qs (mio_periph_insel_25_qs)
6691 );
6692
6693
6694 // Subregister 26 of Multireg mio_periph_insel
6695 // R[mio_periph_insel_26]: V(False)
6696 // Create REGWEN-gated WE signal
6697 logic mio_periph_insel_26_gated_we;
6698 1/1 assign mio_periph_insel_26_gated_we = mio_periph_insel_26_we & mio_periph_insel_regwen_26_qs;
Tests: T27 T42 T43
6699 prim_subreg #(
6700 .DW (6),
6701 .SwAccess(prim_subreg_pkg::SwAccessRW),
6702 .RESVAL (6'h0),
6703 .Mubi (1'b0)
6704 ) u_mio_periph_insel_26 (
6705 .clk_i (clk_i),
6706 .rst_ni (rst_ni),
6707
6708 // from register interface
6709 .we (mio_periph_insel_26_gated_we),
6710 .wd (mio_periph_insel_26_wd),
6711
6712 // from internal hardware
6713 .de (1'b0),
6714 .d ('0),
6715
6716 // to internal hardware
6717 .qe (),
6718 .q (reg2hw.mio_periph_insel[26].q),
6719 .ds (),
6720
6721 // to register interface (read)
6722 .qs (mio_periph_insel_26_qs)
6723 );
6724
6725
6726 // Subregister 27 of Multireg mio_periph_insel
6727 // R[mio_periph_insel_27]: V(False)
6728 // Create REGWEN-gated WE signal
6729 logic mio_periph_insel_27_gated_we;
6730 1/1 assign mio_periph_insel_27_gated_we = mio_periph_insel_27_we & mio_periph_insel_regwen_27_qs;
Tests: T27 T42 T43
6731 prim_subreg #(
6732 .DW (6),
6733 .SwAccess(prim_subreg_pkg::SwAccessRW),
6734 .RESVAL (6'h0),
6735 .Mubi (1'b0)
6736 ) u_mio_periph_insel_27 (
6737 .clk_i (clk_i),
6738 .rst_ni (rst_ni),
6739
6740 // from register interface
6741 .we (mio_periph_insel_27_gated_we),
6742 .wd (mio_periph_insel_27_wd),
6743
6744 // from internal hardware
6745 .de (1'b0),
6746 .d ('0),
6747
6748 // to internal hardware
6749 .qe (),
6750 .q (reg2hw.mio_periph_insel[27].q),
6751 .ds (),
6752
6753 // to register interface (read)
6754 .qs (mio_periph_insel_27_qs)
6755 );
6756
6757
6758 // Subregister 28 of Multireg mio_periph_insel
6759 // R[mio_periph_insel_28]: V(False)
6760 // Create REGWEN-gated WE signal
6761 logic mio_periph_insel_28_gated_we;
6762 1/1 assign mio_periph_insel_28_gated_we = mio_periph_insel_28_we & mio_periph_insel_regwen_28_qs;
Tests: T27 T42 T43
6763 prim_subreg #(
6764 .DW (6),
6765 .SwAccess(prim_subreg_pkg::SwAccessRW),
6766 .RESVAL (6'h0),
6767 .Mubi (1'b0)
6768 ) u_mio_periph_insel_28 (
6769 .clk_i (clk_i),
6770 .rst_ni (rst_ni),
6771
6772 // from register interface
6773 .we (mio_periph_insel_28_gated_we),
6774 .wd (mio_periph_insel_28_wd),
6775
6776 // from internal hardware
6777 .de (1'b0),
6778 .d ('0),
6779
6780 // to internal hardware
6781 .qe (),
6782 .q (reg2hw.mio_periph_insel[28].q),
6783 .ds (),
6784
6785 // to register interface (read)
6786 .qs (mio_periph_insel_28_qs)
6787 );
6788
6789
6790 // Subregister 29 of Multireg mio_periph_insel
6791 // R[mio_periph_insel_29]: V(False)
6792 // Create REGWEN-gated WE signal
6793 logic mio_periph_insel_29_gated_we;
6794 1/1 assign mio_periph_insel_29_gated_we = mio_periph_insel_29_we & mio_periph_insel_regwen_29_qs;
Tests: T27 T42 T43
6795 prim_subreg #(
6796 .DW (6),
6797 .SwAccess(prim_subreg_pkg::SwAccessRW),
6798 .RESVAL (6'h0),
6799 .Mubi (1'b0)
6800 ) u_mio_periph_insel_29 (
6801 .clk_i (clk_i),
6802 .rst_ni (rst_ni),
6803
6804 // from register interface
6805 .we (mio_periph_insel_29_gated_we),
6806 .wd (mio_periph_insel_29_wd),
6807
6808 // from internal hardware
6809 .de (1'b0),
6810 .d ('0),
6811
6812 // to internal hardware
6813 .qe (),
6814 .q (reg2hw.mio_periph_insel[29].q),
6815 .ds (),
6816
6817 // to register interface (read)
6818 .qs (mio_periph_insel_29_qs)
6819 );
6820
6821
6822 // Subregister 30 of Multireg mio_periph_insel
6823 // R[mio_periph_insel_30]: V(False)
6824 // Create REGWEN-gated WE signal
6825 logic mio_periph_insel_30_gated_we;
6826 1/1 assign mio_periph_insel_30_gated_we = mio_periph_insel_30_we & mio_periph_insel_regwen_30_qs;
Tests: T27 T42 T43
6827 prim_subreg #(
6828 .DW (6),
6829 .SwAccess(prim_subreg_pkg::SwAccessRW),
6830 .RESVAL (6'h0),
6831 .Mubi (1'b0)
6832 ) u_mio_periph_insel_30 (
6833 .clk_i (clk_i),
6834 .rst_ni (rst_ni),
6835
6836 // from register interface
6837 .we (mio_periph_insel_30_gated_we),
6838 .wd (mio_periph_insel_30_wd),
6839
6840 // from internal hardware
6841 .de (1'b0),
6842 .d ('0),
6843
6844 // to internal hardware
6845 .qe (),
6846 .q (reg2hw.mio_periph_insel[30].q),
6847 .ds (),
6848
6849 // to register interface (read)
6850 .qs (mio_periph_insel_30_qs)
6851 );
6852
6853
6854 // Subregister 31 of Multireg mio_periph_insel
6855 // R[mio_periph_insel_31]: V(False)
6856 // Create REGWEN-gated WE signal
6857 logic mio_periph_insel_31_gated_we;
6858 1/1 assign mio_periph_insel_31_gated_we = mio_periph_insel_31_we & mio_periph_insel_regwen_31_qs;
Tests: T27 T42 T43
6859 prim_subreg #(
6860 .DW (6),
6861 .SwAccess(prim_subreg_pkg::SwAccessRW),
6862 .RESVAL (6'h0),
6863 .Mubi (1'b0)
6864 ) u_mio_periph_insel_31 (
6865 .clk_i (clk_i),
6866 .rst_ni (rst_ni),
6867
6868 // from register interface
6869 .we (mio_periph_insel_31_gated_we),
6870 .wd (mio_periph_insel_31_wd),
6871
6872 // from internal hardware
6873 .de (1'b0),
6874 .d ('0),
6875
6876 // to internal hardware
6877 .qe (),
6878 .q (reg2hw.mio_periph_insel[31].q),
6879 .ds (),
6880
6881 // to register interface (read)
6882 .qs (mio_periph_insel_31_qs)
6883 );
6884
6885
6886 // Subregister 32 of Multireg mio_periph_insel
6887 // R[mio_periph_insel_32]: V(False)
6888 // Create REGWEN-gated WE signal
6889 logic mio_periph_insel_32_gated_we;
6890 1/1 assign mio_periph_insel_32_gated_we = mio_periph_insel_32_we & mio_periph_insel_regwen_32_qs;
Tests: T62 T37 T63
6891 prim_subreg #(
6892 .DW (6),
6893 .SwAccess(prim_subreg_pkg::SwAccessRW),
6894 .RESVAL (6'h0),
6895 .Mubi (1'b0)
6896 ) u_mio_periph_insel_32 (
6897 .clk_i (clk_i),
6898 .rst_ni (rst_ni),
6899
6900 // from register interface
6901 .we (mio_periph_insel_32_gated_we),
6902 .wd (mio_periph_insel_32_wd),
6903
6904 // from internal hardware
6905 .de (1'b0),
6906 .d ('0),
6907
6908 // to internal hardware
6909 .qe (),
6910 .q (reg2hw.mio_periph_insel[32].q),
6911 .ds (),
6912
6913 // to register interface (read)
6914 .qs (mio_periph_insel_32_qs)
6915 );
6916
6917
6918 // Subregister 33 of Multireg mio_periph_insel
6919 // R[mio_periph_insel_33]: V(False)
6920 // Create REGWEN-gated WE signal
6921 logic mio_periph_insel_33_gated_we;
6922 1/1 assign mio_periph_insel_33_gated_we = mio_periph_insel_33_we & mio_periph_insel_regwen_33_qs;
Tests: T62 T37 T63
6923 prim_subreg #(
6924 .DW (6),
6925 .SwAccess(prim_subreg_pkg::SwAccessRW),
6926 .RESVAL (6'h0),
6927 .Mubi (1'b0)
6928 ) u_mio_periph_insel_33 (
6929 .clk_i (clk_i),
6930 .rst_ni (rst_ni),
6931
6932 // from register interface
6933 .we (mio_periph_insel_33_gated_we),
6934 .wd (mio_periph_insel_33_wd),
6935
6936 // from internal hardware
6937 .de (1'b0),
6938 .d ('0),
6939
6940 // to internal hardware
6941 .qe (),
6942 .q (reg2hw.mio_periph_insel[33].q),
6943 .ds (),
6944
6945 // to register interface (read)
6946 .qs (mio_periph_insel_33_qs)
6947 );
6948
6949
6950 // Subregister 34 of Multireg mio_periph_insel
6951 // R[mio_periph_insel_34]: V(False)
6952 // Create REGWEN-gated WE signal
6953 logic mio_periph_insel_34_gated_we;
6954 1/1 assign mio_periph_insel_34_gated_we = mio_periph_insel_34_we & mio_periph_insel_regwen_34_qs;
Tests: T64 T65 T37
6955 prim_subreg #(
6956 .DW (6),
6957 .SwAccess(prim_subreg_pkg::SwAccessRW),
6958 .RESVAL (6'h0),
6959 .Mubi (1'b0)
6960 ) u_mio_periph_insel_34 (
6961 .clk_i (clk_i),
6962 .rst_ni (rst_ni),
6963
6964 // from register interface
6965 .we (mio_periph_insel_34_gated_we),
6966 .wd (mio_periph_insel_34_wd),
6967
6968 // from internal hardware
6969 .de (1'b0),
6970 .d ('0),
6971
6972 // to internal hardware
6973 .qe (),
6974 .q (reg2hw.mio_periph_insel[34].q),
6975 .ds (),
6976
6977 // to register interface (read)
6978 .qs (mio_periph_insel_34_qs)
6979 );
6980
6981
6982 // Subregister 35 of Multireg mio_periph_insel
6983 // R[mio_periph_insel_35]: V(False)
6984 // Create REGWEN-gated WE signal
6985 logic mio_periph_insel_35_gated_we;
6986 1/1 assign mio_periph_insel_35_gated_we = mio_periph_insel_35_we & mio_periph_insel_regwen_35_qs;
Tests: T64 T65 T37
6987 prim_subreg #(
6988 .DW (6),
6989 .SwAccess(prim_subreg_pkg::SwAccessRW),
6990 .RESVAL (6'h0),
6991 .Mubi (1'b0)
6992 ) u_mio_periph_insel_35 (
6993 .clk_i (clk_i),
6994 .rst_ni (rst_ni),
6995
6996 // from register interface
6997 .we (mio_periph_insel_35_gated_we),
6998 .wd (mio_periph_insel_35_wd),
6999
7000 // from internal hardware
7001 .de (1'b0),
7002 .d ('0),
7003
7004 // to internal hardware
7005 .qe (),
7006 .q (reg2hw.mio_periph_insel[35].q),
7007 .ds (),
7008
7009 // to register interface (read)
7010 .qs (mio_periph_insel_35_qs)
7011 );
7012
7013
7014 // Subregister 36 of Multireg mio_periph_insel
7015 // R[mio_periph_insel_36]: V(False)
7016 // Create REGWEN-gated WE signal
7017 logic mio_periph_insel_36_gated_we;
7018 1/1 assign mio_periph_insel_36_gated_we = mio_periph_insel_36_we & mio_periph_insel_regwen_36_qs;
Tests: T66 T37 T67
7019 prim_subreg #(
7020 .DW (6),
7021 .SwAccess(prim_subreg_pkg::SwAccessRW),
7022 .RESVAL (6'h0),
7023 .Mubi (1'b0)
7024 ) u_mio_periph_insel_36 (
7025 .clk_i (clk_i),
7026 .rst_ni (rst_ni),
7027
7028 // from register interface
7029 .we (mio_periph_insel_36_gated_we),
7030 .wd (mio_periph_insel_36_wd),
7031
7032 // from internal hardware
7033 .de (1'b0),
7034 .d ('0),
7035
7036 // to internal hardware
7037 .qe (),
7038 .q (reg2hw.mio_periph_insel[36].q),
7039 .ds (),
7040
7041 // to register interface (read)
7042 .qs (mio_periph_insel_36_qs)
7043 );
7044
7045
7046 // Subregister 37 of Multireg mio_periph_insel
7047 // R[mio_periph_insel_37]: V(False)
7048 // Create REGWEN-gated WE signal
7049 logic mio_periph_insel_37_gated_we;
7050 1/1 assign mio_periph_insel_37_gated_we = mio_periph_insel_37_we & mio_periph_insel_regwen_37_qs;
Tests: T66 T37 T67
7051 prim_subreg #(
7052 .DW (6),
7053 .SwAccess(prim_subreg_pkg::SwAccessRW),
7054 .RESVAL (6'h0),
7055 .Mubi (1'b0)
7056 ) u_mio_periph_insel_37 (
7057 .clk_i (clk_i),
7058 .rst_ni (rst_ni),
7059
7060 // from register interface
7061 .we (mio_periph_insel_37_gated_we),
7062 .wd (mio_periph_insel_37_wd),
7063
7064 // from internal hardware
7065 .de (1'b0),
7066 .d ('0),
7067
7068 // to internal hardware
7069 .qe (),
7070 .q (reg2hw.mio_periph_insel[37].q),
7071 .ds (),
7072
7073 // to register interface (read)
7074 .qs (mio_periph_insel_37_qs)
7075 );
7076
7077
7078 // Subregister 38 of Multireg mio_periph_insel
7079 // R[mio_periph_insel_38]: V(False)
7080 // Create REGWEN-gated WE signal
7081 logic mio_periph_insel_38_gated_we;
7082 1/1 assign mio_periph_insel_38_gated_we = mio_periph_insel_38_we & mio_periph_insel_regwen_38_qs;
Tests: T9 T37 T47
7083 prim_subreg #(
7084 .DW (6),
7085 .SwAccess(prim_subreg_pkg::SwAccessRW),
7086 .RESVAL (6'h0),
7087 .Mubi (1'b0)
7088 ) u_mio_periph_insel_38 (
7089 .clk_i (clk_i),
7090 .rst_ni (rst_ni),
7091
7092 // from register interface
7093 .we (mio_periph_insel_38_gated_we),
7094 .wd (mio_periph_insel_38_wd),
7095
7096 // from internal hardware
7097 .de (1'b0),
7098 .d ('0),
7099
7100 // to internal hardware
7101 .qe (),
7102 .q (reg2hw.mio_periph_insel[38].q),
7103 .ds (),
7104
7105 // to register interface (read)
7106 .qs (mio_periph_insel_38_qs)
7107 );
7108
7109
7110 // Subregister 39 of Multireg mio_periph_insel
7111 // R[mio_periph_insel_39]: V(False)
7112 // Create REGWEN-gated WE signal
7113 logic mio_periph_insel_39_gated_we;
7114 1/1 assign mio_periph_insel_39_gated_we = mio_periph_insel_39_we & mio_periph_insel_regwen_39_qs;
Tests: T9 T37 T47
7115 prim_subreg #(
7116 .DW (6),
7117 .SwAccess(prim_subreg_pkg::SwAccessRW),
7118 .RESVAL (6'h0),
7119 .Mubi (1'b0)
7120 ) u_mio_periph_insel_39 (
7121 .clk_i (clk_i),
7122 .rst_ni (rst_ni),
7123
7124 // from register interface
7125 .we (mio_periph_insel_39_gated_we),
7126 .wd (mio_periph_insel_39_wd),
7127
7128 // from internal hardware
7129 .de (1'b0),
7130 .d ('0),
7131
7132 // to internal hardware
7133 .qe (),
7134 .q (reg2hw.mio_periph_insel[39].q),
7135 .ds (),
7136
7137 // to register interface (read)
7138 .qs (mio_periph_insel_39_qs)
7139 );
7140
7141
7142 // Subregister 40 of Multireg mio_periph_insel
7143 // R[mio_periph_insel_40]: V(False)
7144 // Create REGWEN-gated WE signal
7145 logic mio_periph_insel_40_gated_we;
7146 1/1 assign mio_periph_insel_40_gated_we = mio_periph_insel_40_we & mio_periph_insel_regwen_40_qs;
Tests: T9 T37 T47
7147 prim_subreg #(
7148 .DW (6),
7149 .SwAccess(prim_subreg_pkg::SwAccessRW),
7150 .RESVAL (6'h0),
7151 .Mubi (1'b0)
7152 ) u_mio_periph_insel_40 (
7153 .clk_i (clk_i),
7154 .rst_ni (rst_ni),
7155
7156 // from register interface
7157 .we (mio_periph_insel_40_gated_we),
7158 .wd (mio_periph_insel_40_wd),
7159
7160 // from internal hardware
7161 .de (1'b0),
7162 .d ('0),
7163
7164 // to internal hardware
7165 .qe (),
7166 .q (reg2hw.mio_periph_insel[40].q),
7167 .ds (),
7168
7169 // to register interface (read)
7170 .qs (mio_periph_insel_40_qs)
7171 );
7172
7173
7174 // Subregister 41 of Multireg mio_periph_insel
7175 // R[mio_periph_insel_41]: V(False)
7176 // Create REGWEN-gated WE signal
7177 logic mio_periph_insel_41_gated_we;
7178 1/1 assign mio_periph_insel_41_gated_we = mio_periph_insel_41_we & mio_periph_insel_regwen_41_qs;
Tests: T9 T10 T11
7179 prim_subreg #(
7180 .DW (6),
7181 .SwAccess(prim_subreg_pkg::SwAccessRW),
7182 .RESVAL (6'h0),
7183 .Mubi (1'b0)
7184 ) u_mio_periph_insel_41 (
7185 .clk_i (clk_i),
7186 .rst_ni (rst_ni),
7187
7188 // from register interface
7189 .we (mio_periph_insel_41_gated_we),
7190 .wd (mio_periph_insel_41_wd),
7191
7192 // from internal hardware
7193 .de (1'b0),
7194 .d ('0),
7195
7196 // to internal hardware
7197 .qe (),
7198 .q (reg2hw.mio_periph_insel[41].q),
7199 .ds (),
7200
7201 // to register interface (read)
7202 .qs (mio_periph_insel_41_qs)
7203 );
7204
7205
7206 // Subregister 42 of Multireg mio_periph_insel
7207 // R[mio_periph_insel_42]: V(False)
7208 // Create REGWEN-gated WE signal
7209 logic mio_periph_insel_42_gated_we;
7210 1/1 assign mio_periph_insel_42_gated_we = mio_periph_insel_42_we & mio_periph_insel_regwen_42_qs;
Tests: T1 T2 T3
7211 prim_subreg #(
7212 .DW (6),
7213 .SwAccess(prim_subreg_pkg::SwAccessRW),
7214 .RESVAL (6'h0),
7215 .Mubi (1'b0)
7216 ) u_mio_periph_insel_42 (
7217 .clk_i (clk_i),
7218 .rst_ni (rst_ni),
7219
7220 // from register interface
7221 .we (mio_periph_insel_42_gated_we),
7222 .wd (mio_periph_insel_42_wd),
7223
7224 // from internal hardware
7225 .de (1'b0),
7226 .d ('0),
7227
7228 // to internal hardware
7229 .qe (),
7230 .q (reg2hw.mio_periph_insel[42].q),
7231 .ds (),
7232
7233 // to register interface (read)
7234 .qs (mio_periph_insel_42_qs)
7235 );
7236
7237
7238 // Subregister 43 of Multireg mio_periph_insel
7239 // R[mio_periph_insel_43]: V(False)
7240 // Create REGWEN-gated WE signal
7241 logic mio_periph_insel_43_gated_we;
7242 1/1 assign mio_periph_insel_43_gated_we = mio_periph_insel_43_we & mio_periph_insel_regwen_43_qs;
Tests: T1 T2 T3
7243 prim_subreg #(
7244 .DW (6),
7245 .SwAccess(prim_subreg_pkg::SwAccessRW),
7246 .RESVAL (6'h0),
7247 .Mubi (1'b0)
7248 ) u_mio_periph_insel_43 (
7249 .clk_i (clk_i),
7250 .rst_ni (rst_ni),
7251
7252 // from register interface
7253 .we (mio_periph_insel_43_gated_we),
7254 .wd (mio_periph_insel_43_wd),
7255
7256 // from internal hardware
7257 .de (1'b0),
7258 .d ('0),
7259
7260 // to internal hardware
7261 .qe (),
7262 .q (reg2hw.mio_periph_insel[43].q),
7263 .ds (),
7264
7265 // to register interface (read)
7266 .qs (mio_periph_insel_43_qs)
7267 );
7268
7269
7270 // Subregister 44 of Multireg mio_periph_insel
7271 // R[mio_periph_insel_44]: V(False)
7272 // Create REGWEN-gated WE signal
7273 logic mio_periph_insel_44_gated_we;
7274 1/1 assign mio_periph_insel_44_gated_we = mio_periph_insel_44_we & mio_periph_insel_regwen_44_qs;
Tests: T68 T37 T69
7275 prim_subreg #(
7276 .DW (6),
7277 .SwAccess(prim_subreg_pkg::SwAccessRW),
7278 .RESVAL (6'h0),
7279 .Mubi (1'b0)
7280 ) u_mio_periph_insel_44 (
7281 .clk_i (clk_i),
7282 .rst_ni (rst_ni),
7283
7284 // from register interface
7285 .we (mio_periph_insel_44_gated_we),
7286 .wd (mio_periph_insel_44_wd),
7287
7288 // from internal hardware
7289 .de (1'b0),
7290 .d ('0),
7291
7292 // to internal hardware
7293 .qe (),
7294 .q (reg2hw.mio_periph_insel[44].q),
7295 .ds (),
7296
7297 // to register interface (read)
7298 .qs (mio_periph_insel_44_qs)
7299 );
7300
7301
7302 // Subregister 45 of Multireg mio_periph_insel
7303 // R[mio_periph_insel_45]: V(False)
7304 // Create REGWEN-gated WE signal
7305 logic mio_periph_insel_45_gated_we;
7306 1/1 assign mio_periph_insel_45_gated_we = mio_periph_insel_45_we & mio_periph_insel_regwen_45_qs;
Tests: T26 T70 T37
7307 prim_subreg #(
7308 .DW (6),
7309 .SwAccess(prim_subreg_pkg::SwAccessRW),
7310 .RESVAL (6'h0),
7311 .Mubi (1'b0)
7312 ) u_mio_periph_insel_45 (
7313 .clk_i (clk_i),
7314 .rst_ni (rst_ni),
7315
7316 // from register interface
7317 .we (mio_periph_insel_45_gated_we),
7318 .wd (mio_periph_insel_45_wd),
7319
7320 // from internal hardware
7321 .de (1'b0),
7322 .d ('0),
7323
7324 // to internal hardware
7325 .qe (),
7326 .q (reg2hw.mio_periph_insel[45].q),
7327 .ds (),
7328
7329 // to register interface (read)
7330 .qs (mio_periph_insel_45_qs)
7331 );
7332
7333
7334 // Subregister 46 of Multireg mio_periph_insel
7335 // R[mio_periph_insel_46]: V(False)
7336 // Create REGWEN-gated WE signal
7337 logic mio_periph_insel_46_gated_we;
7338 1/1 assign mio_periph_insel_46_gated_we = mio_periph_insel_46_we & mio_periph_insel_regwen_46_qs;
Tests: T12 T53 T54
7339 prim_subreg #(
7340 .DW (6),
7341 .SwAccess(prim_subreg_pkg::SwAccessRW),
7342 .RESVAL (6'h0),
7343 .Mubi (1'b0)
7344 ) u_mio_periph_insel_46 (
7345 .clk_i (clk_i),
7346 .rst_ni (rst_ni),
7347
7348 // from register interface
7349 .we (mio_periph_insel_46_gated_we),
7350 .wd (mio_periph_insel_46_wd),
7351
7352 // from internal hardware
7353 .de (1'b0),
7354 .d ('0),
7355
7356 // to internal hardware
7357 .qe (),
7358 .q (reg2hw.mio_periph_insel[46].q),
7359 .ds (),
7360
7361 // to register interface (read)
7362 .qs (mio_periph_insel_46_qs)
7363 );
7364
7365
7366 // Subregister 47 of Multireg mio_periph_insel
7367 // R[mio_periph_insel_47]: V(False)
7368 // Create REGWEN-gated WE signal
7369 logic mio_periph_insel_47_gated_we;
7370 1/1 assign mio_periph_insel_47_gated_we = mio_periph_insel_47_we & mio_periph_insel_regwen_47_qs;
Tests: T71 T96 T97
7371 prim_subreg #(
7372 .DW (6),
7373 .SwAccess(prim_subreg_pkg::SwAccessRW),
7374 .RESVAL (6'h0),
7375 .Mubi (1'b0)
7376 ) u_mio_periph_insel_47 (
7377 .clk_i (clk_i),
7378 .rst_ni (rst_ni),
7379
7380 // from register interface
7381 .we (mio_periph_insel_47_gated_we),
7382 .wd (mio_periph_insel_47_wd),
7383
7384 // from internal hardware
7385 .de (1'b0),
7386 .d ('0),
7387
7388 // to internal hardware
7389 .qe (),
7390 .q (reg2hw.mio_periph_insel[47].q),
7391 .ds (),
7392
7393 // to register interface (read)
7394 .qs (mio_periph_insel_47_qs)
7395 );
7396
7397
7398 // Subregister 48 of Multireg mio_periph_insel
7399 // R[mio_periph_insel_48]: V(False)
7400 // Create REGWEN-gated WE signal
7401 logic mio_periph_insel_48_gated_we;
7402 1/1 assign mio_periph_insel_48_gated_we = mio_periph_insel_48_we & mio_periph_insel_regwen_48_qs;
Tests: T71 T96 T97
7403 prim_subreg #(
7404 .DW (6),
7405 .SwAccess(prim_subreg_pkg::SwAccessRW),
7406 .RESVAL (6'h0),
7407 .Mubi (1'b0)
7408 ) u_mio_periph_insel_48 (
7409 .clk_i (clk_i),
7410 .rst_ni (rst_ni),
7411
7412 // from register interface
7413 .we (mio_periph_insel_48_gated_we),
7414 .wd (mio_periph_insel_48_wd),
7415
7416 // from internal hardware
7417 .de (1'b0),
7418 .d ('0),
7419
7420 // to internal hardware
7421 .qe (),
7422 .q (reg2hw.mio_periph_insel[48].q),
7423 .ds (),
7424
7425 // to register interface (read)
7426 .qs (mio_periph_insel_48_qs)
7427 );
7428
7429
7430 // Subregister 49 of Multireg mio_periph_insel
7431 // R[mio_periph_insel_49]: V(False)
7432 // Create REGWEN-gated WE signal
7433 logic mio_periph_insel_49_gated_we;
7434 1/1 assign mio_periph_insel_49_gated_we = mio_periph_insel_49_we & mio_periph_insel_regwen_49_qs;
Tests: T71 T96 T97
7435 prim_subreg #(
7436 .DW (6),
7437 .SwAccess(prim_subreg_pkg::SwAccessRW),
7438 .RESVAL (6'h0),
7439 .Mubi (1'b0)
7440 ) u_mio_periph_insel_49 (
7441 .clk_i (clk_i),
7442 .rst_ni (rst_ni),
7443
7444 // from register interface
7445 .we (mio_periph_insel_49_gated_we),
7446 .wd (mio_periph_insel_49_wd),
7447
7448 // from internal hardware
7449 .de (1'b0),
7450 .d ('0),
7451
7452 // to internal hardware
7453 .qe (),
7454 .q (reg2hw.mio_periph_insel[49].q),
7455 .ds (),
7456
7457 // to register interface (read)
7458 .qs (mio_periph_insel_49_qs)
7459 );
7460
7461
7462 // Subregister 50 of Multireg mio_periph_insel
7463 // R[mio_periph_insel_50]: V(False)
7464 // Create REGWEN-gated WE signal
7465 logic mio_periph_insel_50_gated_we;
7466 1/1 assign mio_periph_insel_50_gated_we = mio_periph_insel_50_we & mio_periph_insel_regwen_50_qs;
Tests: T28 T15 T72
7467 prim_subreg #(
7468 .DW (6),
7469 .SwAccess(prim_subreg_pkg::SwAccessRW),
7470 .RESVAL (6'h0),
7471 .Mubi (1'b0)
7472 ) u_mio_periph_insel_50 (
7473 .clk_i (clk_i),
7474 .rst_ni (rst_ni),
7475
7476 // from register interface
7477 .we (mio_periph_insel_50_gated_we),
7478 .wd (mio_periph_insel_50_wd),
7479
7480 // from internal hardware
7481 .de (1'b0),
7482 .d ('0),
7483
7484 // to internal hardware
7485 .qe (),
7486 .q (reg2hw.mio_periph_insel[50].q),
7487 .ds (),
7488
7489 // to register interface (read)
7490 .qs (mio_periph_insel_50_qs)
7491 );
7492
7493
7494 // Subregister 51 of Multireg mio_periph_insel
7495 // R[mio_periph_insel_51]: V(False)
7496 // Create REGWEN-gated WE signal
7497 logic mio_periph_insel_51_gated_we;
7498 1/1 assign mio_periph_insel_51_gated_we = mio_periph_insel_51_we & mio_periph_insel_regwen_51_qs;
Tests: T28 T13 T72
7499 prim_subreg #(
7500 .DW (6),
7501 .SwAccess(prim_subreg_pkg::SwAccessRW),
7502 .RESVAL (6'h0),
7503 .Mubi (1'b0)
7504 ) u_mio_periph_insel_51 (
7505 .clk_i (clk_i),
7506 .rst_ni (rst_ni),
7507
7508 // from register interface
7509 .we (mio_periph_insel_51_gated_we),
7510 .wd (mio_periph_insel_51_wd),
7511
7512 // from internal hardware
7513 .de (1'b0),
7514 .d ('0),
7515
7516 // to internal hardware
7517 .qe (),
7518 .q (reg2hw.mio_periph_insel[51].q),
7519 .ds (),
7520
7521 // to register interface (read)
7522 .qs (mio_periph_insel_51_qs)
7523 );
7524
7525
7526 // Subregister 52 of Multireg mio_periph_insel
7527 // R[mio_periph_insel_52]: V(False)
7528 // Create REGWEN-gated WE signal
7529 logic mio_periph_insel_52_gated_we;
7530 1/1 assign mio_periph_insel_52_gated_we = mio_periph_insel_52_we & mio_periph_insel_regwen_52_qs;
Tests: T28 T13 T72
7531 prim_subreg #(
7532 .DW (6),
7533 .SwAccess(prim_subreg_pkg::SwAccessRW),
7534 .RESVAL (6'h0),
7535 .Mubi (1'b0)
7536 ) u_mio_periph_insel_52 (
7537 .clk_i (clk_i),
7538 .rst_ni (rst_ni),
7539
7540 // from register interface
7541 .we (mio_periph_insel_52_gated_we),
7542 .wd (mio_periph_insel_52_wd),
7543
7544 // from internal hardware
7545 .de (1'b0),
7546 .d ('0),
7547
7548 // to internal hardware
7549 .qe (),
7550 .q (reg2hw.mio_periph_insel[52].q),
7551 .ds (),
7552
7553 // to register interface (read)
7554 .qs (mio_periph_insel_52_qs)
7555 );
7556
7557
7558 // Subregister 53 of Multireg mio_periph_insel
7559 // R[mio_periph_insel_53]: V(False)
7560 // Create REGWEN-gated WE signal
7561 logic mio_periph_insel_53_gated_we;
7562 1/1 assign mio_periph_insel_53_gated_we = mio_periph_insel_53_we & mio_periph_insel_regwen_53_qs;
Tests: T28 T13 T72
7563 prim_subreg #(
7564 .DW (6),
7565 .SwAccess(prim_subreg_pkg::SwAccessRW),
7566 .RESVAL (6'h0),
7567 .Mubi (1'b0)
7568 ) u_mio_periph_insel_53 (
7569 .clk_i (clk_i),
7570 .rst_ni (rst_ni),
7571
7572 // from register interface
7573 .we (mio_periph_insel_53_gated_we),
7574 .wd (mio_periph_insel_53_wd),
7575
7576 // from internal hardware
7577 .de (1'b0),
7578 .d ('0),
7579
7580 // to internal hardware
7581 .qe (),
7582 .q (reg2hw.mio_periph_insel[53].q),
7583 .ds (),
7584
7585 // to register interface (read)
7586 .qs (mio_periph_insel_53_qs)
7587 );
7588
7589
7590 // Subregister 54 of Multireg mio_periph_insel
7591 // R[mio_periph_insel_54]: V(False)
7592 // Create REGWEN-gated WE signal
7593 logic mio_periph_insel_54_gated_we;
7594 1/1 assign mio_periph_insel_54_gated_we = mio_periph_insel_54_we & mio_periph_insel_regwen_54_qs;
Tests: T28 T13 T15
7595 prim_subreg #(
7596 .DW (6),
7597 .SwAccess(prim_subreg_pkg::SwAccessRW),
7598 .RESVAL (6'h0),
7599 .Mubi (1'b0)
7600 ) u_mio_periph_insel_54 (
7601 .clk_i (clk_i),
7602 .rst_ni (rst_ni),
7603
7604 // from register interface
7605 .we (mio_periph_insel_54_gated_we),
7606 .wd (mio_periph_insel_54_wd),
7607
7608 // from internal hardware
7609 .de (1'b0),
7610 .d ('0),
7611
7612 // to internal hardware
7613 .qe (),
7614 .q (reg2hw.mio_periph_insel[54].q),
7615 .ds (),
7616
7617 // to register interface (read)
7618 .qs (mio_periph_insel_54_qs)
7619 );
7620
7621
7622 // Subregister 55 of Multireg mio_periph_insel
7623 // R[mio_periph_insel_55]: V(False)
7624 // Create REGWEN-gated WE signal
7625 logic mio_periph_insel_55_gated_we;
7626 1/1 assign mio_periph_insel_55_gated_we = mio_periph_insel_55_we & mio_periph_insel_regwen_55_qs;
Tests: T28 T15 T72
7627 prim_subreg #(
7628 .DW (6),
7629 .SwAccess(prim_subreg_pkg::SwAccessRW),
7630 .RESVAL (6'h0),
7631 .Mubi (1'b0)
7632 ) u_mio_periph_insel_55 (
7633 .clk_i (clk_i),
7634 .rst_ni (rst_ni),
7635
7636 // from register interface
7637 .we (mio_periph_insel_55_gated_we),
7638 .wd (mio_periph_insel_55_wd),
7639
7640 // from internal hardware
7641 .de (1'b0),
7642 .d ('0),
7643
7644 // to internal hardware
7645 .qe (),
7646 .q (reg2hw.mio_periph_insel[55].q),
7647 .ds (),
7648
7649 // to register interface (read)
7650 .qs (mio_periph_insel_55_qs)
7651 );
7652
7653
7654 // Subregister 56 of Multireg mio_periph_insel
7655 // R[mio_periph_insel_56]: V(False)
7656 // Create REGWEN-gated WE signal
7657 logic mio_periph_insel_56_gated_we;
7658 1/1 assign mio_periph_insel_56_gated_we = mio_periph_insel_56_we & mio_periph_insel_regwen_56_qs;
Tests: T7 T31 T8
7659 prim_subreg #(
7660 .DW (6),
7661 .SwAccess(prim_subreg_pkg::SwAccessRW),
7662 .RESVAL (6'h0),
7663 .Mubi (1'b0)
7664 ) u_mio_periph_insel_56 (
7665 .clk_i (clk_i),
7666 .rst_ni (rst_ni),
7667
7668 // from register interface
7669 .we (mio_periph_insel_56_gated_we),
7670 .wd (mio_periph_insel_56_wd),
7671
7672 // from internal hardware
7673 .de (1'b0),
7674 .d ('0),
7675
7676 // to internal hardware
7677 .qe (),
7678 .q (reg2hw.mio_periph_insel[56].q),
7679 .ds (),
7680
7681 // to register interface (read)
7682 .qs (mio_periph_insel_56_qs)
7683 );
7684
7685
7686 // Subregister 0 of Multireg mio_outsel_regwen
7687 // R[mio_outsel_regwen_0]: V(False)
7688 prim_subreg #(
7689 .DW (1),
7690 .SwAccess(prim_subreg_pkg::SwAccessW0C),
7691 .RESVAL (1'h1),
7692 .Mubi (1'b0)
7693 ) u_mio_outsel_regwen_0 (
7694 .clk_i (clk_i),
7695 .rst_ni (rst_ni),
7696
7697 // from register interface
7698 .we (mio_outsel_regwen_0_we),
7699 .wd (mio_outsel_regwen_0_wd),
7700
7701 // from internal hardware
7702 .de (1'b0),
7703 .d ('0),
7704
7705 // to internal hardware
7706 .qe (),
7707 .q (),
7708 .ds (),
7709
7710 // to register interface (read)
7711 .qs (mio_outsel_regwen_0_qs)
7712 );
7713
7714
7715 // Subregister 1 of Multireg mio_outsel_regwen
7716 // R[mio_outsel_regwen_1]: V(False)
7717 prim_subreg #(
7718 .DW (1),
7719 .SwAccess(prim_subreg_pkg::SwAccessW0C),
7720 .RESVAL (1'h1),
7721 .Mubi (1'b0)
7722 ) u_mio_outsel_regwen_1 (
7723 .clk_i (clk_i),
7724 .rst_ni (rst_ni),
7725
7726 // from register interface
7727 .we (mio_outsel_regwen_1_we),
7728 .wd (mio_outsel_regwen_1_wd),
7729
7730 // from internal hardware
7731 .de (1'b0),
7732 .d ('0),
7733
7734 // to internal hardware
7735 .qe (),
7736 .q (),
7737 .ds (),
7738
7739 // to register interface (read)
7740 .qs (mio_outsel_regwen_1_qs)
7741 );
7742
7743
7744 // Subregister 2 of Multireg mio_outsel_regwen
7745 // R[mio_outsel_regwen_2]: V(False)
7746 prim_subreg #(
7747 .DW (1),
7748 .SwAccess(prim_subreg_pkg::SwAccessW0C),
7749 .RESVAL (1'h1),
7750 .Mubi (1'b0)
7751 ) u_mio_outsel_regwen_2 (
7752 .clk_i (clk_i),
7753 .rst_ni (rst_ni),
7754
7755 // from register interface
7756 .we (mio_outsel_regwen_2_we),
7757 .wd (mio_outsel_regwen_2_wd),
7758
7759 // from internal hardware
7760 .de (1'b0),
7761 .d ('0),
7762
7763 // to internal hardware
7764 .qe (),
7765 .q (),
7766 .ds (),
7767
7768 // to register interface (read)
7769 .qs (mio_outsel_regwen_2_qs)
7770 );
7771
7772
7773 // Subregister 3 of Multireg mio_outsel_regwen
7774 // R[mio_outsel_regwen_3]: V(False)
7775 prim_subreg #(
7776 .DW (1),
7777 .SwAccess(prim_subreg_pkg::SwAccessW0C),
7778 .RESVAL (1'h1),
7779 .Mubi (1'b0)
7780 ) u_mio_outsel_regwen_3 (
7781 .clk_i (clk_i),
7782 .rst_ni (rst_ni),
7783
7784 // from register interface
7785 .we (mio_outsel_regwen_3_we),
7786 .wd (mio_outsel_regwen_3_wd),
7787
7788 // from internal hardware
7789 .de (1'b0),
7790 .d ('0),
7791
7792 // to internal hardware
7793 .qe (),
7794 .q (),
7795 .ds (),
7796
7797 // to register interface (read)
7798 .qs (mio_outsel_regwen_3_qs)
7799 );
7800
7801
7802 // Subregister 4 of Multireg mio_outsel_regwen
7803 // R[mio_outsel_regwen_4]: V(False)
7804 prim_subreg #(
7805 .DW (1),
7806 .SwAccess(prim_subreg_pkg::SwAccessW0C),
7807 .RESVAL (1'h1),
7808 .Mubi (1'b0)
7809 ) u_mio_outsel_regwen_4 (
7810 .clk_i (clk_i),
7811 .rst_ni (rst_ni),
7812
7813 // from register interface
7814 .we (mio_outsel_regwen_4_we),
7815 .wd (mio_outsel_regwen_4_wd),
7816
7817 // from internal hardware
7818 .de (1'b0),
7819 .d ('0),
7820
7821 // to internal hardware
7822 .qe (),
7823 .q (),
7824 .ds (),
7825
7826 // to register interface (read)
7827 .qs (mio_outsel_regwen_4_qs)
7828 );
7829
7830
7831 // Subregister 5 of Multireg mio_outsel_regwen
7832 // R[mio_outsel_regwen_5]: V(False)
7833 prim_subreg #(
7834 .DW (1),
7835 .SwAccess(prim_subreg_pkg::SwAccessW0C),
7836 .RESVAL (1'h1),
7837 .Mubi (1'b0)
7838 ) u_mio_outsel_regwen_5 (
7839 .clk_i (clk_i),
7840 .rst_ni (rst_ni),
7841
7842 // from register interface
7843 .we (mio_outsel_regwen_5_we),
7844 .wd (mio_outsel_regwen_5_wd),
7845
7846 // from internal hardware
7847 .de (1'b0),
7848 .d ('0),
7849
7850 // to internal hardware
7851 .qe (),
7852 .q (),
7853 .ds (),
7854
7855 // to register interface (read)
7856 .qs (mio_outsel_regwen_5_qs)
7857 );
7858
7859
7860 // Subregister 6 of Multireg mio_outsel_regwen
7861 // R[mio_outsel_regwen_6]: V(False)
7862 prim_subreg #(
7863 .DW (1),
7864 .SwAccess(prim_subreg_pkg::SwAccessW0C),
7865 .RESVAL (1'h1),
7866 .Mubi (1'b0)
7867 ) u_mio_outsel_regwen_6 (
7868 .clk_i (clk_i),
7869 .rst_ni (rst_ni),
7870
7871 // from register interface
7872 .we (mio_outsel_regwen_6_we),
7873 .wd (mio_outsel_regwen_6_wd),
7874
7875 // from internal hardware
7876 .de (1'b0),
7877 .d ('0),
7878
7879 // to internal hardware
7880 .qe (),
7881 .q (),
7882 .ds (),
7883
7884 // to register interface (read)
7885 .qs (mio_outsel_regwen_6_qs)
7886 );
7887
7888
7889 // Subregister 7 of Multireg mio_outsel_regwen
7890 // R[mio_outsel_regwen_7]: V(False)
7891 prim_subreg #(
7892 .DW (1),
7893 .SwAccess(prim_subreg_pkg::SwAccessW0C),
7894 .RESVAL (1'h1),
7895 .Mubi (1'b0)
7896 ) u_mio_outsel_regwen_7 (
7897 .clk_i (clk_i),
7898 .rst_ni (rst_ni),
7899
7900 // from register interface
7901 .we (mio_outsel_regwen_7_we),
7902 .wd (mio_outsel_regwen_7_wd),
7903
7904 // from internal hardware
7905 .de (1'b0),
7906 .d ('0),
7907
7908 // to internal hardware
7909 .qe (),
7910 .q (),
7911 .ds (),
7912
7913 // to register interface (read)
7914 .qs (mio_outsel_regwen_7_qs)
7915 );
7916
7917
7918 // Subregister 8 of Multireg mio_outsel_regwen
7919 // R[mio_outsel_regwen_8]: V(False)
7920 prim_subreg #(
7921 .DW (1),
7922 .SwAccess(prim_subreg_pkg::SwAccessW0C),
7923 .RESVAL (1'h1),
7924 .Mubi (1'b0)
7925 ) u_mio_outsel_regwen_8 (
7926 .clk_i (clk_i),
7927 .rst_ni (rst_ni),
7928
7929 // from register interface
7930 .we (mio_outsel_regwen_8_we),
7931 .wd (mio_outsel_regwen_8_wd),
7932
7933 // from internal hardware
7934 .de (1'b0),
7935 .d ('0),
7936
7937 // to internal hardware
7938 .qe (),
7939 .q (),
7940 .ds (),
7941
7942 // to register interface (read)
7943 .qs (mio_outsel_regwen_8_qs)
7944 );
7945
7946
7947 // Subregister 9 of Multireg mio_outsel_regwen
7948 // R[mio_outsel_regwen_9]: V(False)
7949 prim_subreg #(
7950 .DW (1),
7951 .SwAccess(prim_subreg_pkg::SwAccessW0C),
7952 .RESVAL (1'h1),
7953 .Mubi (1'b0)
7954 ) u_mio_outsel_regwen_9 (
7955 .clk_i (clk_i),
7956 .rst_ni (rst_ni),
7957
7958 // from register interface
7959 .we (mio_outsel_regwen_9_we),
7960 .wd (mio_outsel_regwen_9_wd),
7961
7962 // from internal hardware
7963 .de (1'b0),
7964 .d ('0),
7965
7966 // to internal hardware
7967 .qe (),
7968 .q (),
7969 .ds (),
7970
7971 // to register interface (read)
7972 .qs (mio_outsel_regwen_9_qs)
7973 );
7974
7975
7976 // Subregister 10 of Multireg mio_outsel_regwen
7977 // R[mio_outsel_regwen_10]: V(False)
7978 prim_subreg #(
7979 .DW (1),
7980 .SwAccess(prim_subreg_pkg::SwAccessW0C),
7981 .RESVAL (1'h1),
7982 .Mubi (1'b0)
7983 ) u_mio_outsel_regwen_10 (
7984 .clk_i (clk_i),
7985 .rst_ni (rst_ni),
7986
7987 // from register interface
7988 .we (mio_outsel_regwen_10_we),
7989 .wd (mio_outsel_regwen_10_wd),
7990
7991 // from internal hardware
7992 .de (1'b0),
7993 .d ('0),
7994
7995 // to internal hardware
7996 .qe (),
7997 .q (),
7998 .ds (),
7999
8000 // to register interface (read)
8001 .qs (mio_outsel_regwen_10_qs)
8002 );
8003
8004
8005 // Subregister 11 of Multireg mio_outsel_regwen
8006 // R[mio_outsel_regwen_11]: V(False)
8007 prim_subreg #(
8008 .DW (1),
8009 .SwAccess(prim_subreg_pkg::SwAccessW0C),
8010 .RESVAL (1'h1),
8011 .Mubi (1'b0)
8012 ) u_mio_outsel_regwen_11 (
8013 .clk_i (clk_i),
8014 .rst_ni (rst_ni),
8015
8016 // from register interface
8017 .we (mio_outsel_regwen_11_we),
8018 .wd (mio_outsel_regwen_11_wd),
8019
8020 // from internal hardware
8021 .de (1'b0),
8022 .d ('0),
8023
8024 // to internal hardware
8025 .qe (),
8026 .q (),
8027 .ds (),
8028
8029 // to register interface (read)
8030 .qs (mio_outsel_regwen_11_qs)
8031 );
8032
8033
8034 // Subregister 12 of Multireg mio_outsel_regwen
8035 // R[mio_outsel_regwen_12]: V(False)
8036 prim_subreg #(
8037 .DW (1),
8038 .SwAccess(prim_subreg_pkg::SwAccessW0C),
8039 .RESVAL (1'h1),
8040 .Mubi (1'b0)
8041 ) u_mio_outsel_regwen_12 (
8042 .clk_i (clk_i),
8043 .rst_ni (rst_ni),
8044
8045 // from register interface
8046 .we (mio_outsel_regwen_12_we),
8047 .wd (mio_outsel_regwen_12_wd),
8048
8049 // from internal hardware
8050 .de (1'b0),
8051 .d ('0),
8052
8053 // to internal hardware
8054 .qe (),
8055 .q (),
8056 .ds (),
8057
8058 // to register interface (read)
8059 .qs (mio_outsel_regwen_12_qs)
8060 );
8061
8062
8063 // Subregister 13 of Multireg mio_outsel_regwen
8064 // R[mio_outsel_regwen_13]: V(False)
8065 prim_subreg #(
8066 .DW (1),
8067 .SwAccess(prim_subreg_pkg::SwAccessW0C),
8068 .RESVAL (1'h1),
8069 .Mubi (1'b0)
8070 ) u_mio_outsel_regwen_13 (
8071 .clk_i (clk_i),
8072 .rst_ni (rst_ni),
8073
8074 // from register interface
8075 .we (mio_outsel_regwen_13_we),
8076 .wd (mio_outsel_regwen_13_wd),
8077
8078 // from internal hardware
8079 .de (1'b0),
8080 .d ('0),
8081
8082 // to internal hardware
8083 .qe (),
8084 .q (),
8085 .ds (),
8086
8087 // to register interface (read)
8088 .qs (mio_outsel_regwen_13_qs)
8089 );
8090
8091
8092 // Subregister 14 of Multireg mio_outsel_regwen
8093 // R[mio_outsel_regwen_14]: V(False)
8094 prim_subreg #(
8095 .DW (1),
8096 .SwAccess(prim_subreg_pkg::SwAccessW0C),
8097 .RESVAL (1'h1),
8098 .Mubi (1'b0)
8099 ) u_mio_outsel_regwen_14 (
8100 .clk_i (clk_i),
8101 .rst_ni (rst_ni),
8102
8103 // from register interface
8104 .we (mio_outsel_regwen_14_we),
8105 .wd (mio_outsel_regwen_14_wd),
8106
8107 // from internal hardware
8108 .de (1'b0),
8109 .d ('0),
8110
8111 // to internal hardware
8112 .qe (),
8113 .q (),
8114 .ds (),
8115
8116 // to register interface (read)
8117 .qs (mio_outsel_regwen_14_qs)
8118 );
8119
8120
8121 // Subregister 15 of Multireg mio_outsel_regwen
8122 // R[mio_outsel_regwen_15]: V(False)
8123 prim_subreg #(
8124 .DW (1),
8125 .SwAccess(prim_subreg_pkg::SwAccessW0C),
8126 .RESVAL (1'h1),
8127 .Mubi (1'b0)
8128 ) u_mio_outsel_regwen_15 (
8129 .clk_i (clk_i),
8130 .rst_ni (rst_ni),
8131
8132 // from register interface
8133 .we (mio_outsel_regwen_15_we),
8134 .wd (mio_outsel_regwen_15_wd),
8135
8136 // from internal hardware
8137 .de (1'b0),
8138 .d ('0),
8139
8140 // to internal hardware
8141 .qe (),
8142 .q (),
8143 .ds (),
8144
8145 // to register interface (read)
8146 .qs (mio_outsel_regwen_15_qs)
8147 );
8148
8149
8150 // Subregister 16 of Multireg mio_outsel_regwen
8151 // R[mio_outsel_regwen_16]: V(False)
8152 prim_subreg #(
8153 .DW (1),
8154 .SwAccess(prim_subreg_pkg::SwAccessW0C),
8155 .RESVAL (1'h1),
8156 .Mubi (1'b0)
8157 ) u_mio_outsel_regwen_16 (
8158 .clk_i (clk_i),
8159 .rst_ni (rst_ni),
8160
8161 // from register interface
8162 .we (mio_outsel_regwen_16_we),
8163 .wd (mio_outsel_regwen_16_wd),
8164
8165 // from internal hardware
8166 .de (1'b0),
8167 .d ('0),
8168
8169 // to internal hardware
8170 .qe (),
8171 .q (),
8172 .ds (),
8173
8174 // to register interface (read)
8175 .qs (mio_outsel_regwen_16_qs)
8176 );
8177
8178
8179 // Subregister 17 of Multireg mio_outsel_regwen
8180 // R[mio_outsel_regwen_17]: V(False)
8181 prim_subreg #(
8182 .DW (1),
8183 .SwAccess(prim_subreg_pkg::SwAccessW0C),
8184 .RESVAL (1'h1),
8185 .Mubi (1'b0)
8186 ) u_mio_outsel_regwen_17 (
8187 .clk_i (clk_i),
8188 .rst_ni (rst_ni),
8189
8190 // from register interface
8191 .we (mio_outsel_regwen_17_we),
8192 .wd (mio_outsel_regwen_17_wd),
8193
8194 // from internal hardware
8195 .de (1'b0),
8196 .d ('0),
8197
8198 // to internal hardware
8199 .qe (),
8200 .q (),
8201 .ds (),
8202
8203 // to register interface (read)
8204 .qs (mio_outsel_regwen_17_qs)
8205 );
8206
8207
8208 // Subregister 18 of Multireg mio_outsel_regwen
8209 // R[mio_outsel_regwen_18]: V(False)
8210 prim_subreg #(
8211 .DW (1),
8212 .SwAccess(prim_subreg_pkg::SwAccessW0C),
8213 .RESVAL (1'h1),
8214 .Mubi (1'b0)
8215 ) u_mio_outsel_regwen_18 (
8216 .clk_i (clk_i),
8217 .rst_ni (rst_ni),
8218
8219 // from register interface
8220 .we (mio_outsel_regwen_18_we),
8221 .wd (mio_outsel_regwen_18_wd),
8222
8223 // from internal hardware
8224 .de (1'b0),
8225 .d ('0),
8226
8227 // to internal hardware
8228 .qe (),
8229 .q (),
8230 .ds (),
8231
8232 // to register interface (read)
8233 .qs (mio_outsel_regwen_18_qs)
8234 );
8235
8236
8237 // Subregister 19 of Multireg mio_outsel_regwen
8238 // R[mio_outsel_regwen_19]: V(False)
8239 prim_subreg #(
8240 .DW (1),
8241 .SwAccess(prim_subreg_pkg::SwAccessW0C),
8242 .RESVAL (1'h1),
8243 .Mubi (1'b0)
8244 ) u_mio_outsel_regwen_19 (
8245 .clk_i (clk_i),
8246 .rst_ni (rst_ni),
8247
8248 // from register interface
8249 .we (mio_outsel_regwen_19_we),
8250 .wd (mio_outsel_regwen_19_wd),
8251
8252 // from internal hardware
8253 .de (1'b0),
8254 .d ('0),
8255
8256 // to internal hardware
8257 .qe (),
8258 .q (),
8259 .ds (),
8260
8261 // to register interface (read)
8262 .qs (mio_outsel_regwen_19_qs)
8263 );
8264
8265
8266 // Subregister 20 of Multireg mio_outsel_regwen
8267 // R[mio_outsel_regwen_20]: V(False)
8268 prim_subreg #(
8269 .DW (1),
8270 .SwAccess(prim_subreg_pkg::SwAccessW0C),
8271 .RESVAL (1'h1),
8272 .Mubi (1'b0)
8273 ) u_mio_outsel_regwen_20 (
8274 .clk_i (clk_i),
8275 .rst_ni (rst_ni),
8276
8277 // from register interface
8278 .we (mio_outsel_regwen_20_we),
8279 .wd (mio_outsel_regwen_20_wd),
8280
8281 // from internal hardware
8282 .de (1'b0),
8283 .d ('0),
8284
8285 // to internal hardware
8286 .qe (),
8287 .q (),
8288 .ds (),
8289
8290 // to register interface (read)
8291 .qs (mio_outsel_regwen_20_qs)
8292 );
8293
8294
8295 // Subregister 21 of Multireg mio_outsel_regwen
8296 // R[mio_outsel_regwen_21]: V(False)
8297 prim_subreg #(
8298 .DW (1),
8299 .SwAccess(prim_subreg_pkg::SwAccessW0C),
8300 .RESVAL (1'h1),
8301 .Mubi (1'b0)
8302 ) u_mio_outsel_regwen_21 (
8303 .clk_i (clk_i),
8304 .rst_ni (rst_ni),
8305
8306 // from register interface
8307 .we (mio_outsel_regwen_21_we),
8308 .wd (mio_outsel_regwen_21_wd),
8309
8310 // from internal hardware
8311 .de (1'b0),
8312 .d ('0),
8313
8314 // to internal hardware
8315 .qe (),
8316 .q (),
8317 .ds (),
8318
8319 // to register interface (read)
8320 .qs (mio_outsel_regwen_21_qs)
8321 );
8322
8323
8324 // Subregister 22 of Multireg mio_outsel_regwen
8325 // R[mio_outsel_regwen_22]: V(False)
8326 prim_subreg #(
8327 .DW (1),
8328 .SwAccess(prim_subreg_pkg::SwAccessW0C),
8329 .RESVAL (1'h1),
8330 .Mubi (1'b0)
8331 ) u_mio_outsel_regwen_22 (
8332 .clk_i (clk_i),
8333 .rst_ni (rst_ni),
8334
8335 // from register interface
8336 .we (mio_outsel_regwen_22_we),
8337 .wd (mio_outsel_regwen_22_wd),
8338
8339 // from internal hardware
8340 .de (1'b0),
8341 .d ('0),
8342
8343 // to internal hardware
8344 .qe (),
8345 .q (),
8346 .ds (),
8347
8348 // to register interface (read)
8349 .qs (mio_outsel_regwen_22_qs)
8350 );
8351
8352
8353 // Subregister 23 of Multireg mio_outsel_regwen
8354 // R[mio_outsel_regwen_23]: V(False)
8355 prim_subreg #(
8356 .DW (1),
8357 .SwAccess(prim_subreg_pkg::SwAccessW0C),
8358 .RESVAL (1'h1),
8359 .Mubi (1'b0)
8360 ) u_mio_outsel_regwen_23 (
8361 .clk_i (clk_i),
8362 .rst_ni (rst_ni),
8363
8364 // from register interface
8365 .we (mio_outsel_regwen_23_we),
8366 .wd (mio_outsel_regwen_23_wd),
8367
8368 // from internal hardware
8369 .de (1'b0),
8370 .d ('0),
8371
8372 // to internal hardware
8373 .qe (),
8374 .q (),
8375 .ds (),
8376
8377 // to register interface (read)
8378 .qs (mio_outsel_regwen_23_qs)
8379 );
8380
8381
8382 // Subregister 24 of Multireg mio_outsel_regwen
8383 // R[mio_outsel_regwen_24]: V(False)
8384 prim_subreg #(
8385 .DW (1),
8386 .SwAccess(prim_subreg_pkg::SwAccessW0C),
8387 .RESVAL (1'h1),
8388 .Mubi (1'b0)
8389 ) u_mio_outsel_regwen_24 (
8390 .clk_i (clk_i),
8391 .rst_ni (rst_ni),
8392
8393 // from register interface
8394 .we (mio_outsel_regwen_24_we),
8395 .wd (mio_outsel_regwen_24_wd),
8396
8397 // from internal hardware
8398 .de (1'b0),
8399 .d ('0),
8400
8401 // to internal hardware
8402 .qe (),
8403 .q (),
8404 .ds (),
8405
8406 // to register interface (read)
8407 .qs (mio_outsel_regwen_24_qs)
8408 );
8409
8410
8411 // Subregister 25 of Multireg mio_outsel_regwen
8412 // R[mio_outsel_regwen_25]: V(False)
8413 prim_subreg #(
8414 .DW (1),
8415 .SwAccess(prim_subreg_pkg::SwAccessW0C),
8416 .RESVAL (1'h1),
8417 .Mubi (1'b0)
8418 ) u_mio_outsel_regwen_25 (
8419 .clk_i (clk_i),
8420 .rst_ni (rst_ni),
8421
8422 // from register interface
8423 .we (mio_outsel_regwen_25_we),
8424 .wd (mio_outsel_regwen_25_wd),
8425
8426 // from internal hardware
8427 .de (1'b0),
8428 .d ('0),
8429
8430 // to internal hardware
8431 .qe (),
8432 .q (),
8433 .ds (),
8434
8435 // to register interface (read)
8436 .qs (mio_outsel_regwen_25_qs)
8437 );
8438
8439
8440 // Subregister 26 of Multireg mio_outsel_regwen
8441 // R[mio_outsel_regwen_26]: V(False)
8442 prim_subreg #(
8443 .DW (1),
8444 .SwAccess(prim_subreg_pkg::SwAccessW0C),
8445 .RESVAL (1'h1),
8446 .Mubi (1'b0)
8447 ) u_mio_outsel_regwen_26 (
8448 .clk_i (clk_i),
8449 .rst_ni (rst_ni),
8450
8451 // from register interface
8452 .we (mio_outsel_regwen_26_we),
8453 .wd (mio_outsel_regwen_26_wd),
8454
8455 // from internal hardware
8456 .de (1'b0),
8457 .d ('0),
8458
8459 // to internal hardware
8460 .qe (),
8461 .q (),
8462 .ds (),
8463
8464 // to register interface (read)
8465 .qs (mio_outsel_regwen_26_qs)
8466 );
8467
8468
8469 // Subregister 27 of Multireg mio_outsel_regwen
8470 // R[mio_outsel_regwen_27]: V(False)
8471 prim_subreg #(
8472 .DW (1),
8473 .SwAccess(prim_subreg_pkg::SwAccessW0C),
8474 .RESVAL (1'h1),
8475 .Mubi (1'b0)
8476 ) u_mio_outsel_regwen_27 (
8477 .clk_i (clk_i),
8478 .rst_ni (rst_ni),
8479
8480 // from register interface
8481 .we (mio_outsel_regwen_27_we),
8482 .wd (mio_outsel_regwen_27_wd),
8483
8484 // from internal hardware
8485 .de (1'b0),
8486 .d ('0),
8487
8488 // to internal hardware
8489 .qe (),
8490 .q (),
8491 .ds (),
8492
8493 // to register interface (read)
8494 .qs (mio_outsel_regwen_27_qs)
8495 );
8496
8497
8498 // Subregister 28 of Multireg mio_outsel_regwen
8499 // R[mio_outsel_regwen_28]: V(False)
8500 prim_subreg #(
8501 .DW (1),
8502 .SwAccess(prim_subreg_pkg::SwAccessW0C),
8503 .RESVAL (1'h1),
8504 .Mubi (1'b0)
8505 ) u_mio_outsel_regwen_28 (
8506 .clk_i (clk_i),
8507 .rst_ni (rst_ni),
8508
8509 // from register interface
8510 .we (mio_outsel_regwen_28_we),
8511 .wd (mio_outsel_regwen_28_wd),
8512
8513 // from internal hardware
8514 .de (1'b0),
8515 .d ('0),
8516
8517 // to internal hardware
8518 .qe (),
8519 .q (),
8520 .ds (),
8521
8522 // to register interface (read)
8523 .qs (mio_outsel_regwen_28_qs)
8524 );
8525
8526
8527 // Subregister 29 of Multireg mio_outsel_regwen
8528 // R[mio_outsel_regwen_29]: V(False)
8529 prim_subreg #(
8530 .DW (1),
8531 .SwAccess(prim_subreg_pkg::SwAccessW0C),
8532 .RESVAL (1'h1),
8533 .Mubi (1'b0)
8534 ) u_mio_outsel_regwen_29 (
8535 .clk_i (clk_i),
8536 .rst_ni (rst_ni),
8537
8538 // from register interface
8539 .we (mio_outsel_regwen_29_we),
8540 .wd (mio_outsel_regwen_29_wd),
8541
8542 // from internal hardware
8543 .de (1'b0),
8544 .d ('0),
8545
8546 // to internal hardware
8547 .qe (),
8548 .q (),
8549 .ds (),
8550
8551 // to register interface (read)
8552 .qs (mio_outsel_regwen_29_qs)
8553 );
8554
8555
8556 // Subregister 30 of Multireg mio_outsel_regwen
8557 // R[mio_outsel_regwen_30]: V(False)
8558 prim_subreg #(
8559 .DW (1),
8560 .SwAccess(prim_subreg_pkg::SwAccessW0C),
8561 .RESVAL (1'h1),
8562 .Mubi (1'b0)
8563 ) u_mio_outsel_regwen_30 (
8564 .clk_i (clk_i),
8565 .rst_ni (rst_ni),
8566
8567 // from register interface
8568 .we (mio_outsel_regwen_30_we),
8569 .wd (mio_outsel_regwen_30_wd),
8570
8571 // from internal hardware
8572 .de (1'b0),
8573 .d ('0),
8574
8575 // to internal hardware
8576 .qe (),
8577 .q (),
8578 .ds (),
8579
8580 // to register interface (read)
8581 .qs (mio_outsel_regwen_30_qs)
8582 );
8583
8584
8585 // Subregister 31 of Multireg mio_outsel_regwen
8586 // R[mio_outsel_regwen_31]: V(False)
8587 prim_subreg #(
8588 .DW (1),
8589 .SwAccess(prim_subreg_pkg::SwAccessW0C),
8590 .RESVAL (1'h1),
8591 .Mubi (1'b0)
8592 ) u_mio_outsel_regwen_31 (
8593 .clk_i (clk_i),
8594 .rst_ni (rst_ni),
8595
8596 // from register interface
8597 .we (mio_outsel_regwen_31_we),
8598 .wd (mio_outsel_regwen_31_wd),
8599
8600 // from internal hardware
8601 .de (1'b0),
8602 .d ('0),
8603
8604 // to internal hardware
8605 .qe (),
8606 .q (),
8607 .ds (),
8608
8609 // to register interface (read)
8610 .qs (mio_outsel_regwen_31_qs)
8611 );
8612
8613
8614 // Subregister 32 of Multireg mio_outsel_regwen
8615 // R[mio_outsel_regwen_32]: V(False)
8616 prim_subreg #(
8617 .DW (1),
8618 .SwAccess(prim_subreg_pkg::SwAccessW0C),
8619 .RESVAL (1'h1),
8620 .Mubi (1'b0)
8621 ) u_mio_outsel_regwen_32 (
8622 .clk_i (clk_i),
8623 .rst_ni (rst_ni),
8624
8625 // from register interface
8626 .we (mio_outsel_regwen_32_we),
8627 .wd (mio_outsel_regwen_32_wd),
8628
8629 // from internal hardware
8630 .de (1'b0),
8631 .d ('0),
8632
8633 // to internal hardware
8634 .qe (),
8635 .q (),
8636 .ds (),
8637
8638 // to register interface (read)
8639 .qs (mio_outsel_regwen_32_qs)
8640 );
8641
8642
8643 // Subregister 33 of Multireg mio_outsel_regwen
8644 // R[mio_outsel_regwen_33]: V(False)
8645 prim_subreg #(
8646 .DW (1),
8647 .SwAccess(prim_subreg_pkg::SwAccessW0C),
8648 .RESVAL (1'h1),
8649 .Mubi (1'b0)
8650 ) u_mio_outsel_regwen_33 (
8651 .clk_i (clk_i),
8652 .rst_ni (rst_ni),
8653
8654 // from register interface
8655 .we (mio_outsel_regwen_33_we),
8656 .wd (mio_outsel_regwen_33_wd),
8657
8658 // from internal hardware
8659 .de (1'b0),
8660 .d ('0),
8661
8662 // to internal hardware
8663 .qe (),
8664 .q (),
8665 .ds (),
8666
8667 // to register interface (read)
8668 .qs (mio_outsel_regwen_33_qs)
8669 );
8670
8671
8672 // Subregister 34 of Multireg mio_outsel_regwen
8673 // R[mio_outsel_regwen_34]: V(False)
8674 prim_subreg #(
8675 .DW (1),
8676 .SwAccess(prim_subreg_pkg::SwAccessW0C),
8677 .RESVAL (1'h1),
8678 .Mubi (1'b0)
8679 ) u_mio_outsel_regwen_34 (
8680 .clk_i (clk_i),
8681 .rst_ni (rst_ni),
8682
8683 // from register interface
8684 .we (mio_outsel_regwen_34_we),
8685 .wd (mio_outsel_regwen_34_wd),
8686
8687 // from internal hardware
8688 .de (1'b0),
8689 .d ('0),
8690
8691 // to internal hardware
8692 .qe (),
8693 .q (),
8694 .ds (),
8695
8696 // to register interface (read)
8697 .qs (mio_outsel_regwen_34_qs)
8698 );
8699
8700
8701 // Subregister 35 of Multireg mio_outsel_regwen
8702 // R[mio_outsel_regwen_35]: V(False)
8703 prim_subreg #(
8704 .DW (1),
8705 .SwAccess(prim_subreg_pkg::SwAccessW0C),
8706 .RESVAL (1'h1),
8707 .Mubi (1'b0)
8708 ) u_mio_outsel_regwen_35 (
8709 .clk_i (clk_i),
8710 .rst_ni (rst_ni),
8711
8712 // from register interface
8713 .we (mio_outsel_regwen_35_we),
8714 .wd (mio_outsel_regwen_35_wd),
8715
8716 // from internal hardware
8717 .de (1'b0),
8718 .d ('0),
8719
8720 // to internal hardware
8721 .qe (),
8722 .q (),
8723 .ds (),
8724
8725 // to register interface (read)
8726 .qs (mio_outsel_regwen_35_qs)
8727 );
8728
8729
8730 // Subregister 36 of Multireg mio_outsel_regwen
8731 // R[mio_outsel_regwen_36]: V(False)
8732 prim_subreg #(
8733 .DW (1),
8734 .SwAccess(prim_subreg_pkg::SwAccessW0C),
8735 .RESVAL (1'h1),
8736 .Mubi (1'b0)
8737 ) u_mio_outsel_regwen_36 (
8738 .clk_i (clk_i),
8739 .rst_ni (rst_ni),
8740
8741 // from register interface
8742 .we (mio_outsel_regwen_36_we),
8743 .wd (mio_outsel_regwen_36_wd),
8744
8745 // from internal hardware
8746 .de (1'b0),
8747 .d ('0),
8748
8749 // to internal hardware
8750 .qe (),
8751 .q (),
8752 .ds (),
8753
8754 // to register interface (read)
8755 .qs (mio_outsel_regwen_36_qs)
8756 );
8757
8758
8759 // Subregister 37 of Multireg mio_outsel_regwen
8760 // R[mio_outsel_regwen_37]: V(False)
8761 prim_subreg #(
8762 .DW (1),
8763 .SwAccess(prim_subreg_pkg::SwAccessW0C),
8764 .RESVAL (1'h1),
8765 .Mubi (1'b0)
8766 ) u_mio_outsel_regwen_37 (
8767 .clk_i (clk_i),
8768 .rst_ni (rst_ni),
8769
8770 // from register interface
8771 .we (mio_outsel_regwen_37_we),
8772 .wd (mio_outsel_regwen_37_wd),
8773
8774 // from internal hardware
8775 .de (1'b0),
8776 .d ('0),
8777
8778 // to internal hardware
8779 .qe (),
8780 .q (),
8781 .ds (),
8782
8783 // to register interface (read)
8784 .qs (mio_outsel_regwen_37_qs)
8785 );
8786
8787
8788 // Subregister 38 of Multireg mio_outsel_regwen
8789 // R[mio_outsel_regwen_38]: V(False)
8790 prim_subreg #(
8791 .DW (1),
8792 .SwAccess(prim_subreg_pkg::SwAccessW0C),
8793 .RESVAL (1'h1),
8794 .Mubi (1'b0)
8795 ) u_mio_outsel_regwen_38 (
8796 .clk_i (clk_i),
8797 .rst_ni (rst_ni),
8798
8799 // from register interface
8800 .we (mio_outsel_regwen_38_we),
8801 .wd (mio_outsel_regwen_38_wd),
8802
8803 // from internal hardware
8804 .de (1'b0),
8805 .d ('0),
8806
8807 // to internal hardware
8808 .qe (),
8809 .q (),
8810 .ds (),
8811
8812 // to register interface (read)
8813 .qs (mio_outsel_regwen_38_qs)
8814 );
8815
8816
8817 // Subregister 39 of Multireg mio_outsel_regwen
8818 // R[mio_outsel_regwen_39]: V(False)
8819 prim_subreg #(
8820 .DW (1),
8821 .SwAccess(prim_subreg_pkg::SwAccessW0C),
8822 .RESVAL (1'h1),
8823 .Mubi (1'b0)
8824 ) u_mio_outsel_regwen_39 (
8825 .clk_i (clk_i),
8826 .rst_ni (rst_ni),
8827
8828 // from register interface
8829 .we (mio_outsel_regwen_39_we),
8830 .wd (mio_outsel_regwen_39_wd),
8831
8832 // from internal hardware
8833 .de (1'b0),
8834 .d ('0),
8835
8836 // to internal hardware
8837 .qe (),
8838 .q (),
8839 .ds (),
8840
8841 // to register interface (read)
8842 .qs (mio_outsel_regwen_39_qs)
8843 );
8844
8845
8846 // Subregister 40 of Multireg mio_outsel_regwen
8847 // R[mio_outsel_regwen_40]: V(False)
8848 prim_subreg #(
8849 .DW (1),
8850 .SwAccess(prim_subreg_pkg::SwAccessW0C),
8851 .RESVAL (1'h1),
8852 .Mubi (1'b0)
8853 ) u_mio_outsel_regwen_40 (
8854 .clk_i (clk_i),
8855 .rst_ni (rst_ni),
8856
8857 // from register interface
8858 .we (mio_outsel_regwen_40_we),
8859 .wd (mio_outsel_regwen_40_wd),
8860
8861 // from internal hardware
8862 .de (1'b0),
8863 .d ('0),
8864
8865 // to internal hardware
8866 .qe (),
8867 .q (),
8868 .ds (),
8869
8870 // to register interface (read)
8871 .qs (mio_outsel_regwen_40_qs)
8872 );
8873
8874
8875 // Subregister 41 of Multireg mio_outsel_regwen
8876 // R[mio_outsel_regwen_41]: V(False)
8877 prim_subreg #(
8878 .DW (1),
8879 .SwAccess(prim_subreg_pkg::SwAccessW0C),
8880 .RESVAL (1'h1),
8881 .Mubi (1'b0)
8882 ) u_mio_outsel_regwen_41 (
8883 .clk_i (clk_i),
8884 .rst_ni (rst_ni),
8885
8886 // from register interface
8887 .we (mio_outsel_regwen_41_we),
8888 .wd (mio_outsel_regwen_41_wd),
8889
8890 // from internal hardware
8891 .de (1'b0),
8892 .d ('0),
8893
8894 // to internal hardware
8895 .qe (),
8896 .q (),
8897 .ds (),
8898
8899 // to register interface (read)
8900 .qs (mio_outsel_regwen_41_qs)
8901 );
8902
8903
8904 // Subregister 42 of Multireg mio_outsel_regwen
8905 // R[mio_outsel_regwen_42]: V(False)
8906 prim_subreg #(
8907 .DW (1),
8908 .SwAccess(prim_subreg_pkg::SwAccessW0C),
8909 .RESVAL (1'h1),
8910 .Mubi (1'b0)
8911 ) u_mio_outsel_regwen_42 (
8912 .clk_i (clk_i),
8913 .rst_ni (rst_ni),
8914
8915 // from register interface
8916 .we (mio_outsel_regwen_42_we),
8917 .wd (mio_outsel_regwen_42_wd),
8918
8919 // from internal hardware
8920 .de (1'b0),
8921 .d ('0),
8922
8923 // to internal hardware
8924 .qe (),
8925 .q (),
8926 .ds (),
8927
8928 // to register interface (read)
8929 .qs (mio_outsel_regwen_42_qs)
8930 );
8931
8932
8933 // Subregister 43 of Multireg mio_outsel_regwen
8934 // R[mio_outsel_regwen_43]: V(False)
8935 prim_subreg #(
8936 .DW (1),
8937 .SwAccess(prim_subreg_pkg::SwAccessW0C),
8938 .RESVAL (1'h1),
8939 .Mubi (1'b0)
8940 ) u_mio_outsel_regwen_43 (
8941 .clk_i (clk_i),
8942 .rst_ni (rst_ni),
8943
8944 // from register interface
8945 .we (mio_outsel_regwen_43_we),
8946 .wd (mio_outsel_regwen_43_wd),
8947
8948 // from internal hardware
8949 .de (1'b0),
8950 .d ('0),
8951
8952 // to internal hardware
8953 .qe (),
8954 .q (),
8955 .ds (),
8956
8957 // to register interface (read)
8958 .qs (mio_outsel_regwen_43_qs)
8959 );
8960
8961
8962 // Subregister 44 of Multireg mio_outsel_regwen
8963 // R[mio_outsel_regwen_44]: V(False)
8964 prim_subreg #(
8965 .DW (1),
8966 .SwAccess(prim_subreg_pkg::SwAccessW0C),
8967 .RESVAL (1'h1),
8968 .Mubi (1'b0)
8969 ) u_mio_outsel_regwen_44 (
8970 .clk_i (clk_i),
8971 .rst_ni (rst_ni),
8972
8973 // from register interface
8974 .we (mio_outsel_regwen_44_we),
8975 .wd (mio_outsel_regwen_44_wd),
8976
8977 // from internal hardware
8978 .de (1'b0),
8979 .d ('0),
8980
8981 // to internal hardware
8982 .qe (),
8983 .q (),
8984 .ds (),
8985
8986 // to register interface (read)
8987 .qs (mio_outsel_regwen_44_qs)
8988 );
8989
8990
8991 // Subregister 45 of Multireg mio_outsel_regwen
8992 // R[mio_outsel_regwen_45]: V(False)
8993 prim_subreg #(
8994 .DW (1),
8995 .SwAccess(prim_subreg_pkg::SwAccessW0C),
8996 .RESVAL (1'h1),
8997 .Mubi (1'b0)
8998 ) u_mio_outsel_regwen_45 (
8999 .clk_i (clk_i),
9000 .rst_ni (rst_ni),
9001
9002 // from register interface
9003 .we (mio_outsel_regwen_45_we),
9004 .wd (mio_outsel_regwen_45_wd),
9005
9006 // from internal hardware
9007 .de (1'b0),
9008 .d ('0),
9009
9010 // to internal hardware
9011 .qe (),
9012 .q (),
9013 .ds (),
9014
9015 // to register interface (read)
9016 .qs (mio_outsel_regwen_45_qs)
9017 );
9018
9019
9020 // Subregister 46 of Multireg mio_outsel_regwen
9021 // R[mio_outsel_regwen_46]: V(False)
9022 prim_subreg #(
9023 .DW (1),
9024 .SwAccess(prim_subreg_pkg::SwAccessW0C),
9025 .RESVAL (1'h1),
9026 .Mubi (1'b0)
9027 ) u_mio_outsel_regwen_46 (
9028 .clk_i (clk_i),
9029 .rst_ni (rst_ni),
9030
9031 // from register interface
9032 .we (mio_outsel_regwen_46_we),
9033 .wd (mio_outsel_regwen_46_wd),
9034
9035 // from internal hardware
9036 .de (1'b0),
9037 .d ('0),
9038
9039 // to internal hardware
9040 .qe (),
9041 .q (),
9042 .ds (),
9043
9044 // to register interface (read)
9045 .qs (mio_outsel_regwen_46_qs)
9046 );
9047
9048
9049 // Subregister 0 of Multireg mio_outsel
9050 // R[mio_outsel_0]: V(False)
9051 // Create REGWEN-gated WE signal
9052 logic mio_outsel_0_gated_we;
9053 1/1 assign mio_outsel_0_gated_we = mio_outsel_0_we & mio_outsel_regwen_0_qs;
Tests: T25 T27 T37
9054 prim_subreg #(
9055 .DW (7),
9056 .SwAccess(prim_subreg_pkg::SwAccessRW),
9057 .RESVAL (7'h2),
9058 .Mubi (1'b0)
9059 ) u_mio_outsel_0 (
9060 .clk_i (clk_i),
9061 .rst_ni (rst_ni),
9062
9063 // from register interface
9064 .we (mio_outsel_0_gated_we),
9065 .wd (mio_outsel_0_wd),
9066
9067 // from internal hardware
9068 .de (1'b0),
9069 .d ('0),
9070
9071 // to internal hardware
9072 .qe (),
9073 .q (reg2hw.mio_outsel[0].q),
9074 .ds (),
9075
9076 // to register interface (read)
9077 .qs (mio_outsel_0_qs)
9078 );
9079
9080
9081 // Subregister 1 of Multireg mio_outsel
9082 // R[mio_outsel_1]: V(False)
9083 // Create REGWEN-gated WE signal
9084 logic mio_outsel_1_gated_we;
9085 1/1 assign mio_outsel_1_gated_we = mio_outsel_1_we & mio_outsel_regwen_1_qs;
Tests: T25 T26 T27
9086 prim_subreg #(
9087 .DW (7),
9088 .SwAccess(prim_subreg_pkg::SwAccessRW),
9089 .RESVAL (7'h2),
9090 .Mubi (1'b0)
9091 ) u_mio_outsel_1 (
9092 .clk_i (clk_i),
9093 .rst_ni (rst_ni),
9094
9095 // from register interface
9096 .we (mio_outsel_1_gated_we),
9097 .wd (mio_outsel_1_wd),
9098
9099 // from internal hardware
9100 .de (1'b0),
9101 .d ('0),
9102
9103 // to internal hardware
9104 .qe (),
9105 .q (reg2hw.mio_outsel[1].q),
9106 .ds (),
9107
9108 // to register interface (read)
9109 .qs (mio_outsel_1_qs)
9110 );
9111
9112
9113 // Subregister 2 of Multireg mio_outsel
9114 // R[mio_outsel_2]: V(False)
9115 // Create REGWEN-gated WE signal
9116 logic mio_outsel_2_gated_we;
9117 1/1 assign mio_outsel_2_gated_we = mio_outsel_2_we & mio_outsel_regwen_2_qs;
Tests: T25 T27 T75
9118 prim_subreg #(
9119 .DW (7),
9120 .SwAccess(prim_subreg_pkg::SwAccessRW),
9121 .RESVAL (7'h2),
9122 .Mubi (1'b0)
9123 ) u_mio_outsel_2 (
9124 .clk_i (clk_i),
9125 .rst_ni (rst_ni),
9126
9127 // from register interface
9128 .we (mio_outsel_2_gated_we),
9129 .wd (mio_outsel_2_wd),
9130
9131 // from internal hardware
9132 .de (1'b0),
9133 .d ('0),
9134
9135 // to internal hardware
9136 .qe (),
9137 .q (reg2hw.mio_outsel[2].q),
9138 .ds (),
9139
9140 // to register interface (read)
9141 .qs (mio_outsel_2_qs)
9142 );
9143
9144
9145 // Subregister 3 of Multireg mio_outsel
9146 // R[mio_outsel_3]: V(False)
9147 // Create REGWEN-gated WE signal
9148 logic mio_outsel_3_gated_we;
9149 1/1 assign mio_outsel_3_gated_we = mio_outsel_3_we & mio_outsel_regwen_3_qs;
Tests: T25 T27 T42
9150 prim_subreg #(
9151 .DW (7),
9152 .SwAccess(prim_subreg_pkg::SwAccessRW),
9153 .RESVAL (7'h2),
9154 .Mubi (1'b0)
9155 ) u_mio_outsel_3 (
9156 .clk_i (clk_i),
9157 .rst_ni (rst_ni),
9158
9159 // from register interface
9160 .we (mio_outsel_3_gated_we),
9161 .wd (mio_outsel_3_wd),
9162
9163 // from internal hardware
9164 .de (1'b0),
9165 .d ('0),
9166
9167 // to internal hardware
9168 .qe (),
9169 .q (reg2hw.mio_outsel[3].q),
9170 .ds (),
9171
9172 // to register interface (read)
9173 .qs (mio_outsel_3_qs)
9174 );
9175
9176
9177 // Subregister 4 of Multireg mio_outsel
9178 // R[mio_outsel_4]: V(False)
9179 // Create REGWEN-gated WE signal
9180 logic mio_outsel_4_gated_we;
9181 1/1 assign mio_outsel_4_gated_we = mio_outsel_4_we & mio_outsel_regwen_4_qs;
Tests: T25 T27 T37
9182 prim_subreg #(
9183 .DW (7),
9184 .SwAccess(prim_subreg_pkg::SwAccessRW),
9185 .RESVAL (7'h2),
9186 .Mubi (1'b0)
9187 ) u_mio_outsel_4 (
9188 .clk_i (clk_i),
9189 .rst_ni (rst_ni),
9190
9191 // from register interface
9192 .we (mio_outsel_4_gated_we),
9193 .wd (mio_outsel_4_wd),
9194
9195 // from internal hardware
9196 .de (1'b0),
9197 .d ('0),
9198
9199 // to internal hardware
9200 .qe (),
9201 .q (reg2hw.mio_outsel[4].q),
9202 .ds (),
9203
9204 // to register interface (read)
9205 .qs (mio_outsel_4_qs)
9206 );
9207
9208
9209 // Subregister 5 of Multireg mio_outsel
9210 // R[mio_outsel_5]: V(False)
9211 // Create REGWEN-gated WE signal
9212 logic mio_outsel_5_gated_we;
9213 1/1 assign mio_outsel_5_gated_we = mio_outsel_5_we & mio_outsel_regwen_5_qs;
Tests: T4 T25 T27
9214 prim_subreg #(
9215 .DW (7),
9216 .SwAccess(prim_subreg_pkg::SwAccessRW),
9217 .RESVAL (7'h2),
9218 .Mubi (1'b0)
9219 ) u_mio_outsel_5 (
9220 .clk_i (clk_i),
9221 .rst_ni (rst_ni),
9222
9223 // from register interface
9224 .we (mio_outsel_5_gated_we),
9225 .wd (mio_outsel_5_wd),
9226
9227 // from internal hardware
9228 .de (1'b0),
9229 .d ('0),
9230
9231 // to internal hardware
9232 .qe (),
9233 .q (reg2hw.mio_outsel[5].q),
9234 .ds (),
9235
9236 // to register interface (read)
9237 .qs (mio_outsel_5_qs)
9238 );
9239
9240
9241 // Subregister 6 of Multireg mio_outsel
9242 // R[mio_outsel_6]: V(False)
9243 // Create REGWEN-gated WE signal
9244 logic mio_outsel_6_gated_we;
9245 1/1 assign mio_outsel_6_gated_we = mio_outsel_6_we & mio_outsel_regwen_6_qs;
Tests: T25 T27 T42
9246 prim_subreg #(
9247 .DW (7),
9248 .SwAccess(prim_subreg_pkg::SwAccessRW),
9249 .RESVAL (7'h2),
9250 .Mubi (1'b0)
9251 ) u_mio_outsel_6 (
9252 .clk_i (clk_i),
9253 .rst_ni (rst_ni),
9254
9255 // from register interface
9256 .we (mio_outsel_6_gated_we),
9257 .wd (mio_outsel_6_wd),
9258
9259 // from internal hardware
9260 .de (1'b0),
9261 .d ('0),
9262
9263 // to internal hardware
9264 .qe (),
9265 .q (reg2hw.mio_outsel[6].q),
9266 .ds (),
9267
9268 // to register interface (read)
9269 .qs (mio_outsel_6_qs)
9270 );
9271
9272
9273 // Subregister 7 of Multireg mio_outsel
9274 // R[mio_outsel_7]: V(False)
9275 // Create REGWEN-gated WE signal
9276 logic mio_outsel_7_gated_we;
9277 1/1 assign mio_outsel_7_gated_we = mio_outsel_7_we & mio_outsel_regwen_7_qs;
Tests: T25 T27 T62
9278 prim_subreg #(
9279 .DW (7),
9280 .SwAccess(prim_subreg_pkg::SwAccessRW),
9281 .RESVAL (7'h2),
9282 .Mubi (1'b0)
9283 ) u_mio_outsel_7 (
9284 .clk_i (clk_i),
9285 .rst_ni (rst_ni),
9286
9287 // from register interface
9288 .we (mio_outsel_7_gated_we),
9289 .wd (mio_outsel_7_wd),
9290
9291 // from internal hardware
9292 .de (1'b0),
9293 .d ('0),
9294
9295 // to internal hardware
9296 .qe (),
9297 .q (reg2hw.mio_outsel[7].q),
9298 .ds (),
9299
9300 // to register interface (read)
9301 .qs (mio_outsel_7_qs)
9302 );
9303
9304
9305 // Subregister 8 of Multireg mio_outsel
9306 // R[mio_outsel_8]: V(False)
9307 // Create REGWEN-gated WE signal
9308 logic mio_outsel_8_gated_we;
9309 1/1 assign mio_outsel_8_gated_we = mio_outsel_8_we & mio_outsel_regwen_8_qs;
Tests: T27 T62 T37
9310 prim_subreg #(
9311 .DW (7),
9312 .SwAccess(prim_subreg_pkg::SwAccessRW),
9313 .RESVAL (7'h2),
9314 .Mubi (1'b0)
9315 ) u_mio_outsel_8 (
9316 .clk_i (clk_i),
9317 .rst_ni (rst_ni),
9318
9319 // from register interface
9320 .we (mio_outsel_8_gated_we),
9321 .wd (mio_outsel_8_wd),
9322
9323 // from internal hardware
9324 .de (1'b0),
9325 .d ('0),
9326
9327 // to internal hardware
9328 .qe (),
9329 .q (reg2hw.mio_outsel[8].q),
9330 .ds (),
9331
9332 // to register interface (read)
9333 .qs (mio_outsel_8_qs)
9334 );
9335
9336
9337 // Subregister 9 of Multireg mio_outsel
9338 // R[mio_outsel_9]: V(False)
9339 // Create REGWEN-gated WE signal
9340 logic mio_outsel_9_gated_we;
9341 1/1 assign mio_outsel_9_gated_we = mio_outsel_9_we & mio_outsel_regwen_9_qs;
Tests: T9 T10 T11
9342 prim_subreg #(
9343 .DW (7),
9344 .SwAccess(prim_subreg_pkg::SwAccessRW),
9345 .RESVAL (7'h2),
9346 .Mubi (1'b0)
9347 ) u_mio_outsel_9 (
9348 .clk_i (clk_i),
9349 .rst_ni (rst_ni),
9350
9351 // from register interface
9352 .we (mio_outsel_9_gated_we),
9353 .wd (mio_outsel_9_wd),
9354
9355 // from internal hardware
9356 .de (1'b0),
9357 .d ('0),
9358
9359 // to internal hardware
9360 .qe (),
9361 .q (reg2hw.mio_outsel[9].q),
9362 .ds (),
9363
9364 // to register interface (read)
9365 .qs (mio_outsel_9_qs)
9366 );
9367
9368
9369 // Subregister 10 of Multireg mio_outsel
9370 // R[mio_outsel_10]: V(False)
9371 // Create REGWEN-gated WE signal
9372 logic mio_outsel_10_gated_we;
9373 1/1 assign mio_outsel_10_gated_we = mio_outsel_10_we & mio_outsel_regwen_10_qs;
Tests: T9 T10 T11
9374 prim_subreg #(
9375 .DW (7),
9376 .SwAccess(prim_subreg_pkg::SwAccessRW),
9377 .RESVAL (7'h2),
9378 .Mubi (1'b0)
9379 ) u_mio_outsel_10 (
9380 .clk_i (clk_i),
9381 .rst_ni (rst_ni),
9382
9383 // from register interface
9384 .we (mio_outsel_10_gated_we),
9385 .wd (mio_outsel_10_wd),
9386
9387 // from internal hardware
9388 .de (1'b0),
9389 .d ('0),
9390
9391 // to internal hardware
9392 .qe (),
9393 .q (reg2hw.mio_outsel[10].q),
9394 .ds (),
9395
9396 // to register interface (read)
9397 .qs (mio_outsel_10_qs)
9398 );
9399
9400
9401 // Subregister 11 of Multireg mio_outsel
9402 // R[mio_outsel_11]: V(False)
9403 // Create REGWEN-gated WE signal
9404 logic mio_outsel_11_gated_we;
9405 1/1 assign mio_outsel_11_gated_we = mio_outsel_11_we & mio_outsel_regwen_11_qs;
Tests: T10 T11 T37
9406 prim_subreg #(
9407 .DW (7),
9408 .SwAccess(prim_subreg_pkg::SwAccessRW),
9409 .RESVAL (7'h2),
9410 .Mubi (1'b0)
9411 ) u_mio_outsel_11 (
9412 .clk_i (clk_i),
9413 .rst_ni (rst_ni),
9414
9415 // from register interface
9416 .we (mio_outsel_11_gated_we),
9417 .wd (mio_outsel_11_wd),
9418
9419 // from internal hardware
9420 .de (1'b0),
9421 .d ('0),
9422
9423 // to internal hardware
9424 .qe (),
9425 .q (reg2hw.mio_outsel[11].q),
9426 .ds (),
9427
9428 // to register interface (read)
9429 .qs (mio_outsel_11_qs)
9430 );
9431
9432
9433 // Subregister 12 of Multireg mio_outsel
9434 // R[mio_outsel_12]: V(False)
9435 // Create REGWEN-gated WE signal
9436 logic mio_outsel_12_gated_we;
9437 1/1 assign mio_outsel_12_gated_we = mio_outsel_12_we & mio_outsel_regwen_12_qs;
Tests: T9 T10 T11
9438 prim_subreg #(
9439 .DW (7),
9440 .SwAccess(prim_subreg_pkg::SwAccessRW),
9441 .RESVAL (7'h2),
9442 .Mubi (1'b0)
9443 ) u_mio_outsel_12 (
9444 .clk_i (clk_i),
9445 .rst_ni (rst_ni),
9446
9447 // from register interface
9448 .we (mio_outsel_12_gated_we),
9449 .wd (mio_outsel_12_wd),
9450
9451 // from internal hardware
9452 .de (1'b0),
9453 .d ('0),
9454
9455 // to internal hardware
9456 .qe (),
9457 .q (reg2hw.mio_outsel[12].q),
9458 .ds (),
9459
9460 // to register interface (read)
9461 .qs (mio_outsel_12_qs)
9462 );
9463
9464
9465 // Subregister 13 of Multireg mio_outsel
9466 // R[mio_outsel_13]: V(False)
9467 // Create REGWEN-gated WE signal
9468 logic mio_outsel_13_gated_we;
9469 1/1 assign mio_outsel_13_gated_we = mio_outsel_13_we & mio_outsel_regwen_13_qs;
Tests: T1 T2 T3
9470 prim_subreg #(
9471 .DW (7),
9472 .SwAccess(prim_subreg_pkg::SwAccessRW),
9473 .RESVAL (7'h2),
9474 .Mubi (1'b0)
9475 ) u_mio_outsel_13 (
9476 .clk_i (clk_i),
9477 .rst_ni (rst_ni),
9478
9479 // from register interface
9480 .we (mio_outsel_13_gated_we),
9481 .wd (mio_outsel_13_wd),
9482
9483 // from internal hardware
9484 .de (1'b0),
9485 .d ('0),
9486
9487 // to internal hardware
9488 .qe (),
9489 .q (reg2hw.mio_outsel[13].q),
9490 .ds (),
9491
9492 // to register interface (read)
9493 .qs (mio_outsel_13_qs)
9494 );
9495
9496
9497 // Subregister 14 of Multireg mio_outsel
9498 // R[mio_outsel_14]: V(False)
9499 // Create REGWEN-gated WE signal
9500 logic mio_outsel_14_gated_we;
9501 1/1 assign mio_outsel_14_gated_we = mio_outsel_14_we & mio_outsel_regwen_14_qs;
Tests: T1 T2 T3
9502 prim_subreg #(
9503 .DW (7),
9504 .SwAccess(prim_subreg_pkg::SwAccessRW),
9505 .RESVAL (7'h2),
9506 .Mubi (1'b0)
9507 ) u_mio_outsel_14 (
9508 .clk_i (clk_i),
9509 .rst_ni (rst_ni),
9510
9511 // from register interface
9512 .we (mio_outsel_14_gated_we),
9513 .wd (mio_outsel_14_wd),
9514
9515 // from internal hardware
9516 .de (1'b0),
9517 .d ('0),
9518
9519 // to internal hardware
9520 .qe (),
9521 .q (reg2hw.mio_outsel[14].q),
9522 .ds (),
9523
9524 // to register interface (read)
9525 .qs (mio_outsel_14_qs)
9526 );
9527
9528
9529 // Subregister 15 of Multireg mio_outsel
9530 // R[mio_outsel_15]: V(False)
9531 // Create REGWEN-gated WE signal
9532 logic mio_outsel_15_gated_we;
9533 1/1 assign mio_outsel_15_gated_we = mio_outsel_15_we & mio_outsel_regwen_15_qs;
Tests: T9 T27 T37
9534 prim_subreg #(
9535 .DW (7),
9536 .SwAccess(prim_subreg_pkg::SwAccessRW),
9537 .RESVAL (7'h2),
9538 .Mubi (1'b0)
9539 ) u_mio_outsel_15 (
9540 .clk_i (clk_i),
9541 .rst_ni (rst_ni),
9542
9543 // from register interface
9544 .we (mio_outsel_15_gated_we),
9545 .wd (mio_outsel_15_wd),
9546
9547 // from internal hardware
9548 .de (1'b0),
9549 .d ('0),
9550
9551 // to internal hardware
9552 .qe (),
9553 .q (reg2hw.mio_outsel[15].q),
9554 .ds (),
9555
9556 // to register interface (read)
9557 .qs (mio_outsel_15_qs)
9558 );
9559
9560
9561 // Subregister 16 of Multireg mio_outsel
9562 // R[mio_outsel_16]: V(False)
9563 // Create REGWEN-gated WE signal
9564 logic mio_outsel_16_gated_we;
9565 1/1 assign mio_outsel_16_gated_we = mio_outsel_16_we & mio_outsel_regwen_16_qs;
Tests: T27 T13 T15
9566 prim_subreg #(
9567 .DW (7),
9568 .SwAccess(prim_subreg_pkg::SwAccessRW),
9569 .RESVAL (7'h2),
9570 .Mubi (1'b0)
9571 ) u_mio_outsel_16 (
9572 .clk_i (clk_i),
9573 .rst_ni (rst_ni),
9574
9575 // from register interface
9576 .we (mio_outsel_16_gated_we),
9577 .wd (mio_outsel_16_wd),
9578
9579 // from internal hardware
9580 .de (1'b0),
9581 .d ('0),
9582
9583 // to internal hardware
9584 .qe (),
9585 .q (reg2hw.mio_outsel[16].q),
9586 .ds (),
9587
9588 // to register interface (read)
9589 .qs (mio_outsel_16_qs)
9590 );
9591
9592
9593 // Subregister 17 of Multireg mio_outsel
9594 // R[mio_outsel_17]: V(False)
9595 // Create REGWEN-gated WE signal
9596 logic mio_outsel_17_gated_we;
9597 1/1 assign mio_outsel_17_gated_we = mio_outsel_17_we & mio_outsel_regwen_17_qs;
Tests: T27 T37 T42
9598 prim_subreg #(
9599 .DW (7),
9600 .SwAccess(prim_subreg_pkg::SwAccessRW),
9601 .RESVAL (7'h2),
9602 .Mubi (1'b0)
9603 ) u_mio_outsel_17 (
9604 .clk_i (clk_i),
9605 .rst_ni (rst_ni),
9606
9607 // from register interface
9608 .we (mio_outsel_17_gated_we),
9609 .wd (mio_outsel_17_wd),
9610
9611 // from internal hardware
9612 .de (1'b0),
9613 .d ('0),
9614
9615 // to internal hardware
9616 .qe (),
9617 .q (reg2hw.mio_outsel[17].q),
9618 .ds (),
9619
9620 // to register interface (read)
9621 .qs (mio_outsel_17_qs)
9622 );
9623
9624
9625 // Subregister 18 of Multireg mio_outsel
9626 // R[mio_outsel_18]: V(False)
9627 // Create REGWEN-gated WE signal
9628 logic mio_outsel_18_gated_we;
9629 1/1 assign mio_outsel_18_gated_we = mio_outsel_18_we & mio_outsel_regwen_18_qs;
Tests: T5 T27 T64
9630 prim_subreg #(
9631 .DW (7),
9632 .SwAccess(prim_subreg_pkg::SwAccessRW),
9633 .RESVAL (7'h2),
9634 .Mubi (1'b0)
9635 ) u_mio_outsel_18 (
9636 .clk_i (clk_i),
9637 .rst_ni (rst_ni),
9638
9639 // from register interface
9640 .we (mio_outsel_18_gated_we),
9641 .wd (mio_outsel_18_wd),
9642
9643 // from internal hardware
9644 .de (1'b0),
9645 .d ('0),
9646
9647 // to internal hardware
9648 .qe (),
9649 .q (reg2hw.mio_outsel[18].q),
9650 .ds (),
9651
9652 // to register interface (read)
9653 .qs (mio_outsel_18_qs)
9654 );
9655
9656
9657 // Subregister 19 of Multireg mio_outsel
9658 // R[mio_outsel_19]: V(False)
9659 // Create REGWEN-gated WE signal
9660 logic mio_outsel_19_gated_we;
9661 1/1 assign mio_outsel_19_gated_we = mio_outsel_19_we & mio_outsel_regwen_19_qs;
Tests: T5 T27 T64
9662 prim_subreg #(
9663 .DW (7),
9664 .SwAccess(prim_subreg_pkg::SwAccessRW),
9665 .RESVAL (7'h2),
9666 .Mubi (1'b0)
9667 ) u_mio_outsel_19 (
9668 .clk_i (clk_i),
9669 .rst_ni (rst_ni),
9670
9671 // from register interface
9672 .we (mio_outsel_19_gated_we),
9673 .wd (mio_outsel_19_wd),
9674
9675 // from internal hardware
9676 .de (1'b0),
9677 .d ('0),
9678
9679 // to internal hardware
9680 .qe (),
9681 .q (reg2hw.mio_outsel[19].q),
9682 .ds (),
9683
9684 // to register interface (read)
9685 .qs (mio_outsel_19_qs)
9686 );
9687
9688
9689 // Subregister 20 of Multireg mio_outsel
9690 // R[mio_outsel_20]: V(False)
9691 // Create REGWEN-gated WE signal
9692 logic mio_outsel_20_gated_we;
9693 1/1 assign mio_outsel_20_gated_we = mio_outsel_20_we & mio_outsel_regwen_20_qs;
Tests: T5 T27 T66
9694 prim_subreg #(
9695 .DW (7),
9696 .SwAccess(prim_subreg_pkg::SwAccessRW),
9697 .RESVAL (7'h2),
9698 .Mubi (1'b0)
9699 ) u_mio_outsel_20 (
9700 .clk_i (clk_i),
9701 .rst_ni (rst_ni),
9702
9703 // from register interface
9704 .we (mio_outsel_20_gated_we),
9705 .wd (mio_outsel_20_wd),
9706
9707 // from internal hardware
9708 .de (1'b0),
9709 .d ('0),
9710
9711 // to internal hardware
9712 .qe (),
9713 .q (reg2hw.mio_outsel[20].q),
9714 .ds (),
9715
9716 // to register interface (read)
9717 .qs (mio_outsel_20_qs)
9718 );
9719
9720
9721 // Subregister 21 of Multireg mio_outsel
9722 // R[mio_outsel_21]: V(False)
9723 // Create REGWEN-gated WE signal
9724 logic mio_outsel_21_gated_we;
9725 1/1 assign mio_outsel_21_gated_we = mio_outsel_21_we & mio_outsel_regwen_21_qs;
Tests: T5 T27 T66
9726 prim_subreg #(
9727 .DW (7),
9728 .SwAccess(prim_subreg_pkg::SwAccessRW),
9729 .RESVAL (7'h2),
9730 .Mubi (1'b0)
9731 ) u_mio_outsel_21 (
9732 .clk_i (clk_i),
9733 .rst_ni (rst_ni),
9734
9735 // from register interface
9736 .we (mio_outsel_21_gated_we),
9737 .wd (mio_outsel_21_wd),
9738
9739 // from internal hardware
9740 .de (1'b0),
9741 .d ('0),
9742
9743 // to internal hardware
9744 .qe (),
9745 .q (reg2hw.mio_outsel[21].q),
9746 .ds (),
9747
9748 // to register interface (read)
9749 .qs (mio_outsel_21_qs)
9750 );
9751
9752
9753 // Subregister 22 of Multireg mio_outsel
9754 // R[mio_outsel_22]: V(False)
9755 // Create REGWEN-gated WE signal
9756 logic mio_outsel_22_gated_we;
9757 1/1 assign mio_outsel_22_gated_we = mio_outsel_22_we & mio_outsel_regwen_22_qs;
Tests: T71 T96 T97
9758 prim_subreg #(
9759 .DW (7),
9760 .SwAccess(prim_subreg_pkg::SwAccessRW),
9761 .RESVAL (7'h2),
9762 .Mubi (1'b0)
9763 ) u_mio_outsel_22 (
9764 .clk_i (clk_i),
9765 .rst_ni (rst_ni),
9766
9767 // from register interface
9768 .we (mio_outsel_22_gated_we),
9769 .wd (mio_outsel_22_wd),
9770
9771 // from internal hardware
9772 .de (1'b0),
9773 .d ('0),
9774
9775 // to internal hardware
9776 .qe (),
9777 .q (reg2hw.mio_outsel[22].q),
9778 .ds (),
9779
9780 // to register interface (read)
9781 .qs (mio_outsel_22_qs)
9782 );
9783
9784
9785 // Subregister 23 of Multireg mio_outsel
9786 // R[mio_outsel_23]: V(False)
9787 // Create REGWEN-gated WE signal
9788 logic mio_outsel_23_gated_we;
9789 1/1 assign mio_outsel_23_gated_we = mio_outsel_23_we & mio_outsel_regwen_23_qs;
Tests: T24 T96 T97
9790 prim_subreg #(
9791 .DW (7),
9792 .SwAccess(prim_subreg_pkg::SwAccessRW),
9793 .RESVAL (7'h2),
9794 .Mubi (1'b0)
9795 ) u_mio_outsel_23 (
9796 .clk_i (clk_i),
9797 .rst_ni (rst_ni),
9798
9799 // from register interface
9800 .we (mio_outsel_23_gated_we),
9801 .wd (mio_outsel_23_wd),
9802
9803 // from internal hardware
9804 .de (1'b0),
9805 .d ('0),
9806
9807 // to internal hardware
9808 .qe (),
9809 .q (reg2hw.mio_outsel[23].q),
9810 .ds (),
9811
9812 // to register interface (read)
9813 .qs (mio_outsel_23_qs)
9814 );
9815
9816
9817 // Subregister 24 of Multireg mio_outsel
9818 // R[mio_outsel_24]: V(False)
9819 // Create REGWEN-gated WE signal
9820 logic mio_outsel_24_gated_we;
9821 1/1 assign mio_outsel_24_gated_we = mio_outsel_24_we & mio_outsel_regwen_24_qs;
Tests: T71 T96 T97
9822 prim_subreg #(
9823 .DW (7),
9824 .SwAccess(prim_subreg_pkg::SwAccessRW),
9825 .RESVAL (7'h2),
9826 .Mubi (1'b0)
9827 ) u_mio_outsel_24 (
9828 .clk_i (clk_i),
9829 .rst_ni (rst_ni),
9830
9831 // from register interface
9832 .we (mio_outsel_24_gated_we),
9833 .wd (mio_outsel_24_wd),
9834
9835 // from internal hardware
9836 .de (1'b0),
9837 .d ('0),
9838
9839 // to internal hardware
9840 .qe (),
9841 .q (reg2hw.mio_outsel[24].q),
9842 .ds (),
9843
9844 // to register interface (read)
9845 .qs (mio_outsel_24_qs)
9846 );
9847
9848
9849 // Subregister 25 of Multireg mio_outsel
9850 // R[mio_outsel_25]: V(False)
9851 // Create REGWEN-gated WE signal
9852 logic mio_outsel_25_gated_we;
9853 1/1 assign mio_outsel_25_gated_we = mio_outsel_25_we & mio_outsel_regwen_25_qs;
Tests: T1 T2 T3
9854 prim_subreg #(
9855 .DW (7),
9856 .SwAccess(prim_subreg_pkg::SwAccessRW),
9857 .RESVAL (7'h2),
9858 .Mubi (1'b0)
9859 ) u_mio_outsel_25 (
9860 .clk_i (clk_i),
9861 .rst_ni (rst_ni),
9862
9863 // from register interface
9864 .we (mio_outsel_25_gated_we),
9865 .wd (mio_outsel_25_wd),
9866
9867 // from internal hardware
9868 .de (1'b0),
9869 .d ('0),
9870
9871 // to internal hardware
9872 .qe (),
9873 .q (reg2hw.mio_outsel[25].q),
9874 .ds (),
9875
9876 // to register interface (read)
9877 .qs (mio_outsel_25_qs)
9878 );
9879
9880
9881 // Subregister 26 of Multireg mio_outsel
9882 // R[mio_outsel_26]: V(False)
9883 // Create REGWEN-gated WE signal
9884 logic mio_outsel_26_gated_we;
9885 1/1 assign mio_outsel_26_gated_we = mio_outsel_26_we & mio_outsel_regwen_26_qs;
Tests: T1 T2 T3
9886 prim_subreg #(
9887 .DW (7),
9888 .SwAccess(prim_subreg_pkg::SwAccessRW),
9889 .RESVAL (7'h2),
9890 .Mubi (1'b0)
9891 ) u_mio_outsel_26 (
9892 .clk_i (clk_i),
9893 .rst_ni (rst_ni),
9894
9895 // from register interface
9896 .we (mio_outsel_26_gated_we),
9897 .wd (mio_outsel_26_wd),
9898
9899 // from internal hardware
9900 .de (1'b0),
9901 .d ('0),
9902
9903 // to internal hardware
9904 .qe (),
9905 .q (reg2hw.mio_outsel[26].q),
9906 .ds (),
9907
9908 // to register interface (read)
9909 .qs (mio_outsel_26_qs)
9910 );
9911
9912
9913 // Subregister 27 of Multireg mio_outsel
9914 // R[mio_outsel_27]: V(False)
9915 // Create REGWEN-gated WE signal
9916 logic mio_outsel_27_gated_we;
9917 1/1 assign mio_outsel_27_gated_we = mio_outsel_27_we & mio_outsel_regwen_27_qs;
Tests: T71 T96 T97
9918 prim_subreg #(
9919 .DW (7),
9920 .SwAccess(prim_subreg_pkg::SwAccessRW),
9921 .RESVAL (7'h2),
9922 .Mubi (1'b0)
9923 ) u_mio_outsel_27 (
9924 .clk_i (clk_i),
9925 .rst_ni (rst_ni),
9926
9927 // from register interface
9928 .we (mio_outsel_27_gated_we),
9929 .wd (mio_outsel_27_wd),
9930
9931 // from internal hardware
9932 .de (1'b0),
9933 .d ('0),
9934
9935 // to internal hardware
9936 .qe (),
9937 .q (reg2hw.mio_outsel[27].q),
9938 .ds (),
9939
9940 // to register interface (read)
9941 .qs (mio_outsel_27_qs)
9942 );
9943
9944
9945 // Subregister 28 of Multireg mio_outsel
9946 // R[mio_outsel_28]: V(False)
9947 // Create REGWEN-gated WE signal
9948 logic mio_outsel_28_gated_we;
9949 1/1 assign mio_outsel_28_gated_we = mio_outsel_28_we & mio_outsel_regwen_28_qs;
Tests: T71 T96 T97
9950 prim_subreg #(
9951 .DW (7),
9952 .SwAccess(prim_subreg_pkg::SwAccessRW),
9953 .RESVAL (7'h2),
9954 .Mubi (1'b0)
9955 ) u_mio_outsel_28 (
9956 .clk_i (clk_i),
9957 .rst_ni (rst_ni),
9958
9959 // from register interface
9960 .we (mio_outsel_28_gated_we),
9961 .wd (mio_outsel_28_wd),
9962
9963 // from internal hardware
9964 .de (1'b0),
9965 .d ('0),
9966
9967 // to internal hardware
9968 .qe (),
9969 .q (reg2hw.mio_outsel[28].q),
9970 .ds (),
9971
9972 // to register interface (read)
9973 .qs (mio_outsel_28_qs)
9974 );
9975
9976
9977 // Subregister 29 of Multireg mio_outsel
9978 // R[mio_outsel_29]: V(False)
9979 // Create REGWEN-gated WE signal
9980 logic mio_outsel_29_gated_we;
9981 1/1 assign mio_outsel_29_gated_we = mio_outsel_29_we & mio_outsel_regwen_29_qs;
Tests: T1 T2 T3
9982 prim_subreg #(
9983 .DW (7),
9984 .SwAccess(prim_subreg_pkg::SwAccessRW),
9985 .RESVAL (7'h2),
9986 .Mubi (1'b0)
9987 ) u_mio_outsel_29 (
9988 .clk_i (clk_i),
9989 .rst_ni (rst_ni),
9990
9991 // from register interface
9992 .we (mio_outsel_29_gated_we),
9993 .wd (mio_outsel_29_wd),
9994
9995 // from internal hardware
9996 .de (1'b0),
9997 .d ('0),
9998
9999 // to internal hardware
10000 .qe (),
10001 .q (reg2hw.mio_outsel[29].q),
10002 .ds (),
10003
10004 // to register interface (read)
10005 .qs (mio_outsel_29_qs)
10006 );
10007
10008
10009 // Subregister 30 of Multireg mio_outsel
10010 // R[mio_outsel_30]: V(False)
10011 // Create REGWEN-gated WE signal
10012 logic mio_outsel_30_gated_we;
10013 1/1 assign mio_outsel_30_gated_we = mio_outsel_30_we & mio_outsel_regwen_30_qs;
Tests: T96 T97 T98
10014 prim_subreg #(
10015 .DW (7),
10016 .SwAccess(prim_subreg_pkg::SwAccessRW),
10017 .RESVAL (7'h2),
10018 .Mubi (1'b0)
10019 ) u_mio_outsel_30 (
10020 .clk_i (clk_i),
10021 .rst_ni (rst_ni),
10022
10023 // from register interface
10024 .we (mio_outsel_30_gated_we),
10025 .wd (mio_outsel_30_wd),
10026
10027 // from internal hardware
10028 .de (1'b0),
10029 .d ('0),
10030
10031 // to internal hardware
10032 .qe (),
10033 .q (reg2hw.mio_outsel[30].q),
10034 .ds (),
10035
10036 // to register interface (read)
10037 .qs (mio_outsel_30_qs)
10038 );
10039
10040
10041 // Subregister 31 of Multireg mio_outsel
10042 // R[mio_outsel_31]: V(False)
10043 // Create REGWEN-gated WE signal
10044 logic mio_outsel_31_gated_we;
10045 1/1 assign mio_outsel_31_gated_we = mio_outsel_31_we & mio_outsel_regwen_31_qs;
Tests: T27 T13 T41
10046 prim_subreg #(
10047 .DW (7),
10048 .SwAccess(prim_subreg_pkg::SwAccessRW),
10049 .RESVAL (7'h2),
10050 .Mubi (1'b0)
10051 ) u_mio_outsel_31 (
10052 .clk_i (clk_i),
10053 .rst_ni (rst_ni),
10054
10055 // from register interface
10056 .we (mio_outsel_31_gated_we),
10057 .wd (mio_outsel_31_wd),
10058
10059 // from internal hardware
10060 .de (1'b0),
10061 .d ('0),
10062
10063 // to internal hardware
10064 .qe (),
10065 .q (reg2hw.mio_outsel[31].q),
10066 .ds (),
10067
10068 // to register interface (read)
10069 .qs (mio_outsel_31_qs)
10070 );
10071
10072
10073 // Subregister 32 of Multireg mio_outsel
10074 // R[mio_outsel_32]: V(False)
10075 // Create REGWEN-gated WE signal
10076 logic mio_outsel_32_gated_we;
10077 1/1 assign mio_outsel_32_gated_we = mio_outsel_32_we & mio_outsel_regwen_32_qs;
Tests: T27 T35 T75
10078 prim_subreg #(
10079 .DW (7),
10080 .SwAccess(prim_subreg_pkg::SwAccessRW),
10081 .RESVAL (7'h2),
10082 .Mubi (1'b0)
10083 ) u_mio_outsel_32 (
10084 .clk_i (clk_i),
10085 .rst_ni (rst_ni),
10086
10087 // from register interface
10088 .we (mio_outsel_32_gated_we),
10089 .wd (mio_outsel_32_wd),
10090
10091 // from internal hardware
10092 .de (1'b0),
10093 .d ('0),
10094
10095 // to internal hardware
10096 .qe (),
10097 .q (reg2hw.mio_outsel[32].q),
10098 .ds (),
10099
10100 // to register interface (read)
10101 .qs (mio_outsel_32_qs)
10102 );
10103
10104
10105 // Subregister 33 of Multireg mio_outsel
10106 // R[mio_outsel_33]: V(False)
10107 // Create REGWEN-gated WE signal
10108 logic mio_outsel_33_gated_we;
10109 1/1 assign mio_outsel_33_gated_we = mio_outsel_33_we & mio_outsel_regwen_33_qs;
Tests: T27 T35 T75
10110 prim_subreg #(
10111 .DW (7),
10112 .SwAccess(prim_subreg_pkg::SwAccessRW),
10113 .RESVAL (7'h2),
10114 .Mubi (1'b0)
10115 ) u_mio_outsel_33 (
10116 .clk_i (clk_i),
10117 .rst_ni (rst_ni),
10118
10119 // from register interface
10120 .we (mio_outsel_33_gated_we),
10121 .wd (mio_outsel_33_wd),
10122
10123 // from internal hardware
10124 .de (1'b0),
10125 .d ('0),
10126
10127 // to internal hardware
10128 .qe (),
10129 .q (reg2hw.mio_outsel[33].q),
10130 .ds (),
10131
10132 // to register interface (read)
10133 .qs (mio_outsel_33_qs)
10134 );
10135
10136
10137 // Subregister 34 of Multireg mio_outsel
10138 // R[mio_outsel_34]: V(False)
10139 // Create REGWEN-gated WE signal
10140 logic mio_outsel_34_gated_we;
10141 1/1 assign mio_outsel_34_gated_we = mio_outsel_34_we & mio_outsel_regwen_34_qs;
Tests: T27 T35 T75
10142 prim_subreg #(
10143 .DW (7),
10144 .SwAccess(prim_subreg_pkg::SwAccessRW),
10145 .RESVAL (7'h2),
10146 .Mubi (1'b0)
10147 ) u_mio_outsel_34 (
10148 .clk_i (clk_i),
10149 .rst_ni (rst_ni),
10150
10151 // from register interface
10152 .we (mio_outsel_34_gated_we),
10153 .wd (mio_outsel_34_wd),
10154
10155 // from internal hardware
10156 .de (1'b0),
10157 .d ('0),
10158
10159 // to internal hardware
10160 .qe (),
10161 .q (reg2hw.mio_outsel[34].q),
10162 .ds (),
10163
10164 // to register interface (read)
10165 .qs (mio_outsel_34_qs)
10166 );
10167
10168
10169 // Subregister 35 of Multireg mio_outsel
10170 // R[mio_outsel_35]: V(False)
10171 // Create REGWEN-gated WE signal
10172 logic mio_outsel_35_gated_we;
10173 1/1 assign mio_outsel_35_gated_we = mio_outsel_35_we & mio_outsel_regwen_35_qs;
Tests: T27 T37 T42
10174 prim_subreg #(
10175 .DW (7),
10176 .SwAccess(prim_subreg_pkg::SwAccessRW),
10177 .RESVAL (7'h2),
10178 .Mubi (1'b0)
10179 ) u_mio_outsel_35 (
10180 .clk_i (clk_i),
10181 .rst_ni (rst_ni),
10182
10183 // from register interface
10184 .we (mio_outsel_35_gated_we),
10185 .wd (mio_outsel_35_wd),
10186
10187 // from internal hardware
10188 .de (1'b0),
10189 .d ('0),
10190
10191 // to internal hardware
10192 .qe (),
10193 .q (reg2hw.mio_outsel[35].q),
10194 .ds (),
10195
10196 // to register interface (read)
10197 .qs (mio_outsel_35_qs)
10198 );
10199
10200
10201 // Subregister 36 of Multireg mio_outsel
10202 // R[mio_outsel_36]: V(False)
10203 // Create REGWEN-gated WE signal
10204 logic mio_outsel_36_gated_we;
10205 1/1 assign mio_outsel_36_gated_we = mio_outsel_36_we & mio_outsel_regwen_36_qs;
Tests: T27 T37 T42
10206 prim_subreg #(
10207 .DW (7),
10208 .SwAccess(prim_subreg_pkg::SwAccessRW),
10209 .RESVAL (7'h2),
10210 .Mubi (1'b0)
10211 ) u_mio_outsel_36 (
10212 .clk_i (clk_i),
10213 .rst_ni (rst_ni),
10214
10215 // from register interface
10216 .we (mio_outsel_36_gated_we),
10217 .wd (mio_outsel_36_wd),
10218
10219 // from internal hardware
10220 .de (1'b0),
10221 .d ('0),
10222
10223 // to internal hardware
10224 .qe (),
10225 .q (reg2hw.mio_outsel[36].q),
10226 .ds (),
10227
10228 // to register interface (read)
10229 .qs (mio_outsel_36_qs)
10230 );
10231
10232
10233 // Subregister 37 of Multireg mio_outsel
10234 // R[mio_outsel_37]: V(False)
10235 // Create REGWEN-gated WE signal
10236 logic mio_outsel_37_gated_we;
10237 1/1 assign mio_outsel_37_gated_we = mio_outsel_37_we & mio_outsel_regwen_37_qs;
Tests: T27 T37 T42
10238 prim_subreg #(
10239 .DW (7),
10240 .SwAccess(prim_subreg_pkg::SwAccessRW),
10241 .RESVAL (7'h2),
10242 .Mubi (1'b0)
10243 ) u_mio_outsel_37 (
10244 .clk_i (clk_i),
10245 .rst_ni (rst_ni),
10246
10247 // from register interface
10248 .we (mio_outsel_37_gated_we),
10249 .wd (mio_outsel_37_wd),
10250
10251 // from internal hardware
10252 .de (1'b0),
10253 .d ('0),
10254
10255 // to internal hardware
10256 .qe (),
10257 .q (reg2hw.mio_outsel[37].q),
10258 .ds (),
10259
10260 // to register interface (read)
10261 .qs (mio_outsel_37_qs)
10262 );
10263
10264
10265 // Subregister 38 of Multireg mio_outsel
10266 // R[mio_outsel_38]: V(False)
10267 // Create REGWEN-gated WE signal
10268 logic mio_outsel_38_gated_we;
10269 1/1 assign mio_outsel_38_gated_we = mio_outsel_38_we & mio_outsel_regwen_38_qs;
Tests: T27 T37 T42
10270 prim_subreg #(
10271 .DW (7),
10272 .SwAccess(prim_subreg_pkg::SwAccessRW),
10273 .RESVAL (7'h2),
10274 .Mubi (1'b0)
10275 ) u_mio_outsel_38 (
10276 .clk_i (clk_i),
10277 .rst_ni (rst_ni),
10278
10279 // from register interface
10280 .we (mio_outsel_38_gated_we),
10281 .wd (mio_outsel_38_wd),
10282
10283 // from internal hardware
10284 .de (1'b0),
10285 .d ('0),
10286
10287 // to internal hardware
10288 .qe (),
10289 .q (reg2hw.mio_outsel[38].q),
10290 .ds (),
10291
10292 // to register interface (read)
10293 .qs (mio_outsel_38_qs)
10294 );
10295
10296
10297 // Subregister 39 of Multireg mio_outsel
10298 // R[mio_outsel_39]: V(False)
10299 // Create REGWEN-gated WE signal
10300 logic mio_outsel_39_gated_we;
10301 1/1 assign mio_outsel_39_gated_we = mio_outsel_39_we & mio_outsel_regwen_39_qs;
Tests: T27 T42 T43
10302 prim_subreg #(
10303 .DW (7),
10304 .SwAccess(prim_subreg_pkg::SwAccessRW),
10305 .RESVAL (7'h2),
10306 .Mubi (1'b0)
10307 ) u_mio_outsel_39 (
10308 .clk_i (clk_i),
10309 .rst_ni (rst_ni),
10310
10311 // from register interface
10312 .we (mio_outsel_39_gated_we),
10313 .wd (mio_outsel_39_wd),
10314
10315 // from internal hardware
10316 .de (1'b0),
10317 .d ('0),
10318
10319 // to internal hardware
10320 .qe (),
10321 .q (reg2hw.mio_outsel[39].q),
10322 .ds (),
10323
10324 // to register interface (read)
10325 .qs (mio_outsel_39_qs)
10326 );
10327
10328
10329 // Subregister 40 of Multireg mio_outsel
10330 // R[mio_outsel_40]: V(False)
10331 // Create REGWEN-gated WE signal
10332 logic mio_outsel_40_gated_we;
10333 1/1 assign mio_outsel_40_gated_we = mio_outsel_40_we & mio_outsel_regwen_40_qs;
Tests: T27 T13 T37
10334 prim_subreg #(
10335 .DW (7),
10336 .SwAccess(prim_subreg_pkg::SwAccessRW),
10337 .RESVAL (7'h2),
10338 .Mubi (1'b0)
10339 ) u_mio_outsel_40 (
10340 .clk_i (clk_i),
10341 .rst_ni (rst_ni),
10342
10343 // from register interface
10344 .we (mio_outsel_40_gated_we),
10345 .wd (mio_outsel_40_wd),
10346
10347 // from internal hardware
10348 .de (1'b0),
10349 .d ('0),
10350
10351 // to internal hardware
10352 .qe (),
10353 .q (reg2hw.mio_outsel[40].q),
10354 .ds (),
10355
10356 // to register interface (read)
10357 .qs (mio_outsel_40_qs)
10358 );
10359
10360
10361 // Subregister 41 of Multireg mio_outsel
10362 // R[mio_outsel_41]: V(False)
10363 // Create REGWEN-gated WE signal
10364 logic mio_outsel_41_gated_we;
10365 1/1 assign mio_outsel_41_gated_we = mio_outsel_41_we & mio_outsel_regwen_41_qs;
Tests: T27 T13 T37
10366 prim_subreg #(
10367 .DW (7),
10368 .SwAccess(prim_subreg_pkg::SwAccessRW),
10369 .RESVAL (7'h2),
10370 .Mubi (1'b0)
10371 ) u_mio_outsel_41 (
10372 .clk_i (clk_i),
10373 .rst_ni (rst_ni),
10374
10375 // from register interface
10376 .we (mio_outsel_41_gated_we),
10377 .wd (mio_outsel_41_wd),
10378
10379 // from internal hardware
10380 .de (1'b0),
10381 .d ('0),
10382
10383 // to internal hardware
10384 .qe (),
10385 .q (reg2hw.mio_outsel[41].q),
10386 .ds (),
10387
10388 // to register interface (read)
10389 .qs (mio_outsel_41_qs)
10390 );
10391
10392
10393 // Subregister 42 of Multireg mio_outsel
10394 // R[mio_outsel_42]: V(False)
10395 // Create REGWEN-gated WE signal
10396 logic mio_outsel_42_gated_we;
10397 1/1 assign mio_outsel_42_gated_we = mio_outsel_42_we & mio_outsel_regwen_42_qs;
Tests: T27 T37 T42
10398 prim_subreg #(
10399 .DW (7),
10400 .SwAccess(prim_subreg_pkg::SwAccessRW),
10401 .RESVAL (7'h2),
10402 .Mubi (1'b0)
10403 ) u_mio_outsel_42 (
10404 .clk_i (clk_i),
10405 .rst_ni (rst_ni),
10406
10407 // from register interface
10408 .we (mio_outsel_42_gated_we),
10409 .wd (mio_outsel_42_wd),
10410
10411 // from internal hardware
10412 .de (1'b0),
10413 .d ('0),
10414
10415 // to internal hardware
10416 .qe (),
10417 .q (reg2hw.mio_outsel[42].q),
10418 .ds (),
10419
10420 // to register interface (read)
10421 .qs (mio_outsel_42_qs)
10422 );
10423
10424
10425 // Subregister 43 of Multireg mio_outsel
10426 // R[mio_outsel_43]: V(False)
10427 // Create REGWEN-gated WE signal
10428 logic mio_outsel_43_gated_we;
10429 1/1 assign mio_outsel_43_gated_we = mio_outsel_43_we & mio_outsel_regwen_43_qs;
Tests: T27 T37 T42
10430 prim_subreg #(
10431 .DW (7),
10432 .SwAccess(prim_subreg_pkg::SwAccessRW),
10433 .RESVAL (7'h2),
10434 .Mubi (1'b0)
10435 ) u_mio_outsel_43 (
10436 .clk_i (clk_i),
10437 .rst_ni (rst_ni),
10438
10439 // from register interface
10440 .we (mio_outsel_43_gated_we),
10441 .wd (mio_outsel_43_wd),
10442
10443 // from internal hardware
10444 .de (1'b0),
10445 .d ('0),
10446
10447 // to internal hardware
10448 .qe (),
10449 .q (reg2hw.mio_outsel[43].q),
10450 .ds (),
10451
10452 // to register interface (read)
10453 .qs (mio_outsel_43_qs)
10454 );
10455
10456
10457 // Subregister 44 of Multireg mio_outsel
10458 // R[mio_outsel_44]: V(False)
10459 // Create REGWEN-gated WE signal
10460 logic mio_outsel_44_gated_we;
10461 1/1 assign mio_outsel_44_gated_we = mio_outsel_44_we & mio_outsel_regwen_44_qs;
Tests: T27 T37 T42
10462 prim_subreg #(
10463 .DW (7),
10464 .SwAccess(prim_subreg_pkg::SwAccessRW),
10465 .RESVAL (7'h2),
10466 .Mubi (1'b0)
10467 ) u_mio_outsel_44 (
10468 .clk_i (clk_i),
10469 .rst_ni (rst_ni),
10470
10471 // from register interface
10472 .we (mio_outsel_44_gated_we),
10473 .wd (mio_outsel_44_wd),
10474
10475 // from internal hardware
10476 .de (1'b0),
10477 .d ('0),
10478
10479 // to internal hardware
10480 .qe (),
10481 .q (reg2hw.mio_outsel[44].q),
10482 .ds (),
10483
10484 // to register interface (read)
10485 .qs (mio_outsel_44_qs)
10486 );
10487
10488
10489 // Subregister 45 of Multireg mio_outsel
10490 // R[mio_outsel_45]: V(False)
10491 // Create REGWEN-gated WE signal
10492 logic mio_outsel_45_gated_we;
10493 1/1 assign mio_outsel_45_gated_we = mio_outsel_45_we & mio_outsel_regwen_45_qs;
Tests: T27 T37 T42
10494 prim_subreg #(
10495 .DW (7),
10496 .SwAccess(prim_subreg_pkg::SwAccessRW),
10497 .RESVAL (7'h2),
10498 .Mubi (1'b0)
10499 ) u_mio_outsel_45 (
10500 .clk_i (clk_i),
10501 .rst_ni (rst_ni),
10502
10503 // from register interface
10504 .we (mio_outsel_45_gated_we),
10505 .wd (mio_outsel_45_wd),
10506
10507 // from internal hardware
10508 .de (1'b0),
10509 .d ('0),
10510
10511 // to internal hardware
10512 .qe (),
10513 .q (reg2hw.mio_outsel[45].q),
10514 .ds (),
10515
10516 // to register interface (read)
10517 .qs (mio_outsel_45_qs)
10518 );
10519
10520
10521 // Subregister 46 of Multireg mio_outsel
10522 // R[mio_outsel_46]: V(False)
10523 // Create REGWEN-gated WE signal
10524 logic mio_outsel_46_gated_we;
10525 1/1 assign mio_outsel_46_gated_we = mio_outsel_46_we & mio_outsel_regwen_46_qs;
Tests: T27 T37 T42
10526 prim_subreg #(
10527 .DW (7),
10528 .SwAccess(prim_subreg_pkg::SwAccessRW),
10529 .RESVAL (7'h2),
10530 .Mubi (1'b0)
10531 ) u_mio_outsel_46 (
10532 .clk_i (clk_i),
10533 .rst_ni (rst_ni),
10534
10535 // from register interface
10536 .we (mio_outsel_46_gated_we),
10537 .wd (mio_outsel_46_wd),
10538
10539 // from internal hardware
10540 .de (1'b0),
10541 .d ('0),
10542
10543 // to internal hardware
10544 .qe (),
10545 .q (reg2hw.mio_outsel[46].q),
10546 .ds (),
10547
10548 // to register interface (read)
10549 .qs (mio_outsel_46_qs)
10550 );
10551
10552
10553 // Subregister 0 of Multireg mio_pad_attr_regwen
10554 // R[mio_pad_attr_regwen_0]: V(False)
10555 prim_subreg #(
10556 .DW (1),
10557 .SwAccess(prim_subreg_pkg::SwAccessW0C),
10558 .RESVAL (1'h1),
10559 .Mubi (1'b0)
10560 ) u_mio_pad_attr_regwen_0 (
10561 .clk_i (clk_i),
10562 .rst_ni (rst_ni),
10563
10564 // from register interface
10565 .we (mio_pad_attr_regwen_0_we),
10566 .wd (mio_pad_attr_regwen_0_wd),
10567
10568 // from internal hardware
10569 .de (1'b0),
10570 .d ('0),
10571
10572 // to internal hardware
10573 .qe (),
10574 .q (),
10575 .ds (),
10576
10577 // to register interface (read)
10578 .qs (mio_pad_attr_regwen_0_qs)
10579 );
10580
10581
10582 // Subregister 1 of Multireg mio_pad_attr_regwen
10583 // R[mio_pad_attr_regwen_1]: V(False)
10584 prim_subreg #(
10585 .DW (1),
10586 .SwAccess(prim_subreg_pkg::SwAccessW0C),
10587 .RESVAL (1'h1),
10588 .Mubi (1'b0)
10589 ) u_mio_pad_attr_regwen_1 (
10590 .clk_i (clk_i),
10591 .rst_ni (rst_ni),
10592
10593 // from register interface
10594 .we (mio_pad_attr_regwen_1_we),
10595 .wd (mio_pad_attr_regwen_1_wd),
10596
10597 // from internal hardware
10598 .de (1'b0),
10599 .d ('0),
10600
10601 // to internal hardware
10602 .qe (),
10603 .q (),
10604 .ds (),
10605
10606 // to register interface (read)
10607 .qs (mio_pad_attr_regwen_1_qs)
10608 );
10609
10610
10611 // Subregister 2 of Multireg mio_pad_attr_regwen
10612 // R[mio_pad_attr_regwen_2]: V(False)
10613 prim_subreg #(
10614 .DW (1),
10615 .SwAccess(prim_subreg_pkg::SwAccessW0C),
10616 .RESVAL (1'h1),
10617 .Mubi (1'b0)
10618 ) u_mio_pad_attr_regwen_2 (
10619 .clk_i (clk_i),
10620 .rst_ni (rst_ni),
10621
10622 // from register interface
10623 .we (mio_pad_attr_regwen_2_we),
10624 .wd (mio_pad_attr_regwen_2_wd),
10625
10626 // from internal hardware
10627 .de (1'b0),
10628 .d ('0),
10629
10630 // to internal hardware
10631 .qe (),
10632 .q (),
10633 .ds (),
10634
10635 // to register interface (read)
10636 .qs (mio_pad_attr_regwen_2_qs)
10637 );
10638
10639
10640 // Subregister 3 of Multireg mio_pad_attr_regwen
10641 // R[mio_pad_attr_regwen_3]: V(False)
10642 prim_subreg #(
10643 .DW (1),
10644 .SwAccess(prim_subreg_pkg::SwAccessW0C),
10645 .RESVAL (1'h1),
10646 .Mubi (1'b0)
10647 ) u_mio_pad_attr_regwen_3 (
10648 .clk_i (clk_i),
10649 .rst_ni (rst_ni),
10650
10651 // from register interface
10652 .we (mio_pad_attr_regwen_3_we),
10653 .wd (mio_pad_attr_regwen_3_wd),
10654
10655 // from internal hardware
10656 .de (1'b0),
10657 .d ('0),
10658
10659 // to internal hardware
10660 .qe (),
10661 .q (),
10662 .ds (),
10663
10664 // to register interface (read)
10665 .qs (mio_pad_attr_regwen_3_qs)
10666 );
10667
10668
10669 // Subregister 4 of Multireg mio_pad_attr_regwen
10670 // R[mio_pad_attr_regwen_4]: V(False)
10671 prim_subreg #(
10672 .DW (1),
10673 .SwAccess(prim_subreg_pkg::SwAccessW0C),
10674 .RESVAL (1'h1),
10675 .Mubi (1'b0)
10676 ) u_mio_pad_attr_regwen_4 (
10677 .clk_i (clk_i),
10678 .rst_ni (rst_ni),
10679
10680 // from register interface
10681 .we (mio_pad_attr_regwen_4_we),
10682 .wd (mio_pad_attr_regwen_4_wd),
10683
10684 // from internal hardware
10685 .de (1'b0),
10686 .d ('0),
10687
10688 // to internal hardware
10689 .qe (),
10690 .q (),
10691 .ds (),
10692
10693 // to register interface (read)
10694 .qs (mio_pad_attr_regwen_4_qs)
10695 );
10696
10697
10698 // Subregister 5 of Multireg mio_pad_attr_regwen
10699 // R[mio_pad_attr_regwen_5]: V(False)
10700 prim_subreg #(
10701 .DW (1),
10702 .SwAccess(prim_subreg_pkg::SwAccessW0C),
10703 .RESVAL (1'h1),
10704 .Mubi (1'b0)
10705 ) u_mio_pad_attr_regwen_5 (
10706 .clk_i (clk_i),
10707 .rst_ni (rst_ni),
10708
10709 // from register interface
10710 .we (mio_pad_attr_regwen_5_we),
10711 .wd (mio_pad_attr_regwen_5_wd),
10712
10713 // from internal hardware
10714 .de (1'b0),
10715 .d ('0),
10716
10717 // to internal hardware
10718 .qe (),
10719 .q (),
10720 .ds (),
10721
10722 // to register interface (read)
10723 .qs (mio_pad_attr_regwen_5_qs)
10724 );
10725
10726
10727 // Subregister 6 of Multireg mio_pad_attr_regwen
10728 // R[mio_pad_attr_regwen_6]: V(False)
10729 prim_subreg #(
10730 .DW (1),
10731 .SwAccess(prim_subreg_pkg::SwAccessW0C),
10732 .RESVAL (1'h1),
10733 .Mubi (1'b0)
10734 ) u_mio_pad_attr_regwen_6 (
10735 .clk_i (clk_i),
10736 .rst_ni (rst_ni),
10737
10738 // from register interface
10739 .we (mio_pad_attr_regwen_6_we),
10740 .wd (mio_pad_attr_regwen_6_wd),
10741
10742 // from internal hardware
10743 .de (1'b0),
10744 .d ('0),
10745
10746 // to internal hardware
10747 .qe (),
10748 .q (),
10749 .ds (),
10750
10751 // to register interface (read)
10752 .qs (mio_pad_attr_regwen_6_qs)
10753 );
10754
10755
10756 // Subregister 7 of Multireg mio_pad_attr_regwen
10757 // R[mio_pad_attr_regwen_7]: V(False)
10758 prim_subreg #(
10759 .DW (1),
10760 .SwAccess(prim_subreg_pkg::SwAccessW0C),
10761 .RESVAL (1'h1),
10762 .Mubi (1'b0)
10763 ) u_mio_pad_attr_regwen_7 (
10764 .clk_i (clk_i),
10765 .rst_ni (rst_ni),
10766
10767 // from register interface
10768 .we (mio_pad_attr_regwen_7_we),
10769 .wd (mio_pad_attr_regwen_7_wd),
10770
10771 // from internal hardware
10772 .de (1'b0),
10773 .d ('0),
10774
10775 // to internal hardware
10776 .qe (),
10777 .q (),
10778 .ds (),
10779
10780 // to register interface (read)
10781 .qs (mio_pad_attr_regwen_7_qs)
10782 );
10783
10784
10785 // Subregister 8 of Multireg mio_pad_attr_regwen
10786 // R[mio_pad_attr_regwen_8]: V(False)
10787 prim_subreg #(
10788 .DW (1),
10789 .SwAccess(prim_subreg_pkg::SwAccessW0C),
10790 .RESVAL (1'h1),
10791 .Mubi (1'b0)
10792 ) u_mio_pad_attr_regwen_8 (
10793 .clk_i (clk_i),
10794 .rst_ni (rst_ni),
10795
10796 // from register interface
10797 .we (mio_pad_attr_regwen_8_we),
10798 .wd (mio_pad_attr_regwen_8_wd),
10799
10800 // from internal hardware
10801 .de (1'b0),
10802 .d ('0),
10803
10804 // to internal hardware
10805 .qe (),
10806 .q (),
10807 .ds (),
10808
10809 // to register interface (read)
10810 .qs (mio_pad_attr_regwen_8_qs)
10811 );
10812
10813
10814 // Subregister 9 of Multireg mio_pad_attr_regwen
10815 // R[mio_pad_attr_regwen_9]: V(False)
10816 prim_subreg #(
10817 .DW (1),
10818 .SwAccess(prim_subreg_pkg::SwAccessW0C),
10819 .RESVAL (1'h1),
10820 .Mubi (1'b0)
10821 ) u_mio_pad_attr_regwen_9 (
10822 .clk_i (clk_i),
10823 .rst_ni (rst_ni),
10824
10825 // from register interface
10826 .we (mio_pad_attr_regwen_9_we),
10827 .wd (mio_pad_attr_regwen_9_wd),
10828
10829 // from internal hardware
10830 .de (1'b0),
10831 .d ('0),
10832
10833 // to internal hardware
10834 .qe (),
10835 .q (),
10836 .ds (),
10837
10838 // to register interface (read)
10839 .qs (mio_pad_attr_regwen_9_qs)
10840 );
10841
10842
10843 // Subregister 10 of Multireg mio_pad_attr_regwen
10844 // R[mio_pad_attr_regwen_10]: V(False)
10845 prim_subreg #(
10846 .DW (1),
10847 .SwAccess(prim_subreg_pkg::SwAccessW0C),
10848 .RESVAL (1'h1),
10849 .Mubi (1'b0)
10850 ) u_mio_pad_attr_regwen_10 (
10851 .clk_i (clk_i),
10852 .rst_ni (rst_ni),
10853
10854 // from register interface
10855 .we (mio_pad_attr_regwen_10_we),
10856 .wd (mio_pad_attr_regwen_10_wd),
10857
10858 // from internal hardware
10859 .de (1'b0),
10860 .d ('0),
10861
10862 // to internal hardware
10863 .qe (),
10864 .q (),
10865 .ds (),
10866
10867 // to register interface (read)
10868 .qs (mio_pad_attr_regwen_10_qs)
10869 );
10870
10871
10872 // Subregister 11 of Multireg mio_pad_attr_regwen
10873 // R[mio_pad_attr_regwen_11]: V(False)
10874 prim_subreg #(
10875 .DW (1),
10876 .SwAccess(prim_subreg_pkg::SwAccessW0C),
10877 .RESVAL (1'h1),
10878 .Mubi (1'b0)
10879 ) u_mio_pad_attr_regwen_11 (
10880 .clk_i (clk_i),
10881 .rst_ni (rst_ni),
10882
10883 // from register interface
10884 .we (mio_pad_attr_regwen_11_we),
10885 .wd (mio_pad_attr_regwen_11_wd),
10886
10887 // from internal hardware
10888 .de (1'b0),
10889 .d ('0),
10890
10891 // to internal hardware
10892 .qe (),
10893 .q (),
10894 .ds (),
10895
10896 // to register interface (read)
10897 .qs (mio_pad_attr_regwen_11_qs)
10898 );
10899
10900
10901 // Subregister 12 of Multireg mio_pad_attr_regwen
10902 // R[mio_pad_attr_regwen_12]: V(False)
10903 prim_subreg #(
10904 .DW (1),
10905 .SwAccess(prim_subreg_pkg::SwAccessW0C),
10906 .RESVAL (1'h1),
10907 .Mubi (1'b0)
10908 ) u_mio_pad_attr_regwen_12 (
10909 .clk_i (clk_i),
10910 .rst_ni (rst_ni),
10911
10912 // from register interface
10913 .we (mio_pad_attr_regwen_12_we),
10914 .wd (mio_pad_attr_regwen_12_wd),
10915
10916 // from internal hardware
10917 .de (1'b0),
10918 .d ('0),
10919
10920 // to internal hardware
10921 .qe (),
10922 .q (),
10923 .ds (),
10924
10925 // to register interface (read)
10926 .qs (mio_pad_attr_regwen_12_qs)
10927 );
10928
10929
10930 // Subregister 13 of Multireg mio_pad_attr_regwen
10931 // R[mio_pad_attr_regwen_13]: V(False)
10932 prim_subreg #(
10933 .DW (1),
10934 .SwAccess(prim_subreg_pkg::SwAccessW0C),
10935 .RESVAL (1'h1),
10936 .Mubi (1'b0)
10937 ) u_mio_pad_attr_regwen_13 (
10938 .clk_i (clk_i),
10939 .rst_ni (rst_ni),
10940
10941 // from register interface
10942 .we (mio_pad_attr_regwen_13_we),
10943 .wd (mio_pad_attr_regwen_13_wd),
10944
10945 // from internal hardware
10946 .de (1'b0),
10947 .d ('0),
10948
10949 // to internal hardware
10950 .qe (),
10951 .q (),
10952 .ds (),
10953
10954 // to register interface (read)
10955 .qs (mio_pad_attr_regwen_13_qs)
10956 );
10957
10958
10959 // Subregister 14 of Multireg mio_pad_attr_regwen
10960 // R[mio_pad_attr_regwen_14]: V(False)
10961 prim_subreg #(
10962 .DW (1),
10963 .SwAccess(prim_subreg_pkg::SwAccessW0C),
10964 .RESVAL (1'h1),
10965 .Mubi (1'b0)
10966 ) u_mio_pad_attr_regwen_14 (
10967 .clk_i (clk_i),
10968 .rst_ni (rst_ni),
10969
10970 // from register interface
10971 .we (mio_pad_attr_regwen_14_we),
10972 .wd (mio_pad_attr_regwen_14_wd),
10973
10974 // from internal hardware
10975 .de (1'b0),
10976 .d ('0),
10977
10978 // to internal hardware
10979 .qe (),
10980 .q (),
10981 .ds (),
10982
10983 // to register interface (read)
10984 .qs (mio_pad_attr_regwen_14_qs)
10985 );
10986
10987
10988 // Subregister 15 of Multireg mio_pad_attr_regwen
10989 // R[mio_pad_attr_regwen_15]: V(False)
10990 prim_subreg #(
10991 .DW (1),
10992 .SwAccess(prim_subreg_pkg::SwAccessW0C),
10993 .RESVAL (1'h1),
10994 .Mubi (1'b0)
10995 ) u_mio_pad_attr_regwen_15 (
10996 .clk_i (clk_i),
10997 .rst_ni (rst_ni),
10998
10999 // from register interface
11000 .we (mio_pad_attr_regwen_15_we),
11001 .wd (mio_pad_attr_regwen_15_wd),
11002
11003 // from internal hardware
11004 .de (1'b0),
11005 .d ('0),
11006
11007 // to internal hardware
11008 .qe (),
11009 .q (),
11010 .ds (),
11011
11012 // to register interface (read)
11013 .qs (mio_pad_attr_regwen_15_qs)
11014 );
11015
11016
11017 // Subregister 16 of Multireg mio_pad_attr_regwen
11018 // R[mio_pad_attr_regwen_16]: V(False)
11019 prim_subreg #(
11020 .DW (1),
11021 .SwAccess(prim_subreg_pkg::SwAccessW0C),
11022 .RESVAL (1'h1),
11023 .Mubi (1'b0)
11024 ) u_mio_pad_attr_regwen_16 (
11025 .clk_i (clk_i),
11026 .rst_ni (rst_ni),
11027
11028 // from register interface
11029 .we (mio_pad_attr_regwen_16_we),
11030 .wd (mio_pad_attr_regwen_16_wd),
11031
11032 // from internal hardware
11033 .de (1'b0),
11034 .d ('0),
11035
11036 // to internal hardware
11037 .qe (),
11038 .q (),
11039 .ds (),
11040
11041 // to register interface (read)
11042 .qs (mio_pad_attr_regwen_16_qs)
11043 );
11044
11045
11046 // Subregister 17 of Multireg mio_pad_attr_regwen
11047 // R[mio_pad_attr_regwen_17]: V(False)
11048 prim_subreg #(
11049 .DW (1),
11050 .SwAccess(prim_subreg_pkg::SwAccessW0C),
11051 .RESVAL (1'h1),
11052 .Mubi (1'b0)
11053 ) u_mio_pad_attr_regwen_17 (
11054 .clk_i (clk_i),
11055 .rst_ni (rst_ni),
11056
11057 // from register interface
11058 .we (mio_pad_attr_regwen_17_we),
11059 .wd (mio_pad_attr_regwen_17_wd),
11060
11061 // from internal hardware
11062 .de (1'b0),
11063 .d ('0),
11064
11065 // to internal hardware
11066 .qe (),
11067 .q (),
11068 .ds (),
11069
11070 // to register interface (read)
11071 .qs (mio_pad_attr_regwen_17_qs)
11072 );
11073
11074
11075 // Subregister 18 of Multireg mio_pad_attr_regwen
11076 // R[mio_pad_attr_regwen_18]: V(False)
11077 prim_subreg #(
11078 .DW (1),
11079 .SwAccess(prim_subreg_pkg::SwAccessW0C),
11080 .RESVAL (1'h1),
11081 .Mubi (1'b0)
11082 ) u_mio_pad_attr_regwen_18 (
11083 .clk_i (clk_i),
11084 .rst_ni (rst_ni),
11085
11086 // from register interface
11087 .we (mio_pad_attr_regwen_18_we),
11088 .wd (mio_pad_attr_regwen_18_wd),
11089
11090 // from internal hardware
11091 .de (1'b0),
11092 .d ('0),
11093
11094 // to internal hardware
11095 .qe (),
11096 .q (),
11097 .ds (),
11098
11099 // to register interface (read)
11100 .qs (mio_pad_attr_regwen_18_qs)
11101 );
11102
11103
11104 // Subregister 19 of Multireg mio_pad_attr_regwen
11105 // R[mio_pad_attr_regwen_19]: V(False)
11106 prim_subreg #(
11107 .DW (1),
11108 .SwAccess(prim_subreg_pkg::SwAccessW0C),
11109 .RESVAL (1'h1),
11110 .Mubi (1'b0)
11111 ) u_mio_pad_attr_regwen_19 (
11112 .clk_i (clk_i),
11113 .rst_ni (rst_ni),
11114
11115 // from register interface
11116 .we (mio_pad_attr_regwen_19_we),
11117 .wd (mio_pad_attr_regwen_19_wd),
11118
11119 // from internal hardware
11120 .de (1'b0),
11121 .d ('0),
11122
11123 // to internal hardware
11124 .qe (),
11125 .q (),
11126 .ds (),
11127
11128 // to register interface (read)
11129 .qs (mio_pad_attr_regwen_19_qs)
11130 );
11131
11132
11133 // Subregister 20 of Multireg mio_pad_attr_regwen
11134 // R[mio_pad_attr_regwen_20]: V(False)
11135 prim_subreg #(
11136 .DW (1),
11137 .SwAccess(prim_subreg_pkg::SwAccessW0C),
11138 .RESVAL (1'h1),
11139 .Mubi (1'b0)
11140 ) u_mio_pad_attr_regwen_20 (
11141 .clk_i (clk_i),
11142 .rst_ni (rst_ni),
11143
11144 // from register interface
11145 .we (mio_pad_attr_regwen_20_we),
11146 .wd (mio_pad_attr_regwen_20_wd),
11147
11148 // from internal hardware
11149 .de (1'b0),
11150 .d ('0),
11151
11152 // to internal hardware
11153 .qe (),
11154 .q (),
11155 .ds (),
11156
11157 // to register interface (read)
11158 .qs (mio_pad_attr_regwen_20_qs)
11159 );
11160
11161
11162 // Subregister 21 of Multireg mio_pad_attr_regwen
11163 // R[mio_pad_attr_regwen_21]: V(False)
11164 prim_subreg #(
11165 .DW (1),
11166 .SwAccess(prim_subreg_pkg::SwAccessW0C),
11167 .RESVAL (1'h1),
11168 .Mubi (1'b0)
11169 ) u_mio_pad_attr_regwen_21 (
11170 .clk_i (clk_i),
11171 .rst_ni (rst_ni),
11172
11173 // from register interface
11174 .we (mio_pad_attr_regwen_21_we),
11175 .wd (mio_pad_attr_regwen_21_wd),
11176
11177 // from internal hardware
11178 .de (1'b0),
11179 .d ('0),
11180
11181 // to internal hardware
11182 .qe (),
11183 .q (),
11184 .ds (),
11185
11186 // to register interface (read)
11187 .qs (mio_pad_attr_regwen_21_qs)
11188 );
11189
11190
11191 // Subregister 22 of Multireg mio_pad_attr_regwen
11192 // R[mio_pad_attr_regwen_22]: V(False)
11193 prim_subreg #(
11194 .DW (1),
11195 .SwAccess(prim_subreg_pkg::SwAccessW0C),
11196 .RESVAL (1'h1),
11197 .Mubi (1'b0)
11198 ) u_mio_pad_attr_regwen_22 (
11199 .clk_i (clk_i),
11200 .rst_ni (rst_ni),
11201
11202 // from register interface
11203 .we (mio_pad_attr_regwen_22_we),
11204 .wd (mio_pad_attr_regwen_22_wd),
11205
11206 // from internal hardware
11207 .de (1'b0),
11208 .d ('0),
11209
11210 // to internal hardware
11211 .qe (),
11212 .q (),
11213 .ds (),
11214
11215 // to register interface (read)
11216 .qs (mio_pad_attr_regwen_22_qs)
11217 );
11218
11219
11220 // Subregister 23 of Multireg mio_pad_attr_regwen
11221 // R[mio_pad_attr_regwen_23]: V(False)
11222 prim_subreg #(
11223 .DW (1),
11224 .SwAccess(prim_subreg_pkg::SwAccessW0C),
11225 .RESVAL (1'h1),
11226 .Mubi (1'b0)
11227 ) u_mio_pad_attr_regwen_23 (
11228 .clk_i (clk_i),
11229 .rst_ni (rst_ni),
11230
11231 // from register interface
11232 .we (mio_pad_attr_regwen_23_we),
11233 .wd (mio_pad_attr_regwen_23_wd),
11234
11235 // from internal hardware
11236 .de (1'b0),
11237 .d ('0),
11238
11239 // to internal hardware
11240 .qe (),
11241 .q (),
11242 .ds (),
11243
11244 // to register interface (read)
11245 .qs (mio_pad_attr_regwen_23_qs)
11246 );
11247
11248
11249 // Subregister 24 of Multireg mio_pad_attr_regwen
11250 // R[mio_pad_attr_regwen_24]: V(False)
11251 prim_subreg #(
11252 .DW (1),
11253 .SwAccess(prim_subreg_pkg::SwAccessW0C),
11254 .RESVAL (1'h1),
11255 .Mubi (1'b0)
11256 ) u_mio_pad_attr_regwen_24 (
11257 .clk_i (clk_i),
11258 .rst_ni (rst_ni),
11259
11260 // from register interface
11261 .we (mio_pad_attr_regwen_24_we),
11262 .wd (mio_pad_attr_regwen_24_wd),
11263
11264 // from internal hardware
11265 .de (1'b0),
11266 .d ('0),
11267
11268 // to internal hardware
11269 .qe (),
11270 .q (),
11271 .ds (),
11272
11273 // to register interface (read)
11274 .qs (mio_pad_attr_regwen_24_qs)
11275 );
11276
11277
11278 // Subregister 25 of Multireg mio_pad_attr_regwen
11279 // R[mio_pad_attr_regwen_25]: V(False)
11280 prim_subreg #(
11281 .DW (1),
11282 .SwAccess(prim_subreg_pkg::SwAccessW0C),
11283 .RESVAL (1'h1),
11284 .Mubi (1'b0)
11285 ) u_mio_pad_attr_regwen_25 (
11286 .clk_i (clk_i),
11287 .rst_ni (rst_ni),
11288
11289 // from register interface
11290 .we (mio_pad_attr_regwen_25_we),
11291 .wd (mio_pad_attr_regwen_25_wd),
11292
11293 // from internal hardware
11294 .de (1'b0),
11295 .d ('0),
11296
11297 // to internal hardware
11298 .qe (),
11299 .q (),
11300 .ds (),
11301
11302 // to register interface (read)
11303 .qs (mio_pad_attr_regwen_25_qs)
11304 );
11305
11306
11307 // Subregister 26 of Multireg mio_pad_attr_regwen
11308 // R[mio_pad_attr_regwen_26]: V(False)
11309 prim_subreg #(
11310 .DW (1),
11311 .SwAccess(prim_subreg_pkg::SwAccessW0C),
11312 .RESVAL (1'h1),
11313 .Mubi (1'b0)
11314 ) u_mio_pad_attr_regwen_26 (
11315 .clk_i (clk_i),
11316 .rst_ni (rst_ni),
11317
11318 // from register interface
11319 .we (mio_pad_attr_regwen_26_we),
11320 .wd (mio_pad_attr_regwen_26_wd),
11321
11322 // from internal hardware
11323 .de (1'b0),
11324 .d ('0),
11325
11326 // to internal hardware
11327 .qe (),
11328 .q (),
11329 .ds (),
11330
11331 // to register interface (read)
11332 .qs (mio_pad_attr_regwen_26_qs)
11333 );
11334
11335
11336 // Subregister 27 of Multireg mio_pad_attr_regwen
11337 // R[mio_pad_attr_regwen_27]: V(False)
11338 prim_subreg #(
11339 .DW (1),
11340 .SwAccess(prim_subreg_pkg::SwAccessW0C),
11341 .RESVAL (1'h1),
11342 .Mubi (1'b0)
11343 ) u_mio_pad_attr_regwen_27 (
11344 .clk_i (clk_i),
11345 .rst_ni (rst_ni),
11346
11347 // from register interface
11348 .we (mio_pad_attr_regwen_27_we),
11349 .wd (mio_pad_attr_regwen_27_wd),
11350
11351 // from internal hardware
11352 .de (1'b0),
11353 .d ('0),
11354
11355 // to internal hardware
11356 .qe (),
11357 .q (),
11358 .ds (),
11359
11360 // to register interface (read)
11361 .qs (mio_pad_attr_regwen_27_qs)
11362 );
11363
11364
11365 // Subregister 28 of Multireg mio_pad_attr_regwen
11366 // R[mio_pad_attr_regwen_28]: V(False)
11367 prim_subreg #(
11368 .DW (1),
11369 .SwAccess(prim_subreg_pkg::SwAccessW0C),
11370 .RESVAL (1'h1),
11371 .Mubi (1'b0)
11372 ) u_mio_pad_attr_regwen_28 (
11373 .clk_i (clk_i),
11374 .rst_ni (rst_ni),
11375
11376 // from register interface
11377 .we (mio_pad_attr_regwen_28_we),
11378 .wd (mio_pad_attr_regwen_28_wd),
11379
11380 // from internal hardware
11381 .de (1'b0),
11382 .d ('0),
11383
11384 // to internal hardware
11385 .qe (),
11386 .q (),
11387 .ds (),
11388
11389 // to register interface (read)
11390 .qs (mio_pad_attr_regwen_28_qs)
11391 );
11392
11393
11394 // Subregister 29 of Multireg mio_pad_attr_regwen
11395 // R[mio_pad_attr_regwen_29]: V(False)
11396 prim_subreg #(
11397 .DW (1),
11398 .SwAccess(prim_subreg_pkg::SwAccessW0C),
11399 .RESVAL (1'h1),
11400 .Mubi (1'b0)
11401 ) u_mio_pad_attr_regwen_29 (
11402 .clk_i (clk_i),
11403 .rst_ni (rst_ni),
11404
11405 // from register interface
11406 .we (mio_pad_attr_regwen_29_we),
11407 .wd (mio_pad_attr_regwen_29_wd),
11408
11409 // from internal hardware
11410 .de (1'b0),
11411 .d ('0),
11412
11413 // to internal hardware
11414 .qe (),
11415 .q (),
11416 .ds (),
11417
11418 // to register interface (read)
11419 .qs (mio_pad_attr_regwen_29_qs)
11420 );
11421
11422
11423 // Subregister 30 of Multireg mio_pad_attr_regwen
11424 // R[mio_pad_attr_regwen_30]: V(False)
11425 prim_subreg #(
11426 .DW (1),
11427 .SwAccess(prim_subreg_pkg::SwAccessW0C),
11428 .RESVAL (1'h1),
11429 .Mubi (1'b0)
11430 ) u_mio_pad_attr_regwen_30 (
11431 .clk_i (clk_i),
11432 .rst_ni (rst_ni),
11433
11434 // from register interface
11435 .we (mio_pad_attr_regwen_30_we),
11436 .wd (mio_pad_attr_regwen_30_wd),
11437
11438 // from internal hardware
11439 .de (1'b0),
11440 .d ('0),
11441
11442 // to internal hardware
11443 .qe (),
11444 .q (),
11445 .ds (),
11446
11447 // to register interface (read)
11448 .qs (mio_pad_attr_regwen_30_qs)
11449 );
11450
11451
11452 // Subregister 31 of Multireg mio_pad_attr_regwen
11453 // R[mio_pad_attr_regwen_31]: V(False)
11454 prim_subreg #(
11455 .DW (1),
11456 .SwAccess(prim_subreg_pkg::SwAccessW0C),
11457 .RESVAL (1'h1),
11458 .Mubi (1'b0)
11459 ) u_mio_pad_attr_regwen_31 (
11460 .clk_i (clk_i),
11461 .rst_ni (rst_ni),
11462
11463 // from register interface
11464 .we (mio_pad_attr_regwen_31_we),
11465 .wd (mio_pad_attr_regwen_31_wd),
11466
11467 // from internal hardware
11468 .de (1'b0),
11469 .d ('0),
11470
11471 // to internal hardware
11472 .qe (),
11473 .q (),
11474 .ds (),
11475
11476 // to register interface (read)
11477 .qs (mio_pad_attr_regwen_31_qs)
11478 );
11479
11480
11481 // Subregister 32 of Multireg mio_pad_attr_regwen
11482 // R[mio_pad_attr_regwen_32]: V(False)
11483 prim_subreg #(
11484 .DW (1),
11485 .SwAccess(prim_subreg_pkg::SwAccessW0C),
11486 .RESVAL (1'h1),
11487 .Mubi (1'b0)
11488 ) u_mio_pad_attr_regwen_32 (
11489 .clk_i (clk_i),
11490 .rst_ni (rst_ni),
11491
11492 // from register interface
11493 .we (mio_pad_attr_regwen_32_we),
11494 .wd (mio_pad_attr_regwen_32_wd),
11495
11496 // from internal hardware
11497 .de (1'b0),
11498 .d ('0),
11499
11500 // to internal hardware
11501 .qe (),
11502 .q (),
11503 .ds (),
11504
11505 // to register interface (read)
11506 .qs (mio_pad_attr_regwen_32_qs)
11507 );
11508
11509
11510 // Subregister 33 of Multireg mio_pad_attr_regwen
11511 // R[mio_pad_attr_regwen_33]: V(False)
11512 prim_subreg #(
11513 .DW (1),
11514 .SwAccess(prim_subreg_pkg::SwAccessW0C),
11515 .RESVAL (1'h1),
11516 .Mubi (1'b0)
11517 ) u_mio_pad_attr_regwen_33 (
11518 .clk_i (clk_i),
11519 .rst_ni (rst_ni),
11520
11521 // from register interface
11522 .we (mio_pad_attr_regwen_33_we),
11523 .wd (mio_pad_attr_regwen_33_wd),
11524
11525 // from internal hardware
11526 .de (1'b0),
11527 .d ('0),
11528
11529 // to internal hardware
11530 .qe (),
11531 .q (),
11532 .ds (),
11533
11534 // to register interface (read)
11535 .qs (mio_pad_attr_regwen_33_qs)
11536 );
11537
11538
11539 // Subregister 34 of Multireg mio_pad_attr_regwen
11540 // R[mio_pad_attr_regwen_34]: V(False)
11541 prim_subreg #(
11542 .DW (1),
11543 .SwAccess(prim_subreg_pkg::SwAccessW0C),
11544 .RESVAL (1'h1),
11545 .Mubi (1'b0)
11546 ) u_mio_pad_attr_regwen_34 (
11547 .clk_i (clk_i),
11548 .rst_ni (rst_ni),
11549
11550 // from register interface
11551 .we (mio_pad_attr_regwen_34_we),
11552 .wd (mio_pad_attr_regwen_34_wd),
11553
11554 // from internal hardware
11555 .de (1'b0),
11556 .d ('0),
11557
11558 // to internal hardware
11559 .qe (),
11560 .q (),
11561 .ds (),
11562
11563 // to register interface (read)
11564 .qs (mio_pad_attr_regwen_34_qs)
11565 );
11566
11567
11568 // Subregister 35 of Multireg mio_pad_attr_regwen
11569 // R[mio_pad_attr_regwen_35]: V(False)
11570 prim_subreg #(
11571 .DW (1),
11572 .SwAccess(prim_subreg_pkg::SwAccessW0C),
11573 .RESVAL (1'h1),
11574 .Mubi (1'b0)
11575 ) u_mio_pad_attr_regwen_35 (
11576 .clk_i (clk_i),
11577 .rst_ni (rst_ni),
11578
11579 // from register interface
11580 .we (mio_pad_attr_regwen_35_we),
11581 .wd (mio_pad_attr_regwen_35_wd),
11582
11583 // from internal hardware
11584 .de (1'b0),
11585 .d ('0),
11586
11587 // to internal hardware
11588 .qe (),
11589 .q (),
11590 .ds (),
11591
11592 // to register interface (read)
11593 .qs (mio_pad_attr_regwen_35_qs)
11594 );
11595
11596
11597 // Subregister 36 of Multireg mio_pad_attr_regwen
11598 // R[mio_pad_attr_regwen_36]: V(False)
11599 prim_subreg #(
11600 .DW (1),
11601 .SwAccess(prim_subreg_pkg::SwAccessW0C),
11602 .RESVAL (1'h1),
11603 .Mubi (1'b0)
11604 ) u_mio_pad_attr_regwen_36 (
11605 .clk_i (clk_i),
11606 .rst_ni (rst_ni),
11607
11608 // from register interface
11609 .we (mio_pad_attr_regwen_36_we),
11610 .wd (mio_pad_attr_regwen_36_wd),
11611
11612 // from internal hardware
11613 .de (1'b0),
11614 .d ('0),
11615
11616 // to internal hardware
11617 .qe (),
11618 .q (),
11619 .ds (),
11620
11621 // to register interface (read)
11622 .qs (mio_pad_attr_regwen_36_qs)
11623 );
11624
11625
11626 // Subregister 37 of Multireg mio_pad_attr_regwen
11627 // R[mio_pad_attr_regwen_37]: V(False)
11628 prim_subreg #(
11629 .DW (1),
11630 .SwAccess(prim_subreg_pkg::SwAccessW0C),
11631 .RESVAL (1'h1),
11632 .Mubi (1'b0)
11633 ) u_mio_pad_attr_regwen_37 (
11634 .clk_i (clk_i),
11635 .rst_ni (rst_ni),
11636
11637 // from register interface
11638 .we (mio_pad_attr_regwen_37_we),
11639 .wd (mio_pad_attr_regwen_37_wd),
11640
11641 // from internal hardware
11642 .de (1'b0),
11643 .d ('0),
11644
11645 // to internal hardware
11646 .qe (),
11647 .q (),
11648 .ds (),
11649
11650 // to register interface (read)
11651 .qs (mio_pad_attr_regwen_37_qs)
11652 );
11653
11654
11655 // Subregister 38 of Multireg mio_pad_attr_regwen
11656 // R[mio_pad_attr_regwen_38]: V(False)
11657 prim_subreg #(
11658 .DW (1),
11659 .SwAccess(prim_subreg_pkg::SwAccessW0C),
11660 .RESVAL (1'h1),
11661 .Mubi (1'b0)
11662 ) u_mio_pad_attr_regwen_38 (
11663 .clk_i (clk_i),
11664 .rst_ni (rst_ni),
11665
11666 // from register interface
11667 .we (mio_pad_attr_regwen_38_we),
11668 .wd (mio_pad_attr_regwen_38_wd),
11669
11670 // from internal hardware
11671 .de (1'b0),
11672 .d ('0),
11673
11674 // to internal hardware
11675 .qe (),
11676 .q (),
11677 .ds (),
11678
11679 // to register interface (read)
11680 .qs (mio_pad_attr_regwen_38_qs)
11681 );
11682
11683
11684 // Subregister 39 of Multireg mio_pad_attr_regwen
11685 // R[mio_pad_attr_regwen_39]: V(False)
11686 prim_subreg #(
11687 .DW (1),
11688 .SwAccess(prim_subreg_pkg::SwAccessW0C),
11689 .RESVAL (1'h1),
11690 .Mubi (1'b0)
11691 ) u_mio_pad_attr_regwen_39 (
11692 .clk_i (clk_i),
11693 .rst_ni (rst_ni),
11694
11695 // from register interface
11696 .we (mio_pad_attr_regwen_39_we),
11697 .wd (mio_pad_attr_regwen_39_wd),
11698
11699 // from internal hardware
11700 .de (1'b0),
11701 .d ('0),
11702
11703 // to internal hardware
11704 .qe (),
11705 .q (),
11706 .ds (),
11707
11708 // to register interface (read)
11709 .qs (mio_pad_attr_regwen_39_qs)
11710 );
11711
11712
11713 // Subregister 40 of Multireg mio_pad_attr_regwen
11714 // R[mio_pad_attr_regwen_40]: V(False)
11715 prim_subreg #(
11716 .DW (1),
11717 .SwAccess(prim_subreg_pkg::SwAccessW0C),
11718 .RESVAL (1'h1),
11719 .Mubi (1'b0)
11720 ) u_mio_pad_attr_regwen_40 (
11721 .clk_i (clk_i),
11722 .rst_ni (rst_ni),
11723
11724 // from register interface
11725 .we (mio_pad_attr_regwen_40_we),
11726 .wd (mio_pad_attr_regwen_40_wd),
11727
11728 // from internal hardware
11729 .de (1'b0),
11730 .d ('0),
11731
11732 // to internal hardware
11733 .qe (),
11734 .q (),
11735 .ds (),
11736
11737 // to register interface (read)
11738 .qs (mio_pad_attr_regwen_40_qs)
11739 );
11740
11741
11742 // Subregister 41 of Multireg mio_pad_attr_regwen
11743 // R[mio_pad_attr_regwen_41]: V(False)
11744 prim_subreg #(
11745 .DW (1),
11746 .SwAccess(prim_subreg_pkg::SwAccessW0C),
11747 .RESVAL (1'h1),
11748 .Mubi (1'b0)
11749 ) u_mio_pad_attr_regwen_41 (
11750 .clk_i (clk_i),
11751 .rst_ni (rst_ni),
11752
11753 // from register interface
11754 .we (mio_pad_attr_regwen_41_we),
11755 .wd (mio_pad_attr_regwen_41_wd),
11756
11757 // from internal hardware
11758 .de (1'b0),
11759 .d ('0),
11760
11761 // to internal hardware
11762 .qe (),
11763 .q (),
11764 .ds (),
11765
11766 // to register interface (read)
11767 .qs (mio_pad_attr_regwen_41_qs)
11768 );
11769
11770
11771 // Subregister 42 of Multireg mio_pad_attr_regwen
11772 // R[mio_pad_attr_regwen_42]: V(False)
11773 prim_subreg #(
11774 .DW (1),
11775 .SwAccess(prim_subreg_pkg::SwAccessW0C),
11776 .RESVAL (1'h1),
11777 .Mubi (1'b0)
11778 ) u_mio_pad_attr_regwen_42 (
11779 .clk_i (clk_i),
11780 .rst_ni (rst_ni),
11781
11782 // from register interface
11783 .we (mio_pad_attr_regwen_42_we),
11784 .wd (mio_pad_attr_regwen_42_wd),
11785
11786 // from internal hardware
11787 .de (1'b0),
11788 .d ('0),
11789
11790 // to internal hardware
11791 .qe (),
11792 .q (),
11793 .ds (),
11794
11795 // to register interface (read)
11796 .qs (mio_pad_attr_regwen_42_qs)
11797 );
11798
11799
11800 // Subregister 43 of Multireg mio_pad_attr_regwen
11801 // R[mio_pad_attr_regwen_43]: V(False)
11802 prim_subreg #(
11803 .DW (1),
11804 .SwAccess(prim_subreg_pkg::SwAccessW0C),
11805 .RESVAL (1'h1),
11806 .Mubi (1'b0)
11807 ) u_mio_pad_attr_regwen_43 (
11808 .clk_i (clk_i),
11809 .rst_ni (rst_ni),
11810
11811 // from register interface
11812 .we (mio_pad_attr_regwen_43_we),
11813 .wd (mio_pad_attr_regwen_43_wd),
11814
11815 // from internal hardware
11816 .de (1'b0),
11817 .d ('0),
11818
11819 // to internal hardware
11820 .qe (),
11821 .q (),
11822 .ds (),
11823
11824 // to register interface (read)
11825 .qs (mio_pad_attr_regwen_43_qs)
11826 );
11827
11828
11829 // Subregister 44 of Multireg mio_pad_attr_regwen
11830 // R[mio_pad_attr_regwen_44]: V(False)
11831 prim_subreg #(
11832 .DW (1),
11833 .SwAccess(prim_subreg_pkg::SwAccessW0C),
11834 .RESVAL (1'h1),
11835 .Mubi (1'b0)
11836 ) u_mio_pad_attr_regwen_44 (
11837 .clk_i (clk_i),
11838 .rst_ni (rst_ni),
11839
11840 // from register interface
11841 .we (mio_pad_attr_regwen_44_we),
11842 .wd (mio_pad_attr_regwen_44_wd),
11843
11844 // from internal hardware
11845 .de (1'b0),
11846 .d ('0),
11847
11848 // to internal hardware
11849 .qe (),
11850 .q (),
11851 .ds (),
11852
11853 // to register interface (read)
11854 .qs (mio_pad_attr_regwen_44_qs)
11855 );
11856
11857
11858 // Subregister 45 of Multireg mio_pad_attr_regwen
11859 // R[mio_pad_attr_regwen_45]: V(False)
11860 prim_subreg #(
11861 .DW (1),
11862 .SwAccess(prim_subreg_pkg::SwAccessW0C),
11863 .RESVAL (1'h1),
11864 .Mubi (1'b0)
11865 ) u_mio_pad_attr_regwen_45 (
11866 .clk_i (clk_i),
11867 .rst_ni (rst_ni),
11868
11869 // from register interface
11870 .we (mio_pad_attr_regwen_45_we),
11871 .wd (mio_pad_attr_regwen_45_wd),
11872
11873 // from internal hardware
11874 .de (1'b0),
11875 .d ('0),
11876
11877 // to internal hardware
11878 .qe (),
11879 .q (),
11880 .ds (),
11881
11882 // to register interface (read)
11883 .qs (mio_pad_attr_regwen_45_qs)
11884 );
11885
11886
11887 // Subregister 46 of Multireg mio_pad_attr_regwen
11888 // R[mio_pad_attr_regwen_46]: V(False)
11889 prim_subreg #(
11890 .DW (1),
11891 .SwAccess(prim_subreg_pkg::SwAccessW0C),
11892 .RESVAL (1'h1),
11893 .Mubi (1'b0)
11894 ) u_mio_pad_attr_regwen_46 (
11895 .clk_i (clk_i),
11896 .rst_ni (rst_ni),
11897
11898 // from register interface
11899 .we (mio_pad_attr_regwen_46_we),
11900 .wd (mio_pad_attr_regwen_46_wd),
11901
11902 // from internal hardware
11903 .de (1'b0),
11904 .d ('0),
11905
11906 // to internal hardware
11907 .qe (),
11908 .q (),
11909 .ds (),
11910
11911 // to register interface (read)
11912 .qs (mio_pad_attr_regwen_46_qs)
11913 );
11914
11915
11916 // Subregister 0 of Multireg mio_pad_attr
11917 // R[mio_pad_attr_0]: V(True)
11918 logic mio_pad_attr_0_qe;
11919 logic [9:0] mio_pad_attr_0_flds_we;
11920 1/1 assign mio_pad_attr_0_qe = &mio_pad_attr_0_flds_we;
Tests: T96 T97 T98
11921 // Create REGWEN-gated WE signal
11922 logic mio_pad_attr_0_gated_we;
11923 1/1 assign mio_pad_attr_0_gated_we = mio_pad_attr_0_we & mio_pad_attr_regwen_0_qs;
Tests: T71 T96 T97
11924 // F[invert_0]: 0:0
11925 prim_subreg_ext #(
11926 .DW (1)
11927 ) u_mio_pad_attr_0_invert_0 (
11928 .re (mio_pad_attr_0_re),
11929 .we (mio_pad_attr_0_gated_we),
11930 .wd (mio_pad_attr_0_invert_0_wd),
11931 .d (hw2reg.mio_pad_attr[0].invert.d),
11932 .qre (),
11933 .qe (mio_pad_attr_0_flds_we[0]),
11934 .q (reg2hw.mio_pad_attr[0].invert.q),
11935 .ds (),
11936 .qs (mio_pad_attr_0_invert_0_qs)
11937 );
11938 1/1 assign reg2hw.mio_pad_attr[0].invert.qe = mio_pad_attr_0_qe;
Tests: T96 T97 T98
11939
11940 // F[virtual_od_en_0]: 1:1
11941 prim_subreg_ext #(
11942 .DW (1)
11943 ) u_mio_pad_attr_0_virtual_od_en_0 (
11944 .re (mio_pad_attr_0_re),
11945 .we (mio_pad_attr_0_gated_we),
11946 .wd (mio_pad_attr_0_virtual_od_en_0_wd),
11947 .d (hw2reg.mio_pad_attr[0].virtual_od_en.d),
11948 .qre (),
11949 .qe (mio_pad_attr_0_flds_we[1]),
11950 .q (reg2hw.mio_pad_attr[0].virtual_od_en.q),
11951 .ds (),
11952 .qs (mio_pad_attr_0_virtual_od_en_0_qs)
11953 );
11954 1/1 assign reg2hw.mio_pad_attr[0].virtual_od_en.qe = mio_pad_attr_0_qe;
Tests: T96 T97 T98
11955
11956 // F[pull_en_0]: 2:2
11957 prim_subreg_ext #(
11958 .DW (1)
11959 ) u_mio_pad_attr_0_pull_en_0 (
11960 .re (mio_pad_attr_0_re),
11961 .we (mio_pad_attr_0_gated_we),
11962 .wd (mio_pad_attr_0_pull_en_0_wd),
11963 .d (hw2reg.mio_pad_attr[0].pull_en.d),
11964 .qre (),
11965 .qe (mio_pad_attr_0_flds_we[2]),
11966 .q (reg2hw.mio_pad_attr[0].pull_en.q),
11967 .ds (),
11968 .qs (mio_pad_attr_0_pull_en_0_qs)
11969 );
11970 1/1 assign reg2hw.mio_pad_attr[0].pull_en.qe = mio_pad_attr_0_qe;
Tests: T96 T97 T98
11971
11972 // F[pull_select_0]: 3:3
11973 prim_subreg_ext #(
11974 .DW (1)
11975 ) u_mio_pad_attr_0_pull_select_0 (
11976 .re (mio_pad_attr_0_re),
11977 .we (mio_pad_attr_0_gated_we),
11978 .wd (mio_pad_attr_0_pull_select_0_wd),
11979 .d (hw2reg.mio_pad_attr[0].pull_select.d),
11980 .qre (),
11981 .qe (mio_pad_attr_0_flds_we[3]),
11982 .q (reg2hw.mio_pad_attr[0].pull_select.q),
11983 .ds (),
11984 .qs (mio_pad_attr_0_pull_select_0_qs)
11985 );
11986 1/1 assign reg2hw.mio_pad_attr[0].pull_select.qe = mio_pad_attr_0_qe;
Tests: T96 T97 T98
11987
11988 // F[keeper_en_0]: 4:4
11989 prim_subreg_ext #(
11990 .DW (1)
11991 ) u_mio_pad_attr_0_keeper_en_0 (
11992 .re (mio_pad_attr_0_re),
11993 .we (mio_pad_attr_0_gated_we),
11994 .wd (mio_pad_attr_0_keeper_en_0_wd),
11995 .d (hw2reg.mio_pad_attr[0].keeper_en.d),
11996 .qre (),
11997 .qe (mio_pad_attr_0_flds_we[4]),
11998 .q (reg2hw.mio_pad_attr[0].keeper_en.q),
11999 .ds (),
12000 .qs (mio_pad_attr_0_keeper_en_0_qs)
12001 );
12002 1/1 assign reg2hw.mio_pad_attr[0].keeper_en.qe = mio_pad_attr_0_qe;
Tests: T96 T97 T98
12003
12004 // F[schmitt_en_0]: 5:5
12005 prim_subreg_ext #(
12006 .DW (1)
12007 ) u_mio_pad_attr_0_schmitt_en_0 (
12008 .re (mio_pad_attr_0_re),
12009 .we (mio_pad_attr_0_gated_we),
12010 .wd (mio_pad_attr_0_schmitt_en_0_wd),
12011 .d (hw2reg.mio_pad_attr[0].schmitt_en.d),
12012 .qre (),
12013 .qe (mio_pad_attr_0_flds_we[5]),
12014 .q (reg2hw.mio_pad_attr[0].schmitt_en.q),
12015 .ds (),
12016 .qs (mio_pad_attr_0_schmitt_en_0_qs)
12017 );
12018 1/1 assign reg2hw.mio_pad_attr[0].schmitt_en.qe = mio_pad_attr_0_qe;
Tests: T96 T97 T98
12019
12020 // F[od_en_0]: 6:6
12021 prim_subreg_ext #(
12022 .DW (1)
12023 ) u_mio_pad_attr_0_od_en_0 (
12024 .re (mio_pad_attr_0_re),
12025 .we (mio_pad_attr_0_gated_we),
12026 .wd (mio_pad_attr_0_od_en_0_wd),
12027 .d (hw2reg.mio_pad_attr[0].od_en.d),
12028 .qre (),
12029 .qe (mio_pad_attr_0_flds_we[6]),
12030 .q (reg2hw.mio_pad_attr[0].od_en.q),
12031 .ds (),
12032 .qs (mio_pad_attr_0_od_en_0_qs)
12033 );
12034 1/1 assign reg2hw.mio_pad_attr[0].od_en.qe = mio_pad_attr_0_qe;
Tests: T96 T97 T98
12035
12036 // F[input_disable_0]: 7:7
12037 prim_subreg_ext #(
12038 .DW (1)
12039 ) u_mio_pad_attr_0_input_disable_0 (
12040 .re (mio_pad_attr_0_re),
12041 .we (mio_pad_attr_0_gated_we),
12042 .wd (mio_pad_attr_0_input_disable_0_wd),
12043 .d (hw2reg.mio_pad_attr[0].input_disable.d),
12044 .qre (),
12045 .qe (mio_pad_attr_0_flds_we[7]),
12046 .q (reg2hw.mio_pad_attr[0].input_disable.q),
12047 .ds (),
12048 .qs (mio_pad_attr_0_input_disable_0_qs)
12049 );
12050 1/1 assign reg2hw.mio_pad_attr[0].input_disable.qe = mio_pad_attr_0_qe;
Tests: T96 T97 T98
12051
12052 // F[slew_rate_0]: 17:16
12053 prim_subreg_ext #(
12054 .DW (2)
12055 ) u_mio_pad_attr_0_slew_rate_0 (
12056 .re (mio_pad_attr_0_re),
12057 .we (mio_pad_attr_0_gated_we),
12058 .wd (mio_pad_attr_0_slew_rate_0_wd),
12059 .d (hw2reg.mio_pad_attr[0].slew_rate.d),
12060 .qre (),
12061 .qe (mio_pad_attr_0_flds_we[8]),
12062 .q (reg2hw.mio_pad_attr[0].slew_rate.q),
12063 .ds (),
12064 .qs (mio_pad_attr_0_slew_rate_0_qs)
12065 );
12066 1/1 assign reg2hw.mio_pad_attr[0].slew_rate.qe = mio_pad_attr_0_qe;
Tests: T96 T97 T98
12067
12068 // F[drive_strength_0]: 23:20
12069 prim_subreg_ext #(
12070 .DW (4)
12071 ) u_mio_pad_attr_0_drive_strength_0 (
12072 .re (mio_pad_attr_0_re),
12073 .we (mio_pad_attr_0_gated_we),
12074 .wd (mio_pad_attr_0_drive_strength_0_wd),
12075 .d (hw2reg.mio_pad_attr[0].drive_strength.d),
12076 .qre (),
12077 .qe (mio_pad_attr_0_flds_we[9]),
12078 .q (reg2hw.mio_pad_attr[0].drive_strength.q),
12079 .ds (),
12080 .qs (mio_pad_attr_0_drive_strength_0_qs)
12081 );
12082 1/1 assign reg2hw.mio_pad_attr[0].drive_strength.qe = mio_pad_attr_0_qe;
Tests: T96 T97 T98
12083
12084
12085 // Subregister 1 of Multireg mio_pad_attr
12086 // R[mio_pad_attr_1]: V(True)
12087 logic mio_pad_attr_1_qe;
12088 logic [9:0] mio_pad_attr_1_flds_we;
12089 1/1 assign mio_pad_attr_1_qe = &mio_pad_attr_1_flds_we;
Tests: T96 T97 T98
12090 // Create REGWEN-gated WE signal
12091 logic mio_pad_attr_1_gated_we;
12092 1/1 assign mio_pad_attr_1_gated_we = mio_pad_attr_1_we & mio_pad_attr_regwen_1_qs;
Tests: T71 T96 T97
12093 // F[invert_1]: 0:0
12094 prim_subreg_ext #(
12095 .DW (1)
12096 ) u_mio_pad_attr_1_invert_1 (
12097 .re (mio_pad_attr_1_re),
12098 .we (mio_pad_attr_1_gated_we),
12099 .wd (mio_pad_attr_1_invert_1_wd),
12100 .d (hw2reg.mio_pad_attr[1].invert.d),
12101 .qre (),
12102 .qe (mio_pad_attr_1_flds_we[0]),
12103 .q (reg2hw.mio_pad_attr[1].invert.q),
12104 .ds (),
12105 .qs (mio_pad_attr_1_invert_1_qs)
12106 );
12107 1/1 assign reg2hw.mio_pad_attr[1].invert.qe = mio_pad_attr_1_qe;
Tests: T96 T97 T98
12108
12109 // F[virtual_od_en_1]: 1:1
12110 prim_subreg_ext #(
12111 .DW (1)
12112 ) u_mio_pad_attr_1_virtual_od_en_1 (
12113 .re (mio_pad_attr_1_re),
12114 .we (mio_pad_attr_1_gated_we),
12115 .wd (mio_pad_attr_1_virtual_od_en_1_wd),
12116 .d (hw2reg.mio_pad_attr[1].virtual_od_en.d),
12117 .qre (),
12118 .qe (mio_pad_attr_1_flds_we[1]),
12119 .q (reg2hw.mio_pad_attr[1].virtual_od_en.q),
12120 .ds (),
12121 .qs (mio_pad_attr_1_virtual_od_en_1_qs)
12122 );
12123 1/1 assign reg2hw.mio_pad_attr[1].virtual_od_en.qe = mio_pad_attr_1_qe;
Tests: T96 T97 T98
12124
12125 // F[pull_en_1]: 2:2
12126 prim_subreg_ext #(
12127 .DW (1)
12128 ) u_mio_pad_attr_1_pull_en_1 (
12129 .re (mio_pad_attr_1_re),
12130 .we (mio_pad_attr_1_gated_we),
12131 .wd (mio_pad_attr_1_pull_en_1_wd),
12132 .d (hw2reg.mio_pad_attr[1].pull_en.d),
12133 .qre (),
12134 .qe (mio_pad_attr_1_flds_we[2]),
12135 .q (reg2hw.mio_pad_attr[1].pull_en.q),
12136 .ds (),
12137 .qs (mio_pad_attr_1_pull_en_1_qs)
12138 );
12139 1/1 assign reg2hw.mio_pad_attr[1].pull_en.qe = mio_pad_attr_1_qe;
Tests: T96 T97 T98
12140
12141 // F[pull_select_1]: 3:3
12142 prim_subreg_ext #(
12143 .DW (1)
12144 ) u_mio_pad_attr_1_pull_select_1 (
12145 .re (mio_pad_attr_1_re),
12146 .we (mio_pad_attr_1_gated_we),
12147 .wd (mio_pad_attr_1_pull_select_1_wd),
12148 .d (hw2reg.mio_pad_attr[1].pull_select.d),
12149 .qre (),
12150 .qe (mio_pad_attr_1_flds_we[3]),
12151 .q (reg2hw.mio_pad_attr[1].pull_select.q),
12152 .ds (),
12153 .qs (mio_pad_attr_1_pull_select_1_qs)
12154 );
12155 1/1 assign reg2hw.mio_pad_attr[1].pull_select.qe = mio_pad_attr_1_qe;
Tests: T96 T97 T98
12156
12157 // F[keeper_en_1]: 4:4
12158 prim_subreg_ext #(
12159 .DW (1)
12160 ) u_mio_pad_attr_1_keeper_en_1 (
12161 .re (mio_pad_attr_1_re),
12162 .we (mio_pad_attr_1_gated_we),
12163 .wd (mio_pad_attr_1_keeper_en_1_wd),
12164 .d (hw2reg.mio_pad_attr[1].keeper_en.d),
12165 .qre (),
12166 .qe (mio_pad_attr_1_flds_we[4]),
12167 .q (reg2hw.mio_pad_attr[1].keeper_en.q),
12168 .ds (),
12169 .qs (mio_pad_attr_1_keeper_en_1_qs)
12170 );
12171 1/1 assign reg2hw.mio_pad_attr[1].keeper_en.qe = mio_pad_attr_1_qe;
Tests: T96 T97 T98
12172
12173 // F[schmitt_en_1]: 5:5
12174 prim_subreg_ext #(
12175 .DW (1)
12176 ) u_mio_pad_attr_1_schmitt_en_1 (
12177 .re (mio_pad_attr_1_re),
12178 .we (mio_pad_attr_1_gated_we),
12179 .wd (mio_pad_attr_1_schmitt_en_1_wd),
12180 .d (hw2reg.mio_pad_attr[1].schmitt_en.d),
12181 .qre (),
12182 .qe (mio_pad_attr_1_flds_we[5]),
12183 .q (reg2hw.mio_pad_attr[1].schmitt_en.q),
12184 .ds (),
12185 .qs (mio_pad_attr_1_schmitt_en_1_qs)
12186 );
12187 1/1 assign reg2hw.mio_pad_attr[1].schmitt_en.qe = mio_pad_attr_1_qe;
Tests: T96 T97 T98
12188
12189 // F[od_en_1]: 6:6
12190 prim_subreg_ext #(
12191 .DW (1)
12192 ) u_mio_pad_attr_1_od_en_1 (
12193 .re (mio_pad_attr_1_re),
12194 .we (mio_pad_attr_1_gated_we),
12195 .wd (mio_pad_attr_1_od_en_1_wd),
12196 .d (hw2reg.mio_pad_attr[1].od_en.d),
12197 .qre (),
12198 .qe (mio_pad_attr_1_flds_we[6]),
12199 .q (reg2hw.mio_pad_attr[1].od_en.q),
12200 .ds (),
12201 .qs (mio_pad_attr_1_od_en_1_qs)
12202 );
12203 1/1 assign reg2hw.mio_pad_attr[1].od_en.qe = mio_pad_attr_1_qe;
Tests: T96 T97 T98
12204
12205 // F[input_disable_1]: 7:7
12206 prim_subreg_ext #(
12207 .DW (1)
12208 ) u_mio_pad_attr_1_input_disable_1 (
12209 .re (mio_pad_attr_1_re),
12210 .we (mio_pad_attr_1_gated_we),
12211 .wd (mio_pad_attr_1_input_disable_1_wd),
12212 .d (hw2reg.mio_pad_attr[1].input_disable.d),
12213 .qre (),
12214 .qe (mio_pad_attr_1_flds_we[7]),
12215 .q (reg2hw.mio_pad_attr[1].input_disable.q),
12216 .ds (),
12217 .qs (mio_pad_attr_1_input_disable_1_qs)
12218 );
12219 1/1 assign reg2hw.mio_pad_attr[1].input_disable.qe = mio_pad_attr_1_qe;
Tests: T96 T97 T98
12220
12221 // F[slew_rate_1]: 17:16
12222 prim_subreg_ext #(
12223 .DW (2)
12224 ) u_mio_pad_attr_1_slew_rate_1 (
12225 .re (mio_pad_attr_1_re),
12226 .we (mio_pad_attr_1_gated_we),
12227 .wd (mio_pad_attr_1_slew_rate_1_wd),
12228 .d (hw2reg.mio_pad_attr[1].slew_rate.d),
12229 .qre (),
12230 .qe (mio_pad_attr_1_flds_we[8]),
12231 .q (reg2hw.mio_pad_attr[1].slew_rate.q),
12232 .ds (),
12233 .qs (mio_pad_attr_1_slew_rate_1_qs)
12234 );
12235 1/1 assign reg2hw.mio_pad_attr[1].slew_rate.qe = mio_pad_attr_1_qe;
Tests: T96 T97 T98
12236
12237 // F[drive_strength_1]: 23:20
12238 prim_subreg_ext #(
12239 .DW (4)
12240 ) u_mio_pad_attr_1_drive_strength_1 (
12241 .re (mio_pad_attr_1_re),
12242 .we (mio_pad_attr_1_gated_we),
12243 .wd (mio_pad_attr_1_drive_strength_1_wd),
12244 .d (hw2reg.mio_pad_attr[1].drive_strength.d),
12245 .qre (),
12246 .qe (mio_pad_attr_1_flds_we[9]),
12247 .q (reg2hw.mio_pad_attr[1].drive_strength.q),
12248 .ds (),
12249 .qs (mio_pad_attr_1_drive_strength_1_qs)
12250 );
12251 1/1 assign reg2hw.mio_pad_attr[1].drive_strength.qe = mio_pad_attr_1_qe;
Tests: T96 T97 T98
12252
12253
12254 // Subregister 2 of Multireg mio_pad_attr
12255 // R[mio_pad_attr_2]: V(True)
12256 logic mio_pad_attr_2_qe;
12257 logic [9:0] mio_pad_attr_2_flds_we;
12258 1/1 assign mio_pad_attr_2_qe = &mio_pad_attr_2_flds_we;
Tests: T9 T47 T48
12259 // Create REGWEN-gated WE signal
12260 logic mio_pad_attr_2_gated_we;
12261 1/1 assign mio_pad_attr_2_gated_we = mio_pad_attr_2_we & mio_pad_attr_regwen_2_qs;
Tests: T9 T47 T48
12262 // F[invert_2]: 0:0
12263 prim_subreg_ext #(
12264 .DW (1)
12265 ) u_mio_pad_attr_2_invert_2 (
12266 .re (mio_pad_attr_2_re),
12267 .we (mio_pad_attr_2_gated_we),
12268 .wd (mio_pad_attr_2_invert_2_wd),
12269 .d (hw2reg.mio_pad_attr[2].invert.d),
12270 .qre (),
12271 .qe (mio_pad_attr_2_flds_we[0]),
12272 .q (reg2hw.mio_pad_attr[2].invert.q),
12273 .ds (),
12274 .qs (mio_pad_attr_2_invert_2_qs)
12275 );
12276 1/1 assign reg2hw.mio_pad_attr[2].invert.qe = mio_pad_attr_2_qe;
Tests: T9 T47 T48
12277
12278 // F[virtual_od_en_2]: 1:1
12279 prim_subreg_ext #(
12280 .DW (1)
12281 ) u_mio_pad_attr_2_virtual_od_en_2 (
12282 .re (mio_pad_attr_2_re),
12283 .we (mio_pad_attr_2_gated_we),
12284 .wd (mio_pad_attr_2_virtual_od_en_2_wd),
12285 .d (hw2reg.mio_pad_attr[2].virtual_od_en.d),
12286 .qre (),
12287 .qe (mio_pad_attr_2_flds_we[1]),
12288 .q (reg2hw.mio_pad_attr[2].virtual_od_en.q),
12289 .ds (),
12290 .qs (mio_pad_attr_2_virtual_od_en_2_qs)
12291 );
12292 1/1 assign reg2hw.mio_pad_attr[2].virtual_od_en.qe = mio_pad_attr_2_qe;
Tests: T9 T47 T48
12293
12294 // F[pull_en_2]: 2:2
12295 prim_subreg_ext #(
12296 .DW (1)
12297 ) u_mio_pad_attr_2_pull_en_2 (
12298 .re (mio_pad_attr_2_re),
12299 .we (mio_pad_attr_2_gated_we),
12300 .wd (mio_pad_attr_2_pull_en_2_wd),
12301 .d (hw2reg.mio_pad_attr[2].pull_en.d),
12302 .qre (),
12303 .qe (mio_pad_attr_2_flds_we[2]),
12304 .q (reg2hw.mio_pad_attr[2].pull_en.q),
12305 .ds (),
12306 .qs (mio_pad_attr_2_pull_en_2_qs)
12307 );
12308 1/1 assign reg2hw.mio_pad_attr[2].pull_en.qe = mio_pad_attr_2_qe;
Tests: T9 T47 T48
12309
12310 // F[pull_select_2]: 3:3
12311 prim_subreg_ext #(
12312 .DW (1)
12313 ) u_mio_pad_attr_2_pull_select_2 (
12314 .re (mio_pad_attr_2_re),
12315 .we (mio_pad_attr_2_gated_we),
12316 .wd (mio_pad_attr_2_pull_select_2_wd),
12317 .d (hw2reg.mio_pad_attr[2].pull_select.d),
12318 .qre (),
12319 .qe (mio_pad_attr_2_flds_we[3]),
12320 .q (reg2hw.mio_pad_attr[2].pull_select.q),
12321 .ds (),
12322 .qs (mio_pad_attr_2_pull_select_2_qs)
12323 );
12324 1/1 assign reg2hw.mio_pad_attr[2].pull_select.qe = mio_pad_attr_2_qe;
Tests: T9 T47 T48
12325
12326 // F[keeper_en_2]: 4:4
12327 prim_subreg_ext #(
12328 .DW (1)
12329 ) u_mio_pad_attr_2_keeper_en_2 (
12330 .re (mio_pad_attr_2_re),
12331 .we (mio_pad_attr_2_gated_we),
12332 .wd (mio_pad_attr_2_keeper_en_2_wd),
12333 .d (hw2reg.mio_pad_attr[2].keeper_en.d),
12334 .qre (),
12335 .qe (mio_pad_attr_2_flds_we[4]),
12336 .q (reg2hw.mio_pad_attr[2].keeper_en.q),
12337 .ds (),
12338 .qs (mio_pad_attr_2_keeper_en_2_qs)
12339 );
12340 1/1 assign reg2hw.mio_pad_attr[2].keeper_en.qe = mio_pad_attr_2_qe;
Tests: T9 T47 T48
12341
12342 // F[schmitt_en_2]: 5:5
12343 prim_subreg_ext #(
12344 .DW (1)
12345 ) u_mio_pad_attr_2_schmitt_en_2 (
12346 .re (mio_pad_attr_2_re),
12347 .we (mio_pad_attr_2_gated_we),
12348 .wd (mio_pad_attr_2_schmitt_en_2_wd),
12349 .d (hw2reg.mio_pad_attr[2].schmitt_en.d),
12350 .qre (),
12351 .qe (mio_pad_attr_2_flds_we[5]),
12352 .q (reg2hw.mio_pad_attr[2].schmitt_en.q),
12353 .ds (),
12354 .qs (mio_pad_attr_2_schmitt_en_2_qs)
12355 );
12356 1/1 assign reg2hw.mio_pad_attr[2].schmitt_en.qe = mio_pad_attr_2_qe;
Tests: T9 T47 T48
12357
12358 // F[od_en_2]: 6:6
12359 prim_subreg_ext #(
12360 .DW (1)
12361 ) u_mio_pad_attr_2_od_en_2 (
12362 .re (mio_pad_attr_2_re),
12363 .we (mio_pad_attr_2_gated_we),
12364 .wd (mio_pad_attr_2_od_en_2_wd),
12365 .d (hw2reg.mio_pad_attr[2].od_en.d),
12366 .qre (),
12367 .qe (mio_pad_attr_2_flds_we[6]),
12368 .q (reg2hw.mio_pad_attr[2].od_en.q),
12369 .ds (),
12370 .qs (mio_pad_attr_2_od_en_2_qs)
12371 );
12372 1/1 assign reg2hw.mio_pad_attr[2].od_en.qe = mio_pad_attr_2_qe;
Tests: T9 T47 T48
12373
12374 // F[input_disable_2]: 7:7
12375 prim_subreg_ext #(
12376 .DW (1)
12377 ) u_mio_pad_attr_2_input_disable_2 (
12378 .re (mio_pad_attr_2_re),
12379 .we (mio_pad_attr_2_gated_we),
12380 .wd (mio_pad_attr_2_input_disable_2_wd),
12381 .d (hw2reg.mio_pad_attr[2].input_disable.d),
12382 .qre (),
12383 .qe (mio_pad_attr_2_flds_we[7]),
12384 .q (reg2hw.mio_pad_attr[2].input_disable.q),
12385 .ds (),
12386 .qs (mio_pad_attr_2_input_disable_2_qs)
12387 );
12388 1/1 assign reg2hw.mio_pad_attr[2].input_disable.qe = mio_pad_attr_2_qe;
Tests: T9 T47 T48
12389
12390 // F[slew_rate_2]: 17:16
12391 prim_subreg_ext #(
12392 .DW (2)
12393 ) u_mio_pad_attr_2_slew_rate_2 (
12394 .re (mio_pad_attr_2_re),
12395 .we (mio_pad_attr_2_gated_we),
12396 .wd (mio_pad_attr_2_slew_rate_2_wd),
12397 .d (hw2reg.mio_pad_attr[2].slew_rate.d),
12398 .qre (),
12399 .qe (mio_pad_attr_2_flds_we[8]),
12400 .q (reg2hw.mio_pad_attr[2].slew_rate.q),
12401 .ds (),
12402 .qs (mio_pad_attr_2_slew_rate_2_qs)
12403 );
12404 1/1 assign reg2hw.mio_pad_attr[2].slew_rate.qe = mio_pad_attr_2_qe;
Tests: T9 T47 T48
12405
12406 // F[drive_strength_2]: 23:20
12407 prim_subreg_ext #(
12408 .DW (4)
12409 ) u_mio_pad_attr_2_drive_strength_2 (
12410 .re (mio_pad_attr_2_re),
12411 .we (mio_pad_attr_2_gated_we),
12412 .wd (mio_pad_attr_2_drive_strength_2_wd),
12413 .d (hw2reg.mio_pad_attr[2].drive_strength.d),
12414 .qre (),
12415 .qe (mio_pad_attr_2_flds_we[9]),
12416 .q (reg2hw.mio_pad_attr[2].drive_strength.q),
12417 .ds (),
12418 .qs (mio_pad_attr_2_drive_strength_2_qs)
12419 );
12420 1/1 assign reg2hw.mio_pad_attr[2].drive_strength.qe = mio_pad_attr_2_qe;
Tests: T9 T47 T48
12421
12422
12423 // Subregister 3 of Multireg mio_pad_attr
12424 // R[mio_pad_attr_3]: V(True)
12425 logic mio_pad_attr_3_qe;
12426 logic [9:0] mio_pad_attr_3_flds_we;
12427 1/1 assign mio_pad_attr_3_qe = &mio_pad_attr_3_flds_we;
Tests: T96 T97 T98
12428 // Create REGWEN-gated WE signal
12429 logic mio_pad_attr_3_gated_we;
12430 1/1 assign mio_pad_attr_3_gated_we = mio_pad_attr_3_we & mio_pad_attr_regwen_3_qs;
Tests: T71 T96 T97
12431 // F[invert_3]: 0:0
12432 prim_subreg_ext #(
12433 .DW (1)
12434 ) u_mio_pad_attr_3_invert_3 (
12435 .re (mio_pad_attr_3_re),
12436 .we (mio_pad_attr_3_gated_we),
12437 .wd (mio_pad_attr_3_invert_3_wd),
12438 .d (hw2reg.mio_pad_attr[3].invert.d),
12439 .qre (),
12440 .qe (mio_pad_attr_3_flds_we[0]),
12441 .q (reg2hw.mio_pad_attr[3].invert.q),
12442 .ds (),
12443 .qs (mio_pad_attr_3_invert_3_qs)
12444 );
12445 1/1 assign reg2hw.mio_pad_attr[3].invert.qe = mio_pad_attr_3_qe;
Tests: T96 T97 T98
12446
12447 // F[virtual_od_en_3]: 1:1
12448 prim_subreg_ext #(
12449 .DW (1)
12450 ) u_mio_pad_attr_3_virtual_od_en_3 (
12451 .re (mio_pad_attr_3_re),
12452 .we (mio_pad_attr_3_gated_we),
12453 .wd (mio_pad_attr_3_virtual_od_en_3_wd),
12454 .d (hw2reg.mio_pad_attr[3].virtual_od_en.d),
12455 .qre (),
12456 .qe (mio_pad_attr_3_flds_we[1]),
12457 .q (reg2hw.mio_pad_attr[3].virtual_od_en.q),
12458 .ds (),
12459 .qs (mio_pad_attr_3_virtual_od_en_3_qs)
12460 );
12461 1/1 assign reg2hw.mio_pad_attr[3].virtual_od_en.qe = mio_pad_attr_3_qe;
Tests: T96 T97 T98
12462
12463 // F[pull_en_3]: 2:2
12464 prim_subreg_ext #(
12465 .DW (1)
12466 ) u_mio_pad_attr_3_pull_en_3 (
12467 .re (mio_pad_attr_3_re),
12468 .we (mio_pad_attr_3_gated_we),
12469 .wd (mio_pad_attr_3_pull_en_3_wd),
12470 .d (hw2reg.mio_pad_attr[3].pull_en.d),
12471 .qre (),
12472 .qe (mio_pad_attr_3_flds_we[2]),
12473 .q (reg2hw.mio_pad_attr[3].pull_en.q),
12474 .ds (),
12475 .qs (mio_pad_attr_3_pull_en_3_qs)
12476 );
12477 1/1 assign reg2hw.mio_pad_attr[3].pull_en.qe = mio_pad_attr_3_qe;
Tests: T96 T97 T98
12478
12479 // F[pull_select_3]: 3:3
12480 prim_subreg_ext #(
12481 .DW (1)
12482 ) u_mio_pad_attr_3_pull_select_3 (
12483 .re (mio_pad_attr_3_re),
12484 .we (mio_pad_attr_3_gated_we),
12485 .wd (mio_pad_attr_3_pull_select_3_wd),
12486 .d (hw2reg.mio_pad_attr[3].pull_select.d),
12487 .qre (),
12488 .qe (mio_pad_attr_3_flds_we[3]),
12489 .q (reg2hw.mio_pad_attr[3].pull_select.q),
12490 .ds (),
12491 .qs (mio_pad_attr_3_pull_select_3_qs)
12492 );
12493 1/1 assign reg2hw.mio_pad_attr[3].pull_select.qe = mio_pad_attr_3_qe;
Tests: T96 T97 T98
12494
12495 // F[keeper_en_3]: 4:4
12496 prim_subreg_ext #(
12497 .DW (1)
12498 ) u_mio_pad_attr_3_keeper_en_3 (
12499 .re (mio_pad_attr_3_re),
12500 .we (mio_pad_attr_3_gated_we),
12501 .wd (mio_pad_attr_3_keeper_en_3_wd),
12502 .d (hw2reg.mio_pad_attr[3].keeper_en.d),
12503 .qre (),
12504 .qe (mio_pad_attr_3_flds_we[4]),
12505 .q (reg2hw.mio_pad_attr[3].keeper_en.q),
12506 .ds (),
12507 .qs (mio_pad_attr_3_keeper_en_3_qs)
12508 );
12509 1/1 assign reg2hw.mio_pad_attr[3].keeper_en.qe = mio_pad_attr_3_qe;
Tests: T96 T97 T98
12510
12511 // F[schmitt_en_3]: 5:5
12512 prim_subreg_ext #(
12513 .DW (1)
12514 ) u_mio_pad_attr_3_schmitt_en_3 (
12515 .re (mio_pad_attr_3_re),
12516 .we (mio_pad_attr_3_gated_we),
12517 .wd (mio_pad_attr_3_schmitt_en_3_wd),
12518 .d (hw2reg.mio_pad_attr[3].schmitt_en.d),
12519 .qre (),
12520 .qe (mio_pad_attr_3_flds_we[5]),
12521 .q (reg2hw.mio_pad_attr[3].schmitt_en.q),
12522 .ds (),
12523 .qs (mio_pad_attr_3_schmitt_en_3_qs)
12524 );
12525 1/1 assign reg2hw.mio_pad_attr[3].schmitt_en.qe = mio_pad_attr_3_qe;
Tests: T96 T97 T98
12526
12527 // F[od_en_3]: 6:6
12528 prim_subreg_ext #(
12529 .DW (1)
12530 ) u_mio_pad_attr_3_od_en_3 (
12531 .re (mio_pad_attr_3_re),
12532 .we (mio_pad_attr_3_gated_we),
12533 .wd (mio_pad_attr_3_od_en_3_wd),
12534 .d (hw2reg.mio_pad_attr[3].od_en.d),
12535 .qre (),
12536 .qe (mio_pad_attr_3_flds_we[6]),
12537 .q (reg2hw.mio_pad_attr[3].od_en.q),
12538 .ds (),
12539 .qs (mio_pad_attr_3_od_en_3_qs)
12540 );
12541 1/1 assign reg2hw.mio_pad_attr[3].od_en.qe = mio_pad_attr_3_qe;
Tests: T96 T97 T98
12542
12543 // F[input_disable_3]: 7:7
12544 prim_subreg_ext #(
12545 .DW (1)
12546 ) u_mio_pad_attr_3_input_disable_3 (
12547 .re (mio_pad_attr_3_re),
12548 .we (mio_pad_attr_3_gated_we),
12549 .wd (mio_pad_attr_3_input_disable_3_wd),
12550 .d (hw2reg.mio_pad_attr[3].input_disable.d),
12551 .qre (),
12552 .qe (mio_pad_attr_3_flds_we[7]),
12553 .q (reg2hw.mio_pad_attr[3].input_disable.q),
12554 .ds (),
12555 .qs (mio_pad_attr_3_input_disable_3_qs)
12556 );
12557 1/1 assign reg2hw.mio_pad_attr[3].input_disable.qe = mio_pad_attr_3_qe;
Tests: T96 T97 T98
12558
12559 // F[slew_rate_3]: 17:16
12560 prim_subreg_ext #(
12561 .DW (2)
12562 ) u_mio_pad_attr_3_slew_rate_3 (
12563 .re (mio_pad_attr_3_re),
12564 .we (mio_pad_attr_3_gated_we),
12565 .wd (mio_pad_attr_3_slew_rate_3_wd),
12566 .d (hw2reg.mio_pad_attr[3].slew_rate.d),
12567 .qre (),
12568 .qe (mio_pad_attr_3_flds_we[8]),
12569 .q (reg2hw.mio_pad_attr[3].slew_rate.q),
12570 .ds (),
12571 .qs (mio_pad_attr_3_slew_rate_3_qs)
12572 );
12573 1/1 assign reg2hw.mio_pad_attr[3].slew_rate.qe = mio_pad_attr_3_qe;
Tests: T96 T97 T98
12574
12575 // F[drive_strength_3]: 23:20
12576 prim_subreg_ext #(
12577 .DW (4)
12578 ) u_mio_pad_attr_3_drive_strength_3 (
12579 .re (mio_pad_attr_3_re),
12580 .we (mio_pad_attr_3_gated_we),
12581 .wd (mio_pad_attr_3_drive_strength_3_wd),
12582 .d (hw2reg.mio_pad_attr[3].drive_strength.d),
12583 .qre (),
12584 .qe (mio_pad_attr_3_flds_we[9]),
12585 .q (reg2hw.mio_pad_attr[3].drive_strength.q),
12586 .ds (),
12587 .qs (mio_pad_attr_3_drive_strength_3_qs)
12588 );
12589 1/1 assign reg2hw.mio_pad_attr[3].drive_strength.qe = mio_pad_attr_3_qe;
Tests: T96 T97 T98
12590
12591
12592 // Subregister 4 of Multireg mio_pad_attr
12593 // R[mio_pad_attr_4]: V(True)
12594 logic mio_pad_attr_4_qe;
12595 logic [9:0] mio_pad_attr_4_flds_we;
12596 1/1 assign mio_pad_attr_4_qe = &mio_pad_attr_4_flds_we;
Tests: T96 T97 T98
12597 // Create REGWEN-gated WE signal
12598 logic mio_pad_attr_4_gated_we;
12599 1/1 assign mio_pad_attr_4_gated_we = mio_pad_attr_4_we & mio_pad_attr_regwen_4_qs;
Tests: T71 T96 T97
12600 // F[invert_4]: 0:0
12601 prim_subreg_ext #(
12602 .DW (1)
12603 ) u_mio_pad_attr_4_invert_4 (
12604 .re (mio_pad_attr_4_re),
12605 .we (mio_pad_attr_4_gated_we),
12606 .wd (mio_pad_attr_4_invert_4_wd),
12607 .d (hw2reg.mio_pad_attr[4].invert.d),
12608 .qre (),
12609 .qe (mio_pad_attr_4_flds_we[0]),
12610 .q (reg2hw.mio_pad_attr[4].invert.q),
12611 .ds (),
12612 .qs (mio_pad_attr_4_invert_4_qs)
12613 );
12614 1/1 assign reg2hw.mio_pad_attr[4].invert.qe = mio_pad_attr_4_qe;
Tests: T96 T97 T98
12615
12616 // F[virtual_od_en_4]: 1:1
12617 prim_subreg_ext #(
12618 .DW (1)
12619 ) u_mio_pad_attr_4_virtual_od_en_4 (
12620 .re (mio_pad_attr_4_re),
12621 .we (mio_pad_attr_4_gated_we),
12622 .wd (mio_pad_attr_4_virtual_od_en_4_wd),
12623 .d (hw2reg.mio_pad_attr[4].virtual_od_en.d),
12624 .qre (),
12625 .qe (mio_pad_attr_4_flds_we[1]),
12626 .q (reg2hw.mio_pad_attr[4].virtual_od_en.q),
12627 .ds (),
12628 .qs (mio_pad_attr_4_virtual_od_en_4_qs)
12629 );
12630 1/1 assign reg2hw.mio_pad_attr[4].virtual_od_en.qe = mio_pad_attr_4_qe;
Tests: T96 T97 T98
12631
12632 // F[pull_en_4]: 2:2
12633 prim_subreg_ext #(
12634 .DW (1)
12635 ) u_mio_pad_attr_4_pull_en_4 (
12636 .re (mio_pad_attr_4_re),
12637 .we (mio_pad_attr_4_gated_we),
12638 .wd (mio_pad_attr_4_pull_en_4_wd),
12639 .d (hw2reg.mio_pad_attr[4].pull_en.d),
12640 .qre (),
12641 .qe (mio_pad_attr_4_flds_we[2]),
12642 .q (reg2hw.mio_pad_attr[4].pull_en.q),
12643 .ds (),
12644 .qs (mio_pad_attr_4_pull_en_4_qs)
12645 );
12646 1/1 assign reg2hw.mio_pad_attr[4].pull_en.qe = mio_pad_attr_4_qe;
Tests: T96 T97 T98
12647
12648 // F[pull_select_4]: 3:3
12649 prim_subreg_ext #(
12650 .DW (1)
12651 ) u_mio_pad_attr_4_pull_select_4 (
12652 .re (mio_pad_attr_4_re),
12653 .we (mio_pad_attr_4_gated_we),
12654 .wd (mio_pad_attr_4_pull_select_4_wd),
12655 .d (hw2reg.mio_pad_attr[4].pull_select.d),
12656 .qre (),
12657 .qe (mio_pad_attr_4_flds_we[3]),
12658 .q (reg2hw.mio_pad_attr[4].pull_select.q),
12659 .ds (),
12660 .qs (mio_pad_attr_4_pull_select_4_qs)
12661 );
12662 1/1 assign reg2hw.mio_pad_attr[4].pull_select.qe = mio_pad_attr_4_qe;
Tests: T96 T97 T98
12663
12664 // F[keeper_en_4]: 4:4
12665 prim_subreg_ext #(
12666 .DW (1)
12667 ) u_mio_pad_attr_4_keeper_en_4 (
12668 .re (mio_pad_attr_4_re),
12669 .we (mio_pad_attr_4_gated_we),
12670 .wd (mio_pad_attr_4_keeper_en_4_wd),
12671 .d (hw2reg.mio_pad_attr[4].keeper_en.d),
12672 .qre (),
12673 .qe (mio_pad_attr_4_flds_we[4]),
12674 .q (reg2hw.mio_pad_attr[4].keeper_en.q),
12675 .ds (),
12676 .qs (mio_pad_attr_4_keeper_en_4_qs)
12677 );
12678 1/1 assign reg2hw.mio_pad_attr[4].keeper_en.qe = mio_pad_attr_4_qe;
Tests: T96 T97 T98
12679
12680 // F[schmitt_en_4]: 5:5
12681 prim_subreg_ext #(
12682 .DW (1)
12683 ) u_mio_pad_attr_4_schmitt_en_4 (
12684 .re (mio_pad_attr_4_re),
12685 .we (mio_pad_attr_4_gated_we),
12686 .wd (mio_pad_attr_4_schmitt_en_4_wd),
12687 .d (hw2reg.mio_pad_attr[4].schmitt_en.d),
12688 .qre (),
12689 .qe (mio_pad_attr_4_flds_we[5]),
12690 .q (reg2hw.mio_pad_attr[4].schmitt_en.q),
12691 .ds (),
12692 .qs (mio_pad_attr_4_schmitt_en_4_qs)
12693 );
12694 1/1 assign reg2hw.mio_pad_attr[4].schmitt_en.qe = mio_pad_attr_4_qe;
Tests: T96 T97 T98
12695
12696 // F[od_en_4]: 6:6
12697 prim_subreg_ext #(
12698 .DW (1)
12699 ) u_mio_pad_attr_4_od_en_4 (
12700 .re (mio_pad_attr_4_re),
12701 .we (mio_pad_attr_4_gated_we),
12702 .wd (mio_pad_attr_4_od_en_4_wd),
12703 .d (hw2reg.mio_pad_attr[4].od_en.d),
12704 .qre (),
12705 .qe (mio_pad_attr_4_flds_we[6]),
12706 .q (reg2hw.mio_pad_attr[4].od_en.q),
12707 .ds (),
12708 .qs (mio_pad_attr_4_od_en_4_qs)
12709 );
12710 1/1 assign reg2hw.mio_pad_attr[4].od_en.qe = mio_pad_attr_4_qe;
Tests: T96 T97 T98
12711
12712 // F[input_disable_4]: 7:7
12713 prim_subreg_ext #(
12714 .DW (1)
12715 ) u_mio_pad_attr_4_input_disable_4 (
12716 .re (mio_pad_attr_4_re),
12717 .we (mio_pad_attr_4_gated_we),
12718 .wd (mio_pad_attr_4_input_disable_4_wd),
12719 .d (hw2reg.mio_pad_attr[4].input_disable.d),
12720 .qre (),
12721 .qe (mio_pad_attr_4_flds_we[7]),
12722 .q (reg2hw.mio_pad_attr[4].input_disable.q),
12723 .ds (),
12724 .qs (mio_pad_attr_4_input_disable_4_qs)
12725 );
12726 1/1 assign reg2hw.mio_pad_attr[4].input_disable.qe = mio_pad_attr_4_qe;
Tests: T96 T97 T98
12727
12728 // F[slew_rate_4]: 17:16
12729 prim_subreg_ext #(
12730 .DW (2)
12731 ) u_mio_pad_attr_4_slew_rate_4 (
12732 .re (mio_pad_attr_4_re),
12733 .we (mio_pad_attr_4_gated_we),
12734 .wd (mio_pad_attr_4_slew_rate_4_wd),
12735 .d (hw2reg.mio_pad_attr[4].slew_rate.d),
12736 .qre (),
12737 .qe (mio_pad_attr_4_flds_we[8]),
12738 .q (reg2hw.mio_pad_attr[4].slew_rate.q),
12739 .ds (),
12740 .qs (mio_pad_attr_4_slew_rate_4_qs)
12741 );
12742 1/1 assign reg2hw.mio_pad_attr[4].slew_rate.qe = mio_pad_attr_4_qe;
Tests: T96 T97 T98
12743
12744 // F[drive_strength_4]: 23:20
12745 prim_subreg_ext #(
12746 .DW (4)
12747 ) u_mio_pad_attr_4_drive_strength_4 (
12748 .re (mio_pad_attr_4_re),
12749 .we (mio_pad_attr_4_gated_we),
12750 .wd (mio_pad_attr_4_drive_strength_4_wd),
12751 .d (hw2reg.mio_pad_attr[4].drive_strength.d),
12752 .qre (),
12753 .qe (mio_pad_attr_4_flds_we[9]),
12754 .q (reg2hw.mio_pad_attr[4].drive_strength.q),
12755 .ds (),
12756 .qs (mio_pad_attr_4_drive_strength_4_qs)
12757 );
12758 1/1 assign reg2hw.mio_pad_attr[4].drive_strength.qe = mio_pad_attr_4_qe;
Tests: T96 T97 T98
12759
12760
12761 // Subregister 5 of Multireg mio_pad_attr
12762 // R[mio_pad_attr_5]: V(True)
12763 logic mio_pad_attr_5_qe;
12764 logic [9:0] mio_pad_attr_5_flds_we;
12765 1/1 assign mio_pad_attr_5_qe = &mio_pad_attr_5_flds_we;
Tests: T96 T97 T98
12766 // Create REGWEN-gated WE signal
12767 logic mio_pad_attr_5_gated_we;
12768 1/1 assign mio_pad_attr_5_gated_we = mio_pad_attr_5_we & mio_pad_attr_regwen_5_qs;
Tests: T71 T96 T97
12769 // F[invert_5]: 0:0
12770 prim_subreg_ext #(
12771 .DW (1)
12772 ) u_mio_pad_attr_5_invert_5 (
12773 .re (mio_pad_attr_5_re),
12774 .we (mio_pad_attr_5_gated_we),
12775 .wd (mio_pad_attr_5_invert_5_wd),
12776 .d (hw2reg.mio_pad_attr[5].invert.d),
12777 .qre (),
12778 .qe (mio_pad_attr_5_flds_we[0]),
12779 .q (reg2hw.mio_pad_attr[5].invert.q),
12780 .ds (),
12781 .qs (mio_pad_attr_5_invert_5_qs)
12782 );
12783 1/1 assign reg2hw.mio_pad_attr[5].invert.qe = mio_pad_attr_5_qe;
Tests: T96 T97 T98
12784
12785 // F[virtual_od_en_5]: 1:1
12786 prim_subreg_ext #(
12787 .DW (1)
12788 ) u_mio_pad_attr_5_virtual_od_en_5 (
12789 .re (mio_pad_attr_5_re),
12790 .we (mio_pad_attr_5_gated_we),
12791 .wd (mio_pad_attr_5_virtual_od_en_5_wd),
12792 .d (hw2reg.mio_pad_attr[5].virtual_od_en.d),
12793 .qre (),
12794 .qe (mio_pad_attr_5_flds_we[1]),
12795 .q (reg2hw.mio_pad_attr[5].virtual_od_en.q),
12796 .ds (),
12797 .qs (mio_pad_attr_5_virtual_od_en_5_qs)
12798 );
12799 1/1 assign reg2hw.mio_pad_attr[5].virtual_od_en.qe = mio_pad_attr_5_qe;
Tests: T96 T97 T98
12800
12801 // F[pull_en_5]: 2:2
12802 prim_subreg_ext #(
12803 .DW (1)
12804 ) u_mio_pad_attr_5_pull_en_5 (
12805 .re (mio_pad_attr_5_re),
12806 .we (mio_pad_attr_5_gated_we),
12807 .wd (mio_pad_attr_5_pull_en_5_wd),
12808 .d (hw2reg.mio_pad_attr[5].pull_en.d),
12809 .qre (),
12810 .qe (mio_pad_attr_5_flds_we[2]),
12811 .q (reg2hw.mio_pad_attr[5].pull_en.q),
12812 .ds (),
12813 .qs (mio_pad_attr_5_pull_en_5_qs)
12814 );
12815 1/1 assign reg2hw.mio_pad_attr[5].pull_en.qe = mio_pad_attr_5_qe;
Tests: T96 T97 T98
12816
12817 // F[pull_select_5]: 3:3
12818 prim_subreg_ext #(
12819 .DW (1)
12820 ) u_mio_pad_attr_5_pull_select_5 (
12821 .re (mio_pad_attr_5_re),
12822 .we (mio_pad_attr_5_gated_we),
12823 .wd (mio_pad_attr_5_pull_select_5_wd),
12824 .d (hw2reg.mio_pad_attr[5].pull_select.d),
12825 .qre (),
12826 .qe (mio_pad_attr_5_flds_we[3]),
12827 .q (reg2hw.mio_pad_attr[5].pull_select.q),
12828 .ds (),
12829 .qs (mio_pad_attr_5_pull_select_5_qs)
12830 );
12831 1/1 assign reg2hw.mio_pad_attr[5].pull_select.qe = mio_pad_attr_5_qe;
Tests: T96 T97 T98
12832
12833 // F[keeper_en_5]: 4:4
12834 prim_subreg_ext #(
12835 .DW (1)
12836 ) u_mio_pad_attr_5_keeper_en_5 (
12837 .re (mio_pad_attr_5_re),
12838 .we (mio_pad_attr_5_gated_we),
12839 .wd (mio_pad_attr_5_keeper_en_5_wd),
12840 .d (hw2reg.mio_pad_attr[5].keeper_en.d),
12841 .qre (),
12842 .qe (mio_pad_attr_5_flds_we[4]),
12843 .q (reg2hw.mio_pad_attr[5].keeper_en.q),
12844 .ds (),
12845 .qs (mio_pad_attr_5_keeper_en_5_qs)
12846 );
12847 1/1 assign reg2hw.mio_pad_attr[5].keeper_en.qe = mio_pad_attr_5_qe;
Tests: T96 T97 T98
12848
12849 // F[schmitt_en_5]: 5:5
12850 prim_subreg_ext #(
12851 .DW (1)
12852 ) u_mio_pad_attr_5_schmitt_en_5 (
12853 .re (mio_pad_attr_5_re),
12854 .we (mio_pad_attr_5_gated_we),
12855 .wd (mio_pad_attr_5_schmitt_en_5_wd),
12856 .d (hw2reg.mio_pad_attr[5].schmitt_en.d),
12857 .qre (),
12858 .qe (mio_pad_attr_5_flds_we[5]),
12859 .q (reg2hw.mio_pad_attr[5].schmitt_en.q),
12860 .ds (),
12861 .qs (mio_pad_attr_5_schmitt_en_5_qs)
12862 );
12863 1/1 assign reg2hw.mio_pad_attr[5].schmitt_en.qe = mio_pad_attr_5_qe;
Tests: T96 T97 T98
12864
12865 // F[od_en_5]: 6:6
12866 prim_subreg_ext #(
12867 .DW (1)
12868 ) u_mio_pad_attr_5_od_en_5 (
12869 .re (mio_pad_attr_5_re),
12870 .we (mio_pad_attr_5_gated_we),
12871 .wd (mio_pad_attr_5_od_en_5_wd),
12872 .d (hw2reg.mio_pad_attr[5].od_en.d),
12873 .qre (),
12874 .qe (mio_pad_attr_5_flds_we[6]),
12875 .q (reg2hw.mio_pad_attr[5].od_en.q),
12876 .ds (),
12877 .qs (mio_pad_attr_5_od_en_5_qs)
12878 );
12879 1/1 assign reg2hw.mio_pad_attr[5].od_en.qe = mio_pad_attr_5_qe;
Tests: T96 T97 T98
12880
12881 // F[input_disable_5]: 7:7
12882 prim_subreg_ext #(
12883 .DW (1)
12884 ) u_mio_pad_attr_5_input_disable_5 (
12885 .re (mio_pad_attr_5_re),
12886 .we (mio_pad_attr_5_gated_we),
12887 .wd (mio_pad_attr_5_input_disable_5_wd),
12888 .d (hw2reg.mio_pad_attr[5].input_disable.d),
12889 .qre (),
12890 .qe (mio_pad_attr_5_flds_we[7]),
12891 .q (reg2hw.mio_pad_attr[5].input_disable.q),
12892 .ds (),
12893 .qs (mio_pad_attr_5_input_disable_5_qs)
12894 );
12895 1/1 assign reg2hw.mio_pad_attr[5].input_disable.qe = mio_pad_attr_5_qe;
Tests: T96 T97 T98
12896
12897 // F[slew_rate_5]: 17:16
12898 prim_subreg_ext #(
12899 .DW (2)
12900 ) u_mio_pad_attr_5_slew_rate_5 (
12901 .re (mio_pad_attr_5_re),
12902 .we (mio_pad_attr_5_gated_we),
12903 .wd (mio_pad_attr_5_slew_rate_5_wd),
12904 .d (hw2reg.mio_pad_attr[5].slew_rate.d),
12905 .qre (),
12906 .qe (mio_pad_attr_5_flds_we[8]),
12907 .q (reg2hw.mio_pad_attr[5].slew_rate.q),
12908 .ds (),
12909 .qs (mio_pad_attr_5_slew_rate_5_qs)
12910 );
12911 1/1 assign reg2hw.mio_pad_attr[5].slew_rate.qe = mio_pad_attr_5_qe;
Tests: T96 T97 T98
12912
12913 // F[drive_strength_5]: 23:20
12914 prim_subreg_ext #(
12915 .DW (4)
12916 ) u_mio_pad_attr_5_drive_strength_5 (
12917 .re (mio_pad_attr_5_re),
12918 .we (mio_pad_attr_5_gated_we),
12919 .wd (mio_pad_attr_5_drive_strength_5_wd),
12920 .d (hw2reg.mio_pad_attr[5].drive_strength.d),
12921 .qre (),
12922 .qe (mio_pad_attr_5_flds_we[9]),
12923 .q (reg2hw.mio_pad_attr[5].drive_strength.q),
12924 .ds (),
12925 .qs (mio_pad_attr_5_drive_strength_5_qs)
12926 );
12927 1/1 assign reg2hw.mio_pad_attr[5].drive_strength.qe = mio_pad_attr_5_qe;
Tests: T96 T97 T98
12928
12929
12930 // Subregister 6 of Multireg mio_pad_attr
12931 // R[mio_pad_attr_6]: V(True)
12932 logic mio_pad_attr_6_qe;
12933 logic [9:0] mio_pad_attr_6_flds_we;
12934 1/1 assign mio_pad_attr_6_qe = &mio_pad_attr_6_flds_we;
Tests: T96 T97 T98
12935 // Create REGWEN-gated WE signal
12936 logic mio_pad_attr_6_gated_we;
12937 1/1 assign mio_pad_attr_6_gated_we = mio_pad_attr_6_we & mio_pad_attr_regwen_6_qs;
Tests: T96 T97 T98
12938 // F[invert_6]: 0:0
12939 prim_subreg_ext #(
12940 .DW (1)
12941 ) u_mio_pad_attr_6_invert_6 (
12942 .re (mio_pad_attr_6_re),
12943 .we (mio_pad_attr_6_gated_we),
12944 .wd (mio_pad_attr_6_invert_6_wd),
12945 .d (hw2reg.mio_pad_attr[6].invert.d),
12946 .qre (),
12947 .qe (mio_pad_attr_6_flds_we[0]),
12948 .q (reg2hw.mio_pad_attr[6].invert.q),
12949 .ds (),
12950 .qs (mio_pad_attr_6_invert_6_qs)
12951 );
12952 1/1 assign reg2hw.mio_pad_attr[6].invert.qe = mio_pad_attr_6_qe;
Tests: T96 T97 T98
12953
12954 // F[virtual_od_en_6]: 1:1
12955 prim_subreg_ext #(
12956 .DW (1)
12957 ) u_mio_pad_attr_6_virtual_od_en_6 (
12958 .re (mio_pad_attr_6_re),
12959 .we (mio_pad_attr_6_gated_we),
12960 .wd (mio_pad_attr_6_virtual_od_en_6_wd),
12961 .d (hw2reg.mio_pad_attr[6].virtual_od_en.d),
12962 .qre (),
12963 .qe (mio_pad_attr_6_flds_we[1]),
12964 .q (reg2hw.mio_pad_attr[6].virtual_od_en.q),
12965 .ds (),
12966 .qs (mio_pad_attr_6_virtual_od_en_6_qs)
12967 );
12968 1/1 assign reg2hw.mio_pad_attr[6].virtual_od_en.qe = mio_pad_attr_6_qe;
Tests: T96 T97 T98
12969
12970 // F[pull_en_6]: 2:2
12971 prim_subreg_ext #(
12972 .DW (1)
12973 ) u_mio_pad_attr_6_pull_en_6 (
12974 .re (mio_pad_attr_6_re),
12975 .we (mio_pad_attr_6_gated_we),
12976 .wd (mio_pad_attr_6_pull_en_6_wd),
12977 .d (hw2reg.mio_pad_attr[6].pull_en.d),
12978 .qre (),
12979 .qe (mio_pad_attr_6_flds_we[2]),
12980 .q (reg2hw.mio_pad_attr[6].pull_en.q),
12981 .ds (),
12982 .qs (mio_pad_attr_6_pull_en_6_qs)
12983 );
12984 1/1 assign reg2hw.mio_pad_attr[6].pull_en.qe = mio_pad_attr_6_qe;
Tests: T96 T97 T98
12985
12986 // F[pull_select_6]: 3:3
12987 prim_subreg_ext #(
12988 .DW (1)
12989 ) u_mio_pad_attr_6_pull_select_6 (
12990 .re (mio_pad_attr_6_re),
12991 .we (mio_pad_attr_6_gated_we),
12992 .wd (mio_pad_attr_6_pull_select_6_wd),
12993 .d (hw2reg.mio_pad_attr[6].pull_select.d),
12994 .qre (),
12995 .qe (mio_pad_attr_6_flds_we[3]),
12996 .q (reg2hw.mio_pad_attr[6].pull_select.q),
12997 .ds (),
12998 .qs (mio_pad_attr_6_pull_select_6_qs)
12999 );
13000 1/1 assign reg2hw.mio_pad_attr[6].pull_select.qe = mio_pad_attr_6_qe;
Tests: T96 T97 T98
13001
13002 // F[keeper_en_6]: 4:4
13003 prim_subreg_ext #(
13004 .DW (1)
13005 ) u_mio_pad_attr_6_keeper_en_6 (
13006 .re (mio_pad_attr_6_re),
13007 .we (mio_pad_attr_6_gated_we),
13008 .wd (mio_pad_attr_6_keeper_en_6_wd),
13009 .d (hw2reg.mio_pad_attr[6].keeper_en.d),
13010 .qre (),
13011 .qe (mio_pad_attr_6_flds_we[4]),
13012 .q (reg2hw.mio_pad_attr[6].keeper_en.q),
13013 .ds (),
13014 .qs (mio_pad_attr_6_keeper_en_6_qs)
13015 );
13016 1/1 assign reg2hw.mio_pad_attr[6].keeper_en.qe = mio_pad_attr_6_qe;
Tests: T96 T97 T98
13017
13018 // F[schmitt_en_6]: 5:5
13019 prim_subreg_ext #(
13020 .DW (1)
13021 ) u_mio_pad_attr_6_schmitt_en_6 (
13022 .re (mio_pad_attr_6_re),
13023 .we (mio_pad_attr_6_gated_we),
13024 .wd (mio_pad_attr_6_schmitt_en_6_wd),
13025 .d (hw2reg.mio_pad_attr[6].schmitt_en.d),
13026 .qre (),
13027 .qe (mio_pad_attr_6_flds_we[5]),
13028 .q (reg2hw.mio_pad_attr[6].schmitt_en.q),
13029 .ds (),
13030 .qs (mio_pad_attr_6_schmitt_en_6_qs)
13031 );
13032 1/1 assign reg2hw.mio_pad_attr[6].schmitt_en.qe = mio_pad_attr_6_qe;
Tests: T96 T97 T98
13033
13034 // F[od_en_6]: 6:6
13035 prim_subreg_ext #(
13036 .DW (1)
13037 ) u_mio_pad_attr_6_od_en_6 (
13038 .re (mio_pad_attr_6_re),
13039 .we (mio_pad_attr_6_gated_we),
13040 .wd (mio_pad_attr_6_od_en_6_wd),
13041 .d (hw2reg.mio_pad_attr[6].od_en.d),
13042 .qre (),
13043 .qe (mio_pad_attr_6_flds_we[6]),
13044 .q (reg2hw.mio_pad_attr[6].od_en.q),
13045 .ds (),
13046 .qs (mio_pad_attr_6_od_en_6_qs)
13047 );
13048 1/1 assign reg2hw.mio_pad_attr[6].od_en.qe = mio_pad_attr_6_qe;
Tests: T96 T97 T98
13049
13050 // F[input_disable_6]: 7:7
13051 prim_subreg_ext #(
13052 .DW (1)
13053 ) u_mio_pad_attr_6_input_disable_6 (
13054 .re (mio_pad_attr_6_re),
13055 .we (mio_pad_attr_6_gated_we),
13056 .wd (mio_pad_attr_6_input_disable_6_wd),
13057 .d (hw2reg.mio_pad_attr[6].input_disable.d),
13058 .qre (),
13059 .qe (mio_pad_attr_6_flds_we[7]),
13060 .q (reg2hw.mio_pad_attr[6].input_disable.q),
13061 .ds (),
13062 .qs (mio_pad_attr_6_input_disable_6_qs)
13063 );
13064 1/1 assign reg2hw.mio_pad_attr[6].input_disable.qe = mio_pad_attr_6_qe;
Tests: T96 T97 T98
13065
13066 // F[slew_rate_6]: 17:16
13067 prim_subreg_ext #(
13068 .DW (2)
13069 ) u_mio_pad_attr_6_slew_rate_6 (
13070 .re (mio_pad_attr_6_re),
13071 .we (mio_pad_attr_6_gated_we),
13072 .wd (mio_pad_attr_6_slew_rate_6_wd),
13073 .d (hw2reg.mio_pad_attr[6].slew_rate.d),
13074 .qre (),
13075 .qe (mio_pad_attr_6_flds_we[8]),
13076 .q (reg2hw.mio_pad_attr[6].slew_rate.q),
13077 .ds (),
13078 .qs (mio_pad_attr_6_slew_rate_6_qs)
13079 );
13080 1/1 assign reg2hw.mio_pad_attr[6].slew_rate.qe = mio_pad_attr_6_qe;
Tests: T96 T97 T98
13081
13082 // F[drive_strength_6]: 23:20
13083 prim_subreg_ext #(
13084 .DW (4)
13085 ) u_mio_pad_attr_6_drive_strength_6 (
13086 .re (mio_pad_attr_6_re),
13087 .we (mio_pad_attr_6_gated_we),
13088 .wd (mio_pad_attr_6_drive_strength_6_wd),
13089 .d (hw2reg.mio_pad_attr[6].drive_strength.d),
13090 .qre (),
13091 .qe (mio_pad_attr_6_flds_we[9]),
13092 .q (reg2hw.mio_pad_attr[6].drive_strength.q),
13093 .ds (),
13094 .qs (mio_pad_attr_6_drive_strength_6_qs)
13095 );
13096 1/1 assign reg2hw.mio_pad_attr[6].drive_strength.qe = mio_pad_attr_6_qe;
Tests: T96 T97 T98
13097
13098
13099 // Subregister 7 of Multireg mio_pad_attr
13100 // R[mio_pad_attr_7]: V(True)
13101 logic mio_pad_attr_7_qe;
13102 logic [9:0] mio_pad_attr_7_flds_we;
13103 1/1 assign mio_pad_attr_7_qe = &mio_pad_attr_7_flds_we;
Tests: T12 T53 T54
13104 // Create REGWEN-gated WE signal
13105 logic mio_pad_attr_7_gated_we;
13106 1/1 assign mio_pad_attr_7_gated_we = mio_pad_attr_7_we & mio_pad_attr_regwen_7_qs;
Tests: T12 T53 T54
13107 // F[invert_7]: 0:0
13108 prim_subreg_ext #(
13109 .DW (1)
13110 ) u_mio_pad_attr_7_invert_7 (
13111 .re (mio_pad_attr_7_re),
13112 .we (mio_pad_attr_7_gated_we),
13113 .wd (mio_pad_attr_7_invert_7_wd),
13114 .d (hw2reg.mio_pad_attr[7].invert.d),
13115 .qre (),
13116 .qe (mio_pad_attr_7_flds_we[0]),
13117 .q (reg2hw.mio_pad_attr[7].invert.q),
13118 .ds (),
13119 .qs (mio_pad_attr_7_invert_7_qs)
13120 );
13121 1/1 assign reg2hw.mio_pad_attr[7].invert.qe = mio_pad_attr_7_qe;
Tests: T12 T53 T54
13122
13123 // F[virtual_od_en_7]: 1:1
13124 prim_subreg_ext #(
13125 .DW (1)
13126 ) u_mio_pad_attr_7_virtual_od_en_7 (
13127 .re (mio_pad_attr_7_re),
13128 .we (mio_pad_attr_7_gated_we),
13129 .wd (mio_pad_attr_7_virtual_od_en_7_wd),
13130 .d (hw2reg.mio_pad_attr[7].virtual_od_en.d),
13131 .qre (),
13132 .qe (mio_pad_attr_7_flds_we[1]),
13133 .q (reg2hw.mio_pad_attr[7].virtual_od_en.q),
13134 .ds (),
13135 .qs (mio_pad_attr_7_virtual_od_en_7_qs)
13136 );
13137 1/1 assign reg2hw.mio_pad_attr[7].virtual_od_en.qe = mio_pad_attr_7_qe;
Tests: T12 T53 T54
13138
13139 // F[pull_en_7]: 2:2
13140 prim_subreg_ext #(
13141 .DW (1)
13142 ) u_mio_pad_attr_7_pull_en_7 (
13143 .re (mio_pad_attr_7_re),
13144 .we (mio_pad_attr_7_gated_we),
13145 .wd (mio_pad_attr_7_pull_en_7_wd),
13146 .d (hw2reg.mio_pad_attr[7].pull_en.d),
13147 .qre (),
13148 .qe (mio_pad_attr_7_flds_we[2]),
13149 .q (reg2hw.mio_pad_attr[7].pull_en.q),
13150 .ds (),
13151 .qs (mio_pad_attr_7_pull_en_7_qs)
13152 );
13153 1/1 assign reg2hw.mio_pad_attr[7].pull_en.qe = mio_pad_attr_7_qe;
Tests: T12 T53 T54
13154
13155 // F[pull_select_7]: 3:3
13156 prim_subreg_ext #(
13157 .DW (1)
13158 ) u_mio_pad_attr_7_pull_select_7 (
13159 .re (mio_pad_attr_7_re),
13160 .we (mio_pad_attr_7_gated_we),
13161 .wd (mio_pad_attr_7_pull_select_7_wd),
13162 .d (hw2reg.mio_pad_attr[7].pull_select.d),
13163 .qre (),
13164 .qe (mio_pad_attr_7_flds_we[3]),
13165 .q (reg2hw.mio_pad_attr[7].pull_select.q),
13166 .ds (),
13167 .qs (mio_pad_attr_7_pull_select_7_qs)
13168 );
13169 1/1 assign reg2hw.mio_pad_attr[7].pull_select.qe = mio_pad_attr_7_qe;
Tests: T12 T53 T54
13170
13171 // F[keeper_en_7]: 4:4
13172 prim_subreg_ext #(
13173 .DW (1)
13174 ) u_mio_pad_attr_7_keeper_en_7 (
13175 .re (mio_pad_attr_7_re),
13176 .we (mio_pad_attr_7_gated_we),
13177 .wd (mio_pad_attr_7_keeper_en_7_wd),
13178 .d (hw2reg.mio_pad_attr[7].keeper_en.d),
13179 .qre (),
13180 .qe (mio_pad_attr_7_flds_we[4]),
13181 .q (reg2hw.mio_pad_attr[7].keeper_en.q),
13182 .ds (),
13183 .qs (mio_pad_attr_7_keeper_en_7_qs)
13184 );
13185 1/1 assign reg2hw.mio_pad_attr[7].keeper_en.qe = mio_pad_attr_7_qe;
Tests: T12 T53 T54
13186
13187 // F[schmitt_en_7]: 5:5
13188 prim_subreg_ext #(
13189 .DW (1)
13190 ) u_mio_pad_attr_7_schmitt_en_7 (
13191 .re (mio_pad_attr_7_re),
13192 .we (mio_pad_attr_7_gated_we),
13193 .wd (mio_pad_attr_7_schmitt_en_7_wd),
13194 .d (hw2reg.mio_pad_attr[7].schmitt_en.d),
13195 .qre (),
13196 .qe (mio_pad_attr_7_flds_we[5]),
13197 .q (reg2hw.mio_pad_attr[7].schmitt_en.q),
13198 .ds (),
13199 .qs (mio_pad_attr_7_schmitt_en_7_qs)
13200 );
13201 1/1 assign reg2hw.mio_pad_attr[7].schmitt_en.qe = mio_pad_attr_7_qe;
Tests: T12 T53 T54
13202
13203 // F[od_en_7]: 6:6
13204 prim_subreg_ext #(
13205 .DW (1)
13206 ) u_mio_pad_attr_7_od_en_7 (
13207 .re (mio_pad_attr_7_re),
13208 .we (mio_pad_attr_7_gated_we),
13209 .wd (mio_pad_attr_7_od_en_7_wd),
13210 .d (hw2reg.mio_pad_attr[7].od_en.d),
13211 .qre (),
13212 .qe (mio_pad_attr_7_flds_we[6]),
13213 .q (reg2hw.mio_pad_attr[7].od_en.q),
13214 .ds (),
13215 .qs (mio_pad_attr_7_od_en_7_qs)
13216 );
13217 1/1 assign reg2hw.mio_pad_attr[7].od_en.qe = mio_pad_attr_7_qe;
Tests: T12 T53 T54
13218
13219 // F[input_disable_7]: 7:7
13220 prim_subreg_ext #(
13221 .DW (1)
13222 ) u_mio_pad_attr_7_input_disable_7 (
13223 .re (mio_pad_attr_7_re),
13224 .we (mio_pad_attr_7_gated_we),
13225 .wd (mio_pad_attr_7_input_disable_7_wd),
13226 .d (hw2reg.mio_pad_attr[7].input_disable.d),
13227 .qre (),
13228 .qe (mio_pad_attr_7_flds_we[7]),
13229 .q (reg2hw.mio_pad_attr[7].input_disable.q),
13230 .ds (),
13231 .qs (mio_pad_attr_7_input_disable_7_qs)
13232 );
13233 1/1 assign reg2hw.mio_pad_attr[7].input_disable.qe = mio_pad_attr_7_qe;
Tests: T12 T53 T54
13234
13235 // F[slew_rate_7]: 17:16
13236 prim_subreg_ext #(
13237 .DW (2)
13238 ) u_mio_pad_attr_7_slew_rate_7 (
13239 .re (mio_pad_attr_7_re),
13240 .we (mio_pad_attr_7_gated_we),
13241 .wd (mio_pad_attr_7_slew_rate_7_wd),
13242 .d (hw2reg.mio_pad_attr[7].slew_rate.d),
13243 .qre (),
13244 .qe (mio_pad_attr_7_flds_we[8]),
13245 .q (reg2hw.mio_pad_attr[7].slew_rate.q),
13246 .ds (),
13247 .qs (mio_pad_attr_7_slew_rate_7_qs)
13248 );
13249 1/1 assign reg2hw.mio_pad_attr[7].slew_rate.qe = mio_pad_attr_7_qe;
Tests: T12 T53 T54
13250
13251 // F[drive_strength_7]: 23:20
13252 prim_subreg_ext #(
13253 .DW (4)
13254 ) u_mio_pad_attr_7_drive_strength_7 (
13255 .re (mio_pad_attr_7_re),
13256 .we (mio_pad_attr_7_gated_we),
13257 .wd (mio_pad_attr_7_drive_strength_7_wd),
13258 .d (hw2reg.mio_pad_attr[7].drive_strength.d),
13259 .qre (),
13260 .qe (mio_pad_attr_7_flds_we[9]),
13261 .q (reg2hw.mio_pad_attr[7].drive_strength.q),
13262 .ds (),
13263 .qs (mio_pad_attr_7_drive_strength_7_qs)
13264 );
13265 1/1 assign reg2hw.mio_pad_attr[7].drive_strength.qe = mio_pad_attr_7_qe;
Tests: T12 T53 T54
13266
13267
13268 // Subregister 8 of Multireg mio_pad_attr
13269 // R[mio_pad_attr_8]: V(True)
13270 logic mio_pad_attr_8_qe;
13271 logic [9:0] mio_pad_attr_8_flds_we;
13272 1/1 assign mio_pad_attr_8_qe = &mio_pad_attr_8_flds_we;
Tests: T96 T97 T98
13273 // Create REGWEN-gated WE signal
13274 logic mio_pad_attr_8_gated_we;
13275 1/1 assign mio_pad_attr_8_gated_we = mio_pad_attr_8_we & mio_pad_attr_regwen_8_qs;
Tests: T96 T97 T98
13276 // F[invert_8]: 0:0
13277 prim_subreg_ext #(
13278 .DW (1)
13279 ) u_mio_pad_attr_8_invert_8 (
13280 .re (mio_pad_attr_8_re),
13281 .we (mio_pad_attr_8_gated_we),
13282 .wd (mio_pad_attr_8_invert_8_wd),
13283 .d (hw2reg.mio_pad_attr[8].invert.d),
13284 .qre (),
13285 .qe (mio_pad_attr_8_flds_we[0]),
13286 .q (reg2hw.mio_pad_attr[8].invert.q),
13287 .ds (),
13288 .qs (mio_pad_attr_8_invert_8_qs)
13289 );
13290 1/1 assign reg2hw.mio_pad_attr[8].invert.qe = mio_pad_attr_8_qe;
Tests: T96 T97 T98
13291
13292 // F[virtual_od_en_8]: 1:1
13293 prim_subreg_ext #(
13294 .DW (1)
13295 ) u_mio_pad_attr_8_virtual_od_en_8 (
13296 .re (mio_pad_attr_8_re),
13297 .we (mio_pad_attr_8_gated_we),
13298 .wd (mio_pad_attr_8_virtual_od_en_8_wd),
13299 .d (hw2reg.mio_pad_attr[8].virtual_od_en.d),
13300 .qre (),
13301 .qe (mio_pad_attr_8_flds_we[1]),
13302 .q (reg2hw.mio_pad_attr[8].virtual_od_en.q),
13303 .ds (),
13304 .qs (mio_pad_attr_8_virtual_od_en_8_qs)
13305 );
13306 1/1 assign reg2hw.mio_pad_attr[8].virtual_od_en.qe = mio_pad_attr_8_qe;
Tests: T96 T97 T98
13307
13308 // F[pull_en_8]: 2:2
13309 prim_subreg_ext #(
13310 .DW (1)
13311 ) u_mio_pad_attr_8_pull_en_8 (
13312 .re (mio_pad_attr_8_re),
13313 .we (mio_pad_attr_8_gated_we),
13314 .wd (mio_pad_attr_8_pull_en_8_wd),
13315 .d (hw2reg.mio_pad_attr[8].pull_en.d),
13316 .qre (),
13317 .qe (mio_pad_attr_8_flds_we[2]),
13318 .q (reg2hw.mio_pad_attr[8].pull_en.q),
13319 .ds (),
13320 .qs (mio_pad_attr_8_pull_en_8_qs)
13321 );
13322 1/1 assign reg2hw.mio_pad_attr[8].pull_en.qe = mio_pad_attr_8_qe;
Tests: T96 T97 T98
13323
13324 // F[pull_select_8]: 3:3
13325 prim_subreg_ext #(
13326 .DW (1)
13327 ) u_mio_pad_attr_8_pull_select_8 (
13328 .re (mio_pad_attr_8_re),
13329 .we (mio_pad_attr_8_gated_we),
13330 .wd (mio_pad_attr_8_pull_select_8_wd),
13331 .d (hw2reg.mio_pad_attr[8].pull_select.d),
13332 .qre (),
13333 .qe (mio_pad_attr_8_flds_we[3]),
13334 .q (reg2hw.mio_pad_attr[8].pull_select.q),
13335 .ds (),
13336 .qs (mio_pad_attr_8_pull_select_8_qs)
13337 );
13338 1/1 assign reg2hw.mio_pad_attr[8].pull_select.qe = mio_pad_attr_8_qe;
Tests: T96 T97 T98
13339
13340 // F[keeper_en_8]: 4:4
13341 prim_subreg_ext #(
13342 .DW (1)
13343 ) u_mio_pad_attr_8_keeper_en_8 (
13344 .re (mio_pad_attr_8_re),
13345 .we (mio_pad_attr_8_gated_we),
13346 .wd (mio_pad_attr_8_keeper_en_8_wd),
13347 .d (hw2reg.mio_pad_attr[8].keeper_en.d),
13348 .qre (),
13349 .qe (mio_pad_attr_8_flds_we[4]),
13350 .q (reg2hw.mio_pad_attr[8].keeper_en.q),
13351 .ds (),
13352 .qs (mio_pad_attr_8_keeper_en_8_qs)
13353 );
13354 1/1 assign reg2hw.mio_pad_attr[8].keeper_en.qe = mio_pad_attr_8_qe;
Tests: T96 T97 T98
13355
13356 // F[schmitt_en_8]: 5:5
13357 prim_subreg_ext #(
13358 .DW (1)
13359 ) u_mio_pad_attr_8_schmitt_en_8 (
13360 .re (mio_pad_attr_8_re),
13361 .we (mio_pad_attr_8_gated_we),
13362 .wd (mio_pad_attr_8_schmitt_en_8_wd),
13363 .d (hw2reg.mio_pad_attr[8].schmitt_en.d),
13364 .qre (),
13365 .qe (mio_pad_attr_8_flds_we[5]),
13366 .q (reg2hw.mio_pad_attr[8].schmitt_en.q),
13367 .ds (),
13368 .qs (mio_pad_attr_8_schmitt_en_8_qs)
13369 );
13370 1/1 assign reg2hw.mio_pad_attr[8].schmitt_en.qe = mio_pad_attr_8_qe;
Tests: T96 T97 T98
13371
13372 // F[od_en_8]: 6:6
13373 prim_subreg_ext #(
13374 .DW (1)
13375 ) u_mio_pad_attr_8_od_en_8 (
13376 .re (mio_pad_attr_8_re),
13377 .we (mio_pad_attr_8_gated_we),
13378 .wd (mio_pad_attr_8_od_en_8_wd),
13379 .d (hw2reg.mio_pad_attr[8].od_en.d),
13380 .qre (),
13381 .qe (mio_pad_attr_8_flds_we[6]),
13382 .q (reg2hw.mio_pad_attr[8].od_en.q),
13383 .ds (),
13384 .qs (mio_pad_attr_8_od_en_8_qs)
13385 );
13386 1/1 assign reg2hw.mio_pad_attr[8].od_en.qe = mio_pad_attr_8_qe;
Tests: T96 T97 T98
13387
13388 // F[input_disable_8]: 7:7
13389 prim_subreg_ext #(
13390 .DW (1)
13391 ) u_mio_pad_attr_8_input_disable_8 (
13392 .re (mio_pad_attr_8_re),
13393 .we (mio_pad_attr_8_gated_we),
13394 .wd (mio_pad_attr_8_input_disable_8_wd),
13395 .d (hw2reg.mio_pad_attr[8].input_disable.d),
13396 .qre (),
13397 .qe (mio_pad_attr_8_flds_we[7]),
13398 .q (reg2hw.mio_pad_attr[8].input_disable.q),
13399 .ds (),
13400 .qs (mio_pad_attr_8_input_disable_8_qs)
13401 );
13402 1/1 assign reg2hw.mio_pad_attr[8].input_disable.qe = mio_pad_attr_8_qe;
Tests: T96 T97 T98
13403
13404 // F[slew_rate_8]: 17:16
13405 prim_subreg_ext #(
13406 .DW (2)
13407 ) u_mio_pad_attr_8_slew_rate_8 (
13408 .re (mio_pad_attr_8_re),
13409 .we (mio_pad_attr_8_gated_we),
13410 .wd (mio_pad_attr_8_slew_rate_8_wd),
13411 .d (hw2reg.mio_pad_attr[8].slew_rate.d),
13412 .qre (),
13413 .qe (mio_pad_attr_8_flds_we[8]),
13414 .q (reg2hw.mio_pad_attr[8].slew_rate.q),
13415 .ds (),
13416 .qs (mio_pad_attr_8_slew_rate_8_qs)
13417 );
13418 1/1 assign reg2hw.mio_pad_attr[8].slew_rate.qe = mio_pad_attr_8_qe;
Tests: T96 T97 T98
13419
13420 // F[drive_strength_8]: 23:20
13421 prim_subreg_ext #(
13422 .DW (4)
13423 ) u_mio_pad_attr_8_drive_strength_8 (
13424 .re (mio_pad_attr_8_re),
13425 .we (mio_pad_attr_8_gated_we),
13426 .wd (mio_pad_attr_8_drive_strength_8_wd),
13427 .d (hw2reg.mio_pad_attr[8].drive_strength.d),
13428 .qre (),
13429 .qe (mio_pad_attr_8_flds_we[9]),
13430 .q (reg2hw.mio_pad_attr[8].drive_strength.q),
13431 .ds (),
13432 .qs (mio_pad_attr_8_drive_strength_8_qs)
13433 );
13434 1/1 assign reg2hw.mio_pad_attr[8].drive_strength.qe = mio_pad_attr_8_qe;
Tests: T96 T97 T98
13435
13436
13437 // Subregister 9 of Multireg mio_pad_attr
13438 // R[mio_pad_attr_9]: V(True)
13439 logic mio_pad_attr_9_qe;
13440 logic [9:0] mio_pad_attr_9_flds_we;
13441 1/1 assign mio_pad_attr_9_qe = &mio_pad_attr_9_flds_we;
Tests: T9 T47 T48
13442 // Create REGWEN-gated WE signal
13443 logic mio_pad_attr_9_gated_we;
13444 1/1 assign mio_pad_attr_9_gated_we = mio_pad_attr_9_we & mio_pad_attr_regwen_9_qs;
Tests: T9 T47 T48
13445 // F[invert_9]: 0:0
13446 prim_subreg_ext #(
13447 .DW (1)
13448 ) u_mio_pad_attr_9_invert_9 (
13449 .re (mio_pad_attr_9_re),
13450 .we (mio_pad_attr_9_gated_we),
13451 .wd (mio_pad_attr_9_invert_9_wd),
13452 .d (hw2reg.mio_pad_attr[9].invert.d),
13453 .qre (),
13454 .qe (mio_pad_attr_9_flds_we[0]),
13455 .q (reg2hw.mio_pad_attr[9].invert.q),
13456 .ds (),
13457 .qs (mio_pad_attr_9_invert_9_qs)
13458 );
13459 1/1 assign reg2hw.mio_pad_attr[9].invert.qe = mio_pad_attr_9_qe;
Tests: T9 T47 T48
13460
13461 // F[virtual_od_en_9]: 1:1
13462 prim_subreg_ext #(
13463 .DW (1)
13464 ) u_mio_pad_attr_9_virtual_od_en_9 (
13465 .re (mio_pad_attr_9_re),
13466 .we (mio_pad_attr_9_gated_we),
13467 .wd (mio_pad_attr_9_virtual_od_en_9_wd),
13468 .d (hw2reg.mio_pad_attr[9].virtual_od_en.d),
13469 .qre (),
13470 .qe (mio_pad_attr_9_flds_we[1]),
13471 .q (reg2hw.mio_pad_attr[9].virtual_od_en.q),
13472 .ds (),
13473 .qs (mio_pad_attr_9_virtual_od_en_9_qs)
13474 );
13475 1/1 assign reg2hw.mio_pad_attr[9].virtual_od_en.qe = mio_pad_attr_9_qe;
Tests: T9 T47 T48
13476
13477 // F[pull_en_9]: 2:2
13478 prim_subreg_ext #(
13479 .DW (1)
13480 ) u_mio_pad_attr_9_pull_en_9 (
13481 .re (mio_pad_attr_9_re),
13482 .we (mio_pad_attr_9_gated_we),
13483 .wd (mio_pad_attr_9_pull_en_9_wd),
13484 .d (hw2reg.mio_pad_attr[9].pull_en.d),
13485 .qre (),
13486 .qe (mio_pad_attr_9_flds_we[2]),
13487 .q (reg2hw.mio_pad_attr[9].pull_en.q),
13488 .ds (),
13489 .qs (mio_pad_attr_9_pull_en_9_qs)
13490 );
13491 1/1 assign reg2hw.mio_pad_attr[9].pull_en.qe = mio_pad_attr_9_qe;
Tests: T9 T47 T48
13492
13493 // F[pull_select_9]: 3:3
13494 prim_subreg_ext #(
13495 .DW (1)
13496 ) u_mio_pad_attr_9_pull_select_9 (
13497 .re (mio_pad_attr_9_re),
13498 .we (mio_pad_attr_9_gated_we),
13499 .wd (mio_pad_attr_9_pull_select_9_wd),
13500 .d (hw2reg.mio_pad_attr[9].pull_select.d),
13501 .qre (),
13502 .qe (mio_pad_attr_9_flds_we[3]),
13503 .q (reg2hw.mio_pad_attr[9].pull_select.q),
13504 .ds (),
13505 .qs (mio_pad_attr_9_pull_select_9_qs)
13506 );
13507 1/1 assign reg2hw.mio_pad_attr[9].pull_select.qe = mio_pad_attr_9_qe;
Tests: T9 T47 T48
13508
13509 // F[keeper_en_9]: 4:4
13510 prim_subreg_ext #(
13511 .DW (1)
13512 ) u_mio_pad_attr_9_keeper_en_9 (
13513 .re (mio_pad_attr_9_re),
13514 .we (mio_pad_attr_9_gated_we),
13515 .wd (mio_pad_attr_9_keeper_en_9_wd),
13516 .d (hw2reg.mio_pad_attr[9].keeper_en.d),
13517 .qre (),
13518 .qe (mio_pad_attr_9_flds_we[4]),
13519 .q (reg2hw.mio_pad_attr[9].keeper_en.q),
13520 .ds (),
13521 .qs (mio_pad_attr_9_keeper_en_9_qs)
13522 );
13523 1/1 assign reg2hw.mio_pad_attr[9].keeper_en.qe = mio_pad_attr_9_qe;
Tests: T9 T47 T48
13524
13525 // F[schmitt_en_9]: 5:5
13526 prim_subreg_ext #(
13527 .DW (1)
13528 ) u_mio_pad_attr_9_schmitt_en_9 (
13529 .re (mio_pad_attr_9_re),
13530 .we (mio_pad_attr_9_gated_we),
13531 .wd (mio_pad_attr_9_schmitt_en_9_wd),
13532 .d (hw2reg.mio_pad_attr[9].schmitt_en.d),
13533 .qre (),
13534 .qe (mio_pad_attr_9_flds_we[5]),
13535 .q (reg2hw.mio_pad_attr[9].schmitt_en.q),
13536 .ds (),
13537 .qs (mio_pad_attr_9_schmitt_en_9_qs)
13538 );
13539 1/1 assign reg2hw.mio_pad_attr[9].schmitt_en.qe = mio_pad_attr_9_qe;
Tests: T9 T47 T48
13540
13541 // F[od_en_9]: 6:6
13542 prim_subreg_ext #(
13543 .DW (1)
13544 ) u_mio_pad_attr_9_od_en_9 (
13545 .re (mio_pad_attr_9_re),
13546 .we (mio_pad_attr_9_gated_we),
13547 .wd (mio_pad_attr_9_od_en_9_wd),
13548 .d (hw2reg.mio_pad_attr[9].od_en.d),
13549 .qre (),
13550 .qe (mio_pad_attr_9_flds_we[6]),
13551 .q (reg2hw.mio_pad_attr[9].od_en.q),
13552 .ds (),
13553 .qs (mio_pad_attr_9_od_en_9_qs)
13554 );
13555 1/1 assign reg2hw.mio_pad_attr[9].od_en.qe = mio_pad_attr_9_qe;
Tests: T9 T47 T48
13556
13557 // F[input_disable_9]: 7:7
13558 prim_subreg_ext #(
13559 .DW (1)
13560 ) u_mio_pad_attr_9_input_disable_9 (
13561 .re (mio_pad_attr_9_re),
13562 .we (mio_pad_attr_9_gated_we),
13563 .wd (mio_pad_attr_9_input_disable_9_wd),
13564 .d (hw2reg.mio_pad_attr[9].input_disable.d),
13565 .qre (),
13566 .qe (mio_pad_attr_9_flds_we[7]),
13567 .q (reg2hw.mio_pad_attr[9].input_disable.q),
13568 .ds (),
13569 .qs (mio_pad_attr_9_input_disable_9_qs)
13570 );
13571 1/1 assign reg2hw.mio_pad_attr[9].input_disable.qe = mio_pad_attr_9_qe;
Tests: T9 T47 T48
13572
13573 // F[slew_rate_9]: 17:16
13574 prim_subreg_ext #(
13575 .DW (2)
13576 ) u_mio_pad_attr_9_slew_rate_9 (
13577 .re (mio_pad_attr_9_re),
13578 .we (mio_pad_attr_9_gated_we),
13579 .wd (mio_pad_attr_9_slew_rate_9_wd),
13580 .d (hw2reg.mio_pad_attr[9].slew_rate.d),
13581 .qre (),
13582 .qe (mio_pad_attr_9_flds_we[8]),
13583 .q (reg2hw.mio_pad_attr[9].slew_rate.q),
13584 .ds (),
13585 .qs (mio_pad_attr_9_slew_rate_9_qs)
13586 );
13587 1/1 assign reg2hw.mio_pad_attr[9].slew_rate.qe = mio_pad_attr_9_qe;
Tests: T9 T47 T48
13588
13589 // F[drive_strength_9]: 23:20
13590 prim_subreg_ext #(
13591 .DW (4)
13592 ) u_mio_pad_attr_9_drive_strength_9 (
13593 .re (mio_pad_attr_9_re),
13594 .we (mio_pad_attr_9_gated_we),
13595 .wd (mio_pad_attr_9_drive_strength_9_wd),
13596 .d (hw2reg.mio_pad_attr[9].drive_strength.d),
13597 .qre (),
13598 .qe (mio_pad_attr_9_flds_we[9]),
13599 .q (reg2hw.mio_pad_attr[9].drive_strength.q),
13600 .ds (),
13601 .qs (mio_pad_attr_9_drive_strength_9_qs)
13602 );
13603 1/1 assign reg2hw.mio_pad_attr[9].drive_strength.qe = mio_pad_attr_9_qe;
Tests: T9 T47 T48
13604
13605
13606 // Subregister 10 of Multireg mio_pad_attr
13607 // R[mio_pad_attr_10]: V(True)
13608 logic mio_pad_attr_10_qe;
13609 logic [9:0] mio_pad_attr_10_flds_we;
13610 1/1 assign mio_pad_attr_10_qe = &mio_pad_attr_10_flds_we;
Tests: T9 T10 T11
13611 // Create REGWEN-gated WE signal
13612 logic mio_pad_attr_10_gated_we;
13613 1/1 assign mio_pad_attr_10_gated_we = mio_pad_attr_10_we & mio_pad_attr_regwen_10_qs;
Tests: T9 T10 T11
13614 // F[invert_10]: 0:0
13615 prim_subreg_ext #(
13616 .DW (1)
13617 ) u_mio_pad_attr_10_invert_10 (
13618 .re (mio_pad_attr_10_re),
13619 .we (mio_pad_attr_10_gated_we),
13620 .wd (mio_pad_attr_10_invert_10_wd),
13621 .d (hw2reg.mio_pad_attr[10].invert.d),
13622 .qre (),
13623 .qe (mio_pad_attr_10_flds_we[0]),
13624 .q (reg2hw.mio_pad_attr[10].invert.q),
13625 .ds (),
13626 .qs (mio_pad_attr_10_invert_10_qs)
13627 );
13628 1/1 assign reg2hw.mio_pad_attr[10].invert.qe = mio_pad_attr_10_qe;
Tests: T9 T10 T11
13629
13630 // F[virtual_od_en_10]: 1:1
13631 prim_subreg_ext #(
13632 .DW (1)
13633 ) u_mio_pad_attr_10_virtual_od_en_10 (
13634 .re (mio_pad_attr_10_re),
13635 .we (mio_pad_attr_10_gated_we),
13636 .wd (mio_pad_attr_10_virtual_od_en_10_wd),
13637 .d (hw2reg.mio_pad_attr[10].virtual_od_en.d),
13638 .qre (),
13639 .qe (mio_pad_attr_10_flds_we[1]),
13640 .q (reg2hw.mio_pad_attr[10].virtual_od_en.q),
13641 .ds (),
13642 .qs (mio_pad_attr_10_virtual_od_en_10_qs)
13643 );
13644 1/1 assign reg2hw.mio_pad_attr[10].virtual_od_en.qe = mio_pad_attr_10_qe;
Tests: T9 T10 T11
13645
13646 // F[pull_en_10]: 2:2
13647 prim_subreg_ext #(
13648 .DW (1)
13649 ) u_mio_pad_attr_10_pull_en_10 (
13650 .re (mio_pad_attr_10_re),
13651 .we (mio_pad_attr_10_gated_we),
13652 .wd (mio_pad_attr_10_pull_en_10_wd),
13653 .d (hw2reg.mio_pad_attr[10].pull_en.d),
13654 .qre (),
13655 .qe (mio_pad_attr_10_flds_we[2]),
13656 .q (reg2hw.mio_pad_attr[10].pull_en.q),
13657 .ds (),
13658 .qs (mio_pad_attr_10_pull_en_10_qs)
13659 );
13660 1/1 assign reg2hw.mio_pad_attr[10].pull_en.qe = mio_pad_attr_10_qe;
Tests: T9 T10 T11
13661
13662 // F[pull_select_10]: 3:3
13663 prim_subreg_ext #(
13664 .DW (1)
13665 ) u_mio_pad_attr_10_pull_select_10 (
13666 .re (mio_pad_attr_10_re),
13667 .we (mio_pad_attr_10_gated_we),
13668 .wd (mio_pad_attr_10_pull_select_10_wd),
13669 .d (hw2reg.mio_pad_attr[10].pull_select.d),
13670 .qre (),
13671 .qe (mio_pad_attr_10_flds_we[3]),
13672 .q (reg2hw.mio_pad_attr[10].pull_select.q),
13673 .ds (),
13674 .qs (mio_pad_attr_10_pull_select_10_qs)
13675 );
13676 1/1 assign reg2hw.mio_pad_attr[10].pull_select.qe = mio_pad_attr_10_qe;
Tests: T9 T10 T11
13677
13678 // F[keeper_en_10]: 4:4
13679 prim_subreg_ext #(
13680 .DW (1)
13681 ) u_mio_pad_attr_10_keeper_en_10 (
13682 .re (mio_pad_attr_10_re),
13683 .we (mio_pad_attr_10_gated_we),
13684 .wd (mio_pad_attr_10_keeper_en_10_wd),
13685 .d (hw2reg.mio_pad_attr[10].keeper_en.d),
13686 .qre (),
13687 .qe (mio_pad_attr_10_flds_we[4]),
13688 .q (reg2hw.mio_pad_attr[10].keeper_en.q),
13689 .ds (),
13690 .qs (mio_pad_attr_10_keeper_en_10_qs)
13691 );
13692 1/1 assign reg2hw.mio_pad_attr[10].keeper_en.qe = mio_pad_attr_10_qe;
Tests: T9 T10 T11
13693
13694 // F[schmitt_en_10]: 5:5
13695 prim_subreg_ext #(
13696 .DW (1)
13697 ) u_mio_pad_attr_10_schmitt_en_10 (
13698 .re (mio_pad_attr_10_re),
13699 .we (mio_pad_attr_10_gated_we),
13700 .wd (mio_pad_attr_10_schmitt_en_10_wd),
13701 .d (hw2reg.mio_pad_attr[10].schmitt_en.d),
13702 .qre (),
13703 .qe (mio_pad_attr_10_flds_we[5]),
13704 .q (reg2hw.mio_pad_attr[10].schmitt_en.q),
13705 .ds (),
13706 .qs (mio_pad_attr_10_schmitt_en_10_qs)
13707 );
13708 1/1 assign reg2hw.mio_pad_attr[10].schmitt_en.qe = mio_pad_attr_10_qe;
Tests: T9 T10 T11
13709
13710 // F[od_en_10]: 6:6
13711 prim_subreg_ext #(
13712 .DW (1)
13713 ) u_mio_pad_attr_10_od_en_10 (
13714 .re (mio_pad_attr_10_re),
13715 .we (mio_pad_attr_10_gated_we),
13716 .wd (mio_pad_attr_10_od_en_10_wd),
13717 .d (hw2reg.mio_pad_attr[10].od_en.d),
13718 .qre (),
13719 .qe (mio_pad_attr_10_flds_we[6]),
13720 .q (reg2hw.mio_pad_attr[10].od_en.q),
13721 .ds (),
13722 .qs (mio_pad_attr_10_od_en_10_qs)
13723 );
13724 1/1 assign reg2hw.mio_pad_attr[10].od_en.qe = mio_pad_attr_10_qe;
Tests: T9 T10 T11
13725
13726 // F[input_disable_10]: 7:7
13727 prim_subreg_ext #(
13728 .DW (1)
13729 ) u_mio_pad_attr_10_input_disable_10 (
13730 .re (mio_pad_attr_10_re),
13731 .we (mio_pad_attr_10_gated_we),
13732 .wd (mio_pad_attr_10_input_disable_10_wd),
13733 .d (hw2reg.mio_pad_attr[10].input_disable.d),
13734 .qre (),
13735 .qe (mio_pad_attr_10_flds_we[7]),
13736 .q (reg2hw.mio_pad_attr[10].input_disable.q),
13737 .ds (),
13738 .qs (mio_pad_attr_10_input_disable_10_qs)
13739 );
13740 1/1 assign reg2hw.mio_pad_attr[10].input_disable.qe = mio_pad_attr_10_qe;
Tests: T9 T10 T11
13741
13742 // F[slew_rate_10]: 17:16
13743 prim_subreg_ext #(
13744 .DW (2)
13745 ) u_mio_pad_attr_10_slew_rate_10 (
13746 .re (mio_pad_attr_10_re),
13747 .we (mio_pad_attr_10_gated_we),
13748 .wd (mio_pad_attr_10_slew_rate_10_wd),
13749 .d (hw2reg.mio_pad_attr[10].slew_rate.d),
13750 .qre (),
13751 .qe (mio_pad_attr_10_flds_we[8]),
13752 .q (reg2hw.mio_pad_attr[10].slew_rate.q),
13753 .ds (),
13754 .qs (mio_pad_attr_10_slew_rate_10_qs)
13755 );
13756 1/1 assign reg2hw.mio_pad_attr[10].slew_rate.qe = mio_pad_attr_10_qe;
Tests: T9 T10 T11
13757
13758 // F[drive_strength_10]: 23:20
13759 prim_subreg_ext #(
13760 .DW (4)
13761 ) u_mio_pad_attr_10_drive_strength_10 (
13762 .re (mio_pad_attr_10_re),
13763 .we (mio_pad_attr_10_gated_we),
13764 .wd (mio_pad_attr_10_drive_strength_10_wd),
13765 .d (hw2reg.mio_pad_attr[10].drive_strength.d),
13766 .qre (),
13767 .qe (mio_pad_attr_10_flds_we[9]),
13768 .q (reg2hw.mio_pad_attr[10].drive_strength.q),
13769 .ds (),
13770 .qs (mio_pad_attr_10_drive_strength_10_qs)
13771 );
13772 1/1 assign reg2hw.mio_pad_attr[10].drive_strength.qe = mio_pad_attr_10_qe;
Tests: T9 T10 T11
13773
13774
13775 // Subregister 11 of Multireg mio_pad_attr
13776 // R[mio_pad_attr_11]: V(True)
13777 logic mio_pad_attr_11_qe;
13778 logic [9:0] mio_pad_attr_11_flds_we;
13779 1/1 assign mio_pad_attr_11_qe = &mio_pad_attr_11_flds_we;
Tests: T96 T97 T98
13780 // Create REGWEN-gated WE signal
13781 logic mio_pad_attr_11_gated_we;
13782 1/1 assign mio_pad_attr_11_gated_we = mio_pad_attr_11_we & mio_pad_attr_regwen_11_qs;
Tests: T71 T96 T97
13783 // F[invert_11]: 0:0
13784 prim_subreg_ext #(
13785 .DW (1)
13786 ) u_mio_pad_attr_11_invert_11 (
13787 .re (mio_pad_attr_11_re),
13788 .we (mio_pad_attr_11_gated_we),
13789 .wd (mio_pad_attr_11_invert_11_wd),
13790 .d (hw2reg.mio_pad_attr[11].invert.d),
13791 .qre (),
13792 .qe (mio_pad_attr_11_flds_we[0]),
13793 .q (reg2hw.mio_pad_attr[11].invert.q),
13794 .ds (),
13795 .qs (mio_pad_attr_11_invert_11_qs)
13796 );
13797 1/1 assign reg2hw.mio_pad_attr[11].invert.qe = mio_pad_attr_11_qe;
Tests: T96 T97 T98
13798
13799 // F[virtual_od_en_11]: 1:1
13800 prim_subreg_ext #(
13801 .DW (1)
13802 ) u_mio_pad_attr_11_virtual_od_en_11 (
13803 .re (mio_pad_attr_11_re),
13804 .we (mio_pad_attr_11_gated_we),
13805 .wd (mio_pad_attr_11_virtual_od_en_11_wd),
13806 .d (hw2reg.mio_pad_attr[11].virtual_od_en.d),
13807 .qre (),
13808 .qe (mio_pad_attr_11_flds_we[1]),
13809 .q (reg2hw.mio_pad_attr[11].virtual_od_en.q),
13810 .ds (),
13811 .qs (mio_pad_attr_11_virtual_od_en_11_qs)
13812 );
13813 1/1 assign reg2hw.mio_pad_attr[11].virtual_od_en.qe = mio_pad_attr_11_qe;
Tests: T96 T97 T98
13814
13815 // F[pull_en_11]: 2:2
13816 prim_subreg_ext #(
13817 .DW (1)
13818 ) u_mio_pad_attr_11_pull_en_11 (
13819 .re (mio_pad_attr_11_re),
13820 .we (mio_pad_attr_11_gated_we),
13821 .wd (mio_pad_attr_11_pull_en_11_wd),
13822 .d (hw2reg.mio_pad_attr[11].pull_en.d),
13823 .qre (),
13824 .qe (mio_pad_attr_11_flds_we[2]),
13825 .q (reg2hw.mio_pad_attr[11].pull_en.q),
13826 .ds (),
13827 .qs (mio_pad_attr_11_pull_en_11_qs)
13828 );
13829 1/1 assign reg2hw.mio_pad_attr[11].pull_en.qe = mio_pad_attr_11_qe;
Tests: T96 T97 T98
13830
13831 // F[pull_select_11]: 3:3
13832 prim_subreg_ext #(
13833 .DW (1)
13834 ) u_mio_pad_attr_11_pull_select_11 (
13835 .re (mio_pad_attr_11_re),
13836 .we (mio_pad_attr_11_gated_we),
13837 .wd (mio_pad_attr_11_pull_select_11_wd),
13838 .d (hw2reg.mio_pad_attr[11].pull_select.d),
13839 .qre (),
13840 .qe (mio_pad_attr_11_flds_we[3]),
13841 .q (reg2hw.mio_pad_attr[11].pull_select.q),
13842 .ds (),
13843 .qs (mio_pad_attr_11_pull_select_11_qs)
13844 );
13845 1/1 assign reg2hw.mio_pad_attr[11].pull_select.qe = mio_pad_attr_11_qe;
Tests: T96 T97 T98
13846
13847 // F[keeper_en_11]: 4:4
13848 prim_subreg_ext #(
13849 .DW (1)
13850 ) u_mio_pad_attr_11_keeper_en_11 (
13851 .re (mio_pad_attr_11_re),
13852 .we (mio_pad_attr_11_gated_we),
13853 .wd (mio_pad_attr_11_keeper_en_11_wd),
13854 .d (hw2reg.mio_pad_attr[11].keeper_en.d),
13855 .qre (),
13856 .qe (mio_pad_attr_11_flds_we[4]),
13857 .q (reg2hw.mio_pad_attr[11].keeper_en.q),
13858 .ds (),
13859 .qs (mio_pad_attr_11_keeper_en_11_qs)
13860 );
13861 1/1 assign reg2hw.mio_pad_attr[11].keeper_en.qe = mio_pad_attr_11_qe;
Tests: T96 T97 T98
13862
13863 // F[schmitt_en_11]: 5:5
13864 prim_subreg_ext #(
13865 .DW (1)
13866 ) u_mio_pad_attr_11_schmitt_en_11 (
13867 .re (mio_pad_attr_11_re),
13868 .we (mio_pad_attr_11_gated_we),
13869 .wd (mio_pad_attr_11_schmitt_en_11_wd),
13870 .d (hw2reg.mio_pad_attr[11].schmitt_en.d),
13871 .qre (),
13872 .qe (mio_pad_attr_11_flds_we[5]),
13873 .q (reg2hw.mio_pad_attr[11].schmitt_en.q),
13874 .ds (),
13875 .qs (mio_pad_attr_11_schmitt_en_11_qs)
13876 );
13877 1/1 assign reg2hw.mio_pad_attr[11].schmitt_en.qe = mio_pad_attr_11_qe;
Tests: T96 T97 T98
13878
13879 // F[od_en_11]: 6:6
13880 prim_subreg_ext #(
13881 .DW (1)
13882 ) u_mio_pad_attr_11_od_en_11 (
13883 .re (mio_pad_attr_11_re),
13884 .we (mio_pad_attr_11_gated_we),
13885 .wd (mio_pad_attr_11_od_en_11_wd),
13886 .d (hw2reg.mio_pad_attr[11].od_en.d),
13887 .qre (),
13888 .qe (mio_pad_attr_11_flds_we[6]),
13889 .q (reg2hw.mio_pad_attr[11].od_en.q),
13890 .ds (),
13891 .qs (mio_pad_attr_11_od_en_11_qs)
13892 );
13893 1/1 assign reg2hw.mio_pad_attr[11].od_en.qe = mio_pad_attr_11_qe;
Tests: T96 T97 T98
13894
13895 // F[input_disable_11]: 7:7
13896 prim_subreg_ext #(
13897 .DW (1)
13898 ) u_mio_pad_attr_11_input_disable_11 (
13899 .re (mio_pad_attr_11_re),
13900 .we (mio_pad_attr_11_gated_we),
13901 .wd (mio_pad_attr_11_input_disable_11_wd),
13902 .d (hw2reg.mio_pad_attr[11].input_disable.d),
13903 .qre (),
13904 .qe (mio_pad_attr_11_flds_we[7]),
13905 .q (reg2hw.mio_pad_attr[11].input_disable.q),
13906 .ds (),
13907 .qs (mio_pad_attr_11_input_disable_11_qs)
13908 );
13909 1/1 assign reg2hw.mio_pad_attr[11].input_disable.qe = mio_pad_attr_11_qe;
Tests: T96 T97 T98
13910
13911 // F[slew_rate_11]: 17:16
13912 prim_subreg_ext #(
13913 .DW (2)
13914 ) u_mio_pad_attr_11_slew_rate_11 (
13915 .re (mio_pad_attr_11_re),
13916 .we (mio_pad_attr_11_gated_we),
13917 .wd (mio_pad_attr_11_slew_rate_11_wd),
13918 .d (hw2reg.mio_pad_attr[11].slew_rate.d),
13919 .qre (),
13920 .qe (mio_pad_attr_11_flds_we[8]),
13921 .q (reg2hw.mio_pad_attr[11].slew_rate.q),
13922 .ds (),
13923 .qs (mio_pad_attr_11_slew_rate_11_qs)
13924 );
13925 1/1 assign reg2hw.mio_pad_attr[11].slew_rate.qe = mio_pad_attr_11_qe;
Tests: T96 T97 T98
13926
13927 // F[drive_strength_11]: 23:20
13928 prim_subreg_ext #(
13929 .DW (4)
13930 ) u_mio_pad_attr_11_drive_strength_11 (
13931 .re (mio_pad_attr_11_re),
13932 .we (mio_pad_attr_11_gated_we),
13933 .wd (mio_pad_attr_11_drive_strength_11_wd),
13934 .d (hw2reg.mio_pad_attr[11].drive_strength.d),
13935 .qre (),
13936 .qe (mio_pad_attr_11_flds_we[9]),
13937 .q (reg2hw.mio_pad_attr[11].drive_strength.q),
13938 .ds (),
13939 .qs (mio_pad_attr_11_drive_strength_11_qs)
13940 );
13941 1/1 assign reg2hw.mio_pad_attr[11].drive_strength.qe = mio_pad_attr_11_qe;
Tests: T96 T97 T98
13942
13943
13944 // Subregister 12 of Multireg mio_pad_attr
13945 // R[mio_pad_attr_12]: V(True)
13946 logic mio_pad_attr_12_qe;
13947 logic [9:0] mio_pad_attr_12_flds_we;
13948 1/1 assign mio_pad_attr_12_qe = &mio_pad_attr_12_flds_we;
Tests: T9 T10 T11
13949 // Create REGWEN-gated WE signal
13950 logic mio_pad_attr_12_gated_we;
13951 1/1 assign mio_pad_attr_12_gated_we = mio_pad_attr_12_we & mio_pad_attr_regwen_12_qs;
Tests: T9 T10 T11
13952 // F[invert_12]: 0:0
13953 prim_subreg_ext #(
13954 .DW (1)
13955 ) u_mio_pad_attr_12_invert_12 (
13956 .re (mio_pad_attr_12_re),
13957 .we (mio_pad_attr_12_gated_we),
13958 .wd (mio_pad_attr_12_invert_12_wd),
13959 .d (hw2reg.mio_pad_attr[12].invert.d),
13960 .qre (),
13961 .qe (mio_pad_attr_12_flds_we[0]),
13962 .q (reg2hw.mio_pad_attr[12].invert.q),
13963 .ds (),
13964 .qs (mio_pad_attr_12_invert_12_qs)
13965 );
13966 1/1 assign reg2hw.mio_pad_attr[12].invert.qe = mio_pad_attr_12_qe;
Tests: T9 T10 T11
13967
13968 // F[virtual_od_en_12]: 1:1
13969 prim_subreg_ext #(
13970 .DW (1)
13971 ) u_mio_pad_attr_12_virtual_od_en_12 (
13972 .re (mio_pad_attr_12_re),
13973 .we (mio_pad_attr_12_gated_we),
13974 .wd (mio_pad_attr_12_virtual_od_en_12_wd),
13975 .d (hw2reg.mio_pad_attr[12].virtual_od_en.d),
13976 .qre (),
13977 .qe (mio_pad_attr_12_flds_we[1]),
13978 .q (reg2hw.mio_pad_attr[12].virtual_od_en.q),
13979 .ds (),
13980 .qs (mio_pad_attr_12_virtual_od_en_12_qs)
13981 );
13982 1/1 assign reg2hw.mio_pad_attr[12].virtual_od_en.qe = mio_pad_attr_12_qe;
Tests: T9 T10 T11
13983
13984 // F[pull_en_12]: 2:2
13985 prim_subreg_ext #(
13986 .DW (1)
13987 ) u_mio_pad_attr_12_pull_en_12 (
13988 .re (mio_pad_attr_12_re),
13989 .we (mio_pad_attr_12_gated_we),
13990 .wd (mio_pad_attr_12_pull_en_12_wd),
13991 .d (hw2reg.mio_pad_attr[12].pull_en.d),
13992 .qre (),
13993 .qe (mio_pad_attr_12_flds_we[2]),
13994 .q (reg2hw.mio_pad_attr[12].pull_en.q),
13995 .ds (),
13996 .qs (mio_pad_attr_12_pull_en_12_qs)
13997 );
13998 1/1 assign reg2hw.mio_pad_attr[12].pull_en.qe = mio_pad_attr_12_qe;
Tests: T9 T10 T11
13999
14000 // F[pull_select_12]: 3:3
14001 prim_subreg_ext #(
14002 .DW (1)
14003 ) u_mio_pad_attr_12_pull_select_12 (
14004 .re (mio_pad_attr_12_re),
14005 .we (mio_pad_attr_12_gated_we),
14006 .wd (mio_pad_attr_12_pull_select_12_wd),
14007 .d (hw2reg.mio_pad_attr[12].pull_select.d),
14008 .qre (),
14009 .qe (mio_pad_attr_12_flds_we[3]),
14010 .q (reg2hw.mio_pad_attr[12].pull_select.q),
14011 .ds (),
14012 .qs (mio_pad_attr_12_pull_select_12_qs)
14013 );
14014 1/1 assign reg2hw.mio_pad_attr[12].pull_select.qe = mio_pad_attr_12_qe;
Tests: T9 T10 T11
14015
14016 // F[keeper_en_12]: 4:4
14017 prim_subreg_ext #(
14018 .DW (1)
14019 ) u_mio_pad_attr_12_keeper_en_12 (
14020 .re (mio_pad_attr_12_re),
14021 .we (mio_pad_attr_12_gated_we),
14022 .wd (mio_pad_attr_12_keeper_en_12_wd),
14023 .d (hw2reg.mio_pad_attr[12].keeper_en.d),
14024 .qre (),
14025 .qe (mio_pad_attr_12_flds_we[4]),
14026 .q (reg2hw.mio_pad_attr[12].keeper_en.q),
14027 .ds (),
14028 .qs (mio_pad_attr_12_keeper_en_12_qs)
14029 );
14030 1/1 assign reg2hw.mio_pad_attr[12].keeper_en.qe = mio_pad_attr_12_qe;
Tests: T9 T10 T11
14031
14032 // F[schmitt_en_12]: 5:5
14033 prim_subreg_ext #(
14034 .DW (1)
14035 ) u_mio_pad_attr_12_schmitt_en_12 (
14036 .re (mio_pad_attr_12_re),
14037 .we (mio_pad_attr_12_gated_we),
14038 .wd (mio_pad_attr_12_schmitt_en_12_wd),
14039 .d (hw2reg.mio_pad_attr[12].schmitt_en.d),
14040 .qre (),
14041 .qe (mio_pad_attr_12_flds_we[5]),
14042 .q (reg2hw.mio_pad_attr[12].schmitt_en.q),
14043 .ds (),
14044 .qs (mio_pad_attr_12_schmitt_en_12_qs)
14045 );
14046 1/1 assign reg2hw.mio_pad_attr[12].schmitt_en.qe = mio_pad_attr_12_qe;
Tests: T9 T10 T11
14047
14048 // F[od_en_12]: 6:6
14049 prim_subreg_ext #(
14050 .DW (1)
14051 ) u_mio_pad_attr_12_od_en_12 (
14052 .re (mio_pad_attr_12_re),
14053 .we (mio_pad_attr_12_gated_we),
14054 .wd (mio_pad_attr_12_od_en_12_wd),
14055 .d (hw2reg.mio_pad_attr[12].od_en.d),
14056 .qre (),
14057 .qe (mio_pad_attr_12_flds_we[6]),
14058 .q (reg2hw.mio_pad_attr[12].od_en.q),
14059 .ds (),
14060 .qs (mio_pad_attr_12_od_en_12_qs)
14061 );
14062 1/1 assign reg2hw.mio_pad_attr[12].od_en.qe = mio_pad_attr_12_qe;
Tests: T9 T10 T11
14063
14064 // F[input_disable_12]: 7:7
14065 prim_subreg_ext #(
14066 .DW (1)
14067 ) u_mio_pad_attr_12_input_disable_12 (
14068 .re (mio_pad_attr_12_re),
14069 .we (mio_pad_attr_12_gated_we),
14070 .wd (mio_pad_attr_12_input_disable_12_wd),
14071 .d (hw2reg.mio_pad_attr[12].input_disable.d),
14072 .qre (),
14073 .qe (mio_pad_attr_12_flds_we[7]),
14074 .q (reg2hw.mio_pad_attr[12].input_disable.q),
14075 .ds (),
14076 .qs (mio_pad_attr_12_input_disable_12_qs)
14077 );
14078 1/1 assign reg2hw.mio_pad_attr[12].input_disable.qe = mio_pad_attr_12_qe;
Tests: T9 T10 T11
14079
14080 // F[slew_rate_12]: 17:16
14081 prim_subreg_ext #(
14082 .DW (2)
14083 ) u_mio_pad_attr_12_slew_rate_12 (
14084 .re (mio_pad_attr_12_re),
14085 .we (mio_pad_attr_12_gated_we),
14086 .wd (mio_pad_attr_12_slew_rate_12_wd),
14087 .d (hw2reg.mio_pad_attr[12].slew_rate.d),
14088 .qre (),
14089 .qe (mio_pad_attr_12_flds_we[8]),
14090 .q (reg2hw.mio_pad_attr[12].slew_rate.q),
14091 .ds (),
14092 .qs (mio_pad_attr_12_slew_rate_12_qs)
14093 );
14094 1/1 assign reg2hw.mio_pad_attr[12].slew_rate.qe = mio_pad_attr_12_qe;
Tests: T9 T10 T11
14095
14096 // F[drive_strength_12]: 23:20
14097 prim_subreg_ext #(
14098 .DW (4)
14099 ) u_mio_pad_attr_12_drive_strength_12 (
14100 .re (mio_pad_attr_12_re),
14101 .we (mio_pad_attr_12_gated_we),
14102 .wd (mio_pad_attr_12_drive_strength_12_wd),
14103 .d (hw2reg.mio_pad_attr[12].drive_strength.d),
14104 .qre (),
14105 .qe (mio_pad_attr_12_flds_we[9]),
14106 .q (reg2hw.mio_pad_attr[12].drive_strength.q),
14107 .ds (),
14108 .qs (mio_pad_attr_12_drive_strength_12_qs)
14109 );
14110 1/1 assign reg2hw.mio_pad_attr[12].drive_strength.qe = mio_pad_attr_12_qe;
Tests: T9 T10 T11
14111
14112
14113 // Subregister 13 of Multireg mio_pad_attr
14114 // R[mio_pad_attr_13]: V(True)
14115 logic mio_pad_attr_13_qe;
14116 logic [9:0] mio_pad_attr_13_flds_we;
14117 1/1 assign mio_pad_attr_13_qe = &mio_pad_attr_13_flds_we;
Tests: T9 T37 T47
14118 // Create REGWEN-gated WE signal
14119 logic mio_pad_attr_13_gated_we;
14120 1/1 assign mio_pad_attr_13_gated_we = mio_pad_attr_13_we & mio_pad_attr_regwen_13_qs;
Tests: T9 T37 T47
14121 // F[invert_13]: 0:0
14122 prim_subreg_ext #(
14123 .DW (1)
14124 ) u_mio_pad_attr_13_invert_13 (
14125 .re (mio_pad_attr_13_re),
14126 .we (mio_pad_attr_13_gated_we),
14127 .wd (mio_pad_attr_13_invert_13_wd),
14128 .d (hw2reg.mio_pad_attr[13].invert.d),
14129 .qre (),
14130 .qe (mio_pad_attr_13_flds_we[0]),
14131 .q (reg2hw.mio_pad_attr[13].invert.q),
14132 .ds (),
14133 .qs (mio_pad_attr_13_invert_13_qs)
14134 );
14135 1/1 assign reg2hw.mio_pad_attr[13].invert.qe = mio_pad_attr_13_qe;
Tests: T9 T37 T47
14136
14137 // F[virtual_od_en_13]: 1:1
14138 prim_subreg_ext #(
14139 .DW (1)
14140 ) u_mio_pad_attr_13_virtual_od_en_13 (
14141 .re (mio_pad_attr_13_re),
14142 .we (mio_pad_attr_13_gated_we),
14143 .wd (mio_pad_attr_13_virtual_od_en_13_wd),
14144 .d (hw2reg.mio_pad_attr[13].virtual_od_en.d),
14145 .qre (),
14146 .qe (mio_pad_attr_13_flds_we[1]),
14147 .q (reg2hw.mio_pad_attr[13].virtual_od_en.q),
14148 .ds (),
14149 .qs (mio_pad_attr_13_virtual_od_en_13_qs)
14150 );
14151 1/1 assign reg2hw.mio_pad_attr[13].virtual_od_en.qe = mio_pad_attr_13_qe;
Tests: T9 T37 T47
14152
14153 // F[pull_en_13]: 2:2
14154 prim_subreg_ext #(
14155 .DW (1)
14156 ) u_mio_pad_attr_13_pull_en_13 (
14157 .re (mio_pad_attr_13_re),
14158 .we (mio_pad_attr_13_gated_we),
14159 .wd (mio_pad_attr_13_pull_en_13_wd),
14160 .d (hw2reg.mio_pad_attr[13].pull_en.d),
14161 .qre (),
14162 .qe (mio_pad_attr_13_flds_we[2]),
14163 .q (reg2hw.mio_pad_attr[13].pull_en.q),
14164 .ds (),
14165 .qs (mio_pad_attr_13_pull_en_13_qs)
14166 );
14167 1/1 assign reg2hw.mio_pad_attr[13].pull_en.qe = mio_pad_attr_13_qe;
Tests: T9 T37 T47
14168
14169 // F[pull_select_13]: 3:3
14170 prim_subreg_ext #(
14171 .DW (1)
14172 ) u_mio_pad_attr_13_pull_select_13 (
14173 .re (mio_pad_attr_13_re),
14174 .we (mio_pad_attr_13_gated_we),
14175 .wd (mio_pad_attr_13_pull_select_13_wd),
14176 .d (hw2reg.mio_pad_attr[13].pull_select.d),
14177 .qre (),
14178 .qe (mio_pad_attr_13_flds_we[3]),
14179 .q (reg2hw.mio_pad_attr[13].pull_select.q),
14180 .ds (),
14181 .qs (mio_pad_attr_13_pull_select_13_qs)
14182 );
14183 1/1 assign reg2hw.mio_pad_attr[13].pull_select.qe = mio_pad_attr_13_qe;
Tests: T9 T37 T47
14184
14185 // F[keeper_en_13]: 4:4
14186 prim_subreg_ext #(
14187 .DW (1)
14188 ) u_mio_pad_attr_13_keeper_en_13 (
14189 .re (mio_pad_attr_13_re),
14190 .we (mio_pad_attr_13_gated_we),
14191 .wd (mio_pad_attr_13_keeper_en_13_wd),
14192 .d (hw2reg.mio_pad_attr[13].keeper_en.d),
14193 .qre (),
14194 .qe (mio_pad_attr_13_flds_we[4]),
14195 .q (reg2hw.mio_pad_attr[13].keeper_en.q),
14196 .ds (),
14197 .qs (mio_pad_attr_13_keeper_en_13_qs)
14198 );
14199 1/1 assign reg2hw.mio_pad_attr[13].keeper_en.qe = mio_pad_attr_13_qe;
Tests: T9 T37 T47
14200
14201 // F[schmitt_en_13]: 5:5
14202 prim_subreg_ext #(
14203 .DW (1)
14204 ) u_mio_pad_attr_13_schmitt_en_13 (
14205 .re (mio_pad_attr_13_re),
14206 .we (mio_pad_attr_13_gated_we),
14207 .wd (mio_pad_attr_13_schmitt_en_13_wd),
14208 .d (hw2reg.mio_pad_attr[13].schmitt_en.d),
14209 .qre (),
14210 .qe (mio_pad_attr_13_flds_we[5]),
14211 .q (reg2hw.mio_pad_attr[13].schmitt_en.q),
14212 .ds (),
14213 .qs (mio_pad_attr_13_schmitt_en_13_qs)
14214 );
14215 1/1 assign reg2hw.mio_pad_attr[13].schmitt_en.qe = mio_pad_attr_13_qe;
Tests: T9 T37 T47
14216
14217 // F[od_en_13]: 6:6
14218 prim_subreg_ext #(
14219 .DW (1)
14220 ) u_mio_pad_attr_13_od_en_13 (
14221 .re (mio_pad_attr_13_re),
14222 .we (mio_pad_attr_13_gated_we),
14223 .wd (mio_pad_attr_13_od_en_13_wd),
14224 .d (hw2reg.mio_pad_attr[13].od_en.d),
14225 .qre (),
14226 .qe (mio_pad_attr_13_flds_we[6]),
14227 .q (reg2hw.mio_pad_attr[13].od_en.q),
14228 .ds (),
14229 .qs (mio_pad_attr_13_od_en_13_qs)
14230 );
14231 1/1 assign reg2hw.mio_pad_attr[13].od_en.qe = mio_pad_attr_13_qe;
Tests: T9 T37 T47
14232
14233 // F[input_disable_13]: 7:7
14234 prim_subreg_ext #(
14235 .DW (1)
14236 ) u_mio_pad_attr_13_input_disable_13 (
14237 .re (mio_pad_attr_13_re),
14238 .we (mio_pad_attr_13_gated_we),
14239 .wd (mio_pad_attr_13_input_disable_13_wd),
14240 .d (hw2reg.mio_pad_attr[13].input_disable.d),
14241 .qre (),
14242 .qe (mio_pad_attr_13_flds_we[7]),
14243 .q (reg2hw.mio_pad_attr[13].input_disable.q),
14244 .ds (),
14245 .qs (mio_pad_attr_13_input_disable_13_qs)
14246 );
14247 1/1 assign reg2hw.mio_pad_attr[13].input_disable.qe = mio_pad_attr_13_qe;
Tests: T9 T37 T47
14248
14249 // F[slew_rate_13]: 17:16
14250 prim_subreg_ext #(
14251 .DW (2)
14252 ) u_mio_pad_attr_13_slew_rate_13 (
14253 .re (mio_pad_attr_13_re),
14254 .we (mio_pad_attr_13_gated_we),
14255 .wd (mio_pad_attr_13_slew_rate_13_wd),
14256 .d (hw2reg.mio_pad_attr[13].slew_rate.d),
14257 .qre (),
14258 .qe (mio_pad_attr_13_flds_we[8]),
14259 .q (reg2hw.mio_pad_attr[13].slew_rate.q),
14260 .ds (),
14261 .qs (mio_pad_attr_13_slew_rate_13_qs)
14262 );
14263 1/1 assign reg2hw.mio_pad_attr[13].slew_rate.qe = mio_pad_attr_13_qe;
Tests: T9 T37 T47
14264
14265 // F[drive_strength_13]: 23:20
14266 prim_subreg_ext #(
14267 .DW (4)
14268 ) u_mio_pad_attr_13_drive_strength_13 (
14269 .re (mio_pad_attr_13_re),
14270 .we (mio_pad_attr_13_gated_we),
14271 .wd (mio_pad_attr_13_drive_strength_13_wd),
14272 .d (hw2reg.mio_pad_attr[13].drive_strength.d),
14273 .qre (),
14274 .qe (mio_pad_attr_13_flds_we[9]),
14275 .q (reg2hw.mio_pad_attr[13].drive_strength.q),
14276 .ds (),
14277 .qs (mio_pad_attr_13_drive_strength_13_qs)
14278 );
14279 1/1 assign reg2hw.mio_pad_attr[13].drive_strength.qe = mio_pad_attr_13_qe;
Tests: T9 T37 T47
14280
14281
14282 // Subregister 14 of Multireg mio_pad_attr
14283 // R[mio_pad_attr_14]: V(True)
14284 logic mio_pad_attr_14_qe;
14285 logic [9:0] mio_pad_attr_14_flds_we;
14286 1/1 assign mio_pad_attr_14_qe = &mio_pad_attr_14_flds_we;
Tests: T9 T37 T47
14287 // Create REGWEN-gated WE signal
14288 logic mio_pad_attr_14_gated_we;
14289 1/1 assign mio_pad_attr_14_gated_we = mio_pad_attr_14_we & mio_pad_attr_regwen_14_qs;
Tests: T9 T37 T47
14290 // F[invert_14]: 0:0
14291 prim_subreg_ext #(
14292 .DW (1)
14293 ) u_mio_pad_attr_14_invert_14 (
14294 .re (mio_pad_attr_14_re),
14295 .we (mio_pad_attr_14_gated_we),
14296 .wd (mio_pad_attr_14_invert_14_wd),
14297 .d (hw2reg.mio_pad_attr[14].invert.d),
14298 .qre (),
14299 .qe (mio_pad_attr_14_flds_we[0]),
14300 .q (reg2hw.mio_pad_attr[14].invert.q),
14301 .ds (),
14302 .qs (mio_pad_attr_14_invert_14_qs)
14303 );
14304 1/1 assign reg2hw.mio_pad_attr[14].invert.qe = mio_pad_attr_14_qe;
Tests: T9 T37 T47
14305
14306 // F[virtual_od_en_14]: 1:1
14307 prim_subreg_ext #(
14308 .DW (1)
14309 ) u_mio_pad_attr_14_virtual_od_en_14 (
14310 .re (mio_pad_attr_14_re),
14311 .we (mio_pad_attr_14_gated_we),
14312 .wd (mio_pad_attr_14_virtual_od_en_14_wd),
14313 .d (hw2reg.mio_pad_attr[14].virtual_od_en.d),
14314 .qre (),
14315 .qe (mio_pad_attr_14_flds_we[1]),
14316 .q (reg2hw.mio_pad_attr[14].virtual_od_en.q),
14317 .ds (),
14318 .qs (mio_pad_attr_14_virtual_od_en_14_qs)
14319 );
14320 1/1 assign reg2hw.mio_pad_attr[14].virtual_od_en.qe = mio_pad_attr_14_qe;
Tests: T9 T37 T47
14321
14322 // F[pull_en_14]: 2:2
14323 prim_subreg_ext #(
14324 .DW (1)
14325 ) u_mio_pad_attr_14_pull_en_14 (
14326 .re (mio_pad_attr_14_re),
14327 .we (mio_pad_attr_14_gated_we),
14328 .wd (mio_pad_attr_14_pull_en_14_wd),
14329 .d (hw2reg.mio_pad_attr[14].pull_en.d),
14330 .qre (),
14331 .qe (mio_pad_attr_14_flds_we[2]),
14332 .q (reg2hw.mio_pad_attr[14].pull_en.q),
14333 .ds (),
14334 .qs (mio_pad_attr_14_pull_en_14_qs)
14335 );
14336 1/1 assign reg2hw.mio_pad_attr[14].pull_en.qe = mio_pad_attr_14_qe;
Tests: T9 T37 T47
14337
14338 // F[pull_select_14]: 3:3
14339 prim_subreg_ext #(
14340 .DW (1)
14341 ) u_mio_pad_attr_14_pull_select_14 (
14342 .re (mio_pad_attr_14_re),
14343 .we (mio_pad_attr_14_gated_we),
14344 .wd (mio_pad_attr_14_pull_select_14_wd),
14345 .d (hw2reg.mio_pad_attr[14].pull_select.d),
14346 .qre (),
14347 .qe (mio_pad_attr_14_flds_we[3]),
14348 .q (reg2hw.mio_pad_attr[14].pull_select.q),
14349 .ds (),
14350 .qs (mio_pad_attr_14_pull_select_14_qs)
14351 );
14352 1/1 assign reg2hw.mio_pad_attr[14].pull_select.qe = mio_pad_attr_14_qe;
Tests: T9 T37 T47
14353
14354 // F[keeper_en_14]: 4:4
14355 prim_subreg_ext #(
14356 .DW (1)
14357 ) u_mio_pad_attr_14_keeper_en_14 (
14358 .re (mio_pad_attr_14_re),
14359 .we (mio_pad_attr_14_gated_we),
14360 .wd (mio_pad_attr_14_keeper_en_14_wd),
14361 .d (hw2reg.mio_pad_attr[14].keeper_en.d),
14362 .qre (),
14363 .qe (mio_pad_attr_14_flds_we[4]),
14364 .q (reg2hw.mio_pad_attr[14].keeper_en.q),
14365 .ds (),
14366 .qs (mio_pad_attr_14_keeper_en_14_qs)
14367 );
14368 1/1 assign reg2hw.mio_pad_attr[14].keeper_en.qe = mio_pad_attr_14_qe;
Tests: T9 T37 T47
14369
14370 // F[schmitt_en_14]: 5:5
14371 prim_subreg_ext #(
14372 .DW (1)
14373 ) u_mio_pad_attr_14_schmitt_en_14 (
14374 .re (mio_pad_attr_14_re),
14375 .we (mio_pad_attr_14_gated_we),
14376 .wd (mio_pad_attr_14_schmitt_en_14_wd),
14377 .d (hw2reg.mio_pad_attr[14].schmitt_en.d),
14378 .qre (),
14379 .qe (mio_pad_attr_14_flds_we[5]),
14380 .q (reg2hw.mio_pad_attr[14].schmitt_en.q),
14381 .ds (),
14382 .qs (mio_pad_attr_14_schmitt_en_14_qs)
14383 );
14384 1/1 assign reg2hw.mio_pad_attr[14].schmitt_en.qe = mio_pad_attr_14_qe;
Tests: T9 T37 T47
14385
14386 // F[od_en_14]: 6:6
14387 prim_subreg_ext #(
14388 .DW (1)
14389 ) u_mio_pad_attr_14_od_en_14 (
14390 .re (mio_pad_attr_14_re),
14391 .we (mio_pad_attr_14_gated_we),
14392 .wd (mio_pad_attr_14_od_en_14_wd),
14393 .d (hw2reg.mio_pad_attr[14].od_en.d),
14394 .qre (),
14395 .qe (mio_pad_attr_14_flds_we[6]),
14396 .q (reg2hw.mio_pad_attr[14].od_en.q),
14397 .ds (),
14398 .qs (mio_pad_attr_14_od_en_14_qs)
14399 );
14400 1/1 assign reg2hw.mio_pad_attr[14].od_en.qe = mio_pad_attr_14_qe;
Tests: T9 T37 T47
14401
14402 // F[input_disable_14]: 7:7
14403 prim_subreg_ext #(
14404 .DW (1)
14405 ) u_mio_pad_attr_14_input_disable_14 (
14406 .re (mio_pad_attr_14_re),
14407 .we (mio_pad_attr_14_gated_we),
14408 .wd (mio_pad_attr_14_input_disable_14_wd),
14409 .d (hw2reg.mio_pad_attr[14].input_disable.d),
14410 .qre (),
14411 .qe (mio_pad_attr_14_flds_we[7]),
14412 .q (reg2hw.mio_pad_attr[14].input_disable.q),
14413 .ds (),
14414 .qs (mio_pad_attr_14_input_disable_14_qs)
14415 );
14416 1/1 assign reg2hw.mio_pad_attr[14].input_disable.qe = mio_pad_attr_14_qe;
Tests: T9 T37 T47
14417
14418 // F[slew_rate_14]: 17:16
14419 prim_subreg_ext #(
14420 .DW (2)
14421 ) u_mio_pad_attr_14_slew_rate_14 (
14422 .re (mio_pad_attr_14_re),
14423 .we (mio_pad_attr_14_gated_we),
14424 .wd (mio_pad_attr_14_slew_rate_14_wd),
14425 .d (hw2reg.mio_pad_attr[14].slew_rate.d),
14426 .qre (),
14427 .qe (mio_pad_attr_14_flds_we[8]),
14428 .q (reg2hw.mio_pad_attr[14].slew_rate.q),
14429 .ds (),
14430 .qs (mio_pad_attr_14_slew_rate_14_qs)
14431 );
14432 1/1 assign reg2hw.mio_pad_attr[14].slew_rate.qe = mio_pad_attr_14_qe;
Tests: T9 T37 T47
14433
14434 // F[drive_strength_14]: 23:20
14435 prim_subreg_ext #(
14436 .DW (4)
14437 ) u_mio_pad_attr_14_drive_strength_14 (
14438 .re (mio_pad_attr_14_re),
14439 .we (mio_pad_attr_14_gated_we),
14440 .wd (mio_pad_attr_14_drive_strength_14_wd),
14441 .d (hw2reg.mio_pad_attr[14].drive_strength.d),
14442 .qre (),
14443 .qe (mio_pad_attr_14_flds_we[9]),
14444 .q (reg2hw.mio_pad_attr[14].drive_strength.q),
14445 .ds (),
14446 .qs (mio_pad_attr_14_drive_strength_14_qs)
14447 );
14448 1/1 assign reg2hw.mio_pad_attr[14].drive_strength.qe = mio_pad_attr_14_qe;
Tests: T9 T37 T47
14449
14450
14451 // Subregister 15 of Multireg mio_pad_attr
14452 // R[mio_pad_attr_15]: V(True)
14453 logic mio_pad_attr_15_qe;
14454 logic [9:0] mio_pad_attr_15_flds_we;
14455 1/1 assign mio_pad_attr_15_qe = &mio_pad_attr_15_flds_we;
Tests: T9 T37 T47
14456 // Create REGWEN-gated WE signal
14457 logic mio_pad_attr_15_gated_we;
14458 1/1 assign mio_pad_attr_15_gated_we = mio_pad_attr_15_we & mio_pad_attr_regwen_15_qs;
Tests: T9 T37 T47
14459 // F[invert_15]: 0:0
14460 prim_subreg_ext #(
14461 .DW (1)
14462 ) u_mio_pad_attr_15_invert_15 (
14463 .re (mio_pad_attr_15_re),
14464 .we (mio_pad_attr_15_gated_we),
14465 .wd (mio_pad_attr_15_invert_15_wd),
14466 .d (hw2reg.mio_pad_attr[15].invert.d),
14467 .qre (),
14468 .qe (mio_pad_attr_15_flds_we[0]),
14469 .q (reg2hw.mio_pad_attr[15].invert.q),
14470 .ds (),
14471 .qs (mio_pad_attr_15_invert_15_qs)
14472 );
14473 1/1 assign reg2hw.mio_pad_attr[15].invert.qe = mio_pad_attr_15_qe;
Tests: T9 T37 T47
14474
14475 // F[virtual_od_en_15]: 1:1
14476 prim_subreg_ext #(
14477 .DW (1)
14478 ) u_mio_pad_attr_15_virtual_od_en_15 (
14479 .re (mio_pad_attr_15_re),
14480 .we (mio_pad_attr_15_gated_we),
14481 .wd (mio_pad_attr_15_virtual_od_en_15_wd),
14482 .d (hw2reg.mio_pad_attr[15].virtual_od_en.d),
14483 .qre (),
14484 .qe (mio_pad_attr_15_flds_we[1]),
14485 .q (reg2hw.mio_pad_attr[15].virtual_od_en.q),
14486 .ds (),
14487 .qs (mio_pad_attr_15_virtual_od_en_15_qs)
14488 );
14489 1/1 assign reg2hw.mio_pad_attr[15].virtual_od_en.qe = mio_pad_attr_15_qe;
Tests: T9 T37 T47
14490
14491 // F[pull_en_15]: 2:2
14492 prim_subreg_ext #(
14493 .DW (1)
14494 ) u_mio_pad_attr_15_pull_en_15 (
14495 .re (mio_pad_attr_15_re),
14496 .we (mio_pad_attr_15_gated_we),
14497 .wd (mio_pad_attr_15_pull_en_15_wd),
14498 .d (hw2reg.mio_pad_attr[15].pull_en.d),
14499 .qre (),
14500 .qe (mio_pad_attr_15_flds_we[2]),
14501 .q (reg2hw.mio_pad_attr[15].pull_en.q),
14502 .ds (),
14503 .qs (mio_pad_attr_15_pull_en_15_qs)
14504 );
14505 1/1 assign reg2hw.mio_pad_attr[15].pull_en.qe = mio_pad_attr_15_qe;
Tests: T9 T37 T47
14506
14507 // F[pull_select_15]: 3:3
14508 prim_subreg_ext #(
14509 .DW (1)
14510 ) u_mio_pad_attr_15_pull_select_15 (
14511 .re (mio_pad_attr_15_re),
14512 .we (mio_pad_attr_15_gated_we),
14513 .wd (mio_pad_attr_15_pull_select_15_wd),
14514 .d (hw2reg.mio_pad_attr[15].pull_select.d),
14515 .qre (),
14516 .qe (mio_pad_attr_15_flds_we[3]),
14517 .q (reg2hw.mio_pad_attr[15].pull_select.q),
14518 .ds (),
14519 .qs (mio_pad_attr_15_pull_select_15_qs)
14520 );
14521 1/1 assign reg2hw.mio_pad_attr[15].pull_select.qe = mio_pad_attr_15_qe;
Tests: T9 T37 T47
14522
14523 // F[keeper_en_15]: 4:4
14524 prim_subreg_ext #(
14525 .DW (1)
14526 ) u_mio_pad_attr_15_keeper_en_15 (
14527 .re (mio_pad_attr_15_re),
14528 .we (mio_pad_attr_15_gated_we),
14529 .wd (mio_pad_attr_15_keeper_en_15_wd),
14530 .d (hw2reg.mio_pad_attr[15].keeper_en.d),
14531 .qre (),
14532 .qe (mio_pad_attr_15_flds_we[4]),
14533 .q (reg2hw.mio_pad_attr[15].keeper_en.q),
14534 .ds (),
14535 .qs (mio_pad_attr_15_keeper_en_15_qs)
14536 );
14537 1/1 assign reg2hw.mio_pad_attr[15].keeper_en.qe = mio_pad_attr_15_qe;
Tests: T9 T37 T47
14538
14539 // F[schmitt_en_15]: 5:5
14540 prim_subreg_ext #(
14541 .DW (1)
14542 ) u_mio_pad_attr_15_schmitt_en_15 (
14543 .re (mio_pad_attr_15_re),
14544 .we (mio_pad_attr_15_gated_we),
14545 .wd (mio_pad_attr_15_schmitt_en_15_wd),
14546 .d (hw2reg.mio_pad_attr[15].schmitt_en.d),
14547 .qre (),
14548 .qe (mio_pad_attr_15_flds_we[5]),
14549 .q (reg2hw.mio_pad_attr[15].schmitt_en.q),
14550 .ds (),
14551 .qs (mio_pad_attr_15_schmitt_en_15_qs)
14552 );
14553 1/1 assign reg2hw.mio_pad_attr[15].schmitt_en.qe = mio_pad_attr_15_qe;
Tests: T9 T37 T47
14554
14555 // F[od_en_15]: 6:6
14556 prim_subreg_ext #(
14557 .DW (1)
14558 ) u_mio_pad_attr_15_od_en_15 (
14559 .re (mio_pad_attr_15_re),
14560 .we (mio_pad_attr_15_gated_we),
14561 .wd (mio_pad_attr_15_od_en_15_wd),
14562 .d (hw2reg.mio_pad_attr[15].od_en.d),
14563 .qre (),
14564 .qe (mio_pad_attr_15_flds_we[6]),
14565 .q (reg2hw.mio_pad_attr[15].od_en.q),
14566 .ds (),
14567 .qs (mio_pad_attr_15_od_en_15_qs)
14568 );
14569 1/1 assign reg2hw.mio_pad_attr[15].od_en.qe = mio_pad_attr_15_qe;
Tests: T9 T37 T47
14570
14571 // F[input_disable_15]: 7:7
14572 prim_subreg_ext #(
14573 .DW (1)
14574 ) u_mio_pad_attr_15_input_disable_15 (
14575 .re (mio_pad_attr_15_re),
14576 .we (mio_pad_attr_15_gated_we),
14577 .wd (mio_pad_attr_15_input_disable_15_wd),
14578 .d (hw2reg.mio_pad_attr[15].input_disable.d),
14579 .qre (),
14580 .qe (mio_pad_attr_15_flds_we[7]),
14581 .q (reg2hw.mio_pad_attr[15].input_disable.q),
14582 .ds (),
14583 .qs (mio_pad_attr_15_input_disable_15_qs)
14584 );
14585 1/1 assign reg2hw.mio_pad_attr[15].input_disable.qe = mio_pad_attr_15_qe;
Tests: T9 T37 T47
14586
14587 // F[slew_rate_15]: 17:16
14588 prim_subreg_ext #(
14589 .DW (2)
14590 ) u_mio_pad_attr_15_slew_rate_15 (
14591 .re (mio_pad_attr_15_re),
14592 .we (mio_pad_attr_15_gated_we),
14593 .wd (mio_pad_attr_15_slew_rate_15_wd),
14594 .d (hw2reg.mio_pad_attr[15].slew_rate.d),
14595 .qre (),
14596 .qe (mio_pad_attr_15_flds_we[8]),
14597 .q (reg2hw.mio_pad_attr[15].slew_rate.q),
14598 .ds (),
14599 .qs (mio_pad_attr_15_slew_rate_15_qs)
14600 );
14601 1/1 assign reg2hw.mio_pad_attr[15].slew_rate.qe = mio_pad_attr_15_qe;
Tests: T9 T37 T47
14602
14603 // F[drive_strength_15]: 23:20
14604 prim_subreg_ext #(
14605 .DW (4)
14606 ) u_mio_pad_attr_15_drive_strength_15 (
14607 .re (mio_pad_attr_15_re),
14608 .we (mio_pad_attr_15_gated_we),
14609 .wd (mio_pad_attr_15_drive_strength_15_wd),
14610 .d (hw2reg.mio_pad_attr[15].drive_strength.d),
14611 .qre (),
14612 .qe (mio_pad_attr_15_flds_we[9]),
14613 .q (reg2hw.mio_pad_attr[15].drive_strength.q),
14614 .ds (),
14615 .qs (mio_pad_attr_15_drive_strength_15_qs)
14616 );
14617 1/1 assign reg2hw.mio_pad_attr[15].drive_strength.qe = mio_pad_attr_15_qe;
Tests: T9 T37 T47
14618
14619
14620 // Subregister 16 of Multireg mio_pad_attr
14621 // R[mio_pad_attr_16]: V(True)
14622 logic mio_pad_attr_16_qe;
14623 logic [9:0] mio_pad_attr_16_flds_we;
14624 1/1 assign mio_pad_attr_16_qe = &mio_pad_attr_16_flds_we;
Tests: T96 T97 T98
14625 // Create REGWEN-gated WE signal
14626 logic mio_pad_attr_16_gated_we;
14627 1/1 assign mio_pad_attr_16_gated_we = mio_pad_attr_16_we & mio_pad_attr_regwen_16_qs;
Tests: T71 T96 T97
14628 // F[invert_16]: 0:0
14629 prim_subreg_ext #(
14630 .DW (1)
14631 ) u_mio_pad_attr_16_invert_16 (
14632 .re (mio_pad_attr_16_re),
14633 .we (mio_pad_attr_16_gated_we),
14634 .wd (mio_pad_attr_16_invert_16_wd),
14635 .d (hw2reg.mio_pad_attr[16].invert.d),
14636 .qre (),
14637 .qe (mio_pad_attr_16_flds_we[0]),
14638 .q (reg2hw.mio_pad_attr[16].invert.q),
14639 .ds (),
14640 .qs (mio_pad_attr_16_invert_16_qs)
14641 );
14642 1/1 assign reg2hw.mio_pad_attr[16].invert.qe = mio_pad_attr_16_qe;
Tests: T96 T97 T98
14643
14644 // F[virtual_od_en_16]: 1:1
14645 prim_subreg_ext #(
14646 .DW (1)
14647 ) u_mio_pad_attr_16_virtual_od_en_16 (
14648 .re (mio_pad_attr_16_re),
14649 .we (mio_pad_attr_16_gated_we),
14650 .wd (mio_pad_attr_16_virtual_od_en_16_wd),
14651 .d (hw2reg.mio_pad_attr[16].virtual_od_en.d),
14652 .qre (),
14653 .qe (mio_pad_attr_16_flds_we[1]),
14654 .q (reg2hw.mio_pad_attr[16].virtual_od_en.q),
14655 .ds (),
14656 .qs (mio_pad_attr_16_virtual_od_en_16_qs)
14657 );
14658 1/1 assign reg2hw.mio_pad_attr[16].virtual_od_en.qe = mio_pad_attr_16_qe;
Tests: T96 T97 T98
14659
14660 // F[pull_en_16]: 2:2
14661 prim_subreg_ext #(
14662 .DW (1)
14663 ) u_mio_pad_attr_16_pull_en_16 (
14664 .re (mio_pad_attr_16_re),
14665 .we (mio_pad_attr_16_gated_we),
14666 .wd (mio_pad_attr_16_pull_en_16_wd),
14667 .d (hw2reg.mio_pad_attr[16].pull_en.d),
14668 .qre (),
14669 .qe (mio_pad_attr_16_flds_we[2]),
14670 .q (reg2hw.mio_pad_attr[16].pull_en.q),
14671 .ds (),
14672 .qs (mio_pad_attr_16_pull_en_16_qs)
14673 );
14674 1/1 assign reg2hw.mio_pad_attr[16].pull_en.qe = mio_pad_attr_16_qe;
Tests: T96 T97 T98
14675
14676 // F[pull_select_16]: 3:3
14677 prim_subreg_ext #(
14678 .DW (1)
14679 ) u_mio_pad_attr_16_pull_select_16 (
14680 .re (mio_pad_attr_16_re),
14681 .we (mio_pad_attr_16_gated_we),
14682 .wd (mio_pad_attr_16_pull_select_16_wd),
14683 .d (hw2reg.mio_pad_attr[16].pull_select.d),
14684 .qre (),
14685 .qe (mio_pad_attr_16_flds_we[3]),
14686 .q (reg2hw.mio_pad_attr[16].pull_select.q),
14687 .ds (),
14688 .qs (mio_pad_attr_16_pull_select_16_qs)
14689 );
14690 1/1 assign reg2hw.mio_pad_attr[16].pull_select.qe = mio_pad_attr_16_qe;
Tests: T96 T97 T98
14691
14692 // F[keeper_en_16]: 4:4
14693 prim_subreg_ext #(
14694 .DW (1)
14695 ) u_mio_pad_attr_16_keeper_en_16 (
14696 .re (mio_pad_attr_16_re),
14697 .we (mio_pad_attr_16_gated_we),
14698 .wd (mio_pad_attr_16_keeper_en_16_wd),
14699 .d (hw2reg.mio_pad_attr[16].keeper_en.d),
14700 .qre (),
14701 .qe (mio_pad_attr_16_flds_we[4]),
14702 .q (reg2hw.mio_pad_attr[16].keeper_en.q),
14703 .ds (),
14704 .qs (mio_pad_attr_16_keeper_en_16_qs)
14705 );
14706 1/1 assign reg2hw.mio_pad_attr[16].keeper_en.qe = mio_pad_attr_16_qe;
Tests: T96 T97 T98
14707
14708 // F[schmitt_en_16]: 5:5
14709 prim_subreg_ext #(
14710 .DW (1)
14711 ) u_mio_pad_attr_16_schmitt_en_16 (
14712 .re (mio_pad_attr_16_re),
14713 .we (mio_pad_attr_16_gated_we),
14714 .wd (mio_pad_attr_16_schmitt_en_16_wd),
14715 .d (hw2reg.mio_pad_attr[16].schmitt_en.d),
14716 .qre (),
14717 .qe (mio_pad_attr_16_flds_we[5]),
14718 .q (reg2hw.mio_pad_attr[16].schmitt_en.q),
14719 .ds (),
14720 .qs (mio_pad_attr_16_schmitt_en_16_qs)
14721 );
14722 1/1 assign reg2hw.mio_pad_attr[16].schmitt_en.qe = mio_pad_attr_16_qe;
Tests: T96 T97 T98
14723
14724 // F[od_en_16]: 6:6
14725 prim_subreg_ext #(
14726 .DW (1)
14727 ) u_mio_pad_attr_16_od_en_16 (
14728 .re (mio_pad_attr_16_re),
14729 .we (mio_pad_attr_16_gated_we),
14730 .wd (mio_pad_attr_16_od_en_16_wd),
14731 .d (hw2reg.mio_pad_attr[16].od_en.d),
14732 .qre (),
14733 .qe (mio_pad_attr_16_flds_we[6]),
14734 .q (reg2hw.mio_pad_attr[16].od_en.q),
14735 .ds (),
14736 .qs (mio_pad_attr_16_od_en_16_qs)
14737 );
14738 1/1 assign reg2hw.mio_pad_attr[16].od_en.qe = mio_pad_attr_16_qe;
Tests: T96 T97 T98
14739
14740 // F[input_disable_16]: 7:7
14741 prim_subreg_ext #(
14742 .DW (1)
14743 ) u_mio_pad_attr_16_input_disable_16 (
14744 .re (mio_pad_attr_16_re),
14745 .we (mio_pad_attr_16_gated_we),
14746 .wd (mio_pad_attr_16_input_disable_16_wd),
14747 .d (hw2reg.mio_pad_attr[16].input_disable.d),
14748 .qre (),
14749 .qe (mio_pad_attr_16_flds_we[7]),
14750 .q (reg2hw.mio_pad_attr[16].input_disable.q),
14751 .ds (),
14752 .qs (mio_pad_attr_16_input_disable_16_qs)
14753 );
14754 1/1 assign reg2hw.mio_pad_attr[16].input_disable.qe = mio_pad_attr_16_qe;
Tests: T96 T97 T98
14755
14756 // F[slew_rate_16]: 17:16
14757 prim_subreg_ext #(
14758 .DW (2)
14759 ) u_mio_pad_attr_16_slew_rate_16 (
14760 .re (mio_pad_attr_16_re),
14761 .we (mio_pad_attr_16_gated_we),
14762 .wd (mio_pad_attr_16_slew_rate_16_wd),
14763 .d (hw2reg.mio_pad_attr[16].slew_rate.d),
14764 .qre (),
14765 .qe (mio_pad_attr_16_flds_we[8]),
14766 .q (reg2hw.mio_pad_attr[16].slew_rate.q),
14767 .ds (),
14768 .qs (mio_pad_attr_16_slew_rate_16_qs)
14769 );
14770 1/1 assign reg2hw.mio_pad_attr[16].slew_rate.qe = mio_pad_attr_16_qe;
Tests: T96 T97 T98
14771
14772 // F[drive_strength_16]: 23:20
14773 prim_subreg_ext #(
14774 .DW (4)
14775 ) u_mio_pad_attr_16_drive_strength_16 (
14776 .re (mio_pad_attr_16_re),
14777 .we (mio_pad_attr_16_gated_we),
14778 .wd (mio_pad_attr_16_drive_strength_16_wd),
14779 .d (hw2reg.mio_pad_attr[16].drive_strength.d),
14780 .qre (),
14781 .qe (mio_pad_attr_16_flds_we[9]),
14782 .q (reg2hw.mio_pad_attr[16].drive_strength.q),
14783 .ds (),
14784 .qs (mio_pad_attr_16_drive_strength_16_qs)
14785 );
14786 1/1 assign reg2hw.mio_pad_attr[16].drive_strength.qe = mio_pad_attr_16_qe;
Tests: T96 T97 T98
14787
14788
14789 // Subregister 17 of Multireg mio_pad_attr
14790 // R[mio_pad_attr_17]: V(True)
14791 logic mio_pad_attr_17_qe;
14792 logic [9:0] mio_pad_attr_17_flds_we;
14793 1/1 assign mio_pad_attr_17_qe = &mio_pad_attr_17_flds_we;
Tests: T96 T97 T98
14794 // Create REGWEN-gated WE signal
14795 logic mio_pad_attr_17_gated_we;
14796 1/1 assign mio_pad_attr_17_gated_we = mio_pad_attr_17_we & mio_pad_attr_regwen_17_qs;
Tests: T96 T97 T98
14797 // F[invert_17]: 0:0
14798 prim_subreg_ext #(
14799 .DW (1)
14800 ) u_mio_pad_attr_17_invert_17 (
14801 .re (mio_pad_attr_17_re),
14802 .we (mio_pad_attr_17_gated_we),
14803 .wd (mio_pad_attr_17_invert_17_wd),
14804 .d (hw2reg.mio_pad_attr[17].invert.d),
14805 .qre (),
14806 .qe (mio_pad_attr_17_flds_we[0]),
14807 .q (reg2hw.mio_pad_attr[17].invert.q),
14808 .ds (),
14809 .qs (mio_pad_attr_17_invert_17_qs)
14810 );
14811 1/1 assign reg2hw.mio_pad_attr[17].invert.qe = mio_pad_attr_17_qe;
Tests: T96 T97 T98
14812
14813 // F[virtual_od_en_17]: 1:1
14814 prim_subreg_ext #(
14815 .DW (1)
14816 ) u_mio_pad_attr_17_virtual_od_en_17 (
14817 .re (mio_pad_attr_17_re),
14818 .we (mio_pad_attr_17_gated_we),
14819 .wd (mio_pad_attr_17_virtual_od_en_17_wd),
14820 .d (hw2reg.mio_pad_attr[17].virtual_od_en.d),
14821 .qre (),
14822 .qe (mio_pad_attr_17_flds_we[1]),
14823 .q (reg2hw.mio_pad_attr[17].virtual_od_en.q),
14824 .ds (),
14825 .qs (mio_pad_attr_17_virtual_od_en_17_qs)
14826 );
14827 1/1 assign reg2hw.mio_pad_attr[17].virtual_od_en.qe = mio_pad_attr_17_qe;
Tests: T96 T97 T98
14828
14829 // F[pull_en_17]: 2:2
14830 prim_subreg_ext #(
14831 .DW (1)
14832 ) u_mio_pad_attr_17_pull_en_17 (
14833 .re (mio_pad_attr_17_re),
14834 .we (mio_pad_attr_17_gated_we),
14835 .wd (mio_pad_attr_17_pull_en_17_wd),
14836 .d (hw2reg.mio_pad_attr[17].pull_en.d),
14837 .qre (),
14838 .qe (mio_pad_attr_17_flds_we[2]),
14839 .q (reg2hw.mio_pad_attr[17].pull_en.q),
14840 .ds (),
14841 .qs (mio_pad_attr_17_pull_en_17_qs)
14842 );
14843 1/1 assign reg2hw.mio_pad_attr[17].pull_en.qe = mio_pad_attr_17_qe;
Tests: T96 T97 T98
14844
14845 // F[pull_select_17]: 3:3
14846 prim_subreg_ext #(
14847 .DW (1)
14848 ) u_mio_pad_attr_17_pull_select_17 (
14849 .re (mio_pad_attr_17_re),
14850 .we (mio_pad_attr_17_gated_we),
14851 .wd (mio_pad_attr_17_pull_select_17_wd),
14852 .d (hw2reg.mio_pad_attr[17].pull_select.d),
14853 .qre (),
14854 .qe (mio_pad_attr_17_flds_we[3]),
14855 .q (reg2hw.mio_pad_attr[17].pull_select.q),
14856 .ds (),
14857 .qs (mio_pad_attr_17_pull_select_17_qs)
14858 );
14859 1/1 assign reg2hw.mio_pad_attr[17].pull_select.qe = mio_pad_attr_17_qe;
Tests: T96 T97 T98
14860
14861 // F[keeper_en_17]: 4:4
14862 prim_subreg_ext #(
14863 .DW (1)
14864 ) u_mio_pad_attr_17_keeper_en_17 (
14865 .re (mio_pad_attr_17_re),
14866 .we (mio_pad_attr_17_gated_we),
14867 .wd (mio_pad_attr_17_keeper_en_17_wd),
14868 .d (hw2reg.mio_pad_attr[17].keeper_en.d),
14869 .qre (),
14870 .qe (mio_pad_attr_17_flds_we[4]),
14871 .q (reg2hw.mio_pad_attr[17].keeper_en.q),
14872 .ds (),
14873 .qs (mio_pad_attr_17_keeper_en_17_qs)
14874 );
14875 1/1 assign reg2hw.mio_pad_attr[17].keeper_en.qe = mio_pad_attr_17_qe;
Tests: T96 T97 T98
14876
14877 // F[schmitt_en_17]: 5:5
14878 prim_subreg_ext #(
14879 .DW (1)
14880 ) u_mio_pad_attr_17_schmitt_en_17 (
14881 .re (mio_pad_attr_17_re),
14882 .we (mio_pad_attr_17_gated_we),
14883 .wd (mio_pad_attr_17_schmitt_en_17_wd),
14884 .d (hw2reg.mio_pad_attr[17].schmitt_en.d),
14885 .qre (),
14886 .qe (mio_pad_attr_17_flds_we[5]),
14887 .q (reg2hw.mio_pad_attr[17].schmitt_en.q),
14888 .ds (),
14889 .qs (mio_pad_attr_17_schmitt_en_17_qs)
14890 );
14891 1/1 assign reg2hw.mio_pad_attr[17].schmitt_en.qe = mio_pad_attr_17_qe;
Tests: T96 T97 T98
14892
14893 // F[od_en_17]: 6:6
14894 prim_subreg_ext #(
14895 .DW (1)
14896 ) u_mio_pad_attr_17_od_en_17 (
14897 .re (mio_pad_attr_17_re),
14898 .we (mio_pad_attr_17_gated_we),
14899 .wd (mio_pad_attr_17_od_en_17_wd),
14900 .d (hw2reg.mio_pad_attr[17].od_en.d),
14901 .qre (),
14902 .qe (mio_pad_attr_17_flds_we[6]),
14903 .q (reg2hw.mio_pad_attr[17].od_en.q),
14904 .ds (),
14905 .qs (mio_pad_attr_17_od_en_17_qs)
14906 );
14907 1/1 assign reg2hw.mio_pad_attr[17].od_en.qe = mio_pad_attr_17_qe;
Tests: T96 T97 T98
14908
14909 // F[input_disable_17]: 7:7
14910 prim_subreg_ext #(
14911 .DW (1)
14912 ) u_mio_pad_attr_17_input_disable_17 (
14913 .re (mio_pad_attr_17_re),
14914 .we (mio_pad_attr_17_gated_we),
14915 .wd (mio_pad_attr_17_input_disable_17_wd),
14916 .d (hw2reg.mio_pad_attr[17].input_disable.d),
14917 .qre (),
14918 .qe (mio_pad_attr_17_flds_we[7]),
14919 .q (reg2hw.mio_pad_attr[17].input_disable.q),
14920 .ds (),
14921 .qs (mio_pad_attr_17_input_disable_17_qs)
14922 );
14923 1/1 assign reg2hw.mio_pad_attr[17].input_disable.qe = mio_pad_attr_17_qe;
Tests: T96 T97 T98
14924
14925 // F[slew_rate_17]: 17:16
14926 prim_subreg_ext #(
14927 .DW (2)
14928 ) u_mio_pad_attr_17_slew_rate_17 (
14929 .re (mio_pad_attr_17_re),
14930 .we (mio_pad_attr_17_gated_we),
14931 .wd (mio_pad_attr_17_slew_rate_17_wd),
14932 .d (hw2reg.mio_pad_attr[17].slew_rate.d),
14933 .qre (),
14934 .qe (mio_pad_attr_17_flds_we[8]),
14935 .q (reg2hw.mio_pad_attr[17].slew_rate.q),
14936 .ds (),
14937 .qs (mio_pad_attr_17_slew_rate_17_qs)
14938 );
14939 1/1 assign reg2hw.mio_pad_attr[17].slew_rate.qe = mio_pad_attr_17_qe;
Tests: T96 T97 T98
14940
14941 // F[drive_strength_17]: 23:20
14942 prim_subreg_ext #(
14943 .DW (4)
14944 ) u_mio_pad_attr_17_drive_strength_17 (
14945 .re (mio_pad_attr_17_re),
14946 .we (mio_pad_attr_17_gated_we),
14947 .wd (mio_pad_attr_17_drive_strength_17_wd),
14948 .d (hw2reg.mio_pad_attr[17].drive_strength.d),
14949 .qre (),
14950 .qe (mio_pad_attr_17_flds_we[9]),
14951 .q (reg2hw.mio_pad_attr[17].drive_strength.q),
14952 .ds (),
14953 .qs (mio_pad_attr_17_drive_strength_17_qs)
14954 );
14955 1/1 assign reg2hw.mio_pad_attr[17].drive_strength.qe = mio_pad_attr_17_qe;
Tests: T96 T97 T98
14956
14957
14958 // Subregister 18 of Multireg mio_pad_attr
14959 // R[mio_pad_attr_18]: V(True)
14960 logic mio_pad_attr_18_qe;
14961 logic [9:0] mio_pad_attr_18_flds_we;
14962 1/1 assign mio_pad_attr_18_qe = &mio_pad_attr_18_flds_we;
Tests: T96 T97 T98
14963 // Create REGWEN-gated WE signal
14964 logic mio_pad_attr_18_gated_we;
14965 1/1 assign mio_pad_attr_18_gated_we = mio_pad_attr_18_we & mio_pad_attr_regwen_18_qs;
Tests: T96 T97 T98
14966 // F[invert_18]: 0:0
14967 prim_subreg_ext #(
14968 .DW (1)
14969 ) u_mio_pad_attr_18_invert_18 (
14970 .re (mio_pad_attr_18_re),
14971 .we (mio_pad_attr_18_gated_we),
14972 .wd (mio_pad_attr_18_invert_18_wd),
14973 .d (hw2reg.mio_pad_attr[18].invert.d),
14974 .qre (),
14975 .qe (mio_pad_attr_18_flds_we[0]),
14976 .q (reg2hw.mio_pad_attr[18].invert.q),
14977 .ds (),
14978 .qs (mio_pad_attr_18_invert_18_qs)
14979 );
14980 1/1 assign reg2hw.mio_pad_attr[18].invert.qe = mio_pad_attr_18_qe;
Tests: T96 T97 T98
14981
14982 // F[virtual_od_en_18]: 1:1
14983 prim_subreg_ext #(
14984 .DW (1)
14985 ) u_mio_pad_attr_18_virtual_od_en_18 (
14986 .re (mio_pad_attr_18_re),
14987 .we (mio_pad_attr_18_gated_we),
14988 .wd (mio_pad_attr_18_virtual_od_en_18_wd),
14989 .d (hw2reg.mio_pad_attr[18].virtual_od_en.d),
14990 .qre (),
14991 .qe (mio_pad_attr_18_flds_we[1]),
14992 .q (reg2hw.mio_pad_attr[18].virtual_od_en.q),
14993 .ds (),
14994 .qs (mio_pad_attr_18_virtual_od_en_18_qs)
14995 );
14996 1/1 assign reg2hw.mio_pad_attr[18].virtual_od_en.qe = mio_pad_attr_18_qe;
Tests: T96 T97 T98
14997
14998 // F[pull_en_18]: 2:2
14999 prim_subreg_ext #(
15000 .DW (1)
15001 ) u_mio_pad_attr_18_pull_en_18 (
15002 .re (mio_pad_attr_18_re),
15003 .we (mio_pad_attr_18_gated_we),
15004 .wd (mio_pad_attr_18_pull_en_18_wd),
15005 .d (hw2reg.mio_pad_attr[18].pull_en.d),
15006 .qre (),
15007 .qe (mio_pad_attr_18_flds_we[2]),
15008 .q (reg2hw.mio_pad_attr[18].pull_en.q),
15009 .ds (),
15010 .qs (mio_pad_attr_18_pull_en_18_qs)
15011 );
15012 1/1 assign reg2hw.mio_pad_attr[18].pull_en.qe = mio_pad_attr_18_qe;
Tests: T96 T97 T98
15013
15014 // F[pull_select_18]: 3:3
15015 prim_subreg_ext #(
15016 .DW (1)
15017 ) u_mio_pad_attr_18_pull_select_18 (
15018 .re (mio_pad_attr_18_re),
15019 .we (mio_pad_attr_18_gated_we),
15020 .wd (mio_pad_attr_18_pull_select_18_wd),
15021 .d (hw2reg.mio_pad_attr[18].pull_select.d),
15022 .qre (),
15023 .qe (mio_pad_attr_18_flds_we[3]),
15024 .q (reg2hw.mio_pad_attr[18].pull_select.q),
15025 .ds (),
15026 .qs (mio_pad_attr_18_pull_select_18_qs)
15027 );
15028 1/1 assign reg2hw.mio_pad_attr[18].pull_select.qe = mio_pad_attr_18_qe;
Tests: T96 T97 T98
15029
15030 // F[keeper_en_18]: 4:4
15031 prim_subreg_ext #(
15032 .DW (1)
15033 ) u_mio_pad_attr_18_keeper_en_18 (
15034 .re (mio_pad_attr_18_re),
15035 .we (mio_pad_attr_18_gated_we),
15036 .wd (mio_pad_attr_18_keeper_en_18_wd),
15037 .d (hw2reg.mio_pad_attr[18].keeper_en.d),
15038 .qre (),
15039 .qe (mio_pad_attr_18_flds_we[4]),
15040 .q (reg2hw.mio_pad_attr[18].keeper_en.q),
15041 .ds (),
15042 .qs (mio_pad_attr_18_keeper_en_18_qs)
15043 );
15044 1/1 assign reg2hw.mio_pad_attr[18].keeper_en.qe = mio_pad_attr_18_qe;
Tests: T96 T97 T98
15045
15046 // F[schmitt_en_18]: 5:5
15047 prim_subreg_ext #(
15048 .DW (1)
15049 ) u_mio_pad_attr_18_schmitt_en_18 (
15050 .re (mio_pad_attr_18_re),
15051 .we (mio_pad_attr_18_gated_we),
15052 .wd (mio_pad_attr_18_schmitt_en_18_wd),
15053 .d (hw2reg.mio_pad_attr[18].schmitt_en.d),
15054 .qre (),
15055 .qe (mio_pad_attr_18_flds_we[5]),
15056 .q (reg2hw.mio_pad_attr[18].schmitt_en.q),
15057 .ds (),
15058 .qs (mio_pad_attr_18_schmitt_en_18_qs)
15059 );
15060 1/1 assign reg2hw.mio_pad_attr[18].schmitt_en.qe = mio_pad_attr_18_qe;
Tests: T96 T97 T98
15061
15062 // F[od_en_18]: 6:6
15063 prim_subreg_ext #(
15064 .DW (1)
15065 ) u_mio_pad_attr_18_od_en_18 (
15066 .re (mio_pad_attr_18_re),
15067 .we (mio_pad_attr_18_gated_we),
15068 .wd (mio_pad_attr_18_od_en_18_wd),
15069 .d (hw2reg.mio_pad_attr[18].od_en.d),
15070 .qre (),
15071 .qe (mio_pad_attr_18_flds_we[6]),
15072 .q (reg2hw.mio_pad_attr[18].od_en.q),
15073 .ds (),
15074 .qs (mio_pad_attr_18_od_en_18_qs)
15075 );
15076 1/1 assign reg2hw.mio_pad_attr[18].od_en.qe = mio_pad_attr_18_qe;
Tests: T96 T97 T98
15077
15078 // F[input_disable_18]: 7:7
15079 prim_subreg_ext #(
15080 .DW (1)
15081 ) u_mio_pad_attr_18_input_disable_18 (
15082 .re (mio_pad_attr_18_re),
15083 .we (mio_pad_attr_18_gated_we),
15084 .wd (mio_pad_attr_18_input_disable_18_wd),
15085 .d (hw2reg.mio_pad_attr[18].input_disable.d),
15086 .qre (),
15087 .qe (mio_pad_attr_18_flds_we[7]),
15088 .q (reg2hw.mio_pad_attr[18].input_disable.q),
15089 .ds (),
15090 .qs (mio_pad_attr_18_input_disable_18_qs)
15091 );
15092 1/1 assign reg2hw.mio_pad_attr[18].input_disable.qe = mio_pad_attr_18_qe;
Tests: T96 T97 T98
15093
15094 // F[slew_rate_18]: 17:16
15095 prim_subreg_ext #(
15096 .DW (2)
15097 ) u_mio_pad_attr_18_slew_rate_18 (
15098 .re (mio_pad_attr_18_re),
15099 .we (mio_pad_attr_18_gated_we),
15100 .wd (mio_pad_attr_18_slew_rate_18_wd),
15101 .d (hw2reg.mio_pad_attr[18].slew_rate.d),
15102 .qre (),
15103 .qe (mio_pad_attr_18_flds_we[8]),
15104 .q (reg2hw.mio_pad_attr[18].slew_rate.q),
15105 .ds (),
15106 .qs (mio_pad_attr_18_slew_rate_18_qs)
15107 );
15108 1/1 assign reg2hw.mio_pad_attr[18].slew_rate.qe = mio_pad_attr_18_qe;
Tests: T96 T97 T98
15109
15110 // F[drive_strength_18]: 23:20
15111 prim_subreg_ext #(
15112 .DW (4)
15113 ) u_mio_pad_attr_18_drive_strength_18 (
15114 .re (mio_pad_attr_18_re),
15115 .we (mio_pad_attr_18_gated_we),
15116 .wd (mio_pad_attr_18_drive_strength_18_wd),
15117 .d (hw2reg.mio_pad_attr[18].drive_strength.d),
15118 .qre (),
15119 .qe (mio_pad_attr_18_flds_we[9]),
15120 .q (reg2hw.mio_pad_attr[18].drive_strength.q),
15121 .ds (),
15122 .qs (mio_pad_attr_18_drive_strength_18_qs)
15123 );
15124 1/1 assign reg2hw.mio_pad_attr[18].drive_strength.qe = mio_pad_attr_18_qe;
Tests: T96 T97 T98
15125
15126
15127 // Subregister 19 of Multireg mio_pad_attr
15128 // R[mio_pad_attr_19]: V(True)
15129 logic mio_pad_attr_19_qe;
15130 logic [9:0] mio_pad_attr_19_flds_we;
15131 1/1 assign mio_pad_attr_19_qe = &mio_pad_attr_19_flds_we;
Tests: T96 T97 T98
15132 // Create REGWEN-gated WE signal
15133 logic mio_pad_attr_19_gated_we;
15134 1/1 assign mio_pad_attr_19_gated_we = mio_pad_attr_19_we & mio_pad_attr_regwen_19_qs;
Tests: T71 T96 T97
15135 // F[invert_19]: 0:0
15136 prim_subreg_ext #(
15137 .DW (1)
15138 ) u_mio_pad_attr_19_invert_19 (
15139 .re (mio_pad_attr_19_re),
15140 .we (mio_pad_attr_19_gated_we),
15141 .wd (mio_pad_attr_19_invert_19_wd),
15142 .d (hw2reg.mio_pad_attr[19].invert.d),
15143 .qre (),
15144 .qe (mio_pad_attr_19_flds_we[0]),
15145 .q (reg2hw.mio_pad_attr[19].invert.q),
15146 .ds (),
15147 .qs (mio_pad_attr_19_invert_19_qs)
15148 );
15149 1/1 assign reg2hw.mio_pad_attr[19].invert.qe = mio_pad_attr_19_qe;
Tests: T96 T97 T98
15150
15151 // F[virtual_od_en_19]: 1:1
15152 prim_subreg_ext #(
15153 .DW (1)
15154 ) u_mio_pad_attr_19_virtual_od_en_19 (
15155 .re (mio_pad_attr_19_re),
15156 .we (mio_pad_attr_19_gated_we),
15157 .wd (mio_pad_attr_19_virtual_od_en_19_wd),
15158 .d (hw2reg.mio_pad_attr[19].virtual_od_en.d),
15159 .qre (),
15160 .qe (mio_pad_attr_19_flds_we[1]),
15161 .q (reg2hw.mio_pad_attr[19].virtual_od_en.q),
15162 .ds (),
15163 .qs (mio_pad_attr_19_virtual_od_en_19_qs)
15164 );
15165 1/1 assign reg2hw.mio_pad_attr[19].virtual_od_en.qe = mio_pad_attr_19_qe;
Tests: T96 T97 T98
15166
15167 // F[pull_en_19]: 2:2
15168 prim_subreg_ext #(
15169 .DW (1)
15170 ) u_mio_pad_attr_19_pull_en_19 (
15171 .re (mio_pad_attr_19_re),
15172 .we (mio_pad_attr_19_gated_we),
15173 .wd (mio_pad_attr_19_pull_en_19_wd),
15174 .d (hw2reg.mio_pad_attr[19].pull_en.d),
15175 .qre (),
15176 .qe (mio_pad_attr_19_flds_we[2]),
15177 .q (reg2hw.mio_pad_attr[19].pull_en.q),
15178 .ds (),
15179 .qs (mio_pad_attr_19_pull_en_19_qs)
15180 );
15181 1/1 assign reg2hw.mio_pad_attr[19].pull_en.qe = mio_pad_attr_19_qe;
Tests: T96 T97 T98
15182
15183 // F[pull_select_19]: 3:3
15184 prim_subreg_ext #(
15185 .DW (1)
15186 ) u_mio_pad_attr_19_pull_select_19 (
15187 .re (mio_pad_attr_19_re),
15188 .we (mio_pad_attr_19_gated_we),
15189 .wd (mio_pad_attr_19_pull_select_19_wd),
15190 .d (hw2reg.mio_pad_attr[19].pull_select.d),
15191 .qre (),
15192 .qe (mio_pad_attr_19_flds_we[3]),
15193 .q (reg2hw.mio_pad_attr[19].pull_select.q),
15194 .ds (),
15195 .qs (mio_pad_attr_19_pull_select_19_qs)
15196 );
15197 1/1 assign reg2hw.mio_pad_attr[19].pull_select.qe = mio_pad_attr_19_qe;
Tests: T96 T97 T98
15198
15199 // F[keeper_en_19]: 4:4
15200 prim_subreg_ext #(
15201 .DW (1)
15202 ) u_mio_pad_attr_19_keeper_en_19 (
15203 .re (mio_pad_attr_19_re),
15204 .we (mio_pad_attr_19_gated_we),
15205 .wd (mio_pad_attr_19_keeper_en_19_wd),
15206 .d (hw2reg.mio_pad_attr[19].keeper_en.d),
15207 .qre (),
15208 .qe (mio_pad_attr_19_flds_we[4]),
15209 .q (reg2hw.mio_pad_attr[19].keeper_en.q),
15210 .ds (),
15211 .qs (mio_pad_attr_19_keeper_en_19_qs)
15212 );
15213 1/1 assign reg2hw.mio_pad_attr[19].keeper_en.qe = mio_pad_attr_19_qe;
Tests: T96 T97 T98
15214
15215 // F[schmitt_en_19]: 5:5
15216 prim_subreg_ext #(
15217 .DW (1)
15218 ) u_mio_pad_attr_19_schmitt_en_19 (
15219 .re (mio_pad_attr_19_re),
15220 .we (mio_pad_attr_19_gated_we),
15221 .wd (mio_pad_attr_19_schmitt_en_19_wd),
15222 .d (hw2reg.mio_pad_attr[19].schmitt_en.d),
15223 .qre (),
15224 .qe (mio_pad_attr_19_flds_we[5]),
15225 .q (reg2hw.mio_pad_attr[19].schmitt_en.q),
15226 .ds (),
15227 .qs (mio_pad_attr_19_schmitt_en_19_qs)
15228 );
15229 1/1 assign reg2hw.mio_pad_attr[19].schmitt_en.qe = mio_pad_attr_19_qe;
Tests: T96 T97 T98
15230
15231 // F[od_en_19]: 6:6
15232 prim_subreg_ext #(
15233 .DW (1)
15234 ) u_mio_pad_attr_19_od_en_19 (
15235 .re (mio_pad_attr_19_re),
15236 .we (mio_pad_attr_19_gated_we),
15237 .wd (mio_pad_attr_19_od_en_19_wd),
15238 .d (hw2reg.mio_pad_attr[19].od_en.d),
15239 .qre (),
15240 .qe (mio_pad_attr_19_flds_we[6]),
15241 .q (reg2hw.mio_pad_attr[19].od_en.q),
15242 .ds (),
15243 .qs (mio_pad_attr_19_od_en_19_qs)
15244 );
15245 1/1 assign reg2hw.mio_pad_attr[19].od_en.qe = mio_pad_attr_19_qe;
Tests: T96 T97 T98
15246
15247 // F[input_disable_19]: 7:7
15248 prim_subreg_ext #(
15249 .DW (1)
15250 ) u_mio_pad_attr_19_input_disable_19 (
15251 .re (mio_pad_attr_19_re),
15252 .we (mio_pad_attr_19_gated_we),
15253 .wd (mio_pad_attr_19_input_disable_19_wd),
15254 .d (hw2reg.mio_pad_attr[19].input_disable.d),
15255 .qre (),
15256 .qe (mio_pad_attr_19_flds_we[7]),
15257 .q (reg2hw.mio_pad_attr[19].input_disable.q),
15258 .ds (),
15259 .qs (mio_pad_attr_19_input_disable_19_qs)
15260 );
15261 1/1 assign reg2hw.mio_pad_attr[19].input_disable.qe = mio_pad_attr_19_qe;
Tests: T96 T97 T98
15262
15263 // F[slew_rate_19]: 17:16
15264 prim_subreg_ext #(
15265 .DW (2)
15266 ) u_mio_pad_attr_19_slew_rate_19 (
15267 .re (mio_pad_attr_19_re),
15268 .we (mio_pad_attr_19_gated_we),
15269 .wd (mio_pad_attr_19_slew_rate_19_wd),
15270 .d (hw2reg.mio_pad_attr[19].slew_rate.d),
15271 .qre (),
15272 .qe (mio_pad_attr_19_flds_we[8]),
15273 .q (reg2hw.mio_pad_attr[19].slew_rate.q),
15274 .ds (),
15275 .qs (mio_pad_attr_19_slew_rate_19_qs)
15276 );
15277 1/1 assign reg2hw.mio_pad_attr[19].slew_rate.qe = mio_pad_attr_19_qe;
Tests: T96 T97 T98
15278
15279 // F[drive_strength_19]: 23:20
15280 prim_subreg_ext #(
15281 .DW (4)
15282 ) u_mio_pad_attr_19_drive_strength_19 (
15283 .re (mio_pad_attr_19_re),
15284 .we (mio_pad_attr_19_gated_we),
15285 .wd (mio_pad_attr_19_drive_strength_19_wd),
15286 .d (hw2reg.mio_pad_attr[19].drive_strength.d),
15287 .qre (),
15288 .qe (mio_pad_attr_19_flds_we[9]),
15289 .q (reg2hw.mio_pad_attr[19].drive_strength.q),
15290 .ds (),
15291 .qs (mio_pad_attr_19_drive_strength_19_qs)
15292 );
15293 1/1 assign reg2hw.mio_pad_attr[19].drive_strength.qe = mio_pad_attr_19_qe;
Tests: T96 T97 T98
15294
15295
15296 // Subregister 20 of Multireg mio_pad_attr
15297 // R[mio_pad_attr_20]: V(True)
15298 logic mio_pad_attr_20_qe;
15299 logic [9:0] mio_pad_attr_20_flds_we;
15300 1/1 assign mio_pad_attr_20_qe = &mio_pad_attr_20_flds_we;
Tests: T96 T97 T98
15301 // Create REGWEN-gated WE signal
15302 logic mio_pad_attr_20_gated_we;
15303 1/1 assign mio_pad_attr_20_gated_we = mio_pad_attr_20_we & mio_pad_attr_regwen_20_qs;
Tests: T71 T96 T97
15304 // F[invert_20]: 0:0
15305 prim_subreg_ext #(
15306 .DW (1)
15307 ) u_mio_pad_attr_20_invert_20 (
15308 .re (mio_pad_attr_20_re),
15309 .we (mio_pad_attr_20_gated_we),
15310 .wd (mio_pad_attr_20_invert_20_wd),
15311 .d (hw2reg.mio_pad_attr[20].invert.d),
15312 .qre (),
15313 .qe (mio_pad_attr_20_flds_we[0]),
15314 .q (reg2hw.mio_pad_attr[20].invert.q),
15315 .ds (),
15316 .qs (mio_pad_attr_20_invert_20_qs)
15317 );
15318 1/1 assign reg2hw.mio_pad_attr[20].invert.qe = mio_pad_attr_20_qe;
Tests: T96 T97 T98
15319
15320 // F[virtual_od_en_20]: 1:1
15321 prim_subreg_ext #(
15322 .DW (1)
15323 ) u_mio_pad_attr_20_virtual_od_en_20 (
15324 .re (mio_pad_attr_20_re),
15325 .we (mio_pad_attr_20_gated_we),
15326 .wd (mio_pad_attr_20_virtual_od_en_20_wd),
15327 .d (hw2reg.mio_pad_attr[20].virtual_od_en.d),
15328 .qre (),
15329 .qe (mio_pad_attr_20_flds_we[1]),
15330 .q (reg2hw.mio_pad_attr[20].virtual_od_en.q),
15331 .ds (),
15332 .qs (mio_pad_attr_20_virtual_od_en_20_qs)
15333 );
15334 1/1 assign reg2hw.mio_pad_attr[20].virtual_od_en.qe = mio_pad_attr_20_qe;
Tests: T96 T97 T98
15335
15336 // F[pull_en_20]: 2:2
15337 prim_subreg_ext #(
15338 .DW (1)
15339 ) u_mio_pad_attr_20_pull_en_20 (
15340 .re (mio_pad_attr_20_re),
15341 .we (mio_pad_attr_20_gated_we),
15342 .wd (mio_pad_attr_20_pull_en_20_wd),
15343 .d (hw2reg.mio_pad_attr[20].pull_en.d),
15344 .qre (),
15345 .qe (mio_pad_attr_20_flds_we[2]),
15346 .q (reg2hw.mio_pad_attr[20].pull_en.q),
15347 .ds (),
15348 .qs (mio_pad_attr_20_pull_en_20_qs)
15349 );
15350 1/1 assign reg2hw.mio_pad_attr[20].pull_en.qe = mio_pad_attr_20_qe;
Tests: T96 T97 T98
15351
15352 // F[pull_select_20]: 3:3
15353 prim_subreg_ext #(
15354 .DW (1)
15355 ) u_mio_pad_attr_20_pull_select_20 (
15356 .re (mio_pad_attr_20_re),
15357 .we (mio_pad_attr_20_gated_we),
15358 .wd (mio_pad_attr_20_pull_select_20_wd),
15359 .d (hw2reg.mio_pad_attr[20].pull_select.d),
15360 .qre (),
15361 .qe (mio_pad_attr_20_flds_we[3]),
15362 .q (reg2hw.mio_pad_attr[20].pull_select.q),
15363 .ds (),
15364 .qs (mio_pad_attr_20_pull_select_20_qs)
15365 );
15366 1/1 assign reg2hw.mio_pad_attr[20].pull_select.qe = mio_pad_attr_20_qe;
Tests: T96 T97 T98
15367
15368 // F[keeper_en_20]: 4:4
15369 prim_subreg_ext #(
15370 .DW (1)
15371 ) u_mio_pad_attr_20_keeper_en_20 (
15372 .re (mio_pad_attr_20_re),
15373 .we (mio_pad_attr_20_gated_we),
15374 .wd (mio_pad_attr_20_keeper_en_20_wd),
15375 .d (hw2reg.mio_pad_attr[20].keeper_en.d),
15376 .qre (),
15377 .qe (mio_pad_attr_20_flds_we[4]),
15378 .q (reg2hw.mio_pad_attr[20].keeper_en.q),
15379 .ds (),
15380 .qs (mio_pad_attr_20_keeper_en_20_qs)
15381 );
15382 1/1 assign reg2hw.mio_pad_attr[20].keeper_en.qe = mio_pad_attr_20_qe;
Tests: T96 T97 T98
15383
15384 // F[schmitt_en_20]: 5:5
15385 prim_subreg_ext #(
15386 .DW (1)
15387 ) u_mio_pad_attr_20_schmitt_en_20 (
15388 .re (mio_pad_attr_20_re),
15389 .we (mio_pad_attr_20_gated_we),
15390 .wd (mio_pad_attr_20_schmitt_en_20_wd),
15391 .d (hw2reg.mio_pad_attr[20].schmitt_en.d),
15392 .qre (),
15393 .qe (mio_pad_attr_20_flds_we[5]),
15394 .q (reg2hw.mio_pad_attr[20].schmitt_en.q),
15395 .ds (),
15396 .qs (mio_pad_attr_20_schmitt_en_20_qs)
15397 );
15398 1/1 assign reg2hw.mio_pad_attr[20].schmitt_en.qe = mio_pad_attr_20_qe;
Tests: T96 T97 T98
15399
15400 // F[od_en_20]: 6:6
15401 prim_subreg_ext #(
15402 .DW (1)
15403 ) u_mio_pad_attr_20_od_en_20 (
15404 .re (mio_pad_attr_20_re),
15405 .we (mio_pad_attr_20_gated_we),
15406 .wd (mio_pad_attr_20_od_en_20_wd),
15407 .d (hw2reg.mio_pad_attr[20].od_en.d),
15408 .qre (),
15409 .qe (mio_pad_attr_20_flds_we[6]),
15410 .q (reg2hw.mio_pad_attr[20].od_en.q),
15411 .ds (),
15412 .qs (mio_pad_attr_20_od_en_20_qs)
15413 );
15414 1/1 assign reg2hw.mio_pad_attr[20].od_en.qe = mio_pad_attr_20_qe;
Tests: T96 T97 T98
15415
15416 // F[input_disable_20]: 7:7
15417 prim_subreg_ext #(
15418 .DW (1)
15419 ) u_mio_pad_attr_20_input_disable_20 (
15420 .re (mio_pad_attr_20_re),
15421 .we (mio_pad_attr_20_gated_we),
15422 .wd (mio_pad_attr_20_input_disable_20_wd),
15423 .d (hw2reg.mio_pad_attr[20].input_disable.d),
15424 .qre (),
15425 .qe (mio_pad_attr_20_flds_we[7]),
15426 .q (reg2hw.mio_pad_attr[20].input_disable.q),
15427 .ds (),
15428 .qs (mio_pad_attr_20_input_disable_20_qs)
15429 );
15430 1/1 assign reg2hw.mio_pad_attr[20].input_disable.qe = mio_pad_attr_20_qe;
Tests: T96 T97 T98
15431
15432 // F[slew_rate_20]: 17:16
15433 prim_subreg_ext #(
15434 .DW (2)
15435 ) u_mio_pad_attr_20_slew_rate_20 (
15436 .re (mio_pad_attr_20_re),
15437 .we (mio_pad_attr_20_gated_we),
15438 .wd (mio_pad_attr_20_slew_rate_20_wd),
15439 .d (hw2reg.mio_pad_attr[20].slew_rate.d),
15440 .qre (),
15441 .qe (mio_pad_attr_20_flds_we[8]),
15442 .q (reg2hw.mio_pad_attr[20].slew_rate.q),
15443 .ds (),
15444 .qs (mio_pad_attr_20_slew_rate_20_qs)
15445 );
15446 1/1 assign reg2hw.mio_pad_attr[20].slew_rate.qe = mio_pad_attr_20_qe;
Tests: T96 T97 T98
15447
15448 // F[drive_strength_20]: 23:20
15449 prim_subreg_ext #(
15450 .DW (4)
15451 ) u_mio_pad_attr_20_drive_strength_20 (
15452 .re (mio_pad_attr_20_re),
15453 .we (mio_pad_attr_20_gated_we),
15454 .wd (mio_pad_attr_20_drive_strength_20_wd),
15455 .d (hw2reg.mio_pad_attr[20].drive_strength.d),
15456 .qre (),
15457 .qe (mio_pad_attr_20_flds_we[9]),
15458 .q (reg2hw.mio_pad_attr[20].drive_strength.q),
15459 .ds (),
15460 .qs (mio_pad_attr_20_drive_strength_20_qs)
15461 );
15462 1/1 assign reg2hw.mio_pad_attr[20].drive_strength.qe = mio_pad_attr_20_qe;
Tests: T96 T97 T98
15463
15464
15465 // Subregister 21 of Multireg mio_pad_attr
15466 // R[mio_pad_attr_21]: V(True)
15467 logic mio_pad_attr_21_qe;
15468 logic [9:0] mio_pad_attr_21_flds_we;
15469 1/1 assign mio_pad_attr_21_qe = &mio_pad_attr_21_flds_we;
Tests: T96 T97 T98
15470 // Create REGWEN-gated WE signal
15471 logic mio_pad_attr_21_gated_we;
15472 1/1 assign mio_pad_attr_21_gated_we = mio_pad_attr_21_we & mio_pad_attr_regwen_21_qs;
Tests: T71 T96 T97
15473 // F[invert_21]: 0:0
15474 prim_subreg_ext #(
15475 .DW (1)
15476 ) u_mio_pad_attr_21_invert_21 (
15477 .re (mio_pad_attr_21_re),
15478 .we (mio_pad_attr_21_gated_we),
15479 .wd (mio_pad_attr_21_invert_21_wd),
15480 .d (hw2reg.mio_pad_attr[21].invert.d),
15481 .qre (),
15482 .qe (mio_pad_attr_21_flds_we[0]),
15483 .q (reg2hw.mio_pad_attr[21].invert.q),
15484 .ds (),
15485 .qs (mio_pad_attr_21_invert_21_qs)
15486 );
15487 1/1 assign reg2hw.mio_pad_attr[21].invert.qe = mio_pad_attr_21_qe;
Tests: T96 T97 T98
15488
15489 // F[virtual_od_en_21]: 1:1
15490 prim_subreg_ext #(
15491 .DW (1)
15492 ) u_mio_pad_attr_21_virtual_od_en_21 (
15493 .re (mio_pad_attr_21_re),
15494 .we (mio_pad_attr_21_gated_we),
15495 .wd (mio_pad_attr_21_virtual_od_en_21_wd),
15496 .d (hw2reg.mio_pad_attr[21].virtual_od_en.d),
15497 .qre (),
15498 .qe (mio_pad_attr_21_flds_we[1]),
15499 .q (reg2hw.mio_pad_attr[21].virtual_od_en.q),
15500 .ds (),
15501 .qs (mio_pad_attr_21_virtual_od_en_21_qs)
15502 );
15503 1/1 assign reg2hw.mio_pad_attr[21].virtual_od_en.qe = mio_pad_attr_21_qe;
Tests: T96 T97 T98
15504
15505 // F[pull_en_21]: 2:2
15506 prim_subreg_ext #(
15507 .DW (1)
15508 ) u_mio_pad_attr_21_pull_en_21 (
15509 .re (mio_pad_attr_21_re),
15510 .we (mio_pad_attr_21_gated_we),
15511 .wd (mio_pad_attr_21_pull_en_21_wd),
15512 .d (hw2reg.mio_pad_attr[21].pull_en.d),
15513 .qre (),
15514 .qe (mio_pad_attr_21_flds_we[2]),
15515 .q (reg2hw.mio_pad_attr[21].pull_en.q),
15516 .ds (),
15517 .qs (mio_pad_attr_21_pull_en_21_qs)
15518 );
15519 1/1 assign reg2hw.mio_pad_attr[21].pull_en.qe = mio_pad_attr_21_qe;
Tests: T96 T97 T98
15520
15521 // F[pull_select_21]: 3:3
15522 prim_subreg_ext #(
15523 .DW (1)
15524 ) u_mio_pad_attr_21_pull_select_21 (
15525 .re (mio_pad_attr_21_re),
15526 .we (mio_pad_attr_21_gated_we),
15527 .wd (mio_pad_attr_21_pull_select_21_wd),
15528 .d (hw2reg.mio_pad_attr[21].pull_select.d),
15529 .qre (),
15530 .qe (mio_pad_attr_21_flds_we[3]),
15531 .q (reg2hw.mio_pad_attr[21].pull_select.q),
15532 .ds (),
15533 .qs (mio_pad_attr_21_pull_select_21_qs)
15534 );
15535 1/1 assign reg2hw.mio_pad_attr[21].pull_select.qe = mio_pad_attr_21_qe;
Tests: T96 T97 T98
15536
15537 // F[keeper_en_21]: 4:4
15538 prim_subreg_ext #(
15539 .DW (1)
15540 ) u_mio_pad_attr_21_keeper_en_21 (
15541 .re (mio_pad_attr_21_re),
15542 .we (mio_pad_attr_21_gated_we),
15543 .wd (mio_pad_attr_21_keeper_en_21_wd),
15544 .d (hw2reg.mio_pad_attr[21].keeper_en.d),
15545 .qre (),
15546 .qe (mio_pad_attr_21_flds_we[4]),
15547 .q (reg2hw.mio_pad_attr[21].keeper_en.q),
15548 .ds (),
15549 .qs (mio_pad_attr_21_keeper_en_21_qs)
15550 );
15551 1/1 assign reg2hw.mio_pad_attr[21].keeper_en.qe = mio_pad_attr_21_qe;
Tests: T96 T97 T98
15552
15553 // F[schmitt_en_21]: 5:5
15554 prim_subreg_ext #(
15555 .DW (1)
15556 ) u_mio_pad_attr_21_schmitt_en_21 (
15557 .re (mio_pad_attr_21_re),
15558 .we (mio_pad_attr_21_gated_we),
15559 .wd (mio_pad_attr_21_schmitt_en_21_wd),
15560 .d (hw2reg.mio_pad_attr[21].schmitt_en.d),
15561 .qre (),
15562 .qe (mio_pad_attr_21_flds_we[5]),
15563 .q (reg2hw.mio_pad_attr[21].schmitt_en.q),
15564 .ds (),
15565 .qs (mio_pad_attr_21_schmitt_en_21_qs)
15566 );
15567 1/1 assign reg2hw.mio_pad_attr[21].schmitt_en.qe = mio_pad_attr_21_qe;
Tests: T96 T97 T98
15568
15569 // F[od_en_21]: 6:6
15570 prim_subreg_ext #(
15571 .DW (1)
15572 ) u_mio_pad_attr_21_od_en_21 (
15573 .re (mio_pad_attr_21_re),
15574 .we (mio_pad_attr_21_gated_we),
15575 .wd (mio_pad_attr_21_od_en_21_wd),
15576 .d (hw2reg.mio_pad_attr[21].od_en.d),
15577 .qre (),
15578 .qe (mio_pad_attr_21_flds_we[6]),
15579 .q (reg2hw.mio_pad_attr[21].od_en.q),
15580 .ds (),
15581 .qs (mio_pad_attr_21_od_en_21_qs)
15582 );
15583 1/1 assign reg2hw.mio_pad_attr[21].od_en.qe = mio_pad_attr_21_qe;
Tests: T96 T97 T98
15584
15585 // F[input_disable_21]: 7:7
15586 prim_subreg_ext #(
15587 .DW (1)
15588 ) u_mio_pad_attr_21_input_disable_21 (
15589 .re (mio_pad_attr_21_re),
15590 .we (mio_pad_attr_21_gated_we),
15591 .wd (mio_pad_attr_21_input_disable_21_wd),
15592 .d (hw2reg.mio_pad_attr[21].input_disable.d),
15593 .qre (),
15594 .qe (mio_pad_attr_21_flds_we[7]),
15595 .q (reg2hw.mio_pad_attr[21].input_disable.q),
15596 .ds (),
15597 .qs (mio_pad_attr_21_input_disable_21_qs)
15598 );
15599 1/1 assign reg2hw.mio_pad_attr[21].input_disable.qe = mio_pad_attr_21_qe;
Tests: T96 T97 T98
15600
15601 // F[slew_rate_21]: 17:16
15602 prim_subreg_ext #(
15603 .DW (2)
15604 ) u_mio_pad_attr_21_slew_rate_21 (
15605 .re (mio_pad_attr_21_re),
15606 .we (mio_pad_attr_21_gated_we),
15607 .wd (mio_pad_attr_21_slew_rate_21_wd),
15608 .d (hw2reg.mio_pad_attr[21].slew_rate.d),
15609 .qre (),
15610 .qe (mio_pad_attr_21_flds_we[8]),
15611 .q (reg2hw.mio_pad_attr[21].slew_rate.q),
15612 .ds (),
15613 .qs (mio_pad_attr_21_slew_rate_21_qs)
15614 );
15615 1/1 assign reg2hw.mio_pad_attr[21].slew_rate.qe = mio_pad_attr_21_qe;
Tests: T96 T97 T98
15616
15617 // F[drive_strength_21]: 23:20
15618 prim_subreg_ext #(
15619 .DW (4)
15620 ) u_mio_pad_attr_21_drive_strength_21 (
15621 .re (mio_pad_attr_21_re),
15622 .we (mio_pad_attr_21_gated_we),
15623 .wd (mio_pad_attr_21_drive_strength_21_wd),
15624 .d (hw2reg.mio_pad_attr[21].drive_strength.d),
15625 .qre (),
15626 .qe (mio_pad_attr_21_flds_we[9]),
15627 .q (reg2hw.mio_pad_attr[21].drive_strength.q),
15628 .ds (),
15629 .qs (mio_pad_attr_21_drive_strength_21_qs)
15630 );
15631 1/1 assign reg2hw.mio_pad_attr[21].drive_strength.qe = mio_pad_attr_21_qe;
Tests: T96 T97 T98
15632
15633
15634 // Subregister 22 of Multireg mio_pad_attr
15635 // R[mio_pad_attr_22]: V(True)
15636 logic mio_pad_attr_22_qe;
15637 logic [9:0] mio_pad_attr_22_flds_we;
15638 1/1 assign mio_pad_attr_22_qe = &mio_pad_attr_22_flds_we;
Tests: T58 T55 T59
15639 // Create REGWEN-gated WE signal
15640 logic mio_pad_attr_22_gated_we;
15641 1/1 assign mio_pad_attr_22_gated_we = mio_pad_attr_22_we & mio_pad_attr_regwen_22_qs;
Tests: T58 T55 T59
15642 // F[invert_22]: 0:0
15643 prim_subreg_ext #(
15644 .DW (1)
15645 ) u_mio_pad_attr_22_invert_22 (
15646 .re (mio_pad_attr_22_re),
15647 .we (mio_pad_attr_22_gated_we),
15648 .wd (mio_pad_attr_22_invert_22_wd),
15649 .d (hw2reg.mio_pad_attr[22].invert.d),
15650 .qre (),
15651 .qe (mio_pad_attr_22_flds_we[0]),
15652 .q (reg2hw.mio_pad_attr[22].invert.q),
15653 .ds (),
15654 .qs (mio_pad_attr_22_invert_22_qs)
15655 );
15656 1/1 assign reg2hw.mio_pad_attr[22].invert.qe = mio_pad_attr_22_qe;
Tests: T58 T55 T59
15657
15658 // F[virtual_od_en_22]: 1:1
15659 prim_subreg_ext #(
15660 .DW (1)
15661 ) u_mio_pad_attr_22_virtual_od_en_22 (
15662 .re (mio_pad_attr_22_re),
15663 .we (mio_pad_attr_22_gated_we),
15664 .wd (mio_pad_attr_22_virtual_od_en_22_wd),
15665 .d (hw2reg.mio_pad_attr[22].virtual_od_en.d),
15666 .qre (),
15667 .qe (mio_pad_attr_22_flds_we[1]),
15668 .q (reg2hw.mio_pad_attr[22].virtual_od_en.q),
15669 .ds (),
15670 .qs (mio_pad_attr_22_virtual_od_en_22_qs)
15671 );
15672 1/1 assign reg2hw.mio_pad_attr[22].virtual_od_en.qe = mio_pad_attr_22_qe;
Tests: T58 T55 T59
15673
15674 // F[pull_en_22]: 2:2
15675 prim_subreg_ext #(
15676 .DW (1)
15677 ) u_mio_pad_attr_22_pull_en_22 (
15678 .re (mio_pad_attr_22_re),
15679 .we (mio_pad_attr_22_gated_we),
15680 .wd (mio_pad_attr_22_pull_en_22_wd),
15681 .d (hw2reg.mio_pad_attr[22].pull_en.d),
15682 .qre (),
15683 .qe (mio_pad_attr_22_flds_we[2]),
15684 .q (reg2hw.mio_pad_attr[22].pull_en.q),
15685 .ds (),
15686 .qs (mio_pad_attr_22_pull_en_22_qs)
15687 );
15688 1/1 assign reg2hw.mio_pad_attr[22].pull_en.qe = mio_pad_attr_22_qe;
Tests: T58 T55 T59
15689
15690 // F[pull_select_22]: 3:3
15691 prim_subreg_ext #(
15692 .DW (1)
15693 ) u_mio_pad_attr_22_pull_select_22 (
15694 .re (mio_pad_attr_22_re),
15695 .we (mio_pad_attr_22_gated_we),
15696 .wd (mio_pad_attr_22_pull_select_22_wd),
15697 .d (hw2reg.mio_pad_attr[22].pull_select.d),
15698 .qre (),
15699 .qe (mio_pad_attr_22_flds_we[3]),
15700 .q (reg2hw.mio_pad_attr[22].pull_select.q),
15701 .ds (),
15702 .qs (mio_pad_attr_22_pull_select_22_qs)
15703 );
15704 1/1 assign reg2hw.mio_pad_attr[22].pull_select.qe = mio_pad_attr_22_qe;
Tests: T58 T55 T59
15705
15706 // F[keeper_en_22]: 4:4
15707 prim_subreg_ext #(
15708 .DW (1)
15709 ) u_mio_pad_attr_22_keeper_en_22 (
15710 .re (mio_pad_attr_22_re),
15711 .we (mio_pad_attr_22_gated_we),
15712 .wd (mio_pad_attr_22_keeper_en_22_wd),
15713 .d (hw2reg.mio_pad_attr[22].keeper_en.d),
15714 .qre (),
15715 .qe (mio_pad_attr_22_flds_we[4]),
15716 .q (reg2hw.mio_pad_attr[22].keeper_en.q),
15717 .ds (),
15718 .qs (mio_pad_attr_22_keeper_en_22_qs)
15719 );
15720 1/1 assign reg2hw.mio_pad_attr[22].keeper_en.qe = mio_pad_attr_22_qe;
Tests: T58 T55 T59
15721
15722 // F[schmitt_en_22]: 5:5
15723 prim_subreg_ext #(
15724 .DW (1)
15725 ) u_mio_pad_attr_22_schmitt_en_22 (
15726 .re (mio_pad_attr_22_re),
15727 .we (mio_pad_attr_22_gated_we),
15728 .wd (mio_pad_attr_22_schmitt_en_22_wd),
15729 .d (hw2reg.mio_pad_attr[22].schmitt_en.d),
15730 .qre (),
15731 .qe (mio_pad_attr_22_flds_we[5]),
15732 .q (reg2hw.mio_pad_attr[22].schmitt_en.q),
15733 .ds (),
15734 .qs (mio_pad_attr_22_schmitt_en_22_qs)
15735 );
15736 1/1 assign reg2hw.mio_pad_attr[22].schmitt_en.qe = mio_pad_attr_22_qe;
Tests: T58 T55 T59
15737
15738 // F[od_en_22]: 6:6
15739 prim_subreg_ext #(
15740 .DW (1)
15741 ) u_mio_pad_attr_22_od_en_22 (
15742 .re (mio_pad_attr_22_re),
15743 .we (mio_pad_attr_22_gated_we),
15744 .wd (mio_pad_attr_22_od_en_22_wd),
15745 .d (hw2reg.mio_pad_attr[22].od_en.d),
15746 .qre (),
15747 .qe (mio_pad_attr_22_flds_we[6]),
15748 .q (reg2hw.mio_pad_attr[22].od_en.q),
15749 .ds (),
15750 .qs (mio_pad_attr_22_od_en_22_qs)
15751 );
15752 1/1 assign reg2hw.mio_pad_attr[22].od_en.qe = mio_pad_attr_22_qe;
Tests: T58 T55 T59
15753
15754 // F[input_disable_22]: 7:7
15755 prim_subreg_ext #(
15756 .DW (1)
15757 ) u_mio_pad_attr_22_input_disable_22 (
15758 .re (mio_pad_attr_22_re),
15759 .we (mio_pad_attr_22_gated_we),
15760 .wd (mio_pad_attr_22_input_disable_22_wd),
15761 .d (hw2reg.mio_pad_attr[22].input_disable.d),
15762 .qre (),
15763 .qe (mio_pad_attr_22_flds_we[7]),
15764 .q (reg2hw.mio_pad_attr[22].input_disable.q),
15765 .ds (),
15766 .qs (mio_pad_attr_22_input_disable_22_qs)
15767 );
15768 1/1 assign reg2hw.mio_pad_attr[22].input_disable.qe = mio_pad_attr_22_qe;
Tests: T58 T55 T59
15769
15770 // F[slew_rate_22]: 17:16
15771 prim_subreg_ext #(
15772 .DW (2)
15773 ) u_mio_pad_attr_22_slew_rate_22 (
15774 .re (mio_pad_attr_22_re),
15775 .we (mio_pad_attr_22_gated_we),
15776 .wd (mio_pad_attr_22_slew_rate_22_wd),
15777 .d (hw2reg.mio_pad_attr[22].slew_rate.d),
15778 .qre (),
15779 .qe (mio_pad_attr_22_flds_we[8]),
15780 .q (reg2hw.mio_pad_attr[22].slew_rate.q),
15781 .ds (),
15782 .qs (mio_pad_attr_22_slew_rate_22_qs)
15783 );
15784 1/1 assign reg2hw.mio_pad_attr[22].slew_rate.qe = mio_pad_attr_22_qe;
Tests: T58 T55 T59
15785
15786 // F[drive_strength_22]: 23:20
15787 prim_subreg_ext #(
15788 .DW (4)
15789 ) u_mio_pad_attr_22_drive_strength_22 (
15790 .re (mio_pad_attr_22_re),
15791 .we (mio_pad_attr_22_gated_we),
15792 .wd (mio_pad_attr_22_drive_strength_22_wd),
15793 .d (hw2reg.mio_pad_attr[22].drive_strength.d),
15794 .qre (),
15795 .qe (mio_pad_attr_22_flds_we[9]),
15796 .q (reg2hw.mio_pad_attr[22].drive_strength.q),
15797 .ds (),
15798 .qs (mio_pad_attr_22_drive_strength_22_qs)
15799 );
15800 1/1 assign reg2hw.mio_pad_attr[22].drive_strength.qe = mio_pad_attr_22_qe;
Tests: T58 T55 T59
15801
15802
15803 // Subregister 23 of Multireg mio_pad_attr
15804 // R[mio_pad_attr_23]: V(True)
15805 logic mio_pad_attr_23_qe;
15806 logic [9:0] mio_pad_attr_23_flds_we;
15807 1/1 assign mio_pad_attr_23_qe = &mio_pad_attr_23_flds_we;
Tests: T58 T55 T59
15808 // Create REGWEN-gated WE signal
15809 logic mio_pad_attr_23_gated_we;
15810 1/1 assign mio_pad_attr_23_gated_we = mio_pad_attr_23_we & mio_pad_attr_regwen_23_qs;
Tests: T58 T55 T59
15811 // F[invert_23]: 0:0
15812 prim_subreg_ext #(
15813 .DW (1)
15814 ) u_mio_pad_attr_23_invert_23 (
15815 .re (mio_pad_attr_23_re),
15816 .we (mio_pad_attr_23_gated_we),
15817 .wd (mio_pad_attr_23_invert_23_wd),
15818 .d (hw2reg.mio_pad_attr[23].invert.d),
15819 .qre (),
15820 .qe (mio_pad_attr_23_flds_we[0]),
15821 .q (reg2hw.mio_pad_attr[23].invert.q),
15822 .ds (),
15823 .qs (mio_pad_attr_23_invert_23_qs)
15824 );
15825 1/1 assign reg2hw.mio_pad_attr[23].invert.qe = mio_pad_attr_23_qe;
Tests: T58 T55 T59
15826
15827 // F[virtual_od_en_23]: 1:1
15828 prim_subreg_ext #(
15829 .DW (1)
15830 ) u_mio_pad_attr_23_virtual_od_en_23 (
15831 .re (mio_pad_attr_23_re),
15832 .we (mio_pad_attr_23_gated_we),
15833 .wd (mio_pad_attr_23_virtual_od_en_23_wd),
15834 .d (hw2reg.mio_pad_attr[23].virtual_od_en.d),
15835 .qre (),
15836 .qe (mio_pad_attr_23_flds_we[1]),
15837 .q (reg2hw.mio_pad_attr[23].virtual_od_en.q),
15838 .ds (),
15839 .qs (mio_pad_attr_23_virtual_od_en_23_qs)
15840 );
15841 1/1 assign reg2hw.mio_pad_attr[23].virtual_od_en.qe = mio_pad_attr_23_qe;
Tests: T58 T55 T59
15842
15843 // F[pull_en_23]: 2:2
15844 prim_subreg_ext #(
15845 .DW (1)
15846 ) u_mio_pad_attr_23_pull_en_23 (
15847 .re (mio_pad_attr_23_re),
15848 .we (mio_pad_attr_23_gated_we),
15849 .wd (mio_pad_attr_23_pull_en_23_wd),
15850 .d (hw2reg.mio_pad_attr[23].pull_en.d),
15851 .qre (),
15852 .qe (mio_pad_attr_23_flds_we[2]),
15853 .q (reg2hw.mio_pad_attr[23].pull_en.q),
15854 .ds (),
15855 .qs (mio_pad_attr_23_pull_en_23_qs)
15856 );
15857 1/1 assign reg2hw.mio_pad_attr[23].pull_en.qe = mio_pad_attr_23_qe;
Tests: T58 T55 T59
15858
15859 // F[pull_select_23]: 3:3
15860 prim_subreg_ext #(
15861 .DW (1)
15862 ) u_mio_pad_attr_23_pull_select_23 (
15863 .re (mio_pad_attr_23_re),
15864 .we (mio_pad_attr_23_gated_we),
15865 .wd (mio_pad_attr_23_pull_select_23_wd),
15866 .d (hw2reg.mio_pad_attr[23].pull_select.d),
15867 .qre (),
15868 .qe (mio_pad_attr_23_flds_we[3]),
15869 .q (reg2hw.mio_pad_attr[23].pull_select.q),
15870 .ds (),
15871 .qs (mio_pad_attr_23_pull_select_23_qs)
15872 );
15873 1/1 assign reg2hw.mio_pad_attr[23].pull_select.qe = mio_pad_attr_23_qe;
Tests: T58 T55 T59
15874
15875 // F[keeper_en_23]: 4:4
15876 prim_subreg_ext #(
15877 .DW (1)
15878 ) u_mio_pad_attr_23_keeper_en_23 (
15879 .re (mio_pad_attr_23_re),
15880 .we (mio_pad_attr_23_gated_we),
15881 .wd (mio_pad_attr_23_keeper_en_23_wd),
15882 .d (hw2reg.mio_pad_attr[23].keeper_en.d),
15883 .qre (),
15884 .qe (mio_pad_attr_23_flds_we[4]),
15885 .q (reg2hw.mio_pad_attr[23].keeper_en.q),
15886 .ds (),
15887 .qs (mio_pad_attr_23_keeper_en_23_qs)
15888 );
15889 1/1 assign reg2hw.mio_pad_attr[23].keeper_en.qe = mio_pad_attr_23_qe;
Tests: T58 T55 T59
15890
15891 // F[schmitt_en_23]: 5:5
15892 prim_subreg_ext #(
15893 .DW (1)
15894 ) u_mio_pad_attr_23_schmitt_en_23 (
15895 .re (mio_pad_attr_23_re),
15896 .we (mio_pad_attr_23_gated_we),
15897 .wd (mio_pad_attr_23_schmitt_en_23_wd),
15898 .d (hw2reg.mio_pad_attr[23].schmitt_en.d),
15899 .qre (),
15900 .qe (mio_pad_attr_23_flds_we[5]),
15901 .q (reg2hw.mio_pad_attr[23].schmitt_en.q),
15902 .ds (),
15903 .qs (mio_pad_attr_23_schmitt_en_23_qs)
15904 );
15905 1/1 assign reg2hw.mio_pad_attr[23].schmitt_en.qe = mio_pad_attr_23_qe;
Tests: T58 T55 T59
15906
15907 // F[od_en_23]: 6:6
15908 prim_subreg_ext #(
15909 .DW (1)
15910 ) u_mio_pad_attr_23_od_en_23 (
15911 .re (mio_pad_attr_23_re),
15912 .we (mio_pad_attr_23_gated_we),
15913 .wd (mio_pad_attr_23_od_en_23_wd),
15914 .d (hw2reg.mio_pad_attr[23].od_en.d),
15915 .qre (),
15916 .qe (mio_pad_attr_23_flds_we[6]),
15917 .q (reg2hw.mio_pad_attr[23].od_en.q),
15918 .ds (),
15919 .qs (mio_pad_attr_23_od_en_23_qs)
15920 );
15921 1/1 assign reg2hw.mio_pad_attr[23].od_en.qe = mio_pad_attr_23_qe;
Tests: T58 T55 T59
15922
15923 // F[input_disable_23]: 7:7
15924 prim_subreg_ext #(
15925 .DW (1)
15926 ) u_mio_pad_attr_23_input_disable_23 (
15927 .re (mio_pad_attr_23_re),
15928 .we (mio_pad_attr_23_gated_we),
15929 .wd (mio_pad_attr_23_input_disable_23_wd),
15930 .d (hw2reg.mio_pad_attr[23].input_disable.d),
15931 .qre (),
15932 .qe (mio_pad_attr_23_flds_we[7]),
15933 .q (reg2hw.mio_pad_attr[23].input_disable.q),
15934 .ds (),
15935 .qs (mio_pad_attr_23_input_disable_23_qs)
15936 );
15937 1/1 assign reg2hw.mio_pad_attr[23].input_disable.qe = mio_pad_attr_23_qe;
Tests: T58 T55 T59
15938
15939 // F[slew_rate_23]: 17:16
15940 prim_subreg_ext #(
15941 .DW (2)
15942 ) u_mio_pad_attr_23_slew_rate_23 (
15943 .re (mio_pad_attr_23_re),
15944 .we (mio_pad_attr_23_gated_we),
15945 .wd (mio_pad_attr_23_slew_rate_23_wd),
15946 .d (hw2reg.mio_pad_attr[23].slew_rate.d),
15947 .qre (),
15948 .qe (mio_pad_attr_23_flds_we[8]),
15949 .q (reg2hw.mio_pad_attr[23].slew_rate.q),
15950 .ds (),
15951 .qs (mio_pad_attr_23_slew_rate_23_qs)
15952 );
15953 1/1 assign reg2hw.mio_pad_attr[23].slew_rate.qe = mio_pad_attr_23_qe;
Tests: T58 T55 T59
15954
15955 // F[drive_strength_23]: 23:20
15956 prim_subreg_ext #(
15957 .DW (4)
15958 ) u_mio_pad_attr_23_drive_strength_23 (
15959 .re (mio_pad_attr_23_re),
15960 .we (mio_pad_attr_23_gated_we),
15961 .wd (mio_pad_attr_23_drive_strength_23_wd),
15962 .d (hw2reg.mio_pad_attr[23].drive_strength.d),
15963 .qre (),
15964 .qe (mio_pad_attr_23_flds_we[9]),
15965 .q (reg2hw.mio_pad_attr[23].drive_strength.q),
15966 .ds (),
15967 .qs (mio_pad_attr_23_drive_strength_23_qs)
15968 );
15969 1/1 assign reg2hw.mio_pad_attr[23].drive_strength.qe = mio_pad_attr_23_qe;
Tests: T58 T55 T59
15970
15971
15972 // Subregister 24 of Multireg mio_pad_attr
15973 // R[mio_pad_attr_24]: V(True)
15974 logic mio_pad_attr_24_qe;
15975 logic [9:0] mio_pad_attr_24_flds_we;
15976 1/1 assign mio_pad_attr_24_qe = &mio_pad_attr_24_flds_we;
Tests: T58 T55 T59
15977 // Create REGWEN-gated WE signal
15978 logic mio_pad_attr_24_gated_we;
15979 1/1 assign mio_pad_attr_24_gated_we = mio_pad_attr_24_we & mio_pad_attr_regwen_24_qs;
Tests: T58 T55 T59
15980 // F[invert_24]: 0:0
15981 prim_subreg_ext #(
15982 .DW (1)
15983 ) u_mio_pad_attr_24_invert_24 (
15984 .re (mio_pad_attr_24_re),
15985 .we (mio_pad_attr_24_gated_we),
15986 .wd (mio_pad_attr_24_invert_24_wd),
15987 .d (hw2reg.mio_pad_attr[24].invert.d),
15988 .qre (),
15989 .qe (mio_pad_attr_24_flds_we[0]),
15990 .q (reg2hw.mio_pad_attr[24].invert.q),
15991 .ds (),
15992 .qs (mio_pad_attr_24_invert_24_qs)
15993 );
15994 1/1 assign reg2hw.mio_pad_attr[24].invert.qe = mio_pad_attr_24_qe;
Tests: T58 T55 T59
15995
15996 // F[virtual_od_en_24]: 1:1
15997 prim_subreg_ext #(
15998 .DW (1)
15999 ) u_mio_pad_attr_24_virtual_od_en_24 (
16000 .re (mio_pad_attr_24_re),
16001 .we (mio_pad_attr_24_gated_we),
16002 .wd (mio_pad_attr_24_virtual_od_en_24_wd),
16003 .d (hw2reg.mio_pad_attr[24].virtual_od_en.d),
16004 .qre (),
16005 .qe (mio_pad_attr_24_flds_we[1]),
16006 .q (reg2hw.mio_pad_attr[24].virtual_od_en.q),
16007 .ds (),
16008 .qs (mio_pad_attr_24_virtual_od_en_24_qs)
16009 );
16010 1/1 assign reg2hw.mio_pad_attr[24].virtual_od_en.qe = mio_pad_attr_24_qe;
Tests: T58 T55 T59
16011
16012 // F[pull_en_24]: 2:2
16013 prim_subreg_ext #(
16014 .DW (1)
16015 ) u_mio_pad_attr_24_pull_en_24 (
16016 .re (mio_pad_attr_24_re),
16017 .we (mio_pad_attr_24_gated_we),
16018 .wd (mio_pad_attr_24_pull_en_24_wd),
16019 .d (hw2reg.mio_pad_attr[24].pull_en.d),
16020 .qre (),
16021 .qe (mio_pad_attr_24_flds_we[2]),
16022 .q (reg2hw.mio_pad_attr[24].pull_en.q),
16023 .ds (),
16024 .qs (mio_pad_attr_24_pull_en_24_qs)
16025 );
16026 1/1 assign reg2hw.mio_pad_attr[24].pull_en.qe = mio_pad_attr_24_qe;
Tests: T58 T55 T59
16027
16028 // F[pull_select_24]: 3:3
16029 prim_subreg_ext #(
16030 .DW (1)
16031 ) u_mio_pad_attr_24_pull_select_24 (
16032 .re (mio_pad_attr_24_re),
16033 .we (mio_pad_attr_24_gated_we),
16034 .wd (mio_pad_attr_24_pull_select_24_wd),
16035 .d (hw2reg.mio_pad_attr[24].pull_select.d),
16036 .qre (),
16037 .qe (mio_pad_attr_24_flds_we[3]),
16038 .q (reg2hw.mio_pad_attr[24].pull_select.q),
16039 .ds (),
16040 .qs (mio_pad_attr_24_pull_select_24_qs)
16041 );
16042 1/1 assign reg2hw.mio_pad_attr[24].pull_select.qe = mio_pad_attr_24_qe;
Tests: T58 T55 T59
16043
16044 // F[keeper_en_24]: 4:4
16045 prim_subreg_ext #(
16046 .DW (1)
16047 ) u_mio_pad_attr_24_keeper_en_24 (
16048 .re (mio_pad_attr_24_re),
16049 .we (mio_pad_attr_24_gated_we),
16050 .wd (mio_pad_attr_24_keeper_en_24_wd),
16051 .d (hw2reg.mio_pad_attr[24].keeper_en.d),
16052 .qre (),
16053 .qe (mio_pad_attr_24_flds_we[4]),
16054 .q (reg2hw.mio_pad_attr[24].keeper_en.q),
16055 .ds (),
16056 .qs (mio_pad_attr_24_keeper_en_24_qs)
16057 );
16058 1/1 assign reg2hw.mio_pad_attr[24].keeper_en.qe = mio_pad_attr_24_qe;
Tests: T58 T55 T59
16059
16060 // F[schmitt_en_24]: 5:5
16061 prim_subreg_ext #(
16062 .DW (1)
16063 ) u_mio_pad_attr_24_schmitt_en_24 (
16064 .re (mio_pad_attr_24_re),
16065 .we (mio_pad_attr_24_gated_we),
16066 .wd (mio_pad_attr_24_schmitt_en_24_wd),
16067 .d (hw2reg.mio_pad_attr[24].schmitt_en.d),
16068 .qre (),
16069 .qe (mio_pad_attr_24_flds_we[5]),
16070 .q (reg2hw.mio_pad_attr[24].schmitt_en.q),
16071 .ds (),
16072 .qs (mio_pad_attr_24_schmitt_en_24_qs)
16073 );
16074 1/1 assign reg2hw.mio_pad_attr[24].schmitt_en.qe = mio_pad_attr_24_qe;
Tests: T58 T55 T59
16075
16076 // F[od_en_24]: 6:6
16077 prim_subreg_ext #(
16078 .DW (1)
16079 ) u_mio_pad_attr_24_od_en_24 (
16080 .re (mio_pad_attr_24_re),
16081 .we (mio_pad_attr_24_gated_we),
16082 .wd (mio_pad_attr_24_od_en_24_wd),
16083 .d (hw2reg.mio_pad_attr[24].od_en.d),
16084 .qre (),
16085 .qe (mio_pad_attr_24_flds_we[6]),
16086 .q (reg2hw.mio_pad_attr[24].od_en.q),
16087 .ds (),
16088 .qs (mio_pad_attr_24_od_en_24_qs)
16089 );
16090 1/1 assign reg2hw.mio_pad_attr[24].od_en.qe = mio_pad_attr_24_qe;
Tests: T58 T55 T59
16091
16092 // F[input_disable_24]: 7:7
16093 prim_subreg_ext #(
16094 .DW (1)
16095 ) u_mio_pad_attr_24_input_disable_24 (
16096 .re (mio_pad_attr_24_re),
16097 .we (mio_pad_attr_24_gated_we),
16098 .wd (mio_pad_attr_24_input_disable_24_wd),
16099 .d (hw2reg.mio_pad_attr[24].input_disable.d),
16100 .qre (),
16101 .qe (mio_pad_attr_24_flds_we[7]),
16102 .q (reg2hw.mio_pad_attr[24].input_disable.q),
16103 .ds (),
16104 .qs (mio_pad_attr_24_input_disable_24_qs)
16105 );
16106 1/1 assign reg2hw.mio_pad_attr[24].input_disable.qe = mio_pad_attr_24_qe;
Tests: T58 T55 T59
16107
16108 // F[slew_rate_24]: 17:16
16109 prim_subreg_ext #(
16110 .DW (2)
16111 ) u_mio_pad_attr_24_slew_rate_24 (
16112 .re (mio_pad_attr_24_re),
16113 .we (mio_pad_attr_24_gated_we),
16114 .wd (mio_pad_attr_24_slew_rate_24_wd),
16115 .d (hw2reg.mio_pad_attr[24].slew_rate.d),
16116 .qre (),
16117 .qe (mio_pad_attr_24_flds_we[8]),
16118 .q (reg2hw.mio_pad_attr[24].slew_rate.q),
16119 .ds (),
16120 .qs (mio_pad_attr_24_slew_rate_24_qs)
16121 );
16122 1/1 assign reg2hw.mio_pad_attr[24].slew_rate.qe = mio_pad_attr_24_qe;
Tests: T58 T55 T59
16123
16124 // F[drive_strength_24]: 23:20
16125 prim_subreg_ext #(
16126 .DW (4)
16127 ) u_mio_pad_attr_24_drive_strength_24 (
16128 .re (mio_pad_attr_24_re),
16129 .we (mio_pad_attr_24_gated_we),
16130 .wd (mio_pad_attr_24_drive_strength_24_wd),
16131 .d (hw2reg.mio_pad_attr[24].drive_strength.d),
16132 .qre (),
16133 .qe (mio_pad_attr_24_flds_we[9]),
16134 .q (reg2hw.mio_pad_attr[24].drive_strength.q),
16135 .ds (),
16136 .qs (mio_pad_attr_24_drive_strength_24_qs)
16137 );
16138 1/1 assign reg2hw.mio_pad_attr[24].drive_strength.qe = mio_pad_attr_24_qe;
Tests: T58 T55 T59
16139
16140
16141 // Subregister 25 of Multireg mio_pad_attr
16142 // R[mio_pad_attr_25]: V(True)
16143 logic mio_pad_attr_25_qe;
16144 logic [9:0] mio_pad_attr_25_flds_we;
16145 1/1 assign mio_pad_attr_25_qe = &mio_pad_attr_25_flds_we;
Tests: T1 T2 T3
16146 // Create REGWEN-gated WE signal
16147 logic mio_pad_attr_25_gated_we;
16148 1/1 assign mio_pad_attr_25_gated_we = mio_pad_attr_25_we & mio_pad_attr_regwen_25_qs;
Tests: T1 T2 T3
16149 // F[invert_25]: 0:0
16150 prim_subreg_ext #(
16151 .DW (1)
16152 ) u_mio_pad_attr_25_invert_25 (
16153 .re (mio_pad_attr_25_re),
16154 .we (mio_pad_attr_25_gated_we),
16155 .wd (mio_pad_attr_25_invert_25_wd),
16156 .d (hw2reg.mio_pad_attr[25].invert.d),
16157 .qre (),
16158 .qe (mio_pad_attr_25_flds_we[0]),
16159 .q (reg2hw.mio_pad_attr[25].invert.q),
16160 .ds (),
16161 .qs (mio_pad_attr_25_invert_25_qs)
16162 );
16163 1/1 assign reg2hw.mio_pad_attr[25].invert.qe = mio_pad_attr_25_qe;
Tests: T1 T2 T3
16164
16165 // F[virtual_od_en_25]: 1:1
16166 prim_subreg_ext #(
16167 .DW (1)
16168 ) u_mio_pad_attr_25_virtual_od_en_25 (
16169 .re (mio_pad_attr_25_re),
16170 .we (mio_pad_attr_25_gated_we),
16171 .wd (mio_pad_attr_25_virtual_od_en_25_wd),
16172 .d (hw2reg.mio_pad_attr[25].virtual_od_en.d),
16173 .qre (),
16174 .qe (mio_pad_attr_25_flds_we[1]),
16175 .q (reg2hw.mio_pad_attr[25].virtual_od_en.q),
16176 .ds (),
16177 .qs (mio_pad_attr_25_virtual_od_en_25_qs)
16178 );
16179 1/1 assign reg2hw.mio_pad_attr[25].virtual_od_en.qe = mio_pad_attr_25_qe;
Tests: T1 T2 T3
16180
16181 // F[pull_en_25]: 2:2
16182 prim_subreg_ext #(
16183 .DW (1)
16184 ) u_mio_pad_attr_25_pull_en_25 (
16185 .re (mio_pad_attr_25_re),
16186 .we (mio_pad_attr_25_gated_we),
16187 .wd (mio_pad_attr_25_pull_en_25_wd),
16188 .d (hw2reg.mio_pad_attr[25].pull_en.d),
16189 .qre (),
16190 .qe (mio_pad_attr_25_flds_we[2]),
16191 .q (reg2hw.mio_pad_attr[25].pull_en.q),
16192 .ds (),
16193 .qs (mio_pad_attr_25_pull_en_25_qs)
16194 );
16195 1/1 assign reg2hw.mio_pad_attr[25].pull_en.qe = mio_pad_attr_25_qe;
Tests: T1 T2 T3
16196
16197 // F[pull_select_25]: 3:3
16198 prim_subreg_ext #(
16199 .DW (1)
16200 ) u_mio_pad_attr_25_pull_select_25 (
16201 .re (mio_pad_attr_25_re),
16202 .we (mio_pad_attr_25_gated_we),
16203 .wd (mio_pad_attr_25_pull_select_25_wd),
16204 .d (hw2reg.mio_pad_attr[25].pull_select.d),
16205 .qre (),
16206 .qe (mio_pad_attr_25_flds_we[3]),
16207 .q (reg2hw.mio_pad_attr[25].pull_select.q),
16208 .ds (),
16209 .qs (mio_pad_attr_25_pull_select_25_qs)
16210 );
16211 1/1 assign reg2hw.mio_pad_attr[25].pull_select.qe = mio_pad_attr_25_qe;
Tests: T1 T2 T3
16212
16213 // F[keeper_en_25]: 4:4
16214 prim_subreg_ext #(
16215 .DW (1)
16216 ) u_mio_pad_attr_25_keeper_en_25 (
16217 .re (mio_pad_attr_25_re),
16218 .we (mio_pad_attr_25_gated_we),
16219 .wd (mio_pad_attr_25_keeper_en_25_wd),
16220 .d (hw2reg.mio_pad_attr[25].keeper_en.d),
16221 .qre (),
16222 .qe (mio_pad_attr_25_flds_we[4]),
16223 .q (reg2hw.mio_pad_attr[25].keeper_en.q),
16224 .ds (),
16225 .qs (mio_pad_attr_25_keeper_en_25_qs)
16226 );
16227 1/1 assign reg2hw.mio_pad_attr[25].keeper_en.qe = mio_pad_attr_25_qe;
Tests: T1 T2 T3
16228
16229 // F[schmitt_en_25]: 5:5
16230 prim_subreg_ext #(
16231 .DW (1)
16232 ) u_mio_pad_attr_25_schmitt_en_25 (
16233 .re (mio_pad_attr_25_re),
16234 .we (mio_pad_attr_25_gated_we),
16235 .wd (mio_pad_attr_25_schmitt_en_25_wd),
16236 .d (hw2reg.mio_pad_attr[25].schmitt_en.d),
16237 .qre (),
16238 .qe (mio_pad_attr_25_flds_we[5]),
16239 .q (reg2hw.mio_pad_attr[25].schmitt_en.q),
16240 .ds (),
16241 .qs (mio_pad_attr_25_schmitt_en_25_qs)
16242 );
16243 1/1 assign reg2hw.mio_pad_attr[25].schmitt_en.qe = mio_pad_attr_25_qe;
Tests: T1 T2 T3
16244
16245 // F[od_en_25]: 6:6
16246 prim_subreg_ext #(
16247 .DW (1)
16248 ) u_mio_pad_attr_25_od_en_25 (
16249 .re (mio_pad_attr_25_re),
16250 .we (mio_pad_attr_25_gated_we),
16251 .wd (mio_pad_attr_25_od_en_25_wd),
16252 .d (hw2reg.mio_pad_attr[25].od_en.d),
16253 .qre (),
16254 .qe (mio_pad_attr_25_flds_we[6]),
16255 .q (reg2hw.mio_pad_attr[25].od_en.q),
16256 .ds (),
16257 .qs (mio_pad_attr_25_od_en_25_qs)
16258 );
16259 1/1 assign reg2hw.mio_pad_attr[25].od_en.qe = mio_pad_attr_25_qe;
Tests: T1 T2 T3
16260
16261 // F[input_disable_25]: 7:7
16262 prim_subreg_ext #(
16263 .DW (1)
16264 ) u_mio_pad_attr_25_input_disable_25 (
16265 .re (mio_pad_attr_25_re),
16266 .we (mio_pad_attr_25_gated_we),
16267 .wd (mio_pad_attr_25_input_disable_25_wd),
16268 .d (hw2reg.mio_pad_attr[25].input_disable.d),
16269 .qre (),
16270 .qe (mio_pad_attr_25_flds_we[7]),
16271 .q (reg2hw.mio_pad_attr[25].input_disable.q),
16272 .ds (),
16273 .qs (mio_pad_attr_25_input_disable_25_qs)
16274 );
16275 1/1 assign reg2hw.mio_pad_attr[25].input_disable.qe = mio_pad_attr_25_qe;
Tests: T1 T2 T3
16276
16277 // F[slew_rate_25]: 17:16
16278 prim_subreg_ext #(
16279 .DW (2)
16280 ) u_mio_pad_attr_25_slew_rate_25 (
16281 .re (mio_pad_attr_25_re),
16282 .we (mio_pad_attr_25_gated_we),
16283 .wd (mio_pad_attr_25_slew_rate_25_wd),
16284 .d (hw2reg.mio_pad_attr[25].slew_rate.d),
16285 .qre (),
16286 .qe (mio_pad_attr_25_flds_we[8]),
16287 .q (reg2hw.mio_pad_attr[25].slew_rate.q),
16288 .ds (),
16289 .qs (mio_pad_attr_25_slew_rate_25_qs)
16290 );
16291 1/1 assign reg2hw.mio_pad_attr[25].slew_rate.qe = mio_pad_attr_25_qe;
Tests: T1 T2 T3
16292
16293 // F[drive_strength_25]: 23:20
16294 prim_subreg_ext #(
16295 .DW (4)
16296 ) u_mio_pad_attr_25_drive_strength_25 (
16297 .re (mio_pad_attr_25_re),
16298 .we (mio_pad_attr_25_gated_we),
16299 .wd (mio_pad_attr_25_drive_strength_25_wd),
16300 .d (hw2reg.mio_pad_attr[25].drive_strength.d),
16301 .qre (),
16302 .qe (mio_pad_attr_25_flds_we[9]),
16303 .q (reg2hw.mio_pad_attr[25].drive_strength.q),
16304 .ds (),
16305 .qs (mio_pad_attr_25_drive_strength_25_qs)
16306 );
16307 1/1 assign reg2hw.mio_pad_attr[25].drive_strength.qe = mio_pad_attr_25_qe;
Tests: T1 T2 T3
16308
16309
16310 // Subregister 26 of Multireg mio_pad_attr
16311 // R[mio_pad_attr_26]: V(True)
16312 logic mio_pad_attr_26_qe;
16313 logic [9:0] mio_pad_attr_26_flds_we;
16314 1/1 assign mio_pad_attr_26_qe = &mio_pad_attr_26_flds_we;
Tests: T96 T97 T98
16315 // Create REGWEN-gated WE signal
16316 logic mio_pad_attr_26_gated_we;
16317 1/1 assign mio_pad_attr_26_gated_we = mio_pad_attr_26_we & mio_pad_attr_regwen_26_qs;
Tests: T96 T97 T98
16318 // F[invert_26]: 0:0
16319 prim_subreg_ext #(
16320 .DW (1)
16321 ) u_mio_pad_attr_26_invert_26 (
16322 .re (mio_pad_attr_26_re),
16323 .we (mio_pad_attr_26_gated_we),
16324 .wd (mio_pad_attr_26_invert_26_wd),
16325 .d (hw2reg.mio_pad_attr[26].invert.d),
16326 .qre (),
16327 .qe (mio_pad_attr_26_flds_we[0]),
16328 .q (reg2hw.mio_pad_attr[26].invert.q),
16329 .ds (),
16330 .qs (mio_pad_attr_26_invert_26_qs)
16331 );
16332 1/1 assign reg2hw.mio_pad_attr[26].invert.qe = mio_pad_attr_26_qe;
Tests: T96 T97 T98
16333
16334 // F[virtual_od_en_26]: 1:1
16335 prim_subreg_ext #(
16336 .DW (1)
16337 ) u_mio_pad_attr_26_virtual_od_en_26 (
16338 .re (mio_pad_attr_26_re),
16339 .we (mio_pad_attr_26_gated_we),
16340 .wd (mio_pad_attr_26_virtual_od_en_26_wd),
16341 .d (hw2reg.mio_pad_attr[26].virtual_od_en.d),
16342 .qre (),
16343 .qe (mio_pad_attr_26_flds_we[1]),
16344 .q (reg2hw.mio_pad_attr[26].virtual_od_en.q),
16345 .ds (),
16346 .qs (mio_pad_attr_26_virtual_od_en_26_qs)
16347 );
16348 1/1 assign reg2hw.mio_pad_attr[26].virtual_od_en.qe = mio_pad_attr_26_qe;
Tests: T96 T97 T98
16349
16350 // F[pull_en_26]: 2:2
16351 prim_subreg_ext #(
16352 .DW (1)
16353 ) u_mio_pad_attr_26_pull_en_26 (
16354 .re (mio_pad_attr_26_re),
16355 .we (mio_pad_attr_26_gated_we),
16356 .wd (mio_pad_attr_26_pull_en_26_wd),
16357 .d (hw2reg.mio_pad_attr[26].pull_en.d),
16358 .qre (),
16359 .qe (mio_pad_attr_26_flds_we[2]),
16360 .q (reg2hw.mio_pad_attr[26].pull_en.q),
16361 .ds (),
16362 .qs (mio_pad_attr_26_pull_en_26_qs)
16363 );
16364 1/1 assign reg2hw.mio_pad_attr[26].pull_en.qe = mio_pad_attr_26_qe;
Tests: T96 T97 T98
16365
16366 // F[pull_select_26]: 3:3
16367 prim_subreg_ext #(
16368 .DW (1)
16369 ) u_mio_pad_attr_26_pull_select_26 (
16370 .re (mio_pad_attr_26_re),
16371 .we (mio_pad_attr_26_gated_we),
16372 .wd (mio_pad_attr_26_pull_select_26_wd),
16373 .d (hw2reg.mio_pad_attr[26].pull_select.d),
16374 .qre (),
16375 .qe (mio_pad_attr_26_flds_we[3]),
16376 .q (reg2hw.mio_pad_attr[26].pull_select.q),
16377 .ds (),
16378 .qs (mio_pad_attr_26_pull_select_26_qs)
16379 );
16380 1/1 assign reg2hw.mio_pad_attr[26].pull_select.qe = mio_pad_attr_26_qe;
Tests: T96 T97 T98
16381
16382 // F[keeper_en_26]: 4:4
16383 prim_subreg_ext #(
16384 .DW (1)
16385 ) u_mio_pad_attr_26_keeper_en_26 (
16386 .re (mio_pad_attr_26_re),
16387 .we (mio_pad_attr_26_gated_we),
16388 .wd (mio_pad_attr_26_keeper_en_26_wd),
16389 .d (hw2reg.mio_pad_attr[26].keeper_en.d),
16390 .qre (),
16391 .qe (mio_pad_attr_26_flds_we[4]),
16392 .q (reg2hw.mio_pad_attr[26].keeper_en.q),
16393 .ds (),
16394 .qs (mio_pad_attr_26_keeper_en_26_qs)
16395 );
16396 1/1 assign reg2hw.mio_pad_attr[26].keeper_en.qe = mio_pad_attr_26_qe;
Tests: T96 T97 T98
16397
16398 // F[schmitt_en_26]: 5:5
16399 prim_subreg_ext #(
16400 .DW (1)
16401 ) u_mio_pad_attr_26_schmitt_en_26 (
16402 .re (mio_pad_attr_26_re),
16403 .we (mio_pad_attr_26_gated_we),
16404 .wd (mio_pad_attr_26_schmitt_en_26_wd),
16405 .d (hw2reg.mio_pad_attr[26].schmitt_en.d),
16406 .qre (),
16407 .qe (mio_pad_attr_26_flds_we[5]),
16408 .q (reg2hw.mio_pad_attr[26].schmitt_en.q),
16409 .ds (),
16410 .qs (mio_pad_attr_26_schmitt_en_26_qs)
16411 );
16412 1/1 assign reg2hw.mio_pad_attr[26].schmitt_en.qe = mio_pad_attr_26_qe;
Tests: T96 T97 T98
16413
16414 // F[od_en_26]: 6:6
16415 prim_subreg_ext #(
16416 .DW (1)
16417 ) u_mio_pad_attr_26_od_en_26 (
16418 .re (mio_pad_attr_26_re),
16419 .we (mio_pad_attr_26_gated_we),
16420 .wd (mio_pad_attr_26_od_en_26_wd),
16421 .d (hw2reg.mio_pad_attr[26].od_en.d),
16422 .qre (),
16423 .qe (mio_pad_attr_26_flds_we[6]),
16424 .q (reg2hw.mio_pad_attr[26].od_en.q),
16425 .ds (),
16426 .qs (mio_pad_attr_26_od_en_26_qs)
16427 );
16428 1/1 assign reg2hw.mio_pad_attr[26].od_en.qe = mio_pad_attr_26_qe;
Tests: T96 T97 T98
16429
16430 // F[input_disable_26]: 7:7
16431 prim_subreg_ext #(
16432 .DW (1)
16433 ) u_mio_pad_attr_26_input_disable_26 (
16434 .re (mio_pad_attr_26_re),
16435 .we (mio_pad_attr_26_gated_we),
16436 .wd (mio_pad_attr_26_input_disable_26_wd),
16437 .d (hw2reg.mio_pad_attr[26].input_disable.d),
16438 .qre (),
16439 .qe (mio_pad_attr_26_flds_we[7]),
16440 .q (reg2hw.mio_pad_attr[26].input_disable.q),
16441 .ds (),
16442 .qs (mio_pad_attr_26_input_disable_26_qs)
16443 );
16444 1/1 assign reg2hw.mio_pad_attr[26].input_disable.qe = mio_pad_attr_26_qe;
Tests: T96 T97 T98
16445
16446 // F[slew_rate_26]: 17:16
16447 prim_subreg_ext #(
16448 .DW (2)
16449 ) u_mio_pad_attr_26_slew_rate_26 (
16450 .re (mio_pad_attr_26_re),
16451 .we (mio_pad_attr_26_gated_we),
16452 .wd (mio_pad_attr_26_slew_rate_26_wd),
16453 .d (hw2reg.mio_pad_attr[26].slew_rate.d),
16454 .qre (),
16455 .qe (mio_pad_attr_26_flds_we[8]),
16456 .q (reg2hw.mio_pad_attr[26].slew_rate.q),
16457 .ds (),
16458 .qs (mio_pad_attr_26_slew_rate_26_qs)
16459 );
16460 1/1 assign reg2hw.mio_pad_attr[26].slew_rate.qe = mio_pad_attr_26_qe;
Tests: T96 T97 T98
16461
16462 // F[drive_strength_26]: 23:20
16463 prim_subreg_ext #(
16464 .DW (4)
16465 ) u_mio_pad_attr_26_drive_strength_26 (
16466 .re (mio_pad_attr_26_re),
16467 .we (mio_pad_attr_26_gated_we),
16468 .wd (mio_pad_attr_26_drive_strength_26_wd),
16469 .d (hw2reg.mio_pad_attr[26].drive_strength.d),
16470 .qre (),
16471 .qe (mio_pad_attr_26_flds_we[9]),
16472 .q (reg2hw.mio_pad_attr[26].drive_strength.q),
16473 .ds (),
16474 .qs (mio_pad_attr_26_drive_strength_26_qs)
16475 );
16476 1/1 assign reg2hw.mio_pad_attr[26].drive_strength.qe = mio_pad_attr_26_qe;
Tests: T96 T97 T98
16477
16478
16479 // Subregister 27 of Multireg mio_pad_attr
16480 // R[mio_pad_attr_27]: V(True)
16481 logic mio_pad_attr_27_qe;
16482 logic [9:0] mio_pad_attr_27_flds_we;
16483 1/1 assign mio_pad_attr_27_qe = &mio_pad_attr_27_flds_we;
Tests: T96 T97 T98
16484 // Create REGWEN-gated WE signal
16485 logic mio_pad_attr_27_gated_we;
16486 1/1 assign mio_pad_attr_27_gated_we = mio_pad_attr_27_we & mio_pad_attr_regwen_27_qs;
Tests: T71 T96 T97
16487 // F[invert_27]: 0:0
16488 prim_subreg_ext #(
16489 .DW (1)
16490 ) u_mio_pad_attr_27_invert_27 (
16491 .re (mio_pad_attr_27_re),
16492 .we (mio_pad_attr_27_gated_we),
16493 .wd (mio_pad_attr_27_invert_27_wd),
16494 .d (hw2reg.mio_pad_attr[27].invert.d),
16495 .qre (),
16496 .qe (mio_pad_attr_27_flds_we[0]),
16497 .q (reg2hw.mio_pad_attr[27].invert.q),
16498 .ds (),
16499 .qs (mio_pad_attr_27_invert_27_qs)
16500 );
16501 1/1 assign reg2hw.mio_pad_attr[27].invert.qe = mio_pad_attr_27_qe;
Tests: T96 T97 T98
16502
16503 // F[virtual_od_en_27]: 1:1
16504 prim_subreg_ext #(
16505 .DW (1)
16506 ) u_mio_pad_attr_27_virtual_od_en_27 (
16507 .re (mio_pad_attr_27_re),
16508 .we (mio_pad_attr_27_gated_we),
16509 .wd (mio_pad_attr_27_virtual_od_en_27_wd),
16510 .d (hw2reg.mio_pad_attr[27].virtual_od_en.d),
16511 .qre (),
16512 .qe (mio_pad_attr_27_flds_we[1]),
16513 .q (reg2hw.mio_pad_attr[27].virtual_od_en.q),
16514 .ds (),
16515 .qs (mio_pad_attr_27_virtual_od_en_27_qs)
16516 );
16517 1/1 assign reg2hw.mio_pad_attr[27].virtual_od_en.qe = mio_pad_attr_27_qe;
Tests: T96 T97 T98
16518
16519 // F[pull_en_27]: 2:2
16520 prim_subreg_ext #(
16521 .DW (1)
16522 ) u_mio_pad_attr_27_pull_en_27 (
16523 .re (mio_pad_attr_27_re),
16524 .we (mio_pad_attr_27_gated_we),
16525 .wd (mio_pad_attr_27_pull_en_27_wd),
16526 .d (hw2reg.mio_pad_attr[27].pull_en.d),
16527 .qre (),
16528 .qe (mio_pad_attr_27_flds_we[2]),
16529 .q (reg2hw.mio_pad_attr[27].pull_en.q),
16530 .ds (),
16531 .qs (mio_pad_attr_27_pull_en_27_qs)
16532 );
16533 1/1 assign reg2hw.mio_pad_attr[27].pull_en.qe = mio_pad_attr_27_qe;
Tests: T96 T97 T98
16534
16535 // F[pull_select_27]: 3:3
16536 prim_subreg_ext #(
16537 .DW (1)
16538 ) u_mio_pad_attr_27_pull_select_27 (
16539 .re (mio_pad_attr_27_re),
16540 .we (mio_pad_attr_27_gated_we),
16541 .wd (mio_pad_attr_27_pull_select_27_wd),
16542 .d (hw2reg.mio_pad_attr[27].pull_select.d),
16543 .qre (),
16544 .qe (mio_pad_attr_27_flds_we[3]),
16545 .q (reg2hw.mio_pad_attr[27].pull_select.q),
16546 .ds (),
16547 .qs (mio_pad_attr_27_pull_select_27_qs)
16548 );
16549 1/1 assign reg2hw.mio_pad_attr[27].pull_select.qe = mio_pad_attr_27_qe;
Tests: T96 T97 T98
16550
16551 // F[keeper_en_27]: 4:4
16552 prim_subreg_ext #(
16553 .DW (1)
16554 ) u_mio_pad_attr_27_keeper_en_27 (
16555 .re (mio_pad_attr_27_re),
16556 .we (mio_pad_attr_27_gated_we),
16557 .wd (mio_pad_attr_27_keeper_en_27_wd),
16558 .d (hw2reg.mio_pad_attr[27].keeper_en.d),
16559 .qre (),
16560 .qe (mio_pad_attr_27_flds_we[4]),
16561 .q (reg2hw.mio_pad_attr[27].keeper_en.q),
16562 .ds (),
16563 .qs (mio_pad_attr_27_keeper_en_27_qs)
16564 );
16565 1/1 assign reg2hw.mio_pad_attr[27].keeper_en.qe = mio_pad_attr_27_qe;
Tests: T96 T97 T98
16566
16567 // F[schmitt_en_27]: 5:5
16568 prim_subreg_ext #(
16569 .DW (1)
16570 ) u_mio_pad_attr_27_schmitt_en_27 (
16571 .re (mio_pad_attr_27_re),
16572 .we (mio_pad_attr_27_gated_we),
16573 .wd (mio_pad_attr_27_schmitt_en_27_wd),
16574 .d (hw2reg.mio_pad_attr[27].schmitt_en.d),
16575 .qre (),
16576 .qe (mio_pad_attr_27_flds_we[5]),
16577 .q (reg2hw.mio_pad_attr[27].schmitt_en.q),
16578 .ds (),
16579 .qs (mio_pad_attr_27_schmitt_en_27_qs)
16580 );
16581 1/1 assign reg2hw.mio_pad_attr[27].schmitt_en.qe = mio_pad_attr_27_qe;
Tests: T96 T97 T98
16582
16583 // F[od_en_27]: 6:6
16584 prim_subreg_ext #(
16585 .DW (1)
16586 ) u_mio_pad_attr_27_od_en_27 (
16587 .re (mio_pad_attr_27_re),
16588 .we (mio_pad_attr_27_gated_we),
16589 .wd (mio_pad_attr_27_od_en_27_wd),
16590 .d (hw2reg.mio_pad_attr[27].od_en.d),
16591 .qre (),
16592 .qe (mio_pad_attr_27_flds_we[6]),
16593 .q (reg2hw.mio_pad_attr[27].od_en.q),
16594 .ds (),
16595 .qs (mio_pad_attr_27_od_en_27_qs)
16596 );
16597 1/1 assign reg2hw.mio_pad_attr[27].od_en.qe = mio_pad_attr_27_qe;
Tests: T96 T97 T98
16598
16599 // F[input_disable_27]: 7:7
16600 prim_subreg_ext #(
16601 .DW (1)
16602 ) u_mio_pad_attr_27_input_disable_27 (
16603 .re (mio_pad_attr_27_re),
16604 .we (mio_pad_attr_27_gated_we),
16605 .wd (mio_pad_attr_27_input_disable_27_wd),
16606 .d (hw2reg.mio_pad_attr[27].input_disable.d),
16607 .qre (),
16608 .qe (mio_pad_attr_27_flds_we[7]),
16609 .q (reg2hw.mio_pad_attr[27].input_disable.q),
16610 .ds (),
16611 .qs (mio_pad_attr_27_input_disable_27_qs)
16612 );
16613 1/1 assign reg2hw.mio_pad_attr[27].input_disable.qe = mio_pad_attr_27_qe;
Tests: T96 T97 T98
16614
16615 // F[slew_rate_27]: 17:16
16616 prim_subreg_ext #(
16617 .DW (2)
16618 ) u_mio_pad_attr_27_slew_rate_27 (
16619 .re (mio_pad_attr_27_re),
16620 .we (mio_pad_attr_27_gated_we),
16621 .wd (mio_pad_attr_27_slew_rate_27_wd),
16622 .d (hw2reg.mio_pad_attr[27].slew_rate.d),
16623 .qre (),
16624 .qe (mio_pad_attr_27_flds_we[8]),
16625 .q (reg2hw.mio_pad_attr[27].slew_rate.q),
16626 .ds (),
16627 .qs (mio_pad_attr_27_slew_rate_27_qs)
16628 );
16629 1/1 assign reg2hw.mio_pad_attr[27].slew_rate.qe = mio_pad_attr_27_qe;
Tests: T96 T97 T98
16630
16631 // F[drive_strength_27]: 23:20
16632 prim_subreg_ext #(
16633 .DW (4)
16634 ) u_mio_pad_attr_27_drive_strength_27 (
16635 .re (mio_pad_attr_27_re),
16636 .we (mio_pad_attr_27_gated_we),
16637 .wd (mio_pad_attr_27_drive_strength_27_wd),
16638 .d (hw2reg.mio_pad_attr[27].drive_strength.d),
16639 .qre (),
16640 .qe (mio_pad_attr_27_flds_we[9]),
16641 .q (reg2hw.mio_pad_attr[27].drive_strength.q),
16642 .ds (),
16643 .qs (mio_pad_attr_27_drive_strength_27_qs)
16644 );
16645 1/1 assign reg2hw.mio_pad_attr[27].drive_strength.qe = mio_pad_attr_27_qe;
Tests: T96 T97 T98
16646
16647
16648 // Subregister 28 of Multireg mio_pad_attr
16649 // R[mio_pad_attr_28]: V(True)
16650 logic mio_pad_attr_28_qe;
16651 logic [9:0] mio_pad_attr_28_flds_we;
16652 1/1 assign mio_pad_attr_28_qe = &mio_pad_attr_28_flds_we;
Tests: T96 T97 T98
16653 // Create REGWEN-gated WE signal
16654 logic mio_pad_attr_28_gated_we;
16655 1/1 assign mio_pad_attr_28_gated_we = mio_pad_attr_28_we & mio_pad_attr_regwen_28_qs;
Tests: T71 T96 T97
16656 // F[invert_28]: 0:0
16657 prim_subreg_ext #(
16658 .DW (1)
16659 ) u_mio_pad_attr_28_invert_28 (
16660 .re (mio_pad_attr_28_re),
16661 .we (mio_pad_attr_28_gated_we),
16662 .wd (mio_pad_attr_28_invert_28_wd),
16663 .d (hw2reg.mio_pad_attr[28].invert.d),
16664 .qre (),
16665 .qe (mio_pad_attr_28_flds_we[0]),
16666 .q (reg2hw.mio_pad_attr[28].invert.q),
16667 .ds (),
16668 .qs (mio_pad_attr_28_invert_28_qs)
16669 );
16670 1/1 assign reg2hw.mio_pad_attr[28].invert.qe = mio_pad_attr_28_qe;
Tests: T96 T97 T98
16671
16672 // F[virtual_od_en_28]: 1:1
16673 prim_subreg_ext #(
16674 .DW (1)
16675 ) u_mio_pad_attr_28_virtual_od_en_28 (
16676 .re (mio_pad_attr_28_re),
16677 .we (mio_pad_attr_28_gated_we),
16678 .wd (mio_pad_attr_28_virtual_od_en_28_wd),
16679 .d (hw2reg.mio_pad_attr[28].virtual_od_en.d),
16680 .qre (),
16681 .qe (mio_pad_attr_28_flds_we[1]),
16682 .q (reg2hw.mio_pad_attr[28].virtual_od_en.q),
16683 .ds (),
16684 .qs (mio_pad_attr_28_virtual_od_en_28_qs)
16685 );
16686 1/1 assign reg2hw.mio_pad_attr[28].virtual_od_en.qe = mio_pad_attr_28_qe;
Tests: T96 T97 T98
16687
16688 // F[pull_en_28]: 2:2
16689 prim_subreg_ext #(
16690 .DW (1)
16691 ) u_mio_pad_attr_28_pull_en_28 (
16692 .re (mio_pad_attr_28_re),
16693 .we (mio_pad_attr_28_gated_we),
16694 .wd (mio_pad_attr_28_pull_en_28_wd),
16695 .d (hw2reg.mio_pad_attr[28].pull_en.d),
16696 .qre (),
16697 .qe (mio_pad_attr_28_flds_we[2]),
16698 .q (reg2hw.mio_pad_attr[28].pull_en.q),
16699 .ds (),
16700 .qs (mio_pad_attr_28_pull_en_28_qs)
16701 );
16702 1/1 assign reg2hw.mio_pad_attr[28].pull_en.qe = mio_pad_attr_28_qe;
Tests: T96 T97 T98
16703
16704 // F[pull_select_28]: 3:3
16705 prim_subreg_ext #(
16706 .DW (1)
16707 ) u_mio_pad_attr_28_pull_select_28 (
16708 .re (mio_pad_attr_28_re),
16709 .we (mio_pad_attr_28_gated_we),
16710 .wd (mio_pad_attr_28_pull_select_28_wd),
16711 .d (hw2reg.mio_pad_attr[28].pull_select.d),
16712 .qre (),
16713 .qe (mio_pad_attr_28_flds_we[3]),
16714 .q (reg2hw.mio_pad_attr[28].pull_select.q),
16715 .ds (),
16716 .qs (mio_pad_attr_28_pull_select_28_qs)
16717 );
16718 1/1 assign reg2hw.mio_pad_attr[28].pull_select.qe = mio_pad_attr_28_qe;
Tests: T96 T97 T98
16719
16720 // F[keeper_en_28]: 4:4
16721 prim_subreg_ext #(
16722 .DW (1)
16723 ) u_mio_pad_attr_28_keeper_en_28 (
16724 .re (mio_pad_attr_28_re),
16725 .we (mio_pad_attr_28_gated_we),
16726 .wd (mio_pad_attr_28_keeper_en_28_wd),
16727 .d (hw2reg.mio_pad_attr[28].keeper_en.d),
16728 .qre (),
16729 .qe (mio_pad_attr_28_flds_we[4]),
16730 .q (reg2hw.mio_pad_attr[28].keeper_en.q),
16731 .ds (),
16732 .qs (mio_pad_attr_28_keeper_en_28_qs)
16733 );
16734 1/1 assign reg2hw.mio_pad_attr[28].keeper_en.qe = mio_pad_attr_28_qe;
Tests: T96 T97 T98
16735
16736 // F[schmitt_en_28]: 5:5
16737 prim_subreg_ext #(
16738 .DW (1)
16739 ) u_mio_pad_attr_28_schmitt_en_28 (
16740 .re (mio_pad_attr_28_re),
16741 .we (mio_pad_attr_28_gated_we),
16742 .wd (mio_pad_attr_28_schmitt_en_28_wd),
16743 .d (hw2reg.mio_pad_attr[28].schmitt_en.d),
16744 .qre (),
16745 .qe (mio_pad_attr_28_flds_we[5]),
16746 .q (reg2hw.mio_pad_attr[28].schmitt_en.q),
16747 .ds (),
16748 .qs (mio_pad_attr_28_schmitt_en_28_qs)
16749 );
16750 1/1 assign reg2hw.mio_pad_attr[28].schmitt_en.qe = mio_pad_attr_28_qe;
Tests: T96 T97 T98
16751
16752 // F[od_en_28]: 6:6
16753 prim_subreg_ext #(
16754 .DW (1)
16755 ) u_mio_pad_attr_28_od_en_28 (
16756 .re (mio_pad_attr_28_re),
16757 .we (mio_pad_attr_28_gated_we),
16758 .wd (mio_pad_attr_28_od_en_28_wd),
16759 .d (hw2reg.mio_pad_attr[28].od_en.d),
16760 .qre (),
16761 .qe (mio_pad_attr_28_flds_we[6]),
16762 .q (reg2hw.mio_pad_attr[28].od_en.q),
16763 .ds (),
16764 .qs (mio_pad_attr_28_od_en_28_qs)
16765 );
16766 1/1 assign reg2hw.mio_pad_attr[28].od_en.qe = mio_pad_attr_28_qe;
Tests: T96 T97 T98
16767
16768 // F[input_disable_28]: 7:7
16769 prim_subreg_ext #(
16770 .DW (1)
16771 ) u_mio_pad_attr_28_input_disable_28 (
16772 .re (mio_pad_attr_28_re),
16773 .we (mio_pad_attr_28_gated_we),
16774 .wd (mio_pad_attr_28_input_disable_28_wd),
16775 .d (hw2reg.mio_pad_attr[28].input_disable.d),
16776 .qre (),
16777 .qe (mio_pad_attr_28_flds_we[7]),
16778 .q (reg2hw.mio_pad_attr[28].input_disable.q),
16779 .ds (),
16780 .qs (mio_pad_attr_28_input_disable_28_qs)
16781 );
16782 1/1 assign reg2hw.mio_pad_attr[28].input_disable.qe = mio_pad_attr_28_qe;
Tests: T96 T97 T98
16783
16784 // F[slew_rate_28]: 17:16
16785 prim_subreg_ext #(
16786 .DW (2)
16787 ) u_mio_pad_attr_28_slew_rate_28 (
16788 .re (mio_pad_attr_28_re),
16789 .we (mio_pad_attr_28_gated_we),
16790 .wd (mio_pad_attr_28_slew_rate_28_wd),
16791 .d (hw2reg.mio_pad_attr[28].slew_rate.d),
16792 .qre (),
16793 .qe (mio_pad_attr_28_flds_we[8]),
16794 .q (reg2hw.mio_pad_attr[28].slew_rate.q),
16795 .ds (),
16796 .qs (mio_pad_attr_28_slew_rate_28_qs)
16797 );
16798 1/1 assign reg2hw.mio_pad_attr[28].slew_rate.qe = mio_pad_attr_28_qe;
Tests: T96 T97 T98
16799
16800 // F[drive_strength_28]: 23:20
16801 prim_subreg_ext #(
16802 .DW (4)
16803 ) u_mio_pad_attr_28_drive_strength_28 (
16804 .re (mio_pad_attr_28_re),
16805 .we (mio_pad_attr_28_gated_we),
16806 .wd (mio_pad_attr_28_drive_strength_28_wd),
16807 .d (hw2reg.mio_pad_attr[28].drive_strength.d),
16808 .qre (),
16809 .qe (mio_pad_attr_28_flds_we[9]),
16810 .q (reg2hw.mio_pad_attr[28].drive_strength.q),
16811 .ds (),
16812 .qs (mio_pad_attr_28_drive_strength_28_qs)
16813 );
16814 1/1 assign reg2hw.mio_pad_attr[28].drive_strength.qe = mio_pad_attr_28_qe;
Tests: T96 T97 T98
16815
16816
16817 // Subregister 29 of Multireg mio_pad_attr
16818 // R[mio_pad_attr_29]: V(True)
16819 logic mio_pad_attr_29_qe;
16820 logic [9:0] mio_pad_attr_29_flds_we;
16821 1/1 assign mio_pad_attr_29_qe = &mio_pad_attr_29_flds_we;
Tests: T96 T97 T98
16822 // Create REGWEN-gated WE signal
16823 logic mio_pad_attr_29_gated_we;
16824 1/1 assign mio_pad_attr_29_gated_we = mio_pad_attr_29_we & mio_pad_attr_regwen_29_qs;
Tests: T71 T96 T97
16825 // F[invert_29]: 0:0
16826 prim_subreg_ext #(
16827 .DW (1)
16828 ) u_mio_pad_attr_29_invert_29 (
16829 .re (mio_pad_attr_29_re),
16830 .we (mio_pad_attr_29_gated_we),
16831 .wd (mio_pad_attr_29_invert_29_wd),
16832 .d (hw2reg.mio_pad_attr[29].invert.d),
16833 .qre (),
16834 .qe (mio_pad_attr_29_flds_we[0]),
16835 .q (reg2hw.mio_pad_attr[29].invert.q),
16836 .ds (),
16837 .qs (mio_pad_attr_29_invert_29_qs)
16838 );
16839 1/1 assign reg2hw.mio_pad_attr[29].invert.qe = mio_pad_attr_29_qe;
Tests: T96 T97 T98
16840
16841 // F[virtual_od_en_29]: 1:1
16842 prim_subreg_ext #(
16843 .DW (1)
16844 ) u_mio_pad_attr_29_virtual_od_en_29 (
16845 .re (mio_pad_attr_29_re),
16846 .we (mio_pad_attr_29_gated_we),
16847 .wd (mio_pad_attr_29_virtual_od_en_29_wd),
16848 .d (hw2reg.mio_pad_attr[29].virtual_od_en.d),
16849 .qre (),
16850 .qe (mio_pad_attr_29_flds_we[1]),
16851 .q (reg2hw.mio_pad_attr[29].virtual_od_en.q),
16852 .ds (),
16853 .qs (mio_pad_attr_29_virtual_od_en_29_qs)
16854 );
16855 1/1 assign reg2hw.mio_pad_attr[29].virtual_od_en.qe = mio_pad_attr_29_qe;
Tests: T96 T97 T98
16856
16857 // F[pull_en_29]: 2:2
16858 prim_subreg_ext #(
16859 .DW (1)
16860 ) u_mio_pad_attr_29_pull_en_29 (
16861 .re (mio_pad_attr_29_re),
16862 .we (mio_pad_attr_29_gated_we),
16863 .wd (mio_pad_attr_29_pull_en_29_wd),
16864 .d (hw2reg.mio_pad_attr[29].pull_en.d),
16865 .qre (),
16866 .qe (mio_pad_attr_29_flds_we[2]),
16867 .q (reg2hw.mio_pad_attr[29].pull_en.q),
16868 .ds (),
16869 .qs (mio_pad_attr_29_pull_en_29_qs)
16870 );
16871 1/1 assign reg2hw.mio_pad_attr[29].pull_en.qe = mio_pad_attr_29_qe;
Tests: T96 T97 T98
16872
16873 // F[pull_select_29]: 3:3
16874 prim_subreg_ext #(
16875 .DW (1)
16876 ) u_mio_pad_attr_29_pull_select_29 (
16877 .re (mio_pad_attr_29_re),
16878 .we (mio_pad_attr_29_gated_we),
16879 .wd (mio_pad_attr_29_pull_select_29_wd),
16880 .d (hw2reg.mio_pad_attr[29].pull_select.d),
16881 .qre (),
16882 .qe (mio_pad_attr_29_flds_we[3]),
16883 .q (reg2hw.mio_pad_attr[29].pull_select.q),
16884 .ds (),
16885 .qs (mio_pad_attr_29_pull_select_29_qs)
16886 );
16887 1/1 assign reg2hw.mio_pad_attr[29].pull_select.qe = mio_pad_attr_29_qe;
Tests: T96 T97 T98
16888
16889 // F[keeper_en_29]: 4:4
16890 prim_subreg_ext #(
16891 .DW (1)
16892 ) u_mio_pad_attr_29_keeper_en_29 (
16893 .re (mio_pad_attr_29_re),
16894 .we (mio_pad_attr_29_gated_we),
16895 .wd (mio_pad_attr_29_keeper_en_29_wd),
16896 .d (hw2reg.mio_pad_attr[29].keeper_en.d),
16897 .qre (),
16898 .qe (mio_pad_attr_29_flds_we[4]),
16899 .q (reg2hw.mio_pad_attr[29].keeper_en.q),
16900 .ds (),
16901 .qs (mio_pad_attr_29_keeper_en_29_qs)
16902 );
16903 1/1 assign reg2hw.mio_pad_attr[29].keeper_en.qe = mio_pad_attr_29_qe;
Tests: T96 T97 T98
16904
16905 // F[schmitt_en_29]: 5:5
16906 prim_subreg_ext #(
16907 .DW (1)
16908 ) u_mio_pad_attr_29_schmitt_en_29 (
16909 .re (mio_pad_attr_29_re),
16910 .we (mio_pad_attr_29_gated_we),
16911 .wd (mio_pad_attr_29_schmitt_en_29_wd),
16912 .d (hw2reg.mio_pad_attr[29].schmitt_en.d),
16913 .qre (),
16914 .qe (mio_pad_attr_29_flds_we[5]),
16915 .q (reg2hw.mio_pad_attr[29].schmitt_en.q),
16916 .ds (),
16917 .qs (mio_pad_attr_29_schmitt_en_29_qs)
16918 );
16919 1/1 assign reg2hw.mio_pad_attr[29].schmitt_en.qe = mio_pad_attr_29_qe;
Tests: T96 T97 T98
16920
16921 // F[od_en_29]: 6:6
16922 prim_subreg_ext #(
16923 .DW (1)
16924 ) u_mio_pad_attr_29_od_en_29 (
16925 .re (mio_pad_attr_29_re),
16926 .we (mio_pad_attr_29_gated_we),
16927 .wd (mio_pad_attr_29_od_en_29_wd),
16928 .d (hw2reg.mio_pad_attr[29].od_en.d),
16929 .qre (),
16930 .qe (mio_pad_attr_29_flds_we[6]),
16931 .q (reg2hw.mio_pad_attr[29].od_en.q),
16932 .ds (),
16933 .qs (mio_pad_attr_29_od_en_29_qs)
16934 );
16935 1/1 assign reg2hw.mio_pad_attr[29].od_en.qe = mio_pad_attr_29_qe;
Tests: T96 T97 T98
16936
16937 // F[input_disable_29]: 7:7
16938 prim_subreg_ext #(
16939 .DW (1)
16940 ) u_mio_pad_attr_29_input_disable_29 (
16941 .re (mio_pad_attr_29_re),
16942 .we (mio_pad_attr_29_gated_we),
16943 .wd (mio_pad_attr_29_input_disable_29_wd),
16944 .d (hw2reg.mio_pad_attr[29].input_disable.d),
16945 .qre (),
16946 .qe (mio_pad_attr_29_flds_we[7]),
16947 .q (reg2hw.mio_pad_attr[29].input_disable.q),
16948 .ds (),
16949 .qs (mio_pad_attr_29_input_disable_29_qs)
16950 );
16951 1/1 assign reg2hw.mio_pad_attr[29].input_disable.qe = mio_pad_attr_29_qe;
Tests: T96 T97 T98
16952
16953 // F[slew_rate_29]: 17:16
16954 prim_subreg_ext #(
16955 .DW (2)
16956 ) u_mio_pad_attr_29_slew_rate_29 (
16957 .re (mio_pad_attr_29_re),
16958 .we (mio_pad_attr_29_gated_we),
16959 .wd (mio_pad_attr_29_slew_rate_29_wd),
16960 .d (hw2reg.mio_pad_attr[29].slew_rate.d),
16961 .qre (),
16962 .qe (mio_pad_attr_29_flds_we[8]),
16963 .q (reg2hw.mio_pad_attr[29].slew_rate.q),
16964 .ds (),
16965 .qs (mio_pad_attr_29_slew_rate_29_qs)
16966 );
16967 1/1 assign reg2hw.mio_pad_attr[29].slew_rate.qe = mio_pad_attr_29_qe;
Tests: T96 T97 T98
16968
16969 // F[drive_strength_29]: 23:20
16970 prim_subreg_ext #(
16971 .DW (4)
16972 ) u_mio_pad_attr_29_drive_strength_29 (
16973 .re (mio_pad_attr_29_re),
16974 .we (mio_pad_attr_29_gated_we),
16975 .wd (mio_pad_attr_29_drive_strength_29_wd),
16976 .d (hw2reg.mio_pad_attr[29].drive_strength.d),
16977 .qre (),
16978 .qe (mio_pad_attr_29_flds_we[9]),
16979 .q (reg2hw.mio_pad_attr[29].drive_strength.q),
16980 .ds (),
16981 .qs (mio_pad_attr_29_drive_strength_29_qs)
16982 );
16983 1/1 assign reg2hw.mio_pad_attr[29].drive_strength.qe = mio_pad_attr_29_qe;
Tests: T96 T97 T98
16984
16985
16986 // Subregister 30 of Multireg mio_pad_attr
16987 // R[mio_pad_attr_30]: V(True)
16988 logic mio_pad_attr_30_qe;
16989 logic [9:0] mio_pad_attr_30_flds_we;
16990 1/1 assign mio_pad_attr_30_qe = &mio_pad_attr_30_flds_we;
Tests: T96 T97 T98
16991 // Create REGWEN-gated WE signal
16992 logic mio_pad_attr_30_gated_we;
16993 1/1 assign mio_pad_attr_30_gated_we = mio_pad_attr_30_we & mio_pad_attr_regwen_30_qs;
Tests: T71 T96 T97
16994 // F[invert_30]: 0:0
16995 prim_subreg_ext #(
16996 .DW (1)
16997 ) u_mio_pad_attr_30_invert_30 (
16998 .re (mio_pad_attr_30_re),
16999 .we (mio_pad_attr_30_gated_we),
17000 .wd (mio_pad_attr_30_invert_30_wd),
17001 .d (hw2reg.mio_pad_attr[30].invert.d),
17002 .qre (),
17003 .qe (mio_pad_attr_30_flds_we[0]),
17004 .q (reg2hw.mio_pad_attr[30].invert.q),
17005 .ds (),
17006 .qs (mio_pad_attr_30_invert_30_qs)
17007 );
17008 1/1 assign reg2hw.mio_pad_attr[30].invert.qe = mio_pad_attr_30_qe;
Tests: T96 T97 T98
17009
17010 // F[virtual_od_en_30]: 1:1
17011 prim_subreg_ext #(
17012 .DW (1)
17013 ) u_mio_pad_attr_30_virtual_od_en_30 (
17014 .re (mio_pad_attr_30_re),
17015 .we (mio_pad_attr_30_gated_we),
17016 .wd (mio_pad_attr_30_virtual_od_en_30_wd),
17017 .d (hw2reg.mio_pad_attr[30].virtual_od_en.d),
17018 .qre (),
17019 .qe (mio_pad_attr_30_flds_we[1]),
17020 .q (reg2hw.mio_pad_attr[30].virtual_od_en.q),
17021 .ds (),
17022 .qs (mio_pad_attr_30_virtual_od_en_30_qs)
17023 );
17024 1/1 assign reg2hw.mio_pad_attr[30].virtual_od_en.qe = mio_pad_attr_30_qe;
Tests: T96 T97 T98
17025
17026 // F[pull_en_30]: 2:2
17027 prim_subreg_ext #(
17028 .DW (1)
17029 ) u_mio_pad_attr_30_pull_en_30 (
17030 .re (mio_pad_attr_30_re),
17031 .we (mio_pad_attr_30_gated_we),
17032 .wd (mio_pad_attr_30_pull_en_30_wd),
17033 .d (hw2reg.mio_pad_attr[30].pull_en.d),
17034 .qre (),
17035 .qe (mio_pad_attr_30_flds_we[2]),
17036 .q (reg2hw.mio_pad_attr[30].pull_en.q),
17037 .ds (),
17038 .qs (mio_pad_attr_30_pull_en_30_qs)
17039 );
17040 1/1 assign reg2hw.mio_pad_attr[30].pull_en.qe = mio_pad_attr_30_qe;
Tests: T96 T97 T98
17041
17042 // F[pull_select_30]: 3:3
17043 prim_subreg_ext #(
17044 .DW (1)
17045 ) u_mio_pad_attr_30_pull_select_30 (
17046 .re (mio_pad_attr_30_re),
17047 .we (mio_pad_attr_30_gated_we),
17048 .wd (mio_pad_attr_30_pull_select_30_wd),
17049 .d (hw2reg.mio_pad_attr[30].pull_select.d),
17050 .qre (),
17051 .qe (mio_pad_attr_30_flds_we[3]),
17052 .q (reg2hw.mio_pad_attr[30].pull_select.q),
17053 .ds (),
17054 .qs (mio_pad_attr_30_pull_select_30_qs)
17055 );
17056 1/1 assign reg2hw.mio_pad_attr[30].pull_select.qe = mio_pad_attr_30_qe;
Tests: T96 T97 T98
17057
17058 // F[keeper_en_30]: 4:4
17059 prim_subreg_ext #(
17060 .DW (1)
17061 ) u_mio_pad_attr_30_keeper_en_30 (
17062 .re (mio_pad_attr_30_re),
17063 .we (mio_pad_attr_30_gated_we),
17064 .wd (mio_pad_attr_30_keeper_en_30_wd),
17065 .d (hw2reg.mio_pad_attr[30].keeper_en.d),
17066 .qre (),
17067 .qe (mio_pad_attr_30_flds_we[4]),
17068 .q (reg2hw.mio_pad_attr[30].keeper_en.q),
17069 .ds (),
17070 .qs (mio_pad_attr_30_keeper_en_30_qs)
17071 );
17072 1/1 assign reg2hw.mio_pad_attr[30].keeper_en.qe = mio_pad_attr_30_qe;
Tests: T96 T97 T98
17073
17074 // F[schmitt_en_30]: 5:5
17075 prim_subreg_ext #(
17076 .DW (1)
17077 ) u_mio_pad_attr_30_schmitt_en_30 (
17078 .re (mio_pad_attr_30_re),
17079 .we (mio_pad_attr_30_gated_we),
17080 .wd (mio_pad_attr_30_schmitt_en_30_wd),
17081 .d (hw2reg.mio_pad_attr[30].schmitt_en.d),
17082 .qre (),
17083 .qe (mio_pad_attr_30_flds_we[5]),
17084 .q (reg2hw.mio_pad_attr[30].schmitt_en.q),
17085 .ds (),
17086 .qs (mio_pad_attr_30_schmitt_en_30_qs)
17087 );
17088 1/1 assign reg2hw.mio_pad_attr[30].schmitt_en.qe = mio_pad_attr_30_qe;
Tests: T96 T97 T98
17089
17090 // F[od_en_30]: 6:6
17091 prim_subreg_ext #(
17092 .DW (1)
17093 ) u_mio_pad_attr_30_od_en_30 (
17094 .re (mio_pad_attr_30_re),
17095 .we (mio_pad_attr_30_gated_we),
17096 .wd (mio_pad_attr_30_od_en_30_wd),
17097 .d (hw2reg.mio_pad_attr[30].od_en.d),
17098 .qre (),
17099 .qe (mio_pad_attr_30_flds_we[6]),
17100 .q (reg2hw.mio_pad_attr[30].od_en.q),
17101 .ds (),
17102 .qs (mio_pad_attr_30_od_en_30_qs)
17103 );
17104 1/1 assign reg2hw.mio_pad_attr[30].od_en.qe = mio_pad_attr_30_qe;
Tests: T96 T97 T98
17105
17106 // F[input_disable_30]: 7:7
17107 prim_subreg_ext #(
17108 .DW (1)
17109 ) u_mio_pad_attr_30_input_disable_30 (
17110 .re (mio_pad_attr_30_re),
17111 .we (mio_pad_attr_30_gated_we),
17112 .wd (mio_pad_attr_30_input_disable_30_wd),
17113 .d (hw2reg.mio_pad_attr[30].input_disable.d),
17114 .qre (),
17115 .qe (mio_pad_attr_30_flds_we[7]),
17116 .q (reg2hw.mio_pad_attr[30].input_disable.q),
17117 .ds (),
17118 .qs (mio_pad_attr_30_input_disable_30_qs)
17119 );
17120 1/1 assign reg2hw.mio_pad_attr[30].input_disable.qe = mio_pad_attr_30_qe;
Tests: T96 T97 T98
17121
17122 // F[slew_rate_30]: 17:16
17123 prim_subreg_ext #(
17124 .DW (2)
17125 ) u_mio_pad_attr_30_slew_rate_30 (
17126 .re (mio_pad_attr_30_re),
17127 .we (mio_pad_attr_30_gated_we),
17128 .wd (mio_pad_attr_30_slew_rate_30_wd),
17129 .d (hw2reg.mio_pad_attr[30].slew_rate.d),
17130 .qre (),
17131 .qe (mio_pad_attr_30_flds_we[8]),
17132 .q (reg2hw.mio_pad_attr[30].slew_rate.q),
17133 .ds (),
17134 .qs (mio_pad_attr_30_slew_rate_30_qs)
17135 );
17136 1/1 assign reg2hw.mio_pad_attr[30].slew_rate.qe = mio_pad_attr_30_qe;
Tests: T96 T97 T98
17137
17138 // F[drive_strength_30]: 23:20
17139 prim_subreg_ext #(
17140 .DW (4)
17141 ) u_mio_pad_attr_30_drive_strength_30 (
17142 .re (mio_pad_attr_30_re),
17143 .we (mio_pad_attr_30_gated_we),
17144 .wd (mio_pad_attr_30_drive_strength_30_wd),
17145 .d (hw2reg.mio_pad_attr[30].drive_strength.d),
17146 .qre (),
17147 .qe (mio_pad_attr_30_flds_we[9]),
17148 .q (reg2hw.mio_pad_attr[30].drive_strength.q),
17149 .ds (),
17150 .qs (mio_pad_attr_30_drive_strength_30_qs)
17151 );
17152 1/1 assign reg2hw.mio_pad_attr[30].drive_strength.qe = mio_pad_attr_30_qe;
Tests: T96 T97 T98
17153
17154
17155 // Subregister 31 of Multireg mio_pad_attr
17156 // R[mio_pad_attr_31]: V(True)
17157 logic mio_pad_attr_31_qe;
17158 logic [9:0] mio_pad_attr_31_flds_we;
17159 1/1 assign mio_pad_attr_31_qe = &mio_pad_attr_31_flds_we;
Tests: T96 T97 T98
17160 // Create REGWEN-gated WE signal
17161 logic mio_pad_attr_31_gated_we;
17162 1/1 assign mio_pad_attr_31_gated_we = mio_pad_attr_31_we & mio_pad_attr_regwen_31_qs;
Tests: T96 T97 T98
17163 // F[invert_31]: 0:0
17164 prim_subreg_ext #(
17165 .DW (1)
17166 ) u_mio_pad_attr_31_invert_31 (
17167 .re (mio_pad_attr_31_re),
17168 .we (mio_pad_attr_31_gated_we),
17169 .wd (mio_pad_attr_31_invert_31_wd),
17170 .d (hw2reg.mio_pad_attr[31].invert.d),
17171 .qre (),
17172 .qe (mio_pad_attr_31_flds_we[0]),
17173 .q (reg2hw.mio_pad_attr[31].invert.q),
17174 .ds (),
17175 .qs (mio_pad_attr_31_invert_31_qs)
17176 );
17177 1/1 assign reg2hw.mio_pad_attr[31].invert.qe = mio_pad_attr_31_qe;
Tests: T96 T97 T98
17178
17179 // F[virtual_od_en_31]: 1:1
17180 prim_subreg_ext #(
17181 .DW (1)
17182 ) u_mio_pad_attr_31_virtual_od_en_31 (
17183 .re (mio_pad_attr_31_re),
17184 .we (mio_pad_attr_31_gated_we),
17185 .wd (mio_pad_attr_31_virtual_od_en_31_wd),
17186 .d (hw2reg.mio_pad_attr[31].virtual_od_en.d),
17187 .qre (),
17188 .qe (mio_pad_attr_31_flds_we[1]),
17189 .q (reg2hw.mio_pad_attr[31].virtual_od_en.q),
17190 .ds (),
17191 .qs (mio_pad_attr_31_virtual_od_en_31_qs)
17192 );
17193 1/1 assign reg2hw.mio_pad_attr[31].virtual_od_en.qe = mio_pad_attr_31_qe;
Tests: T96 T97 T98
17194
17195 // F[pull_en_31]: 2:2
17196 prim_subreg_ext #(
17197 .DW (1)
17198 ) u_mio_pad_attr_31_pull_en_31 (
17199 .re (mio_pad_attr_31_re),
17200 .we (mio_pad_attr_31_gated_we),
17201 .wd (mio_pad_attr_31_pull_en_31_wd),
17202 .d (hw2reg.mio_pad_attr[31].pull_en.d),
17203 .qre (),
17204 .qe (mio_pad_attr_31_flds_we[2]),
17205 .q (reg2hw.mio_pad_attr[31].pull_en.q),
17206 .ds (),
17207 .qs (mio_pad_attr_31_pull_en_31_qs)
17208 );
17209 1/1 assign reg2hw.mio_pad_attr[31].pull_en.qe = mio_pad_attr_31_qe;
Tests: T96 T97 T98
17210
17211 // F[pull_select_31]: 3:3
17212 prim_subreg_ext #(
17213 .DW (1)
17214 ) u_mio_pad_attr_31_pull_select_31 (
17215 .re (mio_pad_attr_31_re),
17216 .we (mio_pad_attr_31_gated_we),
17217 .wd (mio_pad_attr_31_pull_select_31_wd),
17218 .d (hw2reg.mio_pad_attr[31].pull_select.d),
17219 .qre (),
17220 .qe (mio_pad_attr_31_flds_we[3]),
17221 .q (reg2hw.mio_pad_attr[31].pull_select.q),
17222 .ds (),
17223 .qs (mio_pad_attr_31_pull_select_31_qs)
17224 );
17225 1/1 assign reg2hw.mio_pad_attr[31].pull_select.qe = mio_pad_attr_31_qe;
Tests: T96 T97 T98
17226
17227 // F[keeper_en_31]: 4:4
17228 prim_subreg_ext #(
17229 .DW (1)
17230 ) u_mio_pad_attr_31_keeper_en_31 (
17231 .re (mio_pad_attr_31_re),
17232 .we (mio_pad_attr_31_gated_we),
17233 .wd (mio_pad_attr_31_keeper_en_31_wd),
17234 .d (hw2reg.mio_pad_attr[31].keeper_en.d),
17235 .qre (),
17236 .qe (mio_pad_attr_31_flds_we[4]),
17237 .q (reg2hw.mio_pad_attr[31].keeper_en.q),
17238 .ds (),
17239 .qs (mio_pad_attr_31_keeper_en_31_qs)
17240 );
17241 1/1 assign reg2hw.mio_pad_attr[31].keeper_en.qe = mio_pad_attr_31_qe;
Tests: T96 T97 T98
17242
17243 // F[schmitt_en_31]: 5:5
17244 prim_subreg_ext #(
17245 .DW (1)
17246 ) u_mio_pad_attr_31_schmitt_en_31 (
17247 .re (mio_pad_attr_31_re),
17248 .we (mio_pad_attr_31_gated_we),
17249 .wd (mio_pad_attr_31_schmitt_en_31_wd),
17250 .d (hw2reg.mio_pad_attr[31].schmitt_en.d),
17251 .qre (),
17252 .qe (mio_pad_attr_31_flds_we[5]),
17253 .q (reg2hw.mio_pad_attr[31].schmitt_en.q),
17254 .ds (),
17255 .qs (mio_pad_attr_31_schmitt_en_31_qs)
17256 );
17257 1/1 assign reg2hw.mio_pad_attr[31].schmitt_en.qe = mio_pad_attr_31_qe;
Tests: T96 T97 T98
17258
17259 // F[od_en_31]: 6:6
17260 prim_subreg_ext #(
17261 .DW (1)
17262 ) u_mio_pad_attr_31_od_en_31 (
17263 .re (mio_pad_attr_31_re),
17264 .we (mio_pad_attr_31_gated_we),
17265 .wd (mio_pad_attr_31_od_en_31_wd),
17266 .d (hw2reg.mio_pad_attr[31].od_en.d),
17267 .qre (),
17268 .qe (mio_pad_attr_31_flds_we[6]),
17269 .q (reg2hw.mio_pad_attr[31].od_en.q),
17270 .ds (),
17271 .qs (mio_pad_attr_31_od_en_31_qs)
17272 );
17273 1/1 assign reg2hw.mio_pad_attr[31].od_en.qe = mio_pad_attr_31_qe;
Tests: T96 T97 T98
17274
17275 // F[input_disable_31]: 7:7
17276 prim_subreg_ext #(
17277 .DW (1)
17278 ) u_mio_pad_attr_31_input_disable_31 (
17279 .re (mio_pad_attr_31_re),
17280 .we (mio_pad_attr_31_gated_we),
17281 .wd (mio_pad_attr_31_input_disable_31_wd),
17282 .d (hw2reg.mio_pad_attr[31].input_disable.d),
17283 .qre (),
17284 .qe (mio_pad_attr_31_flds_we[7]),
17285 .q (reg2hw.mio_pad_attr[31].input_disable.q),
17286 .ds (),
17287 .qs (mio_pad_attr_31_input_disable_31_qs)
17288 );
17289 1/1 assign reg2hw.mio_pad_attr[31].input_disable.qe = mio_pad_attr_31_qe;
Tests: T96 T97 T98
17290
17291 // F[slew_rate_31]: 17:16
17292 prim_subreg_ext #(
17293 .DW (2)
17294 ) u_mio_pad_attr_31_slew_rate_31 (
17295 .re (mio_pad_attr_31_re),
17296 .we (mio_pad_attr_31_gated_we),
17297 .wd (mio_pad_attr_31_slew_rate_31_wd),
17298 .d (hw2reg.mio_pad_attr[31].slew_rate.d),
17299 .qre (),
17300 .qe (mio_pad_attr_31_flds_we[8]),
17301 .q (reg2hw.mio_pad_attr[31].slew_rate.q),
17302 .ds (),
17303 .qs (mio_pad_attr_31_slew_rate_31_qs)
17304 );
17305 1/1 assign reg2hw.mio_pad_attr[31].slew_rate.qe = mio_pad_attr_31_qe;
Tests: T96 T97 T98
17306
17307 // F[drive_strength_31]: 23:20
17308 prim_subreg_ext #(
17309 .DW (4)
17310 ) u_mio_pad_attr_31_drive_strength_31 (
17311 .re (mio_pad_attr_31_re),
17312 .we (mio_pad_attr_31_gated_we),
17313 .wd (mio_pad_attr_31_drive_strength_31_wd),
17314 .d (hw2reg.mio_pad_attr[31].drive_strength.d),
17315 .qre (),
17316 .qe (mio_pad_attr_31_flds_we[9]),
17317 .q (reg2hw.mio_pad_attr[31].drive_strength.q),
17318 .ds (),
17319 .qs (mio_pad_attr_31_drive_strength_31_qs)
17320 );
17321 1/1 assign reg2hw.mio_pad_attr[31].drive_strength.qe = mio_pad_attr_31_qe;
Tests: T96 T97 T98
17322
17323
17324 // Subregister 32 of Multireg mio_pad_attr
17325 // R[mio_pad_attr_32]: V(True)
17326 logic mio_pad_attr_32_qe;
17327 logic [9:0] mio_pad_attr_32_flds_we;
17328 1/1 assign mio_pad_attr_32_qe = &mio_pad_attr_32_flds_we;
Tests: T96 T97 T98
17329 // Create REGWEN-gated WE signal
17330 logic mio_pad_attr_32_gated_we;
17331 1/1 assign mio_pad_attr_32_gated_we = mio_pad_attr_32_we & mio_pad_attr_regwen_32_qs;
Tests: T96 T97 T98
17332 // F[invert_32]: 0:0
17333 prim_subreg_ext #(
17334 .DW (1)
17335 ) u_mio_pad_attr_32_invert_32 (
17336 .re (mio_pad_attr_32_re),
17337 .we (mio_pad_attr_32_gated_we),
17338 .wd (mio_pad_attr_32_invert_32_wd),
17339 .d (hw2reg.mio_pad_attr[32].invert.d),
17340 .qre (),
17341 .qe (mio_pad_attr_32_flds_we[0]),
17342 .q (reg2hw.mio_pad_attr[32].invert.q),
17343 .ds (),
17344 .qs (mio_pad_attr_32_invert_32_qs)
17345 );
17346 1/1 assign reg2hw.mio_pad_attr[32].invert.qe = mio_pad_attr_32_qe;
Tests: T96 T97 T98
17347
17348 // F[virtual_od_en_32]: 1:1
17349 prim_subreg_ext #(
17350 .DW (1)
17351 ) u_mio_pad_attr_32_virtual_od_en_32 (
17352 .re (mio_pad_attr_32_re),
17353 .we (mio_pad_attr_32_gated_we),
17354 .wd (mio_pad_attr_32_virtual_od_en_32_wd),
17355 .d (hw2reg.mio_pad_attr[32].virtual_od_en.d),
17356 .qre (),
17357 .qe (mio_pad_attr_32_flds_we[1]),
17358 .q (reg2hw.mio_pad_attr[32].virtual_od_en.q),
17359 .ds (),
17360 .qs (mio_pad_attr_32_virtual_od_en_32_qs)
17361 );
17362 1/1 assign reg2hw.mio_pad_attr[32].virtual_od_en.qe = mio_pad_attr_32_qe;
Tests: T96 T97 T98
17363
17364 // F[pull_en_32]: 2:2
17365 prim_subreg_ext #(
17366 .DW (1)
17367 ) u_mio_pad_attr_32_pull_en_32 (
17368 .re (mio_pad_attr_32_re),
17369 .we (mio_pad_attr_32_gated_we),
17370 .wd (mio_pad_attr_32_pull_en_32_wd),
17371 .d (hw2reg.mio_pad_attr[32].pull_en.d),
17372 .qre (),
17373 .qe (mio_pad_attr_32_flds_we[2]),
17374 .q (reg2hw.mio_pad_attr[32].pull_en.q),
17375 .ds (),
17376 .qs (mio_pad_attr_32_pull_en_32_qs)
17377 );
17378 1/1 assign reg2hw.mio_pad_attr[32].pull_en.qe = mio_pad_attr_32_qe;
Tests: T96 T97 T98
17379
17380 // F[pull_select_32]: 3:3
17381 prim_subreg_ext #(
17382 .DW (1)
17383 ) u_mio_pad_attr_32_pull_select_32 (
17384 .re (mio_pad_attr_32_re),
17385 .we (mio_pad_attr_32_gated_we),
17386 .wd (mio_pad_attr_32_pull_select_32_wd),
17387 .d (hw2reg.mio_pad_attr[32].pull_select.d),
17388 .qre (),
17389 .qe (mio_pad_attr_32_flds_we[3]),
17390 .q (reg2hw.mio_pad_attr[32].pull_select.q),
17391 .ds (),
17392 .qs (mio_pad_attr_32_pull_select_32_qs)
17393 );
17394 1/1 assign reg2hw.mio_pad_attr[32].pull_select.qe = mio_pad_attr_32_qe;
Tests: T96 T97 T98
17395
17396 // F[keeper_en_32]: 4:4
17397 prim_subreg_ext #(
17398 .DW (1)
17399 ) u_mio_pad_attr_32_keeper_en_32 (
17400 .re (mio_pad_attr_32_re),
17401 .we (mio_pad_attr_32_gated_we),
17402 .wd (mio_pad_attr_32_keeper_en_32_wd),
17403 .d (hw2reg.mio_pad_attr[32].keeper_en.d),
17404 .qre (),
17405 .qe (mio_pad_attr_32_flds_we[4]),
17406 .q (reg2hw.mio_pad_attr[32].keeper_en.q),
17407 .ds (),
17408 .qs (mio_pad_attr_32_keeper_en_32_qs)
17409 );
17410 1/1 assign reg2hw.mio_pad_attr[32].keeper_en.qe = mio_pad_attr_32_qe;
Tests: T96 T97 T98
17411
17412 // F[schmitt_en_32]: 5:5
17413 prim_subreg_ext #(
17414 .DW (1)
17415 ) u_mio_pad_attr_32_schmitt_en_32 (
17416 .re (mio_pad_attr_32_re),
17417 .we (mio_pad_attr_32_gated_we),
17418 .wd (mio_pad_attr_32_schmitt_en_32_wd),
17419 .d (hw2reg.mio_pad_attr[32].schmitt_en.d),
17420 .qre (),
17421 .qe (mio_pad_attr_32_flds_we[5]),
17422 .q (reg2hw.mio_pad_attr[32].schmitt_en.q),
17423 .ds (),
17424 .qs (mio_pad_attr_32_schmitt_en_32_qs)
17425 );
17426 1/1 assign reg2hw.mio_pad_attr[32].schmitt_en.qe = mio_pad_attr_32_qe;
Tests: T96 T97 T98
17427
17428 // F[od_en_32]: 6:6
17429 prim_subreg_ext #(
17430 .DW (1)
17431 ) u_mio_pad_attr_32_od_en_32 (
17432 .re (mio_pad_attr_32_re),
17433 .we (mio_pad_attr_32_gated_we),
17434 .wd (mio_pad_attr_32_od_en_32_wd),
17435 .d (hw2reg.mio_pad_attr[32].od_en.d),
17436 .qre (),
17437 .qe (mio_pad_attr_32_flds_we[6]),
17438 .q (reg2hw.mio_pad_attr[32].od_en.q),
17439 .ds (),
17440 .qs (mio_pad_attr_32_od_en_32_qs)
17441 );
17442 1/1 assign reg2hw.mio_pad_attr[32].od_en.qe = mio_pad_attr_32_qe;
Tests: T96 T97 T98
17443
17444 // F[input_disable_32]: 7:7
17445 prim_subreg_ext #(
17446 .DW (1)
17447 ) u_mio_pad_attr_32_input_disable_32 (
17448 .re (mio_pad_attr_32_re),
17449 .we (mio_pad_attr_32_gated_we),
17450 .wd (mio_pad_attr_32_input_disable_32_wd),
17451 .d (hw2reg.mio_pad_attr[32].input_disable.d),
17452 .qre (),
17453 .qe (mio_pad_attr_32_flds_we[7]),
17454 .q (reg2hw.mio_pad_attr[32].input_disable.q),
17455 .ds (),
17456 .qs (mio_pad_attr_32_input_disable_32_qs)
17457 );
17458 1/1 assign reg2hw.mio_pad_attr[32].input_disable.qe = mio_pad_attr_32_qe;
Tests: T96 T97 T98
17459
17460 // F[slew_rate_32]: 17:16
17461 prim_subreg_ext #(
17462 .DW (2)
17463 ) u_mio_pad_attr_32_slew_rate_32 (
17464 .re (mio_pad_attr_32_re),
17465 .we (mio_pad_attr_32_gated_we),
17466 .wd (mio_pad_attr_32_slew_rate_32_wd),
17467 .d (hw2reg.mio_pad_attr[32].slew_rate.d),
17468 .qre (),
17469 .qe (mio_pad_attr_32_flds_we[8]),
17470 .q (reg2hw.mio_pad_attr[32].slew_rate.q),
17471 .ds (),
17472 .qs (mio_pad_attr_32_slew_rate_32_qs)
17473 );
17474 1/1 assign reg2hw.mio_pad_attr[32].slew_rate.qe = mio_pad_attr_32_qe;
Tests: T96 T97 T98
17475
17476 // F[drive_strength_32]: 23:20
17477 prim_subreg_ext #(
17478 .DW (4)
17479 ) u_mio_pad_attr_32_drive_strength_32 (
17480 .re (mio_pad_attr_32_re),
17481 .we (mio_pad_attr_32_gated_we),
17482 .wd (mio_pad_attr_32_drive_strength_32_wd),
17483 .d (hw2reg.mio_pad_attr[32].drive_strength.d),
17484 .qre (),
17485 .qe (mio_pad_attr_32_flds_we[9]),
17486 .q (reg2hw.mio_pad_attr[32].drive_strength.q),
17487 .ds (),
17488 .qs (mio_pad_attr_32_drive_strength_32_qs)
17489 );
17490 1/1 assign reg2hw.mio_pad_attr[32].drive_strength.qe = mio_pad_attr_32_qe;
Tests: T96 T97 T98
17491
17492
17493 // Subregister 33 of Multireg mio_pad_attr
17494 // R[mio_pad_attr_33]: V(True)
17495 logic mio_pad_attr_33_qe;
17496 logic [9:0] mio_pad_attr_33_flds_we;
17497 1/1 assign mio_pad_attr_33_qe = &mio_pad_attr_33_flds_we;
Tests: T96 T97 T98
17498 // Create REGWEN-gated WE signal
17499 logic mio_pad_attr_33_gated_we;
17500 1/1 assign mio_pad_attr_33_gated_we = mio_pad_attr_33_we & mio_pad_attr_regwen_33_qs;
Tests: T71 T96 T97
17501 // F[invert_33]: 0:0
17502 prim_subreg_ext #(
17503 .DW (1)
17504 ) u_mio_pad_attr_33_invert_33 (
17505 .re (mio_pad_attr_33_re),
17506 .we (mio_pad_attr_33_gated_we),
17507 .wd (mio_pad_attr_33_invert_33_wd),
17508 .d (hw2reg.mio_pad_attr[33].invert.d),
17509 .qre (),
17510 .qe (mio_pad_attr_33_flds_we[0]),
17511 .q (reg2hw.mio_pad_attr[33].invert.q),
17512 .ds (),
17513 .qs (mio_pad_attr_33_invert_33_qs)
17514 );
17515 1/1 assign reg2hw.mio_pad_attr[33].invert.qe = mio_pad_attr_33_qe;
Tests: T96 T97 T98
17516
17517 // F[virtual_od_en_33]: 1:1
17518 prim_subreg_ext #(
17519 .DW (1)
17520 ) u_mio_pad_attr_33_virtual_od_en_33 (
17521 .re (mio_pad_attr_33_re),
17522 .we (mio_pad_attr_33_gated_we),
17523 .wd (mio_pad_attr_33_virtual_od_en_33_wd),
17524 .d (hw2reg.mio_pad_attr[33].virtual_od_en.d),
17525 .qre (),
17526 .qe (mio_pad_attr_33_flds_we[1]),
17527 .q (reg2hw.mio_pad_attr[33].virtual_od_en.q),
17528 .ds (),
17529 .qs (mio_pad_attr_33_virtual_od_en_33_qs)
17530 );
17531 1/1 assign reg2hw.mio_pad_attr[33].virtual_od_en.qe = mio_pad_attr_33_qe;
Tests: T96 T97 T98
17532
17533 // F[pull_en_33]: 2:2
17534 prim_subreg_ext #(
17535 .DW (1)
17536 ) u_mio_pad_attr_33_pull_en_33 (
17537 .re (mio_pad_attr_33_re),
17538 .we (mio_pad_attr_33_gated_we),
17539 .wd (mio_pad_attr_33_pull_en_33_wd),
17540 .d (hw2reg.mio_pad_attr[33].pull_en.d),
17541 .qre (),
17542 .qe (mio_pad_attr_33_flds_we[2]),
17543 .q (reg2hw.mio_pad_attr[33].pull_en.q),
17544 .ds (),
17545 .qs (mio_pad_attr_33_pull_en_33_qs)
17546 );
17547 1/1 assign reg2hw.mio_pad_attr[33].pull_en.qe = mio_pad_attr_33_qe;
Tests: T96 T97 T98
17548
17549 // F[pull_select_33]: 3:3
17550 prim_subreg_ext #(
17551 .DW (1)
17552 ) u_mio_pad_attr_33_pull_select_33 (
17553 .re (mio_pad_attr_33_re),
17554 .we (mio_pad_attr_33_gated_we),
17555 .wd (mio_pad_attr_33_pull_select_33_wd),
17556 .d (hw2reg.mio_pad_attr[33].pull_select.d),
17557 .qre (),
17558 .qe (mio_pad_attr_33_flds_we[3]),
17559 .q (reg2hw.mio_pad_attr[33].pull_select.q),
17560 .ds (),
17561 .qs (mio_pad_attr_33_pull_select_33_qs)
17562 );
17563 1/1 assign reg2hw.mio_pad_attr[33].pull_select.qe = mio_pad_attr_33_qe;
Tests: T96 T97 T98
17564
17565 // F[keeper_en_33]: 4:4
17566 prim_subreg_ext #(
17567 .DW (1)
17568 ) u_mio_pad_attr_33_keeper_en_33 (
17569 .re (mio_pad_attr_33_re),
17570 .we (mio_pad_attr_33_gated_we),
17571 .wd (mio_pad_attr_33_keeper_en_33_wd),
17572 .d (hw2reg.mio_pad_attr[33].keeper_en.d),
17573 .qre (),
17574 .qe (mio_pad_attr_33_flds_we[4]),
17575 .q (reg2hw.mio_pad_attr[33].keeper_en.q),
17576 .ds (),
17577 .qs (mio_pad_attr_33_keeper_en_33_qs)
17578 );
17579 1/1 assign reg2hw.mio_pad_attr[33].keeper_en.qe = mio_pad_attr_33_qe;
Tests: T96 T97 T98
17580
17581 // F[schmitt_en_33]: 5:5
17582 prim_subreg_ext #(
17583 .DW (1)
17584 ) u_mio_pad_attr_33_schmitt_en_33 (
17585 .re (mio_pad_attr_33_re),
17586 .we (mio_pad_attr_33_gated_we),
17587 .wd (mio_pad_attr_33_schmitt_en_33_wd),
17588 .d (hw2reg.mio_pad_attr[33].schmitt_en.d),
17589 .qre (),
17590 .qe (mio_pad_attr_33_flds_we[5]),
17591 .q (reg2hw.mio_pad_attr[33].schmitt_en.q),
17592 .ds (),
17593 .qs (mio_pad_attr_33_schmitt_en_33_qs)
17594 );
17595 1/1 assign reg2hw.mio_pad_attr[33].schmitt_en.qe = mio_pad_attr_33_qe;
Tests: T96 T97 T98
17596
17597 // F[od_en_33]: 6:6
17598 prim_subreg_ext #(
17599 .DW (1)
17600 ) u_mio_pad_attr_33_od_en_33 (
17601 .re (mio_pad_attr_33_re),
17602 .we (mio_pad_attr_33_gated_we),
17603 .wd (mio_pad_attr_33_od_en_33_wd),
17604 .d (hw2reg.mio_pad_attr[33].od_en.d),
17605 .qre (),
17606 .qe (mio_pad_attr_33_flds_we[6]),
17607 .q (reg2hw.mio_pad_attr[33].od_en.q),
17608 .ds (),
17609 .qs (mio_pad_attr_33_od_en_33_qs)
17610 );
17611 1/1 assign reg2hw.mio_pad_attr[33].od_en.qe = mio_pad_attr_33_qe;
Tests: T96 T97 T98
17612
17613 // F[input_disable_33]: 7:7
17614 prim_subreg_ext #(
17615 .DW (1)
17616 ) u_mio_pad_attr_33_input_disable_33 (
17617 .re (mio_pad_attr_33_re),
17618 .we (mio_pad_attr_33_gated_we),
17619 .wd (mio_pad_attr_33_input_disable_33_wd),
17620 .d (hw2reg.mio_pad_attr[33].input_disable.d),
17621 .qre (),
17622 .qe (mio_pad_attr_33_flds_we[7]),
17623 .q (reg2hw.mio_pad_attr[33].input_disable.q),
17624 .ds (),
17625 .qs (mio_pad_attr_33_input_disable_33_qs)
17626 );
17627 1/1 assign reg2hw.mio_pad_attr[33].input_disable.qe = mio_pad_attr_33_qe;
Tests: T96 T97 T98
17628
17629 // F[slew_rate_33]: 17:16
17630 prim_subreg_ext #(
17631 .DW (2)
17632 ) u_mio_pad_attr_33_slew_rate_33 (
17633 .re (mio_pad_attr_33_re),
17634 .we (mio_pad_attr_33_gated_we),
17635 .wd (mio_pad_attr_33_slew_rate_33_wd),
17636 .d (hw2reg.mio_pad_attr[33].slew_rate.d),
17637 .qre (),
17638 .qe (mio_pad_attr_33_flds_we[8]),
17639 .q (reg2hw.mio_pad_attr[33].slew_rate.q),
17640 .ds (),
17641 .qs (mio_pad_attr_33_slew_rate_33_qs)
17642 );
17643 1/1 assign reg2hw.mio_pad_attr[33].slew_rate.qe = mio_pad_attr_33_qe;
Tests: T96 T97 T98
17644
17645 // F[drive_strength_33]: 23:20
17646 prim_subreg_ext #(
17647 .DW (4)
17648 ) u_mio_pad_attr_33_drive_strength_33 (
17649 .re (mio_pad_attr_33_re),
17650 .we (mio_pad_attr_33_gated_we),
17651 .wd (mio_pad_attr_33_drive_strength_33_wd),
17652 .d (hw2reg.mio_pad_attr[33].drive_strength.d),
17653 .qre (),
17654 .qe (mio_pad_attr_33_flds_we[9]),
17655 .q (reg2hw.mio_pad_attr[33].drive_strength.q),
17656 .ds (),
17657 .qs (mio_pad_attr_33_drive_strength_33_qs)
17658 );
17659 1/1 assign reg2hw.mio_pad_attr[33].drive_strength.qe = mio_pad_attr_33_qe;
Tests: T96 T97 T98
17660
17661
17662 // Subregister 34 of Multireg mio_pad_attr
17663 // R[mio_pad_attr_34]: V(True)
17664 logic mio_pad_attr_34_qe;
17665 logic [9:0] mio_pad_attr_34_flds_we;
17666 1/1 assign mio_pad_attr_34_qe = &mio_pad_attr_34_flds_we;
Tests: T96 T97 T98
17667 // Create REGWEN-gated WE signal
17668 logic mio_pad_attr_34_gated_we;
17669 1/1 assign mio_pad_attr_34_gated_we = mio_pad_attr_34_we & mio_pad_attr_regwen_34_qs;
Tests: T96 T97 T98
17670 // F[invert_34]: 0:0
17671 prim_subreg_ext #(
17672 .DW (1)
17673 ) u_mio_pad_attr_34_invert_34 (
17674 .re (mio_pad_attr_34_re),
17675 .we (mio_pad_attr_34_gated_we),
17676 .wd (mio_pad_attr_34_invert_34_wd),
17677 .d (hw2reg.mio_pad_attr[34].invert.d),
17678 .qre (),
17679 .qe (mio_pad_attr_34_flds_we[0]),
17680 .q (reg2hw.mio_pad_attr[34].invert.q),
17681 .ds (),
17682 .qs (mio_pad_attr_34_invert_34_qs)
17683 );
17684 1/1 assign reg2hw.mio_pad_attr[34].invert.qe = mio_pad_attr_34_qe;
Tests: T96 T97 T98
17685
17686 // F[virtual_od_en_34]: 1:1
17687 prim_subreg_ext #(
17688 .DW (1)
17689 ) u_mio_pad_attr_34_virtual_od_en_34 (
17690 .re (mio_pad_attr_34_re),
17691 .we (mio_pad_attr_34_gated_we),
17692 .wd (mio_pad_attr_34_virtual_od_en_34_wd),
17693 .d (hw2reg.mio_pad_attr[34].virtual_od_en.d),
17694 .qre (),
17695 .qe (mio_pad_attr_34_flds_we[1]),
17696 .q (reg2hw.mio_pad_attr[34].virtual_od_en.q),
17697 .ds (),
17698 .qs (mio_pad_attr_34_virtual_od_en_34_qs)
17699 );
17700 1/1 assign reg2hw.mio_pad_attr[34].virtual_od_en.qe = mio_pad_attr_34_qe;
Tests: T96 T97 T98
17701
17702 // F[pull_en_34]: 2:2
17703 prim_subreg_ext #(
17704 .DW (1)
17705 ) u_mio_pad_attr_34_pull_en_34 (
17706 .re (mio_pad_attr_34_re),
17707 .we (mio_pad_attr_34_gated_we),
17708 .wd (mio_pad_attr_34_pull_en_34_wd),
17709 .d (hw2reg.mio_pad_attr[34].pull_en.d),
17710 .qre (),
17711 .qe (mio_pad_attr_34_flds_we[2]),
17712 .q (reg2hw.mio_pad_attr[34].pull_en.q),
17713 .ds (),
17714 .qs (mio_pad_attr_34_pull_en_34_qs)
17715 );
17716 1/1 assign reg2hw.mio_pad_attr[34].pull_en.qe = mio_pad_attr_34_qe;
Tests: T96 T97 T98
17717
17718 // F[pull_select_34]: 3:3
17719 prim_subreg_ext #(
17720 .DW (1)
17721 ) u_mio_pad_attr_34_pull_select_34 (
17722 .re (mio_pad_attr_34_re),
17723 .we (mio_pad_attr_34_gated_we),
17724 .wd (mio_pad_attr_34_pull_select_34_wd),
17725 .d (hw2reg.mio_pad_attr[34].pull_select.d),
17726 .qre (),
17727 .qe (mio_pad_attr_34_flds_we[3]),
17728 .q (reg2hw.mio_pad_attr[34].pull_select.q),
17729 .ds (),
17730 .qs (mio_pad_attr_34_pull_select_34_qs)
17731 );
17732 1/1 assign reg2hw.mio_pad_attr[34].pull_select.qe = mio_pad_attr_34_qe;
Tests: T96 T97 T98
17733
17734 // F[keeper_en_34]: 4:4
17735 prim_subreg_ext #(
17736 .DW (1)
17737 ) u_mio_pad_attr_34_keeper_en_34 (
17738 .re (mio_pad_attr_34_re),
17739 .we (mio_pad_attr_34_gated_we),
17740 .wd (mio_pad_attr_34_keeper_en_34_wd),
17741 .d (hw2reg.mio_pad_attr[34].keeper_en.d),
17742 .qre (),
17743 .qe (mio_pad_attr_34_flds_we[4]),
17744 .q (reg2hw.mio_pad_attr[34].keeper_en.q),
17745 .ds (),
17746 .qs (mio_pad_attr_34_keeper_en_34_qs)
17747 );
17748 1/1 assign reg2hw.mio_pad_attr[34].keeper_en.qe = mio_pad_attr_34_qe;
Tests: T96 T97 T98
17749
17750 // F[schmitt_en_34]: 5:5
17751 prim_subreg_ext #(
17752 .DW (1)
17753 ) u_mio_pad_attr_34_schmitt_en_34 (
17754 .re (mio_pad_attr_34_re),
17755 .we (mio_pad_attr_34_gated_we),
17756 .wd (mio_pad_attr_34_schmitt_en_34_wd),
17757 .d (hw2reg.mio_pad_attr[34].schmitt_en.d),
17758 .qre (),
17759 .qe (mio_pad_attr_34_flds_we[5]),
17760 .q (reg2hw.mio_pad_attr[34].schmitt_en.q),
17761 .ds (),
17762 .qs (mio_pad_attr_34_schmitt_en_34_qs)
17763 );
17764 1/1 assign reg2hw.mio_pad_attr[34].schmitt_en.qe = mio_pad_attr_34_qe;
Tests: T96 T97 T98
17765
17766 // F[od_en_34]: 6:6
17767 prim_subreg_ext #(
17768 .DW (1)
17769 ) u_mio_pad_attr_34_od_en_34 (
17770 .re (mio_pad_attr_34_re),
17771 .we (mio_pad_attr_34_gated_we),
17772 .wd (mio_pad_attr_34_od_en_34_wd),
17773 .d (hw2reg.mio_pad_attr[34].od_en.d),
17774 .qre (),
17775 .qe (mio_pad_attr_34_flds_we[6]),
17776 .q (reg2hw.mio_pad_attr[34].od_en.q),
17777 .ds (),
17778 .qs (mio_pad_attr_34_od_en_34_qs)
17779 );
17780 1/1 assign reg2hw.mio_pad_attr[34].od_en.qe = mio_pad_attr_34_qe;
Tests: T96 T97 T98
17781
17782 // F[input_disable_34]: 7:7
17783 prim_subreg_ext #(
17784 .DW (1)
17785 ) u_mio_pad_attr_34_input_disable_34 (
17786 .re (mio_pad_attr_34_re),
17787 .we (mio_pad_attr_34_gated_we),
17788 .wd (mio_pad_attr_34_input_disable_34_wd),
17789 .d (hw2reg.mio_pad_attr[34].input_disable.d),
17790 .qre (),
17791 .qe (mio_pad_attr_34_flds_we[7]),
17792 .q (reg2hw.mio_pad_attr[34].input_disable.q),
17793 .ds (),
17794 .qs (mio_pad_attr_34_input_disable_34_qs)
17795 );
17796 1/1 assign reg2hw.mio_pad_attr[34].input_disable.qe = mio_pad_attr_34_qe;
Tests: T96 T97 T98
17797
17798 // F[slew_rate_34]: 17:16
17799 prim_subreg_ext #(
17800 .DW (2)
17801 ) u_mio_pad_attr_34_slew_rate_34 (
17802 .re (mio_pad_attr_34_re),
17803 .we (mio_pad_attr_34_gated_we),
17804 .wd (mio_pad_attr_34_slew_rate_34_wd),
17805 .d (hw2reg.mio_pad_attr[34].slew_rate.d),
17806 .qre (),
17807 .qe (mio_pad_attr_34_flds_we[8]),
17808 .q (reg2hw.mio_pad_attr[34].slew_rate.q),
17809 .ds (),
17810 .qs (mio_pad_attr_34_slew_rate_34_qs)
17811 );
17812 1/1 assign reg2hw.mio_pad_attr[34].slew_rate.qe = mio_pad_attr_34_qe;
Tests: T96 T97 T98
17813
17814 // F[drive_strength_34]: 23:20
17815 prim_subreg_ext #(
17816 .DW (4)
17817 ) u_mio_pad_attr_34_drive_strength_34 (
17818 .re (mio_pad_attr_34_re),
17819 .we (mio_pad_attr_34_gated_we),
17820 .wd (mio_pad_attr_34_drive_strength_34_wd),
17821 .d (hw2reg.mio_pad_attr[34].drive_strength.d),
17822 .qre (),
17823 .qe (mio_pad_attr_34_flds_we[9]),
17824 .q (reg2hw.mio_pad_attr[34].drive_strength.q),
17825 .ds (),
17826 .qs (mio_pad_attr_34_drive_strength_34_qs)
17827 );
17828 1/1 assign reg2hw.mio_pad_attr[34].drive_strength.qe = mio_pad_attr_34_qe;
Tests: T96 T97 T98
17829
17830
17831 // Subregister 35 of Multireg mio_pad_attr
17832 // R[mio_pad_attr_35]: V(True)
17833 logic mio_pad_attr_35_qe;
17834 logic [9:0] mio_pad_attr_35_flds_we;
17835 1/1 assign mio_pad_attr_35_qe = &mio_pad_attr_35_flds_we;
Tests: T96 T97 T98
17836 // Create REGWEN-gated WE signal
17837 logic mio_pad_attr_35_gated_we;
17838 1/1 assign mio_pad_attr_35_gated_we = mio_pad_attr_35_we & mio_pad_attr_regwen_35_qs;
Tests: T71 T96 T97
17839 // F[invert_35]: 0:0
17840 prim_subreg_ext #(
17841 .DW (1)
17842 ) u_mio_pad_attr_35_invert_35 (
17843 .re (mio_pad_attr_35_re),
17844 .we (mio_pad_attr_35_gated_we),
17845 .wd (mio_pad_attr_35_invert_35_wd),
17846 .d (hw2reg.mio_pad_attr[35].invert.d),
17847 .qre (),
17848 .qe (mio_pad_attr_35_flds_we[0]),
17849 .q (reg2hw.mio_pad_attr[35].invert.q),
17850 .ds (),
17851 .qs (mio_pad_attr_35_invert_35_qs)
17852 );
17853 1/1 assign reg2hw.mio_pad_attr[35].invert.qe = mio_pad_attr_35_qe;
Tests: T96 T97 T98
17854
17855 // F[virtual_od_en_35]: 1:1
17856 prim_subreg_ext #(
17857 .DW (1)
17858 ) u_mio_pad_attr_35_virtual_od_en_35 (
17859 .re (mio_pad_attr_35_re),
17860 .we (mio_pad_attr_35_gated_we),
17861 .wd (mio_pad_attr_35_virtual_od_en_35_wd),
17862 .d (hw2reg.mio_pad_attr[35].virtual_od_en.d),
17863 .qre (),
17864 .qe (mio_pad_attr_35_flds_we[1]),
17865 .q (reg2hw.mio_pad_attr[35].virtual_od_en.q),
17866 .ds (),
17867 .qs (mio_pad_attr_35_virtual_od_en_35_qs)
17868 );
17869 1/1 assign reg2hw.mio_pad_attr[35].virtual_od_en.qe = mio_pad_attr_35_qe;
Tests: T96 T97 T98
17870
17871 // F[pull_en_35]: 2:2
17872 prim_subreg_ext #(
17873 .DW (1)
17874 ) u_mio_pad_attr_35_pull_en_35 (
17875 .re (mio_pad_attr_35_re),
17876 .we (mio_pad_attr_35_gated_we),
17877 .wd (mio_pad_attr_35_pull_en_35_wd),
17878 .d (hw2reg.mio_pad_attr[35].pull_en.d),
17879 .qre (),
17880 .qe (mio_pad_attr_35_flds_we[2]),
17881 .q (reg2hw.mio_pad_attr[35].pull_en.q),
17882 .ds (),
17883 .qs (mio_pad_attr_35_pull_en_35_qs)
17884 );
17885 1/1 assign reg2hw.mio_pad_attr[35].pull_en.qe = mio_pad_attr_35_qe;
Tests: T96 T97 T98
17886
17887 // F[pull_select_35]: 3:3
17888 prim_subreg_ext #(
17889 .DW (1)
17890 ) u_mio_pad_attr_35_pull_select_35 (
17891 .re (mio_pad_attr_35_re),
17892 .we (mio_pad_attr_35_gated_we),
17893 .wd (mio_pad_attr_35_pull_select_35_wd),
17894 .d (hw2reg.mio_pad_attr[35].pull_select.d),
17895 .qre (),
17896 .qe (mio_pad_attr_35_flds_we[3]),
17897 .q (reg2hw.mio_pad_attr[35].pull_select.q),
17898 .ds (),
17899 .qs (mio_pad_attr_35_pull_select_35_qs)
17900 );
17901 1/1 assign reg2hw.mio_pad_attr[35].pull_select.qe = mio_pad_attr_35_qe;
Tests: T96 T97 T98
17902
17903 // F[keeper_en_35]: 4:4
17904 prim_subreg_ext #(
17905 .DW (1)
17906 ) u_mio_pad_attr_35_keeper_en_35 (
17907 .re (mio_pad_attr_35_re),
17908 .we (mio_pad_attr_35_gated_we),
17909 .wd (mio_pad_attr_35_keeper_en_35_wd),
17910 .d (hw2reg.mio_pad_attr[35].keeper_en.d),
17911 .qre (),
17912 .qe (mio_pad_attr_35_flds_we[4]),
17913 .q (reg2hw.mio_pad_attr[35].keeper_en.q),
17914 .ds (),
17915 .qs (mio_pad_attr_35_keeper_en_35_qs)
17916 );
17917 1/1 assign reg2hw.mio_pad_attr[35].keeper_en.qe = mio_pad_attr_35_qe;
Tests: T96 T97 T98
17918
17919 // F[schmitt_en_35]: 5:5
17920 prim_subreg_ext #(
17921 .DW (1)
17922 ) u_mio_pad_attr_35_schmitt_en_35 (
17923 .re (mio_pad_attr_35_re),
17924 .we (mio_pad_attr_35_gated_we),
17925 .wd (mio_pad_attr_35_schmitt_en_35_wd),
17926 .d (hw2reg.mio_pad_attr[35].schmitt_en.d),
17927 .qre (),
17928 .qe (mio_pad_attr_35_flds_we[5]),
17929 .q (reg2hw.mio_pad_attr[35].schmitt_en.q),
17930 .ds (),
17931 .qs (mio_pad_attr_35_schmitt_en_35_qs)
17932 );
17933 1/1 assign reg2hw.mio_pad_attr[35].schmitt_en.qe = mio_pad_attr_35_qe;
Tests: T96 T97 T98
17934
17935 // F[od_en_35]: 6:6
17936 prim_subreg_ext #(
17937 .DW (1)
17938 ) u_mio_pad_attr_35_od_en_35 (
17939 .re (mio_pad_attr_35_re),
17940 .we (mio_pad_attr_35_gated_we),
17941 .wd (mio_pad_attr_35_od_en_35_wd),
17942 .d (hw2reg.mio_pad_attr[35].od_en.d),
17943 .qre (),
17944 .qe (mio_pad_attr_35_flds_we[6]),
17945 .q (reg2hw.mio_pad_attr[35].od_en.q),
17946 .ds (),
17947 .qs (mio_pad_attr_35_od_en_35_qs)
17948 );
17949 1/1 assign reg2hw.mio_pad_attr[35].od_en.qe = mio_pad_attr_35_qe;
Tests: T96 T97 T98
17950
17951 // F[input_disable_35]: 7:7
17952 prim_subreg_ext #(
17953 .DW (1)
17954 ) u_mio_pad_attr_35_input_disable_35 (
17955 .re (mio_pad_attr_35_re),
17956 .we (mio_pad_attr_35_gated_we),
17957 .wd (mio_pad_attr_35_input_disable_35_wd),
17958 .d (hw2reg.mio_pad_attr[35].input_disable.d),
17959 .qre (),
17960 .qe (mio_pad_attr_35_flds_we[7]),
17961 .q (reg2hw.mio_pad_attr[35].input_disable.q),
17962 .ds (),
17963 .qs (mio_pad_attr_35_input_disable_35_qs)
17964 );
17965 1/1 assign reg2hw.mio_pad_attr[35].input_disable.qe = mio_pad_attr_35_qe;
Tests: T96 T97 T98
17966
17967 // F[slew_rate_35]: 17:16
17968 prim_subreg_ext #(
17969 .DW (2)
17970 ) u_mio_pad_attr_35_slew_rate_35 (
17971 .re (mio_pad_attr_35_re),
17972 .we (mio_pad_attr_35_gated_we),
17973 .wd (mio_pad_attr_35_slew_rate_35_wd),
17974 .d (hw2reg.mio_pad_attr[35].slew_rate.d),
17975 .qre (),
17976 .qe (mio_pad_attr_35_flds_we[8]),
17977 .q (reg2hw.mio_pad_attr[35].slew_rate.q),
17978 .ds (),
17979 .qs (mio_pad_attr_35_slew_rate_35_qs)
17980 );
17981 1/1 assign reg2hw.mio_pad_attr[35].slew_rate.qe = mio_pad_attr_35_qe;
Tests: T96 T97 T98
17982
17983 // F[drive_strength_35]: 23:20
17984 prim_subreg_ext #(
17985 .DW (4)
17986 ) u_mio_pad_attr_35_drive_strength_35 (
17987 .re (mio_pad_attr_35_re),
17988 .we (mio_pad_attr_35_gated_we),
17989 .wd (mio_pad_attr_35_drive_strength_35_wd),
17990 .d (hw2reg.mio_pad_attr[35].drive_strength.d),
17991 .qre (),
17992 .qe (mio_pad_attr_35_flds_we[9]),
17993 .q (reg2hw.mio_pad_attr[35].drive_strength.q),
17994 .ds (),
17995 .qs (mio_pad_attr_35_drive_strength_35_qs)
17996 );
17997 1/1 assign reg2hw.mio_pad_attr[35].drive_strength.qe = mio_pad_attr_35_qe;
Tests: T96 T97 T98
17998
17999
18000 // Subregister 36 of Multireg mio_pad_attr
18001 // R[mio_pad_attr_36]: V(True)
18002 logic mio_pad_attr_36_qe;
18003 logic [9:0] mio_pad_attr_36_flds_we;
18004 1/1 assign mio_pad_attr_36_qe = &mio_pad_attr_36_flds_we;
Tests: T96 T97 T98
18005 // Create REGWEN-gated WE signal
18006 logic mio_pad_attr_36_gated_we;
18007 1/1 assign mio_pad_attr_36_gated_we = mio_pad_attr_36_we & mio_pad_attr_regwen_36_qs;
Tests: T71 T96 T97
18008 // F[invert_36]: 0:0
18009 prim_subreg_ext #(
18010 .DW (1)
18011 ) u_mio_pad_attr_36_invert_36 (
18012 .re (mio_pad_attr_36_re),
18013 .we (mio_pad_attr_36_gated_we),
18014 .wd (mio_pad_attr_36_invert_36_wd),
18015 .d (hw2reg.mio_pad_attr[36].invert.d),
18016 .qre (),
18017 .qe (mio_pad_attr_36_flds_we[0]),
18018 .q (reg2hw.mio_pad_attr[36].invert.q),
18019 .ds (),
18020 .qs (mio_pad_attr_36_invert_36_qs)
18021 );
18022 1/1 assign reg2hw.mio_pad_attr[36].invert.qe = mio_pad_attr_36_qe;
Tests: T96 T97 T98
18023
18024 // F[virtual_od_en_36]: 1:1
18025 prim_subreg_ext #(
18026 .DW (1)
18027 ) u_mio_pad_attr_36_virtual_od_en_36 (
18028 .re (mio_pad_attr_36_re),
18029 .we (mio_pad_attr_36_gated_we),
18030 .wd (mio_pad_attr_36_virtual_od_en_36_wd),
18031 .d (hw2reg.mio_pad_attr[36].virtual_od_en.d),
18032 .qre (),
18033 .qe (mio_pad_attr_36_flds_we[1]),
18034 .q (reg2hw.mio_pad_attr[36].virtual_od_en.q),
18035 .ds (),
18036 .qs (mio_pad_attr_36_virtual_od_en_36_qs)
18037 );
18038 1/1 assign reg2hw.mio_pad_attr[36].virtual_od_en.qe = mio_pad_attr_36_qe;
Tests: T96 T97 T98
18039
18040 // F[pull_en_36]: 2:2
18041 prim_subreg_ext #(
18042 .DW (1)
18043 ) u_mio_pad_attr_36_pull_en_36 (
18044 .re (mio_pad_attr_36_re),
18045 .we (mio_pad_attr_36_gated_we),
18046 .wd (mio_pad_attr_36_pull_en_36_wd),
18047 .d (hw2reg.mio_pad_attr[36].pull_en.d),
18048 .qre (),
18049 .qe (mio_pad_attr_36_flds_we[2]),
18050 .q (reg2hw.mio_pad_attr[36].pull_en.q),
18051 .ds (),
18052 .qs (mio_pad_attr_36_pull_en_36_qs)
18053 );
18054 1/1 assign reg2hw.mio_pad_attr[36].pull_en.qe = mio_pad_attr_36_qe;
Tests: T96 T97 T98
18055
18056 // F[pull_select_36]: 3:3
18057 prim_subreg_ext #(
18058 .DW (1)
18059 ) u_mio_pad_attr_36_pull_select_36 (
18060 .re (mio_pad_attr_36_re),
18061 .we (mio_pad_attr_36_gated_we),
18062 .wd (mio_pad_attr_36_pull_select_36_wd),
18063 .d (hw2reg.mio_pad_attr[36].pull_select.d),
18064 .qre (),
18065 .qe (mio_pad_attr_36_flds_we[3]),
18066 .q (reg2hw.mio_pad_attr[36].pull_select.q),
18067 .ds (),
18068 .qs (mio_pad_attr_36_pull_select_36_qs)
18069 );
18070 1/1 assign reg2hw.mio_pad_attr[36].pull_select.qe = mio_pad_attr_36_qe;
Tests: T96 T97 T98
18071
18072 // F[keeper_en_36]: 4:4
18073 prim_subreg_ext #(
18074 .DW (1)
18075 ) u_mio_pad_attr_36_keeper_en_36 (
18076 .re (mio_pad_attr_36_re),
18077 .we (mio_pad_attr_36_gated_we),
18078 .wd (mio_pad_attr_36_keeper_en_36_wd),
18079 .d (hw2reg.mio_pad_attr[36].keeper_en.d),
18080 .qre (),
18081 .qe (mio_pad_attr_36_flds_we[4]),
18082 .q (reg2hw.mio_pad_attr[36].keeper_en.q),
18083 .ds (),
18084 .qs (mio_pad_attr_36_keeper_en_36_qs)
18085 );
18086 1/1 assign reg2hw.mio_pad_attr[36].keeper_en.qe = mio_pad_attr_36_qe;
Tests: T96 T97 T98
18087
18088 // F[schmitt_en_36]: 5:5
18089 prim_subreg_ext #(
18090 .DW (1)
18091 ) u_mio_pad_attr_36_schmitt_en_36 (
18092 .re (mio_pad_attr_36_re),
18093 .we (mio_pad_attr_36_gated_we),
18094 .wd (mio_pad_attr_36_schmitt_en_36_wd),
18095 .d (hw2reg.mio_pad_attr[36].schmitt_en.d),
18096 .qre (),
18097 .qe (mio_pad_attr_36_flds_we[5]),
18098 .q (reg2hw.mio_pad_attr[36].schmitt_en.q),
18099 .ds (),
18100 .qs (mio_pad_attr_36_schmitt_en_36_qs)
18101 );
18102 1/1 assign reg2hw.mio_pad_attr[36].schmitt_en.qe = mio_pad_attr_36_qe;
Tests: T96 T97 T98
18103
18104 // F[od_en_36]: 6:6
18105 prim_subreg_ext #(
18106 .DW (1)
18107 ) u_mio_pad_attr_36_od_en_36 (
18108 .re (mio_pad_attr_36_re),
18109 .we (mio_pad_attr_36_gated_we),
18110 .wd (mio_pad_attr_36_od_en_36_wd),
18111 .d (hw2reg.mio_pad_attr[36].od_en.d),
18112 .qre (),
18113 .qe (mio_pad_attr_36_flds_we[6]),
18114 .q (reg2hw.mio_pad_attr[36].od_en.q),
18115 .ds (),
18116 .qs (mio_pad_attr_36_od_en_36_qs)
18117 );
18118 1/1 assign reg2hw.mio_pad_attr[36].od_en.qe = mio_pad_attr_36_qe;
Tests: T96 T97 T98
18119
18120 // F[input_disable_36]: 7:7
18121 prim_subreg_ext #(
18122 .DW (1)
18123 ) u_mio_pad_attr_36_input_disable_36 (
18124 .re (mio_pad_attr_36_re),
18125 .we (mio_pad_attr_36_gated_we),
18126 .wd (mio_pad_attr_36_input_disable_36_wd),
18127 .d (hw2reg.mio_pad_attr[36].input_disable.d),
18128 .qre (),
18129 .qe (mio_pad_attr_36_flds_we[7]),
18130 .q (reg2hw.mio_pad_attr[36].input_disable.q),
18131 .ds (),
18132 .qs (mio_pad_attr_36_input_disable_36_qs)
18133 );
18134 1/1 assign reg2hw.mio_pad_attr[36].input_disable.qe = mio_pad_attr_36_qe;
Tests: T96 T97 T98
18135
18136 // F[slew_rate_36]: 17:16
18137 prim_subreg_ext #(
18138 .DW (2)
18139 ) u_mio_pad_attr_36_slew_rate_36 (
18140 .re (mio_pad_attr_36_re),
18141 .we (mio_pad_attr_36_gated_we),
18142 .wd (mio_pad_attr_36_slew_rate_36_wd),
18143 .d (hw2reg.mio_pad_attr[36].slew_rate.d),
18144 .qre (),
18145 .qe (mio_pad_attr_36_flds_we[8]),
18146 .q (reg2hw.mio_pad_attr[36].slew_rate.q),
18147 .ds (),
18148 .qs (mio_pad_attr_36_slew_rate_36_qs)
18149 );
18150 1/1 assign reg2hw.mio_pad_attr[36].slew_rate.qe = mio_pad_attr_36_qe;
Tests: T96 T97 T98
18151
18152 // F[drive_strength_36]: 23:20
18153 prim_subreg_ext #(
18154 .DW (4)
18155 ) u_mio_pad_attr_36_drive_strength_36 (
18156 .re (mio_pad_attr_36_re),
18157 .we (mio_pad_attr_36_gated_we),
18158 .wd (mio_pad_attr_36_drive_strength_36_wd),
18159 .d (hw2reg.mio_pad_attr[36].drive_strength.d),
18160 .qre (),
18161 .qe (mio_pad_attr_36_flds_we[9]),
18162 .q (reg2hw.mio_pad_attr[36].drive_strength.q),
18163 .ds (),
18164 .qs (mio_pad_attr_36_drive_strength_36_qs)
18165 );
18166 1/1 assign reg2hw.mio_pad_attr[36].drive_strength.qe = mio_pad_attr_36_qe;
Tests: T96 T97 T98
18167
18168
18169 // Subregister 37 of Multireg mio_pad_attr
18170 // R[mio_pad_attr_37]: V(True)
18171 logic mio_pad_attr_37_qe;
18172 logic [9:0] mio_pad_attr_37_flds_we;
18173 1/1 assign mio_pad_attr_37_qe = &mio_pad_attr_37_flds_we;
Tests: T96 T97 T98
18174 // Create REGWEN-gated WE signal
18175 logic mio_pad_attr_37_gated_we;
18176 1/1 assign mio_pad_attr_37_gated_we = mio_pad_attr_37_we & mio_pad_attr_regwen_37_qs;
Tests: T96 T97 T98
18177 // F[invert_37]: 0:0
18178 prim_subreg_ext #(
18179 .DW (1)
18180 ) u_mio_pad_attr_37_invert_37 (
18181 .re (mio_pad_attr_37_re),
18182 .we (mio_pad_attr_37_gated_we),
18183 .wd (mio_pad_attr_37_invert_37_wd),
18184 .d (hw2reg.mio_pad_attr[37].invert.d),
18185 .qre (),
18186 .qe (mio_pad_attr_37_flds_we[0]),
18187 .q (reg2hw.mio_pad_attr[37].invert.q),
18188 .ds (),
18189 .qs (mio_pad_attr_37_invert_37_qs)
18190 );
18191 1/1 assign reg2hw.mio_pad_attr[37].invert.qe = mio_pad_attr_37_qe;
Tests: T96 T97 T98
18192
18193 // F[virtual_od_en_37]: 1:1
18194 prim_subreg_ext #(
18195 .DW (1)
18196 ) u_mio_pad_attr_37_virtual_od_en_37 (
18197 .re (mio_pad_attr_37_re),
18198 .we (mio_pad_attr_37_gated_we),
18199 .wd (mio_pad_attr_37_virtual_od_en_37_wd),
18200 .d (hw2reg.mio_pad_attr[37].virtual_od_en.d),
18201 .qre (),
18202 .qe (mio_pad_attr_37_flds_we[1]),
18203 .q (reg2hw.mio_pad_attr[37].virtual_od_en.q),
18204 .ds (),
18205 .qs (mio_pad_attr_37_virtual_od_en_37_qs)
18206 );
18207 1/1 assign reg2hw.mio_pad_attr[37].virtual_od_en.qe = mio_pad_attr_37_qe;
Tests: T96 T97 T98
18208
18209 // F[pull_en_37]: 2:2
18210 prim_subreg_ext #(
18211 .DW (1)
18212 ) u_mio_pad_attr_37_pull_en_37 (
18213 .re (mio_pad_attr_37_re),
18214 .we (mio_pad_attr_37_gated_we),
18215 .wd (mio_pad_attr_37_pull_en_37_wd),
18216 .d (hw2reg.mio_pad_attr[37].pull_en.d),
18217 .qre (),
18218 .qe (mio_pad_attr_37_flds_we[2]),
18219 .q (reg2hw.mio_pad_attr[37].pull_en.q),
18220 .ds (),
18221 .qs (mio_pad_attr_37_pull_en_37_qs)
18222 );
18223 1/1 assign reg2hw.mio_pad_attr[37].pull_en.qe = mio_pad_attr_37_qe;
Tests: T96 T97 T98
18224
18225 // F[pull_select_37]: 3:3
18226 prim_subreg_ext #(
18227 .DW (1)
18228 ) u_mio_pad_attr_37_pull_select_37 (
18229 .re (mio_pad_attr_37_re),
18230 .we (mio_pad_attr_37_gated_we),
18231 .wd (mio_pad_attr_37_pull_select_37_wd),
18232 .d (hw2reg.mio_pad_attr[37].pull_select.d),
18233 .qre (),
18234 .qe (mio_pad_attr_37_flds_we[3]),
18235 .q (reg2hw.mio_pad_attr[37].pull_select.q),
18236 .ds (),
18237 .qs (mio_pad_attr_37_pull_select_37_qs)
18238 );
18239 1/1 assign reg2hw.mio_pad_attr[37].pull_select.qe = mio_pad_attr_37_qe;
Tests: T96 T97 T98
18240
18241 // F[keeper_en_37]: 4:4
18242 prim_subreg_ext #(
18243 .DW (1)
18244 ) u_mio_pad_attr_37_keeper_en_37 (
18245 .re (mio_pad_attr_37_re),
18246 .we (mio_pad_attr_37_gated_we),
18247 .wd (mio_pad_attr_37_keeper_en_37_wd),
18248 .d (hw2reg.mio_pad_attr[37].keeper_en.d),
18249 .qre (),
18250 .qe (mio_pad_attr_37_flds_we[4]),
18251 .q (reg2hw.mio_pad_attr[37].keeper_en.q),
18252 .ds (),
18253 .qs (mio_pad_attr_37_keeper_en_37_qs)
18254 );
18255 1/1 assign reg2hw.mio_pad_attr[37].keeper_en.qe = mio_pad_attr_37_qe;
Tests: T96 T97 T98
18256
18257 // F[schmitt_en_37]: 5:5
18258 prim_subreg_ext #(
18259 .DW (1)
18260 ) u_mio_pad_attr_37_schmitt_en_37 (
18261 .re (mio_pad_attr_37_re),
18262 .we (mio_pad_attr_37_gated_we),
18263 .wd (mio_pad_attr_37_schmitt_en_37_wd),
18264 .d (hw2reg.mio_pad_attr[37].schmitt_en.d),
18265 .qre (),
18266 .qe (mio_pad_attr_37_flds_we[5]),
18267 .q (reg2hw.mio_pad_attr[37].schmitt_en.q),
18268 .ds (),
18269 .qs (mio_pad_attr_37_schmitt_en_37_qs)
18270 );
18271 1/1 assign reg2hw.mio_pad_attr[37].schmitt_en.qe = mio_pad_attr_37_qe;
Tests: T96 T97 T98
18272
18273 // F[od_en_37]: 6:6
18274 prim_subreg_ext #(
18275 .DW (1)
18276 ) u_mio_pad_attr_37_od_en_37 (
18277 .re (mio_pad_attr_37_re),
18278 .we (mio_pad_attr_37_gated_we),
18279 .wd (mio_pad_attr_37_od_en_37_wd),
18280 .d (hw2reg.mio_pad_attr[37].od_en.d),
18281 .qre (),
18282 .qe (mio_pad_attr_37_flds_we[6]),
18283 .q (reg2hw.mio_pad_attr[37].od_en.q),
18284 .ds (),
18285 .qs (mio_pad_attr_37_od_en_37_qs)
18286 );
18287 1/1 assign reg2hw.mio_pad_attr[37].od_en.qe = mio_pad_attr_37_qe;
Tests: T96 T97 T98
18288
18289 // F[input_disable_37]: 7:7
18290 prim_subreg_ext #(
18291 .DW (1)
18292 ) u_mio_pad_attr_37_input_disable_37 (
18293 .re (mio_pad_attr_37_re),
18294 .we (mio_pad_attr_37_gated_we),
18295 .wd (mio_pad_attr_37_input_disable_37_wd),
18296 .d (hw2reg.mio_pad_attr[37].input_disable.d),
18297 .qre (),
18298 .qe (mio_pad_attr_37_flds_we[7]),
18299 .q (reg2hw.mio_pad_attr[37].input_disable.q),
18300 .ds (),
18301 .qs (mio_pad_attr_37_input_disable_37_qs)
18302 );
18303 1/1 assign reg2hw.mio_pad_attr[37].input_disable.qe = mio_pad_attr_37_qe;
Tests: T96 T97 T98
18304
18305 // F[slew_rate_37]: 17:16
18306 prim_subreg_ext #(
18307 .DW (2)
18308 ) u_mio_pad_attr_37_slew_rate_37 (
18309 .re (mio_pad_attr_37_re),
18310 .we (mio_pad_attr_37_gated_we),
18311 .wd (mio_pad_attr_37_slew_rate_37_wd),
18312 .d (hw2reg.mio_pad_attr[37].slew_rate.d),
18313 .qre (),
18314 .qe (mio_pad_attr_37_flds_we[8]),
18315 .q (reg2hw.mio_pad_attr[37].slew_rate.q),
18316 .ds (),
18317 .qs (mio_pad_attr_37_slew_rate_37_qs)
18318 );
18319 1/1 assign reg2hw.mio_pad_attr[37].slew_rate.qe = mio_pad_attr_37_qe;
Tests: T96 T97 T98
18320
18321 // F[drive_strength_37]: 23:20
18322 prim_subreg_ext #(
18323 .DW (4)
18324 ) u_mio_pad_attr_37_drive_strength_37 (
18325 .re (mio_pad_attr_37_re),
18326 .we (mio_pad_attr_37_gated_we),
18327 .wd (mio_pad_attr_37_drive_strength_37_wd),
18328 .d (hw2reg.mio_pad_attr[37].drive_strength.d),
18329 .qre (),
18330 .qe (mio_pad_attr_37_flds_we[9]),
18331 .q (reg2hw.mio_pad_attr[37].drive_strength.q),
18332 .ds (),
18333 .qs (mio_pad_attr_37_drive_strength_37_qs)
18334 );
18335 1/1 assign reg2hw.mio_pad_attr[37].drive_strength.qe = mio_pad_attr_37_qe;
Tests: T96 T97 T98
18336
18337
18338 // Subregister 38 of Multireg mio_pad_attr
18339 // R[mio_pad_attr_38]: V(True)
18340 logic mio_pad_attr_38_qe;
18341 logic [9:0] mio_pad_attr_38_flds_we;
18342 1/1 assign mio_pad_attr_38_qe = &mio_pad_attr_38_flds_we;
Tests: T96 T97 T98
18343 // Create REGWEN-gated WE signal
18344 logic mio_pad_attr_38_gated_we;
18345 1/1 assign mio_pad_attr_38_gated_we = mio_pad_attr_38_we & mio_pad_attr_regwen_38_qs;
Tests: T71 T96 T97
18346 // F[invert_38]: 0:0
18347 prim_subreg_ext #(
18348 .DW (1)
18349 ) u_mio_pad_attr_38_invert_38 (
18350 .re (mio_pad_attr_38_re),
18351 .we (mio_pad_attr_38_gated_we),
18352 .wd (mio_pad_attr_38_invert_38_wd),
18353 .d (hw2reg.mio_pad_attr[38].invert.d),
18354 .qre (),
18355 .qe (mio_pad_attr_38_flds_we[0]),
18356 .q (reg2hw.mio_pad_attr[38].invert.q),
18357 .ds (),
18358 .qs (mio_pad_attr_38_invert_38_qs)
18359 );
18360 1/1 assign reg2hw.mio_pad_attr[38].invert.qe = mio_pad_attr_38_qe;
Tests: T96 T97 T98
18361
18362 // F[virtual_od_en_38]: 1:1
18363 prim_subreg_ext #(
18364 .DW (1)
18365 ) u_mio_pad_attr_38_virtual_od_en_38 (
18366 .re (mio_pad_attr_38_re),
18367 .we (mio_pad_attr_38_gated_we),
18368 .wd (mio_pad_attr_38_virtual_od_en_38_wd),
18369 .d (hw2reg.mio_pad_attr[38].virtual_od_en.d),
18370 .qre (),
18371 .qe (mio_pad_attr_38_flds_we[1]),
18372 .q (reg2hw.mio_pad_attr[38].virtual_od_en.q),
18373 .ds (),
18374 .qs (mio_pad_attr_38_virtual_od_en_38_qs)
18375 );
18376 1/1 assign reg2hw.mio_pad_attr[38].virtual_od_en.qe = mio_pad_attr_38_qe;
Tests: T96 T97 T98
18377
18378 // F[pull_en_38]: 2:2
18379 prim_subreg_ext #(
18380 .DW (1)
18381 ) u_mio_pad_attr_38_pull_en_38 (
18382 .re (mio_pad_attr_38_re),
18383 .we (mio_pad_attr_38_gated_we),
18384 .wd (mio_pad_attr_38_pull_en_38_wd),
18385 .d (hw2reg.mio_pad_attr[38].pull_en.d),
18386 .qre (),
18387 .qe (mio_pad_attr_38_flds_we[2]),
18388 .q (reg2hw.mio_pad_attr[38].pull_en.q),
18389 .ds (),
18390 .qs (mio_pad_attr_38_pull_en_38_qs)
18391 );
18392 1/1 assign reg2hw.mio_pad_attr[38].pull_en.qe = mio_pad_attr_38_qe;
Tests: T96 T97 T98
18393
18394 // F[pull_select_38]: 3:3
18395 prim_subreg_ext #(
18396 .DW (1)
18397 ) u_mio_pad_attr_38_pull_select_38 (
18398 .re (mio_pad_attr_38_re),
18399 .we (mio_pad_attr_38_gated_we),
18400 .wd (mio_pad_attr_38_pull_select_38_wd),
18401 .d (hw2reg.mio_pad_attr[38].pull_select.d),
18402 .qre (),
18403 .qe (mio_pad_attr_38_flds_we[3]),
18404 .q (reg2hw.mio_pad_attr[38].pull_select.q),
18405 .ds (),
18406 .qs (mio_pad_attr_38_pull_select_38_qs)
18407 );
18408 1/1 assign reg2hw.mio_pad_attr[38].pull_select.qe = mio_pad_attr_38_qe;
Tests: T96 T97 T98
18409
18410 // F[keeper_en_38]: 4:4
18411 prim_subreg_ext #(
18412 .DW (1)
18413 ) u_mio_pad_attr_38_keeper_en_38 (
18414 .re (mio_pad_attr_38_re),
18415 .we (mio_pad_attr_38_gated_we),
18416 .wd (mio_pad_attr_38_keeper_en_38_wd),
18417 .d (hw2reg.mio_pad_attr[38].keeper_en.d),
18418 .qre (),
18419 .qe (mio_pad_attr_38_flds_we[4]),
18420 .q (reg2hw.mio_pad_attr[38].keeper_en.q),
18421 .ds (),
18422 .qs (mio_pad_attr_38_keeper_en_38_qs)
18423 );
18424 1/1 assign reg2hw.mio_pad_attr[38].keeper_en.qe = mio_pad_attr_38_qe;
Tests: T96 T97 T98
18425
18426 // F[schmitt_en_38]: 5:5
18427 prim_subreg_ext #(
18428 .DW (1)
18429 ) u_mio_pad_attr_38_schmitt_en_38 (
18430 .re (mio_pad_attr_38_re),
18431 .we (mio_pad_attr_38_gated_we),
18432 .wd (mio_pad_attr_38_schmitt_en_38_wd),
18433 .d (hw2reg.mio_pad_attr[38].schmitt_en.d),
18434 .qre (),
18435 .qe (mio_pad_attr_38_flds_we[5]),
18436 .q (reg2hw.mio_pad_attr[38].schmitt_en.q),
18437 .ds (),
18438 .qs (mio_pad_attr_38_schmitt_en_38_qs)
18439 );
18440 1/1 assign reg2hw.mio_pad_attr[38].schmitt_en.qe = mio_pad_attr_38_qe;
Tests: T96 T97 T98
18441
18442 // F[od_en_38]: 6:6
18443 prim_subreg_ext #(
18444 .DW (1)
18445 ) u_mio_pad_attr_38_od_en_38 (
18446 .re (mio_pad_attr_38_re),
18447 .we (mio_pad_attr_38_gated_we),
18448 .wd (mio_pad_attr_38_od_en_38_wd),
18449 .d (hw2reg.mio_pad_attr[38].od_en.d),
18450 .qre (),
18451 .qe (mio_pad_attr_38_flds_we[6]),
18452 .q (reg2hw.mio_pad_attr[38].od_en.q),
18453 .ds (),
18454 .qs (mio_pad_attr_38_od_en_38_qs)
18455 );
18456 1/1 assign reg2hw.mio_pad_attr[38].od_en.qe = mio_pad_attr_38_qe;
Tests: T96 T97 T98
18457
18458 // F[input_disable_38]: 7:7
18459 prim_subreg_ext #(
18460 .DW (1)
18461 ) u_mio_pad_attr_38_input_disable_38 (
18462 .re (mio_pad_attr_38_re),
18463 .we (mio_pad_attr_38_gated_we),
18464 .wd (mio_pad_attr_38_input_disable_38_wd),
18465 .d (hw2reg.mio_pad_attr[38].input_disable.d),
18466 .qre (),
18467 .qe (mio_pad_attr_38_flds_we[7]),
18468 .q (reg2hw.mio_pad_attr[38].input_disable.q),
18469 .ds (),
18470 .qs (mio_pad_attr_38_input_disable_38_qs)
18471 );
18472 1/1 assign reg2hw.mio_pad_attr[38].input_disable.qe = mio_pad_attr_38_qe;
Tests: T96 T97 T98
18473
18474 // F[slew_rate_38]: 17:16
18475 prim_subreg_ext #(
18476 .DW (2)
18477 ) u_mio_pad_attr_38_slew_rate_38 (
18478 .re (mio_pad_attr_38_re),
18479 .we (mio_pad_attr_38_gated_we),
18480 .wd (mio_pad_attr_38_slew_rate_38_wd),
18481 .d (hw2reg.mio_pad_attr[38].slew_rate.d),
18482 .qre (),
18483 .qe (mio_pad_attr_38_flds_we[8]),
18484 .q (reg2hw.mio_pad_attr[38].slew_rate.q),
18485 .ds (),
18486 .qs (mio_pad_attr_38_slew_rate_38_qs)
18487 );
18488 1/1 assign reg2hw.mio_pad_attr[38].slew_rate.qe = mio_pad_attr_38_qe;
Tests: T96 T97 T98
18489
18490 // F[drive_strength_38]: 23:20
18491 prim_subreg_ext #(
18492 .DW (4)
18493 ) u_mio_pad_attr_38_drive_strength_38 (
18494 .re (mio_pad_attr_38_re),
18495 .we (mio_pad_attr_38_gated_we),
18496 .wd (mio_pad_attr_38_drive_strength_38_wd),
18497 .d (hw2reg.mio_pad_attr[38].drive_strength.d),
18498 .qre (),
18499 .qe (mio_pad_attr_38_flds_we[9]),
18500 .q (reg2hw.mio_pad_attr[38].drive_strength.q),
18501 .ds (),
18502 .qs (mio_pad_attr_38_drive_strength_38_qs)
18503 );
18504 1/1 assign reg2hw.mio_pad_attr[38].drive_strength.qe = mio_pad_attr_38_qe;
Tests: T96 T97 T98
18505
18506
18507 // Subregister 39 of Multireg mio_pad_attr
18508 // R[mio_pad_attr_39]: V(True)
18509 logic mio_pad_attr_39_qe;
18510 logic [9:0] mio_pad_attr_39_flds_we;
18511 1/1 assign mio_pad_attr_39_qe = &mio_pad_attr_39_flds_we;
Tests: T96 T97 T98
18512 // Create REGWEN-gated WE signal
18513 logic mio_pad_attr_39_gated_we;
18514 1/1 assign mio_pad_attr_39_gated_we = mio_pad_attr_39_we & mio_pad_attr_regwen_39_qs;
Tests: T71 T96 T97
18515 // F[invert_39]: 0:0
18516 prim_subreg_ext #(
18517 .DW (1)
18518 ) u_mio_pad_attr_39_invert_39 (
18519 .re (mio_pad_attr_39_re),
18520 .we (mio_pad_attr_39_gated_we),
18521 .wd (mio_pad_attr_39_invert_39_wd),
18522 .d (hw2reg.mio_pad_attr[39].invert.d),
18523 .qre (),
18524 .qe (mio_pad_attr_39_flds_we[0]),
18525 .q (reg2hw.mio_pad_attr[39].invert.q),
18526 .ds (),
18527 .qs (mio_pad_attr_39_invert_39_qs)
18528 );
18529 1/1 assign reg2hw.mio_pad_attr[39].invert.qe = mio_pad_attr_39_qe;
Tests: T96 T97 T98
18530
18531 // F[virtual_od_en_39]: 1:1
18532 prim_subreg_ext #(
18533 .DW (1)
18534 ) u_mio_pad_attr_39_virtual_od_en_39 (
18535 .re (mio_pad_attr_39_re),
18536 .we (mio_pad_attr_39_gated_we),
18537 .wd (mio_pad_attr_39_virtual_od_en_39_wd),
18538 .d (hw2reg.mio_pad_attr[39].virtual_od_en.d),
18539 .qre (),
18540 .qe (mio_pad_attr_39_flds_we[1]),
18541 .q (reg2hw.mio_pad_attr[39].virtual_od_en.q),
18542 .ds (),
18543 .qs (mio_pad_attr_39_virtual_od_en_39_qs)
18544 );
18545 1/1 assign reg2hw.mio_pad_attr[39].virtual_od_en.qe = mio_pad_attr_39_qe;
Tests: T96 T97 T98
18546
18547 // F[pull_en_39]: 2:2
18548 prim_subreg_ext #(
18549 .DW (1)
18550 ) u_mio_pad_attr_39_pull_en_39 (
18551 .re (mio_pad_attr_39_re),
18552 .we (mio_pad_attr_39_gated_we),
18553 .wd (mio_pad_attr_39_pull_en_39_wd),
18554 .d (hw2reg.mio_pad_attr[39].pull_en.d),
18555 .qre (),
18556 .qe (mio_pad_attr_39_flds_we[2]),
18557 .q (reg2hw.mio_pad_attr[39].pull_en.q),
18558 .ds (),
18559 .qs (mio_pad_attr_39_pull_en_39_qs)
18560 );
18561 1/1 assign reg2hw.mio_pad_attr[39].pull_en.qe = mio_pad_attr_39_qe;
Tests: T96 T97 T98
18562
18563 // F[pull_select_39]: 3:3
18564 prim_subreg_ext #(
18565 .DW (1)
18566 ) u_mio_pad_attr_39_pull_select_39 (
18567 .re (mio_pad_attr_39_re),
18568 .we (mio_pad_attr_39_gated_we),
18569 .wd (mio_pad_attr_39_pull_select_39_wd),
18570 .d (hw2reg.mio_pad_attr[39].pull_select.d),
18571 .qre (),
18572 .qe (mio_pad_attr_39_flds_we[3]),
18573 .q (reg2hw.mio_pad_attr[39].pull_select.q),
18574 .ds (),
18575 .qs (mio_pad_attr_39_pull_select_39_qs)
18576 );
18577 1/1 assign reg2hw.mio_pad_attr[39].pull_select.qe = mio_pad_attr_39_qe;
Tests: T96 T97 T98
18578
18579 // F[keeper_en_39]: 4:4
18580 prim_subreg_ext #(
18581 .DW (1)
18582 ) u_mio_pad_attr_39_keeper_en_39 (
18583 .re (mio_pad_attr_39_re),
18584 .we (mio_pad_attr_39_gated_we),
18585 .wd (mio_pad_attr_39_keeper_en_39_wd),
18586 .d (hw2reg.mio_pad_attr[39].keeper_en.d),
18587 .qre (),
18588 .qe (mio_pad_attr_39_flds_we[4]),
18589 .q (reg2hw.mio_pad_attr[39].keeper_en.q),
18590 .ds (),
18591 .qs (mio_pad_attr_39_keeper_en_39_qs)
18592 );
18593 1/1 assign reg2hw.mio_pad_attr[39].keeper_en.qe = mio_pad_attr_39_qe;
Tests: T96 T97 T98
18594
18595 // F[schmitt_en_39]: 5:5
18596 prim_subreg_ext #(
18597 .DW (1)
18598 ) u_mio_pad_attr_39_schmitt_en_39 (
18599 .re (mio_pad_attr_39_re),
18600 .we (mio_pad_attr_39_gated_we),
18601 .wd (mio_pad_attr_39_schmitt_en_39_wd),
18602 .d (hw2reg.mio_pad_attr[39].schmitt_en.d),
18603 .qre (),
18604 .qe (mio_pad_attr_39_flds_we[5]),
18605 .q (reg2hw.mio_pad_attr[39].schmitt_en.q),
18606 .ds (),
18607 .qs (mio_pad_attr_39_schmitt_en_39_qs)
18608 );
18609 1/1 assign reg2hw.mio_pad_attr[39].schmitt_en.qe = mio_pad_attr_39_qe;
Tests: T96 T97 T98
18610
18611 // F[od_en_39]: 6:6
18612 prim_subreg_ext #(
18613 .DW (1)
18614 ) u_mio_pad_attr_39_od_en_39 (
18615 .re (mio_pad_attr_39_re),
18616 .we (mio_pad_attr_39_gated_we),
18617 .wd (mio_pad_attr_39_od_en_39_wd),
18618 .d (hw2reg.mio_pad_attr[39].od_en.d),
18619 .qre (),
18620 .qe (mio_pad_attr_39_flds_we[6]),
18621 .q (reg2hw.mio_pad_attr[39].od_en.q),
18622 .ds (),
18623 .qs (mio_pad_attr_39_od_en_39_qs)
18624 );
18625 1/1 assign reg2hw.mio_pad_attr[39].od_en.qe = mio_pad_attr_39_qe;
Tests: T96 T97 T98
18626
18627 // F[input_disable_39]: 7:7
18628 prim_subreg_ext #(
18629 .DW (1)
18630 ) u_mio_pad_attr_39_input_disable_39 (
18631 .re (mio_pad_attr_39_re),
18632 .we (mio_pad_attr_39_gated_we),
18633 .wd (mio_pad_attr_39_input_disable_39_wd),
18634 .d (hw2reg.mio_pad_attr[39].input_disable.d),
18635 .qre (),
18636 .qe (mio_pad_attr_39_flds_we[7]),
18637 .q (reg2hw.mio_pad_attr[39].input_disable.q),
18638 .ds (),
18639 .qs (mio_pad_attr_39_input_disable_39_qs)
18640 );
18641 1/1 assign reg2hw.mio_pad_attr[39].input_disable.qe = mio_pad_attr_39_qe;
Tests: T96 T97 T98
18642
18643 // F[slew_rate_39]: 17:16
18644 prim_subreg_ext #(
18645 .DW (2)
18646 ) u_mio_pad_attr_39_slew_rate_39 (
18647 .re (mio_pad_attr_39_re),
18648 .we (mio_pad_attr_39_gated_we),
18649 .wd (mio_pad_attr_39_slew_rate_39_wd),
18650 .d (hw2reg.mio_pad_attr[39].slew_rate.d),
18651 .qre (),
18652 .qe (mio_pad_attr_39_flds_we[8]),
18653 .q (reg2hw.mio_pad_attr[39].slew_rate.q),
18654 .ds (),
18655 .qs (mio_pad_attr_39_slew_rate_39_qs)
18656 );
18657 1/1 assign reg2hw.mio_pad_attr[39].slew_rate.qe = mio_pad_attr_39_qe;
Tests: T96 T97 T98
18658
18659 // F[drive_strength_39]: 23:20
18660 prim_subreg_ext #(
18661 .DW (4)
18662 ) u_mio_pad_attr_39_drive_strength_39 (
18663 .re (mio_pad_attr_39_re),
18664 .we (mio_pad_attr_39_gated_we),
18665 .wd (mio_pad_attr_39_drive_strength_39_wd),
18666 .d (hw2reg.mio_pad_attr[39].drive_strength.d),
18667 .qre (),
18668 .qe (mio_pad_attr_39_flds_we[9]),
18669 .q (reg2hw.mio_pad_attr[39].drive_strength.q),
18670 .ds (),
18671 .qs (mio_pad_attr_39_drive_strength_39_qs)
18672 );
18673 1/1 assign reg2hw.mio_pad_attr[39].drive_strength.qe = mio_pad_attr_39_qe;
Tests: T96 T97 T98
18674
18675
18676 // Subregister 40 of Multireg mio_pad_attr
18677 // R[mio_pad_attr_40]: V(True)
18678 logic mio_pad_attr_40_qe;
18679 logic [9:0] mio_pad_attr_40_flds_we;
18680 1/1 assign mio_pad_attr_40_qe = &mio_pad_attr_40_flds_we;
Tests: T96 T97 T98
18681 // Create REGWEN-gated WE signal
18682 logic mio_pad_attr_40_gated_we;
18683 1/1 assign mio_pad_attr_40_gated_we = mio_pad_attr_40_we & mio_pad_attr_regwen_40_qs;
Tests: T71 T96 T97
18684 // F[invert_40]: 0:0
18685 prim_subreg_ext #(
18686 .DW (1)
18687 ) u_mio_pad_attr_40_invert_40 (
18688 .re (mio_pad_attr_40_re),
18689 .we (mio_pad_attr_40_gated_we),
18690 .wd (mio_pad_attr_40_invert_40_wd),
18691 .d (hw2reg.mio_pad_attr[40].invert.d),
18692 .qre (),
18693 .qe (mio_pad_attr_40_flds_we[0]),
18694 .q (reg2hw.mio_pad_attr[40].invert.q),
18695 .ds (),
18696 .qs (mio_pad_attr_40_invert_40_qs)
18697 );
18698 1/1 assign reg2hw.mio_pad_attr[40].invert.qe = mio_pad_attr_40_qe;
Tests: T96 T97 T98
18699
18700 // F[virtual_od_en_40]: 1:1
18701 prim_subreg_ext #(
18702 .DW (1)
18703 ) u_mio_pad_attr_40_virtual_od_en_40 (
18704 .re (mio_pad_attr_40_re),
18705 .we (mio_pad_attr_40_gated_we),
18706 .wd (mio_pad_attr_40_virtual_od_en_40_wd),
18707 .d (hw2reg.mio_pad_attr[40].virtual_od_en.d),
18708 .qre (),
18709 .qe (mio_pad_attr_40_flds_we[1]),
18710 .q (reg2hw.mio_pad_attr[40].virtual_od_en.q),
18711 .ds (),
18712 .qs (mio_pad_attr_40_virtual_od_en_40_qs)
18713 );
18714 1/1 assign reg2hw.mio_pad_attr[40].virtual_od_en.qe = mio_pad_attr_40_qe;
Tests: T96 T97 T98
18715
18716 // F[pull_en_40]: 2:2
18717 prim_subreg_ext #(
18718 .DW (1)
18719 ) u_mio_pad_attr_40_pull_en_40 (
18720 .re (mio_pad_attr_40_re),
18721 .we (mio_pad_attr_40_gated_we),
18722 .wd (mio_pad_attr_40_pull_en_40_wd),
18723 .d (hw2reg.mio_pad_attr[40].pull_en.d),
18724 .qre (),
18725 .qe (mio_pad_attr_40_flds_we[2]),
18726 .q (reg2hw.mio_pad_attr[40].pull_en.q),
18727 .ds (),
18728 .qs (mio_pad_attr_40_pull_en_40_qs)
18729 );
18730 1/1 assign reg2hw.mio_pad_attr[40].pull_en.qe = mio_pad_attr_40_qe;
Tests: T96 T97 T98
18731
18732 // F[pull_select_40]: 3:3
18733 prim_subreg_ext #(
18734 .DW (1)
18735 ) u_mio_pad_attr_40_pull_select_40 (
18736 .re (mio_pad_attr_40_re),
18737 .we (mio_pad_attr_40_gated_we),
18738 .wd (mio_pad_attr_40_pull_select_40_wd),
18739 .d (hw2reg.mio_pad_attr[40].pull_select.d),
18740 .qre (),
18741 .qe (mio_pad_attr_40_flds_we[3]),
18742 .q (reg2hw.mio_pad_attr[40].pull_select.q),
18743 .ds (),
18744 .qs (mio_pad_attr_40_pull_select_40_qs)
18745 );
18746 1/1 assign reg2hw.mio_pad_attr[40].pull_select.qe = mio_pad_attr_40_qe;
Tests: T96 T97 T98
18747
18748 // F[keeper_en_40]: 4:4
18749 prim_subreg_ext #(
18750 .DW (1)
18751 ) u_mio_pad_attr_40_keeper_en_40 (
18752 .re (mio_pad_attr_40_re),
18753 .we (mio_pad_attr_40_gated_we),
18754 .wd (mio_pad_attr_40_keeper_en_40_wd),
18755 .d (hw2reg.mio_pad_attr[40].keeper_en.d),
18756 .qre (),
18757 .qe (mio_pad_attr_40_flds_we[4]),
18758 .q (reg2hw.mio_pad_attr[40].keeper_en.q),
18759 .ds (),
18760 .qs (mio_pad_attr_40_keeper_en_40_qs)
18761 );
18762 1/1 assign reg2hw.mio_pad_attr[40].keeper_en.qe = mio_pad_attr_40_qe;
Tests: T96 T97 T98
18763
18764 // F[schmitt_en_40]: 5:5
18765 prim_subreg_ext #(
18766 .DW (1)
18767 ) u_mio_pad_attr_40_schmitt_en_40 (
18768 .re (mio_pad_attr_40_re),
18769 .we (mio_pad_attr_40_gated_we),
18770 .wd (mio_pad_attr_40_schmitt_en_40_wd),
18771 .d (hw2reg.mio_pad_attr[40].schmitt_en.d),
18772 .qre (),
18773 .qe (mio_pad_attr_40_flds_we[5]),
18774 .q (reg2hw.mio_pad_attr[40].schmitt_en.q),
18775 .ds (),
18776 .qs (mio_pad_attr_40_schmitt_en_40_qs)
18777 );
18778 1/1 assign reg2hw.mio_pad_attr[40].schmitt_en.qe = mio_pad_attr_40_qe;
Tests: T96 T97 T98
18779
18780 // F[od_en_40]: 6:6
18781 prim_subreg_ext #(
18782 .DW (1)
18783 ) u_mio_pad_attr_40_od_en_40 (
18784 .re (mio_pad_attr_40_re),
18785 .we (mio_pad_attr_40_gated_we),
18786 .wd (mio_pad_attr_40_od_en_40_wd),
18787 .d (hw2reg.mio_pad_attr[40].od_en.d),
18788 .qre (),
18789 .qe (mio_pad_attr_40_flds_we[6]),
18790 .q (reg2hw.mio_pad_attr[40].od_en.q),
18791 .ds (),
18792 .qs (mio_pad_attr_40_od_en_40_qs)
18793 );
18794 1/1 assign reg2hw.mio_pad_attr[40].od_en.qe = mio_pad_attr_40_qe;
Tests: T96 T97 T98
18795
18796 // F[input_disable_40]: 7:7
18797 prim_subreg_ext #(
18798 .DW (1)
18799 ) u_mio_pad_attr_40_input_disable_40 (
18800 .re (mio_pad_attr_40_re),
18801 .we (mio_pad_attr_40_gated_we),
18802 .wd (mio_pad_attr_40_input_disable_40_wd),
18803 .d (hw2reg.mio_pad_attr[40].input_disable.d),
18804 .qre (),
18805 .qe (mio_pad_attr_40_flds_we[7]),
18806 .q (reg2hw.mio_pad_attr[40].input_disable.q),
18807 .ds (),
18808 .qs (mio_pad_attr_40_input_disable_40_qs)
18809 );
18810 1/1 assign reg2hw.mio_pad_attr[40].input_disable.qe = mio_pad_attr_40_qe;
Tests: T96 T97 T98
18811
18812 // F[slew_rate_40]: 17:16
18813 prim_subreg_ext #(
18814 .DW (2)
18815 ) u_mio_pad_attr_40_slew_rate_40 (
18816 .re (mio_pad_attr_40_re),
18817 .we (mio_pad_attr_40_gated_we),
18818 .wd (mio_pad_attr_40_slew_rate_40_wd),
18819 .d (hw2reg.mio_pad_attr[40].slew_rate.d),
18820 .qre (),
18821 .qe (mio_pad_attr_40_flds_we[8]),
18822 .q (reg2hw.mio_pad_attr[40].slew_rate.q),
18823 .ds (),
18824 .qs (mio_pad_attr_40_slew_rate_40_qs)
18825 );
18826 1/1 assign reg2hw.mio_pad_attr[40].slew_rate.qe = mio_pad_attr_40_qe;
Tests: T96 T97 T98
18827
18828 // F[drive_strength_40]: 23:20
18829 prim_subreg_ext #(
18830 .DW (4)
18831 ) u_mio_pad_attr_40_drive_strength_40 (
18832 .re (mio_pad_attr_40_re),
18833 .we (mio_pad_attr_40_gated_we),
18834 .wd (mio_pad_attr_40_drive_strength_40_wd),
18835 .d (hw2reg.mio_pad_attr[40].drive_strength.d),
18836 .qre (),
18837 .qe (mio_pad_attr_40_flds_we[9]),
18838 .q (reg2hw.mio_pad_attr[40].drive_strength.q),
18839 .ds (),
18840 .qs (mio_pad_attr_40_drive_strength_40_qs)
18841 );
18842 1/1 assign reg2hw.mio_pad_attr[40].drive_strength.qe = mio_pad_attr_40_qe;
Tests: T96 T97 T98
18843
18844
18845 // Subregister 41 of Multireg mio_pad_attr
18846 // R[mio_pad_attr_41]: V(True)
18847 logic mio_pad_attr_41_qe;
18848 logic [9:0] mio_pad_attr_41_flds_we;
18849 1/1 assign mio_pad_attr_41_qe = &mio_pad_attr_41_flds_we;
Tests: T96 T97 T98
18850 // Create REGWEN-gated WE signal
18851 logic mio_pad_attr_41_gated_we;
18852 1/1 assign mio_pad_attr_41_gated_we = mio_pad_attr_41_we & mio_pad_attr_regwen_41_qs;
Tests: T71 T96 T97
18853 // F[invert_41]: 0:0
18854 prim_subreg_ext #(
18855 .DW (1)
18856 ) u_mio_pad_attr_41_invert_41 (
18857 .re (mio_pad_attr_41_re),
18858 .we (mio_pad_attr_41_gated_we),
18859 .wd (mio_pad_attr_41_invert_41_wd),
18860 .d (hw2reg.mio_pad_attr[41].invert.d),
18861 .qre (),
18862 .qe (mio_pad_attr_41_flds_we[0]),
18863 .q (reg2hw.mio_pad_attr[41].invert.q),
18864 .ds (),
18865 .qs (mio_pad_attr_41_invert_41_qs)
18866 );
18867 1/1 assign reg2hw.mio_pad_attr[41].invert.qe = mio_pad_attr_41_qe;
Tests: T96 T97 T98
18868
18869 // F[virtual_od_en_41]: 1:1
18870 prim_subreg_ext #(
18871 .DW (1)
18872 ) u_mio_pad_attr_41_virtual_od_en_41 (
18873 .re (mio_pad_attr_41_re),
18874 .we (mio_pad_attr_41_gated_we),
18875 .wd (mio_pad_attr_41_virtual_od_en_41_wd),
18876 .d (hw2reg.mio_pad_attr[41].virtual_od_en.d),
18877 .qre (),
18878 .qe (mio_pad_attr_41_flds_we[1]),
18879 .q (reg2hw.mio_pad_attr[41].virtual_od_en.q),
18880 .ds (),
18881 .qs (mio_pad_attr_41_virtual_od_en_41_qs)
18882 );
18883 1/1 assign reg2hw.mio_pad_attr[41].virtual_od_en.qe = mio_pad_attr_41_qe;
Tests: T96 T97 T98
18884
18885 // F[pull_en_41]: 2:2
18886 prim_subreg_ext #(
18887 .DW (1)
18888 ) u_mio_pad_attr_41_pull_en_41 (
18889 .re (mio_pad_attr_41_re),
18890 .we (mio_pad_attr_41_gated_we),
18891 .wd (mio_pad_attr_41_pull_en_41_wd),
18892 .d (hw2reg.mio_pad_attr[41].pull_en.d),
18893 .qre (),
18894 .qe (mio_pad_attr_41_flds_we[2]),
18895 .q (reg2hw.mio_pad_attr[41].pull_en.q),
18896 .ds (),
18897 .qs (mio_pad_attr_41_pull_en_41_qs)
18898 );
18899 1/1 assign reg2hw.mio_pad_attr[41].pull_en.qe = mio_pad_attr_41_qe;
Tests: T96 T97 T98
18900
18901 // F[pull_select_41]: 3:3
18902 prim_subreg_ext #(
18903 .DW (1)
18904 ) u_mio_pad_attr_41_pull_select_41 (
18905 .re (mio_pad_attr_41_re),
18906 .we (mio_pad_attr_41_gated_we),
18907 .wd (mio_pad_attr_41_pull_select_41_wd),
18908 .d (hw2reg.mio_pad_attr[41].pull_select.d),
18909 .qre (),
18910 .qe (mio_pad_attr_41_flds_we[3]),
18911 .q (reg2hw.mio_pad_attr[41].pull_select.q),
18912 .ds (),
18913 .qs (mio_pad_attr_41_pull_select_41_qs)
18914 );
18915 1/1 assign reg2hw.mio_pad_attr[41].pull_select.qe = mio_pad_attr_41_qe;
Tests: T96 T97 T98
18916
18917 // F[keeper_en_41]: 4:4
18918 prim_subreg_ext #(
18919 .DW (1)
18920 ) u_mio_pad_attr_41_keeper_en_41 (
18921 .re (mio_pad_attr_41_re),
18922 .we (mio_pad_attr_41_gated_we),
18923 .wd (mio_pad_attr_41_keeper_en_41_wd),
18924 .d (hw2reg.mio_pad_attr[41].keeper_en.d),
18925 .qre (),
18926 .qe (mio_pad_attr_41_flds_we[4]),
18927 .q (reg2hw.mio_pad_attr[41].keeper_en.q),
18928 .ds (),
18929 .qs (mio_pad_attr_41_keeper_en_41_qs)
18930 );
18931 1/1 assign reg2hw.mio_pad_attr[41].keeper_en.qe = mio_pad_attr_41_qe;
Tests: T96 T97 T98
18932
18933 // F[schmitt_en_41]: 5:5
18934 prim_subreg_ext #(
18935 .DW (1)
18936 ) u_mio_pad_attr_41_schmitt_en_41 (
18937 .re (mio_pad_attr_41_re),
18938 .we (mio_pad_attr_41_gated_we),
18939 .wd (mio_pad_attr_41_schmitt_en_41_wd),
18940 .d (hw2reg.mio_pad_attr[41].schmitt_en.d),
18941 .qre (),
18942 .qe (mio_pad_attr_41_flds_we[5]),
18943 .q (reg2hw.mio_pad_attr[41].schmitt_en.q),
18944 .ds (),
18945 .qs (mio_pad_attr_41_schmitt_en_41_qs)
18946 );
18947 1/1 assign reg2hw.mio_pad_attr[41].schmitt_en.qe = mio_pad_attr_41_qe;
Tests: T96 T97 T98
18948
18949 // F[od_en_41]: 6:6
18950 prim_subreg_ext #(
18951 .DW (1)
18952 ) u_mio_pad_attr_41_od_en_41 (
18953 .re (mio_pad_attr_41_re),
18954 .we (mio_pad_attr_41_gated_we),
18955 .wd (mio_pad_attr_41_od_en_41_wd),
18956 .d (hw2reg.mio_pad_attr[41].od_en.d),
18957 .qre (),
18958 .qe (mio_pad_attr_41_flds_we[6]),
18959 .q (reg2hw.mio_pad_attr[41].od_en.q),
18960 .ds (),
18961 .qs (mio_pad_attr_41_od_en_41_qs)
18962 );
18963 1/1 assign reg2hw.mio_pad_attr[41].od_en.qe = mio_pad_attr_41_qe;
Tests: T96 T97 T98
18964
18965 // F[input_disable_41]: 7:7
18966 prim_subreg_ext #(
18967 .DW (1)
18968 ) u_mio_pad_attr_41_input_disable_41 (
18969 .re (mio_pad_attr_41_re),
18970 .we (mio_pad_attr_41_gated_we),
18971 .wd (mio_pad_attr_41_input_disable_41_wd),
18972 .d (hw2reg.mio_pad_attr[41].input_disable.d),
18973 .qre (),
18974 .qe (mio_pad_attr_41_flds_we[7]),
18975 .q (reg2hw.mio_pad_attr[41].input_disable.q),
18976 .ds (),
18977 .qs (mio_pad_attr_41_input_disable_41_qs)
18978 );
18979 1/1 assign reg2hw.mio_pad_attr[41].input_disable.qe = mio_pad_attr_41_qe;
Tests: T96 T97 T98
18980
18981 // F[slew_rate_41]: 17:16
18982 prim_subreg_ext #(
18983 .DW (2)
18984 ) u_mio_pad_attr_41_slew_rate_41 (
18985 .re (mio_pad_attr_41_re),
18986 .we (mio_pad_attr_41_gated_we),
18987 .wd (mio_pad_attr_41_slew_rate_41_wd),
18988 .d (hw2reg.mio_pad_attr[41].slew_rate.d),
18989 .qre (),
18990 .qe (mio_pad_attr_41_flds_we[8]),
18991 .q (reg2hw.mio_pad_attr[41].slew_rate.q),
18992 .ds (),
18993 .qs (mio_pad_attr_41_slew_rate_41_qs)
18994 );
18995 1/1 assign reg2hw.mio_pad_attr[41].slew_rate.qe = mio_pad_attr_41_qe;
Tests: T96 T97 T98
18996
18997 // F[drive_strength_41]: 23:20
18998 prim_subreg_ext #(
18999 .DW (4)
19000 ) u_mio_pad_attr_41_drive_strength_41 (
19001 .re (mio_pad_attr_41_re),
19002 .we (mio_pad_attr_41_gated_we),
19003 .wd (mio_pad_attr_41_drive_strength_41_wd),
19004 .d (hw2reg.mio_pad_attr[41].drive_strength.d),
19005 .qre (),
19006 .qe (mio_pad_attr_41_flds_we[9]),
19007 .q (reg2hw.mio_pad_attr[41].drive_strength.q),
19008 .ds (),
19009 .qs (mio_pad_attr_41_drive_strength_41_qs)
19010 );
19011 1/1 assign reg2hw.mio_pad_attr[41].drive_strength.qe = mio_pad_attr_41_qe;
Tests: T96 T97 T98
19012
19013
19014 // Subregister 42 of Multireg mio_pad_attr
19015 // R[mio_pad_attr_42]: V(True)
19016 logic mio_pad_attr_42_qe;
19017 logic [9:0] mio_pad_attr_42_flds_we;
19018 1/1 assign mio_pad_attr_42_qe = &mio_pad_attr_42_flds_we;
Tests: T96 T97 T98
19019 // Create REGWEN-gated WE signal
19020 logic mio_pad_attr_42_gated_we;
19021 1/1 assign mio_pad_attr_42_gated_we = mio_pad_attr_42_we & mio_pad_attr_regwen_42_qs;
Tests: T71 T96 T97
19022 // F[invert_42]: 0:0
19023 prim_subreg_ext #(
19024 .DW (1)
19025 ) u_mio_pad_attr_42_invert_42 (
19026 .re (mio_pad_attr_42_re),
19027 .we (mio_pad_attr_42_gated_we),
19028 .wd (mio_pad_attr_42_invert_42_wd),
19029 .d (hw2reg.mio_pad_attr[42].invert.d),
19030 .qre (),
19031 .qe (mio_pad_attr_42_flds_we[0]),
19032 .q (reg2hw.mio_pad_attr[42].invert.q),
19033 .ds (),
19034 .qs (mio_pad_attr_42_invert_42_qs)
19035 );
19036 1/1 assign reg2hw.mio_pad_attr[42].invert.qe = mio_pad_attr_42_qe;
Tests: T96 T97 T98
19037
19038 // F[virtual_od_en_42]: 1:1
19039 prim_subreg_ext #(
19040 .DW (1)
19041 ) u_mio_pad_attr_42_virtual_od_en_42 (
19042 .re (mio_pad_attr_42_re),
19043 .we (mio_pad_attr_42_gated_we),
19044 .wd (mio_pad_attr_42_virtual_od_en_42_wd),
19045 .d (hw2reg.mio_pad_attr[42].virtual_od_en.d),
19046 .qre (),
19047 .qe (mio_pad_attr_42_flds_we[1]),
19048 .q (reg2hw.mio_pad_attr[42].virtual_od_en.q),
19049 .ds (),
19050 .qs (mio_pad_attr_42_virtual_od_en_42_qs)
19051 );
19052 1/1 assign reg2hw.mio_pad_attr[42].virtual_od_en.qe = mio_pad_attr_42_qe;
Tests: T96 T97 T98
19053
19054 // F[pull_en_42]: 2:2
19055 prim_subreg_ext #(
19056 .DW (1)
19057 ) u_mio_pad_attr_42_pull_en_42 (
19058 .re (mio_pad_attr_42_re),
19059 .we (mio_pad_attr_42_gated_we),
19060 .wd (mio_pad_attr_42_pull_en_42_wd),
19061 .d (hw2reg.mio_pad_attr[42].pull_en.d),
19062 .qre (),
19063 .qe (mio_pad_attr_42_flds_we[2]),
19064 .q (reg2hw.mio_pad_attr[42].pull_en.q),
19065 .ds (),
19066 .qs (mio_pad_attr_42_pull_en_42_qs)
19067 );
19068 1/1 assign reg2hw.mio_pad_attr[42].pull_en.qe = mio_pad_attr_42_qe;
Tests: T96 T97 T98
19069
19070 // F[pull_select_42]: 3:3
19071 prim_subreg_ext #(
19072 .DW (1)
19073 ) u_mio_pad_attr_42_pull_select_42 (
19074 .re (mio_pad_attr_42_re),
19075 .we (mio_pad_attr_42_gated_we),
19076 .wd (mio_pad_attr_42_pull_select_42_wd),
19077 .d (hw2reg.mio_pad_attr[42].pull_select.d),
19078 .qre (),
19079 .qe (mio_pad_attr_42_flds_we[3]),
19080 .q (reg2hw.mio_pad_attr[42].pull_select.q),
19081 .ds (),
19082 .qs (mio_pad_attr_42_pull_select_42_qs)
19083 );
19084 1/1 assign reg2hw.mio_pad_attr[42].pull_select.qe = mio_pad_attr_42_qe;
Tests: T96 T97 T98
19085
19086 // F[keeper_en_42]: 4:4
19087 prim_subreg_ext #(
19088 .DW (1)
19089 ) u_mio_pad_attr_42_keeper_en_42 (
19090 .re (mio_pad_attr_42_re),
19091 .we (mio_pad_attr_42_gated_we),
19092 .wd (mio_pad_attr_42_keeper_en_42_wd),
19093 .d (hw2reg.mio_pad_attr[42].keeper_en.d),
19094 .qre (),
19095 .qe (mio_pad_attr_42_flds_we[4]),
19096 .q (reg2hw.mio_pad_attr[42].keeper_en.q),
19097 .ds (),
19098 .qs (mio_pad_attr_42_keeper_en_42_qs)
19099 );
19100 1/1 assign reg2hw.mio_pad_attr[42].keeper_en.qe = mio_pad_attr_42_qe;
Tests: T96 T97 T98
19101
19102 // F[schmitt_en_42]: 5:5
19103 prim_subreg_ext #(
19104 .DW (1)
19105 ) u_mio_pad_attr_42_schmitt_en_42 (
19106 .re (mio_pad_attr_42_re),
19107 .we (mio_pad_attr_42_gated_we),
19108 .wd (mio_pad_attr_42_schmitt_en_42_wd),
19109 .d (hw2reg.mio_pad_attr[42].schmitt_en.d),
19110 .qre (),
19111 .qe (mio_pad_attr_42_flds_we[5]),
19112 .q (reg2hw.mio_pad_attr[42].schmitt_en.q),
19113 .ds (),
19114 .qs (mio_pad_attr_42_schmitt_en_42_qs)
19115 );
19116 1/1 assign reg2hw.mio_pad_attr[42].schmitt_en.qe = mio_pad_attr_42_qe;
Tests: T96 T97 T98
19117
19118 // F[od_en_42]: 6:6
19119 prim_subreg_ext #(
19120 .DW (1)
19121 ) u_mio_pad_attr_42_od_en_42 (
19122 .re (mio_pad_attr_42_re),
19123 .we (mio_pad_attr_42_gated_we),
19124 .wd (mio_pad_attr_42_od_en_42_wd),
19125 .d (hw2reg.mio_pad_attr[42].od_en.d),
19126 .qre (),
19127 .qe (mio_pad_attr_42_flds_we[6]),
19128 .q (reg2hw.mio_pad_attr[42].od_en.q),
19129 .ds (),
19130 .qs (mio_pad_attr_42_od_en_42_qs)
19131 );
19132 1/1 assign reg2hw.mio_pad_attr[42].od_en.qe = mio_pad_attr_42_qe;
Tests: T96 T97 T98
19133
19134 // F[input_disable_42]: 7:7
19135 prim_subreg_ext #(
19136 .DW (1)
19137 ) u_mio_pad_attr_42_input_disable_42 (
19138 .re (mio_pad_attr_42_re),
19139 .we (mio_pad_attr_42_gated_we),
19140 .wd (mio_pad_attr_42_input_disable_42_wd),
19141 .d (hw2reg.mio_pad_attr[42].input_disable.d),
19142 .qre (),
19143 .qe (mio_pad_attr_42_flds_we[7]),
19144 .q (reg2hw.mio_pad_attr[42].input_disable.q),
19145 .ds (),
19146 .qs (mio_pad_attr_42_input_disable_42_qs)
19147 );
19148 1/1 assign reg2hw.mio_pad_attr[42].input_disable.qe = mio_pad_attr_42_qe;
Tests: T96 T97 T98
19149
19150 // F[slew_rate_42]: 17:16
19151 prim_subreg_ext #(
19152 .DW (2)
19153 ) u_mio_pad_attr_42_slew_rate_42 (
19154 .re (mio_pad_attr_42_re),
19155 .we (mio_pad_attr_42_gated_we),
19156 .wd (mio_pad_attr_42_slew_rate_42_wd),
19157 .d (hw2reg.mio_pad_attr[42].slew_rate.d),
19158 .qre (),
19159 .qe (mio_pad_attr_42_flds_we[8]),
19160 .q (reg2hw.mio_pad_attr[42].slew_rate.q),
19161 .ds (),
19162 .qs (mio_pad_attr_42_slew_rate_42_qs)
19163 );
19164 1/1 assign reg2hw.mio_pad_attr[42].slew_rate.qe = mio_pad_attr_42_qe;
Tests: T96 T97 T98
19165
19166 // F[drive_strength_42]: 23:20
19167 prim_subreg_ext #(
19168 .DW (4)
19169 ) u_mio_pad_attr_42_drive_strength_42 (
19170 .re (mio_pad_attr_42_re),
19171 .we (mio_pad_attr_42_gated_we),
19172 .wd (mio_pad_attr_42_drive_strength_42_wd),
19173 .d (hw2reg.mio_pad_attr[42].drive_strength.d),
19174 .qre (),
19175 .qe (mio_pad_attr_42_flds_we[9]),
19176 .q (reg2hw.mio_pad_attr[42].drive_strength.q),
19177 .ds (),
19178 .qs (mio_pad_attr_42_drive_strength_42_qs)
19179 );
19180 1/1 assign reg2hw.mio_pad_attr[42].drive_strength.qe = mio_pad_attr_42_qe;
Tests: T96 T97 T98
19181
19182
19183 // Subregister 43 of Multireg mio_pad_attr
19184 // R[mio_pad_attr_43]: V(True)
19185 logic mio_pad_attr_43_qe;
19186 logic [9:0] mio_pad_attr_43_flds_we;
19187 1/1 assign mio_pad_attr_43_qe = &mio_pad_attr_43_flds_we;
Tests: T96 T97 T98
19188 // Create REGWEN-gated WE signal
19189 logic mio_pad_attr_43_gated_we;
19190 1/1 assign mio_pad_attr_43_gated_we = mio_pad_attr_43_we & mio_pad_attr_regwen_43_qs;
Tests: T71 T96 T97
19191 // F[invert_43]: 0:0
19192 prim_subreg_ext #(
19193 .DW (1)
19194 ) u_mio_pad_attr_43_invert_43 (
19195 .re (mio_pad_attr_43_re),
19196 .we (mio_pad_attr_43_gated_we),
19197 .wd (mio_pad_attr_43_invert_43_wd),
19198 .d (hw2reg.mio_pad_attr[43].invert.d),
19199 .qre (),
19200 .qe (mio_pad_attr_43_flds_we[0]),
19201 .q (reg2hw.mio_pad_attr[43].invert.q),
19202 .ds (),
19203 .qs (mio_pad_attr_43_invert_43_qs)
19204 );
19205 1/1 assign reg2hw.mio_pad_attr[43].invert.qe = mio_pad_attr_43_qe;
Tests: T96 T97 T98
19206
19207 // F[virtual_od_en_43]: 1:1
19208 prim_subreg_ext #(
19209 .DW (1)
19210 ) u_mio_pad_attr_43_virtual_od_en_43 (
19211 .re (mio_pad_attr_43_re),
19212 .we (mio_pad_attr_43_gated_we),
19213 .wd (mio_pad_attr_43_virtual_od_en_43_wd),
19214 .d (hw2reg.mio_pad_attr[43].virtual_od_en.d),
19215 .qre (),
19216 .qe (mio_pad_attr_43_flds_we[1]),
19217 .q (reg2hw.mio_pad_attr[43].virtual_od_en.q),
19218 .ds (),
19219 .qs (mio_pad_attr_43_virtual_od_en_43_qs)
19220 );
19221 1/1 assign reg2hw.mio_pad_attr[43].virtual_od_en.qe = mio_pad_attr_43_qe;
Tests: T96 T97 T98
19222
19223 // F[pull_en_43]: 2:2
19224 prim_subreg_ext #(
19225 .DW (1)
19226 ) u_mio_pad_attr_43_pull_en_43 (
19227 .re (mio_pad_attr_43_re),
19228 .we (mio_pad_attr_43_gated_we),
19229 .wd (mio_pad_attr_43_pull_en_43_wd),
19230 .d (hw2reg.mio_pad_attr[43].pull_en.d),
19231 .qre (),
19232 .qe (mio_pad_attr_43_flds_we[2]),
19233 .q (reg2hw.mio_pad_attr[43].pull_en.q),
19234 .ds (),
19235 .qs (mio_pad_attr_43_pull_en_43_qs)
19236 );
19237 1/1 assign reg2hw.mio_pad_attr[43].pull_en.qe = mio_pad_attr_43_qe;
Tests: T96 T97 T98
19238
19239 // F[pull_select_43]: 3:3
19240 prim_subreg_ext #(
19241 .DW (1)
19242 ) u_mio_pad_attr_43_pull_select_43 (
19243 .re (mio_pad_attr_43_re),
19244 .we (mio_pad_attr_43_gated_we),
19245 .wd (mio_pad_attr_43_pull_select_43_wd),
19246 .d (hw2reg.mio_pad_attr[43].pull_select.d),
19247 .qre (),
19248 .qe (mio_pad_attr_43_flds_we[3]),
19249 .q (reg2hw.mio_pad_attr[43].pull_select.q),
19250 .ds (),
19251 .qs (mio_pad_attr_43_pull_select_43_qs)
19252 );
19253 1/1 assign reg2hw.mio_pad_attr[43].pull_select.qe = mio_pad_attr_43_qe;
Tests: T96 T97 T98
19254
19255 // F[keeper_en_43]: 4:4
19256 prim_subreg_ext #(
19257 .DW (1)
19258 ) u_mio_pad_attr_43_keeper_en_43 (
19259 .re (mio_pad_attr_43_re),
19260 .we (mio_pad_attr_43_gated_we),
19261 .wd (mio_pad_attr_43_keeper_en_43_wd),
19262 .d (hw2reg.mio_pad_attr[43].keeper_en.d),
19263 .qre (),
19264 .qe (mio_pad_attr_43_flds_we[4]),
19265 .q (reg2hw.mio_pad_attr[43].keeper_en.q),
19266 .ds (),
19267 .qs (mio_pad_attr_43_keeper_en_43_qs)
19268 );
19269 1/1 assign reg2hw.mio_pad_attr[43].keeper_en.qe = mio_pad_attr_43_qe;
Tests: T96 T97 T98
19270
19271 // F[schmitt_en_43]: 5:5
19272 prim_subreg_ext #(
19273 .DW (1)
19274 ) u_mio_pad_attr_43_schmitt_en_43 (
19275 .re (mio_pad_attr_43_re),
19276 .we (mio_pad_attr_43_gated_we),
19277 .wd (mio_pad_attr_43_schmitt_en_43_wd),
19278 .d (hw2reg.mio_pad_attr[43].schmitt_en.d),
19279 .qre (),
19280 .qe (mio_pad_attr_43_flds_we[5]),
19281 .q (reg2hw.mio_pad_attr[43].schmitt_en.q),
19282 .ds (),
19283 .qs (mio_pad_attr_43_schmitt_en_43_qs)
19284 );
19285 1/1 assign reg2hw.mio_pad_attr[43].schmitt_en.qe = mio_pad_attr_43_qe;
Tests: T96 T97 T98
19286
19287 // F[od_en_43]: 6:6
19288 prim_subreg_ext #(
19289 .DW (1)
19290 ) u_mio_pad_attr_43_od_en_43 (
19291 .re (mio_pad_attr_43_re),
19292 .we (mio_pad_attr_43_gated_we),
19293 .wd (mio_pad_attr_43_od_en_43_wd),
19294 .d (hw2reg.mio_pad_attr[43].od_en.d),
19295 .qre (),
19296 .qe (mio_pad_attr_43_flds_we[6]),
19297 .q (reg2hw.mio_pad_attr[43].od_en.q),
19298 .ds (),
19299 .qs (mio_pad_attr_43_od_en_43_qs)
19300 );
19301 1/1 assign reg2hw.mio_pad_attr[43].od_en.qe = mio_pad_attr_43_qe;
Tests: T96 T97 T98
19302
19303 // F[input_disable_43]: 7:7
19304 prim_subreg_ext #(
19305 .DW (1)
19306 ) u_mio_pad_attr_43_input_disable_43 (
19307 .re (mio_pad_attr_43_re),
19308 .we (mio_pad_attr_43_gated_we),
19309 .wd (mio_pad_attr_43_input_disable_43_wd),
19310 .d (hw2reg.mio_pad_attr[43].input_disable.d),
19311 .qre (),
19312 .qe (mio_pad_attr_43_flds_we[7]),
19313 .q (reg2hw.mio_pad_attr[43].input_disable.q),
19314 .ds (),
19315 .qs (mio_pad_attr_43_input_disable_43_qs)
19316 );
19317 1/1 assign reg2hw.mio_pad_attr[43].input_disable.qe = mio_pad_attr_43_qe;
Tests: T96 T97 T98
19318
19319 // F[slew_rate_43]: 17:16
19320 prim_subreg_ext #(
19321 .DW (2)
19322 ) u_mio_pad_attr_43_slew_rate_43 (
19323 .re (mio_pad_attr_43_re),
19324 .we (mio_pad_attr_43_gated_we),
19325 .wd (mio_pad_attr_43_slew_rate_43_wd),
19326 .d (hw2reg.mio_pad_attr[43].slew_rate.d),
19327 .qre (),
19328 .qe (mio_pad_attr_43_flds_we[8]),
19329 .q (reg2hw.mio_pad_attr[43].slew_rate.q),
19330 .ds (),
19331 .qs (mio_pad_attr_43_slew_rate_43_qs)
19332 );
19333 1/1 assign reg2hw.mio_pad_attr[43].slew_rate.qe = mio_pad_attr_43_qe;
Tests: T96 T97 T98
19334
19335 // F[drive_strength_43]: 23:20
19336 prim_subreg_ext #(
19337 .DW (4)
19338 ) u_mio_pad_attr_43_drive_strength_43 (
19339 .re (mio_pad_attr_43_re),
19340 .we (mio_pad_attr_43_gated_we),
19341 .wd (mio_pad_attr_43_drive_strength_43_wd),
19342 .d (hw2reg.mio_pad_attr[43].drive_strength.d),
19343 .qre (),
19344 .qe (mio_pad_attr_43_flds_we[9]),
19345 .q (reg2hw.mio_pad_attr[43].drive_strength.q),
19346 .ds (),
19347 .qs (mio_pad_attr_43_drive_strength_43_qs)
19348 );
19349 1/1 assign reg2hw.mio_pad_attr[43].drive_strength.qe = mio_pad_attr_43_qe;
Tests: T96 T97 T98
19350
19351
19352 // Subregister 44 of Multireg mio_pad_attr
19353 // R[mio_pad_attr_44]: V(True)
19354 logic mio_pad_attr_44_qe;
19355 logic [9:0] mio_pad_attr_44_flds_we;
19356 1/1 assign mio_pad_attr_44_qe = &mio_pad_attr_44_flds_we;
Tests: T96 T97 T98
19357 // Create REGWEN-gated WE signal
19358 logic mio_pad_attr_44_gated_we;
19359 1/1 assign mio_pad_attr_44_gated_we = mio_pad_attr_44_we & mio_pad_attr_regwen_44_qs;
Tests: T71 T96 T97
19360 // F[invert_44]: 0:0
19361 prim_subreg_ext #(
19362 .DW (1)
19363 ) u_mio_pad_attr_44_invert_44 (
19364 .re (mio_pad_attr_44_re),
19365 .we (mio_pad_attr_44_gated_we),
19366 .wd (mio_pad_attr_44_invert_44_wd),
19367 .d (hw2reg.mio_pad_attr[44].invert.d),
19368 .qre (),
19369 .qe (mio_pad_attr_44_flds_we[0]),
19370 .q (reg2hw.mio_pad_attr[44].invert.q),
19371 .ds (),
19372 .qs (mio_pad_attr_44_invert_44_qs)
19373 );
19374 1/1 assign reg2hw.mio_pad_attr[44].invert.qe = mio_pad_attr_44_qe;
Tests: T96 T97 T98
19375
19376 // F[virtual_od_en_44]: 1:1
19377 prim_subreg_ext #(
19378 .DW (1)
19379 ) u_mio_pad_attr_44_virtual_od_en_44 (
19380 .re (mio_pad_attr_44_re),
19381 .we (mio_pad_attr_44_gated_we),
19382 .wd (mio_pad_attr_44_virtual_od_en_44_wd),
19383 .d (hw2reg.mio_pad_attr[44].virtual_od_en.d),
19384 .qre (),
19385 .qe (mio_pad_attr_44_flds_we[1]),
19386 .q (reg2hw.mio_pad_attr[44].virtual_od_en.q),
19387 .ds (),
19388 .qs (mio_pad_attr_44_virtual_od_en_44_qs)
19389 );
19390 1/1 assign reg2hw.mio_pad_attr[44].virtual_od_en.qe = mio_pad_attr_44_qe;
Tests: T96 T97 T98
19391
19392 // F[pull_en_44]: 2:2
19393 prim_subreg_ext #(
19394 .DW (1)
19395 ) u_mio_pad_attr_44_pull_en_44 (
19396 .re (mio_pad_attr_44_re),
19397 .we (mio_pad_attr_44_gated_we),
19398 .wd (mio_pad_attr_44_pull_en_44_wd),
19399 .d (hw2reg.mio_pad_attr[44].pull_en.d),
19400 .qre (),
19401 .qe (mio_pad_attr_44_flds_we[2]),
19402 .q (reg2hw.mio_pad_attr[44].pull_en.q),
19403 .ds (),
19404 .qs (mio_pad_attr_44_pull_en_44_qs)
19405 );
19406 1/1 assign reg2hw.mio_pad_attr[44].pull_en.qe = mio_pad_attr_44_qe;
Tests: T96 T97 T98
19407
19408 // F[pull_select_44]: 3:3
19409 prim_subreg_ext #(
19410 .DW (1)
19411 ) u_mio_pad_attr_44_pull_select_44 (
19412 .re (mio_pad_attr_44_re),
19413 .we (mio_pad_attr_44_gated_we),
19414 .wd (mio_pad_attr_44_pull_select_44_wd),
19415 .d (hw2reg.mio_pad_attr[44].pull_select.d),
19416 .qre (),
19417 .qe (mio_pad_attr_44_flds_we[3]),
19418 .q (reg2hw.mio_pad_attr[44].pull_select.q),
19419 .ds (),
19420 .qs (mio_pad_attr_44_pull_select_44_qs)
19421 );
19422 1/1 assign reg2hw.mio_pad_attr[44].pull_select.qe = mio_pad_attr_44_qe;
Tests: T96 T97 T98
19423
19424 // F[keeper_en_44]: 4:4
19425 prim_subreg_ext #(
19426 .DW (1)
19427 ) u_mio_pad_attr_44_keeper_en_44 (
19428 .re (mio_pad_attr_44_re),
19429 .we (mio_pad_attr_44_gated_we),
19430 .wd (mio_pad_attr_44_keeper_en_44_wd),
19431 .d (hw2reg.mio_pad_attr[44].keeper_en.d),
19432 .qre (),
19433 .qe (mio_pad_attr_44_flds_we[4]),
19434 .q (reg2hw.mio_pad_attr[44].keeper_en.q),
19435 .ds (),
19436 .qs (mio_pad_attr_44_keeper_en_44_qs)
19437 );
19438 1/1 assign reg2hw.mio_pad_attr[44].keeper_en.qe = mio_pad_attr_44_qe;
Tests: T96 T97 T98
19439
19440 // F[schmitt_en_44]: 5:5
19441 prim_subreg_ext #(
19442 .DW (1)
19443 ) u_mio_pad_attr_44_schmitt_en_44 (
19444 .re (mio_pad_attr_44_re),
19445 .we (mio_pad_attr_44_gated_we),
19446 .wd (mio_pad_attr_44_schmitt_en_44_wd),
19447 .d (hw2reg.mio_pad_attr[44].schmitt_en.d),
19448 .qre (),
19449 .qe (mio_pad_attr_44_flds_we[5]),
19450 .q (reg2hw.mio_pad_attr[44].schmitt_en.q),
19451 .ds (),
19452 .qs (mio_pad_attr_44_schmitt_en_44_qs)
19453 );
19454 1/1 assign reg2hw.mio_pad_attr[44].schmitt_en.qe = mio_pad_attr_44_qe;
Tests: T96 T97 T98
19455
19456 // F[od_en_44]: 6:6
19457 prim_subreg_ext #(
19458 .DW (1)
19459 ) u_mio_pad_attr_44_od_en_44 (
19460 .re (mio_pad_attr_44_re),
19461 .we (mio_pad_attr_44_gated_we),
19462 .wd (mio_pad_attr_44_od_en_44_wd),
19463 .d (hw2reg.mio_pad_attr[44].od_en.d),
19464 .qre (),
19465 .qe (mio_pad_attr_44_flds_we[6]),
19466 .q (reg2hw.mio_pad_attr[44].od_en.q),
19467 .ds (),
19468 .qs (mio_pad_attr_44_od_en_44_qs)
19469 );
19470 1/1 assign reg2hw.mio_pad_attr[44].od_en.qe = mio_pad_attr_44_qe;
Tests: T96 T97 T98
19471
19472 // F[input_disable_44]: 7:7
19473 prim_subreg_ext #(
19474 .DW (1)
19475 ) u_mio_pad_attr_44_input_disable_44 (
19476 .re (mio_pad_attr_44_re),
19477 .we (mio_pad_attr_44_gated_we),
19478 .wd (mio_pad_attr_44_input_disable_44_wd),
19479 .d (hw2reg.mio_pad_attr[44].input_disable.d),
19480 .qre (),
19481 .qe (mio_pad_attr_44_flds_we[7]),
19482 .q (reg2hw.mio_pad_attr[44].input_disable.q),
19483 .ds (),
19484 .qs (mio_pad_attr_44_input_disable_44_qs)
19485 );
19486 1/1 assign reg2hw.mio_pad_attr[44].input_disable.qe = mio_pad_attr_44_qe;
Tests: T96 T97 T98
19487
19488 // F[slew_rate_44]: 17:16
19489 prim_subreg_ext #(
19490 .DW (2)
19491 ) u_mio_pad_attr_44_slew_rate_44 (
19492 .re (mio_pad_attr_44_re),
19493 .we (mio_pad_attr_44_gated_we),
19494 .wd (mio_pad_attr_44_slew_rate_44_wd),
19495 .d (hw2reg.mio_pad_attr[44].slew_rate.d),
19496 .qre (),
19497 .qe (mio_pad_attr_44_flds_we[8]),
19498 .q (reg2hw.mio_pad_attr[44].slew_rate.q),
19499 .ds (),
19500 .qs (mio_pad_attr_44_slew_rate_44_qs)
19501 );
19502 1/1 assign reg2hw.mio_pad_attr[44].slew_rate.qe = mio_pad_attr_44_qe;
Tests: T96 T97 T98
19503
19504 // F[drive_strength_44]: 23:20
19505 prim_subreg_ext #(
19506 .DW (4)
19507 ) u_mio_pad_attr_44_drive_strength_44 (
19508 .re (mio_pad_attr_44_re),
19509 .we (mio_pad_attr_44_gated_we),
19510 .wd (mio_pad_attr_44_drive_strength_44_wd),
19511 .d (hw2reg.mio_pad_attr[44].drive_strength.d),
19512 .qre (),
19513 .qe (mio_pad_attr_44_flds_we[9]),
19514 .q (reg2hw.mio_pad_attr[44].drive_strength.q),
19515 .ds (),
19516 .qs (mio_pad_attr_44_drive_strength_44_qs)
19517 );
19518 1/1 assign reg2hw.mio_pad_attr[44].drive_strength.qe = mio_pad_attr_44_qe;
Tests: T96 T97 T98
19519
19520
19521 // Subregister 45 of Multireg mio_pad_attr
19522 // R[mio_pad_attr_45]: V(True)
19523 logic mio_pad_attr_45_qe;
19524 logic [9:0] mio_pad_attr_45_flds_we;
19525 1/1 assign mio_pad_attr_45_qe = &mio_pad_attr_45_flds_we;
Tests: T96 T97 T98
19526 // Create REGWEN-gated WE signal
19527 logic mio_pad_attr_45_gated_we;
19528 1/1 assign mio_pad_attr_45_gated_we = mio_pad_attr_45_we & mio_pad_attr_regwen_45_qs;
Tests: T71 T96 T97
19529 // F[invert_45]: 0:0
19530 prim_subreg_ext #(
19531 .DW (1)
19532 ) u_mio_pad_attr_45_invert_45 (
19533 .re (mio_pad_attr_45_re),
19534 .we (mio_pad_attr_45_gated_we),
19535 .wd (mio_pad_attr_45_invert_45_wd),
19536 .d (hw2reg.mio_pad_attr[45].invert.d),
19537 .qre (),
19538 .qe (mio_pad_attr_45_flds_we[0]),
19539 .q (reg2hw.mio_pad_attr[45].invert.q),
19540 .ds (),
19541 .qs (mio_pad_attr_45_invert_45_qs)
19542 );
19543 1/1 assign reg2hw.mio_pad_attr[45].invert.qe = mio_pad_attr_45_qe;
Tests: T96 T97 T98
19544
19545 // F[virtual_od_en_45]: 1:1
19546 prim_subreg_ext #(
19547 .DW (1)
19548 ) u_mio_pad_attr_45_virtual_od_en_45 (
19549 .re (mio_pad_attr_45_re),
19550 .we (mio_pad_attr_45_gated_we),
19551 .wd (mio_pad_attr_45_virtual_od_en_45_wd),
19552 .d (hw2reg.mio_pad_attr[45].virtual_od_en.d),
19553 .qre (),
19554 .qe (mio_pad_attr_45_flds_we[1]),
19555 .q (reg2hw.mio_pad_attr[45].virtual_od_en.q),
19556 .ds (),
19557 .qs (mio_pad_attr_45_virtual_od_en_45_qs)
19558 );
19559 1/1 assign reg2hw.mio_pad_attr[45].virtual_od_en.qe = mio_pad_attr_45_qe;
Tests: T96 T97 T98
19560
19561 // F[pull_en_45]: 2:2
19562 prim_subreg_ext #(
19563 .DW (1)
19564 ) u_mio_pad_attr_45_pull_en_45 (
19565 .re (mio_pad_attr_45_re),
19566 .we (mio_pad_attr_45_gated_we),
19567 .wd (mio_pad_attr_45_pull_en_45_wd),
19568 .d (hw2reg.mio_pad_attr[45].pull_en.d),
19569 .qre (),
19570 .qe (mio_pad_attr_45_flds_we[2]),
19571 .q (reg2hw.mio_pad_attr[45].pull_en.q),
19572 .ds (),
19573 .qs (mio_pad_attr_45_pull_en_45_qs)
19574 );
19575 1/1 assign reg2hw.mio_pad_attr[45].pull_en.qe = mio_pad_attr_45_qe;
Tests: T96 T97 T98
19576
19577 // F[pull_select_45]: 3:3
19578 prim_subreg_ext #(
19579 .DW (1)
19580 ) u_mio_pad_attr_45_pull_select_45 (
19581 .re (mio_pad_attr_45_re),
19582 .we (mio_pad_attr_45_gated_we),
19583 .wd (mio_pad_attr_45_pull_select_45_wd),
19584 .d (hw2reg.mio_pad_attr[45].pull_select.d),
19585 .qre (),
19586 .qe (mio_pad_attr_45_flds_we[3]),
19587 .q (reg2hw.mio_pad_attr[45].pull_select.q),
19588 .ds (),
19589 .qs (mio_pad_attr_45_pull_select_45_qs)
19590 );
19591 1/1 assign reg2hw.mio_pad_attr[45].pull_select.qe = mio_pad_attr_45_qe;
Tests: T96 T97 T98
19592
19593 // F[keeper_en_45]: 4:4
19594 prim_subreg_ext #(
19595 .DW (1)
19596 ) u_mio_pad_attr_45_keeper_en_45 (
19597 .re (mio_pad_attr_45_re),
19598 .we (mio_pad_attr_45_gated_we),
19599 .wd (mio_pad_attr_45_keeper_en_45_wd),
19600 .d (hw2reg.mio_pad_attr[45].keeper_en.d),
19601 .qre (),
19602 .qe (mio_pad_attr_45_flds_we[4]),
19603 .q (reg2hw.mio_pad_attr[45].keeper_en.q),
19604 .ds (),
19605 .qs (mio_pad_attr_45_keeper_en_45_qs)
19606 );
19607 1/1 assign reg2hw.mio_pad_attr[45].keeper_en.qe = mio_pad_attr_45_qe;
Tests: T96 T97 T98
19608
19609 // F[schmitt_en_45]: 5:5
19610 prim_subreg_ext #(
19611 .DW (1)
19612 ) u_mio_pad_attr_45_schmitt_en_45 (
19613 .re (mio_pad_attr_45_re),
19614 .we (mio_pad_attr_45_gated_we),
19615 .wd (mio_pad_attr_45_schmitt_en_45_wd),
19616 .d (hw2reg.mio_pad_attr[45].schmitt_en.d),
19617 .qre (),
19618 .qe (mio_pad_attr_45_flds_we[5]),
19619 .q (reg2hw.mio_pad_attr[45].schmitt_en.q),
19620 .ds (),
19621 .qs (mio_pad_attr_45_schmitt_en_45_qs)
19622 );
19623 1/1 assign reg2hw.mio_pad_attr[45].schmitt_en.qe = mio_pad_attr_45_qe;
Tests: T96 T97 T98
19624
19625 // F[od_en_45]: 6:6
19626 prim_subreg_ext #(
19627 .DW (1)
19628 ) u_mio_pad_attr_45_od_en_45 (
19629 .re (mio_pad_attr_45_re),
19630 .we (mio_pad_attr_45_gated_we),
19631 .wd (mio_pad_attr_45_od_en_45_wd),
19632 .d (hw2reg.mio_pad_attr[45].od_en.d),
19633 .qre (),
19634 .qe (mio_pad_attr_45_flds_we[6]),
19635 .q (reg2hw.mio_pad_attr[45].od_en.q),
19636 .ds (),
19637 .qs (mio_pad_attr_45_od_en_45_qs)
19638 );
19639 1/1 assign reg2hw.mio_pad_attr[45].od_en.qe = mio_pad_attr_45_qe;
Tests: T96 T97 T98
19640
19641 // F[input_disable_45]: 7:7
19642 prim_subreg_ext #(
19643 .DW (1)
19644 ) u_mio_pad_attr_45_input_disable_45 (
19645 .re (mio_pad_attr_45_re),
19646 .we (mio_pad_attr_45_gated_we),
19647 .wd (mio_pad_attr_45_input_disable_45_wd),
19648 .d (hw2reg.mio_pad_attr[45].input_disable.d),
19649 .qre (),
19650 .qe (mio_pad_attr_45_flds_we[7]),
19651 .q (reg2hw.mio_pad_attr[45].input_disable.q),
19652 .ds (),
19653 .qs (mio_pad_attr_45_input_disable_45_qs)
19654 );
19655 1/1 assign reg2hw.mio_pad_attr[45].input_disable.qe = mio_pad_attr_45_qe;
Tests: T96 T97 T98
19656
19657 // F[slew_rate_45]: 17:16
19658 prim_subreg_ext #(
19659 .DW (2)
19660 ) u_mio_pad_attr_45_slew_rate_45 (
19661 .re (mio_pad_attr_45_re),
19662 .we (mio_pad_attr_45_gated_we),
19663 .wd (mio_pad_attr_45_slew_rate_45_wd),
19664 .d (hw2reg.mio_pad_attr[45].slew_rate.d),
19665 .qre (),
19666 .qe (mio_pad_attr_45_flds_we[8]),
19667 .q (reg2hw.mio_pad_attr[45].slew_rate.q),
19668 .ds (),
19669 .qs (mio_pad_attr_45_slew_rate_45_qs)
19670 );
19671 1/1 assign reg2hw.mio_pad_attr[45].slew_rate.qe = mio_pad_attr_45_qe;
Tests: T96 T97 T98
19672
19673 // F[drive_strength_45]: 23:20
19674 prim_subreg_ext #(
19675 .DW (4)
19676 ) u_mio_pad_attr_45_drive_strength_45 (
19677 .re (mio_pad_attr_45_re),
19678 .we (mio_pad_attr_45_gated_we),
19679 .wd (mio_pad_attr_45_drive_strength_45_wd),
19680 .d (hw2reg.mio_pad_attr[45].drive_strength.d),
19681 .qre (),
19682 .qe (mio_pad_attr_45_flds_we[9]),
19683 .q (reg2hw.mio_pad_attr[45].drive_strength.q),
19684 .ds (),
19685 .qs (mio_pad_attr_45_drive_strength_45_qs)
19686 );
19687 1/1 assign reg2hw.mio_pad_attr[45].drive_strength.qe = mio_pad_attr_45_qe;
Tests: T96 T97 T98
19688
19689
19690 // Subregister 46 of Multireg mio_pad_attr
19691 // R[mio_pad_attr_46]: V(True)
19692 logic mio_pad_attr_46_qe;
19693 logic [9:0] mio_pad_attr_46_flds_we;
19694 1/1 assign mio_pad_attr_46_qe = &mio_pad_attr_46_flds_we;
Tests: T96 T97 T98
19695 // Create REGWEN-gated WE signal
19696 logic mio_pad_attr_46_gated_we;
19697 1/1 assign mio_pad_attr_46_gated_we = mio_pad_attr_46_we & mio_pad_attr_regwen_46_qs;
Tests: T96 T97 T98
19698 // F[invert_46]: 0:0
19699 prim_subreg_ext #(
19700 .DW (1)
19701 ) u_mio_pad_attr_46_invert_46 (
19702 .re (mio_pad_attr_46_re),
19703 .we (mio_pad_attr_46_gated_we),
19704 .wd (mio_pad_attr_46_invert_46_wd),
19705 .d (hw2reg.mio_pad_attr[46].invert.d),
19706 .qre (),
19707 .qe (mio_pad_attr_46_flds_we[0]),
19708 .q (reg2hw.mio_pad_attr[46].invert.q),
19709 .ds (),
19710 .qs (mio_pad_attr_46_invert_46_qs)
19711 );
19712 1/1 assign reg2hw.mio_pad_attr[46].invert.qe = mio_pad_attr_46_qe;
Tests: T96 T97 T98
19713
19714 // F[virtual_od_en_46]: 1:1
19715 prim_subreg_ext #(
19716 .DW (1)
19717 ) u_mio_pad_attr_46_virtual_od_en_46 (
19718 .re (mio_pad_attr_46_re),
19719 .we (mio_pad_attr_46_gated_we),
19720 .wd (mio_pad_attr_46_virtual_od_en_46_wd),
19721 .d (hw2reg.mio_pad_attr[46].virtual_od_en.d),
19722 .qre (),
19723 .qe (mio_pad_attr_46_flds_we[1]),
19724 .q (reg2hw.mio_pad_attr[46].virtual_od_en.q),
19725 .ds (),
19726 .qs (mio_pad_attr_46_virtual_od_en_46_qs)
19727 );
19728 1/1 assign reg2hw.mio_pad_attr[46].virtual_od_en.qe = mio_pad_attr_46_qe;
Tests: T96 T97 T98
19729
19730 // F[pull_en_46]: 2:2
19731 prim_subreg_ext #(
19732 .DW (1)
19733 ) u_mio_pad_attr_46_pull_en_46 (
19734 .re (mio_pad_attr_46_re),
19735 .we (mio_pad_attr_46_gated_we),
19736 .wd (mio_pad_attr_46_pull_en_46_wd),
19737 .d (hw2reg.mio_pad_attr[46].pull_en.d),
19738 .qre (),
19739 .qe (mio_pad_attr_46_flds_we[2]),
19740 .q (reg2hw.mio_pad_attr[46].pull_en.q),
19741 .ds (),
19742 .qs (mio_pad_attr_46_pull_en_46_qs)
19743 );
19744 1/1 assign reg2hw.mio_pad_attr[46].pull_en.qe = mio_pad_attr_46_qe;
Tests: T96 T97 T98
19745
19746 // F[pull_select_46]: 3:3
19747 prim_subreg_ext #(
19748 .DW (1)
19749 ) u_mio_pad_attr_46_pull_select_46 (
19750 .re (mio_pad_attr_46_re),
19751 .we (mio_pad_attr_46_gated_we),
19752 .wd (mio_pad_attr_46_pull_select_46_wd),
19753 .d (hw2reg.mio_pad_attr[46].pull_select.d),
19754 .qre (),
19755 .qe (mio_pad_attr_46_flds_we[3]),
19756 .q (reg2hw.mio_pad_attr[46].pull_select.q),
19757 .ds (),
19758 .qs (mio_pad_attr_46_pull_select_46_qs)
19759 );
19760 1/1 assign reg2hw.mio_pad_attr[46].pull_select.qe = mio_pad_attr_46_qe;
Tests: T96 T97 T98
19761
19762 // F[keeper_en_46]: 4:4
19763 prim_subreg_ext #(
19764 .DW (1)
19765 ) u_mio_pad_attr_46_keeper_en_46 (
19766 .re (mio_pad_attr_46_re),
19767 .we (mio_pad_attr_46_gated_we),
19768 .wd (mio_pad_attr_46_keeper_en_46_wd),
19769 .d (hw2reg.mio_pad_attr[46].keeper_en.d),
19770 .qre (),
19771 .qe (mio_pad_attr_46_flds_we[4]),
19772 .q (reg2hw.mio_pad_attr[46].keeper_en.q),
19773 .ds (),
19774 .qs (mio_pad_attr_46_keeper_en_46_qs)
19775 );
19776 1/1 assign reg2hw.mio_pad_attr[46].keeper_en.qe = mio_pad_attr_46_qe;
Tests: T96 T97 T98
19777
19778 // F[schmitt_en_46]: 5:5
19779 prim_subreg_ext #(
19780 .DW (1)
19781 ) u_mio_pad_attr_46_schmitt_en_46 (
19782 .re (mio_pad_attr_46_re),
19783 .we (mio_pad_attr_46_gated_we),
19784 .wd (mio_pad_attr_46_schmitt_en_46_wd),
19785 .d (hw2reg.mio_pad_attr[46].schmitt_en.d),
19786 .qre (),
19787 .qe (mio_pad_attr_46_flds_we[5]),
19788 .q (reg2hw.mio_pad_attr[46].schmitt_en.q),
19789 .ds (),
19790 .qs (mio_pad_attr_46_schmitt_en_46_qs)
19791 );
19792 1/1 assign reg2hw.mio_pad_attr[46].schmitt_en.qe = mio_pad_attr_46_qe;
Tests: T96 T97 T98
19793
19794 // F[od_en_46]: 6:6
19795 prim_subreg_ext #(
19796 .DW (1)
19797 ) u_mio_pad_attr_46_od_en_46 (
19798 .re (mio_pad_attr_46_re),
19799 .we (mio_pad_attr_46_gated_we),
19800 .wd (mio_pad_attr_46_od_en_46_wd),
19801 .d (hw2reg.mio_pad_attr[46].od_en.d),
19802 .qre (),
19803 .qe (mio_pad_attr_46_flds_we[6]),
19804 .q (reg2hw.mio_pad_attr[46].od_en.q),
19805 .ds (),
19806 .qs (mio_pad_attr_46_od_en_46_qs)
19807 );
19808 1/1 assign reg2hw.mio_pad_attr[46].od_en.qe = mio_pad_attr_46_qe;
Tests: T96 T97 T98
19809
19810 // F[input_disable_46]: 7:7
19811 prim_subreg_ext #(
19812 .DW (1)
19813 ) u_mio_pad_attr_46_input_disable_46 (
19814 .re (mio_pad_attr_46_re),
19815 .we (mio_pad_attr_46_gated_we),
19816 .wd (mio_pad_attr_46_input_disable_46_wd),
19817 .d (hw2reg.mio_pad_attr[46].input_disable.d),
19818 .qre (),
19819 .qe (mio_pad_attr_46_flds_we[7]),
19820 .q (reg2hw.mio_pad_attr[46].input_disable.q),
19821 .ds (),
19822 .qs (mio_pad_attr_46_input_disable_46_qs)
19823 );
19824 1/1 assign reg2hw.mio_pad_attr[46].input_disable.qe = mio_pad_attr_46_qe;
Tests: T96 T97 T98
19825
19826 // F[slew_rate_46]: 17:16
19827 prim_subreg_ext #(
19828 .DW (2)
19829 ) u_mio_pad_attr_46_slew_rate_46 (
19830 .re (mio_pad_attr_46_re),
19831 .we (mio_pad_attr_46_gated_we),
19832 .wd (mio_pad_attr_46_slew_rate_46_wd),
19833 .d (hw2reg.mio_pad_attr[46].slew_rate.d),
19834 .qre (),
19835 .qe (mio_pad_attr_46_flds_we[8]),
19836 .q (reg2hw.mio_pad_attr[46].slew_rate.q),
19837 .ds (),
19838 .qs (mio_pad_attr_46_slew_rate_46_qs)
19839 );
19840 1/1 assign reg2hw.mio_pad_attr[46].slew_rate.qe = mio_pad_attr_46_qe;
Tests: T96 T97 T98
19841
19842 // F[drive_strength_46]: 23:20
19843 prim_subreg_ext #(
19844 .DW (4)
19845 ) u_mio_pad_attr_46_drive_strength_46 (
19846 .re (mio_pad_attr_46_re),
19847 .we (mio_pad_attr_46_gated_we),
19848 .wd (mio_pad_attr_46_drive_strength_46_wd),
19849 .d (hw2reg.mio_pad_attr[46].drive_strength.d),
19850 .qre (),
19851 .qe (mio_pad_attr_46_flds_we[9]),
19852 .q (reg2hw.mio_pad_attr[46].drive_strength.q),
19853 .ds (),
19854 .qs (mio_pad_attr_46_drive_strength_46_qs)
19855 );
19856 1/1 assign reg2hw.mio_pad_attr[46].drive_strength.qe = mio_pad_attr_46_qe;
Tests: T96 T97 T98
19857
19858
19859 // Subregister 0 of Multireg dio_pad_attr_regwen
19860 // R[dio_pad_attr_regwen_0]: V(False)
19861 prim_subreg #(
19862 .DW (1),
19863 .SwAccess(prim_subreg_pkg::SwAccessW0C),
19864 .RESVAL (1'h1),
19865 .Mubi (1'b0)
19866 ) u_dio_pad_attr_regwen_0 (
19867 .clk_i (clk_i),
19868 .rst_ni (rst_ni),
19869
19870 // from register interface
19871 .we (dio_pad_attr_regwen_0_we),
19872 .wd (dio_pad_attr_regwen_0_wd),
19873
19874 // from internal hardware
19875 .de (1'b0),
19876 .d ('0),
19877
19878 // to internal hardware
19879 .qe (),
19880 .q (),
19881 .ds (),
19882
19883 // to register interface (read)
19884 .qs (dio_pad_attr_regwen_0_qs)
19885 );
19886
19887
19888 // Subregister 1 of Multireg dio_pad_attr_regwen
19889 // R[dio_pad_attr_regwen_1]: V(False)
19890 prim_subreg #(
19891 .DW (1),
19892 .SwAccess(prim_subreg_pkg::SwAccessW0C),
19893 .RESVAL (1'h1),
19894 .Mubi (1'b0)
19895 ) u_dio_pad_attr_regwen_1 (
19896 .clk_i (clk_i),
19897 .rst_ni (rst_ni),
19898
19899 // from register interface
19900 .we (dio_pad_attr_regwen_1_we),
19901 .wd (dio_pad_attr_regwen_1_wd),
19902
19903 // from internal hardware
19904 .de (1'b0),
19905 .d ('0),
19906
19907 // to internal hardware
19908 .qe (),
19909 .q (),
19910 .ds (),
19911
19912 // to register interface (read)
19913 .qs (dio_pad_attr_regwen_1_qs)
19914 );
19915
19916
19917 // Subregister 2 of Multireg dio_pad_attr_regwen
19918 // R[dio_pad_attr_regwen_2]: V(False)
19919 prim_subreg #(
19920 .DW (1),
19921 .SwAccess(prim_subreg_pkg::SwAccessW0C),
19922 .RESVAL (1'h1),
19923 .Mubi (1'b0)
19924 ) u_dio_pad_attr_regwen_2 (
19925 .clk_i (clk_i),
19926 .rst_ni (rst_ni),
19927
19928 // from register interface
19929 .we (dio_pad_attr_regwen_2_we),
19930 .wd (dio_pad_attr_regwen_2_wd),
19931
19932 // from internal hardware
19933 .de (1'b0),
19934 .d ('0),
19935
19936 // to internal hardware
19937 .qe (),
19938 .q (),
19939 .ds (),
19940
19941 // to register interface (read)
19942 .qs (dio_pad_attr_regwen_2_qs)
19943 );
19944
19945
19946 // Subregister 3 of Multireg dio_pad_attr_regwen
19947 // R[dio_pad_attr_regwen_3]: V(False)
19948 prim_subreg #(
19949 .DW (1),
19950 .SwAccess(prim_subreg_pkg::SwAccessW0C),
19951 .RESVAL (1'h1),
19952 .Mubi (1'b0)
19953 ) u_dio_pad_attr_regwen_3 (
19954 .clk_i (clk_i),
19955 .rst_ni (rst_ni),
19956
19957 // from register interface
19958 .we (dio_pad_attr_regwen_3_we),
19959 .wd (dio_pad_attr_regwen_3_wd),
19960
19961 // from internal hardware
19962 .de (1'b0),
19963 .d ('0),
19964
19965 // to internal hardware
19966 .qe (),
19967 .q (),
19968 .ds (),
19969
19970 // to register interface (read)
19971 .qs (dio_pad_attr_regwen_3_qs)
19972 );
19973
19974
19975 // Subregister 4 of Multireg dio_pad_attr_regwen
19976 // R[dio_pad_attr_regwen_4]: V(False)
19977 prim_subreg #(
19978 .DW (1),
19979 .SwAccess(prim_subreg_pkg::SwAccessW0C),
19980 .RESVAL (1'h1),
19981 .Mubi (1'b0)
19982 ) u_dio_pad_attr_regwen_4 (
19983 .clk_i (clk_i),
19984 .rst_ni (rst_ni),
19985
19986 // from register interface
19987 .we (dio_pad_attr_regwen_4_we),
19988 .wd (dio_pad_attr_regwen_4_wd),
19989
19990 // from internal hardware
19991 .de (1'b0),
19992 .d ('0),
19993
19994 // to internal hardware
19995 .qe (),
19996 .q (),
19997 .ds (),
19998
19999 // to register interface (read)
20000 .qs (dio_pad_attr_regwen_4_qs)
20001 );
20002
20003
20004 // Subregister 5 of Multireg dio_pad_attr_regwen
20005 // R[dio_pad_attr_regwen_5]: V(False)
20006 prim_subreg #(
20007 .DW (1),
20008 .SwAccess(prim_subreg_pkg::SwAccessW0C),
20009 .RESVAL (1'h1),
20010 .Mubi (1'b0)
20011 ) u_dio_pad_attr_regwen_5 (
20012 .clk_i (clk_i),
20013 .rst_ni (rst_ni),
20014
20015 // from register interface
20016 .we (dio_pad_attr_regwen_5_we),
20017 .wd (dio_pad_attr_regwen_5_wd),
20018
20019 // from internal hardware
20020 .de (1'b0),
20021 .d ('0),
20022
20023 // to internal hardware
20024 .qe (),
20025 .q (),
20026 .ds (),
20027
20028 // to register interface (read)
20029 .qs (dio_pad_attr_regwen_5_qs)
20030 );
20031
20032
20033 // Subregister 6 of Multireg dio_pad_attr_regwen
20034 // R[dio_pad_attr_regwen_6]: V(False)
20035 prim_subreg #(
20036 .DW (1),
20037 .SwAccess(prim_subreg_pkg::SwAccessW0C),
20038 .RESVAL (1'h1),
20039 .Mubi (1'b0)
20040 ) u_dio_pad_attr_regwen_6 (
20041 .clk_i (clk_i),
20042 .rst_ni (rst_ni),
20043
20044 // from register interface
20045 .we (dio_pad_attr_regwen_6_we),
20046 .wd (dio_pad_attr_regwen_6_wd),
20047
20048 // from internal hardware
20049 .de (1'b0),
20050 .d ('0),
20051
20052 // to internal hardware
20053 .qe (),
20054 .q (),
20055 .ds (),
20056
20057 // to register interface (read)
20058 .qs (dio_pad_attr_regwen_6_qs)
20059 );
20060
20061
20062 // Subregister 7 of Multireg dio_pad_attr_regwen
20063 // R[dio_pad_attr_regwen_7]: V(False)
20064 prim_subreg #(
20065 .DW (1),
20066 .SwAccess(prim_subreg_pkg::SwAccessW0C),
20067 .RESVAL (1'h1),
20068 .Mubi (1'b0)
20069 ) u_dio_pad_attr_regwen_7 (
20070 .clk_i (clk_i),
20071 .rst_ni (rst_ni),
20072
20073 // from register interface
20074 .we (dio_pad_attr_regwen_7_we),
20075 .wd (dio_pad_attr_regwen_7_wd),
20076
20077 // from internal hardware
20078 .de (1'b0),
20079 .d ('0),
20080
20081 // to internal hardware
20082 .qe (),
20083 .q (),
20084 .ds (),
20085
20086 // to register interface (read)
20087 .qs (dio_pad_attr_regwen_7_qs)
20088 );
20089
20090
20091 // Subregister 8 of Multireg dio_pad_attr_regwen
20092 // R[dio_pad_attr_regwen_8]: V(False)
20093 prim_subreg #(
20094 .DW (1),
20095 .SwAccess(prim_subreg_pkg::SwAccessW0C),
20096 .RESVAL (1'h1),
20097 .Mubi (1'b0)
20098 ) u_dio_pad_attr_regwen_8 (
20099 .clk_i (clk_i),
20100 .rst_ni (rst_ni),
20101
20102 // from register interface
20103 .we (dio_pad_attr_regwen_8_we),
20104 .wd (dio_pad_attr_regwen_8_wd),
20105
20106 // from internal hardware
20107 .de (1'b0),
20108 .d ('0),
20109
20110 // to internal hardware
20111 .qe (),
20112 .q (),
20113 .ds (),
20114
20115 // to register interface (read)
20116 .qs (dio_pad_attr_regwen_8_qs)
20117 );
20118
20119
20120 // Subregister 9 of Multireg dio_pad_attr_regwen
20121 // R[dio_pad_attr_regwen_9]: V(False)
20122 prim_subreg #(
20123 .DW (1),
20124 .SwAccess(prim_subreg_pkg::SwAccessW0C),
20125 .RESVAL (1'h1),
20126 .Mubi (1'b0)
20127 ) u_dio_pad_attr_regwen_9 (
20128 .clk_i (clk_i),
20129 .rst_ni (rst_ni),
20130
20131 // from register interface
20132 .we (dio_pad_attr_regwen_9_we),
20133 .wd (dio_pad_attr_regwen_9_wd),
20134
20135 // from internal hardware
20136 .de (1'b0),
20137 .d ('0),
20138
20139 // to internal hardware
20140 .qe (),
20141 .q (),
20142 .ds (),
20143
20144 // to register interface (read)
20145 .qs (dio_pad_attr_regwen_9_qs)
20146 );
20147
20148
20149 // Subregister 10 of Multireg dio_pad_attr_regwen
20150 // R[dio_pad_attr_regwen_10]: V(False)
20151 prim_subreg #(
20152 .DW (1),
20153 .SwAccess(prim_subreg_pkg::SwAccessW0C),
20154 .RESVAL (1'h1),
20155 .Mubi (1'b0)
20156 ) u_dio_pad_attr_regwen_10 (
20157 .clk_i (clk_i),
20158 .rst_ni (rst_ni),
20159
20160 // from register interface
20161 .we (dio_pad_attr_regwen_10_we),
20162 .wd (dio_pad_attr_regwen_10_wd),
20163
20164 // from internal hardware
20165 .de (1'b0),
20166 .d ('0),
20167
20168 // to internal hardware
20169 .qe (),
20170 .q (),
20171 .ds (),
20172
20173 // to register interface (read)
20174 .qs (dio_pad_attr_regwen_10_qs)
20175 );
20176
20177
20178 // Subregister 11 of Multireg dio_pad_attr_regwen
20179 // R[dio_pad_attr_regwen_11]: V(False)
20180 prim_subreg #(
20181 .DW (1),
20182 .SwAccess(prim_subreg_pkg::SwAccessW0C),
20183 .RESVAL (1'h1),
20184 .Mubi (1'b0)
20185 ) u_dio_pad_attr_regwen_11 (
20186 .clk_i (clk_i),
20187 .rst_ni (rst_ni),
20188
20189 // from register interface
20190 .we (dio_pad_attr_regwen_11_we),
20191 .wd (dio_pad_attr_regwen_11_wd),
20192
20193 // from internal hardware
20194 .de (1'b0),
20195 .d ('0),
20196
20197 // to internal hardware
20198 .qe (),
20199 .q (),
20200 .ds (),
20201
20202 // to register interface (read)
20203 .qs (dio_pad_attr_regwen_11_qs)
20204 );
20205
20206
20207 // Subregister 12 of Multireg dio_pad_attr_regwen
20208 // R[dio_pad_attr_regwen_12]: V(False)
20209 prim_subreg #(
20210 .DW (1),
20211 .SwAccess(prim_subreg_pkg::SwAccessW0C),
20212 .RESVAL (1'h1),
20213 .Mubi (1'b0)
20214 ) u_dio_pad_attr_regwen_12 (
20215 .clk_i (clk_i),
20216 .rst_ni (rst_ni),
20217
20218 // from register interface
20219 .we (dio_pad_attr_regwen_12_we),
20220 .wd (dio_pad_attr_regwen_12_wd),
20221
20222 // from internal hardware
20223 .de (1'b0),
20224 .d ('0),
20225
20226 // to internal hardware
20227 .qe (),
20228 .q (),
20229 .ds (),
20230
20231 // to register interface (read)
20232 .qs (dio_pad_attr_regwen_12_qs)
20233 );
20234
20235
20236 // Subregister 13 of Multireg dio_pad_attr_regwen
20237 // R[dio_pad_attr_regwen_13]: V(False)
20238 prim_subreg #(
20239 .DW (1),
20240 .SwAccess(prim_subreg_pkg::SwAccessW0C),
20241 .RESVAL (1'h1),
20242 .Mubi (1'b0)
20243 ) u_dio_pad_attr_regwen_13 (
20244 .clk_i (clk_i),
20245 .rst_ni (rst_ni),
20246
20247 // from register interface
20248 .we (dio_pad_attr_regwen_13_we),
20249 .wd (dio_pad_attr_regwen_13_wd),
20250
20251 // from internal hardware
20252 .de (1'b0),
20253 .d ('0),
20254
20255 // to internal hardware
20256 .qe (),
20257 .q (),
20258 .ds (),
20259
20260 // to register interface (read)
20261 .qs (dio_pad_attr_regwen_13_qs)
20262 );
20263
20264
20265 // Subregister 14 of Multireg dio_pad_attr_regwen
20266 // R[dio_pad_attr_regwen_14]: V(False)
20267 prim_subreg #(
20268 .DW (1),
20269 .SwAccess(prim_subreg_pkg::SwAccessW0C),
20270 .RESVAL (1'h1),
20271 .Mubi (1'b0)
20272 ) u_dio_pad_attr_regwen_14 (
20273 .clk_i (clk_i),
20274 .rst_ni (rst_ni),
20275
20276 // from register interface
20277 .we (dio_pad_attr_regwen_14_we),
20278 .wd (dio_pad_attr_regwen_14_wd),
20279
20280 // from internal hardware
20281 .de (1'b0),
20282 .d ('0),
20283
20284 // to internal hardware
20285 .qe (),
20286 .q (),
20287 .ds (),
20288
20289 // to register interface (read)
20290 .qs (dio_pad_attr_regwen_14_qs)
20291 );
20292
20293
20294 // Subregister 15 of Multireg dio_pad_attr_regwen
20295 // R[dio_pad_attr_regwen_15]: V(False)
20296 prim_subreg #(
20297 .DW (1),
20298 .SwAccess(prim_subreg_pkg::SwAccessW0C),
20299 .RESVAL (1'h1),
20300 .Mubi (1'b0)
20301 ) u_dio_pad_attr_regwen_15 (
20302 .clk_i (clk_i),
20303 .rst_ni (rst_ni),
20304
20305 // from register interface
20306 .we (dio_pad_attr_regwen_15_we),
20307 .wd (dio_pad_attr_regwen_15_wd),
20308
20309 // from internal hardware
20310 .de (1'b0),
20311 .d ('0),
20312
20313 // to internal hardware
20314 .qe (),
20315 .q (),
20316 .ds (),
20317
20318 // to register interface (read)
20319 .qs (dio_pad_attr_regwen_15_qs)
20320 );
20321
20322
20323 // Subregister 0 of Multireg dio_pad_attr
20324 // R[dio_pad_attr_0]: V(True)
20325 logic dio_pad_attr_0_qe;
20326 logic [9:0] dio_pad_attr_0_flds_we;
20327 1/1 assign dio_pad_attr_0_qe = &dio_pad_attr_0_flds_we;
Tests: T1 T2 T3
20328 // Create REGWEN-gated WE signal
20329 logic dio_pad_attr_0_gated_we;
20330 1/1 assign dio_pad_attr_0_gated_we = dio_pad_attr_0_we & dio_pad_attr_regwen_0_qs;
Tests: T1 T2 T3
20331 // F[invert_0]: 0:0
20332 prim_subreg_ext #(
20333 .DW (1)
20334 ) u_dio_pad_attr_0_invert_0 (
20335 .re (dio_pad_attr_0_re),
20336 .we (dio_pad_attr_0_gated_we),
20337 .wd (dio_pad_attr_0_invert_0_wd),
20338 .d (hw2reg.dio_pad_attr[0].invert.d),
20339 .qre (),
20340 .qe (dio_pad_attr_0_flds_we[0]),
20341 .q (reg2hw.dio_pad_attr[0].invert.q),
20342 .ds (),
20343 .qs (dio_pad_attr_0_invert_0_qs)
20344 );
20345 1/1 assign reg2hw.dio_pad_attr[0].invert.qe = dio_pad_attr_0_qe;
Tests: T1 T2 T3
20346
20347 // F[virtual_od_en_0]: 1:1
20348 prim_subreg_ext #(
20349 .DW (1)
20350 ) u_dio_pad_attr_0_virtual_od_en_0 (
20351 .re (dio_pad_attr_0_re),
20352 .we (dio_pad_attr_0_gated_we),
20353 .wd (dio_pad_attr_0_virtual_od_en_0_wd),
20354 .d (hw2reg.dio_pad_attr[0].virtual_od_en.d),
20355 .qre (),
20356 .qe (dio_pad_attr_0_flds_we[1]),
20357 .q (reg2hw.dio_pad_attr[0].virtual_od_en.q),
20358 .ds (),
20359 .qs (dio_pad_attr_0_virtual_od_en_0_qs)
20360 );
20361 1/1 assign reg2hw.dio_pad_attr[0].virtual_od_en.qe = dio_pad_attr_0_qe;
Tests: T1 T2 T3
20362
20363 // F[pull_en_0]: 2:2
20364 prim_subreg_ext #(
20365 .DW (1)
20366 ) u_dio_pad_attr_0_pull_en_0 (
20367 .re (dio_pad_attr_0_re),
20368 .we (dio_pad_attr_0_gated_we),
20369 .wd (dio_pad_attr_0_pull_en_0_wd),
20370 .d (hw2reg.dio_pad_attr[0].pull_en.d),
20371 .qre (),
20372 .qe (dio_pad_attr_0_flds_we[2]),
20373 .q (reg2hw.dio_pad_attr[0].pull_en.q),
20374 .ds (),
20375 .qs (dio_pad_attr_0_pull_en_0_qs)
20376 );
20377 1/1 assign reg2hw.dio_pad_attr[0].pull_en.qe = dio_pad_attr_0_qe;
Tests: T1 T2 T3
20378
20379 // F[pull_select_0]: 3:3
20380 prim_subreg_ext #(
20381 .DW (1)
20382 ) u_dio_pad_attr_0_pull_select_0 (
20383 .re (dio_pad_attr_0_re),
20384 .we (dio_pad_attr_0_gated_we),
20385 .wd (dio_pad_attr_0_pull_select_0_wd),
20386 .d (hw2reg.dio_pad_attr[0].pull_select.d),
20387 .qre (),
20388 .qe (dio_pad_attr_0_flds_we[3]),
20389 .q (reg2hw.dio_pad_attr[0].pull_select.q),
20390 .ds (),
20391 .qs (dio_pad_attr_0_pull_select_0_qs)
20392 );
20393 1/1 assign reg2hw.dio_pad_attr[0].pull_select.qe = dio_pad_attr_0_qe;
Tests: T1 T2 T3
20394
20395 // F[keeper_en_0]: 4:4
20396 prim_subreg_ext #(
20397 .DW (1)
20398 ) u_dio_pad_attr_0_keeper_en_0 (
20399 .re (dio_pad_attr_0_re),
20400 .we (dio_pad_attr_0_gated_we),
20401 .wd (dio_pad_attr_0_keeper_en_0_wd),
20402 .d (hw2reg.dio_pad_attr[0].keeper_en.d),
20403 .qre (),
20404 .qe (dio_pad_attr_0_flds_we[4]),
20405 .q (reg2hw.dio_pad_attr[0].keeper_en.q),
20406 .ds (),
20407 .qs (dio_pad_attr_0_keeper_en_0_qs)
20408 );
20409 1/1 assign reg2hw.dio_pad_attr[0].keeper_en.qe = dio_pad_attr_0_qe;
Tests: T1 T2 T3
20410
20411 // F[schmitt_en_0]: 5:5
20412 prim_subreg_ext #(
20413 .DW (1)
20414 ) u_dio_pad_attr_0_schmitt_en_0 (
20415 .re (dio_pad_attr_0_re),
20416 .we (dio_pad_attr_0_gated_we),
20417 .wd (dio_pad_attr_0_schmitt_en_0_wd),
20418 .d (hw2reg.dio_pad_attr[0].schmitt_en.d),
20419 .qre (),
20420 .qe (dio_pad_attr_0_flds_we[5]),
20421 .q (reg2hw.dio_pad_attr[0].schmitt_en.q),
20422 .ds (),
20423 .qs (dio_pad_attr_0_schmitt_en_0_qs)
20424 );
20425 1/1 assign reg2hw.dio_pad_attr[0].schmitt_en.qe = dio_pad_attr_0_qe;
Tests: T1 T2 T3
20426
20427 // F[od_en_0]: 6:6
20428 prim_subreg_ext #(
20429 .DW (1)
20430 ) u_dio_pad_attr_0_od_en_0 (
20431 .re (dio_pad_attr_0_re),
20432 .we (dio_pad_attr_0_gated_we),
20433 .wd (dio_pad_attr_0_od_en_0_wd),
20434 .d (hw2reg.dio_pad_attr[0].od_en.d),
20435 .qre (),
20436 .qe (dio_pad_attr_0_flds_we[6]),
20437 .q (reg2hw.dio_pad_attr[0].od_en.q),
20438 .ds (),
20439 .qs (dio_pad_attr_0_od_en_0_qs)
20440 );
20441 1/1 assign reg2hw.dio_pad_attr[0].od_en.qe = dio_pad_attr_0_qe;
Tests: T1 T2 T3
20442
20443 // F[input_disable_0]: 7:7
20444 prim_subreg_ext #(
20445 .DW (1)
20446 ) u_dio_pad_attr_0_input_disable_0 (
20447 .re (dio_pad_attr_0_re),
20448 .we (dio_pad_attr_0_gated_we),
20449 .wd (dio_pad_attr_0_input_disable_0_wd),
20450 .d (hw2reg.dio_pad_attr[0].input_disable.d),
20451 .qre (),
20452 .qe (dio_pad_attr_0_flds_we[7]),
20453 .q (reg2hw.dio_pad_attr[0].input_disable.q),
20454 .ds (),
20455 .qs (dio_pad_attr_0_input_disable_0_qs)
20456 );
20457 1/1 assign reg2hw.dio_pad_attr[0].input_disable.qe = dio_pad_attr_0_qe;
Tests: T1 T2 T3
20458
20459 // F[slew_rate_0]: 17:16
20460 prim_subreg_ext #(
20461 .DW (2)
20462 ) u_dio_pad_attr_0_slew_rate_0 (
20463 .re (dio_pad_attr_0_re),
20464 .we (dio_pad_attr_0_gated_we),
20465 .wd (dio_pad_attr_0_slew_rate_0_wd),
20466 .d (hw2reg.dio_pad_attr[0].slew_rate.d),
20467 .qre (),
20468 .qe (dio_pad_attr_0_flds_we[8]),
20469 .q (reg2hw.dio_pad_attr[0].slew_rate.q),
20470 .ds (),
20471 .qs (dio_pad_attr_0_slew_rate_0_qs)
20472 );
20473 1/1 assign reg2hw.dio_pad_attr[0].slew_rate.qe = dio_pad_attr_0_qe;
Tests: T1 T2 T3
20474
20475 // F[drive_strength_0]: 23:20
20476 prim_subreg_ext #(
20477 .DW (4)
20478 ) u_dio_pad_attr_0_drive_strength_0 (
20479 .re (dio_pad_attr_0_re),
20480 .we (dio_pad_attr_0_gated_we),
20481 .wd (dio_pad_attr_0_drive_strength_0_wd),
20482 .d (hw2reg.dio_pad_attr[0].drive_strength.d),
20483 .qre (),
20484 .qe (dio_pad_attr_0_flds_we[9]),
20485 .q (reg2hw.dio_pad_attr[0].drive_strength.q),
20486 .ds (),
20487 .qs (dio_pad_attr_0_drive_strength_0_qs)
20488 );
20489 1/1 assign reg2hw.dio_pad_attr[0].drive_strength.qe = dio_pad_attr_0_qe;
Tests: T1 T2 T3
20490
20491
20492 // Subregister 1 of Multireg dio_pad_attr
20493 // R[dio_pad_attr_1]: V(True)
20494 logic dio_pad_attr_1_qe;
20495 logic [9:0] dio_pad_attr_1_flds_we;
20496 1/1 assign dio_pad_attr_1_qe = &dio_pad_attr_1_flds_we;
Tests: T1 T2 T3
20497 // Create REGWEN-gated WE signal
20498 logic dio_pad_attr_1_gated_we;
20499 1/1 assign dio_pad_attr_1_gated_we = dio_pad_attr_1_we & dio_pad_attr_regwen_1_qs;
Tests: T1 T2 T3
20500 // F[invert_1]: 0:0
20501 prim_subreg_ext #(
20502 .DW (1)
20503 ) u_dio_pad_attr_1_invert_1 (
20504 .re (dio_pad_attr_1_re),
20505 .we (dio_pad_attr_1_gated_we),
20506 .wd (dio_pad_attr_1_invert_1_wd),
20507 .d (hw2reg.dio_pad_attr[1].invert.d),
20508 .qre (),
20509 .qe (dio_pad_attr_1_flds_we[0]),
20510 .q (reg2hw.dio_pad_attr[1].invert.q),
20511 .ds (),
20512 .qs (dio_pad_attr_1_invert_1_qs)
20513 );
20514 1/1 assign reg2hw.dio_pad_attr[1].invert.qe = dio_pad_attr_1_qe;
Tests: T1 T2 T3
20515
20516 // F[virtual_od_en_1]: 1:1
20517 prim_subreg_ext #(
20518 .DW (1)
20519 ) u_dio_pad_attr_1_virtual_od_en_1 (
20520 .re (dio_pad_attr_1_re),
20521 .we (dio_pad_attr_1_gated_we),
20522 .wd (dio_pad_attr_1_virtual_od_en_1_wd),
20523 .d (hw2reg.dio_pad_attr[1].virtual_od_en.d),
20524 .qre (),
20525 .qe (dio_pad_attr_1_flds_we[1]),
20526 .q (reg2hw.dio_pad_attr[1].virtual_od_en.q),
20527 .ds (),
20528 .qs (dio_pad_attr_1_virtual_od_en_1_qs)
20529 );
20530 1/1 assign reg2hw.dio_pad_attr[1].virtual_od_en.qe = dio_pad_attr_1_qe;
Tests: T1 T2 T3
20531
20532 // F[pull_en_1]: 2:2
20533 prim_subreg_ext #(
20534 .DW (1)
20535 ) u_dio_pad_attr_1_pull_en_1 (
20536 .re (dio_pad_attr_1_re),
20537 .we (dio_pad_attr_1_gated_we),
20538 .wd (dio_pad_attr_1_pull_en_1_wd),
20539 .d (hw2reg.dio_pad_attr[1].pull_en.d),
20540 .qre (),
20541 .qe (dio_pad_attr_1_flds_we[2]),
20542 .q (reg2hw.dio_pad_attr[1].pull_en.q),
20543 .ds (),
20544 .qs (dio_pad_attr_1_pull_en_1_qs)
20545 );
20546 1/1 assign reg2hw.dio_pad_attr[1].pull_en.qe = dio_pad_attr_1_qe;
Tests: T1 T2 T3
20547
20548 // F[pull_select_1]: 3:3
20549 prim_subreg_ext #(
20550 .DW (1)
20551 ) u_dio_pad_attr_1_pull_select_1 (
20552 .re (dio_pad_attr_1_re),
20553 .we (dio_pad_attr_1_gated_we),
20554 .wd (dio_pad_attr_1_pull_select_1_wd),
20555 .d (hw2reg.dio_pad_attr[1].pull_select.d),
20556 .qre (),
20557 .qe (dio_pad_attr_1_flds_we[3]),
20558 .q (reg2hw.dio_pad_attr[1].pull_select.q),
20559 .ds (),
20560 .qs (dio_pad_attr_1_pull_select_1_qs)
20561 );
20562 1/1 assign reg2hw.dio_pad_attr[1].pull_select.qe = dio_pad_attr_1_qe;
Tests: T1 T2 T3
20563
20564 // F[keeper_en_1]: 4:4
20565 prim_subreg_ext #(
20566 .DW (1)
20567 ) u_dio_pad_attr_1_keeper_en_1 (
20568 .re (dio_pad_attr_1_re),
20569 .we (dio_pad_attr_1_gated_we),
20570 .wd (dio_pad_attr_1_keeper_en_1_wd),
20571 .d (hw2reg.dio_pad_attr[1].keeper_en.d),
20572 .qre (),
20573 .qe (dio_pad_attr_1_flds_we[4]),
20574 .q (reg2hw.dio_pad_attr[1].keeper_en.q),
20575 .ds (),
20576 .qs (dio_pad_attr_1_keeper_en_1_qs)
20577 );
20578 1/1 assign reg2hw.dio_pad_attr[1].keeper_en.qe = dio_pad_attr_1_qe;
Tests: T1 T2 T3
20579
20580 // F[schmitt_en_1]: 5:5
20581 prim_subreg_ext #(
20582 .DW (1)
20583 ) u_dio_pad_attr_1_schmitt_en_1 (
20584 .re (dio_pad_attr_1_re),
20585 .we (dio_pad_attr_1_gated_we),
20586 .wd (dio_pad_attr_1_schmitt_en_1_wd),
20587 .d (hw2reg.dio_pad_attr[1].schmitt_en.d),
20588 .qre (),
20589 .qe (dio_pad_attr_1_flds_we[5]),
20590 .q (reg2hw.dio_pad_attr[1].schmitt_en.q),
20591 .ds (),
20592 .qs (dio_pad_attr_1_schmitt_en_1_qs)
20593 );
20594 1/1 assign reg2hw.dio_pad_attr[1].schmitt_en.qe = dio_pad_attr_1_qe;
Tests: T1 T2 T3
20595
20596 // F[od_en_1]: 6:6
20597 prim_subreg_ext #(
20598 .DW (1)
20599 ) u_dio_pad_attr_1_od_en_1 (
20600 .re (dio_pad_attr_1_re),
20601 .we (dio_pad_attr_1_gated_we),
20602 .wd (dio_pad_attr_1_od_en_1_wd),
20603 .d (hw2reg.dio_pad_attr[1].od_en.d),
20604 .qre (),
20605 .qe (dio_pad_attr_1_flds_we[6]),
20606 .q (reg2hw.dio_pad_attr[1].od_en.q),
20607 .ds (),
20608 .qs (dio_pad_attr_1_od_en_1_qs)
20609 );
20610 1/1 assign reg2hw.dio_pad_attr[1].od_en.qe = dio_pad_attr_1_qe;
Tests: T1 T2 T3
20611
20612 // F[input_disable_1]: 7:7
20613 prim_subreg_ext #(
20614 .DW (1)
20615 ) u_dio_pad_attr_1_input_disable_1 (
20616 .re (dio_pad_attr_1_re),
20617 .we (dio_pad_attr_1_gated_we),
20618 .wd (dio_pad_attr_1_input_disable_1_wd),
20619 .d (hw2reg.dio_pad_attr[1].input_disable.d),
20620 .qre (),
20621 .qe (dio_pad_attr_1_flds_we[7]),
20622 .q (reg2hw.dio_pad_attr[1].input_disable.q),
20623 .ds (),
20624 .qs (dio_pad_attr_1_input_disable_1_qs)
20625 );
20626 1/1 assign reg2hw.dio_pad_attr[1].input_disable.qe = dio_pad_attr_1_qe;
Tests: T1 T2 T3
20627
20628 // F[slew_rate_1]: 17:16
20629 prim_subreg_ext #(
20630 .DW (2)
20631 ) u_dio_pad_attr_1_slew_rate_1 (
20632 .re (dio_pad_attr_1_re),
20633 .we (dio_pad_attr_1_gated_we),
20634 .wd (dio_pad_attr_1_slew_rate_1_wd),
20635 .d (hw2reg.dio_pad_attr[1].slew_rate.d),
20636 .qre (),
20637 .qe (dio_pad_attr_1_flds_we[8]),
20638 .q (reg2hw.dio_pad_attr[1].slew_rate.q),
20639 .ds (),
20640 .qs (dio_pad_attr_1_slew_rate_1_qs)
20641 );
20642 1/1 assign reg2hw.dio_pad_attr[1].slew_rate.qe = dio_pad_attr_1_qe;
Tests: T1 T2 T3
20643
20644 // F[drive_strength_1]: 23:20
20645 prim_subreg_ext #(
20646 .DW (4)
20647 ) u_dio_pad_attr_1_drive_strength_1 (
20648 .re (dio_pad_attr_1_re),
20649 .we (dio_pad_attr_1_gated_we),
20650 .wd (dio_pad_attr_1_drive_strength_1_wd),
20651 .d (hw2reg.dio_pad_attr[1].drive_strength.d),
20652 .qre (),
20653 .qe (dio_pad_attr_1_flds_we[9]),
20654 .q (reg2hw.dio_pad_attr[1].drive_strength.q),
20655 .ds (),
20656 .qs (dio_pad_attr_1_drive_strength_1_qs)
20657 );
20658 1/1 assign reg2hw.dio_pad_attr[1].drive_strength.qe = dio_pad_attr_1_qe;
Tests: T1 T2 T3
20659
20660
20661 // Subregister 2 of Multireg dio_pad_attr
20662 // R[dio_pad_attr_2]: V(True)
20663 logic dio_pad_attr_2_qe;
20664 logic [9:0] dio_pad_attr_2_flds_we;
20665 1/1 assign dio_pad_attr_2_qe = &dio_pad_attr_2_flds_we;
Tests: T9 T10 T11
20666 // Create REGWEN-gated WE signal
20667 logic dio_pad_attr_2_gated_we;
20668 1/1 assign dio_pad_attr_2_gated_we = dio_pad_attr_2_we & dio_pad_attr_regwen_2_qs;
Tests: T9 T10 T11
20669 // F[invert_2]: 0:0
20670 prim_subreg_ext #(
20671 .DW (1)
20672 ) u_dio_pad_attr_2_invert_2 (
20673 .re (dio_pad_attr_2_re),
20674 .we (dio_pad_attr_2_gated_we),
20675 .wd (dio_pad_attr_2_invert_2_wd),
20676 .d (hw2reg.dio_pad_attr[2].invert.d),
20677 .qre (),
20678 .qe (dio_pad_attr_2_flds_we[0]),
20679 .q (reg2hw.dio_pad_attr[2].invert.q),
20680 .ds (),
20681 .qs (dio_pad_attr_2_invert_2_qs)
20682 );
20683 1/1 assign reg2hw.dio_pad_attr[2].invert.qe = dio_pad_attr_2_qe;
Tests: T9 T10 T11
20684
20685 // F[virtual_od_en_2]: 1:1
20686 prim_subreg_ext #(
20687 .DW (1)
20688 ) u_dio_pad_attr_2_virtual_od_en_2 (
20689 .re (dio_pad_attr_2_re),
20690 .we (dio_pad_attr_2_gated_we),
20691 .wd (dio_pad_attr_2_virtual_od_en_2_wd),
20692 .d (hw2reg.dio_pad_attr[2].virtual_od_en.d),
20693 .qre (),
20694 .qe (dio_pad_attr_2_flds_we[1]),
20695 .q (reg2hw.dio_pad_attr[2].virtual_od_en.q),
20696 .ds (),
20697 .qs (dio_pad_attr_2_virtual_od_en_2_qs)
20698 );
20699 1/1 assign reg2hw.dio_pad_attr[2].virtual_od_en.qe = dio_pad_attr_2_qe;
Tests: T9 T10 T11
20700
20701 // F[pull_en_2]: 2:2
20702 prim_subreg_ext #(
20703 .DW (1)
20704 ) u_dio_pad_attr_2_pull_en_2 (
20705 .re (dio_pad_attr_2_re),
20706 .we (dio_pad_attr_2_gated_we),
20707 .wd (dio_pad_attr_2_pull_en_2_wd),
20708 .d (hw2reg.dio_pad_attr[2].pull_en.d),
20709 .qre (),
20710 .qe (dio_pad_attr_2_flds_we[2]),
20711 .q (reg2hw.dio_pad_attr[2].pull_en.q),
20712 .ds (),
20713 .qs (dio_pad_attr_2_pull_en_2_qs)
20714 );
20715 1/1 assign reg2hw.dio_pad_attr[2].pull_en.qe = dio_pad_attr_2_qe;
Tests: T9 T10 T11
20716
20717 // F[pull_select_2]: 3:3
20718 prim_subreg_ext #(
20719 .DW (1)
20720 ) u_dio_pad_attr_2_pull_select_2 (
20721 .re (dio_pad_attr_2_re),
20722 .we (dio_pad_attr_2_gated_we),
20723 .wd (dio_pad_attr_2_pull_select_2_wd),
20724 .d (hw2reg.dio_pad_attr[2].pull_select.d),
20725 .qre (),
20726 .qe (dio_pad_attr_2_flds_we[3]),
20727 .q (reg2hw.dio_pad_attr[2].pull_select.q),
20728 .ds (),
20729 .qs (dio_pad_attr_2_pull_select_2_qs)
20730 );
20731 1/1 assign reg2hw.dio_pad_attr[2].pull_select.qe = dio_pad_attr_2_qe;
Tests: T9 T10 T11
20732
20733 // F[keeper_en_2]: 4:4
20734 prim_subreg_ext #(
20735 .DW (1)
20736 ) u_dio_pad_attr_2_keeper_en_2 (
20737 .re (dio_pad_attr_2_re),
20738 .we (dio_pad_attr_2_gated_we),
20739 .wd (dio_pad_attr_2_keeper_en_2_wd),
20740 .d (hw2reg.dio_pad_attr[2].keeper_en.d),
20741 .qre (),
20742 .qe (dio_pad_attr_2_flds_we[4]),
20743 .q (reg2hw.dio_pad_attr[2].keeper_en.q),
20744 .ds (),
20745 .qs (dio_pad_attr_2_keeper_en_2_qs)
20746 );
20747 1/1 assign reg2hw.dio_pad_attr[2].keeper_en.qe = dio_pad_attr_2_qe;
Tests: T9 T10 T11
20748
20749 // F[schmitt_en_2]: 5:5
20750 prim_subreg_ext #(
20751 .DW (1)
20752 ) u_dio_pad_attr_2_schmitt_en_2 (
20753 .re (dio_pad_attr_2_re),
20754 .we (dio_pad_attr_2_gated_we),
20755 .wd (dio_pad_attr_2_schmitt_en_2_wd),
20756 .d (hw2reg.dio_pad_attr[2].schmitt_en.d),
20757 .qre (),
20758 .qe (dio_pad_attr_2_flds_we[5]),
20759 .q (reg2hw.dio_pad_attr[2].schmitt_en.q),
20760 .ds (),
20761 .qs (dio_pad_attr_2_schmitt_en_2_qs)
20762 );
20763 1/1 assign reg2hw.dio_pad_attr[2].schmitt_en.qe = dio_pad_attr_2_qe;
Tests: T9 T10 T11
20764
20765 // F[od_en_2]: 6:6
20766 prim_subreg_ext #(
20767 .DW (1)
20768 ) u_dio_pad_attr_2_od_en_2 (
20769 .re (dio_pad_attr_2_re),
20770 .we (dio_pad_attr_2_gated_we),
20771 .wd (dio_pad_attr_2_od_en_2_wd),
20772 .d (hw2reg.dio_pad_attr[2].od_en.d),
20773 .qre (),
20774 .qe (dio_pad_attr_2_flds_we[6]),
20775 .q (reg2hw.dio_pad_attr[2].od_en.q),
20776 .ds (),
20777 .qs (dio_pad_attr_2_od_en_2_qs)
20778 );
20779 1/1 assign reg2hw.dio_pad_attr[2].od_en.qe = dio_pad_attr_2_qe;
Tests: T9 T10 T11
20780
20781 // F[input_disable_2]: 7:7
20782 prim_subreg_ext #(
20783 .DW (1)
20784 ) u_dio_pad_attr_2_input_disable_2 (
20785 .re (dio_pad_attr_2_re),
20786 .we (dio_pad_attr_2_gated_we),
20787 .wd (dio_pad_attr_2_input_disable_2_wd),
20788 .d (hw2reg.dio_pad_attr[2].input_disable.d),
20789 .qre (),
20790 .qe (dio_pad_attr_2_flds_we[7]),
20791 .q (reg2hw.dio_pad_attr[2].input_disable.q),
20792 .ds (),
20793 .qs (dio_pad_attr_2_input_disable_2_qs)
20794 );
20795 1/1 assign reg2hw.dio_pad_attr[2].input_disable.qe = dio_pad_attr_2_qe;
Tests: T9 T10 T11
20796
20797 // F[slew_rate_2]: 17:16
20798 prim_subreg_ext #(
20799 .DW (2)
20800 ) u_dio_pad_attr_2_slew_rate_2 (
20801 .re (dio_pad_attr_2_re),
20802 .we (dio_pad_attr_2_gated_we),
20803 .wd (dio_pad_attr_2_slew_rate_2_wd),
20804 .d (hw2reg.dio_pad_attr[2].slew_rate.d),
20805 .qre (),
20806 .qe (dio_pad_attr_2_flds_we[8]),
20807 .q (reg2hw.dio_pad_attr[2].slew_rate.q),
20808 .ds (),
20809 .qs (dio_pad_attr_2_slew_rate_2_qs)
20810 );
20811 1/1 assign reg2hw.dio_pad_attr[2].slew_rate.qe = dio_pad_attr_2_qe;
Tests: T9 T10 T11
20812
20813 // F[drive_strength_2]: 23:20
20814 prim_subreg_ext #(
20815 .DW (4)
20816 ) u_dio_pad_attr_2_drive_strength_2 (
20817 .re (dio_pad_attr_2_re),
20818 .we (dio_pad_attr_2_gated_we),
20819 .wd (dio_pad_attr_2_drive_strength_2_wd),
20820 .d (hw2reg.dio_pad_attr[2].drive_strength.d),
20821 .qre (),
20822 .qe (dio_pad_attr_2_flds_we[9]),
20823 .q (reg2hw.dio_pad_attr[2].drive_strength.q),
20824 .ds (),
20825 .qs (dio_pad_attr_2_drive_strength_2_qs)
20826 );
20827 1/1 assign reg2hw.dio_pad_attr[2].drive_strength.qe = dio_pad_attr_2_qe;
Tests: T9 T10 T11
20828
20829
20830 // Subregister 3 of Multireg dio_pad_attr
20831 // R[dio_pad_attr_3]: V(True)
20832 logic dio_pad_attr_3_qe;
20833 logic [9:0] dio_pad_attr_3_flds_we;
20834 1/1 assign dio_pad_attr_3_qe = &dio_pad_attr_3_flds_we;
Tests: T9 T10 T11
20835 // Create REGWEN-gated WE signal
20836 logic dio_pad_attr_3_gated_we;
20837 1/1 assign dio_pad_attr_3_gated_we = dio_pad_attr_3_we & dio_pad_attr_regwen_3_qs;
Tests: T9 T10 T11
20838 // F[invert_3]: 0:0
20839 prim_subreg_ext #(
20840 .DW (1)
20841 ) u_dio_pad_attr_3_invert_3 (
20842 .re (dio_pad_attr_3_re),
20843 .we (dio_pad_attr_3_gated_we),
20844 .wd (dio_pad_attr_3_invert_3_wd),
20845 .d (hw2reg.dio_pad_attr[3].invert.d),
20846 .qre (),
20847 .qe (dio_pad_attr_3_flds_we[0]),
20848 .q (reg2hw.dio_pad_attr[3].invert.q),
20849 .ds (),
20850 .qs (dio_pad_attr_3_invert_3_qs)
20851 );
20852 1/1 assign reg2hw.dio_pad_attr[3].invert.qe = dio_pad_attr_3_qe;
Tests: T9 T10 T11
20853
20854 // F[virtual_od_en_3]: 1:1
20855 prim_subreg_ext #(
20856 .DW (1)
20857 ) u_dio_pad_attr_3_virtual_od_en_3 (
20858 .re (dio_pad_attr_3_re),
20859 .we (dio_pad_attr_3_gated_we),
20860 .wd (dio_pad_attr_3_virtual_od_en_3_wd),
20861 .d (hw2reg.dio_pad_attr[3].virtual_od_en.d),
20862 .qre (),
20863 .qe (dio_pad_attr_3_flds_we[1]),
20864 .q (reg2hw.dio_pad_attr[3].virtual_od_en.q),
20865 .ds (),
20866 .qs (dio_pad_attr_3_virtual_od_en_3_qs)
20867 );
20868 1/1 assign reg2hw.dio_pad_attr[3].virtual_od_en.qe = dio_pad_attr_3_qe;
Tests: T9 T10 T11
20869
20870 // F[pull_en_3]: 2:2
20871 prim_subreg_ext #(
20872 .DW (1)
20873 ) u_dio_pad_attr_3_pull_en_3 (
20874 .re (dio_pad_attr_3_re),
20875 .we (dio_pad_attr_3_gated_we),
20876 .wd (dio_pad_attr_3_pull_en_3_wd),
20877 .d (hw2reg.dio_pad_attr[3].pull_en.d),
20878 .qre (),
20879 .qe (dio_pad_attr_3_flds_we[2]),
20880 .q (reg2hw.dio_pad_attr[3].pull_en.q),
20881 .ds (),
20882 .qs (dio_pad_attr_3_pull_en_3_qs)
20883 );
20884 1/1 assign reg2hw.dio_pad_attr[3].pull_en.qe = dio_pad_attr_3_qe;
Tests: T9 T10 T11
20885
20886 // F[pull_select_3]: 3:3
20887 prim_subreg_ext #(
20888 .DW (1)
20889 ) u_dio_pad_attr_3_pull_select_3 (
20890 .re (dio_pad_attr_3_re),
20891 .we (dio_pad_attr_3_gated_we),
20892 .wd (dio_pad_attr_3_pull_select_3_wd),
20893 .d (hw2reg.dio_pad_attr[3].pull_select.d),
20894 .qre (),
20895 .qe (dio_pad_attr_3_flds_we[3]),
20896 .q (reg2hw.dio_pad_attr[3].pull_select.q),
20897 .ds (),
20898 .qs (dio_pad_attr_3_pull_select_3_qs)
20899 );
20900 1/1 assign reg2hw.dio_pad_attr[3].pull_select.qe = dio_pad_attr_3_qe;
Tests: T9 T10 T11
20901
20902 // F[keeper_en_3]: 4:4
20903 prim_subreg_ext #(
20904 .DW (1)
20905 ) u_dio_pad_attr_3_keeper_en_3 (
20906 .re (dio_pad_attr_3_re),
20907 .we (dio_pad_attr_3_gated_we),
20908 .wd (dio_pad_attr_3_keeper_en_3_wd),
20909 .d (hw2reg.dio_pad_attr[3].keeper_en.d),
20910 .qre (),
20911 .qe (dio_pad_attr_3_flds_we[4]),
20912 .q (reg2hw.dio_pad_attr[3].keeper_en.q),
20913 .ds (),
20914 .qs (dio_pad_attr_3_keeper_en_3_qs)
20915 );
20916 1/1 assign reg2hw.dio_pad_attr[3].keeper_en.qe = dio_pad_attr_3_qe;
Tests: T9 T10 T11
20917
20918 // F[schmitt_en_3]: 5:5
20919 prim_subreg_ext #(
20920 .DW (1)
20921 ) u_dio_pad_attr_3_schmitt_en_3 (
20922 .re (dio_pad_attr_3_re),
20923 .we (dio_pad_attr_3_gated_we),
20924 .wd (dio_pad_attr_3_schmitt_en_3_wd),
20925 .d (hw2reg.dio_pad_attr[3].schmitt_en.d),
20926 .qre (),
20927 .qe (dio_pad_attr_3_flds_we[5]),
20928 .q (reg2hw.dio_pad_attr[3].schmitt_en.q),
20929 .ds (),
20930 .qs (dio_pad_attr_3_schmitt_en_3_qs)
20931 );
20932 1/1 assign reg2hw.dio_pad_attr[3].schmitt_en.qe = dio_pad_attr_3_qe;
Tests: T9 T10 T11
20933
20934 // F[od_en_3]: 6:6
20935 prim_subreg_ext #(
20936 .DW (1)
20937 ) u_dio_pad_attr_3_od_en_3 (
20938 .re (dio_pad_attr_3_re),
20939 .we (dio_pad_attr_3_gated_we),
20940 .wd (dio_pad_attr_3_od_en_3_wd),
20941 .d (hw2reg.dio_pad_attr[3].od_en.d),
20942 .qre (),
20943 .qe (dio_pad_attr_3_flds_we[6]),
20944 .q (reg2hw.dio_pad_attr[3].od_en.q),
20945 .ds (),
20946 .qs (dio_pad_attr_3_od_en_3_qs)
20947 );
20948 1/1 assign reg2hw.dio_pad_attr[3].od_en.qe = dio_pad_attr_3_qe;
Tests: T9 T10 T11
20949
20950 // F[input_disable_3]: 7:7
20951 prim_subreg_ext #(
20952 .DW (1)
20953 ) u_dio_pad_attr_3_input_disable_3 (
20954 .re (dio_pad_attr_3_re),
20955 .we (dio_pad_attr_3_gated_we),
20956 .wd (dio_pad_attr_3_input_disable_3_wd),
20957 .d (hw2reg.dio_pad_attr[3].input_disable.d),
20958 .qre (),
20959 .qe (dio_pad_attr_3_flds_we[7]),
20960 .q (reg2hw.dio_pad_attr[3].input_disable.q),
20961 .ds (),
20962 .qs (dio_pad_attr_3_input_disable_3_qs)
20963 );
20964 1/1 assign reg2hw.dio_pad_attr[3].input_disable.qe = dio_pad_attr_3_qe;
Tests: T9 T10 T11
20965
20966 // F[slew_rate_3]: 17:16
20967 prim_subreg_ext #(
20968 .DW (2)
20969 ) u_dio_pad_attr_3_slew_rate_3 (
20970 .re (dio_pad_attr_3_re),
20971 .we (dio_pad_attr_3_gated_we),
20972 .wd (dio_pad_attr_3_slew_rate_3_wd),
20973 .d (hw2reg.dio_pad_attr[3].slew_rate.d),
20974 .qre (),
20975 .qe (dio_pad_attr_3_flds_we[8]),
20976 .q (reg2hw.dio_pad_attr[3].slew_rate.q),
20977 .ds (),
20978 .qs (dio_pad_attr_3_slew_rate_3_qs)
20979 );
20980 1/1 assign reg2hw.dio_pad_attr[3].slew_rate.qe = dio_pad_attr_3_qe;
Tests: T9 T10 T11
20981
20982 // F[drive_strength_3]: 23:20
20983 prim_subreg_ext #(
20984 .DW (4)
20985 ) u_dio_pad_attr_3_drive_strength_3 (
20986 .re (dio_pad_attr_3_re),
20987 .we (dio_pad_attr_3_gated_we),
20988 .wd (dio_pad_attr_3_drive_strength_3_wd),
20989 .d (hw2reg.dio_pad_attr[3].drive_strength.d),
20990 .qre (),
20991 .qe (dio_pad_attr_3_flds_we[9]),
20992 .q (reg2hw.dio_pad_attr[3].drive_strength.q),
20993 .ds (),
20994 .qs (dio_pad_attr_3_drive_strength_3_qs)
20995 );
20996 1/1 assign reg2hw.dio_pad_attr[3].drive_strength.qe = dio_pad_attr_3_qe;
Tests: T9 T10 T11
20997
20998
20999 // Subregister 4 of Multireg dio_pad_attr
21000 // R[dio_pad_attr_4]: V(True)
21001 logic dio_pad_attr_4_qe;
21002 logic [9:0] dio_pad_attr_4_flds_we;
21003 1/1 assign dio_pad_attr_4_qe = &dio_pad_attr_4_flds_we;
Tests: T9 T10 T11
21004 // Create REGWEN-gated WE signal
21005 logic dio_pad_attr_4_gated_we;
21006 1/1 assign dio_pad_attr_4_gated_we = dio_pad_attr_4_we & dio_pad_attr_regwen_4_qs;
Tests: T9 T10 T11
21007 // F[invert_4]: 0:0
21008 prim_subreg_ext #(
21009 .DW (1)
21010 ) u_dio_pad_attr_4_invert_4 (
21011 .re (dio_pad_attr_4_re),
21012 .we (dio_pad_attr_4_gated_we),
21013 .wd (dio_pad_attr_4_invert_4_wd),
21014 .d (hw2reg.dio_pad_attr[4].invert.d),
21015 .qre (),
21016 .qe (dio_pad_attr_4_flds_we[0]),
21017 .q (reg2hw.dio_pad_attr[4].invert.q),
21018 .ds (),
21019 .qs (dio_pad_attr_4_invert_4_qs)
21020 );
21021 1/1 assign reg2hw.dio_pad_attr[4].invert.qe = dio_pad_attr_4_qe;
Tests: T9 T10 T11
21022
21023 // F[virtual_od_en_4]: 1:1
21024 prim_subreg_ext #(
21025 .DW (1)
21026 ) u_dio_pad_attr_4_virtual_od_en_4 (
21027 .re (dio_pad_attr_4_re),
21028 .we (dio_pad_attr_4_gated_we),
21029 .wd (dio_pad_attr_4_virtual_od_en_4_wd),
21030 .d (hw2reg.dio_pad_attr[4].virtual_od_en.d),
21031 .qre (),
21032 .qe (dio_pad_attr_4_flds_we[1]),
21033 .q (reg2hw.dio_pad_attr[4].virtual_od_en.q),
21034 .ds (),
21035 .qs (dio_pad_attr_4_virtual_od_en_4_qs)
21036 );
21037 1/1 assign reg2hw.dio_pad_attr[4].virtual_od_en.qe = dio_pad_attr_4_qe;
Tests: T9 T10 T11
21038
21039 // F[pull_en_4]: 2:2
21040 prim_subreg_ext #(
21041 .DW (1)
21042 ) u_dio_pad_attr_4_pull_en_4 (
21043 .re (dio_pad_attr_4_re),
21044 .we (dio_pad_attr_4_gated_we),
21045 .wd (dio_pad_attr_4_pull_en_4_wd),
21046 .d (hw2reg.dio_pad_attr[4].pull_en.d),
21047 .qre (),
21048 .qe (dio_pad_attr_4_flds_we[2]),
21049 .q (reg2hw.dio_pad_attr[4].pull_en.q),
21050 .ds (),
21051 .qs (dio_pad_attr_4_pull_en_4_qs)
21052 );
21053 1/1 assign reg2hw.dio_pad_attr[4].pull_en.qe = dio_pad_attr_4_qe;
Tests: T9 T10 T11
21054
21055 // F[pull_select_4]: 3:3
21056 prim_subreg_ext #(
21057 .DW (1)
21058 ) u_dio_pad_attr_4_pull_select_4 (
21059 .re (dio_pad_attr_4_re),
21060 .we (dio_pad_attr_4_gated_we),
21061 .wd (dio_pad_attr_4_pull_select_4_wd),
21062 .d (hw2reg.dio_pad_attr[4].pull_select.d),
21063 .qre (),
21064 .qe (dio_pad_attr_4_flds_we[3]),
21065 .q (reg2hw.dio_pad_attr[4].pull_select.q),
21066 .ds (),
21067 .qs (dio_pad_attr_4_pull_select_4_qs)
21068 );
21069 1/1 assign reg2hw.dio_pad_attr[4].pull_select.qe = dio_pad_attr_4_qe;
Tests: T9 T10 T11
21070
21071 // F[keeper_en_4]: 4:4
21072 prim_subreg_ext #(
21073 .DW (1)
21074 ) u_dio_pad_attr_4_keeper_en_4 (
21075 .re (dio_pad_attr_4_re),
21076 .we (dio_pad_attr_4_gated_we),
21077 .wd (dio_pad_attr_4_keeper_en_4_wd),
21078 .d (hw2reg.dio_pad_attr[4].keeper_en.d),
21079 .qre (),
21080 .qe (dio_pad_attr_4_flds_we[4]),
21081 .q (reg2hw.dio_pad_attr[4].keeper_en.q),
21082 .ds (),
21083 .qs (dio_pad_attr_4_keeper_en_4_qs)
21084 );
21085 1/1 assign reg2hw.dio_pad_attr[4].keeper_en.qe = dio_pad_attr_4_qe;
Tests: T9 T10 T11
21086
21087 // F[schmitt_en_4]: 5:5
21088 prim_subreg_ext #(
21089 .DW (1)
21090 ) u_dio_pad_attr_4_schmitt_en_4 (
21091 .re (dio_pad_attr_4_re),
21092 .we (dio_pad_attr_4_gated_we),
21093 .wd (dio_pad_attr_4_schmitt_en_4_wd),
21094 .d (hw2reg.dio_pad_attr[4].schmitt_en.d),
21095 .qre (),
21096 .qe (dio_pad_attr_4_flds_we[5]),
21097 .q (reg2hw.dio_pad_attr[4].schmitt_en.q),
21098 .ds (),
21099 .qs (dio_pad_attr_4_schmitt_en_4_qs)
21100 );
21101 1/1 assign reg2hw.dio_pad_attr[4].schmitt_en.qe = dio_pad_attr_4_qe;
Tests: T9 T10 T11
21102
21103 // F[od_en_4]: 6:6
21104 prim_subreg_ext #(
21105 .DW (1)
21106 ) u_dio_pad_attr_4_od_en_4 (
21107 .re (dio_pad_attr_4_re),
21108 .we (dio_pad_attr_4_gated_we),
21109 .wd (dio_pad_attr_4_od_en_4_wd),
21110 .d (hw2reg.dio_pad_attr[4].od_en.d),
21111 .qre (),
21112 .qe (dio_pad_attr_4_flds_we[6]),
21113 .q (reg2hw.dio_pad_attr[4].od_en.q),
21114 .ds (),
21115 .qs (dio_pad_attr_4_od_en_4_qs)
21116 );
21117 1/1 assign reg2hw.dio_pad_attr[4].od_en.qe = dio_pad_attr_4_qe;
Tests: T9 T10 T11
21118
21119 // F[input_disable_4]: 7:7
21120 prim_subreg_ext #(
21121 .DW (1)
21122 ) u_dio_pad_attr_4_input_disable_4 (
21123 .re (dio_pad_attr_4_re),
21124 .we (dio_pad_attr_4_gated_we),
21125 .wd (dio_pad_attr_4_input_disable_4_wd),
21126 .d (hw2reg.dio_pad_attr[4].input_disable.d),
21127 .qre (),
21128 .qe (dio_pad_attr_4_flds_we[7]),
21129 .q (reg2hw.dio_pad_attr[4].input_disable.q),
21130 .ds (),
21131 .qs (dio_pad_attr_4_input_disable_4_qs)
21132 );
21133 1/1 assign reg2hw.dio_pad_attr[4].input_disable.qe = dio_pad_attr_4_qe;
Tests: T9 T10 T11
21134
21135 // F[slew_rate_4]: 17:16
21136 prim_subreg_ext #(
21137 .DW (2)
21138 ) u_dio_pad_attr_4_slew_rate_4 (
21139 .re (dio_pad_attr_4_re),
21140 .we (dio_pad_attr_4_gated_we),
21141 .wd (dio_pad_attr_4_slew_rate_4_wd),
21142 .d (hw2reg.dio_pad_attr[4].slew_rate.d),
21143 .qre (),
21144 .qe (dio_pad_attr_4_flds_we[8]),
21145 .q (reg2hw.dio_pad_attr[4].slew_rate.q),
21146 .ds (),
21147 .qs (dio_pad_attr_4_slew_rate_4_qs)
21148 );
21149 1/1 assign reg2hw.dio_pad_attr[4].slew_rate.qe = dio_pad_attr_4_qe;
Tests: T9 T10 T11
21150
21151 // F[drive_strength_4]: 23:20
21152 prim_subreg_ext #(
21153 .DW (4)
21154 ) u_dio_pad_attr_4_drive_strength_4 (
21155 .re (dio_pad_attr_4_re),
21156 .we (dio_pad_attr_4_gated_we),
21157 .wd (dio_pad_attr_4_drive_strength_4_wd),
21158 .d (hw2reg.dio_pad_attr[4].drive_strength.d),
21159 .qre (),
21160 .qe (dio_pad_attr_4_flds_we[9]),
21161 .q (reg2hw.dio_pad_attr[4].drive_strength.q),
21162 .ds (),
21163 .qs (dio_pad_attr_4_drive_strength_4_qs)
21164 );
21165 1/1 assign reg2hw.dio_pad_attr[4].drive_strength.qe = dio_pad_attr_4_qe;
Tests: T9 T10 T11
21166
21167
21168 // Subregister 5 of Multireg dio_pad_attr
21169 // R[dio_pad_attr_5]: V(True)
21170 logic dio_pad_attr_5_qe;
21171 logic [9:0] dio_pad_attr_5_flds_we;
21172 1/1 assign dio_pad_attr_5_qe = &dio_pad_attr_5_flds_we;
Tests: T9 T10 T11
21173 // Create REGWEN-gated WE signal
21174 logic dio_pad_attr_5_gated_we;
21175 1/1 assign dio_pad_attr_5_gated_we = dio_pad_attr_5_we & dio_pad_attr_regwen_5_qs;
Tests: T9 T10 T11
21176 // F[invert_5]: 0:0
21177 prim_subreg_ext #(
21178 .DW (1)
21179 ) u_dio_pad_attr_5_invert_5 (
21180 .re (dio_pad_attr_5_re),
21181 .we (dio_pad_attr_5_gated_we),
21182 .wd (dio_pad_attr_5_invert_5_wd),
21183 .d (hw2reg.dio_pad_attr[5].invert.d),
21184 .qre (),
21185 .qe (dio_pad_attr_5_flds_we[0]),
21186 .q (reg2hw.dio_pad_attr[5].invert.q),
21187 .ds (),
21188 .qs (dio_pad_attr_5_invert_5_qs)
21189 );
21190 1/1 assign reg2hw.dio_pad_attr[5].invert.qe = dio_pad_attr_5_qe;
Tests: T9 T10 T11
21191
21192 // F[virtual_od_en_5]: 1:1
21193 prim_subreg_ext #(
21194 .DW (1)
21195 ) u_dio_pad_attr_5_virtual_od_en_5 (
21196 .re (dio_pad_attr_5_re),
21197 .we (dio_pad_attr_5_gated_we),
21198 .wd (dio_pad_attr_5_virtual_od_en_5_wd),
21199 .d (hw2reg.dio_pad_attr[5].virtual_od_en.d),
21200 .qre (),
21201 .qe (dio_pad_attr_5_flds_we[1]),
21202 .q (reg2hw.dio_pad_attr[5].virtual_od_en.q),
21203 .ds (),
21204 .qs (dio_pad_attr_5_virtual_od_en_5_qs)
21205 );
21206 1/1 assign reg2hw.dio_pad_attr[5].virtual_od_en.qe = dio_pad_attr_5_qe;
Tests: T9 T10 T11
21207
21208 // F[pull_en_5]: 2:2
21209 prim_subreg_ext #(
21210 .DW (1)
21211 ) u_dio_pad_attr_5_pull_en_5 (
21212 .re (dio_pad_attr_5_re),
21213 .we (dio_pad_attr_5_gated_we),
21214 .wd (dio_pad_attr_5_pull_en_5_wd),
21215 .d (hw2reg.dio_pad_attr[5].pull_en.d),
21216 .qre (),
21217 .qe (dio_pad_attr_5_flds_we[2]),
21218 .q (reg2hw.dio_pad_attr[5].pull_en.q),
21219 .ds (),
21220 .qs (dio_pad_attr_5_pull_en_5_qs)
21221 );
21222 1/1 assign reg2hw.dio_pad_attr[5].pull_en.qe = dio_pad_attr_5_qe;
Tests: T9 T10 T11
21223
21224 // F[pull_select_5]: 3:3
21225 prim_subreg_ext #(
21226 .DW (1)
21227 ) u_dio_pad_attr_5_pull_select_5 (
21228 .re (dio_pad_attr_5_re),
21229 .we (dio_pad_attr_5_gated_we),
21230 .wd (dio_pad_attr_5_pull_select_5_wd),
21231 .d (hw2reg.dio_pad_attr[5].pull_select.d),
21232 .qre (),
21233 .qe (dio_pad_attr_5_flds_we[3]),
21234 .q (reg2hw.dio_pad_attr[5].pull_select.q),
21235 .ds (),
21236 .qs (dio_pad_attr_5_pull_select_5_qs)
21237 );
21238 1/1 assign reg2hw.dio_pad_attr[5].pull_select.qe = dio_pad_attr_5_qe;
Tests: T9 T10 T11
21239
21240 // F[keeper_en_5]: 4:4
21241 prim_subreg_ext #(
21242 .DW (1)
21243 ) u_dio_pad_attr_5_keeper_en_5 (
21244 .re (dio_pad_attr_5_re),
21245 .we (dio_pad_attr_5_gated_we),
21246 .wd (dio_pad_attr_5_keeper_en_5_wd),
21247 .d (hw2reg.dio_pad_attr[5].keeper_en.d),
21248 .qre (),
21249 .qe (dio_pad_attr_5_flds_we[4]),
21250 .q (reg2hw.dio_pad_attr[5].keeper_en.q),
21251 .ds (),
21252 .qs (dio_pad_attr_5_keeper_en_5_qs)
21253 );
21254 1/1 assign reg2hw.dio_pad_attr[5].keeper_en.qe = dio_pad_attr_5_qe;
Tests: T9 T10 T11
21255
21256 // F[schmitt_en_5]: 5:5
21257 prim_subreg_ext #(
21258 .DW (1)
21259 ) u_dio_pad_attr_5_schmitt_en_5 (
21260 .re (dio_pad_attr_5_re),
21261 .we (dio_pad_attr_5_gated_we),
21262 .wd (dio_pad_attr_5_schmitt_en_5_wd),
21263 .d (hw2reg.dio_pad_attr[5].schmitt_en.d),
21264 .qre (),
21265 .qe (dio_pad_attr_5_flds_we[5]),
21266 .q (reg2hw.dio_pad_attr[5].schmitt_en.q),
21267 .ds (),
21268 .qs (dio_pad_attr_5_schmitt_en_5_qs)
21269 );
21270 1/1 assign reg2hw.dio_pad_attr[5].schmitt_en.qe = dio_pad_attr_5_qe;
Tests: T9 T10 T11
21271
21272 // F[od_en_5]: 6:6
21273 prim_subreg_ext #(
21274 .DW (1)
21275 ) u_dio_pad_attr_5_od_en_5 (
21276 .re (dio_pad_attr_5_re),
21277 .we (dio_pad_attr_5_gated_we),
21278 .wd (dio_pad_attr_5_od_en_5_wd),
21279 .d (hw2reg.dio_pad_attr[5].od_en.d),
21280 .qre (),
21281 .qe (dio_pad_attr_5_flds_we[6]),
21282 .q (reg2hw.dio_pad_attr[5].od_en.q),
21283 .ds (),
21284 .qs (dio_pad_attr_5_od_en_5_qs)
21285 );
21286 1/1 assign reg2hw.dio_pad_attr[5].od_en.qe = dio_pad_attr_5_qe;
Tests: T9 T10 T11
21287
21288 // F[input_disable_5]: 7:7
21289 prim_subreg_ext #(
21290 .DW (1)
21291 ) u_dio_pad_attr_5_input_disable_5 (
21292 .re (dio_pad_attr_5_re),
21293 .we (dio_pad_attr_5_gated_we),
21294 .wd (dio_pad_attr_5_input_disable_5_wd),
21295 .d (hw2reg.dio_pad_attr[5].input_disable.d),
21296 .qre (),
21297 .qe (dio_pad_attr_5_flds_we[7]),
21298 .q (reg2hw.dio_pad_attr[5].input_disable.q),
21299 .ds (),
21300 .qs (dio_pad_attr_5_input_disable_5_qs)
21301 );
21302 1/1 assign reg2hw.dio_pad_attr[5].input_disable.qe = dio_pad_attr_5_qe;
Tests: T9 T10 T11
21303
21304 // F[slew_rate_5]: 17:16
21305 prim_subreg_ext #(
21306 .DW (2)
21307 ) u_dio_pad_attr_5_slew_rate_5 (
21308 .re (dio_pad_attr_5_re),
21309 .we (dio_pad_attr_5_gated_we),
21310 .wd (dio_pad_attr_5_slew_rate_5_wd),
21311 .d (hw2reg.dio_pad_attr[5].slew_rate.d),
21312 .qre (),
21313 .qe (dio_pad_attr_5_flds_we[8]),
21314 .q (reg2hw.dio_pad_attr[5].slew_rate.q),
21315 .ds (),
21316 .qs (dio_pad_attr_5_slew_rate_5_qs)
21317 );
21318 1/1 assign reg2hw.dio_pad_attr[5].slew_rate.qe = dio_pad_attr_5_qe;
Tests: T9 T10 T11
21319
21320 // F[drive_strength_5]: 23:20
21321 prim_subreg_ext #(
21322 .DW (4)
21323 ) u_dio_pad_attr_5_drive_strength_5 (
21324 .re (dio_pad_attr_5_re),
21325 .we (dio_pad_attr_5_gated_we),
21326 .wd (dio_pad_attr_5_drive_strength_5_wd),
21327 .d (hw2reg.dio_pad_attr[5].drive_strength.d),
21328 .qre (),
21329 .qe (dio_pad_attr_5_flds_we[9]),
21330 .q (reg2hw.dio_pad_attr[5].drive_strength.q),
21331 .ds (),
21332 .qs (dio_pad_attr_5_drive_strength_5_qs)
21333 );
21334 1/1 assign reg2hw.dio_pad_attr[5].drive_strength.qe = dio_pad_attr_5_qe;
Tests: T9 T10 T11
21335
21336
21337 // Subregister 6 of Multireg dio_pad_attr
21338 // R[dio_pad_attr_6]: V(True)
21339 logic dio_pad_attr_6_qe;
21340 logic [9:0] dio_pad_attr_6_flds_we;
21341 1/1 assign dio_pad_attr_6_qe = &dio_pad_attr_6_flds_we;
Tests: T96 T97 T98
21342 // Create REGWEN-gated WE signal
21343 logic dio_pad_attr_6_gated_we;
21344 1/1 assign dio_pad_attr_6_gated_we = dio_pad_attr_6_we & dio_pad_attr_regwen_6_qs;
Tests: T71 T96 T97
21345 // F[invert_6]: 0:0
21346 prim_subreg_ext #(
21347 .DW (1)
21348 ) u_dio_pad_attr_6_invert_6 (
21349 .re (dio_pad_attr_6_re),
21350 .we (dio_pad_attr_6_gated_we),
21351 .wd (dio_pad_attr_6_invert_6_wd),
21352 .d (hw2reg.dio_pad_attr[6].invert.d),
21353 .qre (),
21354 .qe (dio_pad_attr_6_flds_we[0]),
21355 .q (reg2hw.dio_pad_attr[6].invert.q),
21356 .ds (),
21357 .qs (dio_pad_attr_6_invert_6_qs)
21358 );
21359 1/1 assign reg2hw.dio_pad_attr[6].invert.qe = dio_pad_attr_6_qe;
Tests: T96 T97 T98
21360
21361 // F[virtual_od_en_6]: 1:1
21362 prim_subreg_ext #(
21363 .DW (1)
21364 ) u_dio_pad_attr_6_virtual_od_en_6 (
21365 .re (dio_pad_attr_6_re),
21366 .we (dio_pad_attr_6_gated_we),
21367 .wd (dio_pad_attr_6_virtual_od_en_6_wd),
21368 .d (hw2reg.dio_pad_attr[6].virtual_od_en.d),
21369 .qre (),
21370 .qe (dio_pad_attr_6_flds_we[1]),
21371 .q (reg2hw.dio_pad_attr[6].virtual_od_en.q),
21372 .ds (),
21373 .qs (dio_pad_attr_6_virtual_od_en_6_qs)
21374 );
21375 1/1 assign reg2hw.dio_pad_attr[6].virtual_od_en.qe = dio_pad_attr_6_qe;
Tests: T96 T97 T98
21376
21377 // F[pull_en_6]: 2:2
21378 prim_subreg_ext #(
21379 .DW (1)
21380 ) u_dio_pad_attr_6_pull_en_6 (
21381 .re (dio_pad_attr_6_re),
21382 .we (dio_pad_attr_6_gated_we),
21383 .wd (dio_pad_attr_6_pull_en_6_wd),
21384 .d (hw2reg.dio_pad_attr[6].pull_en.d),
21385 .qre (),
21386 .qe (dio_pad_attr_6_flds_we[2]),
21387 .q (reg2hw.dio_pad_attr[6].pull_en.q),
21388 .ds (),
21389 .qs (dio_pad_attr_6_pull_en_6_qs)
21390 );
21391 1/1 assign reg2hw.dio_pad_attr[6].pull_en.qe = dio_pad_attr_6_qe;
Tests: T96 T97 T98
21392
21393 // F[pull_select_6]: 3:3
21394 prim_subreg_ext #(
21395 .DW (1)
21396 ) u_dio_pad_attr_6_pull_select_6 (
21397 .re (dio_pad_attr_6_re),
21398 .we (dio_pad_attr_6_gated_we),
21399 .wd (dio_pad_attr_6_pull_select_6_wd),
21400 .d (hw2reg.dio_pad_attr[6].pull_select.d),
21401 .qre (),
21402 .qe (dio_pad_attr_6_flds_we[3]),
21403 .q (reg2hw.dio_pad_attr[6].pull_select.q),
21404 .ds (),
21405 .qs (dio_pad_attr_6_pull_select_6_qs)
21406 );
21407 1/1 assign reg2hw.dio_pad_attr[6].pull_select.qe = dio_pad_attr_6_qe;
Tests: T96 T97 T98
21408
21409 // F[keeper_en_6]: 4:4
21410 prim_subreg_ext #(
21411 .DW (1)
21412 ) u_dio_pad_attr_6_keeper_en_6 (
21413 .re (dio_pad_attr_6_re),
21414 .we (dio_pad_attr_6_gated_we),
21415 .wd (dio_pad_attr_6_keeper_en_6_wd),
21416 .d (hw2reg.dio_pad_attr[6].keeper_en.d),
21417 .qre (),
21418 .qe (dio_pad_attr_6_flds_we[4]),
21419 .q (reg2hw.dio_pad_attr[6].keeper_en.q),
21420 .ds (),
21421 .qs (dio_pad_attr_6_keeper_en_6_qs)
21422 );
21423 1/1 assign reg2hw.dio_pad_attr[6].keeper_en.qe = dio_pad_attr_6_qe;
Tests: T96 T97 T98
21424
21425 // F[schmitt_en_6]: 5:5
21426 prim_subreg_ext #(
21427 .DW (1)
21428 ) u_dio_pad_attr_6_schmitt_en_6 (
21429 .re (dio_pad_attr_6_re),
21430 .we (dio_pad_attr_6_gated_we),
21431 .wd (dio_pad_attr_6_schmitt_en_6_wd),
21432 .d (hw2reg.dio_pad_attr[6].schmitt_en.d),
21433 .qre (),
21434 .qe (dio_pad_attr_6_flds_we[5]),
21435 .q (reg2hw.dio_pad_attr[6].schmitt_en.q),
21436 .ds (),
21437 .qs (dio_pad_attr_6_schmitt_en_6_qs)
21438 );
21439 1/1 assign reg2hw.dio_pad_attr[6].schmitt_en.qe = dio_pad_attr_6_qe;
Tests: T96 T97 T98
21440
21441 // F[od_en_6]: 6:6
21442 prim_subreg_ext #(
21443 .DW (1)
21444 ) u_dio_pad_attr_6_od_en_6 (
21445 .re (dio_pad_attr_6_re),
21446 .we (dio_pad_attr_6_gated_we),
21447 .wd (dio_pad_attr_6_od_en_6_wd),
21448 .d (hw2reg.dio_pad_attr[6].od_en.d),
21449 .qre (),
21450 .qe (dio_pad_attr_6_flds_we[6]),
21451 .q (reg2hw.dio_pad_attr[6].od_en.q),
21452 .ds (),
21453 .qs (dio_pad_attr_6_od_en_6_qs)
21454 );
21455 1/1 assign reg2hw.dio_pad_attr[6].od_en.qe = dio_pad_attr_6_qe;
Tests: T96 T97 T98
21456
21457 // F[input_disable_6]: 7:7
21458 prim_subreg_ext #(
21459 .DW (1)
21460 ) u_dio_pad_attr_6_input_disable_6 (
21461 .re (dio_pad_attr_6_re),
21462 .we (dio_pad_attr_6_gated_we),
21463 .wd (dio_pad_attr_6_input_disable_6_wd),
21464 .d (hw2reg.dio_pad_attr[6].input_disable.d),
21465 .qre (),
21466 .qe (dio_pad_attr_6_flds_we[7]),
21467 .q (reg2hw.dio_pad_attr[6].input_disable.q),
21468 .ds (),
21469 .qs (dio_pad_attr_6_input_disable_6_qs)
21470 );
21471 1/1 assign reg2hw.dio_pad_attr[6].input_disable.qe = dio_pad_attr_6_qe;
Tests: T96 T97 T98
21472
21473 // F[slew_rate_6]: 17:16
21474 prim_subreg_ext #(
21475 .DW (2)
21476 ) u_dio_pad_attr_6_slew_rate_6 (
21477 .re (dio_pad_attr_6_re),
21478 .we (dio_pad_attr_6_gated_we),
21479 .wd (dio_pad_attr_6_slew_rate_6_wd),
21480 .d (hw2reg.dio_pad_attr[6].slew_rate.d),
21481 .qre (),
21482 .qe (dio_pad_attr_6_flds_we[8]),
21483 .q (reg2hw.dio_pad_attr[6].slew_rate.q),
21484 .ds (),
21485 .qs (dio_pad_attr_6_slew_rate_6_qs)
21486 );
21487 1/1 assign reg2hw.dio_pad_attr[6].slew_rate.qe = dio_pad_attr_6_qe;
Tests: T96 T97 T98
21488
21489 // F[drive_strength_6]: 23:20
21490 prim_subreg_ext #(
21491 .DW (4)
21492 ) u_dio_pad_attr_6_drive_strength_6 (
21493 .re (dio_pad_attr_6_re),
21494 .we (dio_pad_attr_6_gated_we),
21495 .wd (dio_pad_attr_6_drive_strength_6_wd),
21496 .d (hw2reg.dio_pad_attr[6].drive_strength.d),
21497 .qre (),
21498 .qe (dio_pad_attr_6_flds_we[9]),
21499 .q (reg2hw.dio_pad_attr[6].drive_strength.q),
21500 .ds (),
21501 .qs (dio_pad_attr_6_drive_strength_6_qs)
21502 );
21503 1/1 assign reg2hw.dio_pad_attr[6].drive_strength.qe = dio_pad_attr_6_qe;
Tests: T96 T97 T98
21504
21505
21506 // Subregister 7 of Multireg dio_pad_attr
21507 // R[dio_pad_attr_7]: V(True)
21508 logic dio_pad_attr_7_qe;
21509 logic [9:0] dio_pad_attr_7_flds_we;
21510 1/1 assign dio_pad_attr_7_qe = &dio_pad_attr_7_flds_we;
Tests: T96 T97 T98
21511 // Create REGWEN-gated WE signal
21512 logic dio_pad_attr_7_gated_we;
21513 1/1 assign dio_pad_attr_7_gated_we = dio_pad_attr_7_we & dio_pad_attr_regwen_7_qs;
Tests: T71 T96 T97
21514 // F[invert_7]: 0:0
21515 prim_subreg_ext #(
21516 .DW (1)
21517 ) u_dio_pad_attr_7_invert_7 (
21518 .re (dio_pad_attr_7_re),
21519 .we (dio_pad_attr_7_gated_we),
21520 .wd (dio_pad_attr_7_invert_7_wd),
21521 .d (hw2reg.dio_pad_attr[7].invert.d),
21522 .qre (),
21523 .qe (dio_pad_attr_7_flds_we[0]),
21524 .q (reg2hw.dio_pad_attr[7].invert.q),
21525 .ds (),
21526 .qs (dio_pad_attr_7_invert_7_qs)
21527 );
21528 1/1 assign reg2hw.dio_pad_attr[7].invert.qe = dio_pad_attr_7_qe;
Tests: T96 T97 T98
21529
21530 // F[virtual_od_en_7]: 1:1
21531 prim_subreg_ext #(
21532 .DW (1)
21533 ) u_dio_pad_attr_7_virtual_od_en_7 (
21534 .re (dio_pad_attr_7_re),
21535 .we (dio_pad_attr_7_gated_we),
21536 .wd (dio_pad_attr_7_virtual_od_en_7_wd),
21537 .d (hw2reg.dio_pad_attr[7].virtual_od_en.d),
21538 .qre (),
21539 .qe (dio_pad_attr_7_flds_we[1]),
21540 .q (reg2hw.dio_pad_attr[7].virtual_od_en.q),
21541 .ds (),
21542 .qs (dio_pad_attr_7_virtual_od_en_7_qs)
21543 );
21544 1/1 assign reg2hw.dio_pad_attr[7].virtual_od_en.qe = dio_pad_attr_7_qe;
Tests: T96 T97 T98
21545
21546 // F[pull_en_7]: 2:2
21547 prim_subreg_ext #(
21548 .DW (1)
21549 ) u_dio_pad_attr_7_pull_en_7 (
21550 .re (dio_pad_attr_7_re),
21551 .we (dio_pad_attr_7_gated_we),
21552 .wd (dio_pad_attr_7_pull_en_7_wd),
21553 .d (hw2reg.dio_pad_attr[7].pull_en.d),
21554 .qre (),
21555 .qe (dio_pad_attr_7_flds_we[2]),
21556 .q (reg2hw.dio_pad_attr[7].pull_en.q),
21557 .ds (),
21558 .qs (dio_pad_attr_7_pull_en_7_qs)
21559 );
21560 1/1 assign reg2hw.dio_pad_attr[7].pull_en.qe = dio_pad_attr_7_qe;
Tests: T96 T97 T98
21561
21562 // F[pull_select_7]: 3:3
21563 prim_subreg_ext #(
21564 .DW (1)
21565 ) u_dio_pad_attr_7_pull_select_7 (
21566 .re (dio_pad_attr_7_re),
21567 .we (dio_pad_attr_7_gated_we),
21568 .wd (dio_pad_attr_7_pull_select_7_wd),
21569 .d (hw2reg.dio_pad_attr[7].pull_select.d),
21570 .qre (),
21571 .qe (dio_pad_attr_7_flds_we[3]),
21572 .q (reg2hw.dio_pad_attr[7].pull_select.q),
21573 .ds (),
21574 .qs (dio_pad_attr_7_pull_select_7_qs)
21575 );
21576 1/1 assign reg2hw.dio_pad_attr[7].pull_select.qe = dio_pad_attr_7_qe;
Tests: T96 T97 T98
21577
21578 // F[keeper_en_7]: 4:4
21579 prim_subreg_ext #(
21580 .DW (1)
21581 ) u_dio_pad_attr_7_keeper_en_7 (
21582 .re (dio_pad_attr_7_re),
21583 .we (dio_pad_attr_7_gated_we),
21584 .wd (dio_pad_attr_7_keeper_en_7_wd),
21585 .d (hw2reg.dio_pad_attr[7].keeper_en.d),
21586 .qre (),
21587 .qe (dio_pad_attr_7_flds_we[4]),
21588 .q (reg2hw.dio_pad_attr[7].keeper_en.q),
21589 .ds (),
21590 .qs (dio_pad_attr_7_keeper_en_7_qs)
21591 );
21592 1/1 assign reg2hw.dio_pad_attr[7].keeper_en.qe = dio_pad_attr_7_qe;
Tests: T96 T97 T98
21593
21594 // F[schmitt_en_7]: 5:5
21595 prim_subreg_ext #(
21596 .DW (1)
21597 ) u_dio_pad_attr_7_schmitt_en_7 (
21598 .re (dio_pad_attr_7_re),
21599 .we (dio_pad_attr_7_gated_we),
21600 .wd (dio_pad_attr_7_schmitt_en_7_wd),
21601 .d (hw2reg.dio_pad_attr[7].schmitt_en.d),
21602 .qre (),
21603 .qe (dio_pad_attr_7_flds_we[5]),
21604 .q (reg2hw.dio_pad_attr[7].schmitt_en.q),
21605 .ds (),
21606 .qs (dio_pad_attr_7_schmitt_en_7_qs)
21607 );
21608 1/1 assign reg2hw.dio_pad_attr[7].schmitt_en.qe = dio_pad_attr_7_qe;
Tests: T96 T97 T98
21609
21610 // F[od_en_7]: 6:6
21611 prim_subreg_ext #(
21612 .DW (1)
21613 ) u_dio_pad_attr_7_od_en_7 (
21614 .re (dio_pad_attr_7_re),
21615 .we (dio_pad_attr_7_gated_we),
21616 .wd (dio_pad_attr_7_od_en_7_wd),
21617 .d (hw2reg.dio_pad_attr[7].od_en.d),
21618 .qre (),
21619 .qe (dio_pad_attr_7_flds_we[6]),
21620 .q (reg2hw.dio_pad_attr[7].od_en.q),
21621 .ds (),
21622 .qs (dio_pad_attr_7_od_en_7_qs)
21623 );
21624 1/1 assign reg2hw.dio_pad_attr[7].od_en.qe = dio_pad_attr_7_qe;
Tests: T96 T97 T98
21625
21626 // F[input_disable_7]: 7:7
21627 prim_subreg_ext #(
21628 .DW (1)
21629 ) u_dio_pad_attr_7_input_disable_7 (
21630 .re (dio_pad_attr_7_re),
21631 .we (dio_pad_attr_7_gated_we),
21632 .wd (dio_pad_attr_7_input_disable_7_wd),
21633 .d (hw2reg.dio_pad_attr[7].input_disable.d),
21634 .qre (),
21635 .qe (dio_pad_attr_7_flds_we[7]),
21636 .q (reg2hw.dio_pad_attr[7].input_disable.q),
21637 .ds (),
21638 .qs (dio_pad_attr_7_input_disable_7_qs)
21639 );
21640 1/1 assign reg2hw.dio_pad_attr[7].input_disable.qe = dio_pad_attr_7_qe;
Tests: T96 T97 T98
21641
21642 // F[slew_rate_7]: 17:16
21643 prim_subreg_ext #(
21644 .DW (2)
21645 ) u_dio_pad_attr_7_slew_rate_7 (
21646 .re (dio_pad_attr_7_re),
21647 .we (dio_pad_attr_7_gated_we),
21648 .wd (dio_pad_attr_7_slew_rate_7_wd),
21649 .d (hw2reg.dio_pad_attr[7].slew_rate.d),
21650 .qre (),
21651 .qe (dio_pad_attr_7_flds_we[8]),
21652 .q (reg2hw.dio_pad_attr[7].slew_rate.q),
21653 .ds (),
21654 .qs (dio_pad_attr_7_slew_rate_7_qs)
21655 );
21656 1/1 assign reg2hw.dio_pad_attr[7].slew_rate.qe = dio_pad_attr_7_qe;
Tests: T96 T97 T98
21657
21658 // F[drive_strength_7]: 23:20
21659 prim_subreg_ext #(
21660 .DW (4)
21661 ) u_dio_pad_attr_7_drive_strength_7 (
21662 .re (dio_pad_attr_7_re),
21663 .we (dio_pad_attr_7_gated_we),
21664 .wd (dio_pad_attr_7_drive_strength_7_wd),
21665 .d (hw2reg.dio_pad_attr[7].drive_strength.d),
21666 .qre (),
21667 .qe (dio_pad_attr_7_flds_we[9]),
21668 .q (reg2hw.dio_pad_attr[7].drive_strength.q),
21669 .ds (),
21670 .qs (dio_pad_attr_7_drive_strength_7_qs)
21671 );
21672 1/1 assign reg2hw.dio_pad_attr[7].drive_strength.qe = dio_pad_attr_7_qe;
Tests: T96 T97 T98
21673
21674
21675 // Subregister 8 of Multireg dio_pad_attr
21676 // R[dio_pad_attr_8]: V(True)
21677 logic dio_pad_attr_8_qe;
21678 logic [9:0] dio_pad_attr_8_flds_we;
21679 1/1 assign dio_pad_attr_8_qe = &dio_pad_attr_8_flds_we;
Tests: T96 T97 T98
21680 // Create REGWEN-gated WE signal
21681 logic dio_pad_attr_8_gated_we;
21682 1/1 assign dio_pad_attr_8_gated_we = dio_pad_attr_8_we & dio_pad_attr_regwen_8_qs;
Tests: T71 T96 T97
21683 // F[invert_8]: 0:0
21684 prim_subreg_ext #(
21685 .DW (1)
21686 ) u_dio_pad_attr_8_invert_8 (
21687 .re (dio_pad_attr_8_re),
21688 .we (dio_pad_attr_8_gated_we),
21689 .wd (dio_pad_attr_8_invert_8_wd),
21690 .d (hw2reg.dio_pad_attr[8].invert.d),
21691 .qre (),
21692 .qe (dio_pad_attr_8_flds_we[0]),
21693 .q (reg2hw.dio_pad_attr[8].invert.q),
21694 .ds (),
21695 .qs (dio_pad_attr_8_invert_8_qs)
21696 );
21697 1/1 assign reg2hw.dio_pad_attr[8].invert.qe = dio_pad_attr_8_qe;
Tests: T96 T97 T98
21698
21699 // F[virtual_od_en_8]: 1:1
21700 prim_subreg_ext #(
21701 .DW (1)
21702 ) u_dio_pad_attr_8_virtual_od_en_8 (
21703 .re (dio_pad_attr_8_re),
21704 .we (dio_pad_attr_8_gated_we),
21705 .wd (dio_pad_attr_8_virtual_od_en_8_wd),
21706 .d (hw2reg.dio_pad_attr[8].virtual_od_en.d),
21707 .qre (),
21708 .qe (dio_pad_attr_8_flds_we[1]),
21709 .q (reg2hw.dio_pad_attr[8].virtual_od_en.q),
21710 .ds (),
21711 .qs (dio_pad_attr_8_virtual_od_en_8_qs)
21712 );
21713 1/1 assign reg2hw.dio_pad_attr[8].virtual_od_en.qe = dio_pad_attr_8_qe;
Tests: T96 T97 T98
21714
21715 // F[pull_en_8]: 2:2
21716 prim_subreg_ext #(
21717 .DW (1)
21718 ) u_dio_pad_attr_8_pull_en_8 (
21719 .re (dio_pad_attr_8_re),
21720 .we (dio_pad_attr_8_gated_we),
21721 .wd (dio_pad_attr_8_pull_en_8_wd),
21722 .d (hw2reg.dio_pad_attr[8].pull_en.d),
21723 .qre (),
21724 .qe (dio_pad_attr_8_flds_we[2]),
21725 .q (reg2hw.dio_pad_attr[8].pull_en.q),
21726 .ds (),
21727 .qs (dio_pad_attr_8_pull_en_8_qs)
21728 );
21729 1/1 assign reg2hw.dio_pad_attr[8].pull_en.qe = dio_pad_attr_8_qe;
Tests: T96 T97 T98
21730
21731 // F[pull_select_8]: 3:3
21732 prim_subreg_ext #(
21733 .DW (1)
21734 ) u_dio_pad_attr_8_pull_select_8 (
21735 .re (dio_pad_attr_8_re),
21736 .we (dio_pad_attr_8_gated_we),
21737 .wd (dio_pad_attr_8_pull_select_8_wd),
21738 .d (hw2reg.dio_pad_attr[8].pull_select.d),
21739 .qre (),
21740 .qe (dio_pad_attr_8_flds_we[3]),
21741 .q (reg2hw.dio_pad_attr[8].pull_select.q),
21742 .ds (),
21743 .qs (dio_pad_attr_8_pull_select_8_qs)
21744 );
21745 1/1 assign reg2hw.dio_pad_attr[8].pull_select.qe = dio_pad_attr_8_qe;
Tests: T96 T97 T98
21746
21747 // F[keeper_en_8]: 4:4
21748 prim_subreg_ext #(
21749 .DW (1)
21750 ) u_dio_pad_attr_8_keeper_en_8 (
21751 .re (dio_pad_attr_8_re),
21752 .we (dio_pad_attr_8_gated_we),
21753 .wd (dio_pad_attr_8_keeper_en_8_wd),
21754 .d (hw2reg.dio_pad_attr[8].keeper_en.d),
21755 .qre (),
21756 .qe (dio_pad_attr_8_flds_we[4]),
21757 .q (reg2hw.dio_pad_attr[8].keeper_en.q),
21758 .ds (),
21759 .qs (dio_pad_attr_8_keeper_en_8_qs)
21760 );
21761 1/1 assign reg2hw.dio_pad_attr[8].keeper_en.qe = dio_pad_attr_8_qe;
Tests: T96 T97 T98
21762
21763 // F[schmitt_en_8]: 5:5
21764 prim_subreg_ext #(
21765 .DW (1)
21766 ) u_dio_pad_attr_8_schmitt_en_8 (
21767 .re (dio_pad_attr_8_re),
21768 .we (dio_pad_attr_8_gated_we),
21769 .wd (dio_pad_attr_8_schmitt_en_8_wd),
21770 .d (hw2reg.dio_pad_attr[8].schmitt_en.d),
21771 .qre (),
21772 .qe (dio_pad_attr_8_flds_we[5]),
21773 .q (reg2hw.dio_pad_attr[8].schmitt_en.q),
21774 .ds (),
21775 .qs (dio_pad_attr_8_schmitt_en_8_qs)
21776 );
21777 1/1 assign reg2hw.dio_pad_attr[8].schmitt_en.qe = dio_pad_attr_8_qe;
Tests: T96 T97 T98
21778
21779 // F[od_en_8]: 6:6
21780 prim_subreg_ext #(
21781 .DW (1)
21782 ) u_dio_pad_attr_8_od_en_8 (
21783 .re (dio_pad_attr_8_re),
21784 .we (dio_pad_attr_8_gated_we),
21785 .wd (dio_pad_attr_8_od_en_8_wd),
21786 .d (hw2reg.dio_pad_attr[8].od_en.d),
21787 .qre (),
21788 .qe (dio_pad_attr_8_flds_we[6]),
21789 .q (reg2hw.dio_pad_attr[8].od_en.q),
21790 .ds (),
21791 .qs (dio_pad_attr_8_od_en_8_qs)
21792 );
21793 1/1 assign reg2hw.dio_pad_attr[8].od_en.qe = dio_pad_attr_8_qe;
Tests: T96 T97 T98
21794
21795 // F[input_disable_8]: 7:7
21796 prim_subreg_ext #(
21797 .DW (1)
21798 ) u_dio_pad_attr_8_input_disable_8 (
21799 .re (dio_pad_attr_8_re),
21800 .we (dio_pad_attr_8_gated_we),
21801 .wd (dio_pad_attr_8_input_disable_8_wd),
21802 .d (hw2reg.dio_pad_attr[8].input_disable.d),
21803 .qre (),
21804 .qe (dio_pad_attr_8_flds_we[7]),
21805 .q (reg2hw.dio_pad_attr[8].input_disable.q),
21806 .ds (),
21807 .qs (dio_pad_attr_8_input_disable_8_qs)
21808 );
21809 1/1 assign reg2hw.dio_pad_attr[8].input_disable.qe = dio_pad_attr_8_qe;
Tests: T96 T97 T98
21810
21811 // F[slew_rate_8]: 17:16
21812 prim_subreg_ext #(
21813 .DW (2)
21814 ) u_dio_pad_attr_8_slew_rate_8 (
21815 .re (dio_pad_attr_8_re),
21816 .we (dio_pad_attr_8_gated_we),
21817 .wd (dio_pad_attr_8_slew_rate_8_wd),
21818 .d (hw2reg.dio_pad_attr[8].slew_rate.d),
21819 .qre (),
21820 .qe (dio_pad_attr_8_flds_we[8]),
21821 .q (reg2hw.dio_pad_attr[8].slew_rate.q),
21822 .ds (),
21823 .qs (dio_pad_attr_8_slew_rate_8_qs)
21824 );
21825 1/1 assign reg2hw.dio_pad_attr[8].slew_rate.qe = dio_pad_attr_8_qe;
Tests: T96 T97 T98
21826
21827 // F[drive_strength_8]: 23:20
21828 prim_subreg_ext #(
21829 .DW (4)
21830 ) u_dio_pad_attr_8_drive_strength_8 (
21831 .re (dio_pad_attr_8_re),
21832 .we (dio_pad_attr_8_gated_we),
21833 .wd (dio_pad_attr_8_drive_strength_8_wd),
21834 .d (hw2reg.dio_pad_attr[8].drive_strength.d),
21835 .qre (),
21836 .qe (dio_pad_attr_8_flds_we[9]),
21837 .q (reg2hw.dio_pad_attr[8].drive_strength.q),
21838 .ds (),
21839 .qs (dio_pad_attr_8_drive_strength_8_qs)
21840 );
21841 1/1 assign reg2hw.dio_pad_attr[8].drive_strength.qe = dio_pad_attr_8_qe;
Tests: T96 T97 T98
21842
21843
21844 // Subregister 9 of Multireg dio_pad_attr
21845 // R[dio_pad_attr_9]: V(True)
21846 logic dio_pad_attr_9_qe;
21847 logic [9:0] dio_pad_attr_9_flds_we;
21848 1/1 assign dio_pad_attr_9_qe = &dio_pad_attr_9_flds_we;
Tests: T96 T97 T98
21849 // Create REGWEN-gated WE signal
21850 logic dio_pad_attr_9_gated_we;
21851 1/1 assign dio_pad_attr_9_gated_we = dio_pad_attr_9_we & dio_pad_attr_regwen_9_qs;
Tests: T71 T96 T97
21852 // F[invert_9]: 0:0
21853 prim_subreg_ext #(
21854 .DW (1)
21855 ) u_dio_pad_attr_9_invert_9 (
21856 .re (dio_pad_attr_9_re),
21857 .we (dio_pad_attr_9_gated_we),
21858 .wd (dio_pad_attr_9_invert_9_wd),
21859 .d (hw2reg.dio_pad_attr[9].invert.d),
21860 .qre (),
21861 .qe (dio_pad_attr_9_flds_we[0]),
21862 .q (reg2hw.dio_pad_attr[9].invert.q),
21863 .ds (),
21864 .qs (dio_pad_attr_9_invert_9_qs)
21865 );
21866 1/1 assign reg2hw.dio_pad_attr[9].invert.qe = dio_pad_attr_9_qe;
Tests: T96 T97 T98
21867
21868 // F[virtual_od_en_9]: 1:1
21869 prim_subreg_ext #(
21870 .DW (1)
21871 ) u_dio_pad_attr_9_virtual_od_en_9 (
21872 .re (dio_pad_attr_9_re),
21873 .we (dio_pad_attr_9_gated_we),
21874 .wd (dio_pad_attr_9_virtual_od_en_9_wd),
21875 .d (hw2reg.dio_pad_attr[9].virtual_od_en.d),
21876 .qre (),
21877 .qe (dio_pad_attr_9_flds_we[1]),
21878 .q (reg2hw.dio_pad_attr[9].virtual_od_en.q),
21879 .ds (),
21880 .qs (dio_pad_attr_9_virtual_od_en_9_qs)
21881 );
21882 1/1 assign reg2hw.dio_pad_attr[9].virtual_od_en.qe = dio_pad_attr_9_qe;
Tests: T96 T97 T98
21883
21884 // F[pull_en_9]: 2:2
21885 prim_subreg_ext #(
21886 .DW (1)
21887 ) u_dio_pad_attr_9_pull_en_9 (
21888 .re (dio_pad_attr_9_re),
21889 .we (dio_pad_attr_9_gated_we),
21890 .wd (dio_pad_attr_9_pull_en_9_wd),
21891 .d (hw2reg.dio_pad_attr[9].pull_en.d),
21892 .qre (),
21893 .qe (dio_pad_attr_9_flds_we[2]),
21894 .q (reg2hw.dio_pad_attr[9].pull_en.q),
21895 .ds (),
21896 .qs (dio_pad_attr_9_pull_en_9_qs)
21897 );
21898 1/1 assign reg2hw.dio_pad_attr[9].pull_en.qe = dio_pad_attr_9_qe;
Tests: T96 T97 T98
21899
21900 // F[pull_select_9]: 3:3
21901 prim_subreg_ext #(
21902 .DW (1)
21903 ) u_dio_pad_attr_9_pull_select_9 (
21904 .re (dio_pad_attr_9_re),
21905 .we (dio_pad_attr_9_gated_we),
21906 .wd (dio_pad_attr_9_pull_select_9_wd),
21907 .d (hw2reg.dio_pad_attr[9].pull_select.d),
21908 .qre (),
21909 .qe (dio_pad_attr_9_flds_we[3]),
21910 .q (reg2hw.dio_pad_attr[9].pull_select.q),
21911 .ds (),
21912 .qs (dio_pad_attr_9_pull_select_9_qs)
21913 );
21914 1/1 assign reg2hw.dio_pad_attr[9].pull_select.qe = dio_pad_attr_9_qe;
Tests: T96 T97 T98
21915
21916 // F[keeper_en_9]: 4:4
21917 prim_subreg_ext #(
21918 .DW (1)
21919 ) u_dio_pad_attr_9_keeper_en_9 (
21920 .re (dio_pad_attr_9_re),
21921 .we (dio_pad_attr_9_gated_we),
21922 .wd (dio_pad_attr_9_keeper_en_9_wd),
21923 .d (hw2reg.dio_pad_attr[9].keeper_en.d),
21924 .qre (),
21925 .qe (dio_pad_attr_9_flds_we[4]),
21926 .q (reg2hw.dio_pad_attr[9].keeper_en.q),
21927 .ds (),
21928 .qs (dio_pad_attr_9_keeper_en_9_qs)
21929 );
21930 1/1 assign reg2hw.dio_pad_attr[9].keeper_en.qe = dio_pad_attr_9_qe;
Tests: T96 T97 T98
21931
21932 // F[schmitt_en_9]: 5:5
21933 prim_subreg_ext #(
21934 .DW (1)
21935 ) u_dio_pad_attr_9_schmitt_en_9 (
21936 .re (dio_pad_attr_9_re),
21937 .we (dio_pad_attr_9_gated_we),
21938 .wd (dio_pad_attr_9_schmitt_en_9_wd),
21939 .d (hw2reg.dio_pad_attr[9].schmitt_en.d),
21940 .qre (),
21941 .qe (dio_pad_attr_9_flds_we[5]),
21942 .q (reg2hw.dio_pad_attr[9].schmitt_en.q),
21943 .ds (),
21944 .qs (dio_pad_attr_9_schmitt_en_9_qs)
21945 );
21946 1/1 assign reg2hw.dio_pad_attr[9].schmitt_en.qe = dio_pad_attr_9_qe;
Tests: T96 T97 T98
21947
21948 // F[od_en_9]: 6:6
21949 prim_subreg_ext #(
21950 .DW (1)
21951 ) u_dio_pad_attr_9_od_en_9 (
21952 .re (dio_pad_attr_9_re),
21953 .we (dio_pad_attr_9_gated_we),
21954 .wd (dio_pad_attr_9_od_en_9_wd),
21955 .d (hw2reg.dio_pad_attr[9].od_en.d),
21956 .qre (),
21957 .qe (dio_pad_attr_9_flds_we[6]),
21958 .q (reg2hw.dio_pad_attr[9].od_en.q),
21959 .ds (),
21960 .qs (dio_pad_attr_9_od_en_9_qs)
21961 );
21962 1/1 assign reg2hw.dio_pad_attr[9].od_en.qe = dio_pad_attr_9_qe;
Tests: T96 T97 T98
21963
21964 // F[input_disable_9]: 7:7
21965 prim_subreg_ext #(
21966 .DW (1)
21967 ) u_dio_pad_attr_9_input_disable_9 (
21968 .re (dio_pad_attr_9_re),
21969 .we (dio_pad_attr_9_gated_we),
21970 .wd (dio_pad_attr_9_input_disable_9_wd),
21971 .d (hw2reg.dio_pad_attr[9].input_disable.d),
21972 .qre (),
21973 .qe (dio_pad_attr_9_flds_we[7]),
21974 .q (reg2hw.dio_pad_attr[9].input_disable.q),
21975 .ds (),
21976 .qs (dio_pad_attr_9_input_disable_9_qs)
21977 );
21978 1/1 assign reg2hw.dio_pad_attr[9].input_disable.qe = dio_pad_attr_9_qe;
Tests: T96 T97 T98
21979
21980 // F[slew_rate_9]: 17:16
21981 prim_subreg_ext #(
21982 .DW (2)
21983 ) u_dio_pad_attr_9_slew_rate_9 (
21984 .re (dio_pad_attr_9_re),
21985 .we (dio_pad_attr_9_gated_we),
21986 .wd (dio_pad_attr_9_slew_rate_9_wd),
21987 .d (hw2reg.dio_pad_attr[9].slew_rate.d),
21988 .qre (),
21989 .qe (dio_pad_attr_9_flds_we[8]),
21990 .q (reg2hw.dio_pad_attr[9].slew_rate.q),
21991 .ds (),
21992 .qs (dio_pad_attr_9_slew_rate_9_qs)
21993 );
21994 1/1 assign reg2hw.dio_pad_attr[9].slew_rate.qe = dio_pad_attr_9_qe;
Tests: T96 T97 T98
21995
21996 // F[drive_strength_9]: 23:20
21997 prim_subreg_ext #(
21998 .DW (4)
21999 ) u_dio_pad_attr_9_drive_strength_9 (
22000 .re (dio_pad_attr_9_re),
22001 .we (dio_pad_attr_9_gated_we),
22002 .wd (dio_pad_attr_9_drive_strength_9_wd),
22003 .d (hw2reg.dio_pad_attr[9].drive_strength.d),
22004 .qre (),
22005 .qe (dio_pad_attr_9_flds_we[9]),
22006 .q (reg2hw.dio_pad_attr[9].drive_strength.q),
22007 .ds (),
22008 .qs (dio_pad_attr_9_drive_strength_9_qs)
22009 );
22010 1/1 assign reg2hw.dio_pad_attr[9].drive_strength.qe = dio_pad_attr_9_qe;
Tests: T96 T97 T98
22011
22012
22013 // Subregister 10 of Multireg dio_pad_attr
22014 // R[dio_pad_attr_10]: V(True)
22015 logic dio_pad_attr_10_qe;
22016 logic [9:0] dio_pad_attr_10_flds_we;
22017 1/1 assign dio_pad_attr_10_qe = &dio_pad_attr_10_flds_we;
Tests: T15 T51 T52
22018 // Create REGWEN-gated WE signal
22019 logic dio_pad_attr_10_gated_we;
22020 1/1 assign dio_pad_attr_10_gated_we = dio_pad_attr_10_we & dio_pad_attr_regwen_10_qs;
Tests: T15 T51 T52
22021 // F[invert_10]: 0:0
22022 prim_subreg_ext #(
22023 .DW (1)
22024 ) u_dio_pad_attr_10_invert_10 (
22025 .re (dio_pad_attr_10_re),
22026 .we (dio_pad_attr_10_gated_we),
22027 .wd (dio_pad_attr_10_invert_10_wd),
22028 .d (hw2reg.dio_pad_attr[10].invert.d),
22029 .qre (),
22030 .qe (dio_pad_attr_10_flds_we[0]),
22031 .q (reg2hw.dio_pad_attr[10].invert.q),
22032 .ds (),
22033 .qs (dio_pad_attr_10_invert_10_qs)
22034 );
22035 1/1 assign reg2hw.dio_pad_attr[10].invert.qe = dio_pad_attr_10_qe;
Tests: T15 T51 T52
22036
22037 // F[virtual_od_en_10]: 1:1
22038 prim_subreg_ext #(
22039 .DW (1)
22040 ) u_dio_pad_attr_10_virtual_od_en_10 (
22041 .re (dio_pad_attr_10_re),
22042 .we (dio_pad_attr_10_gated_we),
22043 .wd (dio_pad_attr_10_virtual_od_en_10_wd),
22044 .d (hw2reg.dio_pad_attr[10].virtual_od_en.d),
22045 .qre (),
22046 .qe (dio_pad_attr_10_flds_we[1]),
22047 .q (reg2hw.dio_pad_attr[10].virtual_od_en.q),
22048 .ds (),
22049 .qs (dio_pad_attr_10_virtual_od_en_10_qs)
22050 );
22051 1/1 assign reg2hw.dio_pad_attr[10].virtual_od_en.qe = dio_pad_attr_10_qe;
Tests: T15 T51 T52
22052
22053 // F[pull_en_10]: 2:2
22054 prim_subreg_ext #(
22055 .DW (1)
22056 ) u_dio_pad_attr_10_pull_en_10 (
22057 .re (dio_pad_attr_10_re),
22058 .we (dio_pad_attr_10_gated_we),
22059 .wd (dio_pad_attr_10_pull_en_10_wd),
22060 .d (hw2reg.dio_pad_attr[10].pull_en.d),
22061 .qre (),
22062 .qe (dio_pad_attr_10_flds_we[2]),
22063 .q (reg2hw.dio_pad_attr[10].pull_en.q),
22064 .ds (),
22065 .qs (dio_pad_attr_10_pull_en_10_qs)
22066 );
22067 1/1 assign reg2hw.dio_pad_attr[10].pull_en.qe = dio_pad_attr_10_qe;
Tests: T15 T51 T52
22068
22069 // F[pull_select_10]: 3:3
22070 prim_subreg_ext #(
22071 .DW (1)
22072 ) u_dio_pad_attr_10_pull_select_10 (
22073 .re (dio_pad_attr_10_re),
22074 .we (dio_pad_attr_10_gated_we),
22075 .wd (dio_pad_attr_10_pull_select_10_wd),
22076 .d (hw2reg.dio_pad_attr[10].pull_select.d),
22077 .qre (),
22078 .qe (dio_pad_attr_10_flds_we[3]),
22079 .q (reg2hw.dio_pad_attr[10].pull_select.q),
22080 .ds (),
22081 .qs (dio_pad_attr_10_pull_select_10_qs)
22082 );
22083 1/1 assign reg2hw.dio_pad_attr[10].pull_select.qe = dio_pad_attr_10_qe;
Tests: T15 T51 T52
22084
22085 // F[keeper_en_10]: 4:4
22086 prim_subreg_ext #(
22087 .DW (1)
22088 ) u_dio_pad_attr_10_keeper_en_10 (
22089 .re (dio_pad_attr_10_re),
22090 .we (dio_pad_attr_10_gated_we),
22091 .wd (dio_pad_attr_10_keeper_en_10_wd),
22092 .d (hw2reg.dio_pad_attr[10].keeper_en.d),
22093 .qre (),
22094 .qe (dio_pad_attr_10_flds_we[4]),
22095 .q (reg2hw.dio_pad_attr[10].keeper_en.q),
22096 .ds (),
22097 .qs (dio_pad_attr_10_keeper_en_10_qs)
22098 );
22099 1/1 assign reg2hw.dio_pad_attr[10].keeper_en.qe = dio_pad_attr_10_qe;
Tests: T15 T51 T52
22100
22101 // F[schmitt_en_10]: 5:5
22102 prim_subreg_ext #(
22103 .DW (1)
22104 ) u_dio_pad_attr_10_schmitt_en_10 (
22105 .re (dio_pad_attr_10_re),
22106 .we (dio_pad_attr_10_gated_we),
22107 .wd (dio_pad_attr_10_schmitt_en_10_wd),
22108 .d (hw2reg.dio_pad_attr[10].schmitt_en.d),
22109 .qre (),
22110 .qe (dio_pad_attr_10_flds_we[5]),
22111 .q (reg2hw.dio_pad_attr[10].schmitt_en.q),
22112 .ds (),
22113 .qs (dio_pad_attr_10_schmitt_en_10_qs)
22114 );
22115 1/1 assign reg2hw.dio_pad_attr[10].schmitt_en.qe = dio_pad_attr_10_qe;
Tests: T15 T51 T52
22116
22117 // F[od_en_10]: 6:6
22118 prim_subreg_ext #(
22119 .DW (1)
22120 ) u_dio_pad_attr_10_od_en_10 (
22121 .re (dio_pad_attr_10_re),
22122 .we (dio_pad_attr_10_gated_we),
22123 .wd (dio_pad_attr_10_od_en_10_wd),
22124 .d (hw2reg.dio_pad_attr[10].od_en.d),
22125 .qre (),
22126 .qe (dio_pad_attr_10_flds_we[6]),
22127 .q (reg2hw.dio_pad_attr[10].od_en.q),
22128 .ds (),
22129 .qs (dio_pad_attr_10_od_en_10_qs)
22130 );
22131 1/1 assign reg2hw.dio_pad_attr[10].od_en.qe = dio_pad_attr_10_qe;
Tests: T15 T51 T52
22132
22133 // F[input_disable_10]: 7:7
22134 prim_subreg_ext #(
22135 .DW (1)
22136 ) u_dio_pad_attr_10_input_disable_10 (
22137 .re (dio_pad_attr_10_re),
22138 .we (dio_pad_attr_10_gated_we),
22139 .wd (dio_pad_attr_10_input_disable_10_wd),
22140 .d (hw2reg.dio_pad_attr[10].input_disable.d),
22141 .qre (),
22142 .qe (dio_pad_attr_10_flds_we[7]),
22143 .q (reg2hw.dio_pad_attr[10].input_disable.q),
22144 .ds (),
22145 .qs (dio_pad_attr_10_input_disable_10_qs)
22146 );
22147 1/1 assign reg2hw.dio_pad_attr[10].input_disable.qe = dio_pad_attr_10_qe;
Tests: T15 T51 T52
22148
22149 // F[slew_rate_10]: 17:16
22150 prim_subreg_ext #(
22151 .DW (2)
22152 ) u_dio_pad_attr_10_slew_rate_10 (
22153 .re (dio_pad_attr_10_re),
22154 .we (dio_pad_attr_10_gated_we),
22155 .wd (dio_pad_attr_10_slew_rate_10_wd),
22156 .d (hw2reg.dio_pad_attr[10].slew_rate.d),
22157 .qre (),
22158 .qe (dio_pad_attr_10_flds_we[8]),
22159 .q (reg2hw.dio_pad_attr[10].slew_rate.q),
22160 .ds (),
22161 .qs (dio_pad_attr_10_slew_rate_10_qs)
22162 );
22163 1/1 assign reg2hw.dio_pad_attr[10].slew_rate.qe = dio_pad_attr_10_qe;
Tests: T15 T51 T52
22164
22165 // F[drive_strength_10]: 23:20
22166 prim_subreg_ext #(
22167 .DW (4)
22168 ) u_dio_pad_attr_10_drive_strength_10 (
22169 .re (dio_pad_attr_10_re),
22170 .we (dio_pad_attr_10_gated_we),
22171 .wd (dio_pad_attr_10_drive_strength_10_wd),
22172 .d (hw2reg.dio_pad_attr[10].drive_strength.d),
22173 .qre (),
22174 .qe (dio_pad_attr_10_flds_we[9]),
22175 .q (reg2hw.dio_pad_attr[10].drive_strength.q),
22176 .ds (),
22177 .qs (dio_pad_attr_10_drive_strength_10_qs)
22178 );
22179 1/1 assign reg2hw.dio_pad_attr[10].drive_strength.qe = dio_pad_attr_10_qe;
Tests: T15 T51 T52
22180
22181
22182 // Subregister 11 of Multireg dio_pad_attr
22183 // R[dio_pad_attr_11]: V(True)
22184 logic dio_pad_attr_11_qe;
22185 logic [9:0] dio_pad_attr_11_flds_we;
22186 1/1 assign dio_pad_attr_11_qe = &dio_pad_attr_11_flds_we;
Tests: T15 T51 T52
22187 // Create REGWEN-gated WE signal
22188 logic dio_pad_attr_11_gated_we;
22189 1/1 assign dio_pad_attr_11_gated_we = dio_pad_attr_11_we & dio_pad_attr_regwen_11_qs;
Tests: T15 T51 T52
22190 // F[invert_11]: 0:0
22191 prim_subreg_ext #(
22192 .DW (1)
22193 ) u_dio_pad_attr_11_invert_11 (
22194 .re (dio_pad_attr_11_re),
22195 .we (dio_pad_attr_11_gated_we),
22196 .wd (dio_pad_attr_11_invert_11_wd),
22197 .d (hw2reg.dio_pad_attr[11].invert.d),
22198 .qre (),
22199 .qe (dio_pad_attr_11_flds_we[0]),
22200 .q (reg2hw.dio_pad_attr[11].invert.q),
22201 .ds (),
22202 .qs (dio_pad_attr_11_invert_11_qs)
22203 );
22204 1/1 assign reg2hw.dio_pad_attr[11].invert.qe = dio_pad_attr_11_qe;
Tests: T15 T51 T52
22205
22206 // F[virtual_od_en_11]: 1:1
22207 prim_subreg_ext #(
22208 .DW (1)
22209 ) u_dio_pad_attr_11_virtual_od_en_11 (
22210 .re (dio_pad_attr_11_re),
22211 .we (dio_pad_attr_11_gated_we),
22212 .wd (dio_pad_attr_11_virtual_od_en_11_wd),
22213 .d (hw2reg.dio_pad_attr[11].virtual_od_en.d),
22214 .qre (),
22215 .qe (dio_pad_attr_11_flds_we[1]),
22216 .q (reg2hw.dio_pad_attr[11].virtual_od_en.q),
22217 .ds (),
22218 .qs (dio_pad_attr_11_virtual_od_en_11_qs)
22219 );
22220 1/1 assign reg2hw.dio_pad_attr[11].virtual_od_en.qe = dio_pad_attr_11_qe;
Tests: T15 T51 T52
22221
22222 // F[pull_en_11]: 2:2
22223 prim_subreg_ext #(
22224 .DW (1)
22225 ) u_dio_pad_attr_11_pull_en_11 (
22226 .re (dio_pad_attr_11_re),
22227 .we (dio_pad_attr_11_gated_we),
22228 .wd (dio_pad_attr_11_pull_en_11_wd),
22229 .d (hw2reg.dio_pad_attr[11].pull_en.d),
22230 .qre (),
22231 .qe (dio_pad_attr_11_flds_we[2]),
22232 .q (reg2hw.dio_pad_attr[11].pull_en.q),
22233 .ds (),
22234 .qs (dio_pad_attr_11_pull_en_11_qs)
22235 );
22236 1/1 assign reg2hw.dio_pad_attr[11].pull_en.qe = dio_pad_attr_11_qe;
Tests: T15 T51 T52
22237
22238 // F[pull_select_11]: 3:3
22239 prim_subreg_ext #(
22240 .DW (1)
22241 ) u_dio_pad_attr_11_pull_select_11 (
22242 .re (dio_pad_attr_11_re),
22243 .we (dio_pad_attr_11_gated_we),
22244 .wd (dio_pad_attr_11_pull_select_11_wd),
22245 .d (hw2reg.dio_pad_attr[11].pull_select.d),
22246 .qre (),
22247 .qe (dio_pad_attr_11_flds_we[3]),
22248 .q (reg2hw.dio_pad_attr[11].pull_select.q),
22249 .ds (),
22250 .qs (dio_pad_attr_11_pull_select_11_qs)
22251 );
22252 1/1 assign reg2hw.dio_pad_attr[11].pull_select.qe = dio_pad_attr_11_qe;
Tests: T15 T51 T52
22253
22254 // F[keeper_en_11]: 4:4
22255 prim_subreg_ext #(
22256 .DW (1)
22257 ) u_dio_pad_attr_11_keeper_en_11 (
22258 .re (dio_pad_attr_11_re),
22259 .we (dio_pad_attr_11_gated_we),
22260 .wd (dio_pad_attr_11_keeper_en_11_wd),
22261 .d (hw2reg.dio_pad_attr[11].keeper_en.d),
22262 .qre (),
22263 .qe (dio_pad_attr_11_flds_we[4]),
22264 .q (reg2hw.dio_pad_attr[11].keeper_en.q),
22265 .ds (),
22266 .qs (dio_pad_attr_11_keeper_en_11_qs)
22267 );
22268 1/1 assign reg2hw.dio_pad_attr[11].keeper_en.qe = dio_pad_attr_11_qe;
Tests: T15 T51 T52
22269
22270 // F[schmitt_en_11]: 5:5
22271 prim_subreg_ext #(
22272 .DW (1)
22273 ) u_dio_pad_attr_11_schmitt_en_11 (
22274 .re (dio_pad_attr_11_re),
22275 .we (dio_pad_attr_11_gated_we),
22276 .wd (dio_pad_attr_11_schmitt_en_11_wd),
22277 .d (hw2reg.dio_pad_attr[11].schmitt_en.d),
22278 .qre (),
22279 .qe (dio_pad_attr_11_flds_we[5]),
22280 .q (reg2hw.dio_pad_attr[11].schmitt_en.q),
22281 .ds (),
22282 .qs (dio_pad_attr_11_schmitt_en_11_qs)
22283 );
22284 1/1 assign reg2hw.dio_pad_attr[11].schmitt_en.qe = dio_pad_attr_11_qe;
Tests: T15 T51 T52
22285
22286 // F[od_en_11]: 6:6
22287 prim_subreg_ext #(
22288 .DW (1)
22289 ) u_dio_pad_attr_11_od_en_11 (
22290 .re (dio_pad_attr_11_re),
22291 .we (dio_pad_attr_11_gated_we),
22292 .wd (dio_pad_attr_11_od_en_11_wd),
22293 .d (hw2reg.dio_pad_attr[11].od_en.d),
22294 .qre (),
22295 .qe (dio_pad_attr_11_flds_we[6]),
22296 .q (reg2hw.dio_pad_attr[11].od_en.q),
22297 .ds (),
22298 .qs (dio_pad_attr_11_od_en_11_qs)
22299 );
22300 1/1 assign reg2hw.dio_pad_attr[11].od_en.qe = dio_pad_attr_11_qe;
Tests: T15 T51 T52
22301
22302 // F[input_disable_11]: 7:7
22303 prim_subreg_ext #(
22304 .DW (1)
22305 ) u_dio_pad_attr_11_input_disable_11 (
22306 .re (dio_pad_attr_11_re),
22307 .we (dio_pad_attr_11_gated_we),
22308 .wd (dio_pad_attr_11_input_disable_11_wd),
22309 .d (hw2reg.dio_pad_attr[11].input_disable.d),
22310 .qre (),
22311 .qe (dio_pad_attr_11_flds_we[7]),
22312 .q (reg2hw.dio_pad_attr[11].input_disable.q),
22313 .ds (),
22314 .qs (dio_pad_attr_11_input_disable_11_qs)
22315 );
22316 1/1 assign reg2hw.dio_pad_attr[11].input_disable.qe = dio_pad_attr_11_qe;
Tests: T15 T51 T52
22317
22318 // F[slew_rate_11]: 17:16
22319 prim_subreg_ext #(
22320 .DW (2)
22321 ) u_dio_pad_attr_11_slew_rate_11 (
22322 .re (dio_pad_attr_11_re),
22323 .we (dio_pad_attr_11_gated_we),
22324 .wd (dio_pad_attr_11_slew_rate_11_wd),
22325 .d (hw2reg.dio_pad_attr[11].slew_rate.d),
22326 .qre (),
22327 .qe (dio_pad_attr_11_flds_we[8]),
22328 .q (reg2hw.dio_pad_attr[11].slew_rate.q),
22329 .ds (),
22330 .qs (dio_pad_attr_11_slew_rate_11_qs)
22331 );
22332 1/1 assign reg2hw.dio_pad_attr[11].slew_rate.qe = dio_pad_attr_11_qe;
Tests: T15 T51 T52
22333
22334 // F[drive_strength_11]: 23:20
22335 prim_subreg_ext #(
22336 .DW (4)
22337 ) u_dio_pad_attr_11_drive_strength_11 (
22338 .re (dio_pad_attr_11_re),
22339 .we (dio_pad_attr_11_gated_we),
22340 .wd (dio_pad_attr_11_drive_strength_11_wd),
22341 .d (hw2reg.dio_pad_attr[11].drive_strength.d),
22342 .qre (),
22343 .qe (dio_pad_attr_11_flds_we[9]),
22344 .q (reg2hw.dio_pad_attr[11].drive_strength.q),
22345 .ds (),
22346 .qs (dio_pad_attr_11_drive_strength_11_qs)
22347 );
22348 1/1 assign reg2hw.dio_pad_attr[11].drive_strength.qe = dio_pad_attr_11_qe;
Tests: T15 T51 T52
22349
22350
22351 // Subregister 12 of Multireg dio_pad_attr
22352 // R[dio_pad_attr_12]: V(True)
22353 logic dio_pad_attr_12_qe;
22354 logic [9:0] dio_pad_attr_12_flds_we;
22355 1/1 assign dio_pad_attr_12_qe = &dio_pad_attr_12_flds_we;
Tests: T96 T97 T98
22356 // Create REGWEN-gated WE signal
22357 logic dio_pad_attr_12_gated_we;
22358 1/1 assign dio_pad_attr_12_gated_we = dio_pad_attr_12_we & dio_pad_attr_regwen_12_qs;
Tests: T96 T97 T98
22359 // F[invert_12]: 0:0
22360 prim_subreg_ext #(
22361 .DW (1)
22362 ) u_dio_pad_attr_12_invert_12 (
22363 .re (dio_pad_attr_12_re),
22364 .we (dio_pad_attr_12_gated_we),
22365 .wd (dio_pad_attr_12_invert_12_wd),
22366 .d (hw2reg.dio_pad_attr[12].invert.d),
22367 .qre (),
22368 .qe (dio_pad_attr_12_flds_we[0]),
22369 .q (reg2hw.dio_pad_attr[12].invert.q),
22370 .ds (),
22371 .qs (dio_pad_attr_12_invert_12_qs)
22372 );
22373 1/1 assign reg2hw.dio_pad_attr[12].invert.qe = dio_pad_attr_12_qe;
Tests: T96 T97 T98
22374
22375 // F[virtual_od_en_12]: 1:1
22376 prim_subreg_ext #(
22377 .DW (1)
22378 ) u_dio_pad_attr_12_virtual_od_en_12 (
22379 .re (dio_pad_attr_12_re),
22380 .we (dio_pad_attr_12_gated_we),
22381 .wd (dio_pad_attr_12_virtual_od_en_12_wd),
22382 .d (hw2reg.dio_pad_attr[12].virtual_od_en.d),
22383 .qre (),
22384 .qe (dio_pad_attr_12_flds_we[1]),
22385 .q (reg2hw.dio_pad_attr[12].virtual_od_en.q),
22386 .ds (),
22387 .qs (dio_pad_attr_12_virtual_od_en_12_qs)
22388 );
22389 1/1 assign reg2hw.dio_pad_attr[12].virtual_od_en.qe = dio_pad_attr_12_qe;
Tests: T96 T97 T98
22390
22391 // F[pull_en_12]: 2:2
22392 prim_subreg_ext #(
22393 .DW (1)
22394 ) u_dio_pad_attr_12_pull_en_12 (
22395 .re (dio_pad_attr_12_re),
22396 .we (dio_pad_attr_12_gated_we),
22397 .wd (dio_pad_attr_12_pull_en_12_wd),
22398 .d (hw2reg.dio_pad_attr[12].pull_en.d),
22399 .qre (),
22400 .qe (dio_pad_attr_12_flds_we[2]),
22401 .q (reg2hw.dio_pad_attr[12].pull_en.q),
22402 .ds (),
22403 .qs (dio_pad_attr_12_pull_en_12_qs)
22404 );
22405 1/1 assign reg2hw.dio_pad_attr[12].pull_en.qe = dio_pad_attr_12_qe;
Tests: T96 T97 T98
22406
22407 // F[pull_select_12]: 3:3
22408 prim_subreg_ext #(
22409 .DW (1)
22410 ) u_dio_pad_attr_12_pull_select_12 (
22411 .re (dio_pad_attr_12_re),
22412 .we (dio_pad_attr_12_gated_we),
22413 .wd (dio_pad_attr_12_pull_select_12_wd),
22414 .d (hw2reg.dio_pad_attr[12].pull_select.d),
22415 .qre (),
22416 .qe (dio_pad_attr_12_flds_we[3]),
22417 .q (reg2hw.dio_pad_attr[12].pull_select.q),
22418 .ds (),
22419 .qs (dio_pad_attr_12_pull_select_12_qs)
22420 );
22421 1/1 assign reg2hw.dio_pad_attr[12].pull_select.qe = dio_pad_attr_12_qe;
Tests: T96 T97 T98
22422
22423 // F[keeper_en_12]: 4:4
22424 prim_subreg_ext #(
22425 .DW (1)
22426 ) u_dio_pad_attr_12_keeper_en_12 (
22427 .re (dio_pad_attr_12_re),
22428 .we (dio_pad_attr_12_gated_we),
22429 .wd (dio_pad_attr_12_keeper_en_12_wd),
22430 .d (hw2reg.dio_pad_attr[12].keeper_en.d),
22431 .qre (),
22432 .qe (dio_pad_attr_12_flds_we[4]),
22433 .q (reg2hw.dio_pad_attr[12].keeper_en.q),
22434 .ds (),
22435 .qs (dio_pad_attr_12_keeper_en_12_qs)
22436 );
22437 1/1 assign reg2hw.dio_pad_attr[12].keeper_en.qe = dio_pad_attr_12_qe;
Tests: T96 T97 T98
22438
22439 // F[schmitt_en_12]: 5:5
22440 prim_subreg_ext #(
22441 .DW (1)
22442 ) u_dio_pad_attr_12_schmitt_en_12 (
22443 .re (dio_pad_attr_12_re),
22444 .we (dio_pad_attr_12_gated_we),
22445 .wd (dio_pad_attr_12_schmitt_en_12_wd),
22446 .d (hw2reg.dio_pad_attr[12].schmitt_en.d),
22447 .qre (),
22448 .qe (dio_pad_attr_12_flds_we[5]),
22449 .q (reg2hw.dio_pad_attr[12].schmitt_en.q),
22450 .ds (),
22451 .qs (dio_pad_attr_12_schmitt_en_12_qs)
22452 );
22453 1/1 assign reg2hw.dio_pad_attr[12].schmitt_en.qe = dio_pad_attr_12_qe;
Tests: T96 T97 T98
22454
22455 // F[od_en_12]: 6:6
22456 prim_subreg_ext #(
22457 .DW (1)
22458 ) u_dio_pad_attr_12_od_en_12 (
22459 .re (dio_pad_attr_12_re),
22460 .we (dio_pad_attr_12_gated_we),
22461 .wd (dio_pad_attr_12_od_en_12_wd),
22462 .d (hw2reg.dio_pad_attr[12].od_en.d),
22463 .qre (),
22464 .qe (dio_pad_attr_12_flds_we[6]),
22465 .q (reg2hw.dio_pad_attr[12].od_en.q),
22466 .ds (),
22467 .qs (dio_pad_attr_12_od_en_12_qs)
22468 );
22469 1/1 assign reg2hw.dio_pad_attr[12].od_en.qe = dio_pad_attr_12_qe;
Tests: T96 T97 T98
22470
22471 // F[input_disable_12]: 7:7
22472 prim_subreg_ext #(
22473 .DW (1)
22474 ) u_dio_pad_attr_12_input_disable_12 (
22475 .re (dio_pad_attr_12_re),
22476 .we (dio_pad_attr_12_gated_we),
22477 .wd (dio_pad_attr_12_input_disable_12_wd),
22478 .d (hw2reg.dio_pad_attr[12].input_disable.d),
22479 .qre (),
22480 .qe (dio_pad_attr_12_flds_we[7]),
22481 .q (reg2hw.dio_pad_attr[12].input_disable.q),
22482 .ds (),
22483 .qs (dio_pad_attr_12_input_disable_12_qs)
22484 );
22485 1/1 assign reg2hw.dio_pad_attr[12].input_disable.qe = dio_pad_attr_12_qe;
Tests: T96 T97 T98
22486
22487 // F[slew_rate_12]: 17:16
22488 prim_subreg_ext #(
22489 .DW (2)
22490 ) u_dio_pad_attr_12_slew_rate_12 (
22491 .re (dio_pad_attr_12_re),
22492 .we (dio_pad_attr_12_gated_we),
22493 .wd (dio_pad_attr_12_slew_rate_12_wd),
22494 .d (hw2reg.dio_pad_attr[12].slew_rate.d),
22495 .qre (),
22496 .qe (dio_pad_attr_12_flds_we[8]),
22497 .q (reg2hw.dio_pad_attr[12].slew_rate.q),
22498 .ds (),
22499 .qs (dio_pad_attr_12_slew_rate_12_qs)
22500 );
22501 1/1 assign reg2hw.dio_pad_attr[12].slew_rate.qe = dio_pad_attr_12_qe;
Tests: T96 T97 T98
22502
22503 // F[drive_strength_12]: 23:20
22504 prim_subreg_ext #(
22505 .DW (4)
22506 ) u_dio_pad_attr_12_drive_strength_12 (
22507 .re (dio_pad_attr_12_re),
22508 .we (dio_pad_attr_12_gated_we),
22509 .wd (dio_pad_attr_12_drive_strength_12_wd),
22510 .d (hw2reg.dio_pad_attr[12].drive_strength.d),
22511 .qre (),
22512 .qe (dio_pad_attr_12_flds_we[9]),
22513 .q (reg2hw.dio_pad_attr[12].drive_strength.q),
22514 .ds (),
22515 .qs (dio_pad_attr_12_drive_strength_12_qs)
22516 );
22517 1/1 assign reg2hw.dio_pad_attr[12].drive_strength.qe = dio_pad_attr_12_qe;
Tests: T96 T97 T98
22518
22519
22520 // Subregister 13 of Multireg dio_pad_attr
22521 // R[dio_pad_attr_13]: V(True)
22522 logic dio_pad_attr_13_qe;
22523 logic [9:0] dio_pad_attr_13_flds_we;
22524 1/1 assign dio_pad_attr_13_qe = &dio_pad_attr_13_flds_we;
Tests: T96 T97 T98
22525 // Create REGWEN-gated WE signal
22526 logic dio_pad_attr_13_gated_we;
22527 1/1 assign dio_pad_attr_13_gated_we = dio_pad_attr_13_we & dio_pad_attr_regwen_13_qs;
Tests: T71 T96 T97
22528 // F[invert_13]: 0:0
22529 prim_subreg_ext #(
22530 .DW (1)
22531 ) u_dio_pad_attr_13_invert_13 (
22532 .re (dio_pad_attr_13_re),
22533 .we (dio_pad_attr_13_gated_we),
22534 .wd (dio_pad_attr_13_invert_13_wd),
22535 .d (hw2reg.dio_pad_attr[13].invert.d),
22536 .qre (),
22537 .qe (dio_pad_attr_13_flds_we[0]),
22538 .q (reg2hw.dio_pad_attr[13].invert.q),
22539 .ds (),
22540 .qs (dio_pad_attr_13_invert_13_qs)
22541 );
22542 1/1 assign reg2hw.dio_pad_attr[13].invert.qe = dio_pad_attr_13_qe;
Tests: T96 T97 T98
22543
22544 // F[virtual_od_en_13]: 1:1
22545 prim_subreg_ext #(
22546 .DW (1)
22547 ) u_dio_pad_attr_13_virtual_od_en_13 (
22548 .re (dio_pad_attr_13_re),
22549 .we (dio_pad_attr_13_gated_we),
22550 .wd (dio_pad_attr_13_virtual_od_en_13_wd),
22551 .d (hw2reg.dio_pad_attr[13].virtual_od_en.d),
22552 .qre (),
22553 .qe (dio_pad_attr_13_flds_we[1]),
22554 .q (reg2hw.dio_pad_attr[13].virtual_od_en.q),
22555 .ds (),
22556 .qs (dio_pad_attr_13_virtual_od_en_13_qs)
22557 );
22558 1/1 assign reg2hw.dio_pad_attr[13].virtual_od_en.qe = dio_pad_attr_13_qe;
Tests: T96 T97 T98
22559
22560 // F[pull_en_13]: 2:2
22561 prim_subreg_ext #(
22562 .DW (1)
22563 ) u_dio_pad_attr_13_pull_en_13 (
22564 .re (dio_pad_attr_13_re),
22565 .we (dio_pad_attr_13_gated_we),
22566 .wd (dio_pad_attr_13_pull_en_13_wd),
22567 .d (hw2reg.dio_pad_attr[13].pull_en.d),
22568 .qre (),
22569 .qe (dio_pad_attr_13_flds_we[2]),
22570 .q (reg2hw.dio_pad_attr[13].pull_en.q),
22571 .ds (),
22572 .qs (dio_pad_attr_13_pull_en_13_qs)
22573 );
22574 1/1 assign reg2hw.dio_pad_attr[13].pull_en.qe = dio_pad_attr_13_qe;
Tests: T96 T97 T98
22575
22576 // F[pull_select_13]: 3:3
22577 prim_subreg_ext #(
22578 .DW (1)
22579 ) u_dio_pad_attr_13_pull_select_13 (
22580 .re (dio_pad_attr_13_re),
22581 .we (dio_pad_attr_13_gated_we),
22582 .wd (dio_pad_attr_13_pull_select_13_wd),
22583 .d (hw2reg.dio_pad_attr[13].pull_select.d),
22584 .qre (),
22585 .qe (dio_pad_attr_13_flds_we[3]),
22586 .q (reg2hw.dio_pad_attr[13].pull_select.q),
22587 .ds (),
22588 .qs (dio_pad_attr_13_pull_select_13_qs)
22589 );
22590 1/1 assign reg2hw.dio_pad_attr[13].pull_select.qe = dio_pad_attr_13_qe;
Tests: T96 T97 T98
22591
22592 // F[keeper_en_13]: 4:4
22593 prim_subreg_ext #(
22594 .DW (1)
22595 ) u_dio_pad_attr_13_keeper_en_13 (
22596 .re (dio_pad_attr_13_re),
22597 .we (dio_pad_attr_13_gated_we),
22598 .wd (dio_pad_attr_13_keeper_en_13_wd),
22599 .d (hw2reg.dio_pad_attr[13].keeper_en.d),
22600 .qre (),
22601 .qe (dio_pad_attr_13_flds_we[4]),
22602 .q (reg2hw.dio_pad_attr[13].keeper_en.q),
22603 .ds (),
22604 .qs (dio_pad_attr_13_keeper_en_13_qs)
22605 );
22606 1/1 assign reg2hw.dio_pad_attr[13].keeper_en.qe = dio_pad_attr_13_qe;
Tests: T96 T97 T98
22607
22608 // F[schmitt_en_13]: 5:5
22609 prim_subreg_ext #(
22610 .DW (1)
22611 ) u_dio_pad_attr_13_schmitt_en_13 (
22612 .re (dio_pad_attr_13_re),
22613 .we (dio_pad_attr_13_gated_we),
22614 .wd (dio_pad_attr_13_schmitt_en_13_wd),
22615 .d (hw2reg.dio_pad_attr[13].schmitt_en.d),
22616 .qre (),
22617 .qe (dio_pad_attr_13_flds_we[5]),
22618 .q (reg2hw.dio_pad_attr[13].schmitt_en.q),
22619 .ds (),
22620 .qs (dio_pad_attr_13_schmitt_en_13_qs)
22621 );
22622 1/1 assign reg2hw.dio_pad_attr[13].schmitt_en.qe = dio_pad_attr_13_qe;
Tests: T96 T97 T98
22623
22624 // F[od_en_13]: 6:6
22625 prim_subreg_ext #(
22626 .DW (1)
22627 ) u_dio_pad_attr_13_od_en_13 (
22628 .re (dio_pad_attr_13_re),
22629 .we (dio_pad_attr_13_gated_we),
22630 .wd (dio_pad_attr_13_od_en_13_wd),
22631 .d (hw2reg.dio_pad_attr[13].od_en.d),
22632 .qre (),
22633 .qe (dio_pad_attr_13_flds_we[6]),
22634 .q (reg2hw.dio_pad_attr[13].od_en.q),
22635 .ds (),
22636 .qs (dio_pad_attr_13_od_en_13_qs)
22637 );
22638 1/1 assign reg2hw.dio_pad_attr[13].od_en.qe = dio_pad_attr_13_qe;
Tests: T96 T97 T98
22639
22640 // F[input_disable_13]: 7:7
22641 prim_subreg_ext #(
22642 .DW (1)
22643 ) u_dio_pad_attr_13_input_disable_13 (
22644 .re (dio_pad_attr_13_re),
22645 .we (dio_pad_attr_13_gated_we),
22646 .wd (dio_pad_attr_13_input_disable_13_wd),
22647 .d (hw2reg.dio_pad_attr[13].input_disable.d),
22648 .qre (),
22649 .qe (dio_pad_attr_13_flds_we[7]),
22650 .q (reg2hw.dio_pad_attr[13].input_disable.q),
22651 .ds (),
22652 .qs (dio_pad_attr_13_input_disable_13_qs)
22653 );
22654 1/1 assign reg2hw.dio_pad_attr[13].input_disable.qe = dio_pad_attr_13_qe;
Tests: T96 T97 T98
22655
22656 // F[slew_rate_13]: 17:16
22657 prim_subreg_ext #(
22658 .DW (2)
22659 ) u_dio_pad_attr_13_slew_rate_13 (
22660 .re (dio_pad_attr_13_re),
22661 .we (dio_pad_attr_13_gated_we),
22662 .wd (dio_pad_attr_13_slew_rate_13_wd),
22663 .d (hw2reg.dio_pad_attr[13].slew_rate.d),
22664 .qre (),
22665 .qe (dio_pad_attr_13_flds_we[8]),
22666 .q (reg2hw.dio_pad_attr[13].slew_rate.q),
22667 .ds (),
22668 .qs (dio_pad_attr_13_slew_rate_13_qs)
22669 );
22670 1/1 assign reg2hw.dio_pad_attr[13].slew_rate.qe = dio_pad_attr_13_qe;
Tests: T96 T97 T98
22671
22672 // F[drive_strength_13]: 23:20
22673 prim_subreg_ext #(
22674 .DW (4)
22675 ) u_dio_pad_attr_13_drive_strength_13 (
22676 .re (dio_pad_attr_13_re),
22677 .we (dio_pad_attr_13_gated_we),
22678 .wd (dio_pad_attr_13_drive_strength_13_wd),
22679 .d (hw2reg.dio_pad_attr[13].drive_strength.d),
22680 .qre (),
22681 .qe (dio_pad_attr_13_flds_we[9]),
22682 .q (reg2hw.dio_pad_attr[13].drive_strength.q),
22683 .ds (),
22684 .qs (dio_pad_attr_13_drive_strength_13_qs)
22685 );
22686 1/1 assign reg2hw.dio_pad_attr[13].drive_strength.qe = dio_pad_attr_13_qe;
Tests: T96 T97 T98
22687
22688
22689 // Subregister 14 of Multireg dio_pad_attr
22690 // R[dio_pad_attr_14]: V(True)
22691 logic dio_pad_attr_14_qe;
22692 logic [9:0] dio_pad_attr_14_flds_we;
22693 1/1 assign dio_pad_attr_14_qe = &dio_pad_attr_14_flds_we;
Tests: T9 T47 T48
22694 // Create REGWEN-gated WE signal
22695 logic dio_pad_attr_14_gated_we;
22696 1/1 assign dio_pad_attr_14_gated_we = dio_pad_attr_14_we & dio_pad_attr_regwen_14_qs;
Tests: T9 T47 T48
22697 // F[invert_14]: 0:0
22698 prim_subreg_ext #(
22699 .DW (1)
22700 ) u_dio_pad_attr_14_invert_14 (
22701 .re (dio_pad_attr_14_re),
22702 .we (dio_pad_attr_14_gated_we),
22703 .wd (dio_pad_attr_14_invert_14_wd),
22704 .d (hw2reg.dio_pad_attr[14].invert.d),
22705 .qre (),
22706 .qe (dio_pad_attr_14_flds_we[0]),
22707 .q (reg2hw.dio_pad_attr[14].invert.q),
22708 .ds (),
22709 .qs (dio_pad_attr_14_invert_14_qs)
22710 );
22711 1/1 assign reg2hw.dio_pad_attr[14].invert.qe = dio_pad_attr_14_qe;
Tests: T9 T47 T48
22712
22713 // F[virtual_od_en_14]: 1:1
22714 prim_subreg_ext #(
22715 .DW (1)
22716 ) u_dio_pad_attr_14_virtual_od_en_14 (
22717 .re (dio_pad_attr_14_re),
22718 .we (dio_pad_attr_14_gated_we),
22719 .wd (dio_pad_attr_14_virtual_od_en_14_wd),
22720 .d (hw2reg.dio_pad_attr[14].virtual_od_en.d),
22721 .qre (),
22722 .qe (dio_pad_attr_14_flds_we[1]),
22723 .q (reg2hw.dio_pad_attr[14].virtual_od_en.q),
22724 .ds (),
22725 .qs (dio_pad_attr_14_virtual_od_en_14_qs)
22726 );
22727 1/1 assign reg2hw.dio_pad_attr[14].virtual_od_en.qe = dio_pad_attr_14_qe;
Tests: T9 T47 T48
22728
22729 // F[pull_en_14]: 2:2
22730 prim_subreg_ext #(
22731 .DW (1)
22732 ) u_dio_pad_attr_14_pull_en_14 (
22733 .re (dio_pad_attr_14_re),
22734 .we (dio_pad_attr_14_gated_we),
22735 .wd (dio_pad_attr_14_pull_en_14_wd),
22736 .d (hw2reg.dio_pad_attr[14].pull_en.d),
22737 .qre (),
22738 .qe (dio_pad_attr_14_flds_we[2]),
22739 .q (reg2hw.dio_pad_attr[14].pull_en.q),
22740 .ds (),
22741 .qs (dio_pad_attr_14_pull_en_14_qs)
22742 );
22743 1/1 assign reg2hw.dio_pad_attr[14].pull_en.qe = dio_pad_attr_14_qe;
Tests: T9 T47 T48
22744
22745 // F[pull_select_14]: 3:3
22746 prim_subreg_ext #(
22747 .DW (1)
22748 ) u_dio_pad_attr_14_pull_select_14 (
22749 .re (dio_pad_attr_14_re),
22750 .we (dio_pad_attr_14_gated_we),
22751 .wd (dio_pad_attr_14_pull_select_14_wd),
22752 .d (hw2reg.dio_pad_attr[14].pull_select.d),
22753 .qre (),
22754 .qe (dio_pad_attr_14_flds_we[3]),
22755 .q (reg2hw.dio_pad_attr[14].pull_select.q),
22756 .ds (),
22757 .qs (dio_pad_attr_14_pull_select_14_qs)
22758 );
22759 1/1 assign reg2hw.dio_pad_attr[14].pull_select.qe = dio_pad_attr_14_qe;
Tests: T9 T47 T48
22760
22761 // F[keeper_en_14]: 4:4
22762 prim_subreg_ext #(
22763 .DW (1)
22764 ) u_dio_pad_attr_14_keeper_en_14 (
22765 .re (dio_pad_attr_14_re),
22766 .we (dio_pad_attr_14_gated_we),
22767 .wd (dio_pad_attr_14_keeper_en_14_wd),
22768 .d (hw2reg.dio_pad_attr[14].keeper_en.d),
22769 .qre (),
22770 .qe (dio_pad_attr_14_flds_we[4]),
22771 .q (reg2hw.dio_pad_attr[14].keeper_en.q),
22772 .ds (),
22773 .qs (dio_pad_attr_14_keeper_en_14_qs)
22774 );
22775 1/1 assign reg2hw.dio_pad_attr[14].keeper_en.qe = dio_pad_attr_14_qe;
Tests: T9 T47 T48
22776
22777 // F[schmitt_en_14]: 5:5
22778 prim_subreg_ext #(
22779 .DW (1)
22780 ) u_dio_pad_attr_14_schmitt_en_14 (
22781 .re (dio_pad_attr_14_re),
22782 .we (dio_pad_attr_14_gated_we),
22783 .wd (dio_pad_attr_14_schmitt_en_14_wd),
22784 .d (hw2reg.dio_pad_attr[14].schmitt_en.d),
22785 .qre (),
22786 .qe (dio_pad_attr_14_flds_we[5]),
22787 .q (reg2hw.dio_pad_attr[14].schmitt_en.q),
22788 .ds (),
22789 .qs (dio_pad_attr_14_schmitt_en_14_qs)
22790 );
22791 1/1 assign reg2hw.dio_pad_attr[14].schmitt_en.qe = dio_pad_attr_14_qe;
Tests: T9 T47 T48
22792
22793 // F[od_en_14]: 6:6
22794 prim_subreg_ext #(
22795 .DW (1)
22796 ) u_dio_pad_attr_14_od_en_14 (
22797 .re (dio_pad_attr_14_re),
22798 .we (dio_pad_attr_14_gated_we),
22799 .wd (dio_pad_attr_14_od_en_14_wd),
22800 .d (hw2reg.dio_pad_attr[14].od_en.d),
22801 .qre (),
22802 .qe (dio_pad_attr_14_flds_we[6]),
22803 .q (reg2hw.dio_pad_attr[14].od_en.q),
22804 .ds (),
22805 .qs (dio_pad_attr_14_od_en_14_qs)
22806 );
22807 1/1 assign reg2hw.dio_pad_attr[14].od_en.qe = dio_pad_attr_14_qe;
Tests: T9 T47 T48
22808
22809 // F[input_disable_14]: 7:7
22810 prim_subreg_ext #(
22811 .DW (1)
22812 ) u_dio_pad_attr_14_input_disable_14 (
22813 .re (dio_pad_attr_14_re),
22814 .we (dio_pad_attr_14_gated_we),
22815 .wd (dio_pad_attr_14_input_disable_14_wd),
22816 .d (hw2reg.dio_pad_attr[14].input_disable.d),
22817 .qre (),
22818 .qe (dio_pad_attr_14_flds_we[7]),
22819 .q (reg2hw.dio_pad_attr[14].input_disable.q),
22820 .ds (),
22821 .qs (dio_pad_attr_14_input_disable_14_qs)
22822 );
22823 1/1 assign reg2hw.dio_pad_attr[14].input_disable.qe = dio_pad_attr_14_qe;
Tests: T9 T47 T48
22824
22825 // F[slew_rate_14]: 17:16
22826 prim_subreg_ext #(
22827 .DW (2)
22828 ) u_dio_pad_attr_14_slew_rate_14 (
22829 .re (dio_pad_attr_14_re),
22830 .we (dio_pad_attr_14_gated_we),
22831 .wd (dio_pad_attr_14_slew_rate_14_wd),
22832 .d (hw2reg.dio_pad_attr[14].slew_rate.d),
22833 .qre (),
22834 .qe (dio_pad_attr_14_flds_we[8]),
22835 .q (reg2hw.dio_pad_attr[14].slew_rate.q),
22836 .ds (),
22837 .qs (dio_pad_attr_14_slew_rate_14_qs)
22838 );
22839 1/1 assign reg2hw.dio_pad_attr[14].slew_rate.qe = dio_pad_attr_14_qe;
Tests: T9 T47 T48
22840
22841 // F[drive_strength_14]: 23:20
22842 prim_subreg_ext #(
22843 .DW (4)
22844 ) u_dio_pad_attr_14_drive_strength_14 (
22845 .re (dio_pad_attr_14_re),
22846 .we (dio_pad_attr_14_gated_we),
22847 .wd (dio_pad_attr_14_drive_strength_14_wd),
22848 .d (hw2reg.dio_pad_attr[14].drive_strength.d),
22849 .qre (),
22850 .qe (dio_pad_attr_14_flds_we[9]),
22851 .q (reg2hw.dio_pad_attr[14].drive_strength.q),
22852 .ds (),
22853 .qs (dio_pad_attr_14_drive_strength_14_qs)
22854 );
22855 1/1 assign reg2hw.dio_pad_attr[14].drive_strength.qe = dio_pad_attr_14_qe;
Tests: T9 T47 T48
22856
22857
22858 // Subregister 15 of Multireg dio_pad_attr
22859 // R[dio_pad_attr_15]: V(True)
22860 logic dio_pad_attr_15_qe;
22861 logic [9:0] dio_pad_attr_15_flds_we;
22862 1/1 assign dio_pad_attr_15_qe = &dio_pad_attr_15_flds_we;
Tests: T9 T47 T48
22863 // Create REGWEN-gated WE signal
22864 logic dio_pad_attr_15_gated_we;
22865 1/1 assign dio_pad_attr_15_gated_we = dio_pad_attr_15_we & dio_pad_attr_regwen_15_qs;
Tests: T9 T47 T48
22866 // F[invert_15]: 0:0
22867 prim_subreg_ext #(
22868 .DW (1)
22869 ) u_dio_pad_attr_15_invert_15 (
22870 .re (dio_pad_attr_15_re),
22871 .we (dio_pad_attr_15_gated_we),
22872 .wd (dio_pad_attr_15_invert_15_wd),
22873 .d (hw2reg.dio_pad_attr[15].invert.d),
22874 .qre (),
22875 .qe (dio_pad_attr_15_flds_we[0]),
22876 .q (reg2hw.dio_pad_attr[15].invert.q),
22877 .ds (),
22878 .qs (dio_pad_attr_15_invert_15_qs)
22879 );
22880 1/1 assign reg2hw.dio_pad_attr[15].invert.qe = dio_pad_attr_15_qe;
Tests: T9 T47 T48
22881
22882 // F[virtual_od_en_15]: 1:1
22883 prim_subreg_ext #(
22884 .DW (1)
22885 ) u_dio_pad_attr_15_virtual_od_en_15 (
22886 .re (dio_pad_attr_15_re),
22887 .we (dio_pad_attr_15_gated_we),
22888 .wd (dio_pad_attr_15_virtual_od_en_15_wd),
22889 .d (hw2reg.dio_pad_attr[15].virtual_od_en.d),
22890 .qre (),
22891 .qe (dio_pad_attr_15_flds_we[1]),
22892 .q (reg2hw.dio_pad_attr[15].virtual_od_en.q),
22893 .ds (),
22894 .qs (dio_pad_attr_15_virtual_od_en_15_qs)
22895 );
22896 1/1 assign reg2hw.dio_pad_attr[15].virtual_od_en.qe = dio_pad_attr_15_qe;
Tests: T9 T47 T48
22897
22898 // F[pull_en_15]: 2:2
22899 prim_subreg_ext #(
22900 .DW (1)
22901 ) u_dio_pad_attr_15_pull_en_15 (
22902 .re (dio_pad_attr_15_re),
22903 .we (dio_pad_attr_15_gated_we),
22904 .wd (dio_pad_attr_15_pull_en_15_wd),
22905 .d (hw2reg.dio_pad_attr[15].pull_en.d),
22906 .qre (),
22907 .qe (dio_pad_attr_15_flds_we[2]),
22908 .q (reg2hw.dio_pad_attr[15].pull_en.q),
22909 .ds (),
22910 .qs (dio_pad_attr_15_pull_en_15_qs)
22911 );
22912 1/1 assign reg2hw.dio_pad_attr[15].pull_en.qe = dio_pad_attr_15_qe;
Tests: T9 T47 T48
22913
22914 // F[pull_select_15]: 3:3
22915 prim_subreg_ext #(
22916 .DW (1)
22917 ) u_dio_pad_attr_15_pull_select_15 (
22918 .re (dio_pad_attr_15_re),
22919 .we (dio_pad_attr_15_gated_we),
22920 .wd (dio_pad_attr_15_pull_select_15_wd),
22921 .d (hw2reg.dio_pad_attr[15].pull_select.d),
22922 .qre (),
22923 .qe (dio_pad_attr_15_flds_we[3]),
22924 .q (reg2hw.dio_pad_attr[15].pull_select.q),
22925 .ds (),
22926 .qs (dio_pad_attr_15_pull_select_15_qs)
22927 );
22928 1/1 assign reg2hw.dio_pad_attr[15].pull_select.qe = dio_pad_attr_15_qe;
Tests: T9 T47 T48
22929
22930 // F[keeper_en_15]: 4:4
22931 prim_subreg_ext #(
22932 .DW (1)
22933 ) u_dio_pad_attr_15_keeper_en_15 (
22934 .re (dio_pad_attr_15_re),
22935 .we (dio_pad_attr_15_gated_we),
22936 .wd (dio_pad_attr_15_keeper_en_15_wd),
22937 .d (hw2reg.dio_pad_attr[15].keeper_en.d),
22938 .qre (),
22939 .qe (dio_pad_attr_15_flds_we[4]),
22940 .q (reg2hw.dio_pad_attr[15].keeper_en.q),
22941 .ds (),
22942 .qs (dio_pad_attr_15_keeper_en_15_qs)
22943 );
22944 1/1 assign reg2hw.dio_pad_attr[15].keeper_en.qe = dio_pad_attr_15_qe;
Tests: T9 T47 T48
22945
22946 // F[schmitt_en_15]: 5:5
22947 prim_subreg_ext #(
22948 .DW (1)
22949 ) u_dio_pad_attr_15_schmitt_en_15 (
22950 .re (dio_pad_attr_15_re),
22951 .we (dio_pad_attr_15_gated_we),
22952 .wd (dio_pad_attr_15_schmitt_en_15_wd),
22953 .d (hw2reg.dio_pad_attr[15].schmitt_en.d),
22954 .qre (),
22955 .qe (dio_pad_attr_15_flds_we[5]),
22956 .q (reg2hw.dio_pad_attr[15].schmitt_en.q),
22957 .ds (),
22958 .qs (dio_pad_attr_15_schmitt_en_15_qs)
22959 );
22960 1/1 assign reg2hw.dio_pad_attr[15].schmitt_en.qe = dio_pad_attr_15_qe;
Tests: T9 T47 T48
22961
22962 // F[od_en_15]: 6:6
22963 prim_subreg_ext #(
22964 .DW (1)
22965 ) u_dio_pad_attr_15_od_en_15 (
22966 .re (dio_pad_attr_15_re),
22967 .we (dio_pad_attr_15_gated_we),
22968 .wd (dio_pad_attr_15_od_en_15_wd),
22969 .d (hw2reg.dio_pad_attr[15].od_en.d),
22970 .qre (),
22971 .qe (dio_pad_attr_15_flds_we[6]),
22972 .q (reg2hw.dio_pad_attr[15].od_en.q),
22973 .ds (),
22974 .qs (dio_pad_attr_15_od_en_15_qs)
22975 );
22976 1/1 assign reg2hw.dio_pad_attr[15].od_en.qe = dio_pad_attr_15_qe;
Tests: T9 T47 T48
22977
22978 // F[input_disable_15]: 7:7
22979 prim_subreg_ext #(
22980 .DW (1)
22981 ) u_dio_pad_attr_15_input_disable_15 (
22982 .re (dio_pad_attr_15_re),
22983 .we (dio_pad_attr_15_gated_we),
22984 .wd (dio_pad_attr_15_input_disable_15_wd),
22985 .d (hw2reg.dio_pad_attr[15].input_disable.d),
22986 .qre (),
22987 .qe (dio_pad_attr_15_flds_we[7]),
22988 .q (reg2hw.dio_pad_attr[15].input_disable.q),
22989 .ds (),
22990 .qs (dio_pad_attr_15_input_disable_15_qs)
22991 );
22992 1/1 assign reg2hw.dio_pad_attr[15].input_disable.qe = dio_pad_attr_15_qe;
Tests: T9 T47 T48
22993
22994 // F[slew_rate_15]: 17:16
22995 prim_subreg_ext #(
22996 .DW (2)
22997 ) u_dio_pad_attr_15_slew_rate_15 (
22998 .re (dio_pad_attr_15_re),
22999 .we (dio_pad_attr_15_gated_we),
23000 .wd (dio_pad_attr_15_slew_rate_15_wd),
23001 .d (hw2reg.dio_pad_attr[15].slew_rate.d),
23002 .qre (),
23003 .qe (dio_pad_attr_15_flds_we[8]),
23004 .q (reg2hw.dio_pad_attr[15].slew_rate.q),
23005 .ds (),
23006 .qs (dio_pad_attr_15_slew_rate_15_qs)
23007 );
23008 1/1 assign reg2hw.dio_pad_attr[15].slew_rate.qe = dio_pad_attr_15_qe;
Tests: T9 T47 T48
23009
23010 // F[drive_strength_15]: 23:20
23011 prim_subreg_ext #(
23012 .DW (4)
23013 ) u_dio_pad_attr_15_drive_strength_15 (
23014 .re (dio_pad_attr_15_re),
23015 .we (dio_pad_attr_15_gated_we),
23016 .wd (dio_pad_attr_15_drive_strength_15_wd),
23017 .d (hw2reg.dio_pad_attr[15].drive_strength.d),
23018 .qre (),
23019 .qe (dio_pad_attr_15_flds_we[9]),
23020 .q (reg2hw.dio_pad_attr[15].drive_strength.q),
23021 .ds (),
23022 .qs (dio_pad_attr_15_drive_strength_15_qs)
23023 );
23024 1/1 assign reg2hw.dio_pad_attr[15].drive_strength.qe = dio_pad_attr_15_qe;
Tests: T9 T47 T48
23025
23026
23027 // Subregister 0 of Multireg mio_pad_sleep_status
23028 // R[mio_pad_sleep_status_0]: V(False)
23029 // F[en_0]: 0:0
23030 prim_subreg #(
23031 .DW (1),
23032 .SwAccess(prim_subreg_pkg::SwAccessW0C),
23033 .RESVAL (1'h0),
23034 .Mubi (1'b0)
23035 ) u_mio_pad_sleep_status_0_en_0 (
23036 .clk_i (clk_i),
23037 .rst_ni (rst_ni),
23038
23039 // from register interface
23040 .we (mio_pad_sleep_status_0_we),
23041 .wd (mio_pad_sleep_status_0_en_0_wd),
23042
23043 // from internal hardware
23044 .de (hw2reg.mio_pad_sleep_status[0].de),
23045 .d (hw2reg.mio_pad_sleep_status[0].d),
23046
23047 // to internal hardware
23048 .qe (),
23049 .q (reg2hw.mio_pad_sleep_status[0].q),
23050 .ds (),
23051
23052 // to register interface (read)
23053 .qs (mio_pad_sleep_status_0_en_0_qs)
23054 );
23055
23056 // F[en_1]: 1:1
23057 prim_subreg #(
23058 .DW (1),
23059 .SwAccess(prim_subreg_pkg::SwAccessW0C),
23060 .RESVAL (1'h0),
23061 .Mubi (1'b0)
23062 ) u_mio_pad_sleep_status_0_en_1 (
23063 .clk_i (clk_i),
23064 .rst_ni (rst_ni),
23065
23066 // from register interface
23067 .we (mio_pad_sleep_status_0_we),
23068 .wd (mio_pad_sleep_status_0_en_1_wd),
23069
23070 // from internal hardware
23071 .de (hw2reg.mio_pad_sleep_status[1].de),
23072 .d (hw2reg.mio_pad_sleep_status[1].d),
23073
23074 // to internal hardware
23075 .qe (),
23076 .q (reg2hw.mio_pad_sleep_status[1].q),
23077 .ds (),
23078
23079 // to register interface (read)
23080 .qs (mio_pad_sleep_status_0_en_1_qs)
23081 );
23082
23083 // F[en_2]: 2:2
23084 prim_subreg #(
23085 .DW (1),
23086 .SwAccess(prim_subreg_pkg::SwAccessW0C),
23087 .RESVAL (1'h0),
23088 .Mubi (1'b0)
23089 ) u_mio_pad_sleep_status_0_en_2 (
23090 .clk_i (clk_i),
23091 .rst_ni (rst_ni),
23092
23093 // from register interface
23094 .we (mio_pad_sleep_status_0_we),
23095 .wd (mio_pad_sleep_status_0_en_2_wd),
23096
23097 // from internal hardware
23098 .de (hw2reg.mio_pad_sleep_status[2].de),
23099 .d (hw2reg.mio_pad_sleep_status[2].d),
23100
23101 // to internal hardware
23102 .qe (),
23103 .q (reg2hw.mio_pad_sleep_status[2].q),
23104 .ds (),
23105
23106 // to register interface (read)
23107 .qs (mio_pad_sleep_status_0_en_2_qs)
23108 );
23109
23110 // F[en_3]: 3:3
23111 prim_subreg #(
23112 .DW (1),
23113 .SwAccess(prim_subreg_pkg::SwAccessW0C),
23114 .RESVAL (1'h0),
23115 .Mubi (1'b0)
23116 ) u_mio_pad_sleep_status_0_en_3 (
23117 .clk_i (clk_i),
23118 .rst_ni (rst_ni),
23119
23120 // from register interface
23121 .we (mio_pad_sleep_status_0_we),
23122 .wd (mio_pad_sleep_status_0_en_3_wd),
23123
23124 // from internal hardware
23125 .de (hw2reg.mio_pad_sleep_status[3].de),
23126 .d (hw2reg.mio_pad_sleep_status[3].d),
23127
23128 // to internal hardware
23129 .qe (),
23130 .q (reg2hw.mio_pad_sleep_status[3].q),
23131 .ds (),
23132
23133 // to register interface (read)
23134 .qs (mio_pad_sleep_status_0_en_3_qs)
23135 );
23136
23137 // F[en_4]: 4:4
23138 prim_subreg #(
23139 .DW (1),
23140 .SwAccess(prim_subreg_pkg::SwAccessW0C),
23141 .RESVAL (1'h0),
23142 .Mubi (1'b0)
23143 ) u_mio_pad_sleep_status_0_en_4 (
23144 .clk_i (clk_i),
23145 .rst_ni (rst_ni),
23146
23147 // from register interface
23148 .we (mio_pad_sleep_status_0_we),
23149 .wd (mio_pad_sleep_status_0_en_4_wd),
23150
23151 // from internal hardware
23152 .de (hw2reg.mio_pad_sleep_status[4].de),
23153 .d (hw2reg.mio_pad_sleep_status[4].d),
23154
23155 // to internal hardware
23156 .qe (),
23157 .q (reg2hw.mio_pad_sleep_status[4].q),
23158 .ds (),
23159
23160 // to register interface (read)
23161 .qs (mio_pad_sleep_status_0_en_4_qs)
23162 );
23163
23164 // F[en_5]: 5:5
23165 prim_subreg #(
23166 .DW (1),
23167 .SwAccess(prim_subreg_pkg::SwAccessW0C),
23168 .RESVAL (1'h0),
23169 .Mubi (1'b0)
23170 ) u_mio_pad_sleep_status_0_en_5 (
23171 .clk_i (clk_i),
23172 .rst_ni (rst_ni),
23173
23174 // from register interface
23175 .we (mio_pad_sleep_status_0_we),
23176 .wd (mio_pad_sleep_status_0_en_5_wd),
23177
23178 // from internal hardware
23179 .de (hw2reg.mio_pad_sleep_status[5].de),
23180 .d (hw2reg.mio_pad_sleep_status[5].d),
23181
23182 // to internal hardware
23183 .qe (),
23184 .q (reg2hw.mio_pad_sleep_status[5].q),
23185 .ds (),
23186
23187 // to register interface (read)
23188 .qs (mio_pad_sleep_status_0_en_5_qs)
23189 );
23190
23191 // F[en_6]: 6:6
23192 prim_subreg #(
23193 .DW (1),
23194 .SwAccess(prim_subreg_pkg::SwAccessW0C),
23195 .RESVAL (1'h0),
23196 .Mubi (1'b0)
23197 ) u_mio_pad_sleep_status_0_en_6 (
23198 .clk_i (clk_i),
23199 .rst_ni (rst_ni),
23200
23201 // from register interface
23202 .we (mio_pad_sleep_status_0_we),
23203 .wd (mio_pad_sleep_status_0_en_6_wd),
23204
23205 // from internal hardware
23206 .de (hw2reg.mio_pad_sleep_status[6].de),
23207 .d (hw2reg.mio_pad_sleep_status[6].d),
23208
23209 // to internal hardware
23210 .qe (),
23211 .q (reg2hw.mio_pad_sleep_status[6].q),
23212 .ds (),
23213
23214 // to register interface (read)
23215 .qs (mio_pad_sleep_status_0_en_6_qs)
23216 );
23217
23218 // F[en_7]: 7:7
23219 prim_subreg #(
23220 .DW (1),
23221 .SwAccess(prim_subreg_pkg::SwAccessW0C),
23222 .RESVAL (1'h0),
23223 .Mubi (1'b0)
23224 ) u_mio_pad_sleep_status_0_en_7 (
23225 .clk_i (clk_i),
23226 .rst_ni (rst_ni),
23227
23228 // from register interface
23229 .we (mio_pad_sleep_status_0_we),
23230 .wd (mio_pad_sleep_status_0_en_7_wd),
23231
23232 // from internal hardware
23233 .de (hw2reg.mio_pad_sleep_status[7].de),
23234 .d (hw2reg.mio_pad_sleep_status[7].d),
23235
23236 // to internal hardware
23237 .qe (),
23238 .q (reg2hw.mio_pad_sleep_status[7].q),
23239 .ds (),
23240
23241 // to register interface (read)
23242 .qs (mio_pad_sleep_status_0_en_7_qs)
23243 );
23244
23245 // F[en_8]: 8:8
23246 prim_subreg #(
23247 .DW (1),
23248 .SwAccess(prim_subreg_pkg::SwAccessW0C),
23249 .RESVAL (1'h0),
23250 .Mubi (1'b0)
23251 ) u_mio_pad_sleep_status_0_en_8 (
23252 .clk_i (clk_i),
23253 .rst_ni (rst_ni),
23254
23255 // from register interface
23256 .we (mio_pad_sleep_status_0_we),
23257 .wd (mio_pad_sleep_status_0_en_8_wd),
23258
23259 // from internal hardware
23260 .de (hw2reg.mio_pad_sleep_status[8].de),
23261 .d (hw2reg.mio_pad_sleep_status[8].d),
23262
23263 // to internal hardware
23264 .qe (),
23265 .q (reg2hw.mio_pad_sleep_status[8].q),
23266 .ds (),
23267
23268 // to register interface (read)
23269 .qs (mio_pad_sleep_status_0_en_8_qs)
23270 );
23271
23272 // F[en_9]: 9:9
23273 prim_subreg #(
23274 .DW (1),
23275 .SwAccess(prim_subreg_pkg::SwAccessW0C),
23276 .RESVAL (1'h0),
23277 .Mubi (1'b0)
23278 ) u_mio_pad_sleep_status_0_en_9 (
23279 .clk_i (clk_i),
23280 .rst_ni (rst_ni),
23281
23282 // from register interface
23283 .we (mio_pad_sleep_status_0_we),
23284 .wd (mio_pad_sleep_status_0_en_9_wd),
23285
23286 // from internal hardware
23287 .de (hw2reg.mio_pad_sleep_status[9].de),
23288 .d (hw2reg.mio_pad_sleep_status[9].d),
23289
23290 // to internal hardware
23291 .qe (),
23292 .q (reg2hw.mio_pad_sleep_status[9].q),
23293 .ds (),
23294
23295 // to register interface (read)
23296 .qs (mio_pad_sleep_status_0_en_9_qs)
23297 );
23298
23299 // F[en_10]: 10:10
23300 prim_subreg #(
23301 .DW (1),
23302 .SwAccess(prim_subreg_pkg::SwAccessW0C),
23303 .RESVAL (1'h0),
23304 .Mubi (1'b0)
23305 ) u_mio_pad_sleep_status_0_en_10 (
23306 .clk_i (clk_i),
23307 .rst_ni (rst_ni),
23308
23309 // from register interface
23310 .we (mio_pad_sleep_status_0_we),
23311 .wd (mio_pad_sleep_status_0_en_10_wd),
23312
23313 // from internal hardware
23314 .de (hw2reg.mio_pad_sleep_status[10].de),
23315 .d (hw2reg.mio_pad_sleep_status[10].d),
23316
23317 // to internal hardware
23318 .qe (),
23319 .q (reg2hw.mio_pad_sleep_status[10].q),
23320 .ds (),
23321
23322 // to register interface (read)
23323 .qs (mio_pad_sleep_status_0_en_10_qs)
23324 );
23325
23326 // F[en_11]: 11:11
23327 prim_subreg #(
23328 .DW (1),
23329 .SwAccess(prim_subreg_pkg::SwAccessW0C),
23330 .RESVAL (1'h0),
23331 .Mubi (1'b0)
23332 ) u_mio_pad_sleep_status_0_en_11 (
23333 .clk_i (clk_i),
23334 .rst_ni (rst_ni),
23335
23336 // from register interface
23337 .we (mio_pad_sleep_status_0_we),
23338 .wd (mio_pad_sleep_status_0_en_11_wd),
23339
23340 // from internal hardware
23341 .de (hw2reg.mio_pad_sleep_status[11].de),
23342 .d (hw2reg.mio_pad_sleep_status[11].d),
23343
23344 // to internal hardware
23345 .qe (),
23346 .q (reg2hw.mio_pad_sleep_status[11].q),
23347 .ds (),
23348
23349 // to register interface (read)
23350 .qs (mio_pad_sleep_status_0_en_11_qs)
23351 );
23352
23353 // F[en_12]: 12:12
23354 prim_subreg #(
23355 .DW (1),
23356 .SwAccess(prim_subreg_pkg::SwAccessW0C),
23357 .RESVAL (1'h0),
23358 .Mubi (1'b0)
23359 ) u_mio_pad_sleep_status_0_en_12 (
23360 .clk_i (clk_i),
23361 .rst_ni (rst_ni),
23362
23363 // from register interface
23364 .we (mio_pad_sleep_status_0_we),
23365 .wd (mio_pad_sleep_status_0_en_12_wd),
23366
23367 // from internal hardware
23368 .de (hw2reg.mio_pad_sleep_status[12].de),
23369 .d (hw2reg.mio_pad_sleep_status[12].d),
23370
23371 // to internal hardware
23372 .qe (),
23373 .q (reg2hw.mio_pad_sleep_status[12].q),
23374 .ds (),
23375
23376 // to register interface (read)
23377 .qs (mio_pad_sleep_status_0_en_12_qs)
23378 );
23379
23380 // F[en_13]: 13:13
23381 prim_subreg #(
23382 .DW (1),
23383 .SwAccess(prim_subreg_pkg::SwAccessW0C),
23384 .RESVAL (1'h0),
23385 .Mubi (1'b0)
23386 ) u_mio_pad_sleep_status_0_en_13 (
23387 .clk_i (clk_i),
23388 .rst_ni (rst_ni),
23389
23390 // from register interface
23391 .we (mio_pad_sleep_status_0_we),
23392 .wd (mio_pad_sleep_status_0_en_13_wd),
23393
23394 // from internal hardware
23395 .de (hw2reg.mio_pad_sleep_status[13].de),
23396 .d (hw2reg.mio_pad_sleep_status[13].d),
23397
23398 // to internal hardware
23399 .qe (),
23400 .q (reg2hw.mio_pad_sleep_status[13].q),
23401 .ds (),
23402
23403 // to register interface (read)
23404 .qs (mio_pad_sleep_status_0_en_13_qs)
23405 );
23406
23407 // F[en_14]: 14:14
23408 prim_subreg #(
23409 .DW (1),
23410 .SwAccess(prim_subreg_pkg::SwAccessW0C),
23411 .RESVAL (1'h0),
23412 .Mubi (1'b0)
23413 ) u_mio_pad_sleep_status_0_en_14 (
23414 .clk_i (clk_i),
23415 .rst_ni (rst_ni),
23416
23417 // from register interface
23418 .we (mio_pad_sleep_status_0_we),
23419 .wd (mio_pad_sleep_status_0_en_14_wd),
23420
23421 // from internal hardware
23422 .de (hw2reg.mio_pad_sleep_status[14].de),
23423 .d (hw2reg.mio_pad_sleep_status[14].d),
23424
23425 // to internal hardware
23426 .qe (),
23427 .q (reg2hw.mio_pad_sleep_status[14].q),
23428 .ds (),
23429
23430 // to register interface (read)
23431 .qs (mio_pad_sleep_status_0_en_14_qs)
23432 );
23433
23434 // F[en_15]: 15:15
23435 prim_subreg #(
23436 .DW (1),
23437 .SwAccess(prim_subreg_pkg::SwAccessW0C),
23438 .RESVAL (1'h0),
23439 .Mubi (1'b0)
23440 ) u_mio_pad_sleep_status_0_en_15 (
23441 .clk_i (clk_i),
23442 .rst_ni (rst_ni),
23443
23444 // from register interface
23445 .we (mio_pad_sleep_status_0_we),
23446 .wd (mio_pad_sleep_status_0_en_15_wd),
23447
23448 // from internal hardware
23449 .de (hw2reg.mio_pad_sleep_status[15].de),
23450 .d (hw2reg.mio_pad_sleep_status[15].d),
23451
23452 // to internal hardware
23453 .qe (),
23454 .q (reg2hw.mio_pad_sleep_status[15].q),
23455 .ds (),
23456
23457 // to register interface (read)
23458 .qs (mio_pad_sleep_status_0_en_15_qs)
23459 );
23460
23461 // F[en_16]: 16:16
23462 prim_subreg #(
23463 .DW (1),
23464 .SwAccess(prim_subreg_pkg::SwAccessW0C),
23465 .RESVAL (1'h0),
23466 .Mubi (1'b0)
23467 ) u_mio_pad_sleep_status_0_en_16 (
23468 .clk_i (clk_i),
23469 .rst_ni (rst_ni),
23470
23471 // from register interface
23472 .we (mio_pad_sleep_status_0_we),
23473 .wd (mio_pad_sleep_status_0_en_16_wd),
23474
23475 // from internal hardware
23476 .de (hw2reg.mio_pad_sleep_status[16].de),
23477 .d (hw2reg.mio_pad_sleep_status[16].d),
23478
23479 // to internal hardware
23480 .qe (),
23481 .q (reg2hw.mio_pad_sleep_status[16].q),
23482 .ds (),
23483
23484 // to register interface (read)
23485 .qs (mio_pad_sleep_status_0_en_16_qs)
23486 );
23487
23488 // F[en_17]: 17:17
23489 prim_subreg #(
23490 .DW (1),
23491 .SwAccess(prim_subreg_pkg::SwAccessW0C),
23492 .RESVAL (1'h0),
23493 .Mubi (1'b0)
23494 ) u_mio_pad_sleep_status_0_en_17 (
23495 .clk_i (clk_i),
23496 .rst_ni (rst_ni),
23497
23498 // from register interface
23499 .we (mio_pad_sleep_status_0_we),
23500 .wd (mio_pad_sleep_status_0_en_17_wd),
23501
23502 // from internal hardware
23503 .de (hw2reg.mio_pad_sleep_status[17].de),
23504 .d (hw2reg.mio_pad_sleep_status[17].d),
23505
23506 // to internal hardware
23507 .qe (),
23508 .q (reg2hw.mio_pad_sleep_status[17].q),
23509 .ds (),
23510
23511 // to register interface (read)
23512 .qs (mio_pad_sleep_status_0_en_17_qs)
23513 );
23514
23515 // F[en_18]: 18:18
23516 prim_subreg #(
23517 .DW (1),
23518 .SwAccess(prim_subreg_pkg::SwAccessW0C),
23519 .RESVAL (1'h0),
23520 .Mubi (1'b0)
23521 ) u_mio_pad_sleep_status_0_en_18 (
23522 .clk_i (clk_i),
23523 .rst_ni (rst_ni),
23524
23525 // from register interface
23526 .we (mio_pad_sleep_status_0_we),
23527 .wd (mio_pad_sleep_status_0_en_18_wd),
23528
23529 // from internal hardware
23530 .de (hw2reg.mio_pad_sleep_status[18].de),
23531 .d (hw2reg.mio_pad_sleep_status[18].d),
23532
23533 // to internal hardware
23534 .qe (),
23535 .q (reg2hw.mio_pad_sleep_status[18].q),
23536 .ds (),
23537
23538 // to register interface (read)
23539 .qs (mio_pad_sleep_status_0_en_18_qs)
23540 );
23541
23542 // F[en_19]: 19:19
23543 prim_subreg #(
23544 .DW (1),
23545 .SwAccess(prim_subreg_pkg::SwAccessW0C),
23546 .RESVAL (1'h0),
23547 .Mubi (1'b0)
23548 ) u_mio_pad_sleep_status_0_en_19 (
23549 .clk_i (clk_i),
23550 .rst_ni (rst_ni),
23551
23552 // from register interface
23553 .we (mio_pad_sleep_status_0_we),
23554 .wd (mio_pad_sleep_status_0_en_19_wd),
23555
23556 // from internal hardware
23557 .de (hw2reg.mio_pad_sleep_status[19].de),
23558 .d (hw2reg.mio_pad_sleep_status[19].d),
23559
23560 // to internal hardware
23561 .qe (),
23562 .q (reg2hw.mio_pad_sleep_status[19].q),
23563 .ds (),
23564
23565 // to register interface (read)
23566 .qs (mio_pad_sleep_status_0_en_19_qs)
23567 );
23568
23569 // F[en_20]: 20:20
23570 prim_subreg #(
23571 .DW (1),
23572 .SwAccess(prim_subreg_pkg::SwAccessW0C),
23573 .RESVAL (1'h0),
23574 .Mubi (1'b0)
23575 ) u_mio_pad_sleep_status_0_en_20 (
23576 .clk_i (clk_i),
23577 .rst_ni (rst_ni),
23578
23579 // from register interface
23580 .we (mio_pad_sleep_status_0_we),
23581 .wd (mio_pad_sleep_status_0_en_20_wd),
23582
23583 // from internal hardware
23584 .de (hw2reg.mio_pad_sleep_status[20].de),
23585 .d (hw2reg.mio_pad_sleep_status[20].d),
23586
23587 // to internal hardware
23588 .qe (),
23589 .q (reg2hw.mio_pad_sleep_status[20].q),
23590 .ds (),
23591
23592 // to register interface (read)
23593 .qs (mio_pad_sleep_status_0_en_20_qs)
23594 );
23595
23596 // F[en_21]: 21:21
23597 prim_subreg #(
23598 .DW (1),
23599 .SwAccess(prim_subreg_pkg::SwAccessW0C),
23600 .RESVAL (1'h0),
23601 .Mubi (1'b0)
23602 ) u_mio_pad_sleep_status_0_en_21 (
23603 .clk_i (clk_i),
23604 .rst_ni (rst_ni),
23605
23606 // from register interface
23607 .we (mio_pad_sleep_status_0_we),
23608 .wd (mio_pad_sleep_status_0_en_21_wd),
23609
23610 // from internal hardware
23611 .de (hw2reg.mio_pad_sleep_status[21].de),
23612 .d (hw2reg.mio_pad_sleep_status[21].d),
23613
23614 // to internal hardware
23615 .qe (),
23616 .q (reg2hw.mio_pad_sleep_status[21].q),
23617 .ds (),
23618
23619 // to register interface (read)
23620 .qs (mio_pad_sleep_status_0_en_21_qs)
23621 );
23622
23623 // F[en_22]: 22:22
23624 prim_subreg #(
23625 .DW (1),
23626 .SwAccess(prim_subreg_pkg::SwAccessW0C),
23627 .RESVAL (1'h0),
23628 .Mubi (1'b0)
23629 ) u_mio_pad_sleep_status_0_en_22 (
23630 .clk_i (clk_i),
23631 .rst_ni (rst_ni),
23632
23633 // from register interface
23634 .we (mio_pad_sleep_status_0_we),
23635 .wd (mio_pad_sleep_status_0_en_22_wd),
23636
23637 // from internal hardware
23638 .de (hw2reg.mio_pad_sleep_status[22].de),
23639 .d (hw2reg.mio_pad_sleep_status[22].d),
23640
23641 // to internal hardware
23642 .qe (),
23643 .q (reg2hw.mio_pad_sleep_status[22].q),
23644 .ds (),
23645
23646 // to register interface (read)
23647 .qs (mio_pad_sleep_status_0_en_22_qs)
23648 );
23649
23650 // F[en_23]: 23:23
23651 prim_subreg #(
23652 .DW (1),
23653 .SwAccess(prim_subreg_pkg::SwAccessW0C),
23654 .RESVAL (1'h0),
23655 .Mubi (1'b0)
23656 ) u_mio_pad_sleep_status_0_en_23 (
23657 .clk_i (clk_i),
23658 .rst_ni (rst_ni),
23659
23660 // from register interface
23661 .we (mio_pad_sleep_status_0_we),
23662 .wd (mio_pad_sleep_status_0_en_23_wd),
23663
23664 // from internal hardware
23665 .de (hw2reg.mio_pad_sleep_status[23].de),
23666 .d (hw2reg.mio_pad_sleep_status[23].d),
23667
23668 // to internal hardware
23669 .qe (),
23670 .q (reg2hw.mio_pad_sleep_status[23].q),
23671 .ds (),
23672
23673 // to register interface (read)
23674 .qs (mio_pad_sleep_status_0_en_23_qs)
23675 );
23676
23677 // F[en_24]: 24:24
23678 prim_subreg #(
23679 .DW (1),
23680 .SwAccess(prim_subreg_pkg::SwAccessW0C),
23681 .RESVAL (1'h0),
23682 .Mubi (1'b0)
23683 ) u_mio_pad_sleep_status_0_en_24 (
23684 .clk_i (clk_i),
23685 .rst_ni (rst_ni),
23686
23687 // from register interface
23688 .we (mio_pad_sleep_status_0_we),
23689 .wd (mio_pad_sleep_status_0_en_24_wd),
23690
23691 // from internal hardware
23692 .de (hw2reg.mio_pad_sleep_status[24].de),
23693 .d (hw2reg.mio_pad_sleep_status[24].d),
23694
23695 // to internal hardware
23696 .qe (),
23697 .q (reg2hw.mio_pad_sleep_status[24].q),
23698 .ds (),
23699
23700 // to register interface (read)
23701 .qs (mio_pad_sleep_status_0_en_24_qs)
23702 );
23703
23704 // F[en_25]: 25:25
23705 prim_subreg #(
23706 .DW (1),
23707 .SwAccess(prim_subreg_pkg::SwAccessW0C),
23708 .RESVAL (1'h0),
23709 .Mubi (1'b0)
23710 ) u_mio_pad_sleep_status_0_en_25 (
23711 .clk_i (clk_i),
23712 .rst_ni (rst_ni),
23713
23714 // from register interface
23715 .we (mio_pad_sleep_status_0_we),
23716 .wd (mio_pad_sleep_status_0_en_25_wd),
23717
23718 // from internal hardware
23719 .de (hw2reg.mio_pad_sleep_status[25].de),
23720 .d (hw2reg.mio_pad_sleep_status[25].d),
23721
23722 // to internal hardware
23723 .qe (),
23724 .q (reg2hw.mio_pad_sleep_status[25].q),
23725 .ds (),
23726
23727 // to register interface (read)
23728 .qs (mio_pad_sleep_status_0_en_25_qs)
23729 );
23730
23731 // F[en_26]: 26:26
23732 prim_subreg #(
23733 .DW (1),
23734 .SwAccess(prim_subreg_pkg::SwAccessW0C),
23735 .RESVAL (1'h0),
23736 .Mubi (1'b0)
23737 ) u_mio_pad_sleep_status_0_en_26 (
23738 .clk_i (clk_i),
23739 .rst_ni (rst_ni),
23740
23741 // from register interface
23742 .we (mio_pad_sleep_status_0_we),
23743 .wd (mio_pad_sleep_status_0_en_26_wd),
23744
23745 // from internal hardware
23746 .de (hw2reg.mio_pad_sleep_status[26].de),
23747 .d (hw2reg.mio_pad_sleep_status[26].d),
23748
23749 // to internal hardware
23750 .qe (),
23751 .q (reg2hw.mio_pad_sleep_status[26].q),
23752 .ds (),
23753
23754 // to register interface (read)
23755 .qs (mio_pad_sleep_status_0_en_26_qs)
23756 );
23757
23758 // F[en_27]: 27:27
23759 prim_subreg #(
23760 .DW (1),
23761 .SwAccess(prim_subreg_pkg::SwAccessW0C),
23762 .RESVAL (1'h0),
23763 .Mubi (1'b0)
23764 ) u_mio_pad_sleep_status_0_en_27 (
23765 .clk_i (clk_i),
23766 .rst_ni (rst_ni),
23767
23768 // from register interface
23769 .we (mio_pad_sleep_status_0_we),
23770 .wd (mio_pad_sleep_status_0_en_27_wd),
23771
23772 // from internal hardware
23773 .de (hw2reg.mio_pad_sleep_status[27].de),
23774 .d (hw2reg.mio_pad_sleep_status[27].d),
23775
23776 // to internal hardware
23777 .qe (),
23778 .q (reg2hw.mio_pad_sleep_status[27].q),
23779 .ds (),
23780
23781 // to register interface (read)
23782 .qs (mio_pad_sleep_status_0_en_27_qs)
23783 );
23784
23785 // F[en_28]: 28:28
23786 prim_subreg #(
23787 .DW (1),
23788 .SwAccess(prim_subreg_pkg::SwAccessW0C),
23789 .RESVAL (1'h0),
23790 .Mubi (1'b0)
23791 ) u_mio_pad_sleep_status_0_en_28 (
23792 .clk_i (clk_i),
23793 .rst_ni (rst_ni),
23794
23795 // from register interface
23796 .we (mio_pad_sleep_status_0_we),
23797 .wd (mio_pad_sleep_status_0_en_28_wd),
23798
23799 // from internal hardware
23800 .de (hw2reg.mio_pad_sleep_status[28].de),
23801 .d (hw2reg.mio_pad_sleep_status[28].d),
23802
23803 // to internal hardware
23804 .qe (),
23805 .q (reg2hw.mio_pad_sleep_status[28].q),
23806 .ds (),
23807
23808 // to register interface (read)
23809 .qs (mio_pad_sleep_status_0_en_28_qs)
23810 );
23811
23812 // F[en_29]: 29:29
23813 prim_subreg #(
23814 .DW (1),
23815 .SwAccess(prim_subreg_pkg::SwAccessW0C),
23816 .RESVAL (1'h0),
23817 .Mubi (1'b0)
23818 ) u_mio_pad_sleep_status_0_en_29 (
23819 .clk_i (clk_i),
23820 .rst_ni (rst_ni),
23821
23822 // from register interface
23823 .we (mio_pad_sleep_status_0_we),
23824 .wd (mio_pad_sleep_status_0_en_29_wd),
23825
23826 // from internal hardware
23827 .de (hw2reg.mio_pad_sleep_status[29].de),
23828 .d (hw2reg.mio_pad_sleep_status[29].d),
23829
23830 // to internal hardware
23831 .qe (),
23832 .q (reg2hw.mio_pad_sleep_status[29].q),
23833 .ds (),
23834
23835 // to register interface (read)
23836 .qs (mio_pad_sleep_status_0_en_29_qs)
23837 );
23838
23839 // F[en_30]: 30:30
23840 prim_subreg #(
23841 .DW (1),
23842 .SwAccess(prim_subreg_pkg::SwAccessW0C),
23843 .RESVAL (1'h0),
23844 .Mubi (1'b0)
23845 ) u_mio_pad_sleep_status_0_en_30 (
23846 .clk_i (clk_i),
23847 .rst_ni (rst_ni),
23848
23849 // from register interface
23850 .we (mio_pad_sleep_status_0_we),
23851 .wd (mio_pad_sleep_status_0_en_30_wd),
23852
23853 // from internal hardware
23854 .de (hw2reg.mio_pad_sleep_status[30].de),
23855 .d (hw2reg.mio_pad_sleep_status[30].d),
23856
23857 // to internal hardware
23858 .qe (),
23859 .q (reg2hw.mio_pad_sleep_status[30].q),
23860 .ds (),
23861
23862 // to register interface (read)
23863 .qs (mio_pad_sleep_status_0_en_30_qs)
23864 );
23865
23866 // F[en_31]: 31:31
23867 prim_subreg #(
23868 .DW (1),
23869 .SwAccess(prim_subreg_pkg::SwAccessW0C),
23870 .RESVAL (1'h0),
23871 .Mubi (1'b0)
23872 ) u_mio_pad_sleep_status_0_en_31 (
23873 .clk_i (clk_i),
23874 .rst_ni (rst_ni),
23875
23876 // from register interface
23877 .we (mio_pad_sleep_status_0_we),
23878 .wd (mio_pad_sleep_status_0_en_31_wd),
23879
23880 // from internal hardware
23881 .de (hw2reg.mio_pad_sleep_status[31].de),
23882 .d (hw2reg.mio_pad_sleep_status[31].d),
23883
23884 // to internal hardware
23885 .qe (),
23886 .q (reg2hw.mio_pad_sleep_status[31].q),
23887 .ds (),
23888
23889 // to register interface (read)
23890 .qs (mio_pad_sleep_status_0_en_31_qs)
23891 );
23892
23893
23894 // Subregister 1 of Multireg mio_pad_sleep_status
23895 // R[mio_pad_sleep_status_1]: V(False)
23896 // F[en_32]: 0:0
23897 prim_subreg #(
23898 .DW (1),
23899 .SwAccess(prim_subreg_pkg::SwAccessW0C),
23900 .RESVAL (1'h0),
23901 .Mubi (1'b0)
23902 ) u_mio_pad_sleep_status_1_en_32 (
23903 .clk_i (clk_i),
23904 .rst_ni (rst_ni),
23905
23906 // from register interface
23907 .we (mio_pad_sleep_status_1_we),
23908 .wd (mio_pad_sleep_status_1_en_32_wd),
23909
23910 // from internal hardware
23911 .de (hw2reg.mio_pad_sleep_status[32].de),
23912 .d (hw2reg.mio_pad_sleep_status[32].d),
23913
23914 // to internal hardware
23915 .qe (),
23916 .q (reg2hw.mio_pad_sleep_status[32].q),
23917 .ds (),
23918
23919 // to register interface (read)
23920 .qs (mio_pad_sleep_status_1_en_32_qs)
23921 );
23922
23923 // F[en_33]: 1:1
23924 prim_subreg #(
23925 .DW (1),
23926 .SwAccess(prim_subreg_pkg::SwAccessW0C),
23927 .RESVAL (1'h0),
23928 .Mubi (1'b0)
23929 ) u_mio_pad_sleep_status_1_en_33 (
23930 .clk_i (clk_i),
23931 .rst_ni (rst_ni),
23932
23933 // from register interface
23934 .we (mio_pad_sleep_status_1_we),
23935 .wd (mio_pad_sleep_status_1_en_33_wd),
23936
23937 // from internal hardware
23938 .de (hw2reg.mio_pad_sleep_status[33].de),
23939 .d (hw2reg.mio_pad_sleep_status[33].d),
23940
23941 // to internal hardware
23942 .qe (),
23943 .q (reg2hw.mio_pad_sleep_status[33].q),
23944 .ds (),
23945
23946 // to register interface (read)
23947 .qs (mio_pad_sleep_status_1_en_33_qs)
23948 );
23949
23950 // F[en_34]: 2:2
23951 prim_subreg #(
23952 .DW (1),
23953 .SwAccess(prim_subreg_pkg::SwAccessW0C),
23954 .RESVAL (1'h0),
23955 .Mubi (1'b0)
23956 ) u_mio_pad_sleep_status_1_en_34 (
23957 .clk_i (clk_i),
23958 .rst_ni (rst_ni),
23959
23960 // from register interface
23961 .we (mio_pad_sleep_status_1_we),
23962 .wd (mio_pad_sleep_status_1_en_34_wd),
23963
23964 // from internal hardware
23965 .de (hw2reg.mio_pad_sleep_status[34].de),
23966 .d (hw2reg.mio_pad_sleep_status[34].d),
23967
23968 // to internal hardware
23969 .qe (),
23970 .q (reg2hw.mio_pad_sleep_status[34].q),
23971 .ds (),
23972
23973 // to register interface (read)
23974 .qs (mio_pad_sleep_status_1_en_34_qs)
23975 );
23976
23977 // F[en_35]: 3:3
23978 prim_subreg #(
23979 .DW (1),
23980 .SwAccess(prim_subreg_pkg::SwAccessW0C),
23981 .RESVAL (1'h0),
23982 .Mubi (1'b0)
23983 ) u_mio_pad_sleep_status_1_en_35 (
23984 .clk_i (clk_i),
23985 .rst_ni (rst_ni),
23986
23987 // from register interface
23988 .we (mio_pad_sleep_status_1_we),
23989 .wd (mio_pad_sleep_status_1_en_35_wd),
23990
23991 // from internal hardware
23992 .de (hw2reg.mio_pad_sleep_status[35].de),
23993 .d (hw2reg.mio_pad_sleep_status[35].d),
23994
23995 // to internal hardware
23996 .qe (),
23997 .q (reg2hw.mio_pad_sleep_status[35].q),
23998 .ds (),
23999
24000 // to register interface (read)
24001 .qs (mio_pad_sleep_status_1_en_35_qs)
24002 );
24003
24004 // F[en_36]: 4:4
24005 prim_subreg #(
24006 .DW (1),
24007 .SwAccess(prim_subreg_pkg::SwAccessW0C),
24008 .RESVAL (1'h0),
24009 .Mubi (1'b0)
24010 ) u_mio_pad_sleep_status_1_en_36 (
24011 .clk_i (clk_i),
24012 .rst_ni (rst_ni),
24013
24014 // from register interface
24015 .we (mio_pad_sleep_status_1_we),
24016 .wd (mio_pad_sleep_status_1_en_36_wd),
24017
24018 // from internal hardware
24019 .de (hw2reg.mio_pad_sleep_status[36].de),
24020 .d (hw2reg.mio_pad_sleep_status[36].d),
24021
24022 // to internal hardware
24023 .qe (),
24024 .q (reg2hw.mio_pad_sleep_status[36].q),
24025 .ds (),
24026
24027 // to register interface (read)
24028 .qs (mio_pad_sleep_status_1_en_36_qs)
24029 );
24030
24031 // F[en_37]: 5:5
24032 prim_subreg #(
24033 .DW (1),
24034 .SwAccess(prim_subreg_pkg::SwAccessW0C),
24035 .RESVAL (1'h0),
24036 .Mubi (1'b0)
24037 ) u_mio_pad_sleep_status_1_en_37 (
24038 .clk_i (clk_i),
24039 .rst_ni (rst_ni),
24040
24041 // from register interface
24042 .we (mio_pad_sleep_status_1_we),
24043 .wd (mio_pad_sleep_status_1_en_37_wd),
24044
24045 // from internal hardware
24046 .de (hw2reg.mio_pad_sleep_status[37].de),
24047 .d (hw2reg.mio_pad_sleep_status[37].d),
24048
24049 // to internal hardware
24050 .qe (),
24051 .q (reg2hw.mio_pad_sleep_status[37].q),
24052 .ds (),
24053
24054 // to register interface (read)
24055 .qs (mio_pad_sleep_status_1_en_37_qs)
24056 );
24057
24058 // F[en_38]: 6:6
24059 prim_subreg #(
24060 .DW (1),
24061 .SwAccess(prim_subreg_pkg::SwAccessW0C),
24062 .RESVAL (1'h0),
24063 .Mubi (1'b0)
24064 ) u_mio_pad_sleep_status_1_en_38 (
24065 .clk_i (clk_i),
24066 .rst_ni (rst_ni),
24067
24068 // from register interface
24069 .we (mio_pad_sleep_status_1_we),
24070 .wd (mio_pad_sleep_status_1_en_38_wd),
24071
24072 // from internal hardware
24073 .de (hw2reg.mio_pad_sleep_status[38].de),
24074 .d (hw2reg.mio_pad_sleep_status[38].d),
24075
24076 // to internal hardware
24077 .qe (),
24078 .q (reg2hw.mio_pad_sleep_status[38].q),
24079 .ds (),
24080
24081 // to register interface (read)
24082 .qs (mio_pad_sleep_status_1_en_38_qs)
24083 );
24084
24085 // F[en_39]: 7:7
24086 prim_subreg #(
24087 .DW (1),
24088 .SwAccess(prim_subreg_pkg::SwAccessW0C),
24089 .RESVAL (1'h0),
24090 .Mubi (1'b0)
24091 ) u_mio_pad_sleep_status_1_en_39 (
24092 .clk_i (clk_i),
24093 .rst_ni (rst_ni),
24094
24095 // from register interface
24096 .we (mio_pad_sleep_status_1_we),
24097 .wd (mio_pad_sleep_status_1_en_39_wd),
24098
24099 // from internal hardware
24100 .de (hw2reg.mio_pad_sleep_status[39].de),
24101 .d (hw2reg.mio_pad_sleep_status[39].d),
24102
24103 // to internal hardware
24104 .qe (),
24105 .q (reg2hw.mio_pad_sleep_status[39].q),
24106 .ds (),
24107
24108 // to register interface (read)
24109 .qs (mio_pad_sleep_status_1_en_39_qs)
24110 );
24111
24112 // F[en_40]: 8:8
24113 prim_subreg #(
24114 .DW (1),
24115 .SwAccess(prim_subreg_pkg::SwAccessW0C),
24116 .RESVAL (1'h0),
24117 .Mubi (1'b0)
24118 ) u_mio_pad_sleep_status_1_en_40 (
24119 .clk_i (clk_i),
24120 .rst_ni (rst_ni),
24121
24122 // from register interface
24123 .we (mio_pad_sleep_status_1_we),
24124 .wd (mio_pad_sleep_status_1_en_40_wd),
24125
24126 // from internal hardware
24127 .de (hw2reg.mio_pad_sleep_status[40].de),
24128 .d (hw2reg.mio_pad_sleep_status[40].d),
24129
24130 // to internal hardware
24131 .qe (),
24132 .q (reg2hw.mio_pad_sleep_status[40].q),
24133 .ds (),
24134
24135 // to register interface (read)
24136 .qs (mio_pad_sleep_status_1_en_40_qs)
24137 );
24138
24139 // F[en_41]: 9:9
24140 prim_subreg #(
24141 .DW (1),
24142 .SwAccess(prim_subreg_pkg::SwAccessW0C),
24143 .RESVAL (1'h0),
24144 .Mubi (1'b0)
24145 ) u_mio_pad_sleep_status_1_en_41 (
24146 .clk_i (clk_i),
24147 .rst_ni (rst_ni),
24148
24149 // from register interface
24150 .we (mio_pad_sleep_status_1_we),
24151 .wd (mio_pad_sleep_status_1_en_41_wd),
24152
24153 // from internal hardware
24154 .de (hw2reg.mio_pad_sleep_status[41].de),
24155 .d (hw2reg.mio_pad_sleep_status[41].d),
24156
24157 // to internal hardware
24158 .qe (),
24159 .q (reg2hw.mio_pad_sleep_status[41].q),
24160 .ds (),
24161
24162 // to register interface (read)
24163 .qs (mio_pad_sleep_status_1_en_41_qs)
24164 );
24165
24166 // F[en_42]: 10:10
24167 prim_subreg #(
24168 .DW (1),
24169 .SwAccess(prim_subreg_pkg::SwAccessW0C),
24170 .RESVAL (1'h0),
24171 .Mubi (1'b0)
24172 ) u_mio_pad_sleep_status_1_en_42 (
24173 .clk_i (clk_i),
24174 .rst_ni (rst_ni),
24175
24176 // from register interface
24177 .we (mio_pad_sleep_status_1_we),
24178 .wd (mio_pad_sleep_status_1_en_42_wd),
24179
24180 // from internal hardware
24181 .de (hw2reg.mio_pad_sleep_status[42].de),
24182 .d (hw2reg.mio_pad_sleep_status[42].d),
24183
24184 // to internal hardware
24185 .qe (),
24186 .q (reg2hw.mio_pad_sleep_status[42].q),
24187 .ds (),
24188
24189 // to register interface (read)
24190 .qs (mio_pad_sleep_status_1_en_42_qs)
24191 );
24192
24193 // F[en_43]: 11:11
24194 prim_subreg #(
24195 .DW (1),
24196 .SwAccess(prim_subreg_pkg::SwAccessW0C),
24197 .RESVAL (1'h0),
24198 .Mubi (1'b0)
24199 ) u_mio_pad_sleep_status_1_en_43 (
24200 .clk_i (clk_i),
24201 .rst_ni (rst_ni),
24202
24203 // from register interface
24204 .we (mio_pad_sleep_status_1_we),
24205 .wd (mio_pad_sleep_status_1_en_43_wd),
24206
24207 // from internal hardware
24208 .de (hw2reg.mio_pad_sleep_status[43].de),
24209 .d (hw2reg.mio_pad_sleep_status[43].d),
24210
24211 // to internal hardware
24212 .qe (),
24213 .q (reg2hw.mio_pad_sleep_status[43].q),
24214 .ds (),
24215
24216 // to register interface (read)
24217 .qs (mio_pad_sleep_status_1_en_43_qs)
24218 );
24219
24220 // F[en_44]: 12:12
24221 prim_subreg #(
24222 .DW (1),
24223 .SwAccess(prim_subreg_pkg::SwAccessW0C),
24224 .RESVAL (1'h0),
24225 .Mubi (1'b0)
24226 ) u_mio_pad_sleep_status_1_en_44 (
24227 .clk_i (clk_i),
24228 .rst_ni (rst_ni),
24229
24230 // from register interface
24231 .we (mio_pad_sleep_status_1_we),
24232 .wd (mio_pad_sleep_status_1_en_44_wd),
24233
24234 // from internal hardware
24235 .de (hw2reg.mio_pad_sleep_status[44].de),
24236 .d (hw2reg.mio_pad_sleep_status[44].d),
24237
24238 // to internal hardware
24239 .qe (),
24240 .q (reg2hw.mio_pad_sleep_status[44].q),
24241 .ds (),
24242
24243 // to register interface (read)
24244 .qs (mio_pad_sleep_status_1_en_44_qs)
24245 );
24246
24247 // F[en_45]: 13:13
24248 prim_subreg #(
24249 .DW (1),
24250 .SwAccess(prim_subreg_pkg::SwAccessW0C),
24251 .RESVAL (1'h0),
24252 .Mubi (1'b0)
24253 ) u_mio_pad_sleep_status_1_en_45 (
24254 .clk_i (clk_i),
24255 .rst_ni (rst_ni),
24256
24257 // from register interface
24258 .we (mio_pad_sleep_status_1_we),
24259 .wd (mio_pad_sleep_status_1_en_45_wd),
24260
24261 // from internal hardware
24262 .de (hw2reg.mio_pad_sleep_status[45].de),
24263 .d (hw2reg.mio_pad_sleep_status[45].d),
24264
24265 // to internal hardware
24266 .qe (),
24267 .q (reg2hw.mio_pad_sleep_status[45].q),
24268 .ds (),
24269
24270 // to register interface (read)
24271 .qs (mio_pad_sleep_status_1_en_45_qs)
24272 );
24273
24274 // F[en_46]: 14:14
24275 prim_subreg #(
24276 .DW (1),
24277 .SwAccess(prim_subreg_pkg::SwAccessW0C),
24278 .RESVAL (1'h0),
24279 .Mubi (1'b0)
24280 ) u_mio_pad_sleep_status_1_en_46 (
24281 .clk_i (clk_i),
24282 .rst_ni (rst_ni),
24283
24284 // from register interface
24285 .we (mio_pad_sleep_status_1_we),
24286 .wd (mio_pad_sleep_status_1_en_46_wd),
24287
24288 // from internal hardware
24289 .de (hw2reg.mio_pad_sleep_status[46].de),
24290 .d (hw2reg.mio_pad_sleep_status[46].d),
24291
24292 // to internal hardware
24293 .qe (),
24294 .q (reg2hw.mio_pad_sleep_status[46].q),
24295 .ds (),
24296
24297 // to register interface (read)
24298 .qs (mio_pad_sleep_status_1_en_46_qs)
24299 );
24300
24301
24302 // Subregister 0 of Multireg mio_pad_sleep_regwen
24303 // R[mio_pad_sleep_regwen_0]: V(False)
24304 prim_subreg #(
24305 .DW (1),
24306 .SwAccess(prim_subreg_pkg::SwAccessW0C),
24307 .RESVAL (1'h1),
24308 .Mubi (1'b0)
24309 ) u_mio_pad_sleep_regwen_0 (
24310 .clk_i (clk_i),
24311 .rst_ni (rst_ni),
24312
24313 // from register interface
24314 .we (mio_pad_sleep_regwen_0_we),
24315 .wd (mio_pad_sleep_regwen_0_wd),
24316
24317 // from internal hardware
24318 .de (1'b0),
24319 .d ('0),
24320
24321 // to internal hardware
24322 .qe (),
24323 .q (),
24324 .ds (),
24325
24326 // to register interface (read)
24327 .qs (mio_pad_sleep_regwen_0_qs)
24328 );
24329
24330
24331 // Subregister 1 of Multireg mio_pad_sleep_regwen
24332 // R[mio_pad_sleep_regwen_1]: V(False)
24333 prim_subreg #(
24334 .DW (1),
24335 .SwAccess(prim_subreg_pkg::SwAccessW0C),
24336 .RESVAL (1'h1),
24337 .Mubi (1'b0)
24338 ) u_mio_pad_sleep_regwen_1 (
24339 .clk_i (clk_i),
24340 .rst_ni (rst_ni),
24341
24342 // from register interface
24343 .we (mio_pad_sleep_regwen_1_we),
24344 .wd (mio_pad_sleep_regwen_1_wd),
24345
24346 // from internal hardware
24347 .de (1'b0),
24348 .d ('0),
24349
24350 // to internal hardware
24351 .qe (),
24352 .q (),
24353 .ds (),
24354
24355 // to register interface (read)
24356 .qs (mio_pad_sleep_regwen_1_qs)
24357 );
24358
24359
24360 // Subregister 2 of Multireg mio_pad_sleep_regwen
24361 // R[mio_pad_sleep_regwen_2]: V(False)
24362 prim_subreg #(
24363 .DW (1),
24364 .SwAccess(prim_subreg_pkg::SwAccessW0C),
24365 .RESVAL (1'h1),
24366 .Mubi (1'b0)
24367 ) u_mio_pad_sleep_regwen_2 (
24368 .clk_i (clk_i),
24369 .rst_ni (rst_ni),
24370
24371 // from register interface
24372 .we (mio_pad_sleep_regwen_2_we),
24373 .wd (mio_pad_sleep_regwen_2_wd),
24374
24375 // from internal hardware
24376 .de (1'b0),
24377 .d ('0),
24378
24379 // to internal hardware
24380 .qe (),
24381 .q (),
24382 .ds (),
24383
24384 // to register interface (read)
24385 .qs (mio_pad_sleep_regwen_2_qs)
24386 );
24387
24388
24389 // Subregister 3 of Multireg mio_pad_sleep_regwen
24390 // R[mio_pad_sleep_regwen_3]: V(False)
24391 prim_subreg #(
24392 .DW (1),
24393 .SwAccess(prim_subreg_pkg::SwAccessW0C),
24394 .RESVAL (1'h1),
24395 .Mubi (1'b0)
24396 ) u_mio_pad_sleep_regwen_3 (
24397 .clk_i (clk_i),
24398 .rst_ni (rst_ni),
24399
24400 // from register interface
24401 .we (mio_pad_sleep_regwen_3_we),
24402 .wd (mio_pad_sleep_regwen_3_wd),
24403
24404 // from internal hardware
24405 .de (1'b0),
24406 .d ('0),
24407
24408 // to internal hardware
24409 .qe (),
24410 .q (),
24411 .ds (),
24412
24413 // to register interface (read)
24414 .qs (mio_pad_sleep_regwen_3_qs)
24415 );
24416
24417
24418 // Subregister 4 of Multireg mio_pad_sleep_regwen
24419 // R[mio_pad_sleep_regwen_4]: V(False)
24420 prim_subreg #(
24421 .DW (1),
24422 .SwAccess(prim_subreg_pkg::SwAccessW0C),
24423 .RESVAL (1'h1),
24424 .Mubi (1'b0)
24425 ) u_mio_pad_sleep_regwen_4 (
24426 .clk_i (clk_i),
24427 .rst_ni (rst_ni),
24428
24429 // from register interface
24430 .we (mio_pad_sleep_regwen_4_we),
24431 .wd (mio_pad_sleep_regwen_4_wd),
24432
24433 // from internal hardware
24434 .de (1'b0),
24435 .d ('0),
24436
24437 // to internal hardware
24438 .qe (),
24439 .q (),
24440 .ds (),
24441
24442 // to register interface (read)
24443 .qs (mio_pad_sleep_regwen_4_qs)
24444 );
24445
24446
24447 // Subregister 5 of Multireg mio_pad_sleep_regwen
24448 // R[mio_pad_sleep_regwen_5]: V(False)
24449 prim_subreg #(
24450 .DW (1),
24451 .SwAccess(prim_subreg_pkg::SwAccessW0C),
24452 .RESVAL (1'h1),
24453 .Mubi (1'b0)
24454 ) u_mio_pad_sleep_regwen_5 (
24455 .clk_i (clk_i),
24456 .rst_ni (rst_ni),
24457
24458 // from register interface
24459 .we (mio_pad_sleep_regwen_5_we),
24460 .wd (mio_pad_sleep_regwen_5_wd),
24461
24462 // from internal hardware
24463 .de (1'b0),
24464 .d ('0),
24465
24466 // to internal hardware
24467 .qe (),
24468 .q (),
24469 .ds (),
24470
24471 // to register interface (read)
24472 .qs (mio_pad_sleep_regwen_5_qs)
24473 );
24474
24475
24476 // Subregister 6 of Multireg mio_pad_sleep_regwen
24477 // R[mio_pad_sleep_regwen_6]: V(False)
24478 prim_subreg #(
24479 .DW (1),
24480 .SwAccess(prim_subreg_pkg::SwAccessW0C),
24481 .RESVAL (1'h1),
24482 .Mubi (1'b0)
24483 ) u_mio_pad_sleep_regwen_6 (
24484 .clk_i (clk_i),
24485 .rst_ni (rst_ni),
24486
24487 // from register interface
24488 .we (mio_pad_sleep_regwen_6_we),
24489 .wd (mio_pad_sleep_regwen_6_wd),
24490
24491 // from internal hardware
24492 .de (1'b0),
24493 .d ('0),
24494
24495 // to internal hardware
24496 .qe (),
24497 .q (),
24498 .ds (),
24499
24500 // to register interface (read)
24501 .qs (mio_pad_sleep_regwen_6_qs)
24502 );
24503
24504
24505 // Subregister 7 of Multireg mio_pad_sleep_regwen
24506 // R[mio_pad_sleep_regwen_7]: V(False)
24507 prim_subreg #(
24508 .DW (1),
24509 .SwAccess(prim_subreg_pkg::SwAccessW0C),
24510 .RESVAL (1'h1),
24511 .Mubi (1'b0)
24512 ) u_mio_pad_sleep_regwen_7 (
24513 .clk_i (clk_i),
24514 .rst_ni (rst_ni),
24515
24516 // from register interface
24517 .we (mio_pad_sleep_regwen_7_we),
24518 .wd (mio_pad_sleep_regwen_7_wd),
24519
24520 // from internal hardware
24521 .de (1'b0),
24522 .d ('0),
24523
24524 // to internal hardware
24525 .qe (),
24526 .q (),
24527 .ds (),
24528
24529 // to register interface (read)
24530 .qs (mio_pad_sleep_regwen_7_qs)
24531 );
24532
24533
24534 // Subregister 8 of Multireg mio_pad_sleep_regwen
24535 // R[mio_pad_sleep_regwen_8]: V(False)
24536 prim_subreg #(
24537 .DW (1),
24538 .SwAccess(prim_subreg_pkg::SwAccessW0C),
24539 .RESVAL (1'h1),
24540 .Mubi (1'b0)
24541 ) u_mio_pad_sleep_regwen_8 (
24542 .clk_i (clk_i),
24543 .rst_ni (rst_ni),
24544
24545 // from register interface
24546 .we (mio_pad_sleep_regwen_8_we),
24547 .wd (mio_pad_sleep_regwen_8_wd),
24548
24549 // from internal hardware
24550 .de (1'b0),
24551 .d ('0),
24552
24553 // to internal hardware
24554 .qe (),
24555 .q (),
24556 .ds (),
24557
24558 // to register interface (read)
24559 .qs (mio_pad_sleep_regwen_8_qs)
24560 );
24561
24562
24563 // Subregister 9 of Multireg mio_pad_sleep_regwen
24564 // R[mio_pad_sleep_regwen_9]: V(False)
24565 prim_subreg #(
24566 .DW (1),
24567 .SwAccess(prim_subreg_pkg::SwAccessW0C),
24568 .RESVAL (1'h1),
24569 .Mubi (1'b0)
24570 ) u_mio_pad_sleep_regwen_9 (
24571 .clk_i (clk_i),
24572 .rst_ni (rst_ni),
24573
24574 // from register interface
24575 .we (mio_pad_sleep_regwen_9_we),
24576 .wd (mio_pad_sleep_regwen_9_wd),
24577
24578 // from internal hardware
24579 .de (1'b0),
24580 .d ('0),
24581
24582 // to internal hardware
24583 .qe (),
24584 .q (),
24585 .ds (),
24586
24587 // to register interface (read)
24588 .qs (mio_pad_sleep_regwen_9_qs)
24589 );
24590
24591
24592 // Subregister 10 of Multireg mio_pad_sleep_regwen
24593 // R[mio_pad_sleep_regwen_10]: V(False)
24594 prim_subreg #(
24595 .DW (1),
24596 .SwAccess(prim_subreg_pkg::SwAccessW0C),
24597 .RESVAL (1'h1),
24598 .Mubi (1'b0)
24599 ) u_mio_pad_sleep_regwen_10 (
24600 .clk_i (clk_i),
24601 .rst_ni (rst_ni),
24602
24603 // from register interface
24604 .we (mio_pad_sleep_regwen_10_we),
24605 .wd (mio_pad_sleep_regwen_10_wd),
24606
24607 // from internal hardware
24608 .de (1'b0),
24609 .d ('0),
24610
24611 // to internal hardware
24612 .qe (),
24613 .q (),
24614 .ds (),
24615
24616 // to register interface (read)
24617 .qs (mio_pad_sleep_regwen_10_qs)
24618 );
24619
24620
24621 // Subregister 11 of Multireg mio_pad_sleep_regwen
24622 // R[mio_pad_sleep_regwen_11]: V(False)
24623 prim_subreg #(
24624 .DW (1),
24625 .SwAccess(prim_subreg_pkg::SwAccessW0C),
24626 .RESVAL (1'h1),
24627 .Mubi (1'b0)
24628 ) u_mio_pad_sleep_regwen_11 (
24629 .clk_i (clk_i),
24630 .rst_ni (rst_ni),
24631
24632 // from register interface
24633 .we (mio_pad_sleep_regwen_11_we),
24634 .wd (mio_pad_sleep_regwen_11_wd),
24635
24636 // from internal hardware
24637 .de (1'b0),
24638 .d ('0),
24639
24640 // to internal hardware
24641 .qe (),
24642 .q (),
24643 .ds (),
24644
24645 // to register interface (read)
24646 .qs (mio_pad_sleep_regwen_11_qs)
24647 );
24648
24649
24650 // Subregister 12 of Multireg mio_pad_sleep_regwen
24651 // R[mio_pad_sleep_regwen_12]: V(False)
24652 prim_subreg #(
24653 .DW (1),
24654 .SwAccess(prim_subreg_pkg::SwAccessW0C),
24655 .RESVAL (1'h1),
24656 .Mubi (1'b0)
24657 ) u_mio_pad_sleep_regwen_12 (
24658 .clk_i (clk_i),
24659 .rst_ni (rst_ni),
24660
24661 // from register interface
24662 .we (mio_pad_sleep_regwen_12_we),
24663 .wd (mio_pad_sleep_regwen_12_wd),
24664
24665 // from internal hardware
24666 .de (1'b0),
24667 .d ('0),
24668
24669 // to internal hardware
24670 .qe (),
24671 .q (),
24672 .ds (),
24673
24674 // to register interface (read)
24675 .qs (mio_pad_sleep_regwen_12_qs)
24676 );
24677
24678
24679 // Subregister 13 of Multireg mio_pad_sleep_regwen
24680 // R[mio_pad_sleep_regwen_13]: V(False)
24681 prim_subreg #(
24682 .DW (1),
24683 .SwAccess(prim_subreg_pkg::SwAccessW0C),
24684 .RESVAL (1'h1),
24685 .Mubi (1'b0)
24686 ) u_mio_pad_sleep_regwen_13 (
24687 .clk_i (clk_i),
24688 .rst_ni (rst_ni),
24689
24690 // from register interface
24691 .we (mio_pad_sleep_regwen_13_we),
24692 .wd (mio_pad_sleep_regwen_13_wd),
24693
24694 // from internal hardware
24695 .de (1'b0),
24696 .d ('0),
24697
24698 // to internal hardware
24699 .qe (),
24700 .q (),
24701 .ds (),
24702
24703 // to register interface (read)
24704 .qs (mio_pad_sleep_regwen_13_qs)
24705 );
24706
24707
24708 // Subregister 14 of Multireg mio_pad_sleep_regwen
24709 // R[mio_pad_sleep_regwen_14]: V(False)
24710 prim_subreg #(
24711 .DW (1),
24712 .SwAccess(prim_subreg_pkg::SwAccessW0C),
24713 .RESVAL (1'h1),
24714 .Mubi (1'b0)
24715 ) u_mio_pad_sleep_regwen_14 (
24716 .clk_i (clk_i),
24717 .rst_ni (rst_ni),
24718
24719 // from register interface
24720 .we (mio_pad_sleep_regwen_14_we),
24721 .wd (mio_pad_sleep_regwen_14_wd),
24722
24723 // from internal hardware
24724 .de (1'b0),
24725 .d ('0),
24726
24727 // to internal hardware
24728 .qe (),
24729 .q (),
24730 .ds (),
24731
24732 // to register interface (read)
24733 .qs (mio_pad_sleep_regwen_14_qs)
24734 );
24735
24736
24737 // Subregister 15 of Multireg mio_pad_sleep_regwen
24738 // R[mio_pad_sleep_regwen_15]: V(False)
24739 prim_subreg #(
24740 .DW (1),
24741 .SwAccess(prim_subreg_pkg::SwAccessW0C),
24742 .RESVAL (1'h1),
24743 .Mubi (1'b0)
24744 ) u_mio_pad_sleep_regwen_15 (
24745 .clk_i (clk_i),
24746 .rst_ni (rst_ni),
24747
24748 // from register interface
24749 .we (mio_pad_sleep_regwen_15_we),
24750 .wd (mio_pad_sleep_regwen_15_wd),
24751
24752 // from internal hardware
24753 .de (1'b0),
24754 .d ('0),
24755
24756 // to internal hardware
24757 .qe (),
24758 .q (),
24759 .ds (),
24760
24761 // to register interface (read)
24762 .qs (mio_pad_sleep_regwen_15_qs)
24763 );
24764
24765
24766 // Subregister 16 of Multireg mio_pad_sleep_regwen
24767 // R[mio_pad_sleep_regwen_16]: V(False)
24768 prim_subreg #(
24769 .DW (1),
24770 .SwAccess(prim_subreg_pkg::SwAccessW0C),
24771 .RESVAL (1'h1),
24772 .Mubi (1'b0)
24773 ) u_mio_pad_sleep_regwen_16 (
24774 .clk_i (clk_i),
24775 .rst_ni (rst_ni),
24776
24777 // from register interface
24778 .we (mio_pad_sleep_regwen_16_we),
24779 .wd (mio_pad_sleep_regwen_16_wd),
24780
24781 // from internal hardware
24782 .de (1'b0),
24783 .d ('0),
24784
24785 // to internal hardware
24786 .qe (),
24787 .q (),
24788 .ds (),
24789
24790 // to register interface (read)
24791 .qs (mio_pad_sleep_regwen_16_qs)
24792 );
24793
24794
24795 // Subregister 17 of Multireg mio_pad_sleep_regwen
24796 // R[mio_pad_sleep_regwen_17]: V(False)
24797 prim_subreg #(
24798 .DW (1),
24799 .SwAccess(prim_subreg_pkg::SwAccessW0C),
24800 .RESVAL (1'h1),
24801 .Mubi (1'b0)
24802 ) u_mio_pad_sleep_regwen_17 (
24803 .clk_i (clk_i),
24804 .rst_ni (rst_ni),
24805
24806 // from register interface
24807 .we (mio_pad_sleep_regwen_17_we),
24808 .wd (mio_pad_sleep_regwen_17_wd),
24809
24810 // from internal hardware
24811 .de (1'b0),
24812 .d ('0),
24813
24814 // to internal hardware
24815 .qe (),
24816 .q (),
24817 .ds (),
24818
24819 // to register interface (read)
24820 .qs (mio_pad_sleep_regwen_17_qs)
24821 );
24822
24823
24824 // Subregister 18 of Multireg mio_pad_sleep_regwen
24825 // R[mio_pad_sleep_regwen_18]: V(False)
24826 prim_subreg #(
24827 .DW (1),
24828 .SwAccess(prim_subreg_pkg::SwAccessW0C),
24829 .RESVAL (1'h1),
24830 .Mubi (1'b0)
24831 ) u_mio_pad_sleep_regwen_18 (
24832 .clk_i (clk_i),
24833 .rst_ni (rst_ni),
24834
24835 // from register interface
24836 .we (mio_pad_sleep_regwen_18_we),
24837 .wd (mio_pad_sleep_regwen_18_wd),
24838
24839 // from internal hardware
24840 .de (1'b0),
24841 .d ('0),
24842
24843 // to internal hardware
24844 .qe (),
24845 .q (),
24846 .ds (),
24847
24848 // to register interface (read)
24849 .qs (mio_pad_sleep_regwen_18_qs)
24850 );
24851
24852
24853 // Subregister 19 of Multireg mio_pad_sleep_regwen
24854 // R[mio_pad_sleep_regwen_19]: V(False)
24855 prim_subreg #(
24856 .DW (1),
24857 .SwAccess(prim_subreg_pkg::SwAccessW0C),
24858 .RESVAL (1'h1),
24859 .Mubi (1'b0)
24860 ) u_mio_pad_sleep_regwen_19 (
24861 .clk_i (clk_i),
24862 .rst_ni (rst_ni),
24863
24864 // from register interface
24865 .we (mio_pad_sleep_regwen_19_we),
24866 .wd (mio_pad_sleep_regwen_19_wd),
24867
24868 // from internal hardware
24869 .de (1'b0),
24870 .d ('0),
24871
24872 // to internal hardware
24873 .qe (),
24874 .q (),
24875 .ds (),
24876
24877 // to register interface (read)
24878 .qs (mio_pad_sleep_regwen_19_qs)
24879 );
24880
24881
24882 // Subregister 20 of Multireg mio_pad_sleep_regwen
24883 // R[mio_pad_sleep_regwen_20]: V(False)
24884 prim_subreg #(
24885 .DW (1),
24886 .SwAccess(prim_subreg_pkg::SwAccessW0C),
24887 .RESVAL (1'h1),
24888 .Mubi (1'b0)
24889 ) u_mio_pad_sleep_regwen_20 (
24890 .clk_i (clk_i),
24891 .rst_ni (rst_ni),
24892
24893 // from register interface
24894 .we (mio_pad_sleep_regwen_20_we),
24895 .wd (mio_pad_sleep_regwen_20_wd),
24896
24897 // from internal hardware
24898 .de (1'b0),
24899 .d ('0),
24900
24901 // to internal hardware
24902 .qe (),
24903 .q (),
24904 .ds (),
24905
24906 // to register interface (read)
24907 .qs (mio_pad_sleep_regwen_20_qs)
24908 );
24909
24910
24911 // Subregister 21 of Multireg mio_pad_sleep_regwen
24912 // R[mio_pad_sleep_regwen_21]: V(False)
24913 prim_subreg #(
24914 .DW (1),
24915 .SwAccess(prim_subreg_pkg::SwAccessW0C),
24916 .RESVAL (1'h1),
24917 .Mubi (1'b0)
24918 ) u_mio_pad_sleep_regwen_21 (
24919 .clk_i (clk_i),
24920 .rst_ni (rst_ni),
24921
24922 // from register interface
24923 .we (mio_pad_sleep_regwen_21_we),
24924 .wd (mio_pad_sleep_regwen_21_wd),
24925
24926 // from internal hardware
24927 .de (1'b0),
24928 .d ('0),
24929
24930 // to internal hardware
24931 .qe (),
24932 .q (),
24933 .ds (),
24934
24935 // to register interface (read)
24936 .qs (mio_pad_sleep_regwen_21_qs)
24937 );
24938
24939
24940 // Subregister 22 of Multireg mio_pad_sleep_regwen
24941 // R[mio_pad_sleep_regwen_22]: V(False)
24942 prim_subreg #(
24943 .DW (1),
24944 .SwAccess(prim_subreg_pkg::SwAccessW0C),
24945 .RESVAL (1'h1),
24946 .Mubi (1'b0)
24947 ) u_mio_pad_sleep_regwen_22 (
24948 .clk_i (clk_i),
24949 .rst_ni (rst_ni),
24950
24951 // from register interface
24952 .we (mio_pad_sleep_regwen_22_we),
24953 .wd (mio_pad_sleep_regwen_22_wd),
24954
24955 // from internal hardware
24956 .de (1'b0),
24957 .d ('0),
24958
24959 // to internal hardware
24960 .qe (),
24961 .q (),
24962 .ds (),
24963
24964 // to register interface (read)
24965 .qs (mio_pad_sleep_regwen_22_qs)
24966 );
24967
24968
24969 // Subregister 23 of Multireg mio_pad_sleep_regwen
24970 // R[mio_pad_sleep_regwen_23]: V(False)
24971 prim_subreg #(
24972 .DW (1),
24973 .SwAccess(prim_subreg_pkg::SwAccessW0C),
24974 .RESVAL (1'h1),
24975 .Mubi (1'b0)
24976 ) u_mio_pad_sleep_regwen_23 (
24977 .clk_i (clk_i),
24978 .rst_ni (rst_ni),
24979
24980 // from register interface
24981 .we (mio_pad_sleep_regwen_23_we),
24982 .wd (mio_pad_sleep_regwen_23_wd),
24983
24984 // from internal hardware
24985 .de (1'b0),
24986 .d ('0),
24987
24988 // to internal hardware
24989 .qe (),
24990 .q (),
24991 .ds (),
24992
24993 // to register interface (read)
24994 .qs (mio_pad_sleep_regwen_23_qs)
24995 );
24996
24997
24998 // Subregister 24 of Multireg mio_pad_sleep_regwen
24999 // R[mio_pad_sleep_regwen_24]: V(False)
25000 prim_subreg #(
25001 .DW (1),
25002 .SwAccess(prim_subreg_pkg::SwAccessW0C),
25003 .RESVAL (1'h1),
25004 .Mubi (1'b0)
25005 ) u_mio_pad_sleep_regwen_24 (
25006 .clk_i (clk_i),
25007 .rst_ni (rst_ni),
25008
25009 // from register interface
25010 .we (mio_pad_sleep_regwen_24_we),
25011 .wd (mio_pad_sleep_regwen_24_wd),
25012
25013 // from internal hardware
25014 .de (1'b0),
25015 .d ('0),
25016
25017 // to internal hardware
25018 .qe (),
25019 .q (),
25020 .ds (),
25021
25022 // to register interface (read)
25023 .qs (mio_pad_sleep_regwen_24_qs)
25024 );
25025
25026
25027 // Subregister 25 of Multireg mio_pad_sleep_regwen
25028 // R[mio_pad_sleep_regwen_25]: V(False)
25029 prim_subreg #(
25030 .DW (1),
25031 .SwAccess(prim_subreg_pkg::SwAccessW0C),
25032 .RESVAL (1'h1),
25033 .Mubi (1'b0)
25034 ) u_mio_pad_sleep_regwen_25 (
25035 .clk_i (clk_i),
25036 .rst_ni (rst_ni),
25037
25038 // from register interface
25039 .we (mio_pad_sleep_regwen_25_we),
25040 .wd (mio_pad_sleep_regwen_25_wd),
25041
25042 // from internal hardware
25043 .de (1'b0),
25044 .d ('0),
25045
25046 // to internal hardware
25047 .qe (),
25048 .q (),
25049 .ds (),
25050
25051 // to register interface (read)
25052 .qs (mio_pad_sleep_regwen_25_qs)
25053 );
25054
25055
25056 // Subregister 26 of Multireg mio_pad_sleep_regwen
25057 // R[mio_pad_sleep_regwen_26]: V(False)
25058 prim_subreg #(
25059 .DW (1),
25060 .SwAccess(prim_subreg_pkg::SwAccessW0C),
25061 .RESVAL (1'h1),
25062 .Mubi (1'b0)
25063 ) u_mio_pad_sleep_regwen_26 (
25064 .clk_i (clk_i),
25065 .rst_ni (rst_ni),
25066
25067 // from register interface
25068 .we (mio_pad_sleep_regwen_26_we),
25069 .wd (mio_pad_sleep_regwen_26_wd),
25070
25071 // from internal hardware
25072 .de (1'b0),
25073 .d ('0),
25074
25075 // to internal hardware
25076 .qe (),
25077 .q (),
25078 .ds (),
25079
25080 // to register interface (read)
25081 .qs (mio_pad_sleep_regwen_26_qs)
25082 );
25083
25084
25085 // Subregister 27 of Multireg mio_pad_sleep_regwen
25086 // R[mio_pad_sleep_regwen_27]: V(False)
25087 prim_subreg #(
25088 .DW (1),
25089 .SwAccess(prim_subreg_pkg::SwAccessW0C),
25090 .RESVAL (1'h1),
25091 .Mubi (1'b0)
25092 ) u_mio_pad_sleep_regwen_27 (
25093 .clk_i (clk_i),
25094 .rst_ni (rst_ni),
25095
25096 // from register interface
25097 .we (mio_pad_sleep_regwen_27_we),
25098 .wd (mio_pad_sleep_regwen_27_wd),
25099
25100 // from internal hardware
25101 .de (1'b0),
25102 .d ('0),
25103
25104 // to internal hardware
25105 .qe (),
25106 .q (),
25107 .ds (),
25108
25109 // to register interface (read)
25110 .qs (mio_pad_sleep_regwen_27_qs)
25111 );
25112
25113
25114 // Subregister 28 of Multireg mio_pad_sleep_regwen
25115 // R[mio_pad_sleep_regwen_28]: V(False)
25116 prim_subreg #(
25117 .DW (1),
25118 .SwAccess(prim_subreg_pkg::SwAccessW0C),
25119 .RESVAL (1'h1),
25120 .Mubi (1'b0)
25121 ) u_mio_pad_sleep_regwen_28 (
25122 .clk_i (clk_i),
25123 .rst_ni (rst_ni),
25124
25125 // from register interface
25126 .we (mio_pad_sleep_regwen_28_we),
25127 .wd (mio_pad_sleep_regwen_28_wd),
25128
25129 // from internal hardware
25130 .de (1'b0),
25131 .d ('0),
25132
25133 // to internal hardware
25134 .qe (),
25135 .q (),
25136 .ds (),
25137
25138 // to register interface (read)
25139 .qs (mio_pad_sleep_regwen_28_qs)
25140 );
25141
25142
25143 // Subregister 29 of Multireg mio_pad_sleep_regwen
25144 // R[mio_pad_sleep_regwen_29]: V(False)
25145 prim_subreg #(
25146 .DW (1),
25147 .SwAccess(prim_subreg_pkg::SwAccessW0C),
25148 .RESVAL (1'h1),
25149 .Mubi (1'b0)
25150 ) u_mio_pad_sleep_regwen_29 (
25151 .clk_i (clk_i),
25152 .rst_ni (rst_ni),
25153
25154 // from register interface
25155 .we (mio_pad_sleep_regwen_29_we),
25156 .wd (mio_pad_sleep_regwen_29_wd),
25157
25158 // from internal hardware
25159 .de (1'b0),
25160 .d ('0),
25161
25162 // to internal hardware
25163 .qe (),
25164 .q (),
25165 .ds (),
25166
25167 // to register interface (read)
25168 .qs (mio_pad_sleep_regwen_29_qs)
25169 );
25170
25171
25172 // Subregister 30 of Multireg mio_pad_sleep_regwen
25173 // R[mio_pad_sleep_regwen_30]: V(False)
25174 prim_subreg #(
25175 .DW (1),
25176 .SwAccess(prim_subreg_pkg::SwAccessW0C),
25177 .RESVAL (1'h1),
25178 .Mubi (1'b0)
25179 ) u_mio_pad_sleep_regwen_30 (
25180 .clk_i (clk_i),
25181 .rst_ni (rst_ni),
25182
25183 // from register interface
25184 .we (mio_pad_sleep_regwen_30_we),
25185 .wd (mio_pad_sleep_regwen_30_wd),
25186
25187 // from internal hardware
25188 .de (1'b0),
25189 .d ('0),
25190
25191 // to internal hardware
25192 .qe (),
25193 .q (),
25194 .ds (),
25195
25196 // to register interface (read)
25197 .qs (mio_pad_sleep_regwen_30_qs)
25198 );
25199
25200
25201 // Subregister 31 of Multireg mio_pad_sleep_regwen
25202 // R[mio_pad_sleep_regwen_31]: V(False)
25203 prim_subreg #(
25204 .DW (1),
25205 .SwAccess(prim_subreg_pkg::SwAccessW0C),
25206 .RESVAL (1'h1),
25207 .Mubi (1'b0)
25208 ) u_mio_pad_sleep_regwen_31 (
25209 .clk_i (clk_i),
25210 .rst_ni (rst_ni),
25211
25212 // from register interface
25213 .we (mio_pad_sleep_regwen_31_we),
25214 .wd (mio_pad_sleep_regwen_31_wd),
25215
25216 // from internal hardware
25217 .de (1'b0),
25218 .d ('0),
25219
25220 // to internal hardware
25221 .qe (),
25222 .q (),
25223 .ds (),
25224
25225 // to register interface (read)
25226 .qs (mio_pad_sleep_regwen_31_qs)
25227 );
25228
25229
25230 // Subregister 32 of Multireg mio_pad_sleep_regwen
25231 // R[mio_pad_sleep_regwen_32]: V(False)
25232 prim_subreg #(
25233 .DW (1),
25234 .SwAccess(prim_subreg_pkg::SwAccessW0C),
25235 .RESVAL (1'h1),
25236 .Mubi (1'b0)
25237 ) u_mio_pad_sleep_regwen_32 (
25238 .clk_i (clk_i),
25239 .rst_ni (rst_ni),
25240
25241 // from register interface
25242 .we (mio_pad_sleep_regwen_32_we),
25243 .wd (mio_pad_sleep_regwen_32_wd),
25244
25245 // from internal hardware
25246 .de (1'b0),
25247 .d ('0),
25248
25249 // to internal hardware
25250 .qe (),
25251 .q (),
25252 .ds (),
25253
25254 // to register interface (read)
25255 .qs (mio_pad_sleep_regwen_32_qs)
25256 );
25257
25258
25259 // Subregister 33 of Multireg mio_pad_sleep_regwen
25260 // R[mio_pad_sleep_regwen_33]: V(False)
25261 prim_subreg #(
25262 .DW (1),
25263 .SwAccess(prim_subreg_pkg::SwAccessW0C),
25264 .RESVAL (1'h1),
25265 .Mubi (1'b0)
25266 ) u_mio_pad_sleep_regwen_33 (
25267 .clk_i (clk_i),
25268 .rst_ni (rst_ni),
25269
25270 // from register interface
25271 .we (mio_pad_sleep_regwen_33_we),
25272 .wd (mio_pad_sleep_regwen_33_wd),
25273
25274 // from internal hardware
25275 .de (1'b0),
25276 .d ('0),
25277
25278 // to internal hardware
25279 .qe (),
25280 .q (),
25281 .ds (),
25282
25283 // to register interface (read)
25284 .qs (mio_pad_sleep_regwen_33_qs)
25285 );
25286
25287
25288 // Subregister 34 of Multireg mio_pad_sleep_regwen
25289 // R[mio_pad_sleep_regwen_34]: V(False)
25290 prim_subreg #(
25291 .DW (1),
25292 .SwAccess(prim_subreg_pkg::SwAccessW0C),
25293 .RESVAL (1'h1),
25294 .Mubi (1'b0)
25295 ) u_mio_pad_sleep_regwen_34 (
25296 .clk_i (clk_i),
25297 .rst_ni (rst_ni),
25298
25299 // from register interface
25300 .we (mio_pad_sleep_regwen_34_we),
25301 .wd (mio_pad_sleep_regwen_34_wd),
25302
25303 // from internal hardware
25304 .de (1'b0),
25305 .d ('0),
25306
25307 // to internal hardware
25308 .qe (),
25309 .q (),
25310 .ds (),
25311
25312 // to register interface (read)
25313 .qs (mio_pad_sleep_regwen_34_qs)
25314 );
25315
25316
25317 // Subregister 35 of Multireg mio_pad_sleep_regwen
25318 // R[mio_pad_sleep_regwen_35]: V(False)
25319 prim_subreg #(
25320 .DW (1),
25321 .SwAccess(prim_subreg_pkg::SwAccessW0C),
25322 .RESVAL (1'h1),
25323 .Mubi (1'b0)
25324 ) u_mio_pad_sleep_regwen_35 (
25325 .clk_i (clk_i),
25326 .rst_ni (rst_ni),
25327
25328 // from register interface
25329 .we (mio_pad_sleep_regwen_35_we),
25330 .wd (mio_pad_sleep_regwen_35_wd),
25331
25332 // from internal hardware
25333 .de (1'b0),
25334 .d ('0),
25335
25336 // to internal hardware
25337 .qe (),
25338 .q (),
25339 .ds (),
25340
25341 // to register interface (read)
25342 .qs (mio_pad_sleep_regwen_35_qs)
25343 );
25344
25345
25346 // Subregister 36 of Multireg mio_pad_sleep_regwen
25347 // R[mio_pad_sleep_regwen_36]: V(False)
25348 prim_subreg #(
25349 .DW (1),
25350 .SwAccess(prim_subreg_pkg::SwAccessW0C),
25351 .RESVAL (1'h1),
25352 .Mubi (1'b0)
25353 ) u_mio_pad_sleep_regwen_36 (
25354 .clk_i (clk_i),
25355 .rst_ni (rst_ni),
25356
25357 // from register interface
25358 .we (mio_pad_sleep_regwen_36_we),
25359 .wd (mio_pad_sleep_regwen_36_wd),
25360
25361 // from internal hardware
25362 .de (1'b0),
25363 .d ('0),
25364
25365 // to internal hardware
25366 .qe (),
25367 .q (),
25368 .ds (),
25369
25370 // to register interface (read)
25371 .qs (mio_pad_sleep_regwen_36_qs)
25372 );
25373
25374
25375 // Subregister 37 of Multireg mio_pad_sleep_regwen
25376 // R[mio_pad_sleep_regwen_37]: V(False)
25377 prim_subreg #(
25378 .DW (1),
25379 .SwAccess(prim_subreg_pkg::SwAccessW0C),
25380 .RESVAL (1'h1),
25381 .Mubi (1'b0)
25382 ) u_mio_pad_sleep_regwen_37 (
25383 .clk_i (clk_i),
25384 .rst_ni (rst_ni),
25385
25386 // from register interface
25387 .we (mio_pad_sleep_regwen_37_we),
25388 .wd (mio_pad_sleep_regwen_37_wd),
25389
25390 // from internal hardware
25391 .de (1'b0),
25392 .d ('0),
25393
25394 // to internal hardware
25395 .qe (),
25396 .q (),
25397 .ds (),
25398
25399 // to register interface (read)
25400 .qs (mio_pad_sleep_regwen_37_qs)
25401 );
25402
25403
25404 // Subregister 38 of Multireg mio_pad_sleep_regwen
25405 // R[mio_pad_sleep_regwen_38]: V(False)
25406 prim_subreg #(
25407 .DW (1),
25408 .SwAccess(prim_subreg_pkg::SwAccessW0C),
25409 .RESVAL (1'h1),
25410 .Mubi (1'b0)
25411 ) u_mio_pad_sleep_regwen_38 (
25412 .clk_i (clk_i),
25413 .rst_ni (rst_ni),
25414
25415 // from register interface
25416 .we (mio_pad_sleep_regwen_38_we),
25417 .wd (mio_pad_sleep_regwen_38_wd),
25418
25419 // from internal hardware
25420 .de (1'b0),
25421 .d ('0),
25422
25423 // to internal hardware
25424 .qe (),
25425 .q (),
25426 .ds (),
25427
25428 // to register interface (read)
25429 .qs (mio_pad_sleep_regwen_38_qs)
25430 );
25431
25432
25433 // Subregister 39 of Multireg mio_pad_sleep_regwen
25434 // R[mio_pad_sleep_regwen_39]: V(False)
25435 prim_subreg #(
25436 .DW (1),
25437 .SwAccess(prim_subreg_pkg::SwAccessW0C),
25438 .RESVAL (1'h1),
25439 .Mubi (1'b0)
25440 ) u_mio_pad_sleep_regwen_39 (
25441 .clk_i (clk_i),
25442 .rst_ni (rst_ni),
25443
25444 // from register interface
25445 .we (mio_pad_sleep_regwen_39_we),
25446 .wd (mio_pad_sleep_regwen_39_wd),
25447
25448 // from internal hardware
25449 .de (1'b0),
25450 .d ('0),
25451
25452 // to internal hardware
25453 .qe (),
25454 .q (),
25455 .ds (),
25456
25457 // to register interface (read)
25458 .qs (mio_pad_sleep_regwen_39_qs)
25459 );
25460
25461
25462 // Subregister 40 of Multireg mio_pad_sleep_regwen
25463 // R[mio_pad_sleep_regwen_40]: V(False)
25464 prim_subreg #(
25465 .DW (1),
25466 .SwAccess(prim_subreg_pkg::SwAccessW0C),
25467 .RESVAL (1'h1),
25468 .Mubi (1'b0)
25469 ) u_mio_pad_sleep_regwen_40 (
25470 .clk_i (clk_i),
25471 .rst_ni (rst_ni),
25472
25473 // from register interface
25474 .we (mio_pad_sleep_regwen_40_we),
25475 .wd (mio_pad_sleep_regwen_40_wd),
25476
25477 // from internal hardware
25478 .de (1'b0),
25479 .d ('0),
25480
25481 // to internal hardware
25482 .qe (),
25483 .q (),
25484 .ds (),
25485
25486 // to register interface (read)
25487 .qs (mio_pad_sleep_regwen_40_qs)
25488 );
25489
25490
25491 // Subregister 41 of Multireg mio_pad_sleep_regwen
25492 // R[mio_pad_sleep_regwen_41]: V(False)
25493 prim_subreg #(
25494 .DW (1),
25495 .SwAccess(prim_subreg_pkg::SwAccessW0C),
25496 .RESVAL (1'h1),
25497 .Mubi (1'b0)
25498 ) u_mio_pad_sleep_regwen_41 (
25499 .clk_i (clk_i),
25500 .rst_ni (rst_ni),
25501
25502 // from register interface
25503 .we (mio_pad_sleep_regwen_41_we),
25504 .wd (mio_pad_sleep_regwen_41_wd),
25505
25506 // from internal hardware
25507 .de (1'b0),
25508 .d ('0),
25509
25510 // to internal hardware
25511 .qe (),
25512 .q (),
25513 .ds (),
25514
25515 // to register interface (read)
25516 .qs (mio_pad_sleep_regwen_41_qs)
25517 );
25518
25519
25520 // Subregister 42 of Multireg mio_pad_sleep_regwen
25521 // R[mio_pad_sleep_regwen_42]: V(False)
25522 prim_subreg #(
25523 .DW (1),
25524 .SwAccess(prim_subreg_pkg::SwAccessW0C),
25525 .RESVAL (1'h1),
25526 .Mubi (1'b0)
25527 ) u_mio_pad_sleep_regwen_42 (
25528 .clk_i (clk_i),
25529 .rst_ni (rst_ni),
25530
25531 // from register interface
25532 .we (mio_pad_sleep_regwen_42_we),
25533 .wd (mio_pad_sleep_regwen_42_wd),
25534
25535 // from internal hardware
25536 .de (1'b0),
25537 .d ('0),
25538
25539 // to internal hardware
25540 .qe (),
25541 .q (),
25542 .ds (),
25543
25544 // to register interface (read)
25545 .qs (mio_pad_sleep_regwen_42_qs)
25546 );
25547
25548
25549 // Subregister 43 of Multireg mio_pad_sleep_regwen
25550 // R[mio_pad_sleep_regwen_43]: V(False)
25551 prim_subreg #(
25552 .DW (1),
25553 .SwAccess(prim_subreg_pkg::SwAccessW0C),
25554 .RESVAL (1'h1),
25555 .Mubi (1'b0)
25556 ) u_mio_pad_sleep_regwen_43 (
25557 .clk_i (clk_i),
25558 .rst_ni (rst_ni),
25559
25560 // from register interface
25561 .we (mio_pad_sleep_regwen_43_we),
25562 .wd (mio_pad_sleep_regwen_43_wd),
25563
25564 // from internal hardware
25565 .de (1'b0),
25566 .d ('0),
25567
25568 // to internal hardware
25569 .qe (),
25570 .q (),
25571 .ds (),
25572
25573 // to register interface (read)
25574 .qs (mio_pad_sleep_regwen_43_qs)
25575 );
25576
25577
25578 // Subregister 44 of Multireg mio_pad_sleep_regwen
25579 // R[mio_pad_sleep_regwen_44]: V(False)
25580 prim_subreg #(
25581 .DW (1),
25582 .SwAccess(prim_subreg_pkg::SwAccessW0C),
25583 .RESVAL (1'h1),
25584 .Mubi (1'b0)
25585 ) u_mio_pad_sleep_regwen_44 (
25586 .clk_i (clk_i),
25587 .rst_ni (rst_ni),
25588
25589 // from register interface
25590 .we (mio_pad_sleep_regwen_44_we),
25591 .wd (mio_pad_sleep_regwen_44_wd),
25592
25593 // from internal hardware
25594 .de (1'b0),
25595 .d ('0),
25596
25597 // to internal hardware
25598 .qe (),
25599 .q (),
25600 .ds (),
25601
25602 // to register interface (read)
25603 .qs (mio_pad_sleep_regwen_44_qs)
25604 );
25605
25606
25607 // Subregister 45 of Multireg mio_pad_sleep_regwen
25608 // R[mio_pad_sleep_regwen_45]: V(False)
25609 prim_subreg #(
25610 .DW (1),
25611 .SwAccess(prim_subreg_pkg::SwAccessW0C),
25612 .RESVAL (1'h1),
25613 .Mubi (1'b0)
25614 ) u_mio_pad_sleep_regwen_45 (
25615 .clk_i (clk_i),
25616 .rst_ni (rst_ni),
25617
25618 // from register interface
25619 .we (mio_pad_sleep_regwen_45_we),
25620 .wd (mio_pad_sleep_regwen_45_wd),
25621
25622 // from internal hardware
25623 .de (1'b0),
25624 .d ('0),
25625
25626 // to internal hardware
25627 .qe (),
25628 .q (),
25629 .ds (),
25630
25631 // to register interface (read)
25632 .qs (mio_pad_sleep_regwen_45_qs)
25633 );
25634
25635
25636 // Subregister 46 of Multireg mio_pad_sleep_regwen
25637 // R[mio_pad_sleep_regwen_46]: V(False)
25638 prim_subreg #(
25639 .DW (1),
25640 .SwAccess(prim_subreg_pkg::SwAccessW0C),
25641 .RESVAL (1'h1),
25642 .Mubi (1'b0)
25643 ) u_mio_pad_sleep_regwen_46 (
25644 .clk_i (clk_i),
25645 .rst_ni (rst_ni),
25646
25647 // from register interface
25648 .we (mio_pad_sleep_regwen_46_we),
25649 .wd (mio_pad_sleep_regwen_46_wd),
25650
25651 // from internal hardware
25652 .de (1'b0),
25653 .d ('0),
25654
25655 // to internal hardware
25656 .qe (),
25657 .q (),
25658 .ds (),
25659
25660 // to register interface (read)
25661 .qs (mio_pad_sleep_regwen_46_qs)
25662 );
25663
25664
25665 // Subregister 0 of Multireg mio_pad_sleep_en
25666 // R[mio_pad_sleep_en_0]: V(False)
25667 // Create REGWEN-gated WE signal
25668 logic mio_pad_sleep_en_0_gated_we;
25669 1/1 assign mio_pad_sleep_en_0_gated_we = mio_pad_sleep_en_0_we & mio_pad_sleep_regwen_0_qs;
Tests: T2 T25 T19
25670 prim_subreg #(
25671 .DW (1),
25672 .SwAccess(prim_subreg_pkg::SwAccessRW),
25673 .RESVAL (1'h0),
25674 .Mubi (1'b0)
25675 ) u_mio_pad_sleep_en_0 (
25676 .clk_i (clk_i),
25677 .rst_ni (rst_ni),
25678
25679 // from register interface
25680 .we (mio_pad_sleep_en_0_gated_we),
25681 .wd (mio_pad_sleep_en_0_wd),
25682
25683 // from internal hardware
25684 .de (1'b0),
25685 .d ('0),
25686
25687 // to internal hardware
25688 .qe (),
25689 .q (reg2hw.mio_pad_sleep_en[0].q),
25690 .ds (),
25691
25692 // to register interface (read)
25693 .qs (mio_pad_sleep_en_0_qs)
25694 );
25695
25696
25697 // Subregister 1 of Multireg mio_pad_sleep_en
25698 // R[mio_pad_sleep_en_1]: V(False)
25699 // Create REGWEN-gated WE signal
25700 logic mio_pad_sleep_en_1_gated_we;
25701 1/1 assign mio_pad_sleep_en_1_gated_we = mio_pad_sleep_en_1_we & mio_pad_sleep_regwen_1_qs;
Tests: T2 T25 T19
25702 prim_subreg #(
25703 .DW (1),
25704 .SwAccess(prim_subreg_pkg::SwAccessRW),
25705 .RESVAL (1'h0),
25706 .Mubi (1'b0)
25707 ) u_mio_pad_sleep_en_1 (
25708 .clk_i (clk_i),
25709 .rst_ni (rst_ni),
25710
25711 // from register interface
25712 .we (mio_pad_sleep_en_1_gated_we),
25713 .wd (mio_pad_sleep_en_1_wd),
25714
25715 // from internal hardware
25716 .de (1'b0),
25717 .d ('0),
25718
25719 // to internal hardware
25720 .qe (),
25721 .q (reg2hw.mio_pad_sleep_en[1].q),
25722 .ds (),
25723
25724 // to register interface (read)
25725 .qs (mio_pad_sleep_en_1_qs)
25726 );
25727
25728
25729 // Subregister 2 of Multireg mio_pad_sleep_en
25730 // R[mio_pad_sleep_en_2]: V(False)
25731 // Create REGWEN-gated WE signal
25732 logic mio_pad_sleep_en_2_gated_we;
25733 1/1 assign mio_pad_sleep_en_2_gated_we = mio_pad_sleep_en_2_we & mio_pad_sleep_regwen_2_qs;
Tests: T2 T25 T19
25734 prim_subreg #(
25735 .DW (1),
25736 .SwAccess(prim_subreg_pkg::SwAccessRW),
25737 .RESVAL (1'h0),
25738 .Mubi (1'b0)
25739 ) u_mio_pad_sleep_en_2 (
25740 .clk_i (clk_i),
25741 .rst_ni (rst_ni),
25742
25743 // from register interface
25744 .we (mio_pad_sleep_en_2_gated_we),
25745 .wd (mio_pad_sleep_en_2_wd),
25746
25747 // from internal hardware
25748 .de (1'b0),
25749 .d ('0),
25750
25751 // to internal hardware
25752 .qe (),
25753 .q (reg2hw.mio_pad_sleep_en[2].q),
25754 .ds (),
25755
25756 // to register interface (read)
25757 .qs (mio_pad_sleep_en_2_qs)
25758 );
25759
25760
25761 // Subregister 3 of Multireg mio_pad_sleep_en
25762 // R[mio_pad_sleep_en_3]: V(False)
25763 // Create REGWEN-gated WE signal
25764 logic mio_pad_sleep_en_3_gated_we;
25765 1/1 assign mio_pad_sleep_en_3_gated_we = mio_pad_sleep_en_3_we & mio_pad_sleep_regwen_3_qs;
Tests: T2 T25 T19
25766 prim_subreg #(
25767 .DW (1),
25768 .SwAccess(prim_subreg_pkg::SwAccessRW),
25769 .RESVAL (1'h0),
25770 .Mubi (1'b0)
25771 ) u_mio_pad_sleep_en_3 (
25772 .clk_i (clk_i),
25773 .rst_ni (rst_ni),
25774
25775 // from register interface
25776 .we (mio_pad_sleep_en_3_gated_we),
25777 .wd (mio_pad_sleep_en_3_wd),
25778
25779 // from internal hardware
25780 .de (1'b0),
25781 .d ('0),
25782
25783 // to internal hardware
25784 .qe (),
25785 .q (reg2hw.mio_pad_sleep_en[3].q),
25786 .ds (),
25787
25788 // to register interface (read)
25789 .qs (mio_pad_sleep_en_3_qs)
25790 );
25791
25792
25793 // Subregister 4 of Multireg mio_pad_sleep_en
25794 // R[mio_pad_sleep_en_4]: V(False)
25795 // Create REGWEN-gated WE signal
25796 logic mio_pad_sleep_en_4_gated_we;
25797 1/1 assign mio_pad_sleep_en_4_gated_we = mio_pad_sleep_en_4_we & mio_pad_sleep_regwen_4_qs;
Tests: T2 T25 T19
25798 prim_subreg #(
25799 .DW (1),
25800 .SwAccess(prim_subreg_pkg::SwAccessRW),
25801 .RESVAL (1'h0),
25802 .Mubi (1'b0)
25803 ) u_mio_pad_sleep_en_4 (
25804 .clk_i (clk_i),
25805 .rst_ni (rst_ni),
25806
25807 // from register interface
25808 .we (mio_pad_sleep_en_4_gated_we),
25809 .wd (mio_pad_sleep_en_4_wd),
25810
25811 // from internal hardware
25812 .de (1'b0),
25813 .d ('0),
25814
25815 // to internal hardware
25816 .qe (),
25817 .q (reg2hw.mio_pad_sleep_en[4].q),
25818 .ds (),
25819
25820 // to register interface (read)
25821 .qs (mio_pad_sleep_en_4_qs)
25822 );
25823
25824
25825 // Subregister 5 of Multireg mio_pad_sleep_en
25826 // R[mio_pad_sleep_en_5]: V(False)
25827 // Create REGWEN-gated WE signal
25828 logic mio_pad_sleep_en_5_gated_we;
25829 1/1 assign mio_pad_sleep_en_5_gated_we = mio_pad_sleep_en_5_we & mio_pad_sleep_regwen_5_qs;
Tests: T2 T25 T19
25830 prim_subreg #(
25831 .DW (1),
25832 .SwAccess(prim_subreg_pkg::SwAccessRW),
25833 .RESVAL (1'h0),
25834 .Mubi (1'b0)
25835 ) u_mio_pad_sleep_en_5 (
25836 .clk_i (clk_i),
25837 .rst_ni (rst_ni),
25838
25839 // from register interface
25840 .we (mio_pad_sleep_en_5_gated_we),
25841 .wd (mio_pad_sleep_en_5_wd),
25842
25843 // from internal hardware
25844 .de (1'b0),
25845 .d ('0),
25846
25847 // to internal hardware
25848 .qe (),
25849 .q (reg2hw.mio_pad_sleep_en[5].q),
25850 .ds (),
25851
25852 // to register interface (read)
25853 .qs (mio_pad_sleep_en_5_qs)
25854 );
25855
25856
25857 // Subregister 6 of Multireg mio_pad_sleep_en
25858 // R[mio_pad_sleep_en_6]: V(False)
25859 // Create REGWEN-gated WE signal
25860 logic mio_pad_sleep_en_6_gated_we;
25861 1/1 assign mio_pad_sleep_en_6_gated_we = mio_pad_sleep_en_6_we & mio_pad_sleep_regwen_6_qs;
Tests: T2 T25 T19
25862 prim_subreg #(
25863 .DW (1),
25864 .SwAccess(prim_subreg_pkg::SwAccessRW),
25865 .RESVAL (1'h0),
25866 .Mubi (1'b0)
25867 ) u_mio_pad_sleep_en_6 (
25868 .clk_i (clk_i),
25869 .rst_ni (rst_ni),
25870
25871 // from register interface
25872 .we (mio_pad_sleep_en_6_gated_we),
25873 .wd (mio_pad_sleep_en_6_wd),
25874
25875 // from internal hardware
25876 .de (1'b0),
25877 .d ('0),
25878
25879 // to internal hardware
25880 .qe (),
25881 .q (reg2hw.mio_pad_sleep_en[6].q),
25882 .ds (),
25883
25884 // to register interface (read)
25885 .qs (mio_pad_sleep_en_6_qs)
25886 );
25887
25888
25889 // Subregister 7 of Multireg mio_pad_sleep_en
25890 // R[mio_pad_sleep_en_7]: V(False)
25891 // Create REGWEN-gated WE signal
25892 logic mio_pad_sleep_en_7_gated_we;
25893 1/1 assign mio_pad_sleep_en_7_gated_we = mio_pad_sleep_en_7_we & mio_pad_sleep_regwen_7_qs;
Tests: T2 T6 T25
25894 prim_subreg #(
25895 .DW (1),
25896 .SwAccess(prim_subreg_pkg::SwAccessRW),
25897 .RESVAL (1'h0),
25898 .Mubi (1'b0)
25899 ) u_mio_pad_sleep_en_7 (
25900 .clk_i (clk_i),
25901 .rst_ni (rst_ni),
25902
25903 // from register interface
25904 .we (mio_pad_sleep_en_7_gated_we),
25905 .wd (mio_pad_sleep_en_7_wd),
25906
25907 // from internal hardware
25908 .de (1'b0),
25909 .d ('0),
25910
25911 // to internal hardware
25912 .qe (),
25913 .q (reg2hw.mio_pad_sleep_en[7].q),
25914 .ds (),
25915
25916 // to register interface (read)
25917 .qs (mio_pad_sleep_en_7_qs)
25918 );
25919
25920
25921 // Subregister 8 of Multireg mio_pad_sleep_en
25922 // R[mio_pad_sleep_en_8]: V(False)
25923 // Create REGWEN-gated WE signal
25924 logic mio_pad_sleep_en_8_gated_we;
25925 1/1 assign mio_pad_sleep_en_8_gated_we = mio_pad_sleep_en_8_we & mio_pad_sleep_regwen_8_qs;
Tests: T2 T19 T40
25926 prim_subreg #(
25927 .DW (1),
25928 .SwAccess(prim_subreg_pkg::SwAccessRW),
25929 .RESVAL (1'h0),
25930 .Mubi (1'b0)
25931 ) u_mio_pad_sleep_en_8 (
25932 .clk_i (clk_i),
25933 .rst_ni (rst_ni),
25934
25935 // from register interface
25936 .we (mio_pad_sleep_en_8_gated_we),
25937 .wd (mio_pad_sleep_en_8_wd),
25938
25939 // from internal hardware
25940 .de (1'b0),
25941 .d ('0),
25942
25943 // to internal hardware
25944 .qe (),
25945 .q (reg2hw.mio_pad_sleep_en[8].q),
25946 .ds (),
25947
25948 // to register interface (read)
25949 .qs (mio_pad_sleep_en_8_qs)
25950 );
25951
25952
25953 // Subregister 9 of Multireg mio_pad_sleep_en
25954 // R[mio_pad_sleep_en_9]: V(False)
25955 // Create REGWEN-gated WE signal
25956 logic mio_pad_sleep_en_9_gated_we;
25957 1/1 assign mio_pad_sleep_en_9_gated_we = mio_pad_sleep_en_9_we & mio_pad_sleep_regwen_9_qs;
Tests: T2 T19 T40
25958 prim_subreg #(
25959 .DW (1),
25960 .SwAccess(prim_subreg_pkg::SwAccessRW),
25961 .RESVAL (1'h0),
25962 .Mubi (1'b0)
25963 ) u_mio_pad_sleep_en_9 (
25964 .clk_i (clk_i),
25965 .rst_ni (rst_ni),
25966
25967 // from register interface
25968 .we (mio_pad_sleep_en_9_gated_we),
25969 .wd (mio_pad_sleep_en_9_wd),
25970
25971 // from internal hardware
25972 .de (1'b0),
25973 .d ('0),
25974
25975 // to internal hardware
25976 .qe (),
25977 .q (reg2hw.mio_pad_sleep_en[9].q),
25978 .ds (),
25979
25980 // to register interface (read)
25981 .qs (mio_pad_sleep_en_9_qs)
25982 );
25983
25984
25985 // Subregister 10 of Multireg mio_pad_sleep_en
25986 // R[mio_pad_sleep_en_10]: V(False)
25987 // Create REGWEN-gated WE signal
25988 logic mio_pad_sleep_en_10_gated_we;
25989 1/1 assign mio_pad_sleep_en_10_gated_we = mio_pad_sleep_en_10_we & mio_pad_sleep_regwen_10_qs;
Tests: T2 T19 T40
25990 prim_subreg #(
25991 .DW (1),
25992 .SwAccess(prim_subreg_pkg::SwAccessRW),
25993 .RESVAL (1'h0),
25994 .Mubi (1'b0)
25995 ) u_mio_pad_sleep_en_10 (
25996 .clk_i (clk_i),
25997 .rst_ni (rst_ni),
25998
25999 // from register interface
26000 .we (mio_pad_sleep_en_10_gated_we),
26001 .wd (mio_pad_sleep_en_10_wd),
26002
26003 // from internal hardware
26004 .de (1'b0),
26005 .d ('0),
26006
26007 // to internal hardware
26008 .qe (),
26009 .q (reg2hw.mio_pad_sleep_en[10].q),
26010 .ds (),
26011
26012 // to register interface (read)
26013 .qs (mio_pad_sleep_en_10_qs)
26014 );
26015
26016
26017 // Subregister 11 of Multireg mio_pad_sleep_en
26018 // R[mio_pad_sleep_en_11]: V(False)
26019 // Create REGWEN-gated WE signal
26020 logic mio_pad_sleep_en_11_gated_we;
26021 1/1 assign mio_pad_sleep_en_11_gated_we = mio_pad_sleep_en_11_we & mio_pad_sleep_regwen_11_qs;
Tests: T2 T19 T40
26022 prim_subreg #(
26023 .DW (1),
26024 .SwAccess(prim_subreg_pkg::SwAccessRW),
26025 .RESVAL (1'h0),
26026 .Mubi (1'b0)
26027 ) u_mio_pad_sleep_en_11 (
26028 .clk_i (clk_i),
26029 .rst_ni (rst_ni),
26030
26031 // from register interface
26032 .we (mio_pad_sleep_en_11_gated_we),
26033 .wd (mio_pad_sleep_en_11_wd),
26034
26035 // from internal hardware
26036 .de (1'b0),
26037 .d ('0),
26038
26039 // to internal hardware
26040 .qe (),
26041 .q (reg2hw.mio_pad_sleep_en[11].q),
26042 .ds (),
26043
26044 // to register interface (read)
26045 .qs (mio_pad_sleep_en_11_qs)
26046 );
26047
26048
26049 // Subregister 12 of Multireg mio_pad_sleep_en
26050 // R[mio_pad_sleep_en_12]: V(False)
26051 // Create REGWEN-gated WE signal
26052 logic mio_pad_sleep_en_12_gated_we;
26053 1/1 assign mio_pad_sleep_en_12_gated_we = mio_pad_sleep_en_12_we & mio_pad_sleep_regwen_12_qs;
Tests: T2 T19 T40
26054 prim_subreg #(
26055 .DW (1),
26056 .SwAccess(prim_subreg_pkg::SwAccessRW),
26057 .RESVAL (1'h0),
26058 .Mubi (1'b0)
26059 ) u_mio_pad_sleep_en_12 (
26060 .clk_i (clk_i),
26061 .rst_ni (rst_ni),
26062
26063 // from register interface
26064 .we (mio_pad_sleep_en_12_gated_we),
26065 .wd (mio_pad_sleep_en_12_wd),
26066
26067 // from internal hardware
26068 .de (1'b0),
26069 .d ('0),
26070
26071 // to internal hardware
26072 .qe (),
26073 .q (reg2hw.mio_pad_sleep_en[12].q),
26074 .ds (),
26075
26076 // to register interface (read)
26077 .qs (mio_pad_sleep_en_12_qs)
26078 );
26079
26080
26081 // Subregister 13 of Multireg mio_pad_sleep_en
26082 // R[mio_pad_sleep_en_13]: V(False)
26083 // Create REGWEN-gated WE signal
26084 logic mio_pad_sleep_en_13_gated_we;
26085 1/1 assign mio_pad_sleep_en_13_gated_we = mio_pad_sleep_en_13_we & mio_pad_sleep_regwen_13_qs;
Tests: T2 T19 T40
26086 prim_subreg #(
26087 .DW (1),
26088 .SwAccess(prim_subreg_pkg::SwAccessRW),
26089 .RESVAL (1'h0),
26090 .Mubi (1'b0)
26091 ) u_mio_pad_sleep_en_13 (
26092 .clk_i (clk_i),
26093 .rst_ni (rst_ni),
26094
26095 // from register interface
26096 .we (mio_pad_sleep_en_13_gated_we),
26097 .wd (mio_pad_sleep_en_13_wd),
26098
26099 // from internal hardware
26100 .de (1'b0),
26101 .d ('0),
26102
26103 // to internal hardware
26104 .qe (),
26105 .q (reg2hw.mio_pad_sleep_en[13].q),
26106 .ds (),
26107
26108 // to register interface (read)
26109 .qs (mio_pad_sleep_en_13_qs)
26110 );
26111
26112
26113 // Subregister 14 of Multireg mio_pad_sleep_en
26114 // R[mio_pad_sleep_en_14]: V(False)
26115 // Create REGWEN-gated WE signal
26116 logic mio_pad_sleep_en_14_gated_we;
26117 1/1 assign mio_pad_sleep_en_14_gated_we = mio_pad_sleep_en_14_we & mio_pad_sleep_regwen_14_qs;
Tests: T2 T19 T40
26118 prim_subreg #(
26119 .DW (1),
26120 .SwAccess(prim_subreg_pkg::SwAccessRW),
26121 .RESVAL (1'h0),
26122 .Mubi (1'b0)
26123 ) u_mio_pad_sleep_en_14 (
26124 .clk_i (clk_i),
26125 .rst_ni (rst_ni),
26126
26127 // from register interface
26128 .we (mio_pad_sleep_en_14_gated_we),
26129 .wd (mio_pad_sleep_en_14_wd),
26130
26131 // from internal hardware
26132 .de (1'b0),
26133 .d ('0),
26134
26135 // to internal hardware
26136 .qe (),
26137 .q (reg2hw.mio_pad_sleep_en[14].q),
26138 .ds (),
26139
26140 // to register interface (read)
26141 .qs (mio_pad_sleep_en_14_qs)
26142 );
26143
26144
26145 // Subregister 15 of Multireg mio_pad_sleep_en
26146 // R[mio_pad_sleep_en_15]: V(False)
26147 // Create REGWEN-gated WE signal
26148 logic mio_pad_sleep_en_15_gated_we;
26149 1/1 assign mio_pad_sleep_en_15_gated_we = mio_pad_sleep_en_15_we & mio_pad_sleep_regwen_15_qs;
Tests: T2 T19 T40
26150 prim_subreg #(
26151 .DW (1),
26152 .SwAccess(prim_subreg_pkg::SwAccessRW),
26153 .RESVAL (1'h0),
26154 .Mubi (1'b0)
26155 ) u_mio_pad_sleep_en_15 (
26156 .clk_i (clk_i),
26157 .rst_ni (rst_ni),
26158
26159 // from register interface
26160 .we (mio_pad_sleep_en_15_gated_we),
26161 .wd (mio_pad_sleep_en_15_wd),
26162
26163 // from internal hardware
26164 .de (1'b0),
26165 .d ('0),
26166
26167 // to internal hardware
26168 .qe (),
26169 .q (reg2hw.mio_pad_sleep_en[15].q),
26170 .ds (),
26171
26172 // to register interface (read)
26173 .qs (mio_pad_sleep_en_15_qs)
26174 );
26175
26176
26177 // Subregister 16 of Multireg mio_pad_sleep_en
26178 // R[mio_pad_sleep_en_16]: V(False)
26179 // Create REGWEN-gated WE signal
26180 logic mio_pad_sleep_en_16_gated_we;
26181 1/1 assign mio_pad_sleep_en_16_gated_we = mio_pad_sleep_en_16_we & mio_pad_sleep_regwen_16_qs;
Tests: T2 T19 T40
26182 prim_subreg #(
26183 .DW (1),
26184 .SwAccess(prim_subreg_pkg::SwAccessRW),
26185 .RESVAL (1'h0),
26186 .Mubi (1'b0)
26187 ) u_mio_pad_sleep_en_16 (
26188 .clk_i (clk_i),
26189 .rst_ni (rst_ni),
26190
26191 // from register interface
26192 .we (mio_pad_sleep_en_16_gated_we),
26193 .wd (mio_pad_sleep_en_16_wd),
26194
26195 // from internal hardware
26196 .de (1'b0),
26197 .d ('0),
26198
26199 // to internal hardware
26200 .qe (),
26201 .q (reg2hw.mio_pad_sleep_en[16].q),
26202 .ds (),
26203
26204 // to register interface (read)
26205 .qs (mio_pad_sleep_en_16_qs)
26206 );
26207
26208
26209 // Subregister 17 of Multireg mio_pad_sleep_en
26210 // R[mio_pad_sleep_en_17]: V(False)
26211 // Create REGWEN-gated WE signal
26212 logic mio_pad_sleep_en_17_gated_we;
26213 1/1 assign mio_pad_sleep_en_17_gated_we = mio_pad_sleep_en_17_we & mio_pad_sleep_regwen_17_qs;
Tests: T2 T19 T40
26214 prim_subreg #(
26215 .DW (1),
26216 .SwAccess(prim_subreg_pkg::SwAccessRW),
26217 .RESVAL (1'h0),
26218 .Mubi (1'b0)
26219 ) u_mio_pad_sleep_en_17 (
26220 .clk_i (clk_i),
26221 .rst_ni (rst_ni),
26222
26223 // from register interface
26224 .we (mio_pad_sleep_en_17_gated_we),
26225 .wd (mio_pad_sleep_en_17_wd),
26226
26227 // from internal hardware
26228 .de (1'b0),
26229 .d ('0),
26230
26231 // to internal hardware
26232 .qe (),
26233 .q (reg2hw.mio_pad_sleep_en[17].q),
26234 .ds (),
26235
26236 // to register interface (read)
26237 .qs (mio_pad_sleep_en_17_qs)
26238 );
26239
26240
26241 // Subregister 18 of Multireg mio_pad_sleep_en
26242 // R[mio_pad_sleep_en_18]: V(False)
26243 // Create REGWEN-gated WE signal
26244 logic mio_pad_sleep_en_18_gated_we;
26245 1/1 assign mio_pad_sleep_en_18_gated_we = mio_pad_sleep_en_18_we & mio_pad_sleep_regwen_18_qs;
Tests: T2 T19 T40
26246 prim_subreg #(
26247 .DW (1),
26248 .SwAccess(prim_subreg_pkg::SwAccessRW),
26249 .RESVAL (1'h0),
26250 .Mubi (1'b0)
26251 ) u_mio_pad_sleep_en_18 (
26252 .clk_i (clk_i),
26253 .rst_ni (rst_ni),
26254
26255 // from register interface
26256 .we (mio_pad_sleep_en_18_gated_we),
26257 .wd (mio_pad_sleep_en_18_wd),
26258
26259 // from internal hardware
26260 .de (1'b0),
26261 .d ('0),
26262
26263 // to internal hardware
26264 .qe (),
26265 .q (reg2hw.mio_pad_sleep_en[18].q),
26266 .ds (),
26267
26268 // to register interface (read)
26269 .qs (mio_pad_sleep_en_18_qs)
26270 );
26271
26272
26273 // Subregister 19 of Multireg mio_pad_sleep_en
26274 // R[mio_pad_sleep_en_19]: V(False)
26275 // Create REGWEN-gated WE signal
26276 logic mio_pad_sleep_en_19_gated_we;
26277 1/1 assign mio_pad_sleep_en_19_gated_we = mio_pad_sleep_en_19_we & mio_pad_sleep_regwen_19_qs;
Tests: T2 T19 T40
26278 prim_subreg #(
26279 .DW (1),
26280 .SwAccess(prim_subreg_pkg::SwAccessRW),
26281 .RESVAL (1'h0),
26282 .Mubi (1'b0)
26283 ) u_mio_pad_sleep_en_19 (
26284 .clk_i (clk_i),
26285 .rst_ni (rst_ni),
26286
26287 // from register interface
26288 .we (mio_pad_sleep_en_19_gated_we),
26289 .wd (mio_pad_sleep_en_19_wd),
26290
26291 // from internal hardware
26292 .de (1'b0),
26293 .d ('0),
26294
26295 // to internal hardware
26296 .qe (),
26297 .q (reg2hw.mio_pad_sleep_en[19].q),
26298 .ds (),
26299
26300 // to register interface (read)
26301 .qs (mio_pad_sleep_en_19_qs)
26302 );
26303
26304
26305 // Subregister 20 of Multireg mio_pad_sleep_en
26306 // R[mio_pad_sleep_en_20]: V(False)
26307 // Create REGWEN-gated WE signal
26308 logic mio_pad_sleep_en_20_gated_we;
26309 1/1 assign mio_pad_sleep_en_20_gated_we = mio_pad_sleep_en_20_we & mio_pad_sleep_regwen_20_qs;
Tests: T2 T19 T40
26310 prim_subreg #(
26311 .DW (1),
26312 .SwAccess(prim_subreg_pkg::SwAccessRW),
26313 .RESVAL (1'h0),
26314 .Mubi (1'b0)
26315 ) u_mio_pad_sleep_en_20 (
26316 .clk_i (clk_i),
26317 .rst_ni (rst_ni),
26318
26319 // from register interface
26320 .we (mio_pad_sleep_en_20_gated_we),
26321 .wd (mio_pad_sleep_en_20_wd),
26322
26323 // from internal hardware
26324 .de (1'b0),
26325 .d ('0),
26326
26327 // to internal hardware
26328 .qe (),
26329 .q (reg2hw.mio_pad_sleep_en[20].q),
26330 .ds (),
26331
26332 // to register interface (read)
26333 .qs (mio_pad_sleep_en_20_qs)
26334 );
26335
26336
26337 // Subregister 21 of Multireg mio_pad_sleep_en
26338 // R[mio_pad_sleep_en_21]: V(False)
26339 // Create REGWEN-gated WE signal
26340 logic mio_pad_sleep_en_21_gated_we;
26341 1/1 assign mio_pad_sleep_en_21_gated_we = mio_pad_sleep_en_21_we & mio_pad_sleep_regwen_21_qs;
Tests: T2 T19 T40
26342 prim_subreg #(
26343 .DW (1),
26344 .SwAccess(prim_subreg_pkg::SwAccessRW),
26345 .RESVAL (1'h0),
26346 .Mubi (1'b0)
26347 ) u_mio_pad_sleep_en_21 (
26348 .clk_i (clk_i),
26349 .rst_ni (rst_ni),
26350
26351 // from register interface
26352 .we (mio_pad_sleep_en_21_gated_we),
26353 .wd (mio_pad_sleep_en_21_wd),
26354
26355 // from internal hardware
26356 .de (1'b0),
26357 .d ('0),
26358
26359 // to internal hardware
26360 .qe (),
26361 .q (reg2hw.mio_pad_sleep_en[21].q),
26362 .ds (),
26363
26364 // to register interface (read)
26365 .qs (mio_pad_sleep_en_21_qs)
26366 );
26367
26368
26369 // Subregister 22 of Multireg mio_pad_sleep_en
26370 // R[mio_pad_sleep_en_22]: V(False)
26371 // Create REGWEN-gated WE signal
26372 logic mio_pad_sleep_en_22_gated_we;
26373 1/1 assign mio_pad_sleep_en_22_gated_we = mio_pad_sleep_en_22_we & mio_pad_sleep_regwen_22_qs;
Tests: T2 T19 T40
26374 prim_subreg #(
26375 .DW (1),
26376 .SwAccess(prim_subreg_pkg::SwAccessRW),
26377 .RESVAL (1'h0),
26378 .Mubi (1'b0)
26379 ) u_mio_pad_sleep_en_22 (
26380 .clk_i (clk_i),
26381 .rst_ni (rst_ni),
26382
26383 // from register interface
26384 .we (mio_pad_sleep_en_22_gated_we),
26385 .wd (mio_pad_sleep_en_22_wd),
26386
26387 // from internal hardware
26388 .de (1'b0),
26389 .d ('0),
26390
26391 // to internal hardware
26392 .qe (),
26393 .q (reg2hw.mio_pad_sleep_en[22].q),
26394 .ds (),
26395
26396 // to register interface (read)
26397 .qs (mio_pad_sleep_en_22_qs)
26398 );
26399
26400
26401 // Subregister 23 of Multireg mio_pad_sleep_en
26402 // R[mio_pad_sleep_en_23]: V(False)
26403 // Create REGWEN-gated WE signal
26404 logic mio_pad_sleep_en_23_gated_we;
26405 1/1 assign mio_pad_sleep_en_23_gated_we = mio_pad_sleep_en_23_we & mio_pad_sleep_regwen_23_qs;
Tests: T2 T19 T40
26406 prim_subreg #(
26407 .DW (1),
26408 .SwAccess(prim_subreg_pkg::SwAccessRW),
26409 .RESVAL (1'h0),
26410 .Mubi (1'b0)
26411 ) u_mio_pad_sleep_en_23 (
26412 .clk_i (clk_i),
26413 .rst_ni (rst_ni),
26414
26415 // from register interface
26416 .we (mio_pad_sleep_en_23_gated_we),
26417 .wd (mio_pad_sleep_en_23_wd),
26418
26419 // from internal hardware
26420 .de (1'b0),
26421 .d ('0),
26422
26423 // to internal hardware
26424 .qe (),
26425 .q (reg2hw.mio_pad_sleep_en[23].q),
26426 .ds (),
26427
26428 // to register interface (read)
26429 .qs (mio_pad_sleep_en_23_qs)
26430 );
26431
26432
26433 // Subregister 24 of Multireg mio_pad_sleep_en
26434 // R[mio_pad_sleep_en_24]: V(False)
26435 // Create REGWEN-gated WE signal
26436 logic mio_pad_sleep_en_24_gated_we;
26437 1/1 assign mio_pad_sleep_en_24_gated_we = mio_pad_sleep_en_24_we & mio_pad_sleep_regwen_24_qs;
Tests: T2 T19 T40
26438 prim_subreg #(
26439 .DW (1),
26440 .SwAccess(prim_subreg_pkg::SwAccessRW),
26441 .RESVAL (1'h0),
26442 .Mubi (1'b0)
26443 ) u_mio_pad_sleep_en_24 (
26444 .clk_i (clk_i),
26445 .rst_ni (rst_ni),
26446
26447 // from register interface
26448 .we (mio_pad_sleep_en_24_gated_we),
26449 .wd (mio_pad_sleep_en_24_wd),
26450
26451 // from internal hardware
26452 .de (1'b0),
26453 .d ('0),
26454
26455 // to internal hardware
26456 .qe (),
26457 .q (reg2hw.mio_pad_sleep_en[24].q),
26458 .ds (),
26459
26460 // to register interface (read)
26461 .qs (mio_pad_sleep_en_24_qs)
26462 );
26463
26464
26465 // Subregister 25 of Multireg mio_pad_sleep_en
26466 // R[mio_pad_sleep_en_25]: V(False)
26467 // Create REGWEN-gated WE signal
26468 logic mio_pad_sleep_en_25_gated_we;
26469 1/1 assign mio_pad_sleep_en_25_gated_we = mio_pad_sleep_en_25_we & mio_pad_sleep_regwen_25_qs;
Tests: T2 T19 T40
26470 prim_subreg #(
26471 .DW (1),
26472 .SwAccess(prim_subreg_pkg::SwAccessRW),
26473 .RESVAL (1'h0),
26474 .Mubi (1'b0)
26475 ) u_mio_pad_sleep_en_25 (
26476 .clk_i (clk_i),
26477 .rst_ni (rst_ni),
26478
26479 // from register interface
26480 .we (mio_pad_sleep_en_25_gated_we),
26481 .wd (mio_pad_sleep_en_25_wd),
26482
26483 // from internal hardware
26484 .de (1'b0),
26485 .d ('0),
26486
26487 // to internal hardware
26488 .qe (),
26489 .q (reg2hw.mio_pad_sleep_en[25].q),
26490 .ds (),
26491
26492 // to register interface (read)
26493 .qs (mio_pad_sleep_en_25_qs)
26494 );
26495
26496
26497 // Subregister 26 of Multireg mio_pad_sleep_en
26498 // R[mio_pad_sleep_en_26]: V(False)
26499 // Create REGWEN-gated WE signal
26500 logic mio_pad_sleep_en_26_gated_we;
26501 1/1 assign mio_pad_sleep_en_26_gated_we = mio_pad_sleep_en_26_we & mio_pad_sleep_regwen_26_qs;
Tests: T2 T19 T40
26502 prim_subreg #(
26503 .DW (1),
26504 .SwAccess(prim_subreg_pkg::SwAccessRW),
26505 .RESVAL (1'h0),
26506 .Mubi (1'b0)
26507 ) u_mio_pad_sleep_en_26 (
26508 .clk_i (clk_i),
26509 .rst_ni (rst_ni),
26510
26511 // from register interface
26512 .we (mio_pad_sleep_en_26_gated_we),
26513 .wd (mio_pad_sleep_en_26_wd),
26514
26515 // from internal hardware
26516 .de (1'b0),
26517 .d ('0),
26518
26519 // to internal hardware
26520 .qe (),
26521 .q (reg2hw.mio_pad_sleep_en[26].q),
26522 .ds (),
26523
26524 // to register interface (read)
26525 .qs (mio_pad_sleep_en_26_qs)
26526 );
26527
26528
26529 // Subregister 27 of Multireg mio_pad_sleep_en
26530 // R[mio_pad_sleep_en_27]: V(False)
26531 // Create REGWEN-gated WE signal
26532 logic mio_pad_sleep_en_27_gated_we;
26533 1/1 assign mio_pad_sleep_en_27_gated_we = mio_pad_sleep_en_27_we & mio_pad_sleep_regwen_27_qs;
Tests: T2 T19 T40
26534 prim_subreg #(
26535 .DW (1),
26536 .SwAccess(prim_subreg_pkg::SwAccessRW),
26537 .RESVAL (1'h0),
26538 .Mubi (1'b0)
26539 ) u_mio_pad_sleep_en_27 (
26540 .clk_i (clk_i),
26541 .rst_ni (rst_ni),
26542
26543 // from register interface
26544 .we (mio_pad_sleep_en_27_gated_we),
26545 .wd (mio_pad_sleep_en_27_wd),
26546
26547 // from internal hardware
26548 .de (1'b0),
26549 .d ('0),
26550
26551 // to internal hardware
26552 .qe (),
26553 .q (reg2hw.mio_pad_sleep_en[27].q),
26554 .ds (),
26555
26556 // to register interface (read)
26557 .qs (mio_pad_sleep_en_27_qs)
26558 );
26559
26560
26561 // Subregister 28 of Multireg mio_pad_sleep_en
26562 // R[mio_pad_sleep_en_28]: V(False)
26563 // Create REGWEN-gated WE signal
26564 logic mio_pad_sleep_en_28_gated_we;
26565 1/1 assign mio_pad_sleep_en_28_gated_we = mio_pad_sleep_en_28_we & mio_pad_sleep_regwen_28_qs;
Tests: T2 T19 T40
26566 prim_subreg #(
26567 .DW (1),
26568 .SwAccess(prim_subreg_pkg::SwAccessRW),
26569 .RESVAL (1'h0),
26570 .Mubi (1'b0)
26571 ) u_mio_pad_sleep_en_28 (
26572 .clk_i (clk_i),
26573 .rst_ni (rst_ni),
26574
26575 // from register interface
26576 .we (mio_pad_sleep_en_28_gated_we),
26577 .wd (mio_pad_sleep_en_28_wd),
26578
26579 // from internal hardware
26580 .de (1'b0),
26581 .d ('0),
26582
26583 // to internal hardware
26584 .qe (),
26585 .q (reg2hw.mio_pad_sleep_en[28].q),
26586 .ds (),
26587
26588 // to register interface (read)
26589 .qs (mio_pad_sleep_en_28_qs)
26590 );
26591
26592
26593 // Subregister 29 of Multireg mio_pad_sleep_en
26594 // R[mio_pad_sleep_en_29]: V(False)
26595 // Create REGWEN-gated WE signal
26596 logic mio_pad_sleep_en_29_gated_we;
26597 1/1 assign mio_pad_sleep_en_29_gated_we = mio_pad_sleep_en_29_we & mio_pad_sleep_regwen_29_qs;
Tests: T2 T19 T40
26598 prim_subreg #(
26599 .DW (1),
26600 .SwAccess(prim_subreg_pkg::SwAccessRW),
26601 .RESVAL (1'h0),
26602 .Mubi (1'b0)
26603 ) u_mio_pad_sleep_en_29 (
26604 .clk_i (clk_i),
26605 .rst_ni (rst_ni),
26606
26607 // from register interface
26608 .we (mio_pad_sleep_en_29_gated_we),
26609 .wd (mio_pad_sleep_en_29_wd),
26610
26611 // from internal hardware
26612 .de (1'b0),
26613 .d ('0),
26614
26615 // to internal hardware
26616 .qe (),
26617 .q (reg2hw.mio_pad_sleep_en[29].q),
26618 .ds (),
26619
26620 // to register interface (read)
26621 .qs (mio_pad_sleep_en_29_qs)
26622 );
26623
26624
26625 // Subregister 30 of Multireg mio_pad_sleep_en
26626 // R[mio_pad_sleep_en_30]: V(False)
26627 // Create REGWEN-gated WE signal
26628 logic mio_pad_sleep_en_30_gated_we;
26629 1/1 assign mio_pad_sleep_en_30_gated_we = mio_pad_sleep_en_30_we & mio_pad_sleep_regwen_30_qs;
Tests: T2 T19 T40
26630 prim_subreg #(
26631 .DW (1),
26632 .SwAccess(prim_subreg_pkg::SwAccessRW),
26633 .RESVAL (1'h0),
26634 .Mubi (1'b0)
26635 ) u_mio_pad_sleep_en_30 (
26636 .clk_i (clk_i),
26637 .rst_ni (rst_ni),
26638
26639 // from register interface
26640 .we (mio_pad_sleep_en_30_gated_we),
26641 .wd (mio_pad_sleep_en_30_wd),
26642
26643 // from internal hardware
26644 .de (1'b0),
26645 .d ('0),
26646
26647 // to internal hardware
26648 .qe (),
26649 .q (reg2hw.mio_pad_sleep_en[30].q),
26650 .ds (),
26651
26652 // to register interface (read)
26653 .qs (mio_pad_sleep_en_30_qs)
26654 );
26655
26656
26657 // Subregister 31 of Multireg mio_pad_sleep_en
26658 // R[mio_pad_sleep_en_31]: V(False)
26659 // Create REGWEN-gated WE signal
26660 logic mio_pad_sleep_en_31_gated_we;
26661 1/1 assign mio_pad_sleep_en_31_gated_we = mio_pad_sleep_en_31_we & mio_pad_sleep_regwen_31_qs;
Tests: T2 T19 T40
26662 prim_subreg #(
26663 .DW (1),
26664 .SwAccess(prim_subreg_pkg::SwAccessRW),
26665 .RESVAL (1'h0),
26666 .Mubi (1'b0)
26667 ) u_mio_pad_sleep_en_31 (
26668 .clk_i (clk_i),
26669 .rst_ni (rst_ni),
26670
26671 // from register interface
26672 .we (mio_pad_sleep_en_31_gated_we),
26673 .wd (mio_pad_sleep_en_31_wd),
26674
26675 // from internal hardware
26676 .de (1'b0),
26677 .d ('0),
26678
26679 // to internal hardware
26680 .qe (),
26681 .q (reg2hw.mio_pad_sleep_en[31].q),
26682 .ds (),
26683
26684 // to register interface (read)
26685 .qs (mio_pad_sleep_en_31_qs)
26686 );
26687
26688
26689 // Subregister 32 of Multireg mio_pad_sleep_en
26690 // R[mio_pad_sleep_en_32]: V(False)
26691 // Create REGWEN-gated WE signal
26692 logic mio_pad_sleep_en_32_gated_we;
26693 1/1 assign mio_pad_sleep_en_32_gated_we = mio_pad_sleep_en_32_we & mio_pad_sleep_regwen_32_qs;
Tests: T2 T19 T40
26694 prim_subreg #(
26695 .DW (1),
26696 .SwAccess(prim_subreg_pkg::SwAccessRW),
26697 .RESVAL (1'h0),
26698 .Mubi (1'b0)
26699 ) u_mio_pad_sleep_en_32 (
26700 .clk_i (clk_i),
26701 .rst_ni (rst_ni),
26702
26703 // from register interface
26704 .we (mio_pad_sleep_en_32_gated_we),
26705 .wd (mio_pad_sleep_en_32_wd),
26706
26707 // from internal hardware
26708 .de (1'b0),
26709 .d ('0),
26710
26711 // to internal hardware
26712 .qe (),
26713 .q (reg2hw.mio_pad_sleep_en[32].q),
26714 .ds (),
26715
26716 // to register interface (read)
26717 .qs (mio_pad_sleep_en_32_qs)
26718 );
26719
26720
26721 // Subregister 33 of Multireg mio_pad_sleep_en
26722 // R[mio_pad_sleep_en_33]: V(False)
26723 // Create REGWEN-gated WE signal
26724 logic mio_pad_sleep_en_33_gated_we;
26725 1/1 assign mio_pad_sleep_en_33_gated_we = mio_pad_sleep_en_33_we & mio_pad_sleep_regwen_33_qs;
Tests: T2 T19 T40
26726 prim_subreg #(
26727 .DW (1),
26728 .SwAccess(prim_subreg_pkg::SwAccessRW),
26729 .RESVAL (1'h0),
26730 .Mubi (1'b0)
26731 ) u_mio_pad_sleep_en_33 (
26732 .clk_i (clk_i),
26733 .rst_ni (rst_ni),
26734
26735 // from register interface
26736 .we (mio_pad_sleep_en_33_gated_we),
26737 .wd (mio_pad_sleep_en_33_wd),
26738
26739 // from internal hardware
26740 .de (1'b0),
26741 .d ('0),
26742
26743 // to internal hardware
26744 .qe (),
26745 .q (reg2hw.mio_pad_sleep_en[33].q),
26746 .ds (),
26747
26748 // to register interface (read)
26749 .qs (mio_pad_sleep_en_33_qs)
26750 );
26751
26752
26753 // Subregister 34 of Multireg mio_pad_sleep_en
26754 // R[mio_pad_sleep_en_34]: V(False)
26755 // Create REGWEN-gated WE signal
26756 logic mio_pad_sleep_en_34_gated_we;
26757 1/1 assign mio_pad_sleep_en_34_gated_we = mio_pad_sleep_en_34_we & mio_pad_sleep_regwen_34_qs;
Tests: T2 T19 T40
26758 prim_subreg #(
26759 .DW (1),
26760 .SwAccess(prim_subreg_pkg::SwAccessRW),
26761 .RESVAL (1'h0),
26762 .Mubi (1'b0)
26763 ) u_mio_pad_sleep_en_34 (
26764 .clk_i (clk_i),
26765 .rst_ni (rst_ni),
26766
26767 // from register interface
26768 .we (mio_pad_sleep_en_34_gated_we),
26769 .wd (mio_pad_sleep_en_34_wd),
26770
26771 // from internal hardware
26772 .de (1'b0),
26773 .d ('0),
26774
26775 // to internal hardware
26776 .qe (),
26777 .q (reg2hw.mio_pad_sleep_en[34].q),
26778 .ds (),
26779
26780 // to register interface (read)
26781 .qs (mio_pad_sleep_en_34_qs)
26782 );
26783
26784
26785 // Subregister 35 of Multireg mio_pad_sleep_en
26786 // R[mio_pad_sleep_en_35]: V(False)
26787 // Create REGWEN-gated WE signal
26788 logic mio_pad_sleep_en_35_gated_we;
26789 1/1 assign mio_pad_sleep_en_35_gated_we = mio_pad_sleep_en_35_we & mio_pad_sleep_regwen_35_qs;
Tests: T2 T19 T40
26790 prim_subreg #(
26791 .DW (1),
26792 .SwAccess(prim_subreg_pkg::SwAccessRW),
26793 .RESVAL (1'h0),
26794 .Mubi (1'b0)
26795 ) u_mio_pad_sleep_en_35 (
26796 .clk_i (clk_i),
26797 .rst_ni (rst_ni),
26798
26799 // from register interface
26800 .we (mio_pad_sleep_en_35_gated_we),
26801 .wd (mio_pad_sleep_en_35_wd),
26802
26803 // from internal hardware
26804 .de (1'b0),
26805 .d ('0),
26806
26807 // to internal hardware
26808 .qe (),
26809 .q (reg2hw.mio_pad_sleep_en[35].q),
26810 .ds (),
26811
26812 // to register interface (read)
26813 .qs (mio_pad_sleep_en_35_qs)
26814 );
26815
26816
26817 // Subregister 36 of Multireg mio_pad_sleep_en
26818 // R[mio_pad_sleep_en_36]: V(False)
26819 // Create REGWEN-gated WE signal
26820 logic mio_pad_sleep_en_36_gated_we;
26821 1/1 assign mio_pad_sleep_en_36_gated_we = mio_pad_sleep_en_36_we & mio_pad_sleep_regwen_36_qs;
Tests: T2 T19 T40
26822 prim_subreg #(
26823 .DW (1),
26824 .SwAccess(prim_subreg_pkg::SwAccessRW),
26825 .RESVAL (1'h0),
26826 .Mubi (1'b0)
26827 ) u_mio_pad_sleep_en_36 (
26828 .clk_i (clk_i),
26829 .rst_ni (rst_ni),
26830
26831 // from register interface
26832 .we (mio_pad_sleep_en_36_gated_we),
26833 .wd (mio_pad_sleep_en_36_wd),
26834
26835 // from internal hardware
26836 .de (1'b0),
26837 .d ('0),
26838
26839 // to internal hardware
26840 .qe (),
26841 .q (reg2hw.mio_pad_sleep_en[36].q),
26842 .ds (),
26843
26844 // to register interface (read)
26845 .qs (mio_pad_sleep_en_36_qs)
26846 );
26847
26848
26849 // Subregister 37 of Multireg mio_pad_sleep_en
26850 // R[mio_pad_sleep_en_37]: V(False)
26851 // Create REGWEN-gated WE signal
26852 logic mio_pad_sleep_en_37_gated_we;
26853 1/1 assign mio_pad_sleep_en_37_gated_we = mio_pad_sleep_en_37_we & mio_pad_sleep_regwen_37_qs;
Tests: T2 T19 T40
26854 prim_subreg #(
26855 .DW (1),
26856 .SwAccess(prim_subreg_pkg::SwAccessRW),
26857 .RESVAL (1'h0),
26858 .Mubi (1'b0)
26859 ) u_mio_pad_sleep_en_37 (
26860 .clk_i (clk_i),
26861 .rst_ni (rst_ni),
26862
26863 // from register interface
26864 .we (mio_pad_sleep_en_37_gated_we),
26865 .wd (mio_pad_sleep_en_37_wd),
26866
26867 // from internal hardware
26868 .de (1'b0),
26869 .d ('0),
26870
26871 // to internal hardware
26872 .qe (),
26873 .q (reg2hw.mio_pad_sleep_en[37].q),
26874 .ds (),
26875
26876 // to register interface (read)
26877 .qs (mio_pad_sleep_en_37_qs)
26878 );
26879
26880
26881 // Subregister 38 of Multireg mio_pad_sleep_en
26882 // R[mio_pad_sleep_en_38]: V(False)
26883 // Create REGWEN-gated WE signal
26884 logic mio_pad_sleep_en_38_gated_we;
26885 1/1 assign mio_pad_sleep_en_38_gated_we = mio_pad_sleep_en_38_we & mio_pad_sleep_regwen_38_qs;
Tests: T2 T19 T40
26886 prim_subreg #(
26887 .DW (1),
26888 .SwAccess(prim_subreg_pkg::SwAccessRW),
26889 .RESVAL (1'h0),
26890 .Mubi (1'b0)
26891 ) u_mio_pad_sleep_en_38 (
26892 .clk_i (clk_i),
26893 .rst_ni (rst_ni),
26894
26895 // from register interface
26896 .we (mio_pad_sleep_en_38_gated_we),
26897 .wd (mio_pad_sleep_en_38_wd),
26898
26899 // from internal hardware
26900 .de (1'b0),
26901 .d ('0),
26902
26903 // to internal hardware
26904 .qe (),
26905 .q (reg2hw.mio_pad_sleep_en[38].q),
26906 .ds (),
26907
26908 // to register interface (read)
26909 .qs (mio_pad_sleep_en_38_qs)
26910 );
26911
26912
26913 // Subregister 39 of Multireg mio_pad_sleep_en
26914 // R[mio_pad_sleep_en_39]: V(False)
26915 // Create REGWEN-gated WE signal
26916 logic mio_pad_sleep_en_39_gated_we;
26917 1/1 assign mio_pad_sleep_en_39_gated_we = mio_pad_sleep_en_39_we & mio_pad_sleep_regwen_39_qs;
Tests: T2 T19 T40
26918 prim_subreg #(
26919 .DW (1),
26920 .SwAccess(prim_subreg_pkg::SwAccessRW),
26921 .RESVAL (1'h0),
26922 .Mubi (1'b0)
26923 ) u_mio_pad_sleep_en_39 (
26924 .clk_i (clk_i),
26925 .rst_ni (rst_ni),
26926
26927 // from register interface
26928 .we (mio_pad_sleep_en_39_gated_we),
26929 .wd (mio_pad_sleep_en_39_wd),
26930
26931 // from internal hardware
26932 .de (1'b0),
26933 .d ('0),
26934
26935 // to internal hardware
26936 .qe (),
26937 .q (reg2hw.mio_pad_sleep_en[39].q),
26938 .ds (),
26939
26940 // to register interface (read)
26941 .qs (mio_pad_sleep_en_39_qs)
26942 );
26943
26944
26945 // Subregister 40 of Multireg mio_pad_sleep_en
26946 // R[mio_pad_sleep_en_40]: V(False)
26947 // Create REGWEN-gated WE signal
26948 logic mio_pad_sleep_en_40_gated_we;
26949 1/1 assign mio_pad_sleep_en_40_gated_we = mio_pad_sleep_en_40_we & mio_pad_sleep_regwen_40_qs;
Tests: T2 T19 T40
26950 prim_subreg #(
26951 .DW (1),
26952 .SwAccess(prim_subreg_pkg::SwAccessRW),
26953 .RESVAL (1'h0),
26954 .Mubi (1'b0)
26955 ) u_mio_pad_sleep_en_40 (
26956 .clk_i (clk_i),
26957 .rst_ni (rst_ni),
26958
26959 // from register interface
26960 .we (mio_pad_sleep_en_40_gated_we),
26961 .wd (mio_pad_sleep_en_40_wd),
26962
26963 // from internal hardware
26964 .de (1'b0),
26965 .d ('0),
26966
26967 // to internal hardware
26968 .qe (),
26969 .q (reg2hw.mio_pad_sleep_en[40].q),
26970 .ds (),
26971
26972 // to register interface (read)
26973 .qs (mio_pad_sleep_en_40_qs)
26974 );
26975
26976
26977 // Subregister 41 of Multireg mio_pad_sleep_en
26978 // R[mio_pad_sleep_en_41]: V(False)
26979 // Create REGWEN-gated WE signal
26980 logic mio_pad_sleep_en_41_gated_we;
26981 1/1 assign mio_pad_sleep_en_41_gated_we = mio_pad_sleep_en_41_we & mio_pad_sleep_regwen_41_qs;
Tests: T2 T19 T40
26982 prim_subreg #(
26983 .DW (1),
26984 .SwAccess(prim_subreg_pkg::SwAccessRW),
26985 .RESVAL (1'h0),
26986 .Mubi (1'b0)
26987 ) u_mio_pad_sleep_en_41 (
26988 .clk_i (clk_i),
26989 .rst_ni (rst_ni),
26990
26991 // from register interface
26992 .we (mio_pad_sleep_en_41_gated_we),
26993 .wd (mio_pad_sleep_en_41_wd),
26994
26995 // from internal hardware
26996 .de (1'b0),
26997 .d ('0),
26998
26999 // to internal hardware
27000 .qe (),
27001 .q (reg2hw.mio_pad_sleep_en[41].q),
27002 .ds (),
27003
27004 // to register interface (read)
27005 .qs (mio_pad_sleep_en_41_qs)
27006 );
27007
27008
27009 // Subregister 42 of Multireg mio_pad_sleep_en
27010 // R[mio_pad_sleep_en_42]: V(False)
27011 // Create REGWEN-gated WE signal
27012 logic mio_pad_sleep_en_42_gated_we;
27013 1/1 assign mio_pad_sleep_en_42_gated_we = mio_pad_sleep_en_42_we & mio_pad_sleep_regwen_42_qs;
Tests: T2 T19 T40
27014 prim_subreg #(
27015 .DW (1),
27016 .SwAccess(prim_subreg_pkg::SwAccessRW),
27017 .RESVAL (1'h0),
27018 .Mubi (1'b0)
27019 ) u_mio_pad_sleep_en_42 (
27020 .clk_i (clk_i),
27021 .rst_ni (rst_ni),
27022
27023 // from register interface
27024 .we (mio_pad_sleep_en_42_gated_we),
27025 .wd (mio_pad_sleep_en_42_wd),
27026
27027 // from internal hardware
27028 .de (1'b0),
27029 .d ('0),
27030
27031 // to internal hardware
27032 .qe (),
27033 .q (reg2hw.mio_pad_sleep_en[42].q),
27034 .ds (),
27035
27036 // to register interface (read)
27037 .qs (mio_pad_sleep_en_42_qs)
27038 );
27039
27040
27041 // Subregister 43 of Multireg mio_pad_sleep_en
27042 // R[mio_pad_sleep_en_43]: V(False)
27043 // Create REGWEN-gated WE signal
27044 logic mio_pad_sleep_en_43_gated_we;
27045 1/1 assign mio_pad_sleep_en_43_gated_we = mio_pad_sleep_en_43_we & mio_pad_sleep_regwen_43_qs;
Tests: T2 T19 T40
27046 prim_subreg #(
27047 .DW (1),
27048 .SwAccess(prim_subreg_pkg::SwAccessRW),
27049 .RESVAL (1'h0),
27050 .Mubi (1'b0)
27051 ) u_mio_pad_sleep_en_43 (
27052 .clk_i (clk_i),
27053 .rst_ni (rst_ni),
27054
27055 // from register interface
27056 .we (mio_pad_sleep_en_43_gated_we),
27057 .wd (mio_pad_sleep_en_43_wd),
27058
27059 // from internal hardware
27060 .de (1'b0),
27061 .d ('0),
27062
27063 // to internal hardware
27064 .qe (),
27065 .q (reg2hw.mio_pad_sleep_en[43].q),
27066 .ds (),
27067
27068 // to register interface (read)
27069 .qs (mio_pad_sleep_en_43_qs)
27070 );
27071
27072
27073 // Subregister 44 of Multireg mio_pad_sleep_en
27074 // R[mio_pad_sleep_en_44]: V(False)
27075 // Create REGWEN-gated WE signal
27076 logic mio_pad_sleep_en_44_gated_we;
27077 1/1 assign mio_pad_sleep_en_44_gated_we = mio_pad_sleep_en_44_we & mio_pad_sleep_regwen_44_qs;
Tests: T2 T19 T40
27078 prim_subreg #(
27079 .DW (1),
27080 .SwAccess(prim_subreg_pkg::SwAccessRW),
27081 .RESVAL (1'h0),
27082 .Mubi (1'b0)
27083 ) u_mio_pad_sleep_en_44 (
27084 .clk_i (clk_i),
27085 .rst_ni (rst_ni),
27086
27087 // from register interface
27088 .we (mio_pad_sleep_en_44_gated_we),
27089 .wd (mio_pad_sleep_en_44_wd),
27090
27091 // from internal hardware
27092 .de (1'b0),
27093 .d ('0),
27094
27095 // to internal hardware
27096 .qe (),
27097 .q (reg2hw.mio_pad_sleep_en[44].q),
27098 .ds (),
27099
27100 // to register interface (read)
27101 .qs (mio_pad_sleep_en_44_qs)
27102 );
27103
27104
27105 // Subregister 45 of Multireg mio_pad_sleep_en
27106 // R[mio_pad_sleep_en_45]: V(False)
27107 // Create REGWEN-gated WE signal
27108 logic mio_pad_sleep_en_45_gated_we;
27109 1/1 assign mio_pad_sleep_en_45_gated_we = mio_pad_sleep_en_45_we & mio_pad_sleep_regwen_45_qs;
Tests: T2 T19 T40
27110 prim_subreg #(
27111 .DW (1),
27112 .SwAccess(prim_subreg_pkg::SwAccessRW),
27113 .RESVAL (1'h0),
27114 .Mubi (1'b0)
27115 ) u_mio_pad_sleep_en_45 (
27116 .clk_i (clk_i),
27117 .rst_ni (rst_ni),
27118
27119 // from register interface
27120 .we (mio_pad_sleep_en_45_gated_we),
27121 .wd (mio_pad_sleep_en_45_wd),
27122
27123 // from internal hardware
27124 .de (1'b0),
27125 .d ('0),
27126
27127 // to internal hardware
27128 .qe (),
27129 .q (reg2hw.mio_pad_sleep_en[45].q),
27130 .ds (),
27131
27132 // to register interface (read)
27133 .qs (mio_pad_sleep_en_45_qs)
27134 );
27135
27136
27137 // Subregister 46 of Multireg mio_pad_sleep_en
27138 // R[mio_pad_sleep_en_46]: V(False)
27139 // Create REGWEN-gated WE signal
27140 logic mio_pad_sleep_en_46_gated_we;
27141 1/1 assign mio_pad_sleep_en_46_gated_we = mio_pad_sleep_en_46_we & mio_pad_sleep_regwen_46_qs;
Tests: T2 T19 T40
27142 prim_subreg #(
27143 .DW (1),
27144 .SwAccess(prim_subreg_pkg::SwAccessRW),
27145 .RESVAL (1'h0),
27146 .Mubi (1'b0)
27147 ) u_mio_pad_sleep_en_46 (
27148 .clk_i (clk_i),
27149 .rst_ni (rst_ni),
27150
27151 // from register interface
27152 .we (mio_pad_sleep_en_46_gated_we),
27153 .wd (mio_pad_sleep_en_46_wd),
27154
27155 // from internal hardware
27156 .de (1'b0),
27157 .d ('0),
27158
27159 // to internal hardware
27160 .qe (),
27161 .q (reg2hw.mio_pad_sleep_en[46].q),
27162 .ds (),
27163
27164 // to register interface (read)
27165 .qs (mio_pad_sleep_en_46_qs)
27166 );
27167
27168
27169 // Subregister 0 of Multireg mio_pad_sleep_mode
27170 // R[mio_pad_sleep_mode_0]: V(False)
27171 // Create REGWEN-gated WE signal
27172 logic mio_pad_sleep_mode_0_gated_we;
27173 1/1 assign mio_pad_sleep_mode_0_gated_we = mio_pad_sleep_mode_0_we & mio_pad_sleep_regwen_0_qs;
Tests: T2 T25 T19
27174 prim_subreg #(
27175 .DW (2),
27176 .SwAccess(prim_subreg_pkg::SwAccessRW),
27177 .RESVAL (2'h2),
27178 .Mubi (1'b0)
27179 ) u_mio_pad_sleep_mode_0 (
27180 .clk_i (clk_i),
27181 .rst_ni (rst_ni),
27182
27183 // from register interface
27184 .we (mio_pad_sleep_mode_0_gated_we),
27185 .wd (mio_pad_sleep_mode_0_wd),
27186
27187 // from internal hardware
27188 .de (1'b0),
27189 .d ('0),
27190
27191 // to internal hardware
27192 .qe (),
27193 .q (reg2hw.mio_pad_sleep_mode[0].q),
27194 .ds (),
27195
27196 // to register interface (read)
27197 .qs (mio_pad_sleep_mode_0_qs)
27198 );
27199
27200
27201 // Subregister 1 of Multireg mio_pad_sleep_mode
27202 // R[mio_pad_sleep_mode_1]: V(False)
27203 // Create REGWEN-gated WE signal
27204 logic mio_pad_sleep_mode_1_gated_we;
27205 1/1 assign mio_pad_sleep_mode_1_gated_we = mio_pad_sleep_mode_1_we & mio_pad_sleep_regwen_1_qs;
Tests: T2 T25 T19
27206 prim_subreg #(
27207 .DW (2),
27208 .SwAccess(prim_subreg_pkg::SwAccessRW),
27209 .RESVAL (2'h2),
27210 .Mubi (1'b0)
27211 ) u_mio_pad_sleep_mode_1 (
27212 .clk_i (clk_i),
27213 .rst_ni (rst_ni),
27214
27215 // from register interface
27216 .we (mio_pad_sleep_mode_1_gated_we),
27217 .wd (mio_pad_sleep_mode_1_wd),
27218
27219 // from internal hardware
27220 .de (1'b0),
27221 .d ('0),
27222
27223 // to internal hardware
27224 .qe (),
27225 .q (reg2hw.mio_pad_sleep_mode[1].q),
27226 .ds (),
27227
27228 // to register interface (read)
27229 .qs (mio_pad_sleep_mode_1_qs)
27230 );
27231
27232
27233 // Subregister 2 of Multireg mio_pad_sleep_mode
27234 // R[mio_pad_sleep_mode_2]: V(False)
27235 // Create REGWEN-gated WE signal
27236 logic mio_pad_sleep_mode_2_gated_we;
27237 1/1 assign mio_pad_sleep_mode_2_gated_we = mio_pad_sleep_mode_2_we & mio_pad_sleep_regwen_2_qs;
Tests: T2 T25 T19
27238 prim_subreg #(
27239 .DW (2),
27240 .SwAccess(prim_subreg_pkg::SwAccessRW),
27241 .RESVAL (2'h2),
27242 .Mubi (1'b0)
27243 ) u_mio_pad_sleep_mode_2 (
27244 .clk_i (clk_i),
27245 .rst_ni (rst_ni),
27246
27247 // from register interface
27248 .we (mio_pad_sleep_mode_2_gated_we),
27249 .wd (mio_pad_sleep_mode_2_wd),
27250
27251 // from internal hardware
27252 .de (1'b0),
27253 .d ('0),
27254
27255 // to internal hardware
27256 .qe (),
27257 .q (reg2hw.mio_pad_sleep_mode[2].q),
27258 .ds (),
27259
27260 // to register interface (read)
27261 .qs (mio_pad_sleep_mode_2_qs)
27262 );
27263
27264
27265 // Subregister 3 of Multireg mio_pad_sleep_mode
27266 // R[mio_pad_sleep_mode_3]: V(False)
27267 // Create REGWEN-gated WE signal
27268 logic mio_pad_sleep_mode_3_gated_we;
27269 1/1 assign mio_pad_sleep_mode_3_gated_we = mio_pad_sleep_mode_3_we & mio_pad_sleep_regwen_3_qs;
Tests: T2 T25 T19
27270 prim_subreg #(
27271 .DW (2),
27272 .SwAccess(prim_subreg_pkg::SwAccessRW),
27273 .RESVAL (2'h2),
27274 .Mubi (1'b0)
27275 ) u_mio_pad_sleep_mode_3 (
27276 .clk_i (clk_i),
27277 .rst_ni (rst_ni),
27278
27279 // from register interface
27280 .we (mio_pad_sleep_mode_3_gated_we),
27281 .wd (mio_pad_sleep_mode_3_wd),
27282
27283 // from internal hardware
27284 .de (1'b0),
27285 .d ('0),
27286
27287 // to internal hardware
27288 .qe (),
27289 .q (reg2hw.mio_pad_sleep_mode[3].q),
27290 .ds (),
27291
27292 // to register interface (read)
27293 .qs (mio_pad_sleep_mode_3_qs)
27294 );
27295
27296
27297 // Subregister 4 of Multireg mio_pad_sleep_mode
27298 // R[mio_pad_sleep_mode_4]: V(False)
27299 // Create REGWEN-gated WE signal
27300 logic mio_pad_sleep_mode_4_gated_we;
27301 1/1 assign mio_pad_sleep_mode_4_gated_we = mio_pad_sleep_mode_4_we & mio_pad_sleep_regwen_4_qs;
Tests: T2 T25 T19
27302 prim_subreg #(
27303 .DW (2),
27304 .SwAccess(prim_subreg_pkg::SwAccessRW),
27305 .RESVAL (2'h2),
27306 .Mubi (1'b0)
27307 ) u_mio_pad_sleep_mode_4 (
27308 .clk_i (clk_i),
27309 .rst_ni (rst_ni),
27310
27311 // from register interface
27312 .we (mio_pad_sleep_mode_4_gated_we),
27313 .wd (mio_pad_sleep_mode_4_wd),
27314
27315 // from internal hardware
27316 .de (1'b0),
27317 .d ('0),
27318
27319 // to internal hardware
27320 .qe (),
27321 .q (reg2hw.mio_pad_sleep_mode[4].q),
27322 .ds (),
27323
27324 // to register interface (read)
27325 .qs (mio_pad_sleep_mode_4_qs)
27326 );
27327
27328
27329 // Subregister 5 of Multireg mio_pad_sleep_mode
27330 // R[mio_pad_sleep_mode_5]: V(False)
27331 // Create REGWEN-gated WE signal
27332 logic mio_pad_sleep_mode_5_gated_we;
27333 1/1 assign mio_pad_sleep_mode_5_gated_we = mio_pad_sleep_mode_5_we & mio_pad_sleep_regwen_5_qs;
Tests: T2 T25 T19
27334 prim_subreg #(
27335 .DW (2),
27336 .SwAccess(prim_subreg_pkg::SwAccessRW),
27337 .RESVAL (2'h2),
27338 .Mubi (1'b0)
27339 ) u_mio_pad_sleep_mode_5 (
27340 .clk_i (clk_i),
27341 .rst_ni (rst_ni),
27342
27343 // from register interface
27344 .we (mio_pad_sleep_mode_5_gated_we),
27345 .wd (mio_pad_sleep_mode_5_wd),
27346
27347 // from internal hardware
27348 .de (1'b0),
27349 .d ('0),
27350
27351 // to internal hardware
27352 .qe (),
27353 .q (reg2hw.mio_pad_sleep_mode[5].q),
27354 .ds (),
27355
27356 // to register interface (read)
27357 .qs (mio_pad_sleep_mode_5_qs)
27358 );
27359
27360
27361 // Subregister 6 of Multireg mio_pad_sleep_mode
27362 // R[mio_pad_sleep_mode_6]: V(False)
27363 // Create REGWEN-gated WE signal
27364 logic mio_pad_sleep_mode_6_gated_we;
27365 1/1 assign mio_pad_sleep_mode_6_gated_we = mio_pad_sleep_mode_6_we & mio_pad_sleep_regwen_6_qs;
Tests: T2 T25 T19
27366 prim_subreg #(
27367 .DW (2),
27368 .SwAccess(prim_subreg_pkg::SwAccessRW),
27369 .RESVAL (2'h2),
27370 .Mubi (1'b0)
27371 ) u_mio_pad_sleep_mode_6 (
27372 .clk_i (clk_i),
27373 .rst_ni (rst_ni),
27374
27375 // from register interface
27376 .we (mio_pad_sleep_mode_6_gated_we),
27377 .wd (mio_pad_sleep_mode_6_wd),
27378
27379 // from internal hardware
27380 .de (1'b0),
27381 .d ('0),
27382
27383 // to internal hardware
27384 .qe (),
27385 .q (reg2hw.mio_pad_sleep_mode[6].q),
27386 .ds (),
27387
27388 // to register interface (read)
27389 .qs (mio_pad_sleep_mode_6_qs)
27390 );
27391
27392
27393 // Subregister 7 of Multireg mio_pad_sleep_mode
27394 // R[mio_pad_sleep_mode_7]: V(False)
27395 // Create REGWEN-gated WE signal
27396 logic mio_pad_sleep_mode_7_gated_we;
27397 1/1 assign mio_pad_sleep_mode_7_gated_we = mio_pad_sleep_mode_7_we & mio_pad_sleep_regwen_7_qs;
Tests: T2 T6 T25
27398 prim_subreg #(
27399 .DW (2),
27400 .SwAccess(prim_subreg_pkg::SwAccessRW),
27401 .RESVAL (2'h2),
27402 .Mubi (1'b0)
27403 ) u_mio_pad_sleep_mode_7 (
27404 .clk_i (clk_i),
27405 .rst_ni (rst_ni),
27406
27407 // from register interface
27408 .we (mio_pad_sleep_mode_7_gated_we),
27409 .wd (mio_pad_sleep_mode_7_wd),
27410
27411 // from internal hardware
27412 .de (1'b0),
27413 .d ('0),
27414
27415 // to internal hardware
27416 .qe (),
27417 .q (reg2hw.mio_pad_sleep_mode[7].q),
27418 .ds (),
27419
27420 // to register interface (read)
27421 .qs (mio_pad_sleep_mode_7_qs)
27422 );
27423
27424
27425 // Subregister 8 of Multireg mio_pad_sleep_mode
27426 // R[mio_pad_sleep_mode_8]: V(False)
27427 // Create REGWEN-gated WE signal
27428 logic mio_pad_sleep_mode_8_gated_we;
27429 1/1 assign mio_pad_sleep_mode_8_gated_we = mio_pad_sleep_mode_8_we & mio_pad_sleep_regwen_8_qs;
Tests: T2 T19 T40
27430 prim_subreg #(
27431 .DW (2),
27432 .SwAccess(prim_subreg_pkg::SwAccessRW),
27433 .RESVAL (2'h2),
27434 .Mubi (1'b0)
27435 ) u_mio_pad_sleep_mode_8 (
27436 .clk_i (clk_i),
27437 .rst_ni (rst_ni),
27438
27439 // from register interface
27440 .we (mio_pad_sleep_mode_8_gated_we),
27441 .wd (mio_pad_sleep_mode_8_wd),
27442
27443 // from internal hardware
27444 .de (1'b0),
27445 .d ('0),
27446
27447 // to internal hardware
27448 .qe (),
27449 .q (reg2hw.mio_pad_sleep_mode[8].q),
27450 .ds (),
27451
27452 // to register interface (read)
27453 .qs (mio_pad_sleep_mode_8_qs)
27454 );
27455
27456
27457 // Subregister 9 of Multireg mio_pad_sleep_mode
27458 // R[mio_pad_sleep_mode_9]: V(False)
27459 // Create REGWEN-gated WE signal
27460 logic mio_pad_sleep_mode_9_gated_we;
27461 1/1 assign mio_pad_sleep_mode_9_gated_we = mio_pad_sleep_mode_9_we & mio_pad_sleep_regwen_9_qs;
Tests: T2 T19 T40
27462 prim_subreg #(
27463 .DW (2),
27464 .SwAccess(prim_subreg_pkg::SwAccessRW),
27465 .RESVAL (2'h2),
27466 .Mubi (1'b0)
27467 ) u_mio_pad_sleep_mode_9 (
27468 .clk_i (clk_i),
27469 .rst_ni (rst_ni),
27470
27471 // from register interface
27472 .we (mio_pad_sleep_mode_9_gated_we),
27473 .wd (mio_pad_sleep_mode_9_wd),
27474
27475 // from internal hardware
27476 .de (1'b0),
27477 .d ('0),
27478
27479 // to internal hardware
27480 .qe (),
27481 .q (reg2hw.mio_pad_sleep_mode[9].q),
27482 .ds (),
27483
27484 // to register interface (read)
27485 .qs (mio_pad_sleep_mode_9_qs)
27486 );
27487
27488
27489 // Subregister 10 of Multireg mio_pad_sleep_mode
27490 // R[mio_pad_sleep_mode_10]: V(False)
27491 // Create REGWEN-gated WE signal
27492 logic mio_pad_sleep_mode_10_gated_we;
27493 1/1 assign mio_pad_sleep_mode_10_gated_we = mio_pad_sleep_mode_10_we & mio_pad_sleep_regwen_10_qs;
Tests: T2 T19 T40
27494 prim_subreg #(
27495 .DW (2),
27496 .SwAccess(prim_subreg_pkg::SwAccessRW),
27497 .RESVAL (2'h2),
27498 .Mubi (1'b0)
27499 ) u_mio_pad_sleep_mode_10 (
27500 .clk_i (clk_i),
27501 .rst_ni (rst_ni),
27502
27503 // from register interface
27504 .we (mio_pad_sleep_mode_10_gated_we),
27505 .wd (mio_pad_sleep_mode_10_wd),
27506
27507 // from internal hardware
27508 .de (1'b0),
27509 .d ('0),
27510
27511 // to internal hardware
27512 .qe (),
27513 .q (reg2hw.mio_pad_sleep_mode[10].q),
27514 .ds (),
27515
27516 // to register interface (read)
27517 .qs (mio_pad_sleep_mode_10_qs)
27518 );
27519
27520
27521 // Subregister 11 of Multireg mio_pad_sleep_mode
27522 // R[mio_pad_sleep_mode_11]: V(False)
27523 // Create REGWEN-gated WE signal
27524 logic mio_pad_sleep_mode_11_gated_we;
27525 1/1 assign mio_pad_sleep_mode_11_gated_we = mio_pad_sleep_mode_11_we & mio_pad_sleep_regwen_11_qs;
Tests: T2 T19 T40
27526 prim_subreg #(
27527 .DW (2),
27528 .SwAccess(prim_subreg_pkg::SwAccessRW),
27529 .RESVAL (2'h2),
27530 .Mubi (1'b0)
27531 ) u_mio_pad_sleep_mode_11 (
27532 .clk_i (clk_i),
27533 .rst_ni (rst_ni),
27534
27535 // from register interface
27536 .we (mio_pad_sleep_mode_11_gated_we),
27537 .wd (mio_pad_sleep_mode_11_wd),
27538
27539 // from internal hardware
27540 .de (1'b0),
27541 .d ('0),
27542
27543 // to internal hardware
27544 .qe (),
27545 .q (reg2hw.mio_pad_sleep_mode[11].q),
27546 .ds (),
27547
27548 // to register interface (read)
27549 .qs (mio_pad_sleep_mode_11_qs)
27550 );
27551
27552
27553 // Subregister 12 of Multireg mio_pad_sleep_mode
27554 // R[mio_pad_sleep_mode_12]: V(False)
27555 // Create REGWEN-gated WE signal
27556 logic mio_pad_sleep_mode_12_gated_we;
27557 1/1 assign mio_pad_sleep_mode_12_gated_we = mio_pad_sleep_mode_12_we & mio_pad_sleep_regwen_12_qs;
Tests: T2 T19 T40
27558 prim_subreg #(
27559 .DW (2),
27560 .SwAccess(prim_subreg_pkg::SwAccessRW),
27561 .RESVAL (2'h2),
27562 .Mubi (1'b0)
27563 ) u_mio_pad_sleep_mode_12 (
27564 .clk_i (clk_i),
27565 .rst_ni (rst_ni),
27566
27567 // from register interface
27568 .we (mio_pad_sleep_mode_12_gated_we),
27569 .wd (mio_pad_sleep_mode_12_wd),
27570
27571 // from internal hardware
27572 .de (1'b0),
27573 .d ('0),
27574
27575 // to internal hardware
27576 .qe (),
27577 .q (reg2hw.mio_pad_sleep_mode[12].q),
27578 .ds (),
27579
27580 // to register interface (read)
27581 .qs (mio_pad_sleep_mode_12_qs)
27582 );
27583
27584
27585 // Subregister 13 of Multireg mio_pad_sleep_mode
27586 // R[mio_pad_sleep_mode_13]: V(False)
27587 // Create REGWEN-gated WE signal
27588 logic mio_pad_sleep_mode_13_gated_we;
27589 1/1 assign mio_pad_sleep_mode_13_gated_we = mio_pad_sleep_mode_13_we & mio_pad_sleep_regwen_13_qs;
Tests: T2 T19 T40
27590 prim_subreg #(
27591 .DW (2),
27592 .SwAccess(prim_subreg_pkg::SwAccessRW),
27593 .RESVAL (2'h2),
27594 .Mubi (1'b0)
27595 ) u_mio_pad_sleep_mode_13 (
27596 .clk_i (clk_i),
27597 .rst_ni (rst_ni),
27598
27599 // from register interface
27600 .we (mio_pad_sleep_mode_13_gated_we),
27601 .wd (mio_pad_sleep_mode_13_wd),
27602
27603 // from internal hardware
27604 .de (1'b0),
27605 .d ('0),
27606
27607 // to internal hardware
27608 .qe (),
27609 .q (reg2hw.mio_pad_sleep_mode[13].q),
27610 .ds (),
27611
27612 // to register interface (read)
27613 .qs (mio_pad_sleep_mode_13_qs)
27614 );
27615
27616
27617 // Subregister 14 of Multireg mio_pad_sleep_mode
27618 // R[mio_pad_sleep_mode_14]: V(False)
27619 // Create REGWEN-gated WE signal
27620 logic mio_pad_sleep_mode_14_gated_we;
27621 1/1 assign mio_pad_sleep_mode_14_gated_we = mio_pad_sleep_mode_14_we & mio_pad_sleep_regwen_14_qs;
Tests: T2 T19 T40
27622 prim_subreg #(
27623 .DW (2),
27624 .SwAccess(prim_subreg_pkg::SwAccessRW),
27625 .RESVAL (2'h2),
27626 .Mubi (1'b0)
27627 ) u_mio_pad_sleep_mode_14 (
27628 .clk_i (clk_i),
27629 .rst_ni (rst_ni),
27630
27631 // from register interface
27632 .we (mio_pad_sleep_mode_14_gated_we),
27633 .wd (mio_pad_sleep_mode_14_wd),
27634
27635 // from internal hardware
27636 .de (1'b0),
27637 .d ('0),
27638
27639 // to internal hardware
27640 .qe (),
27641 .q (reg2hw.mio_pad_sleep_mode[14].q),
27642 .ds (),
27643
27644 // to register interface (read)
27645 .qs (mio_pad_sleep_mode_14_qs)
27646 );
27647
27648
27649 // Subregister 15 of Multireg mio_pad_sleep_mode
27650 // R[mio_pad_sleep_mode_15]: V(False)
27651 // Create REGWEN-gated WE signal
27652 logic mio_pad_sleep_mode_15_gated_we;
27653 1/1 assign mio_pad_sleep_mode_15_gated_we = mio_pad_sleep_mode_15_we & mio_pad_sleep_regwen_15_qs;
Tests: T2 T19 T40
27654 prim_subreg #(
27655 .DW (2),
27656 .SwAccess(prim_subreg_pkg::SwAccessRW),
27657 .RESVAL (2'h2),
27658 .Mubi (1'b0)
27659 ) u_mio_pad_sleep_mode_15 (
27660 .clk_i (clk_i),
27661 .rst_ni (rst_ni),
27662
27663 // from register interface
27664 .we (mio_pad_sleep_mode_15_gated_we),
27665 .wd (mio_pad_sleep_mode_15_wd),
27666
27667 // from internal hardware
27668 .de (1'b0),
27669 .d ('0),
27670
27671 // to internal hardware
27672 .qe (),
27673 .q (reg2hw.mio_pad_sleep_mode[15].q),
27674 .ds (),
27675
27676 // to register interface (read)
27677 .qs (mio_pad_sleep_mode_15_qs)
27678 );
27679
27680
27681 // Subregister 16 of Multireg mio_pad_sleep_mode
27682 // R[mio_pad_sleep_mode_16]: V(False)
27683 // Create REGWEN-gated WE signal
27684 logic mio_pad_sleep_mode_16_gated_we;
27685 1/1 assign mio_pad_sleep_mode_16_gated_we = mio_pad_sleep_mode_16_we & mio_pad_sleep_regwen_16_qs;
Tests: T2 T19 T40
27686 prim_subreg #(
27687 .DW (2),
27688 .SwAccess(prim_subreg_pkg::SwAccessRW),
27689 .RESVAL (2'h2),
27690 .Mubi (1'b0)
27691 ) u_mio_pad_sleep_mode_16 (
27692 .clk_i (clk_i),
27693 .rst_ni (rst_ni),
27694
27695 // from register interface
27696 .we (mio_pad_sleep_mode_16_gated_we),
27697 .wd (mio_pad_sleep_mode_16_wd),
27698
27699 // from internal hardware
27700 .de (1'b0),
27701 .d ('0),
27702
27703 // to internal hardware
27704 .qe (),
27705 .q (reg2hw.mio_pad_sleep_mode[16].q),
27706 .ds (),
27707
27708 // to register interface (read)
27709 .qs (mio_pad_sleep_mode_16_qs)
27710 );
27711
27712
27713 // Subregister 17 of Multireg mio_pad_sleep_mode
27714 // R[mio_pad_sleep_mode_17]: V(False)
27715 // Create REGWEN-gated WE signal
27716 logic mio_pad_sleep_mode_17_gated_we;
27717 1/1 assign mio_pad_sleep_mode_17_gated_we = mio_pad_sleep_mode_17_we & mio_pad_sleep_regwen_17_qs;
Tests: T2 T19 T40
27718 prim_subreg #(
27719 .DW (2),
27720 .SwAccess(prim_subreg_pkg::SwAccessRW),
27721 .RESVAL (2'h2),
27722 .Mubi (1'b0)
27723 ) u_mio_pad_sleep_mode_17 (
27724 .clk_i (clk_i),
27725 .rst_ni (rst_ni),
27726
27727 // from register interface
27728 .we (mio_pad_sleep_mode_17_gated_we),
27729 .wd (mio_pad_sleep_mode_17_wd),
27730
27731 // from internal hardware
27732 .de (1'b0),
27733 .d ('0),
27734
27735 // to internal hardware
27736 .qe (),
27737 .q (reg2hw.mio_pad_sleep_mode[17].q),
27738 .ds (),
27739
27740 // to register interface (read)
27741 .qs (mio_pad_sleep_mode_17_qs)
27742 );
27743
27744
27745 // Subregister 18 of Multireg mio_pad_sleep_mode
27746 // R[mio_pad_sleep_mode_18]: V(False)
27747 // Create REGWEN-gated WE signal
27748 logic mio_pad_sleep_mode_18_gated_we;
27749 1/1 assign mio_pad_sleep_mode_18_gated_we = mio_pad_sleep_mode_18_we & mio_pad_sleep_regwen_18_qs;
Tests: T2 T19 T40
27750 prim_subreg #(
27751 .DW (2),
27752 .SwAccess(prim_subreg_pkg::SwAccessRW),
27753 .RESVAL (2'h2),
27754 .Mubi (1'b0)
27755 ) u_mio_pad_sleep_mode_18 (
27756 .clk_i (clk_i),
27757 .rst_ni (rst_ni),
27758
27759 // from register interface
27760 .we (mio_pad_sleep_mode_18_gated_we),
27761 .wd (mio_pad_sleep_mode_18_wd),
27762
27763 // from internal hardware
27764 .de (1'b0),
27765 .d ('0),
27766
27767 // to internal hardware
27768 .qe (),
27769 .q (reg2hw.mio_pad_sleep_mode[18].q),
27770 .ds (),
27771
27772 // to register interface (read)
27773 .qs (mio_pad_sleep_mode_18_qs)
27774 );
27775
27776
27777 // Subregister 19 of Multireg mio_pad_sleep_mode
27778 // R[mio_pad_sleep_mode_19]: V(False)
27779 // Create REGWEN-gated WE signal
27780 logic mio_pad_sleep_mode_19_gated_we;
27781 1/1 assign mio_pad_sleep_mode_19_gated_we = mio_pad_sleep_mode_19_we & mio_pad_sleep_regwen_19_qs;
Tests: T2 T19 T40
27782 prim_subreg #(
27783 .DW (2),
27784 .SwAccess(prim_subreg_pkg::SwAccessRW),
27785 .RESVAL (2'h2),
27786 .Mubi (1'b0)
27787 ) u_mio_pad_sleep_mode_19 (
27788 .clk_i (clk_i),
27789 .rst_ni (rst_ni),
27790
27791 // from register interface
27792 .we (mio_pad_sleep_mode_19_gated_we),
27793 .wd (mio_pad_sleep_mode_19_wd),
27794
27795 // from internal hardware
27796 .de (1'b0),
27797 .d ('0),
27798
27799 // to internal hardware
27800 .qe (),
27801 .q (reg2hw.mio_pad_sleep_mode[19].q),
27802 .ds (),
27803
27804 // to register interface (read)
27805 .qs (mio_pad_sleep_mode_19_qs)
27806 );
27807
27808
27809 // Subregister 20 of Multireg mio_pad_sleep_mode
27810 // R[mio_pad_sleep_mode_20]: V(False)
27811 // Create REGWEN-gated WE signal
27812 logic mio_pad_sleep_mode_20_gated_we;
27813 1/1 assign mio_pad_sleep_mode_20_gated_we = mio_pad_sleep_mode_20_we & mio_pad_sleep_regwen_20_qs;
Tests: T2 T19 T40
27814 prim_subreg #(
27815 .DW (2),
27816 .SwAccess(prim_subreg_pkg::SwAccessRW),
27817 .RESVAL (2'h2),
27818 .Mubi (1'b0)
27819 ) u_mio_pad_sleep_mode_20 (
27820 .clk_i (clk_i),
27821 .rst_ni (rst_ni),
27822
27823 // from register interface
27824 .we (mio_pad_sleep_mode_20_gated_we),
27825 .wd (mio_pad_sleep_mode_20_wd),
27826
27827 // from internal hardware
27828 .de (1'b0),
27829 .d ('0),
27830
27831 // to internal hardware
27832 .qe (),
27833 .q (reg2hw.mio_pad_sleep_mode[20].q),
27834 .ds (),
27835
27836 // to register interface (read)
27837 .qs (mio_pad_sleep_mode_20_qs)
27838 );
27839
27840
27841 // Subregister 21 of Multireg mio_pad_sleep_mode
27842 // R[mio_pad_sleep_mode_21]: V(False)
27843 // Create REGWEN-gated WE signal
27844 logic mio_pad_sleep_mode_21_gated_we;
27845 1/1 assign mio_pad_sleep_mode_21_gated_we = mio_pad_sleep_mode_21_we & mio_pad_sleep_regwen_21_qs;
Tests: T2 T19 T40
27846 prim_subreg #(
27847 .DW (2),
27848 .SwAccess(prim_subreg_pkg::SwAccessRW),
27849 .RESVAL (2'h2),
27850 .Mubi (1'b0)
27851 ) u_mio_pad_sleep_mode_21 (
27852 .clk_i (clk_i),
27853 .rst_ni (rst_ni),
27854
27855 // from register interface
27856 .we (mio_pad_sleep_mode_21_gated_we),
27857 .wd (mio_pad_sleep_mode_21_wd),
27858
27859 // from internal hardware
27860 .de (1'b0),
27861 .d ('0),
27862
27863 // to internal hardware
27864 .qe (),
27865 .q (reg2hw.mio_pad_sleep_mode[21].q),
27866 .ds (),
27867
27868 // to register interface (read)
27869 .qs (mio_pad_sleep_mode_21_qs)
27870 );
27871
27872
27873 // Subregister 22 of Multireg mio_pad_sleep_mode
27874 // R[mio_pad_sleep_mode_22]: V(False)
27875 // Create REGWEN-gated WE signal
27876 logic mio_pad_sleep_mode_22_gated_we;
27877 1/1 assign mio_pad_sleep_mode_22_gated_we = mio_pad_sleep_mode_22_we & mio_pad_sleep_regwen_22_qs;
Tests: T2 T19 T40
27878 prim_subreg #(
27879 .DW (2),
27880 .SwAccess(prim_subreg_pkg::SwAccessRW),
27881 .RESVAL (2'h2),
27882 .Mubi (1'b0)
27883 ) u_mio_pad_sleep_mode_22 (
27884 .clk_i (clk_i),
27885 .rst_ni (rst_ni),
27886
27887 // from register interface
27888 .we (mio_pad_sleep_mode_22_gated_we),
27889 .wd (mio_pad_sleep_mode_22_wd),
27890
27891 // from internal hardware
27892 .de (1'b0),
27893 .d ('0),
27894
27895 // to internal hardware
27896 .qe (),
27897 .q (reg2hw.mio_pad_sleep_mode[22].q),
27898 .ds (),
27899
27900 // to register interface (read)
27901 .qs (mio_pad_sleep_mode_22_qs)
27902 );
27903
27904
27905 // Subregister 23 of Multireg mio_pad_sleep_mode
27906 // R[mio_pad_sleep_mode_23]: V(False)
27907 // Create REGWEN-gated WE signal
27908 logic mio_pad_sleep_mode_23_gated_we;
27909 1/1 assign mio_pad_sleep_mode_23_gated_we = mio_pad_sleep_mode_23_we & mio_pad_sleep_regwen_23_qs;
Tests: T2 T19 T40
27910 prim_subreg #(
27911 .DW (2),
27912 .SwAccess(prim_subreg_pkg::SwAccessRW),
27913 .RESVAL (2'h2),
27914 .Mubi (1'b0)
27915 ) u_mio_pad_sleep_mode_23 (
27916 .clk_i (clk_i),
27917 .rst_ni (rst_ni),
27918
27919 // from register interface
27920 .we (mio_pad_sleep_mode_23_gated_we),
27921 .wd (mio_pad_sleep_mode_23_wd),
27922
27923 // from internal hardware
27924 .de (1'b0),
27925 .d ('0),
27926
27927 // to internal hardware
27928 .qe (),
27929 .q (reg2hw.mio_pad_sleep_mode[23].q),
27930 .ds (),
27931
27932 // to register interface (read)
27933 .qs (mio_pad_sleep_mode_23_qs)
27934 );
27935
27936
27937 // Subregister 24 of Multireg mio_pad_sleep_mode
27938 // R[mio_pad_sleep_mode_24]: V(False)
27939 // Create REGWEN-gated WE signal
27940 logic mio_pad_sleep_mode_24_gated_we;
27941 1/1 assign mio_pad_sleep_mode_24_gated_we = mio_pad_sleep_mode_24_we & mio_pad_sleep_regwen_24_qs;
Tests: T2 T19 T40
27942 prim_subreg #(
27943 .DW (2),
27944 .SwAccess(prim_subreg_pkg::SwAccessRW),
27945 .RESVAL (2'h2),
27946 .Mubi (1'b0)
27947 ) u_mio_pad_sleep_mode_24 (
27948 .clk_i (clk_i),
27949 .rst_ni (rst_ni),
27950
27951 // from register interface
27952 .we (mio_pad_sleep_mode_24_gated_we),
27953 .wd (mio_pad_sleep_mode_24_wd),
27954
27955 // from internal hardware
27956 .de (1'b0),
27957 .d ('0),
27958
27959 // to internal hardware
27960 .qe (),
27961 .q (reg2hw.mio_pad_sleep_mode[24].q),
27962 .ds (),
27963
27964 // to register interface (read)
27965 .qs (mio_pad_sleep_mode_24_qs)
27966 );
27967
27968
27969 // Subregister 25 of Multireg mio_pad_sleep_mode
27970 // R[mio_pad_sleep_mode_25]: V(False)
27971 // Create REGWEN-gated WE signal
27972 logic mio_pad_sleep_mode_25_gated_we;
27973 1/1 assign mio_pad_sleep_mode_25_gated_we = mio_pad_sleep_mode_25_we & mio_pad_sleep_regwen_25_qs;
Tests: T2 T19 T40
27974 prim_subreg #(
27975 .DW (2),
27976 .SwAccess(prim_subreg_pkg::SwAccessRW),
27977 .RESVAL (2'h2),
27978 .Mubi (1'b0)
27979 ) u_mio_pad_sleep_mode_25 (
27980 .clk_i (clk_i),
27981 .rst_ni (rst_ni),
27982
27983 // from register interface
27984 .we (mio_pad_sleep_mode_25_gated_we),
27985 .wd (mio_pad_sleep_mode_25_wd),
27986
27987 // from internal hardware
27988 .de (1'b0),
27989 .d ('0),
27990
27991 // to internal hardware
27992 .qe (),
27993 .q (reg2hw.mio_pad_sleep_mode[25].q),
27994 .ds (),
27995
27996 // to register interface (read)
27997 .qs (mio_pad_sleep_mode_25_qs)
27998 );
27999
28000
28001 // Subregister 26 of Multireg mio_pad_sleep_mode
28002 // R[mio_pad_sleep_mode_26]: V(False)
28003 // Create REGWEN-gated WE signal
28004 logic mio_pad_sleep_mode_26_gated_we;
28005 1/1 assign mio_pad_sleep_mode_26_gated_we = mio_pad_sleep_mode_26_we & mio_pad_sleep_regwen_26_qs;
Tests: T2 T19 T40
28006 prim_subreg #(
28007 .DW (2),
28008 .SwAccess(prim_subreg_pkg::SwAccessRW),
28009 .RESVAL (2'h2),
28010 .Mubi (1'b0)
28011 ) u_mio_pad_sleep_mode_26 (
28012 .clk_i (clk_i),
28013 .rst_ni (rst_ni),
28014
28015 // from register interface
28016 .we (mio_pad_sleep_mode_26_gated_we),
28017 .wd (mio_pad_sleep_mode_26_wd),
28018
28019 // from internal hardware
28020 .de (1'b0),
28021 .d ('0),
28022
28023 // to internal hardware
28024 .qe (),
28025 .q (reg2hw.mio_pad_sleep_mode[26].q),
28026 .ds (),
28027
28028 // to register interface (read)
28029 .qs (mio_pad_sleep_mode_26_qs)
28030 );
28031
28032
28033 // Subregister 27 of Multireg mio_pad_sleep_mode
28034 // R[mio_pad_sleep_mode_27]: V(False)
28035 // Create REGWEN-gated WE signal
28036 logic mio_pad_sleep_mode_27_gated_we;
28037 1/1 assign mio_pad_sleep_mode_27_gated_we = mio_pad_sleep_mode_27_we & mio_pad_sleep_regwen_27_qs;
Tests: T2 T19 T40
28038 prim_subreg #(
28039 .DW (2),
28040 .SwAccess(prim_subreg_pkg::SwAccessRW),
28041 .RESVAL (2'h2),
28042 .Mubi (1'b0)
28043 ) u_mio_pad_sleep_mode_27 (
28044 .clk_i (clk_i),
28045 .rst_ni (rst_ni),
28046
28047 // from register interface
28048 .we (mio_pad_sleep_mode_27_gated_we),
28049 .wd (mio_pad_sleep_mode_27_wd),
28050
28051 // from internal hardware
28052 .de (1'b0),
28053 .d ('0),
28054
28055 // to internal hardware
28056 .qe (),
28057 .q (reg2hw.mio_pad_sleep_mode[27].q),
28058 .ds (),
28059
28060 // to register interface (read)
28061 .qs (mio_pad_sleep_mode_27_qs)
28062 );
28063
28064
28065 // Subregister 28 of Multireg mio_pad_sleep_mode
28066 // R[mio_pad_sleep_mode_28]: V(False)
28067 // Create REGWEN-gated WE signal
28068 logic mio_pad_sleep_mode_28_gated_we;
28069 1/1 assign mio_pad_sleep_mode_28_gated_we = mio_pad_sleep_mode_28_we & mio_pad_sleep_regwen_28_qs;
Tests: T2 T19 T40
28070 prim_subreg #(
28071 .DW (2),
28072 .SwAccess(prim_subreg_pkg::SwAccessRW),
28073 .RESVAL (2'h2),
28074 .Mubi (1'b0)
28075 ) u_mio_pad_sleep_mode_28 (
28076 .clk_i (clk_i),
28077 .rst_ni (rst_ni),
28078
28079 // from register interface
28080 .we (mio_pad_sleep_mode_28_gated_we),
28081 .wd (mio_pad_sleep_mode_28_wd),
28082
28083 // from internal hardware
28084 .de (1'b0),
28085 .d ('0),
28086
28087 // to internal hardware
28088 .qe (),
28089 .q (reg2hw.mio_pad_sleep_mode[28].q),
28090 .ds (),
28091
28092 // to register interface (read)
28093 .qs (mio_pad_sleep_mode_28_qs)
28094 );
28095
28096
28097 // Subregister 29 of Multireg mio_pad_sleep_mode
28098 // R[mio_pad_sleep_mode_29]: V(False)
28099 // Create REGWEN-gated WE signal
28100 logic mio_pad_sleep_mode_29_gated_we;
28101 1/1 assign mio_pad_sleep_mode_29_gated_we = mio_pad_sleep_mode_29_we & mio_pad_sleep_regwen_29_qs;
Tests: T2 T19 T40
28102 prim_subreg #(
28103 .DW (2),
28104 .SwAccess(prim_subreg_pkg::SwAccessRW),
28105 .RESVAL (2'h2),
28106 .Mubi (1'b0)
28107 ) u_mio_pad_sleep_mode_29 (
28108 .clk_i (clk_i),
28109 .rst_ni (rst_ni),
28110
28111 // from register interface
28112 .we (mio_pad_sleep_mode_29_gated_we),
28113 .wd (mio_pad_sleep_mode_29_wd),
28114
28115 // from internal hardware
28116 .de (1'b0),
28117 .d ('0),
28118
28119 // to internal hardware
28120 .qe (),
28121 .q (reg2hw.mio_pad_sleep_mode[29].q),
28122 .ds (),
28123
28124 // to register interface (read)
28125 .qs (mio_pad_sleep_mode_29_qs)
28126 );
28127
28128
28129 // Subregister 30 of Multireg mio_pad_sleep_mode
28130 // R[mio_pad_sleep_mode_30]: V(False)
28131 // Create REGWEN-gated WE signal
28132 logic mio_pad_sleep_mode_30_gated_we;
28133 1/1 assign mio_pad_sleep_mode_30_gated_we = mio_pad_sleep_mode_30_we & mio_pad_sleep_regwen_30_qs;
Tests: T2 T19 T40
28134 prim_subreg #(
28135 .DW (2),
28136 .SwAccess(prim_subreg_pkg::SwAccessRW),
28137 .RESVAL (2'h2),
28138 .Mubi (1'b0)
28139 ) u_mio_pad_sleep_mode_30 (
28140 .clk_i (clk_i),
28141 .rst_ni (rst_ni),
28142
28143 // from register interface
28144 .we (mio_pad_sleep_mode_30_gated_we),
28145 .wd (mio_pad_sleep_mode_30_wd),
28146
28147 // from internal hardware
28148 .de (1'b0),
28149 .d ('0),
28150
28151 // to internal hardware
28152 .qe (),
28153 .q (reg2hw.mio_pad_sleep_mode[30].q),
28154 .ds (),
28155
28156 // to register interface (read)
28157 .qs (mio_pad_sleep_mode_30_qs)
28158 );
28159
28160
28161 // Subregister 31 of Multireg mio_pad_sleep_mode
28162 // R[mio_pad_sleep_mode_31]: V(False)
28163 // Create REGWEN-gated WE signal
28164 logic mio_pad_sleep_mode_31_gated_we;
28165 1/1 assign mio_pad_sleep_mode_31_gated_we = mio_pad_sleep_mode_31_we & mio_pad_sleep_regwen_31_qs;
Tests: T2 T19 T40
28166 prim_subreg #(
28167 .DW (2),
28168 .SwAccess(prim_subreg_pkg::SwAccessRW),
28169 .RESVAL (2'h2),
28170 .Mubi (1'b0)
28171 ) u_mio_pad_sleep_mode_31 (
28172 .clk_i (clk_i),
28173 .rst_ni (rst_ni),
28174
28175 // from register interface
28176 .we (mio_pad_sleep_mode_31_gated_we),
28177 .wd (mio_pad_sleep_mode_31_wd),
28178
28179 // from internal hardware
28180 .de (1'b0),
28181 .d ('0),
28182
28183 // to internal hardware
28184 .qe (),
28185 .q (reg2hw.mio_pad_sleep_mode[31].q),
28186 .ds (),
28187
28188 // to register interface (read)
28189 .qs (mio_pad_sleep_mode_31_qs)
28190 );
28191
28192
28193 // Subregister 32 of Multireg mio_pad_sleep_mode
28194 // R[mio_pad_sleep_mode_32]: V(False)
28195 // Create REGWEN-gated WE signal
28196 logic mio_pad_sleep_mode_32_gated_we;
28197 1/1 assign mio_pad_sleep_mode_32_gated_we = mio_pad_sleep_mode_32_we & mio_pad_sleep_regwen_32_qs;
Tests: T2 T19 T40
28198 prim_subreg #(
28199 .DW (2),
28200 .SwAccess(prim_subreg_pkg::SwAccessRW),
28201 .RESVAL (2'h2),
28202 .Mubi (1'b0)
28203 ) u_mio_pad_sleep_mode_32 (
28204 .clk_i (clk_i),
28205 .rst_ni (rst_ni),
28206
28207 // from register interface
28208 .we (mio_pad_sleep_mode_32_gated_we),
28209 .wd (mio_pad_sleep_mode_32_wd),
28210
28211 // from internal hardware
28212 .de (1'b0),
28213 .d ('0),
28214
28215 // to internal hardware
28216 .qe (),
28217 .q (reg2hw.mio_pad_sleep_mode[32].q),
28218 .ds (),
28219
28220 // to register interface (read)
28221 .qs (mio_pad_sleep_mode_32_qs)
28222 );
28223
28224
28225 // Subregister 33 of Multireg mio_pad_sleep_mode
28226 // R[mio_pad_sleep_mode_33]: V(False)
28227 // Create REGWEN-gated WE signal
28228 logic mio_pad_sleep_mode_33_gated_we;
28229 1/1 assign mio_pad_sleep_mode_33_gated_we = mio_pad_sleep_mode_33_we & mio_pad_sleep_regwen_33_qs;
Tests: T2 T19 T40
28230 prim_subreg #(
28231 .DW (2),
28232 .SwAccess(prim_subreg_pkg::SwAccessRW),
28233 .RESVAL (2'h2),
28234 .Mubi (1'b0)
28235 ) u_mio_pad_sleep_mode_33 (
28236 .clk_i (clk_i),
28237 .rst_ni (rst_ni),
28238
28239 // from register interface
28240 .we (mio_pad_sleep_mode_33_gated_we),
28241 .wd (mio_pad_sleep_mode_33_wd),
28242
28243 // from internal hardware
28244 .de (1'b0),
28245 .d ('0),
28246
28247 // to internal hardware
28248 .qe (),
28249 .q (reg2hw.mio_pad_sleep_mode[33].q),
28250 .ds (),
28251
28252 // to register interface (read)
28253 .qs (mio_pad_sleep_mode_33_qs)
28254 );
28255
28256
28257 // Subregister 34 of Multireg mio_pad_sleep_mode
28258 // R[mio_pad_sleep_mode_34]: V(False)
28259 // Create REGWEN-gated WE signal
28260 logic mio_pad_sleep_mode_34_gated_we;
28261 1/1 assign mio_pad_sleep_mode_34_gated_we = mio_pad_sleep_mode_34_we & mio_pad_sleep_regwen_34_qs;
Tests: T2 T19 T40
28262 prim_subreg #(
28263 .DW (2),
28264 .SwAccess(prim_subreg_pkg::SwAccessRW),
28265 .RESVAL (2'h2),
28266 .Mubi (1'b0)
28267 ) u_mio_pad_sleep_mode_34 (
28268 .clk_i (clk_i),
28269 .rst_ni (rst_ni),
28270
28271 // from register interface
28272 .we (mio_pad_sleep_mode_34_gated_we),
28273 .wd (mio_pad_sleep_mode_34_wd),
28274
28275 // from internal hardware
28276 .de (1'b0),
28277 .d ('0),
28278
28279 // to internal hardware
28280 .qe (),
28281 .q (reg2hw.mio_pad_sleep_mode[34].q),
28282 .ds (),
28283
28284 // to register interface (read)
28285 .qs (mio_pad_sleep_mode_34_qs)
28286 );
28287
28288
28289 // Subregister 35 of Multireg mio_pad_sleep_mode
28290 // R[mio_pad_sleep_mode_35]: V(False)
28291 // Create REGWEN-gated WE signal
28292 logic mio_pad_sleep_mode_35_gated_we;
28293 1/1 assign mio_pad_sleep_mode_35_gated_we = mio_pad_sleep_mode_35_we & mio_pad_sleep_regwen_35_qs;
Tests: T2 T19 T40
28294 prim_subreg #(
28295 .DW (2),
28296 .SwAccess(prim_subreg_pkg::SwAccessRW),
28297 .RESVAL (2'h2),
28298 .Mubi (1'b0)
28299 ) u_mio_pad_sleep_mode_35 (
28300 .clk_i (clk_i),
28301 .rst_ni (rst_ni),
28302
28303 // from register interface
28304 .we (mio_pad_sleep_mode_35_gated_we),
28305 .wd (mio_pad_sleep_mode_35_wd),
28306
28307 // from internal hardware
28308 .de (1'b0),
28309 .d ('0),
28310
28311 // to internal hardware
28312 .qe (),
28313 .q (reg2hw.mio_pad_sleep_mode[35].q),
28314 .ds (),
28315
28316 // to register interface (read)
28317 .qs (mio_pad_sleep_mode_35_qs)
28318 );
28319
28320
28321 // Subregister 36 of Multireg mio_pad_sleep_mode
28322 // R[mio_pad_sleep_mode_36]: V(False)
28323 // Create REGWEN-gated WE signal
28324 logic mio_pad_sleep_mode_36_gated_we;
28325 1/1 assign mio_pad_sleep_mode_36_gated_we = mio_pad_sleep_mode_36_we & mio_pad_sleep_regwen_36_qs;
Tests: T2 T19 T40
28326 prim_subreg #(
28327 .DW (2),
28328 .SwAccess(prim_subreg_pkg::SwAccessRW),
28329 .RESVAL (2'h2),
28330 .Mubi (1'b0)
28331 ) u_mio_pad_sleep_mode_36 (
28332 .clk_i (clk_i),
28333 .rst_ni (rst_ni),
28334
28335 // from register interface
28336 .we (mio_pad_sleep_mode_36_gated_we),
28337 .wd (mio_pad_sleep_mode_36_wd),
28338
28339 // from internal hardware
28340 .de (1'b0),
28341 .d ('0),
28342
28343 // to internal hardware
28344 .qe (),
28345 .q (reg2hw.mio_pad_sleep_mode[36].q),
28346 .ds (),
28347
28348 // to register interface (read)
28349 .qs (mio_pad_sleep_mode_36_qs)
28350 );
28351
28352
28353 // Subregister 37 of Multireg mio_pad_sleep_mode
28354 // R[mio_pad_sleep_mode_37]: V(False)
28355 // Create REGWEN-gated WE signal
28356 logic mio_pad_sleep_mode_37_gated_we;
28357 1/1 assign mio_pad_sleep_mode_37_gated_we = mio_pad_sleep_mode_37_we & mio_pad_sleep_regwen_37_qs;
Tests: T2 T19 T40
28358 prim_subreg #(
28359 .DW (2),
28360 .SwAccess(prim_subreg_pkg::SwAccessRW),
28361 .RESVAL (2'h2),
28362 .Mubi (1'b0)
28363 ) u_mio_pad_sleep_mode_37 (
28364 .clk_i (clk_i),
28365 .rst_ni (rst_ni),
28366
28367 // from register interface
28368 .we (mio_pad_sleep_mode_37_gated_we),
28369 .wd (mio_pad_sleep_mode_37_wd),
28370
28371 // from internal hardware
28372 .de (1'b0),
28373 .d ('0),
28374
28375 // to internal hardware
28376 .qe (),
28377 .q (reg2hw.mio_pad_sleep_mode[37].q),
28378 .ds (),
28379
28380 // to register interface (read)
28381 .qs (mio_pad_sleep_mode_37_qs)
28382 );
28383
28384
28385 // Subregister 38 of Multireg mio_pad_sleep_mode
28386 // R[mio_pad_sleep_mode_38]: V(False)
28387 // Create REGWEN-gated WE signal
28388 logic mio_pad_sleep_mode_38_gated_we;
28389 1/1 assign mio_pad_sleep_mode_38_gated_we = mio_pad_sleep_mode_38_we & mio_pad_sleep_regwen_38_qs;
Tests: T2 T19 T40
28390 prim_subreg #(
28391 .DW (2),
28392 .SwAccess(prim_subreg_pkg::SwAccessRW),
28393 .RESVAL (2'h2),
28394 .Mubi (1'b0)
28395 ) u_mio_pad_sleep_mode_38 (
28396 .clk_i (clk_i),
28397 .rst_ni (rst_ni),
28398
28399 // from register interface
28400 .we (mio_pad_sleep_mode_38_gated_we),
28401 .wd (mio_pad_sleep_mode_38_wd),
28402
28403 // from internal hardware
28404 .de (1'b0),
28405 .d ('0),
28406
28407 // to internal hardware
28408 .qe (),
28409 .q (reg2hw.mio_pad_sleep_mode[38].q),
28410 .ds (),
28411
28412 // to register interface (read)
28413 .qs (mio_pad_sleep_mode_38_qs)
28414 );
28415
28416
28417 // Subregister 39 of Multireg mio_pad_sleep_mode
28418 // R[mio_pad_sleep_mode_39]: V(False)
28419 // Create REGWEN-gated WE signal
28420 logic mio_pad_sleep_mode_39_gated_we;
28421 1/1 assign mio_pad_sleep_mode_39_gated_we = mio_pad_sleep_mode_39_we & mio_pad_sleep_regwen_39_qs;
Tests: T2 T19 T40
28422 prim_subreg #(
28423 .DW (2),
28424 .SwAccess(prim_subreg_pkg::SwAccessRW),
28425 .RESVAL (2'h2),
28426 .Mubi (1'b0)
28427 ) u_mio_pad_sleep_mode_39 (
28428 .clk_i (clk_i),
28429 .rst_ni (rst_ni),
28430
28431 // from register interface
28432 .we (mio_pad_sleep_mode_39_gated_we),
28433 .wd (mio_pad_sleep_mode_39_wd),
28434
28435 // from internal hardware
28436 .de (1'b0),
28437 .d ('0),
28438
28439 // to internal hardware
28440 .qe (),
28441 .q (reg2hw.mio_pad_sleep_mode[39].q),
28442 .ds (),
28443
28444 // to register interface (read)
28445 .qs (mio_pad_sleep_mode_39_qs)
28446 );
28447
28448
28449 // Subregister 40 of Multireg mio_pad_sleep_mode
28450 // R[mio_pad_sleep_mode_40]: V(False)
28451 // Create REGWEN-gated WE signal
28452 logic mio_pad_sleep_mode_40_gated_we;
28453 1/1 assign mio_pad_sleep_mode_40_gated_we = mio_pad_sleep_mode_40_we & mio_pad_sleep_regwen_40_qs;
Tests: T2 T19 T40
28454 prim_subreg #(
28455 .DW (2),
28456 .SwAccess(prim_subreg_pkg::SwAccessRW),
28457 .RESVAL (2'h2),
28458 .Mubi (1'b0)
28459 ) u_mio_pad_sleep_mode_40 (
28460 .clk_i (clk_i),
28461 .rst_ni (rst_ni),
28462
28463 // from register interface
28464 .we (mio_pad_sleep_mode_40_gated_we),
28465 .wd (mio_pad_sleep_mode_40_wd),
28466
28467 // from internal hardware
28468 .de (1'b0),
28469 .d ('0),
28470
28471 // to internal hardware
28472 .qe (),
28473 .q (reg2hw.mio_pad_sleep_mode[40].q),
28474 .ds (),
28475
28476 // to register interface (read)
28477 .qs (mio_pad_sleep_mode_40_qs)
28478 );
28479
28480
28481 // Subregister 41 of Multireg mio_pad_sleep_mode
28482 // R[mio_pad_sleep_mode_41]: V(False)
28483 // Create REGWEN-gated WE signal
28484 logic mio_pad_sleep_mode_41_gated_we;
28485 1/1 assign mio_pad_sleep_mode_41_gated_we = mio_pad_sleep_mode_41_we & mio_pad_sleep_regwen_41_qs;
Tests: T2 T19 T40
28486 prim_subreg #(
28487 .DW (2),
28488 .SwAccess(prim_subreg_pkg::SwAccessRW),
28489 .RESVAL (2'h2),
28490 .Mubi (1'b0)
28491 ) u_mio_pad_sleep_mode_41 (
28492 .clk_i (clk_i),
28493 .rst_ni (rst_ni),
28494
28495 // from register interface
28496 .we (mio_pad_sleep_mode_41_gated_we),
28497 .wd (mio_pad_sleep_mode_41_wd),
28498
28499 // from internal hardware
28500 .de (1'b0),
28501 .d ('0),
28502
28503 // to internal hardware
28504 .qe (),
28505 .q (reg2hw.mio_pad_sleep_mode[41].q),
28506 .ds (),
28507
28508 // to register interface (read)
28509 .qs (mio_pad_sleep_mode_41_qs)
28510 );
28511
28512
28513 // Subregister 42 of Multireg mio_pad_sleep_mode
28514 // R[mio_pad_sleep_mode_42]: V(False)
28515 // Create REGWEN-gated WE signal
28516 logic mio_pad_sleep_mode_42_gated_we;
28517 1/1 assign mio_pad_sleep_mode_42_gated_we = mio_pad_sleep_mode_42_we & mio_pad_sleep_regwen_42_qs;
Tests: T2 T19 T40
28518 prim_subreg #(
28519 .DW (2),
28520 .SwAccess(prim_subreg_pkg::SwAccessRW),
28521 .RESVAL (2'h2),
28522 .Mubi (1'b0)
28523 ) u_mio_pad_sleep_mode_42 (
28524 .clk_i (clk_i),
28525 .rst_ni (rst_ni),
28526
28527 // from register interface
28528 .we (mio_pad_sleep_mode_42_gated_we),
28529 .wd (mio_pad_sleep_mode_42_wd),
28530
28531 // from internal hardware
28532 .de (1'b0),
28533 .d ('0),
28534
28535 // to internal hardware
28536 .qe (),
28537 .q (reg2hw.mio_pad_sleep_mode[42].q),
28538 .ds (),
28539
28540 // to register interface (read)
28541 .qs (mio_pad_sleep_mode_42_qs)
28542 );
28543
28544
28545 // Subregister 43 of Multireg mio_pad_sleep_mode
28546 // R[mio_pad_sleep_mode_43]: V(False)
28547 // Create REGWEN-gated WE signal
28548 logic mio_pad_sleep_mode_43_gated_we;
28549 1/1 assign mio_pad_sleep_mode_43_gated_we = mio_pad_sleep_mode_43_we & mio_pad_sleep_regwen_43_qs;
Tests: T2 T19 T40
28550 prim_subreg #(
28551 .DW (2),
28552 .SwAccess(prim_subreg_pkg::SwAccessRW),
28553 .RESVAL (2'h2),
28554 .Mubi (1'b0)
28555 ) u_mio_pad_sleep_mode_43 (
28556 .clk_i (clk_i),
28557 .rst_ni (rst_ni),
28558
28559 // from register interface
28560 .we (mio_pad_sleep_mode_43_gated_we),
28561 .wd (mio_pad_sleep_mode_43_wd),
28562
28563 // from internal hardware
28564 .de (1'b0),
28565 .d ('0),
28566
28567 // to internal hardware
28568 .qe (),
28569 .q (reg2hw.mio_pad_sleep_mode[43].q),
28570 .ds (),
28571
28572 // to register interface (read)
28573 .qs (mio_pad_sleep_mode_43_qs)
28574 );
28575
28576
28577 // Subregister 44 of Multireg mio_pad_sleep_mode
28578 // R[mio_pad_sleep_mode_44]: V(False)
28579 // Create REGWEN-gated WE signal
28580 logic mio_pad_sleep_mode_44_gated_we;
28581 1/1 assign mio_pad_sleep_mode_44_gated_we = mio_pad_sleep_mode_44_we & mio_pad_sleep_regwen_44_qs;
Tests: T2 T19 T40
28582 prim_subreg #(
28583 .DW (2),
28584 .SwAccess(prim_subreg_pkg::SwAccessRW),
28585 .RESVAL (2'h2),
28586 .Mubi (1'b0)
28587 ) u_mio_pad_sleep_mode_44 (
28588 .clk_i (clk_i),
28589 .rst_ni (rst_ni),
28590
28591 // from register interface
28592 .we (mio_pad_sleep_mode_44_gated_we),
28593 .wd (mio_pad_sleep_mode_44_wd),
28594
28595 // from internal hardware
28596 .de (1'b0),
28597 .d ('0),
28598
28599 // to internal hardware
28600 .qe (),
28601 .q (reg2hw.mio_pad_sleep_mode[44].q),
28602 .ds (),
28603
28604 // to register interface (read)
28605 .qs (mio_pad_sleep_mode_44_qs)
28606 );
28607
28608
28609 // Subregister 45 of Multireg mio_pad_sleep_mode
28610 // R[mio_pad_sleep_mode_45]: V(False)
28611 // Create REGWEN-gated WE signal
28612 logic mio_pad_sleep_mode_45_gated_we;
28613 1/1 assign mio_pad_sleep_mode_45_gated_we = mio_pad_sleep_mode_45_we & mio_pad_sleep_regwen_45_qs;
Tests: T2 T19 T40
28614 prim_subreg #(
28615 .DW (2),
28616 .SwAccess(prim_subreg_pkg::SwAccessRW),
28617 .RESVAL (2'h2),
28618 .Mubi (1'b0)
28619 ) u_mio_pad_sleep_mode_45 (
28620 .clk_i (clk_i),
28621 .rst_ni (rst_ni),
28622
28623 // from register interface
28624 .we (mio_pad_sleep_mode_45_gated_we),
28625 .wd (mio_pad_sleep_mode_45_wd),
28626
28627 // from internal hardware
28628 .de (1'b0),
28629 .d ('0),
28630
28631 // to internal hardware
28632 .qe (),
28633 .q (reg2hw.mio_pad_sleep_mode[45].q),
28634 .ds (),
28635
28636 // to register interface (read)
28637 .qs (mio_pad_sleep_mode_45_qs)
28638 );
28639
28640
28641 // Subregister 46 of Multireg mio_pad_sleep_mode
28642 // R[mio_pad_sleep_mode_46]: V(False)
28643 // Create REGWEN-gated WE signal
28644 logic mio_pad_sleep_mode_46_gated_we;
28645 1/1 assign mio_pad_sleep_mode_46_gated_we = mio_pad_sleep_mode_46_we & mio_pad_sleep_regwen_46_qs;
Tests: T2 T19 T40
28646 prim_subreg #(
28647 .DW (2),
28648 .SwAccess(prim_subreg_pkg::SwAccessRW),
28649 .RESVAL (2'h2),
28650 .Mubi (1'b0)
28651 ) u_mio_pad_sleep_mode_46 (
28652 .clk_i (clk_i),
28653 .rst_ni (rst_ni),
28654
28655 // from register interface
28656 .we (mio_pad_sleep_mode_46_gated_we),
28657 .wd (mio_pad_sleep_mode_46_wd),
28658
28659 // from internal hardware
28660 .de (1'b0),
28661 .d ('0),
28662
28663 // to internal hardware
28664 .qe (),
28665 .q (reg2hw.mio_pad_sleep_mode[46].q),
28666 .ds (),
28667
28668 // to register interface (read)
28669 .qs (mio_pad_sleep_mode_46_qs)
28670 );
28671
28672
28673 // Subregister 0 of Multireg dio_pad_sleep_status
28674 // R[dio_pad_sleep_status]: V(False)
28675 // F[en_0]: 0:0
28676 prim_subreg #(
28677 .DW (1),
28678 .SwAccess(prim_subreg_pkg::SwAccessW0C),
28679 .RESVAL (1'h0),
28680 .Mubi (1'b0)
28681 ) u_dio_pad_sleep_status_en_0 (
28682 .clk_i (clk_i),
28683 .rst_ni (rst_ni),
28684
28685 // from register interface
28686 .we (dio_pad_sleep_status_we),
28687 .wd (dio_pad_sleep_status_en_0_wd),
28688
28689 // from internal hardware
28690 .de (hw2reg.dio_pad_sleep_status[0].de),
28691 .d (hw2reg.dio_pad_sleep_status[0].d),
28692
28693 // to internal hardware
28694 .qe (),
28695 .q (reg2hw.dio_pad_sleep_status[0].q),
28696 .ds (),
28697
28698 // to register interface (read)
28699 .qs (dio_pad_sleep_status_en_0_qs)
28700 );
28701
28702 // F[en_1]: 1:1
28703 prim_subreg #(
28704 .DW (1),
28705 .SwAccess(prim_subreg_pkg::SwAccessW0C),
28706 .RESVAL (1'h0),
28707 .Mubi (1'b0)
28708 ) u_dio_pad_sleep_status_en_1 (
28709 .clk_i (clk_i),
28710 .rst_ni (rst_ni),
28711
28712 // from register interface
28713 .we (dio_pad_sleep_status_we),
28714 .wd (dio_pad_sleep_status_en_1_wd),
28715
28716 // from internal hardware
28717 .de (hw2reg.dio_pad_sleep_status[1].de),
28718 .d (hw2reg.dio_pad_sleep_status[1].d),
28719
28720 // to internal hardware
28721 .qe (),
28722 .q (reg2hw.dio_pad_sleep_status[1].q),
28723 .ds (),
28724
28725 // to register interface (read)
28726 .qs (dio_pad_sleep_status_en_1_qs)
28727 );
28728
28729 // F[en_2]: 2:2
28730 prim_subreg #(
28731 .DW (1),
28732 .SwAccess(prim_subreg_pkg::SwAccessW0C),
28733 .RESVAL (1'h0),
28734 .Mubi (1'b0)
28735 ) u_dio_pad_sleep_status_en_2 (
28736 .clk_i (clk_i),
28737 .rst_ni (rst_ni),
28738
28739 // from register interface
28740 .we (dio_pad_sleep_status_we),
28741 .wd (dio_pad_sleep_status_en_2_wd),
28742
28743 // from internal hardware
28744 .de (hw2reg.dio_pad_sleep_status[2].de),
28745 .d (hw2reg.dio_pad_sleep_status[2].d),
28746
28747 // to internal hardware
28748 .qe (),
28749 .q (reg2hw.dio_pad_sleep_status[2].q),
28750 .ds (),
28751
28752 // to register interface (read)
28753 .qs (dio_pad_sleep_status_en_2_qs)
28754 );
28755
28756 // F[en_3]: 3:3
28757 prim_subreg #(
28758 .DW (1),
28759 .SwAccess(prim_subreg_pkg::SwAccessW0C),
28760 .RESVAL (1'h0),
28761 .Mubi (1'b0)
28762 ) u_dio_pad_sleep_status_en_3 (
28763 .clk_i (clk_i),
28764 .rst_ni (rst_ni),
28765
28766 // from register interface
28767 .we (dio_pad_sleep_status_we),
28768 .wd (dio_pad_sleep_status_en_3_wd),
28769
28770 // from internal hardware
28771 .de (hw2reg.dio_pad_sleep_status[3].de),
28772 .d (hw2reg.dio_pad_sleep_status[3].d),
28773
28774 // to internal hardware
28775 .qe (),
28776 .q (reg2hw.dio_pad_sleep_status[3].q),
28777 .ds (),
28778
28779 // to register interface (read)
28780 .qs (dio_pad_sleep_status_en_3_qs)
28781 );
28782
28783 // F[en_4]: 4:4
28784 prim_subreg #(
28785 .DW (1),
28786 .SwAccess(prim_subreg_pkg::SwAccessW0C),
28787 .RESVAL (1'h0),
28788 .Mubi (1'b0)
28789 ) u_dio_pad_sleep_status_en_4 (
28790 .clk_i (clk_i),
28791 .rst_ni (rst_ni),
28792
28793 // from register interface
28794 .we (dio_pad_sleep_status_we),
28795 .wd (dio_pad_sleep_status_en_4_wd),
28796
28797 // from internal hardware
28798 .de (hw2reg.dio_pad_sleep_status[4].de),
28799 .d (hw2reg.dio_pad_sleep_status[4].d),
28800
28801 // to internal hardware
28802 .qe (),
28803 .q (reg2hw.dio_pad_sleep_status[4].q),
28804 .ds (),
28805
28806 // to register interface (read)
28807 .qs (dio_pad_sleep_status_en_4_qs)
28808 );
28809
28810 // F[en_5]: 5:5
28811 prim_subreg #(
28812 .DW (1),
28813 .SwAccess(prim_subreg_pkg::SwAccessW0C),
28814 .RESVAL (1'h0),
28815 .Mubi (1'b0)
28816 ) u_dio_pad_sleep_status_en_5 (
28817 .clk_i (clk_i),
28818 .rst_ni (rst_ni),
28819
28820 // from register interface
28821 .we (dio_pad_sleep_status_we),
28822 .wd (dio_pad_sleep_status_en_5_wd),
28823
28824 // from internal hardware
28825 .de (hw2reg.dio_pad_sleep_status[5].de),
28826 .d (hw2reg.dio_pad_sleep_status[5].d),
28827
28828 // to internal hardware
28829 .qe (),
28830 .q (reg2hw.dio_pad_sleep_status[5].q),
28831 .ds (),
28832
28833 // to register interface (read)
28834 .qs (dio_pad_sleep_status_en_5_qs)
28835 );
28836
28837 // F[en_6]: 6:6
28838 prim_subreg #(
28839 .DW (1),
28840 .SwAccess(prim_subreg_pkg::SwAccessW0C),
28841 .RESVAL (1'h0),
28842 .Mubi (1'b0)
28843 ) u_dio_pad_sleep_status_en_6 (
28844 .clk_i (clk_i),
28845 .rst_ni (rst_ni),
28846
28847 // from register interface
28848 .we (dio_pad_sleep_status_we),
28849 .wd (dio_pad_sleep_status_en_6_wd),
28850
28851 // from internal hardware
28852 .de (hw2reg.dio_pad_sleep_status[6].de),
28853 .d (hw2reg.dio_pad_sleep_status[6].d),
28854
28855 // to internal hardware
28856 .qe (),
28857 .q (reg2hw.dio_pad_sleep_status[6].q),
28858 .ds (),
28859
28860 // to register interface (read)
28861 .qs (dio_pad_sleep_status_en_6_qs)
28862 );
28863
28864 // F[en_7]: 7:7
28865 prim_subreg #(
28866 .DW (1),
28867 .SwAccess(prim_subreg_pkg::SwAccessW0C),
28868 .RESVAL (1'h0),
28869 .Mubi (1'b0)
28870 ) u_dio_pad_sleep_status_en_7 (
28871 .clk_i (clk_i),
28872 .rst_ni (rst_ni),
28873
28874 // from register interface
28875 .we (dio_pad_sleep_status_we),
28876 .wd (dio_pad_sleep_status_en_7_wd),
28877
28878 // from internal hardware
28879 .de (hw2reg.dio_pad_sleep_status[7].de),
28880 .d (hw2reg.dio_pad_sleep_status[7].d),
28881
28882 // to internal hardware
28883 .qe (),
28884 .q (reg2hw.dio_pad_sleep_status[7].q),
28885 .ds (),
28886
28887 // to register interface (read)
28888 .qs (dio_pad_sleep_status_en_7_qs)
28889 );
28890
28891 // F[en_8]: 8:8
28892 prim_subreg #(
28893 .DW (1),
28894 .SwAccess(prim_subreg_pkg::SwAccessW0C),
28895 .RESVAL (1'h0),
28896 .Mubi (1'b0)
28897 ) u_dio_pad_sleep_status_en_8 (
28898 .clk_i (clk_i),
28899 .rst_ni (rst_ni),
28900
28901 // from register interface
28902 .we (dio_pad_sleep_status_we),
28903 .wd (dio_pad_sleep_status_en_8_wd),
28904
28905 // from internal hardware
28906 .de (hw2reg.dio_pad_sleep_status[8].de),
28907 .d (hw2reg.dio_pad_sleep_status[8].d),
28908
28909 // to internal hardware
28910 .qe (),
28911 .q (reg2hw.dio_pad_sleep_status[8].q),
28912 .ds (),
28913
28914 // to register interface (read)
28915 .qs (dio_pad_sleep_status_en_8_qs)
28916 );
28917
28918 // F[en_9]: 9:9
28919 prim_subreg #(
28920 .DW (1),
28921 .SwAccess(prim_subreg_pkg::SwAccessW0C),
28922 .RESVAL (1'h0),
28923 .Mubi (1'b0)
28924 ) u_dio_pad_sleep_status_en_9 (
28925 .clk_i (clk_i),
28926 .rst_ni (rst_ni),
28927
28928 // from register interface
28929 .we (dio_pad_sleep_status_we),
28930 .wd (dio_pad_sleep_status_en_9_wd),
28931
28932 // from internal hardware
28933 .de (hw2reg.dio_pad_sleep_status[9].de),
28934 .d (hw2reg.dio_pad_sleep_status[9].d),
28935
28936 // to internal hardware
28937 .qe (),
28938 .q (reg2hw.dio_pad_sleep_status[9].q),
28939 .ds (),
28940
28941 // to register interface (read)
28942 .qs (dio_pad_sleep_status_en_9_qs)
28943 );
28944
28945 // F[en_10]: 10:10
28946 prim_subreg #(
28947 .DW (1),
28948 .SwAccess(prim_subreg_pkg::SwAccessW0C),
28949 .RESVAL (1'h0),
28950 .Mubi (1'b0)
28951 ) u_dio_pad_sleep_status_en_10 (
28952 .clk_i (clk_i),
28953 .rst_ni (rst_ni),
28954
28955 // from register interface
28956 .we (dio_pad_sleep_status_we),
28957 .wd (dio_pad_sleep_status_en_10_wd),
28958
28959 // from internal hardware
28960 .de (hw2reg.dio_pad_sleep_status[10].de),
28961 .d (hw2reg.dio_pad_sleep_status[10].d),
28962
28963 // to internal hardware
28964 .qe (),
28965 .q (reg2hw.dio_pad_sleep_status[10].q),
28966 .ds (),
28967
28968 // to register interface (read)
28969 .qs (dio_pad_sleep_status_en_10_qs)
28970 );
28971
28972 // F[en_11]: 11:11
28973 prim_subreg #(
28974 .DW (1),
28975 .SwAccess(prim_subreg_pkg::SwAccessW0C),
28976 .RESVAL (1'h0),
28977 .Mubi (1'b0)
28978 ) u_dio_pad_sleep_status_en_11 (
28979 .clk_i (clk_i),
28980 .rst_ni (rst_ni),
28981
28982 // from register interface
28983 .we (dio_pad_sleep_status_we),
28984 .wd (dio_pad_sleep_status_en_11_wd),
28985
28986 // from internal hardware
28987 .de (hw2reg.dio_pad_sleep_status[11].de),
28988 .d (hw2reg.dio_pad_sleep_status[11].d),
28989
28990 // to internal hardware
28991 .qe (),
28992 .q (reg2hw.dio_pad_sleep_status[11].q),
28993 .ds (),
28994
28995 // to register interface (read)
28996 .qs (dio_pad_sleep_status_en_11_qs)
28997 );
28998
28999 // F[en_12]: 12:12
29000 prim_subreg #(
29001 .DW (1),
29002 .SwAccess(prim_subreg_pkg::SwAccessW0C),
29003 .RESVAL (1'h0),
29004 .Mubi (1'b0)
29005 ) u_dio_pad_sleep_status_en_12 (
29006 .clk_i (clk_i),
29007 .rst_ni (rst_ni),
29008
29009 // from register interface
29010 .we (dio_pad_sleep_status_we),
29011 .wd (dio_pad_sleep_status_en_12_wd),
29012
29013 // from internal hardware
29014 .de (hw2reg.dio_pad_sleep_status[12].de),
29015 .d (hw2reg.dio_pad_sleep_status[12].d),
29016
29017 // to internal hardware
29018 .qe (),
29019 .q (reg2hw.dio_pad_sleep_status[12].q),
29020 .ds (),
29021
29022 // to register interface (read)
29023 .qs (dio_pad_sleep_status_en_12_qs)
29024 );
29025
29026 // F[en_13]: 13:13
29027 prim_subreg #(
29028 .DW (1),
29029 .SwAccess(prim_subreg_pkg::SwAccessW0C),
29030 .RESVAL (1'h0),
29031 .Mubi (1'b0)
29032 ) u_dio_pad_sleep_status_en_13 (
29033 .clk_i (clk_i),
29034 .rst_ni (rst_ni),
29035
29036 // from register interface
29037 .we (dio_pad_sleep_status_we),
29038 .wd (dio_pad_sleep_status_en_13_wd),
29039
29040 // from internal hardware
29041 .de (hw2reg.dio_pad_sleep_status[13].de),
29042 .d (hw2reg.dio_pad_sleep_status[13].d),
29043
29044 // to internal hardware
29045 .qe (),
29046 .q (reg2hw.dio_pad_sleep_status[13].q),
29047 .ds (),
29048
29049 // to register interface (read)
29050 .qs (dio_pad_sleep_status_en_13_qs)
29051 );
29052
29053 // F[en_14]: 14:14
29054 prim_subreg #(
29055 .DW (1),
29056 .SwAccess(prim_subreg_pkg::SwAccessW0C),
29057 .RESVAL (1'h0),
29058 .Mubi (1'b0)
29059 ) u_dio_pad_sleep_status_en_14 (
29060 .clk_i (clk_i),
29061 .rst_ni (rst_ni),
29062
29063 // from register interface
29064 .we (dio_pad_sleep_status_we),
29065 .wd (dio_pad_sleep_status_en_14_wd),
29066
29067 // from internal hardware
29068 .de (hw2reg.dio_pad_sleep_status[14].de),
29069 .d (hw2reg.dio_pad_sleep_status[14].d),
29070
29071 // to internal hardware
29072 .qe (),
29073 .q (reg2hw.dio_pad_sleep_status[14].q),
29074 .ds (),
29075
29076 // to register interface (read)
29077 .qs (dio_pad_sleep_status_en_14_qs)
29078 );
29079
29080 // F[en_15]: 15:15
29081 prim_subreg #(
29082 .DW (1),
29083 .SwAccess(prim_subreg_pkg::SwAccessW0C),
29084 .RESVAL (1'h0),
29085 .Mubi (1'b0)
29086 ) u_dio_pad_sleep_status_en_15 (
29087 .clk_i (clk_i),
29088 .rst_ni (rst_ni),
29089
29090 // from register interface
29091 .we (dio_pad_sleep_status_we),
29092 .wd (dio_pad_sleep_status_en_15_wd),
29093
29094 // from internal hardware
29095 .de (hw2reg.dio_pad_sleep_status[15].de),
29096 .d (hw2reg.dio_pad_sleep_status[15].d),
29097
29098 // to internal hardware
29099 .qe (),
29100 .q (reg2hw.dio_pad_sleep_status[15].q),
29101 .ds (),
29102
29103 // to register interface (read)
29104 .qs (dio_pad_sleep_status_en_15_qs)
29105 );
29106
29107
29108 // Subregister 0 of Multireg dio_pad_sleep_regwen
29109 // R[dio_pad_sleep_regwen_0]: V(False)
29110 prim_subreg #(
29111 .DW (1),
29112 .SwAccess(prim_subreg_pkg::SwAccessW0C),
29113 .RESVAL (1'h1),
29114 .Mubi (1'b0)
29115 ) u_dio_pad_sleep_regwen_0 (
29116 .clk_i (clk_i),
29117 .rst_ni (rst_ni),
29118
29119 // from register interface
29120 .we (dio_pad_sleep_regwen_0_we),
29121 .wd (dio_pad_sleep_regwen_0_wd),
29122
29123 // from internal hardware
29124 .de (1'b0),
29125 .d ('0),
29126
29127 // to internal hardware
29128 .qe (),
29129 .q (),
29130 .ds (),
29131
29132 // to register interface (read)
29133 .qs (dio_pad_sleep_regwen_0_qs)
29134 );
29135
29136
29137 // Subregister 1 of Multireg dio_pad_sleep_regwen
29138 // R[dio_pad_sleep_regwen_1]: V(False)
29139 prim_subreg #(
29140 .DW (1),
29141 .SwAccess(prim_subreg_pkg::SwAccessW0C),
29142 .RESVAL (1'h1),
29143 .Mubi (1'b0)
29144 ) u_dio_pad_sleep_regwen_1 (
29145 .clk_i (clk_i),
29146 .rst_ni (rst_ni),
29147
29148 // from register interface
29149 .we (dio_pad_sleep_regwen_1_we),
29150 .wd (dio_pad_sleep_regwen_1_wd),
29151
29152 // from internal hardware
29153 .de (1'b0),
29154 .d ('0),
29155
29156 // to internal hardware
29157 .qe (),
29158 .q (),
29159 .ds (),
29160
29161 // to register interface (read)
29162 .qs (dio_pad_sleep_regwen_1_qs)
29163 );
29164
29165
29166 // Subregister 2 of Multireg dio_pad_sleep_regwen
29167 // R[dio_pad_sleep_regwen_2]: V(False)
29168 prim_subreg #(
29169 .DW (1),
29170 .SwAccess(prim_subreg_pkg::SwAccessW0C),
29171 .RESVAL (1'h1),
29172 .Mubi (1'b0)
29173 ) u_dio_pad_sleep_regwen_2 (
29174 .clk_i (clk_i),
29175 .rst_ni (rst_ni),
29176
29177 // from register interface
29178 .we (dio_pad_sleep_regwen_2_we),
29179 .wd (dio_pad_sleep_regwen_2_wd),
29180
29181 // from internal hardware
29182 .de (1'b0),
29183 .d ('0),
29184
29185 // to internal hardware
29186 .qe (),
29187 .q (),
29188 .ds (),
29189
29190 // to register interface (read)
29191 .qs (dio_pad_sleep_regwen_2_qs)
29192 );
29193
29194
29195 // Subregister 3 of Multireg dio_pad_sleep_regwen
29196 // R[dio_pad_sleep_regwen_3]: V(False)
29197 prim_subreg #(
29198 .DW (1),
29199 .SwAccess(prim_subreg_pkg::SwAccessW0C),
29200 .RESVAL (1'h1),
29201 .Mubi (1'b0)
29202 ) u_dio_pad_sleep_regwen_3 (
29203 .clk_i (clk_i),
29204 .rst_ni (rst_ni),
29205
29206 // from register interface
29207 .we (dio_pad_sleep_regwen_3_we),
29208 .wd (dio_pad_sleep_regwen_3_wd),
29209
29210 // from internal hardware
29211 .de (1'b0),
29212 .d ('0),
29213
29214 // to internal hardware
29215 .qe (),
29216 .q (),
29217 .ds (),
29218
29219 // to register interface (read)
29220 .qs (dio_pad_sleep_regwen_3_qs)
29221 );
29222
29223
29224 // Subregister 4 of Multireg dio_pad_sleep_regwen
29225 // R[dio_pad_sleep_regwen_4]: V(False)
29226 prim_subreg #(
29227 .DW (1),
29228 .SwAccess(prim_subreg_pkg::SwAccessW0C),
29229 .RESVAL (1'h1),
29230 .Mubi (1'b0)
29231 ) u_dio_pad_sleep_regwen_4 (
29232 .clk_i (clk_i),
29233 .rst_ni (rst_ni),
29234
29235 // from register interface
29236 .we (dio_pad_sleep_regwen_4_we),
29237 .wd (dio_pad_sleep_regwen_4_wd),
29238
29239 // from internal hardware
29240 .de (1'b0),
29241 .d ('0),
29242
29243 // to internal hardware
29244 .qe (),
29245 .q (),
29246 .ds (),
29247
29248 // to register interface (read)
29249 .qs (dio_pad_sleep_regwen_4_qs)
29250 );
29251
29252
29253 // Subregister 5 of Multireg dio_pad_sleep_regwen
29254 // R[dio_pad_sleep_regwen_5]: V(False)
29255 prim_subreg #(
29256 .DW (1),
29257 .SwAccess(prim_subreg_pkg::SwAccessW0C),
29258 .RESVAL (1'h1),
29259 .Mubi (1'b0)
29260 ) u_dio_pad_sleep_regwen_5 (
29261 .clk_i (clk_i),
29262 .rst_ni (rst_ni),
29263
29264 // from register interface
29265 .we (dio_pad_sleep_regwen_5_we),
29266 .wd (dio_pad_sleep_regwen_5_wd),
29267
29268 // from internal hardware
29269 .de (1'b0),
29270 .d ('0),
29271
29272 // to internal hardware
29273 .qe (),
29274 .q (),
29275 .ds (),
29276
29277 // to register interface (read)
29278 .qs (dio_pad_sleep_regwen_5_qs)
29279 );
29280
29281
29282 // Subregister 6 of Multireg dio_pad_sleep_regwen
29283 // R[dio_pad_sleep_regwen_6]: V(False)
29284 prim_subreg #(
29285 .DW (1),
29286 .SwAccess(prim_subreg_pkg::SwAccessW0C),
29287 .RESVAL (1'h1),
29288 .Mubi (1'b0)
29289 ) u_dio_pad_sleep_regwen_6 (
29290 .clk_i (clk_i),
29291 .rst_ni (rst_ni),
29292
29293 // from register interface
29294 .we (dio_pad_sleep_regwen_6_we),
29295 .wd (dio_pad_sleep_regwen_6_wd),
29296
29297 // from internal hardware
29298 .de (1'b0),
29299 .d ('0),
29300
29301 // to internal hardware
29302 .qe (),
29303 .q (),
29304 .ds (),
29305
29306 // to register interface (read)
29307 .qs (dio_pad_sleep_regwen_6_qs)
29308 );
29309
29310
29311 // Subregister 7 of Multireg dio_pad_sleep_regwen
29312 // R[dio_pad_sleep_regwen_7]: V(False)
29313 prim_subreg #(
29314 .DW (1),
29315 .SwAccess(prim_subreg_pkg::SwAccessW0C),
29316 .RESVAL (1'h1),
29317 .Mubi (1'b0)
29318 ) u_dio_pad_sleep_regwen_7 (
29319 .clk_i (clk_i),
29320 .rst_ni (rst_ni),
29321
29322 // from register interface
29323 .we (dio_pad_sleep_regwen_7_we),
29324 .wd (dio_pad_sleep_regwen_7_wd),
29325
29326 // from internal hardware
29327 .de (1'b0),
29328 .d ('0),
29329
29330 // to internal hardware
29331 .qe (),
29332 .q (),
29333 .ds (),
29334
29335 // to register interface (read)
29336 .qs (dio_pad_sleep_regwen_7_qs)
29337 );
29338
29339
29340 // Subregister 8 of Multireg dio_pad_sleep_regwen
29341 // R[dio_pad_sleep_regwen_8]: V(False)
29342 prim_subreg #(
29343 .DW (1),
29344 .SwAccess(prim_subreg_pkg::SwAccessW0C),
29345 .RESVAL (1'h1),
29346 .Mubi (1'b0)
29347 ) u_dio_pad_sleep_regwen_8 (
29348 .clk_i (clk_i),
29349 .rst_ni (rst_ni),
29350
29351 // from register interface
29352 .we (dio_pad_sleep_regwen_8_we),
29353 .wd (dio_pad_sleep_regwen_8_wd),
29354
29355 // from internal hardware
29356 .de (1'b0),
29357 .d ('0),
29358
29359 // to internal hardware
29360 .qe (),
29361 .q (),
29362 .ds (),
29363
29364 // to register interface (read)
29365 .qs (dio_pad_sleep_regwen_8_qs)
29366 );
29367
29368
29369 // Subregister 9 of Multireg dio_pad_sleep_regwen
29370 // R[dio_pad_sleep_regwen_9]: V(False)
29371 prim_subreg #(
29372 .DW (1),
29373 .SwAccess(prim_subreg_pkg::SwAccessW0C),
29374 .RESVAL (1'h1),
29375 .Mubi (1'b0)
29376 ) u_dio_pad_sleep_regwen_9 (
29377 .clk_i (clk_i),
29378 .rst_ni (rst_ni),
29379
29380 // from register interface
29381 .we (dio_pad_sleep_regwen_9_we),
29382 .wd (dio_pad_sleep_regwen_9_wd),
29383
29384 // from internal hardware
29385 .de (1'b0),
29386 .d ('0),
29387
29388 // to internal hardware
29389 .qe (),
29390 .q (),
29391 .ds (),
29392
29393 // to register interface (read)
29394 .qs (dio_pad_sleep_regwen_9_qs)
29395 );
29396
29397
29398 // Subregister 10 of Multireg dio_pad_sleep_regwen
29399 // R[dio_pad_sleep_regwen_10]: V(False)
29400 prim_subreg #(
29401 .DW (1),
29402 .SwAccess(prim_subreg_pkg::SwAccessW0C),
29403 .RESVAL (1'h1),
29404 .Mubi (1'b0)
29405 ) u_dio_pad_sleep_regwen_10 (
29406 .clk_i (clk_i),
29407 .rst_ni (rst_ni),
29408
29409 // from register interface
29410 .we (dio_pad_sleep_regwen_10_we),
29411 .wd (dio_pad_sleep_regwen_10_wd),
29412
29413 // from internal hardware
29414 .de (1'b0),
29415 .d ('0),
29416
29417 // to internal hardware
29418 .qe (),
29419 .q (),
29420 .ds (),
29421
29422 // to register interface (read)
29423 .qs (dio_pad_sleep_regwen_10_qs)
29424 );
29425
29426
29427 // Subregister 11 of Multireg dio_pad_sleep_regwen
29428 // R[dio_pad_sleep_regwen_11]: V(False)
29429 prim_subreg #(
29430 .DW (1),
29431 .SwAccess(prim_subreg_pkg::SwAccessW0C),
29432 .RESVAL (1'h1),
29433 .Mubi (1'b0)
29434 ) u_dio_pad_sleep_regwen_11 (
29435 .clk_i (clk_i),
29436 .rst_ni (rst_ni),
29437
29438 // from register interface
29439 .we (dio_pad_sleep_regwen_11_we),
29440 .wd (dio_pad_sleep_regwen_11_wd),
29441
29442 // from internal hardware
29443 .de (1'b0),
29444 .d ('0),
29445
29446 // to internal hardware
29447 .qe (),
29448 .q (),
29449 .ds (),
29450
29451 // to register interface (read)
29452 .qs (dio_pad_sleep_regwen_11_qs)
29453 );
29454
29455
29456 // Subregister 12 of Multireg dio_pad_sleep_regwen
29457 // R[dio_pad_sleep_regwen_12]: V(False)
29458 prim_subreg #(
29459 .DW (1),
29460 .SwAccess(prim_subreg_pkg::SwAccessW0C),
29461 .RESVAL (1'h1),
29462 .Mubi (1'b0)
29463 ) u_dio_pad_sleep_regwen_12 (
29464 .clk_i (clk_i),
29465 .rst_ni (rst_ni),
29466
29467 // from register interface
29468 .we (dio_pad_sleep_regwen_12_we),
29469 .wd (dio_pad_sleep_regwen_12_wd),
29470
29471 // from internal hardware
29472 .de (1'b0),
29473 .d ('0),
29474
29475 // to internal hardware
29476 .qe (),
29477 .q (),
29478 .ds (),
29479
29480 // to register interface (read)
29481 .qs (dio_pad_sleep_regwen_12_qs)
29482 );
29483
29484
29485 // Subregister 13 of Multireg dio_pad_sleep_regwen
29486 // R[dio_pad_sleep_regwen_13]: V(False)
29487 prim_subreg #(
29488 .DW (1),
29489 .SwAccess(prim_subreg_pkg::SwAccessW0C),
29490 .RESVAL (1'h1),
29491 .Mubi (1'b0)
29492 ) u_dio_pad_sleep_regwen_13 (
29493 .clk_i (clk_i),
29494 .rst_ni (rst_ni),
29495
29496 // from register interface
29497 .we (dio_pad_sleep_regwen_13_we),
29498 .wd (dio_pad_sleep_regwen_13_wd),
29499
29500 // from internal hardware
29501 .de (1'b0),
29502 .d ('0),
29503
29504 // to internal hardware
29505 .qe (),
29506 .q (),
29507 .ds (),
29508
29509 // to register interface (read)
29510 .qs (dio_pad_sleep_regwen_13_qs)
29511 );
29512
29513
29514 // Subregister 14 of Multireg dio_pad_sleep_regwen
29515 // R[dio_pad_sleep_regwen_14]: V(False)
29516 prim_subreg #(
29517 .DW (1),
29518 .SwAccess(prim_subreg_pkg::SwAccessW0C),
29519 .RESVAL (1'h1),
29520 .Mubi (1'b0)
29521 ) u_dio_pad_sleep_regwen_14 (
29522 .clk_i (clk_i),
29523 .rst_ni (rst_ni),
29524
29525 // from register interface
29526 .we (dio_pad_sleep_regwen_14_we),
29527 .wd (dio_pad_sleep_regwen_14_wd),
29528
29529 // from internal hardware
29530 .de (1'b0),
29531 .d ('0),
29532
29533 // to internal hardware
29534 .qe (),
29535 .q (),
29536 .ds (),
29537
29538 // to register interface (read)
29539 .qs (dio_pad_sleep_regwen_14_qs)
29540 );
29541
29542
29543 // Subregister 15 of Multireg dio_pad_sleep_regwen
29544 // R[dio_pad_sleep_regwen_15]: V(False)
29545 prim_subreg #(
29546 .DW (1),
29547 .SwAccess(prim_subreg_pkg::SwAccessW0C),
29548 .RESVAL (1'h1),
29549 .Mubi (1'b0)
29550 ) u_dio_pad_sleep_regwen_15 (
29551 .clk_i (clk_i),
29552 .rst_ni (rst_ni),
29553
29554 // from register interface
29555 .we (dio_pad_sleep_regwen_15_we),
29556 .wd (dio_pad_sleep_regwen_15_wd),
29557
29558 // from internal hardware
29559 .de (1'b0),
29560 .d ('0),
29561
29562 // to internal hardware
29563 .qe (),
29564 .q (),
29565 .ds (),
29566
29567 // to register interface (read)
29568 .qs (dio_pad_sleep_regwen_15_qs)
29569 );
29570
29571
29572 // Subregister 0 of Multireg dio_pad_sleep_en
29573 // R[dio_pad_sleep_en_0]: V(False)
29574 // Create REGWEN-gated WE signal
29575 logic dio_pad_sleep_en_0_gated_we;
29576 1/1 assign dio_pad_sleep_en_0_gated_we = dio_pad_sleep_en_0_we & dio_pad_sleep_regwen_0_qs;
Tests: T2 T19 T40
29577 prim_subreg #(
29578 .DW (1),
29579 .SwAccess(prim_subreg_pkg::SwAccessRW),
29580 .RESVAL (1'h0),
29581 .Mubi (1'b0)
29582 ) u_dio_pad_sleep_en_0 (
29583 .clk_i (clk_i),
29584 .rst_ni (rst_ni),
29585
29586 // from register interface
29587 .we (dio_pad_sleep_en_0_gated_we),
29588 .wd (dio_pad_sleep_en_0_wd),
29589
29590 // from internal hardware
29591 .de (1'b0),
29592 .d ('0),
29593
29594 // to internal hardware
29595 .qe (),
29596 .q (reg2hw.dio_pad_sleep_en[0].q),
29597 .ds (),
29598
29599 // to register interface (read)
29600 .qs (dio_pad_sleep_en_0_qs)
29601 );
29602
29603
29604 // Subregister 1 of Multireg dio_pad_sleep_en
29605 // R[dio_pad_sleep_en_1]: V(False)
29606 // Create REGWEN-gated WE signal
29607 logic dio_pad_sleep_en_1_gated_we;
29608 1/1 assign dio_pad_sleep_en_1_gated_we = dio_pad_sleep_en_1_we & dio_pad_sleep_regwen_1_qs;
Tests: T2 T19 T40
29609 prim_subreg #(
29610 .DW (1),
29611 .SwAccess(prim_subreg_pkg::SwAccessRW),
29612 .RESVAL (1'h0),
29613 .Mubi (1'b0)
29614 ) u_dio_pad_sleep_en_1 (
29615 .clk_i (clk_i),
29616 .rst_ni (rst_ni),
29617
29618 // from register interface
29619 .we (dio_pad_sleep_en_1_gated_we),
29620 .wd (dio_pad_sleep_en_1_wd),
29621
29622 // from internal hardware
29623 .de (1'b0),
29624 .d ('0),
29625
29626 // to internal hardware
29627 .qe (),
29628 .q (reg2hw.dio_pad_sleep_en[1].q),
29629 .ds (),
29630
29631 // to register interface (read)
29632 .qs (dio_pad_sleep_en_1_qs)
29633 );
29634
29635
29636 // Subregister 2 of Multireg dio_pad_sleep_en
29637 // R[dio_pad_sleep_en_2]: V(False)
29638 // Create REGWEN-gated WE signal
29639 logic dio_pad_sleep_en_2_gated_we;
29640 1/1 assign dio_pad_sleep_en_2_gated_we = dio_pad_sleep_en_2_we & dio_pad_sleep_regwen_2_qs;
Tests: T2 T19 T40
29641 prim_subreg #(
29642 .DW (1),
29643 .SwAccess(prim_subreg_pkg::SwAccessRW),
29644 .RESVAL (1'h0),
29645 .Mubi (1'b0)
29646 ) u_dio_pad_sleep_en_2 (
29647 .clk_i (clk_i),
29648 .rst_ni (rst_ni),
29649
29650 // from register interface
29651 .we (dio_pad_sleep_en_2_gated_we),
29652 .wd (dio_pad_sleep_en_2_wd),
29653
29654 // from internal hardware
29655 .de (1'b0),
29656 .d ('0),
29657
29658 // to internal hardware
29659 .qe (),
29660 .q (reg2hw.dio_pad_sleep_en[2].q),
29661 .ds (),
29662
29663 // to register interface (read)
29664 .qs (dio_pad_sleep_en_2_qs)
29665 );
29666
29667
29668 // Subregister 3 of Multireg dio_pad_sleep_en
29669 // R[dio_pad_sleep_en_3]: V(False)
29670 // Create REGWEN-gated WE signal
29671 logic dio_pad_sleep_en_3_gated_we;
29672 1/1 assign dio_pad_sleep_en_3_gated_we = dio_pad_sleep_en_3_we & dio_pad_sleep_regwen_3_qs;
Tests: T2 T19 T40
29673 prim_subreg #(
29674 .DW (1),
29675 .SwAccess(prim_subreg_pkg::SwAccessRW),
29676 .RESVAL (1'h0),
29677 .Mubi (1'b0)
29678 ) u_dio_pad_sleep_en_3 (
29679 .clk_i (clk_i),
29680 .rst_ni (rst_ni),
29681
29682 // from register interface
29683 .we (dio_pad_sleep_en_3_gated_we),
29684 .wd (dio_pad_sleep_en_3_wd),
29685
29686 // from internal hardware
29687 .de (1'b0),
29688 .d ('0),
29689
29690 // to internal hardware
29691 .qe (),
29692 .q (reg2hw.dio_pad_sleep_en[3].q),
29693 .ds (),
29694
29695 // to register interface (read)
29696 .qs (dio_pad_sleep_en_3_qs)
29697 );
29698
29699
29700 // Subregister 4 of Multireg dio_pad_sleep_en
29701 // R[dio_pad_sleep_en_4]: V(False)
29702 // Create REGWEN-gated WE signal
29703 logic dio_pad_sleep_en_4_gated_we;
29704 1/1 assign dio_pad_sleep_en_4_gated_we = dio_pad_sleep_en_4_we & dio_pad_sleep_regwen_4_qs;
Tests: T2 T19 T40
29705 prim_subreg #(
29706 .DW (1),
29707 .SwAccess(prim_subreg_pkg::SwAccessRW),
29708 .RESVAL (1'h0),
29709 .Mubi (1'b0)
29710 ) u_dio_pad_sleep_en_4 (
29711 .clk_i (clk_i),
29712 .rst_ni (rst_ni),
29713
29714 // from register interface
29715 .we (dio_pad_sleep_en_4_gated_we),
29716 .wd (dio_pad_sleep_en_4_wd),
29717
29718 // from internal hardware
29719 .de (1'b0),
29720 .d ('0),
29721
29722 // to internal hardware
29723 .qe (),
29724 .q (reg2hw.dio_pad_sleep_en[4].q),
29725 .ds (),
29726
29727 // to register interface (read)
29728 .qs (dio_pad_sleep_en_4_qs)
29729 );
29730
29731
29732 // Subregister 5 of Multireg dio_pad_sleep_en
29733 // R[dio_pad_sleep_en_5]: V(False)
29734 // Create REGWEN-gated WE signal
29735 logic dio_pad_sleep_en_5_gated_we;
29736 1/1 assign dio_pad_sleep_en_5_gated_we = dio_pad_sleep_en_5_we & dio_pad_sleep_regwen_5_qs;
Tests: T2 T19 T40
29737 prim_subreg #(
29738 .DW (1),
29739 .SwAccess(prim_subreg_pkg::SwAccessRW),
29740 .RESVAL (1'h0),
29741 .Mubi (1'b0)
29742 ) u_dio_pad_sleep_en_5 (
29743 .clk_i (clk_i),
29744 .rst_ni (rst_ni),
29745
29746 // from register interface
29747 .we (dio_pad_sleep_en_5_gated_we),
29748 .wd (dio_pad_sleep_en_5_wd),
29749
29750 // from internal hardware
29751 .de (1'b0),
29752 .d ('0),
29753
29754 // to internal hardware
29755 .qe (),
29756 .q (reg2hw.dio_pad_sleep_en[5].q),
29757 .ds (),
29758
29759 // to register interface (read)
29760 .qs (dio_pad_sleep_en_5_qs)
29761 );
29762
29763
29764 // Subregister 6 of Multireg dio_pad_sleep_en
29765 // R[dio_pad_sleep_en_6]: V(False)
29766 // Create REGWEN-gated WE signal
29767 logic dio_pad_sleep_en_6_gated_we;
29768 1/1 assign dio_pad_sleep_en_6_gated_we = dio_pad_sleep_en_6_we & dio_pad_sleep_regwen_6_qs;
Tests: T2 T6 T19
29769 prim_subreg #(
29770 .DW (1),
29771 .SwAccess(prim_subreg_pkg::SwAccessRW),
29772 .RESVAL (1'h0),
29773 .Mubi (1'b0)
29774 ) u_dio_pad_sleep_en_6 (
29775 .clk_i (clk_i),
29776 .rst_ni (rst_ni),
29777
29778 // from register interface
29779 .we (dio_pad_sleep_en_6_gated_we),
29780 .wd (dio_pad_sleep_en_6_wd),
29781
29782 // from internal hardware
29783 .de (1'b0),
29784 .d ('0),
29785
29786 // to internal hardware
29787 .qe (),
29788 .q (reg2hw.dio_pad_sleep_en[6].q),
29789 .ds (),
29790
29791 // to register interface (read)
29792 .qs (dio_pad_sleep_en_6_qs)
29793 );
29794
29795
29796 // Subregister 7 of Multireg dio_pad_sleep_en
29797 // R[dio_pad_sleep_en_7]: V(False)
29798 // Create REGWEN-gated WE signal
29799 logic dio_pad_sleep_en_7_gated_we;
29800 1/1 assign dio_pad_sleep_en_7_gated_we = dio_pad_sleep_en_7_we & dio_pad_sleep_regwen_7_qs;
Tests: T2 T6 T19
29801 prim_subreg #(
29802 .DW (1),
29803 .SwAccess(prim_subreg_pkg::SwAccessRW),
29804 .RESVAL (1'h0),
29805 .Mubi (1'b0)
29806 ) u_dio_pad_sleep_en_7 (
29807 .clk_i (clk_i),
29808 .rst_ni (rst_ni),
29809
29810 // from register interface
29811 .we (dio_pad_sleep_en_7_gated_we),
29812 .wd (dio_pad_sleep_en_7_wd),
29813
29814 // from internal hardware
29815 .de (1'b0),
29816 .d ('0),
29817
29818 // to internal hardware
29819 .qe (),
29820 .q (reg2hw.dio_pad_sleep_en[7].q),
29821 .ds (),
29822
29823 // to register interface (read)
29824 .qs (dio_pad_sleep_en_7_qs)
29825 );
29826
29827
29828 // Subregister 8 of Multireg dio_pad_sleep_en
29829 // R[dio_pad_sleep_en_8]: V(False)
29830 // Create REGWEN-gated WE signal
29831 logic dio_pad_sleep_en_8_gated_we;
29832 1/1 assign dio_pad_sleep_en_8_gated_we = dio_pad_sleep_en_8_we & dio_pad_sleep_regwen_8_qs;
Tests: T2 T6 T19
29833 prim_subreg #(
29834 .DW (1),
29835 .SwAccess(prim_subreg_pkg::SwAccessRW),
29836 .RESVAL (1'h0),
29837 .Mubi (1'b0)
29838 ) u_dio_pad_sleep_en_8 (
29839 .clk_i (clk_i),
29840 .rst_ni (rst_ni),
29841
29842 // from register interface
29843 .we (dio_pad_sleep_en_8_gated_we),
29844 .wd (dio_pad_sleep_en_8_wd),
29845
29846 // from internal hardware
29847 .de (1'b0),
29848 .d ('0),
29849
29850 // to internal hardware
29851 .qe (),
29852 .q (reg2hw.dio_pad_sleep_en[8].q),
29853 .ds (),
29854
29855 // to register interface (read)
29856 .qs (dio_pad_sleep_en_8_qs)
29857 );
29858
29859
29860 // Subregister 9 of Multireg dio_pad_sleep_en
29861 // R[dio_pad_sleep_en_9]: V(False)
29862 // Create REGWEN-gated WE signal
29863 logic dio_pad_sleep_en_9_gated_we;
29864 1/1 assign dio_pad_sleep_en_9_gated_we = dio_pad_sleep_en_9_we & dio_pad_sleep_regwen_9_qs;
Tests: T2 T6 T19
29865 prim_subreg #(
29866 .DW (1),
29867 .SwAccess(prim_subreg_pkg::SwAccessRW),
29868 .RESVAL (1'h0),
29869 .Mubi (1'b0)
29870 ) u_dio_pad_sleep_en_9 (
29871 .clk_i (clk_i),
29872 .rst_ni (rst_ni),
29873
29874 // from register interface
29875 .we (dio_pad_sleep_en_9_gated_we),
29876 .wd (dio_pad_sleep_en_9_wd),
29877
29878 // from internal hardware
29879 .de (1'b0),
29880 .d ('0),
29881
29882 // to internal hardware
29883 .qe (),
29884 .q (reg2hw.dio_pad_sleep_en[9].q),
29885 .ds (),
29886
29887 // to register interface (read)
29888 .qs (dio_pad_sleep_en_9_qs)
29889 );
29890
29891
29892 // Subregister 10 of Multireg dio_pad_sleep_en
29893 // R[dio_pad_sleep_en_10]: V(False)
29894 // Create REGWEN-gated WE signal
29895 logic dio_pad_sleep_en_10_gated_we;
29896 1/1 assign dio_pad_sleep_en_10_gated_we = dio_pad_sleep_en_10_we & dio_pad_sleep_regwen_10_qs;
Tests: T2 T19 T40
29897 prim_subreg #(
29898 .DW (1),
29899 .SwAccess(prim_subreg_pkg::SwAccessRW),
29900 .RESVAL (1'h0),
29901 .Mubi (1'b0)
29902 ) u_dio_pad_sleep_en_10 (
29903 .clk_i (clk_i),
29904 .rst_ni (rst_ni),
29905
29906 // from register interface
29907 .we (dio_pad_sleep_en_10_gated_we),
29908 .wd (dio_pad_sleep_en_10_wd),
29909
29910 // from internal hardware
29911 .de (1'b0),
29912 .d ('0),
29913
29914 // to internal hardware
29915 .qe (),
29916 .q (reg2hw.dio_pad_sleep_en[10].q),
29917 .ds (),
29918
29919 // to register interface (read)
29920 .qs (dio_pad_sleep_en_10_qs)
29921 );
29922
29923
29924 // Subregister 11 of Multireg dio_pad_sleep_en
29925 // R[dio_pad_sleep_en_11]: V(False)
29926 // Create REGWEN-gated WE signal
29927 logic dio_pad_sleep_en_11_gated_we;
29928 1/1 assign dio_pad_sleep_en_11_gated_we = dio_pad_sleep_en_11_we & dio_pad_sleep_regwen_11_qs;
Tests: T2 T19 T40
29929 prim_subreg #(
29930 .DW (1),
29931 .SwAccess(prim_subreg_pkg::SwAccessRW),
29932 .RESVAL (1'h0),
29933 .Mubi (1'b0)
29934 ) u_dio_pad_sleep_en_11 (
29935 .clk_i (clk_i),
29936 .rst_ni (rst_ni),
29937
29938 // from register interface
29939 .we (dio_pad_sleep_en_11_gated_we),
29940 .wd (dio_pad_sleep_en_11_wd),
29941
29942 // from internal hardware
29943 .de (1'b0),
29944 .d ('0),
29945
29946 // to internal hardware
29947 .qe (),
29948 .q (reg2hw.dio_pad_sleep_en[11].q),
29949 .ds (),
29950
29951 // to register interface (read)
29952 .qs (dio_pad_sleep_en_11_qs)
29953 );
29954
29955
29956 // Subregister 12 of Multireg dio_pad_sleep_en
29957 // R[dio_pad_sleep_en_12]: V(False)
29958 // Create REGWEN-gated WE signal
29959 logic dio_pad_sleep_en_12_gated_we;
29960 1/1 assign dio_pad_sleep_en_12_gated_we = dio_pad_sleep_en_12_we & dio_pad_sleep_regwen_12_qs;
Tests: T2 T19 T40
29961 prim_subreg #(
29962 .DW (1),
29963 .SwAccess(prim_subreg_pkg::SwAccessRW),
29964 .RESVAL (1'h0),
29965 .Mubi (1'b0)
29966 ) u_dio_pad_sleep_en_12 (
29967 .clk_i (clk_i),
29968 .rst_ni (rst_ni),
29969
29970 // from register interface
29971 .we (dio_pad_sleep_en_12_gated_we),
29972 .wd (dio_pad_sleep_en_12_wd),
29973
29974 // from internal hardware
29975 .de (1'b0),
29976 .d ('0),
29977
29978 // to internal hardware
29979 .qe (),
29980 .q (reg2hw.dio_pad_sleep_en[12].q),
29981 .ds (),
29982
29983 // to register interface (read)
29984 .qs (dio_pad_sleep_en_12_qs)
29985 );
29986
29987
29988 // Subregister 13 of Multireg dio_pad_sleep_en
29989 // R[dio_pad_sleep_en_13]: V(False)
29990 // Create REGWEN-gated WE signal
29991 logic dio_pad_sleep_en_13_gated_we;
29992 1/1 assign dio_pad_sleep_en_13_gated_we = dio_pad_sleep_en_13_we & dio_pad_sleep_regwen_13_qs;
Tests: T2 T19 T40
29993 prim_subreg #(
29994 .DW (1),
29995 .SwAccess(prim_subreg_pkg::SwAccessRW),
29996 .RESVAL (1'h0),
29997 .Mubi (1'b0)
29998 ) u_dio_pad_sleep_en_13 (
29999 .clk_i (clk_i),
30000 .rst_ni (rst_ni),
30001
30002 // from register interface
30003 .we (dio_pad_sleep_en_13_gated_we),
30004 .wd (dio_pad_sleep_en_13_wd),
30005
30006 // from internal hardware
30007 .de (1'b0),
30008 .d ('0),
30009
30010 // to internal hardware
30011 .qe (),
30012 .q (reg2hw.dio_pad_sleep_en[13].q),
30013 .ds (),
30014
30015 // to register interface (read)
30016 .qs (dio_pad_sleep_en_13_qs)
30017 );
30018
30019
30020 // Subregister 14 of Multireg dio_pad_sleep_en
30021 // R[dio_pad_sleep_en_14]: V(False)
30022 // Create REGWEN-gated WE signal
30023 logic dio_pad_sleep_en_14_gated_we;
30024 1/1 assign dio_pad_sleep_en_14_gated_we = dio_pad_sleep_en_14_we & dio_pad_sleep_regwen_14_qs;
Tests: T2 T19 T40
30025 prim_subreg #(
30026 .DW (1),
30027 .SwAccess(prim_subreg_pkg::SwAccessRW),
30028 .RESVAL (1'h0),
30029 .Mubi (1'b0)
30030 ) u_dio_pad_sleep_en_14 (
30031 .clk_i (clk_i),
30032 .rst_ni (rst_ni),
30033
30034 // from register interface
30035 .we (dio_pad_sleep_en_14_gated_we),
30036 .wd (dio_pad_sleep_en_14_wd),
30037
30038 // from internal hardware
30039 .de (1'b0),
30040 .d ('0),
30041
30042 // to internal hardware
30043 .qe (),
30044 .q (reg2hw.dio_pad_sleep_en[14].q),
30045 .ds (),
30046
30047 // to register interface (read)
30048 .qs (dio_pad_sleep_en_14_qs)
30049 );
30050
30051
30052 // Subregister 15 of Multireg dio_pad_sleep_en
30053 // R[dio_pad_sleep_en_15]: V(False)
30054 // Create REGWEN-gated WE signal
30055 logic dio_pad_sleep_en_15_gated_we;
30056 1/1 assign dio_pad_sleep_en_15_gated_we = dio_pad_sleep_en_15_we & dio_pad_sleep_regwen_15_qs;
Tests: T2 T19 T40
30057 prim_subreg #(
30058 .DW (1),
30059 .SwAccess(prim_subreg_pkg::SwAccessRW),
30060 .RESVAL (1'h0),
30061 .Mubi (1'b0)
30062 ) u_dio_pad_sleep_en_15 (
30063 .clk_i (clk_i),
30064 .rst_ni (rst_ni),
30065
30066 // from register interface
30067 .we (dio_pad_sleep_en_15_gated_we),
30068 .wd (dio_pad_sleep_en_15_wd),
30069
30070 // from internal hardware
30071 .de (1'b0),
30072 .d ('0),
30073
30074 // to internal hardware
30075 .qe (),
30076 .q (reg2hw.dio_pad_sleep_en[15].q),
30077 .ds (),
30078
30079 // to register interface (read)
30080 .qs (dio_pad_sleep_en_15_qs)
30081 );
30082
30083
30084 // Subregister 0 of Multireg dio_pad_sleep_mode
30085 // R[dio_pad_sleep_mode_0]: V(False)
30086 // Create REGWEN-gated WE signal
30087 logic dio_pad_sleep_mode_0_gated_we;
30088 1/1 assign dio_pad_sleep_mode_0_gated_we = dio_pad_sleep_mode_0_we & dio_pad_sleep_regwen_0_qs;
Tests: T2 T19 T40
30089 prim_subreg #(
30090 .DW (2),
30091 .SwAccess(prim_subreg_pkg::SwAccessRW),
30092 .RESVAL (2'h2),
30093 .Mubi (1'b0)
30094 ) u_dio_pad_sleep_mode_0 (
30095 .clk_i (clk_i),
30096 .rst_ni (rst_ni),
30097
30098 // from register interface
30099 .we (dio_pad_sleep_mode_0_gated_we),
30100 .wd (dio_pad_sleep_mode_0_wd),
30101
30102 // from internal hardware
30103 .de (1'b0),
30104 .d ('0),
30105
30106 // to internal hardware
30107 .qe (),
30108 .q (reg2hw.dio_pad_sleep_mode[0].q),
30109 .ds (),
30110
30111 // to register interface (read)
30112 .qs (dio_pad_sleep_mode_0_qs)
30113 );
30114
30115
30116 // Subregister 1 of Multireg dio_pad_sleep_mode
30117 // R[dio_pad_sleep_mode_1]: V(False)
30118 // Create REGWEN-gated WE signal
30119 logic dio_pad_sleep_mode_1_gated_we;
30120 1/1 assign dio_pad_sleep_mode_1_gated_we = dio_pad_sleep_mode_1_we & dio_pad_sleep_regwen_1_qs;
Tests: T2 T19 T40
30121 prim_subreg #(
30122 .DW (2),
30123 .SwAccess(prim_subreg_pkg::SwAccessRW),
30124 .RESVAL (2'h2),
30125 .Mubi (1'b0)
30126 ) u_dio_pad_sleep_mode_1 (
30127 .clk_i (clk_i),
30128 .rst_ni (rst_ni),
30129
30130 // from register interface
30131 .we (dio_pad_sleep_mode_1_gated_we),
30132 .wd (dio_pad_sleep_mode_1_wd),
30133
30134 // from internal hardware
30135 .de (1'b0),
30136 .d ('0),
30137
30138 // to internal hardware
30139 .qe (),
30140 .q (reg2hw.dio_pad_sleep_mode[1].q),
30141 .ds (),
30142
30143 // to register interface (read)
30144 .qs (dio_pad_sleep_mode_1_qs)
30145 );
30146
30147
30148 // Subregister 2 of Multireg dio_pad_sleep_mode
30149 // R[dio_pad_sleep_mode_2]: V(False)
30150 // Create REGWEN-gated WE signal
30151 logic dio_pad_sleep_mode_2_gated_we;
30152 1/1 assign dio_pad_sleep_mode_2_gated_we = dio_pad_sleep_mode_2_we & dio_pad_sleep_regwen_2_qs;
Tests: T2 T19 T40
30153 prim_subreg #(
30154 .DW (2),
30155 .SwAccess(prim_subreg_pkg::SwAccessRW),
30156 .RESVAL (2'h2),
30157 .Mubi (1'b0)
30158 ) u_dio_pad_sleep_mode_2 (
30159 .clk_i (clk_i),
30160 .rst_ni (rst_ni),
30161
30162 // from register interface
30163 .we (dio_pad_sleep_mode_2_gated_we),
30164 .wd (dio_pad_sleep_mode_2_wd),
30165
30166 // from internal hardware
30167 .de (1'b0),
30168 .d ('0),
30169
30170 // to internal hardware
30171 .qe (),
30172 .q (reg2hw.dio_pad_sleep_mode[2].q),
30173 .ds (),
30174
30175 // to register interface (read)
30176 .qs (dio_pad_sleep_mode_2_qs)
30177 );
30178
30179
30180 // Subregister 3 of Multireg dio_pad_sleep_mode
30181 // R[dio_pad_sleep_mode_3]: V(False)
30182 // Create REGWEN-gated WE signal
30183 logic dio_pad_sleep_mode_3_gated_we;
30184 1/1 assign dio_pad_sleep_mode_3_gated_we = dio_pad_sleep_mode_3_we & dio_pad_sleep_regwen_3_qs;
Tests: T2 T19 T40
30185 prim_subreg #(
30186 .DW (2),
30187 .SwAccess(prim_subreg_pkg::SwAccessRW),
30188 .RESVAL (2'h2),
30189 .Mubi (1'b0)
30190 ) u_dio_pad_sleep_mode_3 (
30191 .clk_i (clk_i),
30192 .rst_ni (rst_ni),
30193
30194 // from register interface
30195 .we (dio_pad_sleep_mode_3_gated_we),
30196 .wd (dio_pad_sleep_mode_3_wd),
30197
30198 // from internal hardware
30199 .de (1'b0),
30200 .d ('0),
30201
30202 // to internal hardware
30203 .qe (),
30204 .q (reg2hw.dio_pad_sleep_mode[3].q),
30205 .ds (),
30206
30207 // to register interface (read)
30208 .qs (dio_pad_sleep_mode_3_qs)
30209 );
30210
30211
30212 // Subregister 4 of Multireg dio_pad_sleep_mode
30213 // R[dio_pad_sleep_mode_4]: V(False)
30214 // Create REGWEN-gated WE signal
30215 logic dio_pad_sleep_mode_4_gated_we;
30216 1/1 assign dio_pad_sleep_mode_4_gated_we = dio_pad_sleep_mode_4_we & dio_pad_sleep_regwen_4_qs;
Tests: T2 T19 T40
30217 prim_subreg #(
30218 .DW (2),
30219 .SwAccess(prim_subreg_pkg::SwAccessRW),
30220 .RESVAL (2'h2),
30221 .Mubi (1'b0)
30222 ) u_dio_pad_sleep_mode_4 (
30223 .clk_i (clk_i),
30224 .rst_ni (rst_ni),
30225
30226 // from register interface
30227 .we (dio_pad_sleep_mode_4_gated_we),
30228 .wd (dio_pad_sleep_mode_4_wd),
30229
30230 // from internal hardware
30231 .de (1'b0),
30232 .d ('0),
30233
30234 // to internal hardware
30235 .qe (),
30236 .q (reg2hw.dio_pad_sleep_mode[4].q),
30237 .ds (),
30238
30239 // to register interface (read)
30240 .qs (dio_pad_sleep_mode_4_qs)
30241 );
30242
30243
30244 // Subregister 5 of Multireg dio_pad_sleep_mode
30245 // R[dio_pad_sleep_mode_5]: V(False)
30246 // Create REGWEN-gated WE signal
30247 logic dio_pad_sleep_mode_5_gated_we;
30248 1/1 assign dio_pad_sleep_mode_5_gated_we = dio_pad_sleep_mode_5_we & dio_pad_sleep_regwen_5_qs;
Tests: T2 T19 T40
30249 prim_subreg #(
30250 .DW (2),
30251 .SwAccess(prim_subreg_pkg::SwAccessRW),
30252 .RESVAL (2'h2),
30253 .Mubi (1'b0)
30254 ) u_dio_pad_sleep_mode_5 (
30255 .clk_i (clk_i),
30256 .rst_ni (rst_ni),
30257
30258 // from register interface
30259 .we (dio_pad_sleep_mode_5_gated_we),
30260 .wd (dio_pad_sleep_mode_5_wd),
30261
30262 // from internal hardware
30263 .de (1'b0),
30264 .d ('0),
30265
30266 // to internal hardware
30267 .qe (),
30268 .q (reg2hw.dio_pad_sleep_mode[5].q),
30269 .ds (),
30270
30271 // to register interface (read)
30272 .qs (dio_pad_sleep_mode_5_qs)
30273 );
30274
30275
30276 // Subregister 6 of Multireg dio_pad_sleep_mode
30277 // R[dio_pad_sleep_mode_6]: V(False)
30278 // Create REGWEN-gated WE signal
30279 logic dio_pad_sleep_mode_6_gated_we;
30280 1/1 assign dio_pad_sleep_mode_6_gated_we = dio_pad_sleep_mode_6_we & dio_pad_sleep_regwen_6_qs;
Tests: T2 T6 T19
30281 prim_subreg #(
30282 .DW (2),
30283 .SwAccess(prim_subreg_pkg::SwAccessRW),
30284 .RESVAL (2'h2),
30285 .Mubi (1'b0)
30286 ) u_dio_pad_sleep_mode_6 (
30287 .clk_i (clk_i),
30288 .rst_ni (rst_ni),
30289
30290 // from register interface
30291 .we (dio_pad_sleep_mode_6_gated_we),
30292 .wd (dio_pad_sleep_mode_6_wd),
30293
30294 // from internal hardware
30295 .de (1'b0),
30296 .d ('0),
30297
30298 // to internal hardware
30299 .qe (),
30300 .q (reg2hw.dio_pad_sleep_mode[6].q),
30301 .ds (),
30302
30303 // to register interface (read)
30304 .qs (dio_pad_sleep_mode_6_qs)
30305 );
30306
30307
30308 // Subregister 7 of Multireg dio_pad_sleep_mode
30309 // R[dio_pad_sleep_mode_7]: V(False)
30310 // Create REGWEN-gated WE signal
30311 logic dio_pad_sleep_mode_7_gated_we;
30312 1/1 assign dio_pad_sleep_mode_7_gated_we = dio_pad_sleep_mode_7_we & dio_pad_sleep_regwen_7_qs;
Tests: T2 T6 T19
30313 prim_subreg #(
30314 .DW (2),
30315 .SwAccess(prim_subreg_pkg::SwAccessRW),
30316 .RESVAL (2'h2),
30317 .Mubi (1'b0)
30318 ) u_dio_pad_sleep_mode_7 (
30319 .clk_i (clk_i),
30320 .rst_ni (rst_ni),
30321
30322 // from register interface
30323 .we (dio_pad_sleep_mode_7_gated_we),
30324 .wd (dio_pad_sleep_mode_7_wd),
30325
30326 // from internal hardware
30327 .de (1'b0),
30328 .d ('0),
30329
30330 // to internal hardware
30331 .qe (),
30332 .q (reg2hw.dio_pad_sleep_mode[7].q),
30333 .ds (),
30334
30335 // to register interface (read)
30336 .qs (dio_pad_sleep_mode_7_qs)
30337 );
30338
30339
30340 // Subregister 8 of Multireg dio_pad_sleep_mode
30341 // R[dio_pad_sleep_mode_8]: V(False)
30342 // Create REGWEN-gated WE signal
30343 logic dio_pad_sleep_mode_8_gated_we;
30344 1/1 assign dio_pad_sleep_mode_8_gated_we = dio_pad_sleep_mode_8_we & dio_pad_sleep_regwen_8_qs;
Tests: T2 T6 T19
30345 prim_subreg #(
30346 .DW (2),
30347 .SwAccess(prim_subreg_pkg::SwAccessRW),
30348 .RESVAL (2'h2),
30349 .Mubi (1'b0)
30350 ) u_dio_pad_sleep_mode_8 (
30351 .clk_i (clk_i),
30352 .rst_ni (rst_ni),
30353
30354 // from register interface
30355 .we (dio_pad_sleep_mode_8_gated_we),
30356 .wd (dio_pad_sleep_mode_8_wd),
30357
30358 // from internal hardware
30359 .de (1'b0),
30360 .d ('0),
30361
30362 // to internal hardware
30363 .qe (),
30364 .q (reg2hw.dio_pad_sleep_mode[8].q),
30365 .ds (),
30366
30367 // to register interface (read)
30368 .qs (dio_pad_sleep_mode_8_qs)
30369 );
30370
30371
30372 // Subregister 9 of Multireg dio_pad_sleep_mode
30373 // R[dio_pad_sleep_mode_9]: V(False)
30374 // Create REGWEN-gated WE signal
30375 logic dio_pad_sleep_mode_9_gated_we;
30376 1/1 assign dio_pad_sleep_mode_9_gated_we = dio_pad_sleep_mode_9_we & dio_pad_sleep_regwen_9_qs;
Tests: T2 T6 T19
30377 prim_subreg #(
30378 .DW (2),
30379 .SwAccess(prim_subreg_pkg::SwAccessRW),
30380 .RESVAL (2'h2),
30381 .Mubi (1'b0)
30382 ) u_dio_pad_sleep_mode_9 (
30383 .clk_i (clk_i),
30384 .rst_ni (rst_ni),
30385
30386 // from register interface
30387 .we (dio_pad_sleep_mode_9_gated_we),
30388 .wd (dio_pad_sleep_mode_9_wd),
30389
30390 // from internal hardware
30391 .de (1'b0),
30392 .d ('0),
30393
30394 // to internal hardware
30395 .qe (),
30396 .q (reg2hw.dio_pad_sleep_mode[9].q),
30397 .ds (),
30398
30399 // to register interface (read)
30400 .qs (dio_pad_sleep_mode_9_qs)
30401 );
30402
30403
30404 // Subregister 10 of Multireg dio_pad_sleep_mode
30405 // R[dio_pad_sleep_mode_10]: V(False)
30406 // Create REGWEN-gated WE signal
30407 logic dio_pad_sleep_mode_10_gated_we;
30408 1/1 assign dio_pad_sleep_mode_10_gated_we = dio_pad_sleep_mode_10_we & dio_pad_sleep_regwen_10_qs;
Tests: T2 T19 T40
30409 prim_subreg #(
30410 .DW (2),
30411 .SwAccess(prim_subreg_pkg::SwAccessRW),
30412 .RESVAL (2'h2),
30413 .Mubi (1'b0)
30414 ) u_dio_pad_sleep_mode_10 (
30415 .clk_i (clk_i),
30416 .rst_ni (rst_ni),
30417
30418 // from register interface
30419 .we (dio_pad_sleep_mode_10_gated_we),
30420 .wd (dio_pad_sleep_mode_10_wd),
30421
30422 // from internal hardware
30423 .de (1'b0),
30424 .d ('0),
30425
30426 // to internal hardware
30427 .qe (),
30428 .q (reg2hw.dio_pad_sleep_mode[10].q),
30429 .ds (),
30430
30431 // to register interface (read)
30432 .qs (dio_pad_sleep_mode_10_qs)
30433 );
30434
30435
30436 // Subregister 11 of Multireg dio_pad_sleep_mode
30437 // R[dio_pad_sleep_mode_11]: V(False)
30438 // Create REGWEN-gated WE signal
30439 logic dio_pad_sleep_mode_11_gated_we;
30440 1/1 assign dio_pad_sleep_mode_11_gated_we = dio_pad_sleep_mode_11_we & dio_pad_sleep_regwen_11_qs;
Tests: T2 T19 T40
30441 prim_subreg #(
30442 .DW (2),
30443 .SwAccess(prim_subreg_pkg::SwAccessRW),
30444 .RESVAL (2'h2),
30445 .Mubi (1'b0)
30446 ) u_dio_pad_sleep_mode_11 (
30447 .clk_i (clk_i),
30448 .rst_ni (rst_ni),
30449
30450 // from register interface
30451 .we (dio_pad_sleep_mode_11_gated_we),
30452 .wd (dio_pad_sleep_mode_11_wd),
30453
30454 // from internal hardware
30455 .de (1'b0),
30456 .d ('0),
30457
30458 // to internal hardware
30459 .qe (),
30460 .q (reg2hw.dio_pad_sleep_mode[11].q),
30461 .ds (),
30462
30463 // to register interface (read)
30464 .qs (dio_pad_sleep_mode_11_qs)
30465 );
30466
30467
30468 // Subregister 12 of Multireg dio_pad_sleep_mode
30469 // R[dio_pad_sleep_mode_12]: V(False)
30470 // Create REGWEN-gated WE signal
30471 logic dio_pad_sleep_mode_12_gated_we;
30472 1/1 assign dio_pad_sleep_mode_12_gated_we = dio_pad_sleep_mode_12_we & dio_pad_sleep_regwen_12_qs;
Tests: T2 T19 T40
30473 prim_subreg #(
30474 .DW (2),
30475 .SwAccess(prim_subreg_pkg::SwAccessRW),
30476 .RESVAL (2'h2),
30477 .Mubi (1'b0)
30478 ) u_dio_pad_sleep_mode_12 (
30479 .clk_i (clk_i),
30480 .rst_ni (rst_ni),
30481
30482 // from register interface
30483 .we (dio_pad_sleep_mode_12_gated_we),
30484 .wd (dio_pad_sleep_mode_12_wd),
30485
30486 // from internal hardware
30487 .de (1'b0),
30488 .d ('0),
30489
30490 // to internal hardware
30491 .qe (),
30492 .q (reg2hw.dio_pad_sleep_mode[12].q),
30493 .ds (),
30494
30495 // to register interface (read)
30496 .qs (dio_pad_sleep_mode_12_qs)
30497 );
30498
30499
30500 // Subregister 13 of Multireg dio_pad_sleep_mode
30501 // R[dio_pad_sleep_mode_13]: V(False)
30502 // Create REGWEN-gated WE signal
30503 logic dio_pad_sleep_mode_13_gated_we;
30504 1/1 assign dio_pad_sleep_mode_13_gated_we = dio_pad_sleep_mode_13_we & dio_pad_sleep_regwen_13_qs;
Tests: T2 T19 T40
30505 prim_subreg #(
30506 .DW (2),
30507 .SwAccess(prim_subreg_pkg::SwAccessRW),
30508 .RESVAL (2'h2),
30509 .Mubi (1'b0)
30510 ) u_dio_pad_sleep_mode_13 (
30511 .clk_i (clk_i),
30512 .rst_ni (rst_ni),
30513
30514 // from register interface
30515 .we (dio_pad_sleep_mode_13_gated_we),
30516 .wd (dio_pad_sleep_mode_13_wd),
30517
30518 // from internal hardware
30519 .de (1'b0),
30520 .d ('0),
30521
30522 // to internal hardware
30523 .qe (),
30524 .q (reg2hw.dio_pad_sleep_mode[13].q),
30525 .ds (),
30526
30527 // to register interface (read)
30528 .qs (dio_pad_sleep_mode_13_qs)
30529 );
30530
30531
30532 // Subregister 14 of Multireg dio_pad_sleep_mode
30533 // R[dio_pad_sleep_mode_14]: V(False)
30534 // Create REGWEN-gated WE signal
30535 logic dio_pad_sleep_mode_14_gated_we;
30536 1/1 assign dio_pad_sleep_mode_14_gated_we = dio_pad_sleep_mode_14_we & dio_pad_sleep_regwen_14_qs;
Tests: T2 T19 T40
30537 prim_subreg #(
30538 .DW (2),
30539 .SwAccess(prim_subreg_pkg::SwAccessRW),
30540 .RESVAL (2'h2),
30541 .Mubi (1'b0)
30542 ) u_dio_pad_sleep_mode_14 (
30543 .clk_i (clk_i),
30544 .rst_ni (rst_ni),
30545
30546 // from register interface
30547 .we (dio_pad_sleep_mode_14_gated_we),
30548 .wd (dio_pad_sleep_mode_14_wd),
30549
30550 // from internal hardware
30551 .de (1'b0),
30552 .d ('0),
30553
30554 // to internal hardware
30555 .qe (),
30556 .q (reg2hw.dio_pad_sleep_mode[14].q),
30557 .ds (),
30558
30559 // to register interface (read)
30560 .qs (dio_pad_sleep_mode_14_qs)
30561 );
30562
30563
30564 // Subregister 15 of Multireg dio_pad_sleep_mode
30565 // R[dio_pad_sleep_mode_15]: V(False)
30566 // Create REGWEN-gated WE signal
30567 logic dio_pad_sleep_mode_15_gated_we;
30568 1/1 assign dio_pad_sleep_mode_15_gated_we = dio_pad_sleep_mode_15_we & dio_pad_sleep_regwen_15_qs;
Tests: T2 T19 T40
30569 prim_subreg #(
30570 .DW (2),
30571 .SwAccess(prim_subreg_pkg::SwAccessRW),
30572 .RESVAL (2'h2),
30573 .Mubi (1'b0)
30574 ) u_dio_pad_sleep_mode_15 (
30575 .clk_i (clk_i),
30576 .rst_ni (rst_ni),
30577
30578 // from register interface
30579 .we (dio_pad_sleep_mode_15_gated_we),
30580 .wd (dio_pad_sleep_mode_15_wd),
30581
30582 // from internal hardware
30583 .de (1'b0),
30584 .d ('0),
30585
30586 // to internal hardware
30587 .qe (),
30588 .q (reg2hw.dio_pad_sleep_mode[15].q),
30589 .ds (),
30590
30591 // to register interface (read)
30592 .qs (dio_pad_sleep_mode_15_qs)
30593 );
30594
30595
30596 // Subregister 0 of Multireg wkup_detector_regwen
30597 // R[wkup_detector_regwen_0]: V(False)
30598 prim_subreg #(
30599 .DW (1),
30600 .SwAccess(prim_subreg_pkg::SwAccessW0C),
30601 .RESVAL (1'h1),
30602 .Mubi (1'b0)
30603 ) u_wkup_detector_regwen_0 (
30604 .clk_i (clk_i),
30605 .rst_ni (rst_ni),
30606
30607 // from register interface
30608 .we (wkup_detector_regwen_0_we),
30609 .wd (wkup_detector_regwen_0_wd),
30610
30611 // from internal hardware
30612 .de (1'b0),
30613 .d ('0),
30614
30615 // to internal hardware
30616 .qe (),
30617 .q (),
30618 .ds (),
30619
30620 // to register interface (read)
30621 .qs (wkup_detector_regwen_0_qs)
30622 );
30623
30624
30625 // Subregister 1 of Multireg wkup_detector_regwen
30626 // R[wkup_detector_regwen_1]: V(False)
30627 prim_subreg #(
30628 .DW (1),
30629 .SwAccess(prim_subreg_pkg::SwAccessW0C),
30630 .RESVAL (1'h1),
30631 .Mubi (1'b0)
30632 ) u_wkup_detector_regwen_1 (
30633 .clk_i (clk_i),
30634 .rst_ni (rst_ni),
30635
30636 // from register interface
30637 .we (wkup_detector_regwen_1_we),
30638 .wd (wkup_detector_regwen_1_wd),
30639
30640 // from internal hardware
30641 .de (1'b0),
30642 .d ('0),
30643
30644 // to internal hardware
30645 .qe (),
30646 .q (),
30647 .ds (),
30648
30649 // to register interface (read)
30650 .qs (wkup_detector_regwen_1_qs)
30651 );
30652
30653
30654 // Subregister 2 of Multireg wkup_detector_regwen
30655 // R[wkup_detector_regwen_2]: V(False)
30656 prim_subreg #(
30657 .DW (1),
30658 .SwAccess(prim_subreg_pkg::SwAccessW0C),
30659 .RESVAL (1'h1),
30660 .Mubi (1'b0)
30661 ) u_wkup_detector_regwen_2 (
30662 .clk_i (clk_i),
30663 .rst_ni (rst_ni),
30664
30665 // from register interface
30666 .we (wkup_detector_regwen_2_we),
30667 .wd (wkup_detector_regwen_2_wd),
30668
30669 // from internal hardware
30670 .de (1'b0),
30671 .d ('0),
30672
30673 // to internal hardware
30674 .qe (),
30675 .q (),
30676 .ds (),
30677
30678 // to register interface (read)
30679 .qs (wkup_detector_regwen_2_qs)
30680 );
30681
30682
30683 // Subregister 3 of Multireg wkup_detector_regwen
30684 // R[wkup_detector_regwen_3]: V(False)
30685 prim_subreg #(
30686 .DW (1),
30687 .SwAccess(prim_subreg_pkg::SwAccessW0C),
30688 .RESVAL (1'h1),
30689 .Mubi (1'b0)
30690 ) u_wkup_detector_regwen_3 (
30691 .clk_i (clk_i),
30692 .rst_ni (rst_ni),
30693
30694 // from register interface
30695 .we (wkup_detector_regwen_3_we),
30696 .wd (wkup_detector_regwen_3_wd),
30697
30698 // from internal hardware
30699 .de (1'b0),
30700 .d ('0),
30701
30702 // to internal hardware
30703 .qe (),
30704 .q (),
30705 .ds (),
30706
30707 // to register interface (read)
30708 .qs (wkup_detector_regwen_3_qs)
30709 );
30710
30711
30712 // Subregister 4 of Multireg wkup_detector_regwen
30713 // R[wkup_detector_regwen_4]: V(False)
30714 prim_subreg #(
30715 .DW (1),
30716 .SwAccess(prim_subreg_pkg::SwAccessW0C),
30717 .RESVAL (1'h1),
30718 .Mubi (1'b0)
30719 ) u_wkup_detector_regwen_4 (
30720 .clk_i (clk_i),
30721 .rst_ni (rst_ni),
30722
30723 // from register interface
30724 .we (wkup_detector_regwen_4_we),
30725 .wd (wkup_detector_regwen_4_wd),
30726
30727 // from internal hardware
30728 .de (1'b0),
30729 .d ('0),
30730
30731 // to internal hardware
30732 .qe (),
30733 .q (),
30734 .ds (),
30735
30736 // to register interface (read)
30737 .qs (wkup_detector_regwen_4_qs)
30738 );
30739
30740
30741 // Subregister 5 of Multireg wkup_detector_regwen
30742 // R[wkup_detector_regwen_5]: V(False)
30743 prim_subreg #(
30744 .DW (1),
30745 .SwAccess(prim_subreg_pkg::SwAccessW0C),
30746 .RESVAL (1'h1),
30747 .Mubi (1'b0)
30748 ) u_wkup_detector_regwen_5 (
30749 .clk_i (clk_i),
30750 .rst_ni (rst_ni),
30751
30752 // from register interface
30753 .we (wkup_detector_regwen_5_we),
30754 .wd (wkup_detector_regwen_5_wd),
30755
30756 // from internal hardware
30757 .de (1'b0),
30758 .d ('0),
30759
30760 // to internal hardware
30761 .qe (),
30762 .q (),
30763 .ds (),
30764
30765 // to register interface (read)
30766 .qs (wkup_detector_regwen_5_qs)
30767 );
30768
30769
30770 // Subregister 6 of Multireg wkup_detector_regwen
30771 // R[wkup_detector_regwen_6]: V(False)
30772 prim_subreg #(
30773 .DW (1),
30774 .SwAccess(prim_subreg_pkg::SwAccessW0C),
30775 .RESVAL (1'h1),
30776 .Mubi (1'b0)
30777 ) u_wkup_detector_regwen_6 (
30778 .clk_i (clk_i),
30779 .rst_ni (rst_ni),
30780
30781 // from register interface
30782 .we (wkup_detector_regwen_6_we),
30783 .wd (wkup_detector_regwen_6_wd),
30784
30785 // from internal hardware
30786 .de (1'b0),
30787 .d ('0),
30788
30789 // to internal hardware
30790 .qe (),
30791 .q (),
30792 .ds (),
30793
30794 // to register interface (read)
30795 .qs (wkup_detector_regwen_6_qs)
30796 );
30797
30798
30799 // Subregister 7 of Multireg wkup_detector_regwen
30800 // R[wkup_detector_regwen_7]: V(False)
30801 prim_subreg #(
30802 .DW (1),
30803 .SwAccess(prim_subreg_pkg::SwAccessW0C),
30804 .RESVAL (1'h1),
30805 .Mubi (1'b0)
30806 ) u_wkup_detector_regwen_7 (
30807 .clk_i (clk_i),
30808 .rst_ni (rst_ni),
30809
30810 // from register interface
30811 .we (wkup_detector_regwen_7_we),
30812 .wd (wkup_detector_regwen_7_wd),
30813
30814 // from internal hardware
30815 .de (1'b0),
30816 .d ('0),
30817
30818 // to internal hardware
30819 .qe (),
30820 .q (),
30821 .ds (),
30822
30823 // to register interface (read)
30824 .qs (wkup_detector_regwen_7_qs)
30825 );
30826
30827
30828 // Subregister 0 of Multireg wkup_detector_en
30829 // R[wkup_detector_en_0]: V(False)
30830 // Create REGWEN-gated WE signal
30831 logic aon_wkup_detector_en_0_gated_we;
30832 1/1 assign aon_wkup_detector_en_0_gated_we =
Tests: T6 T25 T76
30833 aon_wkup_detector_en_0_we & aon_wkup_detector_en_0_regwen;
30834 prim_subreg #(
30835 .DW (1),
30836 .SwAccess(prim_subreg_pkg::SwAccessRW),
30837 .RESVAL (1'h0),
30838 .Mubi (1'b0)
30839 ) u_wkup_detector_en_0 (
30840 .clk_i (clk_aon_i),
30841 .rst_ni (rst_aon_ni),
30842
30843 // from register interface
30844 .we (aon_wkup_detector_en_0_gated_we),
30845 .wd (aon_wkup_detector_en_0_wdata[0]),
30846
30847 // from internal hardware
30848 .de (1'b0),
30849 .d ('0),
30850
30851 // to internal hardware
30852 .qe (),
30853 .q (reg2hw.wkup_detector_en[0].q),
30854 .ds (),
30855
30856 // to register interface (read)
30857 .qs (aon_wkup_detector_en_0_qs_int)
30858 );
30859
30860
30861 // Subregister 1 of Multireg wkup_detector_en
30862 // R[wkup_detector_en_1]: V(False)
30863 // Create REGWEN-gated WE signal
30864 logic aon_wkup_detector_en_1_gated_we;
30865 1/1 assign aon_wkup_detector_en_1_gated_we =
Tests: T177 T179 T188
30866 aon_wkup_detector_en_1_we & aon_wkup_detector_en_1_regwen;
30867 prim_subreg #(
30868 .DW (1),
30869 .SwAccess(prim_subreg_pkg::SwAccessRW),
30870 .RESVAL (1'h0),
30871 .Mubi (1'b0)
30872 ) u_wkup_detector_en_1 (
30873 .clk_i (clk_aon_i),
30874 .rst_ni (rst_aon_ni),
30875
30876 // from register interface
30877 .we (aon_wkup_detector_en_1_gated_we),
30878 .wd (aon_wkup_detector_en_1_wdata[0]),
30879
30880 // from internal hardware
30881 .de (1'b0),
30882 .d ('0),
30883
30884 // to internal hardware
30885 .qe (),
30886 .q (reg2hw.wkup_detector_en[1].q),
30887 .ds (),
30888
30889 // to register interface (read)
30890 .qs (aon_wkup_detector_en_1_qs_int)
30891 );
30892
30893
30894 // Subregister 2 of Multireg wkup_detector_en
30895 // R[wkup_detector_en_2]: V(False)
30896 // Create REGWEN-gated WE signal
30897 logic aon_wkup_detector_en_2_gated_we;
30898 1/1 assign aon_wkup_detector_en_2_gated_we =
Tests: T177 T179 T188
30899 aon_wkup_detector_en_2_we & aon_wkup_detector_en_2_regwen;
30900 prim_subreg #(
30901 .DW (1),
30902 .SwAccess(prim_subreg_pkg::SwAccessRW),
30903 .RESVAL (1'h0),
30904 .Mubi (1'b0)
30905 ) u_wkup_detector_en_2 (
30906 .clk_i (clk_aon_i),
30907 .rst_ni (rst_aon_ni),
30908
30909 // from register interface
30910 .we (aon_wkup_detector_en_2_gated_we),
30911 .wd (aon_wkup_detector_en_2_wdata[0]),
30912
30913 // from internal hardware
30914 .de (1'b0),
30915 .d ('0),
30916
30917 // to internal hardware
30918 .qe (),
30919 .q (reg2hw.wkup_detector_en[2].q),
30920 .ds (),
30921
30922 // to register interface (read)
30923 .qs (aon_wkup_detector_en_2_qs_int)
30924 );
30925
30926
30927 // Subregister 3 of Multireg wkup_detector_en
30928 // R[wkup_detector_en_3]: V(False)
30929 // Create REGWEN-gated WE signal
30930 logic aon_wkup_detector_en_3_gated_we;
30931 1/1 assign aon_wkup_detector_en_3_gated_we =
Tests: T23 T177 T179
30932 aon_wkup_detector_en_3_we & aon_wkup_detector_en_3_regwen;
30933 prim_subreg #(
30934 .DW (1),
30935 .SwAccess(prim_subreg_pkg::SwAccessRW),
30936 .RESVAL (1'h0),
30937 .Mubi (1'b0)
30938 ) u_wkup_detector_en_3 (
30939 .clk_i (clk_aon_i),
30940 .rst_ni (rst_aon_ni),
30941
30942 // from register interface
30943 .we (aon_wkup_detector_en_3_gated_we),
30944 .wd (aon_wkup_detector_en_3_wdata[0]),
30945
30946 // from internal hardware
30947 .de (1'b0),
30948 .d ('0),
30949
30950 // to internal hardware
30951 .qe (),
30952 .q (reg2hw.wkup_detector_en[3].q),
30953 .ds (),
30954
30955 // to register interface (read)
30956 .qs (aon_wkup_detector_en_3_qs_int)
30957 );
30958
30959
30960 // Subregister 4 of Multireg wkup_detector_en
30961 // R[wkup_detector_en_4]: V(False)
30962 // Create REGWEN-gated WE signal
30963 logic aon_wkup_detector_en_4_gated_we;
30964 1/1 assign aon_wkup_detector_en_4_gated_we =
Tests: T177 T179 T188
30965 aon_wkup_detector_en_4_we & aon_wkup_detector_en_4_regwen;
30966 prim_subreg #(
30967 .DW (1),
30968 .SwAccess(prim_subreg_pkg::SwAccessRW),
30969 .RESVAL (1'h0),
30970 .Mubi (1'b0)
30971 ) u_wkup_detector_en_4 (
30972 .clk_i (clk_aon_i),
30973 .rst_ni (rst_aon_ni),
30974
30975 // from register interface
30976 .we (aon_wkup_detector_en_4_gated_we),
30977 .wd (aon_wkup_detector_en_4_wdata[0]),
30978
30979 // from internal hardware
30980 .de (1'b0),
30981 .d ('0),
30982
30983 // to internal hardware
30984 .qe (),
30985 .q (reg2hw.wkup_detector_en[4].q),
30986 .ds (),
30987
30988 // to register interface (read)
30989 .qs (aon_wkup_detector_en_4_qs_int)
30990 );
30991
30992
30993 // Subregister 5 of Multireg wkup_detector_en
30994 // R[wkup_detector_en_5]: V(False)
30995 // Create REGWEN-gated WE signal
30996 logic aon_wkup_detector_en_5_gated_we;
30997 1/1 assign aon_wkup_detector_en_5_gated_we =
Tests: T77 T78 T79
30998 aon_wkup_detector_en_5_we & aon_wkup_detector_en_5_regwen;
30999 prim_subreg #(
31000 .DW (1),
31001 .SwAccess(prim_subreg_pkg::SwAccessRW),
31002 .RESVAL (1'h0),
31003 .Mubi (1'b0)
31004 ) u_wkup_detector_en_5 (
31005 .clk_i (clk_aon_i),
31006 .rst_ni (rst_aon_ni),
31007
31008 // from register interface
31009 .we (aon_wkup_detector_en_5_gated_we),
31010 .wd (aon_wkup_detector_en_5_wdata[0]),
31011
31012 // from internal hardware
31013 .de (1'b0),
31014 .d ('0),
31015
31016 // to internal hardware
31017 .qe (),
31018 .q (reg2hw.wkup_detector_en[5].q),
31019 .ds (),
31020
31021 // to register interface (read)
31022 .qs (aon_wkup_detector_en_5_qs_int)
31023 );
31024
31025
31026 // Subregister 6 of Multireg wkup_detector_en
31027 // R[wkup_detector_en_6]: V(False)
31028 // Create REGWEN-gated WE signal
31029 logic aon_wkup_detector_en_6_gated_we;
31030 1/1 assign aon_wkup_detector_en_6_gated_we =
Tests: T177 T179 T188
31031 aon_wkup_detector_en_6_we & aon_wkup_detector_en_6_regwen;
31032 prim_subreg #(
31033 .DW (1),
31034 .SwAccess(prim_subreg_pkg::SwAccessRW),
31035 .RESVAL (1'h0),
31036 .Mubi (1'b0)
31037 ) u_wkup_detector_en_6 (
31038 .clk_i (clk_aon_i),
31039 .rst_ni (rst_aon_ni),
31040
31041 // from register interface
31042 .we (aon_wkup_detector_en_6_gated_we),
31043 .wd (aon_wkup_detector_en_6_wdata[0]),
31044
31045 // from internal hardware
31046 .de (1'b0),
31047 .d ('0),
31048
31049 // to internal hardware
31050 .qe (),
31051 .q (reg2hw.wkup_detector_en[6].q),
31052 .ds (),
31053
31054 // to register interface (read)
31055 .qs (aon_wkup_detector_en_6_qs_int)
31056 );
31057
31058
31059 // Subregister 7 of Multireg wkup_detector_en
31060 // R[wkup_detector_en_7]: V(False)
31061 // Create REGWEN-gated WE signal
31062 logic aon_wkup_detector_en_7_gated_we;
31063 1/1 assign aon_wkup_detector_en_7_gated_we =
Tests: T4 T24 T177
31064 aon_wkup_detector_en_7_we & aon_wkup_detector_en_7_regwen;
31065 prim_subreg #(
31066 .DW (1),
31067 .SwAccess(prim_subreg_pkg::SwAccessRW),
31068 .RESVAL (1'h0),
31069 .Mubi (1'b0)
31070 ) u_wkup_detector_en_7 (
31071 .clk_i (clk_aon_i),
31072 .rst_ni (rst_aon_ni),
31073
31074 // from register interface
31075 .we (aon_wkup_detector_en_7_gated_we),
31076 .wd (aon_wkup_detector_en_7_wdata[0]),
31077
31078 // from internal hardware
31079 .de (1'b0),
31080 .d ('0),
31081
31082 // to internal hardware
31083 .qe (),
31084 .q (reg2hw.wkup_detector_en[7].q),
31085 .ds (),
31086
31087 // to register interface (read)
31088 .qs (aon_wkup_detector_en_7_qs_int)
31089 );
31090
31091
31092 // Subregister 0 of Multireg wkup_detector
31093 // R[wkup_detector_0]: V(False)
31094 // Create REGWEN-gated WE signal
31095 logic aon_wkup_detector_0_gated_we;
31096 1/1 assign aon_wkup_detector_0_gated_we = aon_wkup_detector_0_we & aon_wkup_detector_0_regwen;
Tests: T6 T25 T76
31097 // F[mode_0]: 2:0
31098 prim_subreg #(
31099 .DW (3),
31100 .SwAccess(prim_subreg_pkg::SwAccessRW),
31101 .RESVAL (3'h0),
31102 .Mubi (1'b0)
31103 ) u_wkup_detector_0_mode_0 (
31104 .clk_i (clk_aon_i),
31105 .rst_ni (rst_aon_ni),
31106
31107 // from register interface
31108 .we (aon_wkup_detector_0_gated_we),
31109 .wd (aon_wkup_detector_0_wdata[2:0]),
31110
31111 // from internal hardware
31112 .de (1'b0),
31113 .d ('0),
31114
31115 // to internal hardware
31116 .qe (),
31117 .q (reg2hw.wkup_detector[0].mode.q),
31118 .ds (),
31119
31120 // to register interface (read)
31121 .qs (aon_wkup_detector_0_mode_0_qs_int)
31122 );
31123
31124 // F[filter_0]: 3:3
31125 prim_subreg #(
31126 .DW (1),
31127 .SwAccess(prim_subreg_pkg::SwAccessRW),
31128 .RESVAL (1'h0),
31129 .Mubi (1'b0)
31130 ) u_wkup_detector_0_filter_0 (
31131 .clk_i (clk_aon_i),
31132 .rst_ni (rst_aon_ni),
31133
31134 // from register interface
31135 .we (aon_wkup_detector_0_gated_we),
31136 .wd (aon_wkup_detector_0_wdata[3]),
31137
31138 // from internal hardware
31139 .de (1'b0),
31140 .d ('0),
31141
31142 // to internal hardware
31143 .qe (),
31144 .q (reg2hw.wkup_detector[0].filter.q),
31145 .ds (),
31146
31147 // to register interface (read)
31148 .qs (aon_wkup_detector_0_filter_0_qs_int)
31149 );
31150
31151 // F[miodio_0]: 4:4
31152 prim_subreg #(
31153 .DW (1),
31154 .SwAccess(prim_subreg_pkg::SwAccessRW),
31155 .RESVAL (1'h0),
31156 .Mubi (1'b0)
31157 ) u_wkup_detector_0_miodio_0 (
31158 .clk_i (clk_aon_i),
31159 .rst_ni (rst_aon_ni),
31160
31161 // from register interface
31162 .we (aon_wkup_detector_0_gated_we),
31163 .wd (aon_wkup_detector_0_wdata[4]),
31164
31165 // from internal hardware
31166 .de (1'b0),
31167 .d ('0),
31168
31169 // to internal hardware
31170 .qe (),
31171 .q (reg2hw.wkup_detector[0].miodio.q),
31172 .ds (),
31173
31174 // to register interface (read)
31175 .qs (aon_wkup_detector_0_miodio_0_qs_int)
31176 );
31177
31178
31179 // Subregister 1 of Multireg wkup_detector
31180 // R[wkup_detector_1]: V(False)
31181 // Create REGWEN-gated WE signal
31182 logic aon_wkup_detector_1_gated_we;
31183 1/1 assign aon_wkup_detector_1_gated_we = aon_wkup_detector_1_we & aon_wkup_detector_1_regwen;
Tests: T177 T179 T188
31184 // F[mode_1]: 2:0
31185 prim_subreg #(
31186 .DW (3),
31187 .SwAccess(prim_subreg_pkg::SwAccessRW),
31188 .RESVAL (3'h0),
31189 .Mubi (1'b0)
31190 ) u_wkup_detector_1_mode_1 (
31191 .clk_i (clk_aon_i),
31192 .rst_ni (rst_aon_ni),
31193
31194 // from register interface
31195 .we (aon_wkup_detector_1_gated_we),
31196 .wd (aon_wkup_detector_1_wdata[2:0]),
31197
31198 // from internal hardware
31199 .de (1'b0),
31200 .d ('0),
31201
31202 // to internal hardware
31203 .qe (),
31204 .q (reg2hw.wkup_detector[1].mode.q),
31205 .ds (),
31206
31207 // to register interface (read)
31208 .qs (aon_wkup_detector_1_mode_1_qs_int)
31209 );
31210
31211 // F[filter_1]: 3:3
31212 prim_subreg #(
31213 .DW (1),
31214 .SwAccess(prim_subreg_pkg::SwAccessRW),
31215 .RESVAL (1'h0),
31216 .Mubi (1'b0)
31217 ) u_wkup_detector_1_filter_1 (
31218 .clk_i (clk_aon_i),
31219 .rst_ni (rst_aon_ni),
31220
31221 // from register interface
31222 .we (aon_wkup_detector_1_gated_we),
31223 .wd (aon_wkup_detector_1_wdata[3]),
31224
31225 // from internal hardware
31226 .de (1'b0),
31227 .d ('0),
31228
31229 // to internal hardware
31230 .qe (),
31231 .q (reg2hw.wkup_detector[1].filter.q),
31232 .ds (),
31233
31234 // to register interface (read)
31235 .qs (aon_wkup_detector_1_filter_1_qs_int)
31236 );
31237
31238 // F[miodio_1]: 4:4
31239 prim_subreg #(
31240 .DW (1),
31241 .SwAccess(prim_subreg_pkg::SwAccessRW),
31242 .RESVAL (1'h0),
31243 .Mubi (1'b0)
31244 ) u_wkup_detector_1_miodio_1 (
31245 .clk_i (clk_aon_i),
31246 .rst_ni (rst_aon_ni),
31247
31248 // from register interface
31249 .we (aon_wkup_detector_1_gated_we),
31250 .wd (aon_wkup_detector_1_wdata[4]),
31251
31252 // from internal hardware
31253 .de (1'b0),
31254 .d ('0),
31255
31256 // to internal hardware
31257 .qe (),
31258 .q (reg2hw.wkup_detector[1].miodio.q),
31259 .ds (),
31260
31261 // to register interface (read)
31262 .qs (aon_wkup_detector_1_miodio_1_qs_int)
31263 );
31264
31265
31266 // Subregister 2 of Multireg wkup_detector
31267 // R[wkup_detector_2]: V(False)
31268 // Create REGWEN-gated WE signal
31269 logic aon_wkup_detector_2_gated_we;
31270 1/1 assign aon_wkup_detector_2_gated_we = aon_wkup_detector_2_we & aon_wkup_detector_2_regwen;
Tests: T177 T179 T188
31271 // F[mode_2]: 2:0
31272 prim_subreg #(
31273 .DW (3),
31274 .SwAccess(prim_subreg_pkg::SwAccessRW),
31275 .RESVAL (3'h0),
31276 .Mubi (1'b0)
31277 ) u_wkup_detector_2_mode_2 (
31278 .clk_i (clk_aon_i),
31279 .rst_ni (rst_aon_ni),
31280
31281 // from register interface
31282 .we (aon_wkup_detector_2_gated_we),
31283 .wd (aon_wkup_detector_2_wdata[2:0]),
31284
31285 // from internal hardware
31286 .de (1'b0),
31287 .d ('0),
31288
31289 // to internal hardware
31290 .qe (),
31291 .q (reg2hw.wkup_detector[2].mode.q),
31292 .ds (),
31293
31294 // to register interface (read)
31295 .qs (aon_wkup_detector_2_mode_2_qs_int)
31296 );
31297
31298 // F[filter_2]: 3:3
31299 prim_subreg #(
31300 .DW (1),
31301 .SwAccess(prim_subreg_pkg::SwAccessRW),
31302 .RESVAL (1'h0),
31303 .Mubi (1'b0)
31304 ) u_wkup_detector_2_filter_2 (
31305 .clk_i (clk_aon_i),
31306 .rst_ni (rst_aon_ni),
31307
31308 // from register interface
31309 .we (aon_wkup_detector_2_gated_we),
31310 .wd (aon_wkup_detector_2_wdata[3]),
31311
31312 // from internal hardware
31313 .de (1'b0),
31314 .d ('0),
31315
31316 // to internal hardware
31317 .qe (),
31318 .q (reg2hw.wkup_detector[2].filter.q),
31319 .ds (),
31320
31321 // to register interface (read)
31322 .qs (aon_wkup_detector_2_filter_2_qs_int)
31323 );
31324
31325 // F[miodio_2]: 4:4
31326 prim_subreg #(
31327 .DW (1),
31328 .SwAccess(prim_subreg_pkg::SwAccessRW),
31329 .RESVAL (1'h0),
31330 .Mubi (1'b0)
31331 ) u_wkup_detector_2_miodio_2 (
31332 .clk_i (clk_aon_i),
31333 .rst_ni (rst_aon_ni),
31334
31335 // from register interface
31336 .we (aon_wkup_detector_2_gated_we),
31337 .wd (aon_wkup_detector_2_wdata[4]),
31338
31339 // from internal hardware
31340 .de (1'b0),
31341 .d ('0),
31342
31343 // to internal hardware
31344 .qe (),
31345 .q (reg2hw.wkup_detector[2].miodio.q),
31346 .ds (),
31347
31348 // to register interface (read)
31349 .qs (aon_wkup_detector_2_miodio_2_qs_int)
31350 );
31351
31352
31353 // Subregister 3 of Multireg wkup_detector
31354 // R[wkup_detector_3]: V(False)
31355 // Create REGWEN-gated WE signal
31356 logic aon_wkup_detector_3_gated_we;
31357 1/1 assign aon_wkup_detector_3_gated_we = aon_wkup_detector_3_we & aon_wkup_detector_3_regwen;
Tests: T23 T177 T179
31358 // F[mode_3]: 2:0
31359 prim_subreg #(
31360 .DW (3),
31361 .SwAccess(prim_subreg_pkg::SwAccessRW),
31362 .RESVAL (3'h0),
31363 .Mubi (1'b0)
31364 ) u_wkup_detector_3_mode_3 (
31365 .clk_i (clk_aon_i),
31366 .rst_ni (rst_aon_ni),
31367
31368 // from register interface
31369 .we (aon_wkup_detector_3_gated_we),
31370 .wd (aon_wkup_detector_3_wdata[2:0]),
31371
31372 // from internal hardware
31373 .de (1'b0),
31374 .d ('0),
31375
31376 // to internal hardware
31377 .qe (),
31378 .q (reg2hw.wkup_detector[3].mode.q),
31379 .ds (),
31380
31381 // to register interface (read)
31382 .qs (aon_wkup_detector_3_mode_3_qs_int)
31383 );
31384
31385 // F[filter_3]: 3:3
31386 prim_subreg #(
31387 .DW (1),
31388 .SwAccess(prim_subreg_pkg::SwAccessRW),
31389 .RESVAL (1'h0),
31390 .Mubi (1'b0)
31391 ) u_wkup_detector_3_filter_3 (
31392 .clk_i (clk_aon_i),
31393 .rst_ni (rst_aon_ni),
31394
31395 // from register interface
31396 .we (aon_wkup_detector_3_gated_we),
31397 .wd (aon_wkup_detector_3_wdata[3]),
31398
31399 // from internal hardware
31400 .de (1'b0),
31401 .d ('0),
31402
31403 // to internal hardware
31404 .qe (),
31405 .q (reg2hw.wkup_detector[3].filter.q),
31406 .ds (),
31407
31408 // to register interface (read)
31409 .qs (aon_wkup_detector_3_filter_3_qs_int)
31410 );
31411
31412 // F[miodio_3]: 4:4
31413 prim_subreg #(
31414 .DW (1),
31415 .SwAccess(prim_subreg_pkg::SwAccessRW),
31416 .RESVAL (1'h0),
31417 .Mubi (1'b0)
31418 ) u_wkup_detector_3_miodio_3 (
31419 .clk_i (clk_aon_i),
31420 .rst_ni (rst_aon_ni),
31421
31422 // from register interface
31423 .we (aon_wkup_detector_3_gated_we),
31424 .wd (aon_wkup_detector_3_wdata[4]),
31425
31426 // from internal hardware
31427 .de (1'b0),
31428 .d ('0),
31429
31430 // to internal hardware
31431 .qe (),
31432 .q (reg2hw.wkup_detector[3].miodio.q),
31433 .ds (),
31434
31435 // to register interface (read)
31436 .qs (aon_wkup_detector_3_miodio_3_qs_int)
31437 );
31438
31439
31440 // Subregister 4 of Multireg wkup_detector
31441 // R[wkup_detector_4]: V(False)
31442 // Create REGWEN-gated WE signal
31443 logic aon_wkup_detector_4_gated_we;
31444 1/1 assign aon_wkup_detector_4_gated_we = aon_wkup_detector_4_we & aon_wkup_detector_4_regwen;
Tests: T177 T179 T188
31445 // F[mode_4]: 2:0
31446 prim_subreg #(
31447 .DW (3),
31448 .SwAccess(prim_subreg_pkg::SwAccessRW),
31449 .RESVAL (3'h0),
31450 .Mubi (1'b0)
31451 ) u_wkup_detector_4_mode_4 (
31452 .clk_i (clk_aon_i),
31453 .rst_ni (rst_aon_ni),
31454
31455 // from register interface
31456 .we (aon_wkup_detector_4_gated_we),
31457 .wd (aon_wkup_detector_4_wdata[2:0]),
31458
31459 // from internal hardware
31460 .de (1'b0),
31461 .d ('0),
31462
31463 // to internal hardware
31464 .qe (),
31465 .q (reg2hw.wkup_detector[4].mode.q),
31466 .ds (),
31467
31468 // to register interface (read)
31469 .qs (aon_wkup_detector_4_mode_4_qs_int)
31470 );
31471
31472 // F[filter_4]: 3:3
31473 prim_subreg #(
31474 .DW (1),
31475 .SwAccess(prim_subreg_pkg::SwAccessRW),
31476 .RESVAL (1'h0),
31477 .Mubi (1'b0)
31478 ) u_wkup_detector_4_filter_4 (
31479 .clk_i (clk_aon_i),
31480 .rst_ni (rst_aon_ni),
31481
31482 // from register interface
31483 .we (aon_wkup_detector_4_gated_we),
31484 .wd (aon_wkup_detector_4_wdata[3]),
31485
31486 // from internal hardware
31487 .de (1'b0),
31488 .d ('0),
31489
31490 // to internal hardware
31491 .qe (),
31492 .q (reg2hw.wkup_detector[4].filter.q),
31493 .ds (),
31494
31495 // to register interface (read)
31496 .qs (aon_wkup_detector_4_filter_4_qs_int)
31497 );
31498
31499 // F[miodio_4]: 4:4
31500 prim_subreg #(
31501 .DW (1),
31502 .SwAccess(prim_subreg_pkg::SwAccessRW),
31503 .RESVAL (1'h0),
31504 .Mubi (1'b0)
31505 ) u_wkup_detector_4_miodio_4 (
31506 .clk_i (clk_aon_i),
31507 .rst_ni (rst_aon_ni),
31508
31509 // from register interface
31510 .we (aon_wkup_detector_4_gated_we),
31511 .wd (aon_wkup_detector_4_wdata[4]),
31512
31513 // from internal hardware
31514 .de (1'b0),
31515 .d ('0),
31516
31517 // to internal hardware
31518 .qe (),
31519 .q (reg2hw.wkup_detector[4].miodio.q),
31520 .ds (),
31521
31522 // to register interface (read)
31523 .qs (aon_wkup_detector_4_miodio_4_qs_int)
31524 );
31525
31526
31527 // Subregister 5 of Multireg wkup_detector
31528 // R[wkup_detector_5]: V(False)
31529 // Create REGWEN-gated WE signal
31530 logic aon_wkup_detector_5_gated_we;
31531 1/1 assign aon_wkup_detector_5_gated_we = aon_wkup_detector_5_we & aon_wkup_detector_5_regwen;
Tests: T77 T78 T79
31532 // F[mode_5]: 2:0
31533 prim_subreg #(
31534 .DW (3),
31535 .SwAccess(prim_subreg_pkg::SwAccessRW),
31536 .RESVAL (3'h0),
31537 .Mubi (1'b0)
31538 ) u_wkup_detector_5_mode_5 (
31539 .clk_i (clk_aon_i),
31540 .rst_ni (rst_aon_ni),
31541
31542 // from register interface
31543 .we (aon_wkup_detector_5_gated_we),
31544 .wd (aon_wkup_detector_5_wdata[2:0]),
31545
31546 // from internal hardware
31547 .de (1'b0),
31548 .d ('0),
31549
31550 // to internal hardware
31551 .qe (),
31552 .q (reg2hw.wkup_detector[5].mode.q),
31553 .ds (),
31554
31555 // to register interface (read)
31556 .qs (aon_wkup_detector_5_mode_5_qs_int)
31557 );
31558
31559 // F[filter_5]: 3:3
31560 prim_subreg #(
31561 .DW (1),
31562 .SwAccess(prim_subreg_pkg::SwAccessRW),
31563 .RESVAL (1'h0),
31564 .Mubi (1'b0)
31565 ) u_wkup_detector_5_filter_5 (
31566 .clk_i (clk_aon_i),
31567 .rst_ni (rst_aon_ni),
31568
31569 // from register interface
31570 .we (aon_wkup_detector_5_gated_we),
31571 .wd (aon_wkup_detector_5_wdata[3]),
31572
31573 // from internal hardware
31574 .de (1'b0),
31575 .d ('0),
31576
31577 // to internal hardware
31578 .qe (),
31579 .q (reg2hw.wkup_detector[5].filter.q),
31580 .ds (),
31581
31582 // to register interface (read)
31583 .qs (aon_wkup_detector_5_filter_5_qs_int)
31584 );
31585
31586 // F[miodio_5]: 4:4
31587 prim_subreg #(
31588 .DW (1),
31589 .SwAccess(prim_subreg_pkg::SwAccessRW),
31590 .RESVAL (1'h0),
31591 .Mubi (1'b0)
31592 ) u_wkup_detector_5_miodio_5 (
31593 .clk_i (clk_aon_i),
31594 .rst_ni (rst_aon_ni),
31595
31596 // from register interface
31597 .we (aon_wkup_detector_5_gated_we),
31598 .wd (aon_wkup_detector_5_wdata[4]),
31599
31600 // from internal hardware
31601 .de (1'b0),
31602 .d ('0),
31603
31604 // to internal hardware
31605 .qe (),
31606 .q (reg2hw.wkup_detector[5].miodio.q),
31607 .ds (),
31608
31609 // to register interface (read)
31610 .qs (aon_wkup_detector_5_miodio_5_qs_int)
31611 );
31612
31613
31614 // Subregister 6 of Multireg wkup_detector
31615 // R[wkup_detector_6]: V(False)
31616 // Create REGWEN-gated WE signal
31617 logic aon_wkup_detector_6_gated_we;
31618 1/1 assign aon_wkup_detector_6_gated_we = aon_wkup_detector_6_we & aon_wkup_detector_6_regwen;
Tests: T177 T179 T188
31619 // F[mode_6]: 2:0
31620 prim_subreg #(
31621 .DW (3),
31622 .SwAccess(prim_subreg_pkg::SwAccessRW),
31623 .RESVAL (3'h0),
31624 .Mubi (1'b0)
31625 ) u_wkup_detector_6_mode_6 (
31626 .clk_i (clk_aon_i),
31627 .rst_ni (rst_aon_ni),
31628
31629 // from register interface
31630 .we (aon_wkup_detector_6_gated_we),
31631 .wd (aon_wkup_detector_6_wdata[2:0]),
31632
31633 // from internal hardware
31634 .de (1'b0),
31635 .d ('0),
31636
31637 // to internal hardware
31638 .qe (),
31639 .q (reg2hw.wkup_detector[6].mode.q),
31640 .ds (),
31641
31642 // to register interface (read)
31643 .qs (aon_wkup_detector_6_mode_6_qs_int)
31644 );
31645
31646 // F[filter_6]: 3:3
31647 prim_subreg #(
31648 .DW (1),
31649 .SwAccess(prim_subreg_pkg::SwAccessRW),
31650 .RESVAL (1'h0),
31651 .Mubi (1'b0)
31652 ) u_wkup_detector_6_filter_6 (
31653 .clk_i (clk_aon_i),
31654 .rst_ni (rst_aon_ni),
31655
31656 // from register interface
31657 .we (aon_wkup_detector_6_gated_we),
31658 .wd (aon_wkup_detector_6_wdata[3]),
31659
31660 // from internal hardware
31661 .de (1'b0),
31662 .d ('0),
31663
31664 // to internal hardware
31665 .qe (),
31666 .q (reg2hw.wkup_detector[6].filter.q),
31667 .ds (),
31668
31669 // to register interface (read)
31670 .qs (aon_wkup_detector_6_filter_6_qs_int)
31671 );
31672
31673 // F[miodio_6]: 4:4
31674 prim_subreg #(
31675 .DW (1),
31676 .SwAccess(prim_subreg_pkg::SwAccessRW),
31677 .RESVAL (1'h0),
31678 .Mubi (1'b0)
31679 ) u_wkup_detector_6_miodio_6 (
31680 .clk_i (clk_aon_i),
31681 .rst_ni (rst_aon_ni),
31682
31683 // from register interface
31684 .we (aon_wkup_detector_6_gated_we),
31685 .wd (aon_wkup_detector_6_wdata[4]),
31686
31687 // from internal hardware
31688 .de (1'b0),
31689 .d ('0),
31690
31691 // to internal hardware
31692 .qe (),
31693 .q (reg2hw.wkup_detector[6].miodio.q),
31694 .ds (),
31695
31696 // to register interface (read)
31697 .qs (aon_wkup_detector_6_miodio_6_qs_int)
31698 );
31699
31700
31701 // Subregister 7 of Multireg wkup_detector
31702 // R[wkup_detector_7]: V(False)
31703 // Create REGWEN-gated WE signal
31704 logic aon_wkup_detector_7_gated_we;
31705 1/1 assign aon_wkup_detector_7_gated_we = aon_wkup_detector_7_we & aon_wkup_detector_7_regwen;
Tests: T4 T24 T177
31706 // F[mode_7]: 2:0
31707 prim_subreg #(
31708 .DW (3),
31709 .SwAccess(prim_subreg_pkg::SwAccessRW),
31710 .RESVAL (3'h0),
31711 .Mubi (1'b0)
31712 ) u_wkup_detector_7_mode_7 (
31713 .clk_i (clk_aon_i),
31714 .rst_ni (rst_aon_ni),
31715
31716 // from register interface
31717 .we (aon_wkup_detector_7_gated_we),
31718 .wd (aon_wkup_detector_7_wdata[2:0]),
31719
31720 // from internal hardware
31721 .de (1'b0),
31722 .d ('0),
31723
31724 // to internal hardware
31725 .qe (),
31726 .q (reg2hw.wkup_detector[7].mode.q),
31727 .ds (),
31728
31729 // to register interface (read)
31730 .qs (aon_wkup_detector_7_mode_7_qs_int)
31731 );
31732
31733 // F[filter_7]: 3:3
31734 prim_subreg #(
31735 .DW (1),
31736 .SwAccess(prim_subreg_pkg::SwAccessRW),
31737 .RESVAL (1'h0),
31738 .Mubi (1'b0)
31739 ) u_wkup_detector_7_filter_7 (
31740 .clk_i (clk_aon_i),
31741 .rst_ni (rst_aon_ni),
31742
31743 // from register interface
31744 .we (aon_wkup_detector_7_gated_we),
31745 .wd (aon_wkup_detector_7_wdata[3]),
31746
31747 // from internal hardware
31748 .de (1'b0),
31749 .d ('0),
31750
31751 // to internal hardware
31752 .qe (),
31753 .q (reg2hw.wkup_detector[7].filter.q),
31754 .ds (),
31755
31756 // to register interface (read)
31757 .qs (aon_wkup_detector_7_filter_7_qs_int)
31758 );
31759
31760 // F[miodio_7]: 4:4
31761 prim_subreg #(
31762 .DW (1),
31763 .SwAccess(prim_subreg_pkg::SwAccessRW),
31764 .RESVAL (1'h0),
31765 .Mubi (1'b0)
31766 ) u_wkup_detector_7_miodio_7 (
31767 .clk_i (clk_aon_i),
31768 .rst_ni (rst_aon_ni),
31769
31770 // from register interface
31771 .we (aon_wkup_detector_7_gated_we),
31772 .wd (aon_wkup_detector_7_wdata[4]),
31773
31774 // from internal hardware
31775 .de (1'b0),
31776 .d ('0),
31777
31778 // to internal hardware
31779 .qe (),
31780 .q (reg2hw.wkup_detector[7].miodio.q),
31781 .ds (),
31782
31783 // to register interface (read)
31784 .qs (aon_wkup_detector_7_miodio_7_qs_int)
31785 );
31786
31787
31788 // Subregister 0 of Multireg wkup_detector_cnt_th
31789 // R[wkup_detector_cnt_th_0]: V(False)
31790 // Create REGWEN-gated WE signal
31791 logic aon_wkup_detector_cnt_th_0_gated_we;
31792 1/1 assign aon_wkup_detector_cnt_th_0_gated_we =
Tests: T177 T179 T188
31793 aon_wkup_detector_cnt_th_0_we & aon_wkup_detector_cnt_th_0_regwen;
31794 prim_subreg #(
31795 .DW (8),
31796 .SwAccess(prim_subreg_pkg::SwAccessRW),
31797 .RESVAL (8'h0),
31798 .Mubi (1'b0)
31799 ) u_wkup_detector_cnt_th_0 (
31800 .clk_i (clk_aon_i),
31801 .rst_ni (rst_aon_ni),
31802
31803 // from register interface
31804 .we (aon_wkup_detector_cnt_th_0_gated_we),
31805 .wd (aon_wkup_detector_cnt_th_0_wdata[7:0]),
31806
31807 // from internal hardware
31808 .de (1'b0),
31809 .d ('0),
31810
31811 // to internal hardware
31812 .qe (),
31813 .q (reg2hw.wkup_detector_cnt_th[0].q),
31814 .ds (),
31815
31816 // to register interface (read)
31817 .qs (aon_wkup_detector_cnt_th_0_qs_int)
31818 );
31819
31820
31821 // Subregister 1 of Multireg wkup_detector_cnt_th
31822 // R[wkup_detector_cnt_th_1]: V(False)
31823 // Create REGWEN-gated WE signal
31824 logic aon_wkup_detector_cnt_th_1_gated_we;
31825 1/1 assign aon_wkup_detector_cnt_th_1_gated_we =
Tests: T91 T126 T127
31826 aon_wkup_detector_cnt_th_1_we & aon_wkup_detector_cnt_th_1_regwen;
31827 prim_subreg #(
31828 .DW (8),
31829 .SwAccess(prim_subreg_pkg::SwAccessRW),
31830 .RESVAL (8'h0),
31831 .Mubi (1'b0)
31832 ) u_wkup_detector_cnt_th_1 (
31833 .clk_i (clk_aon_i),
31834 .rst_ni (rst_aon_ni),
31835
31836 // from register interface
31837 .we (aon_wkup_detector_cnt_th_1_gated_we),
31838 .wd (aon_wkup_detector_cnt_th_1_wdata[7:0]),
31839
31840 // from internal hardware
31841 .de (1'b0),
31842 .d ('0),
31843
31844 // to internal hardware
31845 .qe (),
31846 .q (reg2hw.wkup_detector_cnt_th[1].q),
31847 .ds (),
31848
31849 // to register interface (read)
31850 .qs (aon_wkup_detector_cnt_th_1_qs_int)
31851 );
31852
31853
31854 // Subregister 2 of Multireg wkup_detector_cnt_th
31855 // R[wkup_detector_cnt_th_2]: V(False)
31856 // Create REGWEN-gated WE signal
31857 logic aon_wkup_detector_cnt_th_2_gated_we;
31858 1/1 assign aon_wkup_detector_cnt_th_2_gated_we =
Tests: T177 T179 T188
31859 aon_wkup_detector_cnt_th_2_we & aon_wkup_detector_cnt_th_2_regwen;
31860 prim_subreg #(
31861 .DW (8),
31862 .SwAccess(prim_subreg_pkg::SwAccessRW),
31863 .RESVAL (8'h0),
31864 .Mubi (1'b0)
31865 ) u_wkup_detector_cnt_th_2 (
31866 .clk_i (clk_aon_i),
31867 .rst_ni (rst_aon_ni),
31868
31869 // from register interface
31870 .we (aon_wkup_detector_cnt_th_2_gated_we),
31871 .wd (aon_wkup_detector_cnt_th_2_wdata[7:0]),
31872
31873 // from internal hardware
31874 .de (1'b0),
31875 .d ('0),
31876
31877 // to internal hardware
31878 .qe (),
31879 .q (reg2hw.wkup_detector_cnt_th[2].q),
31880 .ds (),
31881
31882 // to register interface (read)
31883 .qs (aon_wkup_detector_cnt_th_2_qs_int)
31884 );
31885
31886
31887 // Subregister 3 of Multireg wkup_detector_cnt_th
31888 // R[wkup_detector_cnt_th_3]: V(False)
31889 // Create REGWEN-gated WE signal
31890 logic aon_wkup_detector_cnt_th_3_gated_we;
31891 1/1 assign aon_wkup_detector_cnt_th_3_gated_we =
Tests: T177 T179 T188
31892 aon_wkup_detector_cnt_th_3_we & aon_wkup_detector_cnt_th_3_regwen;
31893 prim_subreg #(
31894 .DW (8),
31895 .SwAccess(prim_subreg_pkg::SwAccessRW),
31896 .RESVAL (8'h0),
31897 .Mubi (1'b0)
31898 ) u_wkup_detector_cnt_th_3 (
31899 .clk_i (clk_aon_i),
31900 .rst_ni (rst_aon_ni),
31901
31902 // from register interface
31903 .we (aon_wkup_detector_cnt_th_3_gated_we),
31904 .wd (aon_wkup_detector_cnt_th_3_wdata[7:0]),
31905
31906 // from internal hardware
31907 .de (1'b0),
31908 .d ('0),
31909
31910 // to internal hardware
31911 .qe (),
31912 .q (reg2hw.wkup_detector_cnt_th[3].q),
31913 .ds (),
31914
31915 // to register interface (read)
31916 .qs (aon_wkup_detector_cnt_th_3_qs_int)
31917 );
31918
31919
31920 // Subregister 4 of Multireg wkup_detector_cnt_th
31921 // R[wkup_detector_cnt_th_4]: V(False)
31922 // Create REGWEN-gated WE signal
31923 logic aon_wkup_detector_cnt_th_4_gated_we;
31924 1/1 assign aon_wkup_detector_cnt_th_4_gated_we =
Tests: T177 T179 T188
31925 aon_wkup_detector_cnt_th_4_we & aon_wkup_detector_cnt_th_4_regwen;
31926 prim_subreg #(
31927 .DW (8),
31928 .SwAccess(prim_subreg_pkg::SwAccessRW),
31929 .RESVAL (8'h0),
31930 .Mubi (1'b0)
31931 ) u_wkup_detector_cnt_th_4 (
31932 .clk_i (clk_aon_i),
31933 .rst_ni (rst_aon_ni),
31934
31935 // from register interface
31936 .we (aon_wkup_detector_cnt_th_4_gated_we),
31937 .wd (aon_wkup_detector_cnt_th_4_wdata[7:0]),
31938
31939 // from internal hardware
31940 .de (1'b0),
31941 .d ('0),
31942
31943 // to internal hardware
31944 .qe (),
31945 .q (reg2hw.wkup_detector_cnt_th[4].q),
31946 .ds (),
31947
31948 // to register interface (read)
31949 .qs (aon_wkup_detector_cnt_th_4_qs_int)
31950 );
31951
31952
31953 // Subregister 5 of Multireg wkup_detector_cnt_th
31954 // R[wkup_detector_cnt_th_5]: V(False)
31955 // Create REGWEN-gated WE signal
31956 logic aon_wkup_detector_cnt_th_5_gated_we;
31957 1/1 assign aon_wkup_detector_cnt_th_5_gated_we =
Tests: T177 T179 T188
31958 aon_wkup_detector_cnt_th_5_we & aon_wkup_detector_cnt_th_5_regwen;
31959 prim_subreg #(
31960 .DW (8),
31961 .SwAccess(prim_subreg_pkg::SwAccessRW),
31962 .RESVAL (8'h0),
31963 .Mubi (1'b0)
31964 ) u_wkup_detector_cnt_th_5 (
31965 .clk_i (clk_aon_i),
31966 .rst_ni (rst_aon_ni),
31967
31968 // from register interface
31969 .we (aon_wkup_detector_cnt_th_5_gated_we),
31970 .wd (aon_wkup_detector_cnt_th_5_wdata[7:0]),
31971
31972 // from internal hardware
31973 .de (1'b0),
31974 .d ('0),
31975
31976 // to internal hardware
31977 .qe (),
31978 .q (reg2hw.wkup_detector_cnt_th[5].q),
31979 .ds (),
31980
31981 // to register interface (read)
31982 .qs (aon_wkup_detector_cnt_th_5_qs_int)
31983 );
31984
31985
31986 // Subregister 6 of Multireg wkup_detector_cnt_th
31987 // R[wkup_detector_cnt_th_6]: V(False)
31988 // Create REGWEN-gated WE signal
31989 logic aon_wkup_detector_cnt_th_6_gated_we;
31990 1/1 assign aon_wkup_detector_cnt_th_6_gated_we =
Tests: T177 T179 T188
31991 aon_wkup_detector_cnt_th_6_we & aon_wkup_detector_cnt_th_6_regwen;
31992 prim_subreg #(
31993 .DW (8),
31994 .SwAccess(prim_subreg_pkg::SwAccessRW),
31995 .RESVAL (8'h0),
31996 .Mubi (1'b0)
31997 ) u_wkup_detector_cnt_th_6 (
31998 .clk_i (clk_aon_i),
31999 .rst_ni (rst_aon_ni),
32000
32001 // from register interface
32002 .we (aon_wkup_detector_cnt_th_6_gated_we),
32003 .wd (aon_wkup_detector_cnt_th_6_wdata[7:0]),
32004
32005 // from internal hardware
32006 .de (1'b0),
32007 .d ('0),
32008
32009 // to internal hardware
32010 .qe (),
32011 .q (reg2hw.wkup_detector_cnt_th[6].q),
32012 .ds (),
32013
32014 // to register interface (read)
32015 .qs (aon_wkup_detector_cnt_th_6_qs_int)
32016 );
32017
32018
32019 // Subregister 7 of Multireg wkup_detector_cnt_th
32020 // R[wkup_detector_cnt_th_7]: V(False)
32021 // Create REGWEN-gated WE signal
32022 logic aon_wkup_detector_cnt_th_7_gated_we;
32023 1/1 assign aon_wkup_detector_cnt_th_7_gated_we =
Tests: T177 T179 T188
32024 aon_wkup_detector_cnt_th_7_we & aon_wkup_detector_cnt_th_7_regwen;
32025 prim_subreg #(
32026 .DW (8),
32027 .SwAccess(prim_subreg_pkg::SwAccessRW),
32028 .RESVAL (8'h0),
32029 .Mubi (1'b0)
32030 ) u_wkup_detector_cnt_th_7 (
32031 .clk_i (clk_aon_i),
32032 .rst_ni (rst_aon_ni),
32033
32034 // from register interface
32035 .we (aon_wkup_detector_cnt_th_7_gated_we),
32036 .wd (aon_wkup_detector_cnt_th_7_wdata[7:0]),
32037
32038 // from internal hardware
32039 .de (1'b0),
32040 .d ('0),
32041
32042 // to internal hardware
32043 .qe (),
32044 .q (reg2hw.wkup_detector_cnt_th[7].q),
32045 .ds (),
32046
32047 // to register interface (read)
32048 .qs (aon_wkup_detector_cnt_th_7_qs_int)
32049 );
32050
32051
32052 // Subregister 0 of Multireg wkup_detector_padsel
32053 // R[wkup_detector_padsel_0]: V(False)
32054 // Create REGWEN-gated WE signal
32055 logic wkup_detector_padsel_0_gated_we;
32056 1/1 assign wkup_detector_padsel_0_gated_we = wkup_detector_padsel_0_we & wkup_detector_regwen_0_qs;
Tests: T6 T25 T76
32057 prim_subreg #(
32058 .DW (6),
32059 .SwAccess(prim_subreg_pkg::SwAccessRW),
32060 .RESVAL (6'h0),
32061 .Mubi (1'b0)
32062 ) u_wkup_detector_padsel_0 (
32063 .clk_i (clk_i),
32064 .rst_ni (rst_ni),
32065
32066 // from register interface
32067 .we (wkup_detector_padsel_0_gated_we),
32068 .wd (wkup_detector_padsel_0_wd),
32069
32070 // from internal hardware
32071 .de (1'b0),
32072 .d ('0),
32073
32074 // to internal hardware
32075 .qe (),
32076 .q (reg2hw.wkup_detector_padsel[0].q),
32077 .ds (),
32078
32079 // to register interface (read)
32080 .qs (wkup_detector_padsel_0_qs)
32081 );
32082
32083
32084 // Subregister 1 of Multireg wkup_detector_padsel
32085 // R[wkup_detector_padsel_1]: V(False)
32086 // Create REGWEN-gated WE signal
32087 logic wkup_detector_padsel_1_gated_we;
32088 1/1 assign wkup_detector_padsel_1_gated_we = wkup_detector_padsel_1_we & wkup_detector_regwen_1_qs;
Tests: T96 T97 T98
32089 prim_subreg #(
32090 .DW (6),
32091 .SwAccess(prim_subreg_pkg::SwAccessRW),
32092 .RESVAL (6'h0),
32093 .Mubi (1'b0)
32094 ) u_wkup_detector_padsel_1 (
32095 .clk_i (clk_i),
32096 .rst_ni (rst_ni),
32097
32098 // from register interface
32099 .we (wkup_detector_padsel_1_gated_we),
32100 .wd (wkup_detector_padsel_1_wd),
32101
32102 // from internal hardware
32103 .de (1'b0),
32104 .d ('0),
32105
32106 // to internal hardware
32107 .qe (),
32108 .q (reg2hw.wkup_detector_padsel[1].q),
32109 .ds (),
32110
32111 // to register interface (read)
32112 .qs (wkup_detector_padsel_1_qs)
32113 );
32114
32115
32116 // Subregister 2 of Multireg wkup_detector_padsel
32117 // R[wkup_detector_padsel_2]: V(False)
32118 // Create REGWEN-gated WE signal
32119 logic wkup_detector_padsel_2_gated_we;
32120 1/1 assign wkup_detector_padsel_2_gated_we = wkup_detector_padsel_2_we & wkup_detector_regwen_2_qs;
Tests: T96 T97 T98
32121 prim_subreg #(
32122 .DW (6),
32123 .SwAccess(prim_subreg_pkg::SwAccessRW),
32124 .RESVAL (6'h0),
32125 .Mubi (1'b0)
32126 ) u_wkup_detector_padsel_2 (
32127 .clk_i (clk_i),
32128 .rst_ni (rst_ni),
32129
32130 // from register interface
32131 .we (wkup_detector_padsel_2_gated_we),
32132 .wd (wkup_detector_padsel_2_wd),
32133
32134 // from internal hardware
32135 .de (1'b0),
32136 .d ('0),
32137
32138 // to internal hardware
32139 .qe (),
32140 .q (reg2hw.wkup_detector_padsel[2].q),
32141 .ds (),
32142
32143 // to register interface (read)
32144 .qs (wkup_detector_padsel_2_qs)
32145 );
32146
32147
32148 // Subregister 3 of Multireg wkup_detector_padsel
32149 // R[wkup_detector_padsel_3]: V(False)
32150 // Create REGWEN-gated WE signal
32151 logic wkup_detector_padsel_3_gated_we;
32152 1/1 assign wkup_detector_padsel_3_gated_we = wkup_detector_padsel_3_we & wkup_detector_regwen_3_qs;
Tests: T23 T96 T97
32153 prim_subreg #(
32154 .DW (6),
32155 .SwAccess(prim_subreg_pkg::SwAccessRW),
32156 .RESVAL (6'h0),
32157 .Mubi (1'b0)
32158 ) u_wkup_detector_padsel_3 (
32159 .clk_i (clk_i),
32160 .rst_ni (rst_ni),
32161
32162 // from register interface
32163 .we (wkup_detector_padsel_3_gated_we),
32164 .wd (wkup_detector_padsel_3_wd),
32165
32166 // from internal hardware
32167 .de (1'b0),
32168 .d ('0),
32169
32170 // to internal hardware
32171 .qe (),
32172 .q (reg2hw.wkup_detector_padsel[3].q),
32173 .ds (),
32174
32175 // to register interface (read)
32176 .qs (wkup_detector_padsel_3_qs)
32177 );
32178
32179
32180 // Subregister 4 of Multireg wkup_detector_padsel
32181 // R[wkup_detector_padsel_4]: V(False)
32182 // Create REGWEN-gated WE signal
32183 logic wkup_detector_padsel_4_gated_we;
32184 1/1 assign wkup_detector_padsel_4_gated_we = wkup_detector_padsel_4_we & wkup_detector_regwen_4_qs;
Tests: T96 T97 T98
32185 prim_subreg #(
32186 .DW (6),
32187 .SwAccess(prim_subreg_pkg::SwAccessRW),
32188 .RESVAL (6'h0),
32189 .Mubi (1'b0)
32190 ) u_wkup_detector_padsel_4 (
32191 .clk_i (clk_i),
32192 .rst_ni (rst_ni),
32193
32194 // from register interface
32195 .we (wkup_detector_padsel_4_gated_we),
32196 .wd (wkup_detector_padsel_4_wd),
32197
32198 // from internal hardware
32199 .de (1'b0),
32200 .d ('0),
32201
32202 // to internal hardware
32203 .qe (),
32204 .q (reg2hw.wkup_detector_padsel[4].q),
32205 .ds (),
32206
32207 // to register interface (read)
32208 .qs (wkup_detector_padsel_4_qs)
32209 );
32210
32211
32212 // Subregister 5 of Multireg wkup_detector_padsel
32213 // R[wkup_detector_padsel_5]: V(False)
32214 // Create REGWEN-gated WE signal
32215 logic wkup_detector_padsel_5_gated_we;
32216 1/1 assign wkup_detector_padsel_5_gated_we = wkup_detector_padsel_5_we & wkup_detector_regwen_5_qs;
Tests: T77 T78 T79
32217 prim_subreg #(
32218 .DW (6),
32219 .SwAccess(prim_subreg_pkg::SwAccessRW),
32220 .RESVAL (6'h0),
32221 .Mubi (1'b0)
32222 ) u_wkup_detector_padsel_5 (
32223 .clk_i (clk_i),
32224 .rst_ni (rst_ni),
32225
32226 // from register interface
32227 .we (wkup_detector_padsel_5_gated_we),
32228 .wd (wkup_detector_padsel_5_wd),
32229
32230 // from internal hardware
32231 .de (1'b0),
32232 .d ('0),
32233
32234 // to internal hardware
32235 .qe (),
32236 .q (reg2hw.wkup_detector_padsel[5].q),
32237 .ds (),
32238
32239 // to register interface (read)
32240 .qs (wkup_detector_padsel_5_qs)
32241 );
32242
32243
32244 // Subregister 6 of Multireg wkup_detector_padsel
32245 // R[wkup_detector_padsel_6]: V(False)
32246 // Create REGWEN-gated WE signal
32247 logic wkup_detector_padsel_6_gated_we;
32248 1/1 assign wkup_detector_padsel_6_gated_we = wkup_detector_padsel_6_we & wkup_detector_regwen_6_qs;
Tests: T96 T97 T98
32249 prim_subreg #(
32250 .DW (6),
32251 .SwAccess(prim_subreg_pkg::SwAccessRW),
32252 .RESVAL (6'h0),
32253 .Mubi (1'b0)
32254 ) u_wkup_detector_padsel_6 (
32255 .clk_i (clk_i),
32256 .rst_ni (rst_ni),
32257
32258 // from register interface
32259 .we (wkup_detector_padsel_6_gated_we),
32260 .wd (wkup_detector_padsel_6_wd),
32261
32262 // from internal hardware
32263 .de (1'b0),
32264 .d ('0),
32265
32266 // to internal hardware
32267 .qe (),
32268 .q (reg2hw.wkup_detector_padsel[6].q),
32269 .ds (),
32270
32271 // to register interface (read)
32272 .qs (wkup_detector_padsel_6_qs)
32273 );
32274
32275
32276 // Subregister 7 of Multireg wkup_detector_padsel
32277 // R[wkup_detector_padsel_7]: V(False)
32278 // Create REGWEN-gated WE signal
32279 logic wkup_detector_padsel_7_gated_we;
32280 1/1 assign wkup_detector_padsel_7_gated_we = wkup_detector_padsel_7_we & wkup_detector_regwen_7_qs;
Tests: T4 T24 T96
32281 prim_subreg #(
32282 .DW (6),
32283 .SwAccess(prim_subreg_pkg::SwAccessRW),
32284 .RESVAL (6'h0),
32285 .Mubi (1'b0)
32286 ) u_wkup_detector_padsel_7 (
32287 .clk_i (clk_i),
32288 .rst_ni (rst_ni),
32289
32290 // from register interface
32291 .we (wkup_detector_padsel_7_gated_we),
32292 .wd (wkup_detector_padsel_7_wd),
32293
32294 // from internal hardware
32295 .de (1'b0),
32296 .d ('0),
32297
32298 // to internal hardware
32299 .qe (),
32300 .q (reg2hw.wkup_detector_padsel[7].q),
32301 .ds (),
32302
32303 // to register interface (read)
32304 .qs (wkup_detector_padsel_7_qs)
32305 );
32306
32307
32308 // Subregister 0 of Multireg wkup_cause
32309 // R[wkup_cause]: V(False)
32310 logic [7:0] wkup_cause_flds_we;
32311 1/1 assign aon_wkup_cause_qe = |wkup_cause_flds_we;
Tests: T4 T6 T25
32312 // F[cause_0]: 0:0
32313 prim_subreg #(
32314 .DW (1),
32315 .SwAccess(prim_subreg_pkg::SwAccessW0C),
32316 .RESVAL (1'h0),
32317 .Mubi (1'b0)
32318 ) u_wkup_cause_cause_0 (
32319 .clk_i (clk_aon_i),
32320 .rst_ni (rst_aon_ni),
32321
32322 // from register interface
32323 .we (aon_wkup_cause_we),
32324 .wd (aon_wkup_cause_wdata[0]),
32325
32326 // from internal hardware
32327 .de (hw2reg.wkup_cause[0].de),
32328 .d (hw2reg.wkup_cause[0].d),
32329
32330 // to internal hardware
32331 .qe (wkup_cause_flds_we[0]),
32332 .q (reg2hw.wkup_cause[0].q),
32333 .ds (aon_wkup_cause_cause_0_ds_int),
32334
32335 // to register interface (read)
32336 .qs (aon_wkup_cause_cause_0_qs_int)
32337 );
32338
32339 // F[cause_1]: 1:1
32340 prim_subreg #(
32341 .DW (1),
32342 .SwAccess(prim_subreg_pkg::SwAccessW0C),
32343 .RESVAL (1'h0),
32344 .Mubi (1'b0)
32345 ) u_wkup_cause_cause_1 (
32346 .clk_i (clk_aon_i),
32347 .rst_ni (rst_aon_ni),
32348
32349 // from register interface
32350 .we (aon_wkup_cause_we),
32351 .wd (aon_wkup_cause_wdata[1]),
32352
32353 // from internal hardware
32354 .de (hw2reg.wkup_cause[1].de),
32355 .d (hw2reg.wkup_cause[1].d),
32356
32357 // to internal hardware
32358 .qe (wkup_cause_flds_we[1]),
32359 .q (reg2hw.wkup_cause[1].q),
32360 .ds (aon_wkup_cause_cause_1_ds_int),
32361
32362 // to register interface (read)
32363 .qs (aon_wkup_cause_cause_1_qs_int)
32364 );
32365
32366 // F[cause_2]: 2:2
32367 prim_subreg #(
32368 .DW (1),
32369 .SwAccess(prim_subreg_pkg::SwAccessW0C),
32370 .RESVAL (1'h0),
32371 .Mubi (1'b0)
32372 ) u_wkup_cause_cause_2 (
32373 .clk_i (clk_aon_i),
32374 .rst_ni (rst_aon_ni),
32375
32376 // from register interface
32377 .we (aon_wkup_cause_we),
32378 .wd (aon_wkup_cause_wdata[2]),
32379
32380 // from internal hardware
32381 .de (hw2reg.wkup_cause[2].de),
32382 .d (hw2reg.wkup_cause[2].d),
32383
32384 // to internal hardware
32385 .qe (wkup_cause_flds_we[2]),
32386 .q (reg2hw.wkup_cause[2].q),
32387 .ds (aon_wkup_cause_cause_2_ds_int),
32388
32389 // to register interface (read)
32390 .qs (aon_wkup_cause_cause_2_qs_int)
32391 );
32392
32393 // F[cause_3]: 3:3
32394 prim_subreg #(
32395 .DW (1),
32396 .SwAccess(prim_subreg_pkg::SwAccessW0C),
32397 .RESVAL (1'h0),
32398 .Mubi (1'b0)
32399 ) u_wkup_cause_cause_3 (
32400 .clk_i (clk_aon_i),
32401 .rst_ni (rst_aon_ni),
32402
32403 // from register interface
32404 .we (aon_wkup_cause_we),
32405 .wd (aon_wkup_cause_wdata[3]),
32406
32407 // from internal hardware
32408 .de (hw2reg.wkup_cause[3].de),
32409 .d (hw2reg.wkup_cause[3].d),
32410
32411 // to internal hardware
32412 .qe (wkup_cause_flds_we[3]),
32413 .q (reg2hw.wkup_cause[3].q),
32414 .ds (aon_wkup_cause_cause_3_ds_int),
32415
32416 // to register interface (read)
32417 .qs (aon_wkup_cause_cause_3_qs_int)
32418 );
32419
32420 // F[cause_4]: 4:4
32421 prim_subreg #(
32422 .DW (1),
32423 .SwAccess(prim_subreg_pkg::SwAccessW0C),
32424 .RESVAL (1'h0),
32425 .Mubi (1'b0)
32426 ) u_wkup_cause_cause_4 (
32427 .clk_i (clk_aon_i),
32428 .rst_ni (rst_aon_ni),
32429
32430 // from register interface
32431 .we (aon_wkup_cause_we),
32432 .wd (aon_wkup_cause_wdata[4]),
32433
32434 // from internal hardware
32435 .de (hw2reg.wkup_cause[4].de),
32436 .d (hw2reg.wkup_cause[4].d),
32437
32438 // to internal hardware
32439 .qe (wkup_cause_flds_we[4]),
32440 .q (reg2hw.wkup_cause[4].q),
32441 .ds (aon_wkup_cause_cause_4_ds_int),
32442
32443 // to register interface (read)
32444 .qs (aon_wkup_cause_cause_4_qs_int)
32445 );
32446
32447 // F[cause_5]: 5:5
32448 prim_subreg #(
32449 .DW (1),
32450 .SwAccess(prim_subreg_pkg::SwAccessW0C),
32451 .RESVAL (1'h0),
32452 .Mubi (1'b0)
32453 ) u_wkup_cause_cause_5 (
32454 .clk_i (clk_aon_i),
32455 .rst_ni (rst_aon_ni),
32456
32457 // from register interface
32458 .we (aon_wkup_cause_we),
32459 .wd (aon_wkup_cause_wdata[5]),
32460
32461 // from internal hardware
32462 .de (hw2reg.wkup_cause[5].de),
32463 .d (hw2reg.wkup_cause[5].d),
32464
32465 // to internal hardware
32466 .qe (wkup_cause_flds_we[5]),
32467 .q (reg2hw.wkup_cause[5].q),
32468 .ds (aon_wkup_cause_cause_5_ds_int),
32469
32470 // to register interface (read)
32471 .qs (aon_wkup_cause_cause_5_qs_int)
32472 );
32473
32474 // F[cause_6]: 6:6
32475 prim_subreg #(
32476 .DW (1),
32477 .SwAccess(prim_subreg_pkg::SwAccessW0C),
32478 .RESVAL (1'h0),
32479 .Mubi (1'b0)
32480 ) u_wkup_cause_cause_6 (
32481 .clk_i (clk_aon_i),
32482 .rst_ni (rst_aon_ni),
32483
32484 // from register interface
32485 .we (aon_wkup_cause_we),
32486 .wd (aon_wkup_cause_wdata[6]),
32487
32488 // from internal hardware
32489 .de (hw2reg.wkup_cause[6].de),
32490 .d (hw2reg.wkup_cause[6].d),
32491
32492 // to internal hardware
32493 .qe (wkup_cause_flds_we[6]),
32494 .q (reg2hw.wkup_cause[6].q),
32495 .ds (aon_wkup_cause_cause_6_ds_int),
32496
32497 // to register interface (read)
32498 .qs (aon_wkup_cause_cause_6_qs_int)
32499 );
32500
32501 // F[cause_7]: 7:7
32502 prim_subreg #(
32503 .DW (1),
32504 .SwAccess(prim_subreg_pkg::SwAccessW0C),
32505 .RESVAL (1'h0),
32506 .Mubi (1'b0)
32507 ) u_wkup_cause_cause_7 (
32508 .clk_i (clk_aon_i),
32509 .rst_ni (rst_aon_ni),
32510
32511 // from register interface
32512 .we (aon_wkup_cause_we),
32513 .wd (aon_wkup_cause_wdata[7]),
32514
32515 // from internal hardware
32516 .de (hw2reg.wkup_cause[7].de),
32517 .d (hw2reg.wkup_cause[7].d),
32518
32519 // to internal hardware
32520 .qe (wkup_cause_flds_we[7]),
32521 .q (reg2hw.wkup_cause[7].q),
32522 .ds (aon_wkup_cause_cause_7_ds_int),
32523
32524 // to register interface (read)
32525 .qs (aon_wkup_cause_cause_7_qs_int)
32526 );
32527
32528
32529
32530 logic [567:0] addr_hit;
32531 always_comb begin
32532 1/1 addr_hit = '0;
Tests: T1 T2 T3
32533 1/1 addr_hit[ 0] = (reg_addr == PINMUX_ALERT_TEST_OFFSET);
Tests: T1 T2 T3
32534 1/1 addr_hit[ 1] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_0_OFFSET);
Tests: T1 T2 T3
32535 1/1 addr_hit[ 2] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_1_OFFSET);
Tests: T1 T2 T3
32536 1/1 addr_hit[ 3] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_2_OFFSET);
Tests: T1 T2 T3
32537 1/1 addr_hit[ 4] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_3_OFFSET);
Tests: T1 T2 T3
32538 1/1 addr_hit[ 5] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_4_OFFSET);
Tests: T1 T2 T3
32539 1/1 addr_hit[ 6] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_5_OFFSET);
Tests: T1 T2 T3
32540 1/1 addr_hit[ 7] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_6_OFFSET);
Tests: T1 T2 T3
32541 1/1 addr_hit[ 8] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_7_OFFSET);
Tests: T1 T2 T3
32542 1/1 addr_hit[ 9] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_8_OFFSET);
Tests: T1 T2 T3
32543 1/1 addr_hit[ 10] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_9_OFFSET);
Tests: T1 T2 T3
32544 1/1 addr_hit[ 11] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_10_OFFSET);
Tests: T1 T2 T3
32545 1/1 addr_hit[ 12] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_11_OFFSET);
Tests: T1 T2 T3
32546 1/1 addr_hit[ 13] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_12_OFFSET);
Tests: T1 T2 T3
32547 1/1 addr_hit[ 14] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_13_OFFSET);
Tests: T1 T2 T3
32548 1/1 addr_hit[ 15] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_14_OFFSET);
Tests: T1 T2 T3
32549 1/1 addr_hit[ 16] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_15_OFFSET);
Tests: T1 T2 T3
32550 1/1 addr_hit[ 17] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_16_OFFSET);
Tests: T1 T2 T3
32551 1/1 addr_hit[ 18] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_17_OFFSET);
Tests: T1 T2 T3
32552 1/1 addr_hit[ 19] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_18_OFFSET);
Tests: T1 T2 T3
32553 1/1 addr_hit[ 20] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_19_OFFSET);
Tests: T1 T2 T3
32554 1/1 addr_hit[ 21] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_20_OFFSET);
Tests: T1 T2 T3
32555 1/1 addr_hit[ 22] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_21_OFFSET);
Tests: T1 T2 T3
32556 1/1 addr_hit[ 23] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_22_OFFSET);
Tests: T1 T2 T3
32557 1/1 addr_hit[ 24] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_23_OFFSET);
Tests: T1 T2 T3
32558 1/1 addr_hit[ 25] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_24_OFFSET);
Tests: T1 T2 T3
32559 1/1 addr_hit[ 26] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_25_OFFSET);
Tests: T1 T2 T3
32560 1/1 addr_hit[ 27] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_26_OFFSET);
Tests: T1 T2 T3
32561 1/1 addr_hit[ 28] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_27_OFFSET);
Tests: T1 T2 T3
32562 1/1 addr_hit[ 29] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_28_OFFSET);
Tests: T1 T2 T3
32563 1/1 addr_hit[ 30] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_29_OFFSET);
Tests: T1 T2 T3
32564 1/1 addr_hit[ 31] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_30_OFFSET);
Tests: T1 T2 T3
32565 1/1 addr_hit[ 32] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_31_OFFSET);
Tests: T1 T2 T3
32566 1/1 addr_hit[ 33] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_32_OFFSET);
Tests: T1 T2 T3
32567 1/1 addr_hit[ 34] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_33_OFFSET);
Tests: T1 T2 T3
32568 1/1 addr_hit[ 35] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_34_OFFSET);
Tests: T1 T2 T3
32569 1/1 addr_hit[ 36] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_35_OFFSET);
Tests: T1 T2 T3
32570 1/1 addr_hit[ 37] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_36_OFFSET);
Tests: T1 T2 T3
32571 1/1 addr_hit[ 38] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_37_OFFSET);
Tests: T1 T2 T3
32572 1/1 addr_hit[ 39] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_38_OFFSET);
Tests: T1 T2 T3
32573 1/1 addr_hit[ 40] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_39_OFFSET);
Tests: T1 T2 T3
32574 1/1 addr_hit[ 41] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_40_OFFSET);
Tests: T1 T2 T3
32575 1/1 addr_hit[ 42] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_41_OFFSET);
Tests: T1 T2 T3
32576 1/1 addr_hit[ 43] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_42_OFFSET);
Tests: T1 T2 T3
32577 1/1 addr_hit[ 44] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_43_OFFSET);
Tests: T1 T2 T3
32578 1/1 addr_hit[ 45] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_44_OFFSET);
Tests: T1 T2 T3
32579 1/1 addr_hit[ 46] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_45_OFFSET);
Tests: T1 T2 T3
32580 1/1 addr_hit[ 47] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_46_OFFSET);
Tests: T1 T2 T3
32581 1/1 addr_hit[ 48] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_47_OFFSET);
Tests: T1 T2 T3
32582 1/1 addr_hit[ 49] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_48_OFFSET);
Tests: T1 T2 T3
32583 1/1 addr_hit[ 50] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_49_OFFSET);
Tests: T1 T2 T3
32584 1/1 addr_hit[ 51] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_50_OFFSET);
Tests: T1 T2 T3
32585 1/1 addr_hit[ 52] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_51_OFFSET);
Tests: T1 T2 T3
32586 1/1 addr_hit[ 53] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_52_OFFSET);
Tests: T1 T2 T3
32587 1/1 addr_hit[ 54] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_53_OFFSET);
Tests: T1 T2 T3
32588 1/1 addr_hit[ 55] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_54_OFFSET);
Tests: T1 T2 T3
32589 1/1 addr_hit[ 56] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_55_OFFSET);
Tests: T1 T2 T3
32590 1/1 addr_hit[ 57] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_56_OFFSET);
Tests: T1 T2 T3
32591 1/1 addr_hit[ 58] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_0_OFFSET);
Tests: T1 T2 T3
32592 1/1 addr_hit[ 59] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_1_OFFSET);
Tests: T1 T2 T3
32593 1/1 addr_hit[ 60] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_2_OFFSET);
Tests: T1 T2 T3
32594 1/1 addr_hit[ 61] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_3_OFFSET);
Tests: T1 T2 T3
32595 1/1 addr_hit[ 62] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_4_OFFSET);
Tests: T1 T2 T3
32596 1/1 addr_hit[ 63] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_5_OFFSET);
Tests: T1 T2 T3
32597 1/1 addr_hit[ 64] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_6_OFFSET);
Tests: T1 T2 T3
32598 1/1 addr_hit[ 65] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_7_OFFSET);
Tests: T1 T2 T3
32599 1/1 addr_hit[ 66] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_8_OFFSET);
Tests: T1 T2 T3
32600 1/1 addr_hit[ 67] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_9_OFFSET);
Tests: T1 T2 T3
32601 1/1 addr_hit[ 68] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_10_OFFSET);
Tests: T1 T2 T3
32602 1/1 addr_hit[ 69] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_11_OFFSET);
Tests: T1 T2 T3
32603 1/1 addr_hit[ 70] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_12_OFFSET);
Tests: T1 T2 T3
32604 1/1 addr_hit[ 71] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_13_OFFSET);
Tests: T1 T2 T3
32605 1/1 addr_hit[ 72] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_14_OFFSET);
Tests: T1 T2 T3
32606 1/1 addr_hit[ 73] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_15_OFFSET);
Tests: T1 T2 T3
32607 1/1 addr_hit[ 74] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_16_OFFSET);
Tests: T1 T2 T3
32608 1/1 addr_hit[ 75] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_17_OFFSET);
Tests: T1 T2 T3
32609 1/1 addr_hit[ 76] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_18_OFFSET);
Tests: T1 T2 T3
32610 1/1 addr_hit[ 77] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_19_OFFSET);
Tests: T1 T2 T3
32611 1/1 addr_hit[ 78] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_20_OFFSET);
Tests: T1 T2 T3
32612 1/1 addr_hit[ 79] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_21_OFFSET);
Tests: T1 T2 T3
32613 1/1 addr_hit[ 80] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_22_OFFSET);
Tests: T1 T2 T3
32614 1/1 addr_hit[ 81] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_23_OFFSET);
Tests: T1 T2 T3
32615 1/1 addr_hit[ 82] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_24_OFFSET);
Tests: T1 T2 T3
32616 1/1 addr_hit[ 83] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_25_OFFSET);
Tests: T1 T2 T3
32617 1/1 addr_hit[ 84] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_26_OFFSET);
Tests: T1 T2 T3
32618 1/1 addr_hit[ 85] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_27_OFFSET);
Tests: T1 T2 T3
32619 1/1 addr_hit[ 86] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_28_OFFSET);
Tests: T1 T2 T3
32620 1/1 addr_hit[ 87] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_29_OFFSET);
Tests: T1 T2 T3
32621 1/1 addr_hit[ 88] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_30_OFFSET);
Tests: T1 T2 T3
32622 1/1 addr_hit[ 89] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_31_OFFSET);
Tests: T1 T2 T3
32623 1/1 addr_hit[ 90] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_32_OFFSET);
Tests: T1 T2 T3
32624 1/1 addr_hit[ 91] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_33_OFFSET);
Tests: T1 T2 T3
32625 1/1 addr_hit[ 92] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_34_OFFSET);
Tests: T1 T2 T3
32626 1/1 addr_hit[ 93] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_35_OFFSET);
Tests: T1 T2 T3
32627 1/1 addr_hit[ 94] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_36_OFFSET);
Tests: T1 T2 T3
32628 1/1 addr_hit[ 95] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_37_OFFSET);
Tests: T1 T2 T3
32629 1/1 addr_hit[ 96] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_38_OFFSET);
Tests: T1 T2 T3
32630 1/1 addr_hit[ 97] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_39_OFFSET);
Tests: T1 T2 T3
32631 1/1 addr_hit[ 98] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_40_OFFSET);
Tests: T1 T2 T3
32632 1/1 addr_hit[ 99] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_41_OFFSET);
Tests: T1 T2 T3
32633 1/1 addr_hit[100] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_42_OFFSET);
Tests: T1 T2 T3
32634 1/1 addr_hit[101] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_43_OFFSET);
Tests: T1 T2 T3
32635 1/1 addr_hit[102] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_44_OFFSET);
Tests: T1 T2 T3
32636 1/1 addr_hit[103] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_45_OFFSET);
Tests: T1 T2 T3
32637 1/1 addr_hit[104] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_46_OFFSET);
Tests: T1 T2 T3
32638 1/1 addr_hit[105] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_47_OFFSET);
Tests: T1 T2 T3
32639 1/1 addr_hit[106] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_48_OFFSET);
Tests: T1 T2 T3
32640 1/1 addr_hit[107] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_49_OFFSET);
Tests: T1 T2 T3
32641 1/1 addr_hit[108] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_50_OFFSET);
Tests: T1 T2 T3
32642 1/1 addr_hit[109] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_51_OFFSET);
Tests: T1 T2 T3
32643 1/1 addr_hit[110] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_52_OFFSET);
Tests: T1 T2 T3
32644 1/1 addr_hit[111] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_53_OFFSET);
Tests: T1 T2 T3
32645 1/1 addr_hit[112] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_54_OFFSET);
Tests: T1 T2 T3
32646 1/1 addr_hit[113] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_55_OFFSET);
Tests: T1 T2 T3
32647 1/1 addr_hit[114] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_56_OFFSET);
Tests: T1 T2 T3
32648 1/1 addr_hit[115] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_0_OFFSET);
Tests: T1 T2 T3
32649 1/1 addr_hit[116] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_1_OFFSET);
Tests: T1 T2 T3
32650 1/1 addr_hit[117] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_2_OFFSET);
Tests: T1 T2 T3
32651 1/1 addr_hit[118] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_3_OFFSET);
Tests: T1 T2 T3
32652 1/1 addr_hit[119] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_4_OFFSET);
Tests: T1 T2 T3
32653 1/1 addr_hit[120] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_5_OFFSET);
Tests: T1 T2 T3
32654 1/1 addr_hit[121] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_6_OFFSET);
Tests: T1 T2 T3
32655 1/1 addr_hit[122] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_7_OFFSET);
Tests: T1 T2 T3
32656 1/1 addr_hit[123] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_8_OFFSET);
Tests: T1 T2 T3
32657 1/1 addr_hit[124] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_9_OFFSET);
Tests: T1 T2 T3
32658 1/1 addr_hit[125] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_10_OFFSET);
Tests: T1 T2 T3
32659 1/1 addr_hit[126] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_11_OFFSET);
Tests: T1 T2 T3
32660 1/1 addr_hit[127] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_12_OFFSET);
Tests: T1 T2 T3
32661 1/1 addr_hit[128] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_13_OFFSET);
Tests: T1 T2 T3
32662 1/1 addr_hit[129] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_14_OFFSET);
Tests: T1 T2 T3
32663 1/1 addr_hit[130] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_15_OFFSET);
Tests: T1 T2 T3
32664 1/1 addr_hit[131] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_16_OFFSET);
Tests: T1 T2 T3
32665 1/1 addr_hit[132] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_17_OFFSET);
Tests: T1 T2 T3
32666 1/1 addr_hit[133] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_18_OFFSET);
Tests: T1 T2 T3
32667 1/1 addr_hit[134] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_19_OFFSET);
Tests: T1 T2 T3
32668 1/1 addr_hit[135] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_20_OFFSET);
Tests: T1 T2 T3
32669 1/1 addr_hit[136] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_21_OFFSET);
Tests: T1 T2 T3
32670 1/1 addr_hit[137] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_22_OFFSET);
Tests: T1 T2 T3
32671 1/1 addr_hit[138] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_23_OFFSET);
Tests: T1 T2 T3
32672 1/1 addr_hit[139] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_24_OFFSET);
Tests: T1 T2 T3
32673 1/1 addr_hit[140] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_25_OFFSET);
Tests: T1 T2 T3
32674 1/1 addr_hit[141] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_26_OFFSET);
Tests: T1 T2 T3
32675 1/1 addr_hit[142] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_27_OFFSET);
Tests: T1 T2 T3
32676 1/1 addr_hit[143] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_28_OFFSET);
Tests: T1 T2 T3
32677 1/1 addr_hit[144] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_29_OFFSET);
Tests: T1 T2 T3
32678 1/1 addr_hit[145] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_30_OFFSET);
Tests: T1 T2 T3
32679 1/1 addr_hit[146] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_31_OFFSET);
Tests: T1 T2 T3
32680 1/1 addr_hit[147] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_32_OFFSET);
Tests: T1 T2 T3
32681 1/1 addr_hit[148] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_33_OFFSET);
Tests: T1 T2 T3
32682 1/1 addr_hit[149] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_34_OFFSET);
Tests: T1 T2 T3
32683 1/1 addr_hit[150] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_35_OFFSET);
Tests: T1 T2 T3
32684 1/1 addr_hit[151] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_36_OFFSET);
Tests: T1 T2 T3
32685 1/1 addr_hit[152] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_37_OFFSET);
Tests: T1 T2 T3
32686 1/1 addr_hit[153] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_38_OFFSET);
Tests: T1 T2 T3
32687 1/1 addr_hit[154] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_39_OFFSET);
Tests: T1 T2 T3
32688 1/1 addr_hit[155] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_40_OFFSET);
Tests: T1 T2 T3
32689 1/1 addr_hit[156] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_41_OFFSET);
Tests: T1 T2 T3
32690 1/1 addr_hit[157] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_42_OFFSET);
Tests: T1 T2 T3
32691 1/1 addr_hit[158] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_43_OFFSET);
Tests: T1 T2 T3
32692 1/1 addr_hit[159] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_44_OFFSET);
Tests: T1 T2 T3
32693 1/1 addr_hit[160] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_45_OFFSET);
Tests: T1 T2 T3
32694 1/1 addr_hit[161] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_46_OFFSET);
Tests: T1 T2 T3
32695 1/1 addr_hit[162] = (reg_addr == PINMUX_MIO_OUTSEL_0_OFFSET);
Tests: T1 T2 T3
32696 1/1 addr_hit[163] = (reg_addr == PINMUX_MIO_OUTSEL_1_OFFSET);
Tests: T1 T2 T3
32697 1/1 addr_hit[164] = (reg_addr == PINMUX_MIO_OUTSEL_2_OFFSET);
Tests: T1 T2 T3
32698 1/1 addr_hit[165] = (reg_addr == PINMUX_MIO_OUTSEL_3_OFFSET);
Tests: T1 T2 T3
32699 1/1 addr_hit[166] = (reg_addr == PINMUX_MIO_OUTSEL_4_OFFSET);
Tests: T1 T2 T3
32700 1/1 addr_hit[167] = (reg_addr == PINMUX_MIO_OUTSEL_5_OFFSET);
Tests: T1 T2 T3
32701 1/1 addr_hit[168] = (reg_addr == PINMUX_MIO_OUTSEL_6_OFFSET);
Tests: T1 T2 T3
32702 1/1 addr_hit[169] = (reg_addr == PINMUX_MIO_OUTSEL_7_OFFSET);
Tests: T1 T2 T3
32703 1/1 addr_hit[170] = (reg_addr == PINMUX_MIO_OUTSEL_8_OFFSET);
Tests: T1 T2 T3
32704 1/1 addr_hit[171] = (reg_addr == PINMUX_MIO_OUTSEL_9_OFFSET);
Tests: T1 T2 T3
32705 1/1 addr_hit[172] = (reg_addr == PINMUX_MIO_OUTSEL_10_OFFSET);
Tests: T1 T2 T3
32706 1/1 addr_hit[173] = (reg_addr == PINMUX_MIO_OUTSEL_11_OFFSET);
Tests: T1 T2 T3
32707 1/1 addr_hit[174] = (reg_addr == PINMUX_MIO_OUTSEL_12_OFFSET);
Tests: T1 T2 T3
32708 1/1 addr_hit[175] = (reg_addr == PINMUX_MIO_OUTSEL_13_OFFSET);
Tests: T1 T2 T3
32709 1/1 addr_hit[176] = (reg_addr == PINMUX_MIO_OUTSEL_14_OFFSET);
Tests: T1 T2 T3
32710 1/1 addr_hit[177] = (reg_addr == PINMUX_MIO_OUTSEL_15_OFFSET);
Tests: T1 T2 T3
32711 1/1 addr_hit[178] = (reg_addr == PINMUX_MIO_OUTSEL_16_OFFSET);
Tests: T1 T2 T3
32712 1/1 addr_hit[179] = (reg_addr == PINMUX_MIO_OUTSEL_17_OFFSET);
Tests: T1 T2 T3
32713 1/1 addr_hit[180] = (reg_addr == PINMUX_MIO_OUTSEL_18_OFFSET);
Tests: T1 T2 T3
32714 1/1 addr_hit[181] = (reg_addr == PINMUX_MIO_OUTSEL_19_OFFSET);
Tests: T1 T2 T3
32715 1/1 addr_hit[182] = (reg_addr == PINMUX_MIO_OUTSEL_20_OFFSET);
Tests: T1 T2 T3
32716 1/1 addr_hit[183] = (reg_addr == PINMUX_MIO_OUTSEL_21_OFFSET);
Tests: T1 T2 T3
32717 1/1 addr_hit[184] = (reg_addr == PINMUX_MIO_OUTSEL_22_OFFSET);
Tests: T1 T2 T3
32718 1/1 addr_hit[185] = (reg_addr == PINMUX_MIO_OUTSEL_23_OFFSET);
Tests: T1 T2 T3
32719 1/1 addr_hit[186] = (reg_addr == PINMUX_MIO_OUTSEL_24_OFFSET);
Tests: T1 T2 T3
32720 1/1 addr_hit[187] = (reg_addr == PINMUX_MIO_OUTSEL_25_OFFSET);
Tests: T1 T2 T3
32721 1/1 addr_hit[188] = (reg_addr == PINMUX_MIO_OUTSEL_26_OFFSET);
Tests: T1 T2 T3
32722 1/1 addr_hit[189] = (reg_addr == PINMUX_MIO_OUTSEL_27_OFFSET);
Tests: T1 T2 T3
32723 1/1 addr_hit[190] = (reg_addr == PINMUX_MIO_OUTSEL_28_OFFSET);
Tests: T1 T2 T3
32724 1/1 addr_hit[191] = (reg_addr == PINMUX_MIO_OUTSEL_29_OFFSET);
Tests: T1 T2 T3
32725 1/1 addr_hit[192] = (reg_addr == PINMUX_MIO_OUTSEL_30_OFFSET);
Tests: T1 T2 T3
32726 1/1 addr_hit[193] = (reg_addr == PINMUX_MIO_OUTSEL_31_OFFSET);
Tests: T1 T2 T3
32727 1/1 addr_hit[194] = (reg_addr == PINMUX_MIO_OUTSEL_32_OFFSET);
Tests: T1 T2 T3
32728 1/1 addr_hit[195] = (reg_addr == PINMUX_MIO_OUTSEL_33_OFFSET);
Tests: T1 T2 T3
32729 1/1 addr_hit[196] = (reg_addr == PINMUX_MIO_OUTSEL_34_OFFSET);
Tests: T1 T2 T3
32730 1/1 addr_hit[197] = (reg_addr == PINMUX_MIO_OUTSEL_35_OFFSET);
Tests: T1 T2 T3
32731 1/1 addr_hit[198] = (reg_addr == PINMUX_MIO_OUTSEL_36_OFFSET);
Tests: T1 T2 T3
32732 1/1 addr_hit[199] = (reg_addr == PINMUX_MIO_OUTSEL_37_OFFSET);
Tests: T1 T2 T3
32733 1/1 addr_hit[200] = (reg_addr == PINMUX_MIO_OUTSEL_38_OFFSET);
Tests: T1 T2 T3
32734 1/1 addr_hit[201] = (reg_addr == PINMUX_MIO_OUTSEL_39_OFFSET);
Tests: T1 T2 T3
32735 1/1 addr_hit[202] = (reg_addr == PINMUX_MIO_OUTSEL_40_OFFSET);
Tests: T1 T2 T3
32736 1/1 addr_hit[203] = (reg_addr == PINMUX_MIO_OUTSEL_41_OFFSET);
Tests: T1 T2 T3
32737 1/1 addr_hit[204] = (reg_addr == PINMUX_MIO_OUTSEL_42_OFFSET);
Tests: T1 T2 T3
32738 1/1 addr_hit[205] = (reg_addr == PINMUX_MIO_OUTSEL_43_OFFSET);
Tests: T1 T2 T3
32739 1/1 addr_hit[206] = (reg_addr == PINMUX_MIO_OUTSEL_44_OFFSET);
Tests: T1 T2 T3
32740 1/1 addr_hit[207] = (reg_addr == PINMUX_MIO_OUTSEL_45_OFFSET);
Tests: T1 T2 T3
32741 1/1 addr_hit[208] = (reg_addr == PINMUX_MIO_OUTSEL_46_OFFSET);
Tests: T1 T2 T3
32742 1/1 addr_hit[209] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_0_OFFSET);
Tests: T1 T2 T3
32743 1/1 addr_hit[210] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_1_OFFSET);
Tests: T1 T2 T3
32744 1/1 addr_hit[211] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_2_OFFSET);
Tests: T1 T2 T3
32745 1/1 addr_hit[212] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_3_OFFSET);
Tests: T1 T2 T3
32746 1/1 addr_hit[213] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_4_OFFSET);
Tests: T1 T2 T3
32747 1/1 addr_hit[214] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_5_OFFSET);
Tests: T1 T2 T3
32748 1/1 addr_hit[215] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_6_OFFSET);
Tests: T1 T2 T3
32749 1/1 addr_hit[216] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_7_OFFSET);
Tests: T1 T2 T3
32750 1/1 addr_hit[217] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_8_OFFSET);
Tests: T1 T2 T3
32751 1/1 addr_hit[218] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_9_OFFSET);
Tests: T1 T2 T3
32752 1/1 addr_hit[219] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_10_OFFSET);
Tests: T1 T2 T3
32753 1/1 addr_hit[220] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_11_OFFSET);
Tests: T1 T2 T3
32754 1/1 addr_hit[221] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_12_OFFSET);
Tests: T1 T2 T3
32755 1/1 addr_hit[222] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_13_OFFSET);
Tests: T1 T2 T3
32756 1/1 addr_hit[223] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_14_OFFSET);
Tests: T1 T2 T3
32757 1/1 addr_hit[224] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_15_OFFSET);
Tests: T1 T2 T3
32758 1/1 addr_hit[225] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_16_OFFSET);
Tests: T1 T2 T3
32759 1/1 addr_hit[226] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_17_OFFSET);
Tests: T1 T2 T3
32760 1/1 addr_hit[227] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_18_OFFSET);
Tests: T1 T2 T3
32761 1/1 addr_hit[228] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_19_OFFSET);
Tests: T1 T2 T3
32762 1/1 addr_hit[229] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_20_OFFSET);
Tests: T1 T2 T3
32763 1/1 addr_hit[230] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_21_OFFSET);
Tests: T1 T2 T3
32764 1/1 addr_hit[231] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_22_OFFSET);
Tests: T1 T2 T3
32765 1/1 addr_hit[232] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_23_OFFSET);
Tests: T1 T2 T3
32766 1/1 addr_hit[233] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_24_OFFSET);
Tests: T1 T2 T3
32767 1/1 addr_hit[234] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_25_OFFSET);
Tests: T1 T2 T3
32768 1/1 addr_hit[235] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_26_OFFSET);
Tests: T1 T2 T3
32769 1/1 addr_hit[236] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_27_OFFSET);
Tests: T1 T2 T3
32770 1/1 addr_hit[237] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_28_OFFSET);
Tests: T1 T2 T3
32771 1/1 addr_hit[238] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_29_OFFSET);
Tests: T1 T2 T3
32772 1/1 addr_hit[239] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_30_OFFSET);
Tests: T1 T2 T3
32773 1/1 addr_hit[240] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_31_OFFSET);
Tests: T1 T2 T3
32774 1/1 addr_hit[241] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_32_OFFSET);
Tests: T1 T2 T3
32775 1/1 addr_hit[242] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_33_OFFSET);
Tests: T1 T2 T3
32776 1/1 addr_hit[243] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_34_OFFSET);
Tests: T1 T2 T3
32777 1/1 addr_hit[244] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_35_OFFSET);
Tests: T1 T2 T3
32778 1/1 addr_hit[245] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_36_OFFSET);
Tests: T1 T2 T3
32779 1/1 addr_hit[246] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_37_OFFSET);
Tests: T1 T2 T3
32780 1/1 addr_hit[247] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_38_OFFSET);
Tests: T1 T2 T3
32781 1/1 addr_hit[248] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_39_OFFSET);
Tests: T1 T2 T3
32782 1/1 addr_hit[249] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_40_OFFSET);
Tests: T1 T2 T3
32783 1/1 addr_hit[250] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_41_OFFSET);
Tests: T1 T2 T3
32784 1/1 addr_hit[251] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_42_OFFSET);
Tests: T1 T2 T3
32785 1/1 addr_hit[252] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_43_OFFSET);
Tests: T1 T2 T3
32786 1/1 addr_hit[253] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_44_OFFSET);
Tests: T1 T2 T3
32787 1/1 addr_hit[254] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_45_OFFSET);
Tests: T1 T2 T3
32788 1/1 addr_hit[255] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_46_OFFSET);
Tests: T1 T2 T3
32789 1/1 addr_hit[256] = (reg_addr == PINMUX_MIO_PAD_ATTR_0_OFFSET);
Tests: T1 T2 T3
32790 1/1 addr_hit[257] = (reg_addr == PINMUX_MIO_PAD_ATTR_1_OFFSET);
Tests: T1 T2 T3
32791 1/1 addr_hit[258] = (reg_addr == PINMUX_MIO_PAD_ATTR_2_OFFSET);
Tests: T1 T2 T3
32792 1/1 addr_hit[259] = (reg_addr == PINMUX_MIO_PAD_ATTR_3_OFFSET);
Tests: T1 T2 T3
32793 1/1 addr_hit[260] = (reg_addr == PINMUX_MIO_PAD_ATTR_4_OFFSET);
Tests: T1 T2 T3
32794 1/1 addr_hit[261] = (reg_addr == PINMUX_MIO_PAD_ATTR_5_OFFSET);
Tests: T1 T2 T3
32795 1/1 addr_hit[262] = (reg_addr == PINMUX_MIO_PAD_ATTR_6_OFFSET);
Tests: T1 T2 T3
32796 1/1 addr_hit[263] = (reg_addr == PINMUX_MIO_PAD_ATTR_7_OFFSET);
Tests: T1 T2 T3
32797 1/1 addr_hit[264] = (reg_addr == PINMUX_MIO_PAD_ATTR_8_OFFSET);
Tests: T1 T2 T3
32798 1/1 addr_hit[265] = (reg_addr == PINMUX_MIO_PAD_ATTR_9_OFFSET);
Tests: T1 T2 T3
32799 1/1 addr_hit[266] = (reg_addr == PINMUX_MIO_PAD_ATTR_10_OFFSET);
Tests: T1 T2 T3
32800 1/1 addr_hit[267] = (reg_addr == PINMUX_MIO_PAD_ATTR_11_OFFSET);
Tests: T1 T2 T3
32801 1/1 addr_hit[268] = (reg_addr == PINMUX_MIO_PAD_ATTR_12_OFFSET);
Tests: T1 T2 T3
32802 1/1 addr_hit[269] = (reg_addr == PINMUX_MIO_PAD_ATTR_13_OFFSET);
Tests: T1 T2 T3
32803 1/1 addr_hit[270] = (reg_addr == PINMUX_MIO_PAD_ATTR_14_OFFSET);
Tests: T1 T2 T3
32804 1/1 addr_hit[271] = (reg_addr == PINMUX_MIO_PAD_ATTR_15_OFFSET);
Tests: T1 T2 T3
32805 1/1 addr_hit[272] = (reg_addr == PINMUX_MIO_PAD_ATTR_16_OFFSET);
Tests: T1 T2 T3
32806 1/1 addr_hit[273] = (reg_addr == PINMUX_MIO_PAD_ATTR_17_OFFSET);
Tests: T1 T2 T3
32807 1/1 addr_hit[274] = (reg_addr == PINMUX_MIO_PAD_ATTR_18_OFFSET);
Tests: T1 T2 T3
32808 1/1 addr_hit[275] = (reg_addr == PINMUX_MIO_PAD_ATTR_19_OFFSET);
Tests: T1 T2 T3
32809 1/1 addr_hit[276] = (reg_addr == PINMUX_MIO_PAD_ATTR_20_OFFSET);
Tests: T1 T2 T3
32810 1/1 addr_hit[277] = (reg_addr == PINMUX_MIO_PAD_ATTR_21_OFFSET);
Tests: T1 T2 T3
32811 1/1 addr_hit[278] = (reg_addr == PINMUX_MIO_PAD_ATTR_22_OFFSET);
Tests: T1 T2 T3
32812 1/1 addr_hit[279] = (reg_addr == PINMUX_MIO_PAD_ATTR_23_OFFSET);
Tests: T1 T2 T3
32813 1/1 addr_hit[280] = (reg_addr == PINMUX_MIO_PAD_ATTR_24_OFFSET);
Tests: T1 T2 T3
32814 1/1 addr_hit[281] = (reg_addr == PINMUX_MIO_PAD_ATTR_25_OFFSET);
Tests: T1 T2 T3
32815 1/1 addr_hit[282] = (reg_addr == PINMUX_MIO_PAD_ATTR_26_OFFSET);
Tests: T1 T2 T3
32816 1/1 addr_hit[283] = (reg_addr == PINMUX_MIO_PAD_ATTR_27_OFFSET);
Tests: T1 T2 T3
32817 1/1 addr_hit[284] = (reg_addr == PINMUX_MIO_PAD_ATTR_28_OFFSET);
Tests: T1 T2 T3
32818 1/1 addr_hit[285] = (reg_addr == PINMUX_MIO_PAD_ATTR_29_OFFSET);
Tests: T1 T2 T3
32819 1/1 addr_hit[286] = (reg_addr == PINMUX_MIO_PAD_ATTR_30_OFFSET);
Tests: T1 T2 T3
32820 1/1 addr_hit[287] = (reg_addr == PINMUX_MIO_PAD_ATTR_31_OFFSET);
Tests: T1 T2 T3
32821 1/1 addr_hit[288] = (reg_addr == PINMUX_MIO_PAD_ATTR_32_OFFSET);
Tests: T1 T2 T3
32822 1/1 addr_hit[289] = (reg_addr == PINMUX_MIO_PAD_ATTR_33_OFFSET);
Tests: T1 T2 T3
32823 1/1 addr_hit[290] = (reg_addr == PINMUX_MIO_PAD_ATTR_34_OFFSET);
Tests: T1 T2 T3
32824 1/1 addr_hit[291] = (reg_addr == PINMUX_MIO_PAD_ATTR_35_OFFSET);
Tests: T1 T2 T3
32825 1/1 addr_hit[292] = (reg_addr == PINMUX_MIO_PAD_ATTR_36_OFFSET);
Tests: T1 T2 T3
32826 1/1 addr_hit[293] = (reg_addr == PINMUX_MIO_PAD_ATTR_37_OFFSET);
Tests: T1 T2 T3
32827 1/1 addr_hit[294] = (reg_addr == PINMUX_MIO_PAD_ATTR_38_OFFSET);
Tests: T1 T2 T3
32828 1/1 addr_hit[295] = (reg_addr == PINMUX_MIO_PAD_ATTR_39_OFFSET);
Tests: T1 T2 T3
32829 1/1 addr_hit[296] = (reg_addr == PINMUX_MIO_PAD_ATTR_40_OFFSET);
Tests: T1 T2 T3
32830 1/1 addr_hit[297] = (reg_addr == PINMUX_MIO_PAD_ATTR_41_OFFSET);
Tests: T1 T2 T3
32831 1/1 addr_hit[298] = (reg_addr == PINMUX_MIO_PAD_ATTR_42_OFFSET);
Tests: T1 T2 T3
32832 1/1 addr_hit[299] = (reg_addr == PINMUX_MIO_PAD_ATTR_43_OFFSET);
Tests: T1 T2 T3
32833 1/1 addr_hit[300] = (reg_addr == PINMUX_MIO_PAD_ATTR_44_OFFSET);
Tests: T1 T2 T3
32834 1/1 addr_hit[301] = (reg_addr == PINMUX_MIO_PAD_ATTR_45_OFFSET);
Tests: T1 T2 T3
32835 1/1 addr_hit[302] = (reg_addr == PINMUX_MIO_PAD_ATTR_46_OFFSET);
Tests: T1 T2 T3
32836 1/1 addr_hit[303] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_0_OFFSET);
Tests: T1 T2 T3
32837 1/1 addr_hit[304] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_1_OFFSET);
Tests: T1 T2 T3
32838 1/1 addr_hit[305] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_2_OFFSET);
Tests: T1 T2 T3
32839 1/1 addr_hit[306] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_3_OFFSET);
Tests: T1 T2 T3
32840 1/1 addr_hit[307] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_4_OFFSET);
Tests: T1 T2 T3
32841 1/1 addr_hit[308] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_5_OFFSET);
Tests: T1 T2 T3
32842 1/1 addr_hit[309] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_6_OFFSET);
Tests: T1 T2 T3
32843 1/1 addr_hit[310] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_7_OFFSET);
Tests: T1 T2 T3
32844 1/1 addr_hit[311] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_8_OFFSET);
Tests: T1 T2 T3
32845 1/1 addr_hit[312] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_9_OFFSET);
Tests: T1 T2 T3
32846 1/1 addr_hit[313] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_10_OFFSET);
Tests: T1 T2 T3
32847 1/1 addr_hit[314] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_11_OFFSET);
Tests: T1 T2 T3
32848 1/1 addr_hit[315] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_12_OFFSET);
Tests: T1 T2 T3
32849 1/1 addr_hit[316] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_13_OFFSET);
Tests: T1 T2 T3
32850 1/1 addr_hit[317] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_14_OFFSET);
Tests: T1 T2 T3
32851 1/1 addr_hit[318] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_15_OFFSET);
Tests: T1 T2 T3
32852 1/1 addr_hit[319] = (reg_addr == PINMUX_DIO_PAD_ATTR_0_OFFSET);
Tests: T1 T2 T3
32853 1/1 addr_hit[320] = (reg_addr == PINMUX_DIO_PAD_ATTR_1_OFFSET);
Tests: T1 T2 T3
32854 1/1 addr_hit[321] = (reg_addr == PINMUX_DIO_PAD_ATTR_2_OFFSET);
Tests: T1 T2 T3
32855 1/1 addr_hit[322] = (reg_addr == PINMUX_DIO_PAD_ATTR_3_OFFSET);
Tests: T1 T2 T3
32856 1/1 addr_hit[323] = (reg_addr == PINMUX_DIO_PAD_ATTR_4_OFFSET);
Tests: T1 T2 T3
32857 1/1 addr_hit[324] = (reg_addr == PINMUX_DIO_PAD_ATTR_5_OFFSET);
Tests: T1 T2 T3
32858 1/1 addr_hit[325] = (reg_addr == PINMUX_DIO_PAD_ATTR_6_OFFSET);
Tests: T1 T2 T3
32859 1/1 addr_hit[326] = (reg_addr == PINMUX_DIO_PAD_ATTR_7_OFFSET);
Tests: T1 T2 T3
32860 1/1 addr_hit[327] = (reg_addr == PINMUX_DIO_PAD_ATTR_8_OFFSET);
Tests: T1 T2 T3
32861 1/1 addr_hit[328] = (reg_addr == PINMUX_DIO_PAD_ATTR_9_OFFSET);
Tests: T1 T2 T3
32862 1/1 addr_hit[329] = (reg_addr == PINMUX_DIO_PAD_ATTR_10_OFFSET);
Tests: T1 T2 T3
32863 1/1 addr_hit[330] = (reg_addr == PINMUX_DIO_PAD_ATTR_11_OFFSET);
Tests: T1 T2 T3
32864 1/1 addr_hit[331] = (reg_addr == PINMUX_DIO_PAD_ATTR_12_OFFSET);
Tests: T1 T2 T3
32865 1/1 addr_hit[332] = (reg_addr == PINMUX_DIO_PAD_ATTR_13_OFFSET);
Tests: T1 T2 T3
32866 1/1 addr_hit[333] = (reg_addr == PINMUX_DIO_PAD_ATTR_14_OFFSET);
Tests: T1 T2 T3
32867 1/1 addr_hit[334] = (reg_addr == PINMUX_DIO_PAD_ATTR_15_OFFSET);
Tests: T1 T2 T3
32868 1/1 addr_hit[335] = (reg_addr == PINMUX_MIO_PAD_SLEEP_STATUS_0_OFFSET);
Tests: T1 T2 T3
32869 1/1 addr_hit[336] = (reg_addr == PINMUX_MIO_PAD_SLEEP_STATUS_1_OFFSET);
Tests: T1 T2 T3
32870 1/1 addr_hit[337] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_0_OFFSET);
Tests: T1 T2 T3
32871 1/1 addr_hit[338] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_1_OFFSET);
Tests: T1 T2 T3
32872 1/1 addr_hit[339] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_2_OFFSET);
Tests: T1 T2 T3
32873 1/1 addr_hit[340] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_3_OFFSET);
Tests: T1 T2 T3
32874 1/1 addr_hit[341] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_4_OFFSET);
Tests: T1 T2 T3
32875 1/1 addr_hit[342] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_5_OFFSET);
Tests: T1 T2 T3
32876 1/1 addr_hit[343] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_6_OFFSET);
Tests: T1 T2 T3
32877 1/1 addr_hit[344] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_7_OFFSET);
Tests: T1 T2 T3
32878 1/1 addr_hit[345] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_8_OFFSET);
Tests: T1 T2 T3
32879 1/1 addr_hit[346] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_9_OFFSET);
Tests: T1 T2 T3
32880 1/1 addr_hit[347] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_10_OFFSET);
Tests: T1 T2 T3
32881 1/1 addr_hit[348] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_11_OFFSET);
Tests: T1 T2 T3
32882 1/1 addr_hit[349] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_12_OFFSET);
Tests: T1 T2 T3
32883 1/1 addr_hit[350] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_13_OFFSET);
Tests: T1 T2 T3
32884 1/1 addr_hit[351] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_14_OFFSET);
Tests: T1 T2 T3
32885 1/1 addr_hit[352] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_15_OFFSET);
Tests: T1 T2 T3
32886 1/1 addr_hit[353] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_16_OFFSET);
Tests: T1 T2 T3
32887 1/1 addr_hit[354] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_17_OFFSET);
Tests: T1 T2 T3
32888 1/1 addr_hit[355] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_18_OFFSET);
Tests: T1 T2 T3
32889 1/1 addr_hit[356] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_19_OFFSET);
Tests: T1 T2 T3
32890 1/1 addr_hit[357] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_20_OFFSET);
Tests: T1 T2 T3
32891 1/1 addr_hit[358] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_21_OFFSET);
Tests: T1 T2 T3
32892 1/1 addr_hit[359] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_22_OFFSET);
Tests: T1 T2 T3
32893 1/1 addr_hit[360] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_23_OFFSET);
Tests: T1 T2 T3
32894 1/1 addr_hit[361] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_24_OFFSET);
Tests: T1 T2 T3
32895 1/1 addr_hit[362] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_25_OFFSET);
Tests: T1 T2 T3
32896 1/1 addr_hit[363] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_26_OFFSET);
Tests: T1 T2 T3
32897 1/1 addr_hit[364] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_27_OFFSET);
Tests: T1 T2 T3
32898 1/1 addr_hit[365] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_28_OFFSET);
Tests: T1 T2 T3
32899 1/1 addr_hit[366] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_29_OFFSET);
Tests: T1 T2 T3
32900 1/1 addr_hit[367] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_30_OFFSET);
Tests: T1 T2 T3
32901 1/1 addr_hit[368] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_31_OFFSET);
Tests: T1 T2 T3
32902 1/1 addr_hit[369] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_32_OFFSET);
Tests: T1 T2 T3
32903 1/1 addr_hit[370] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_33_OFFSET);
Tests: T1 T2 T3
32904 1/1 addr_hit[371] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_34_OFFSET);
Tests: T1 T2 T3
32905 1/1 addr_hit[372] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_35_OFFSET);
Tests: T1 T2 T3
32906 1/1 addr_hit[373] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_36_OFFSET);
Tests: T1 T2 T3
32907 1/1 addr_hit[374] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_37_OFFSET);
Tests: T1 T2 T3
32908 1/1 addr_hit[375] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_38_OFFSET);
Tests: T1 T2 T3
32909 1/1 addr_hit[376] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_39_OFFSET);
Tests: T1 T2 T3
32910 1/1 addr_hit[377] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_40_OFFSET);
Tests: T1 T2 T3
32911 1/1 addr_hit[378] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_41_OFFSET);
Tests: T1 T2 T3
32912 1/1 addr_hit[379] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_42_OFFSET);
Tests: T1 T2 T3
32913 1/1 addr_hit[380] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_43_OFFSET);
Tests: T1 T2 T3
32914 1/1 addr_hit[381] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_44_OFFSET);
Tests: T1 T2 T3
32915 1/1 addr_hit[382] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_45_OFFSET);
Tests: T1 T2 T3
32916 1/1 addr_hit[383] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_46_OFFSET);
Tests: T1 T2 T3
32917 1/1 addr_hit[384] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_0_OFFSET);
Tests: T1 T2 T3
32918 1/1 addr_hit[385] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_1_OFFSET);
Tests: T1 T2 T3
32919 1/1 addr_hit[386] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_2_OFFSET);
Tests: T1 T2 T3
32920 1/1 addr_hit[387] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_3_OFFSET);
Tests: T1 T2 T3
32921 1/1 addr_hit[388] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_4_OFFSET);
Tests: T1 T2 T3
32922 1/1 addr_hit[389] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_5_OFFSET);
Tests: T1 T2 T3
32923 1/1 addr_hit[390] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_6_OFFSET);
Tests: T1 T2 T3
32924 1/1 addr_hit[391] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_7_OFFSET);
Tests: T1 T2 T3
32925 1/1 addr_hit[392] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_8_OFFSET);
Tests: T1 T2 T3
32926 1/1 addr_hit[393] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_9_OFFSET);
Tests: T1 T2 T3
32927 1/1 addr_hit[394] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_10_OFFSET);
Tests: T1 T2 T3
32928 1/1 addr_hit[395] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_11_OFFSET);
Tests: T1 T2 T3
32929 1/1 addr_hit[396] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_12_OFFSET);
Tests: T1 T2 T3
32930 1/1 addr_hit[397] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_13_OFFSET);
Tests: T1 T2 T3
32931 1/1 addr_hit[398] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_14_OFFSET);
Tests: T1 T2 T3
32932 1/1 addr_hit[399] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_15_OFFSET);
Tests: T1 T2 T3
32933 1/1 addr_hit[400] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_16_OFFSET);
Tests: T1 T2 T3
32934 1/1 addr_hit[401] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_17_OFFSET);
Tests: T1 T2 T3
32935 1/1 addr_hit[402] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_18_OFFSET);
Tests: T1 T2 T3
32936 1/1 addr_hit[403] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_19_OFFSET);
Tests: T1 T2 T3
32937 1/1 addr_hit[404] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_20_OFFSET);
Tests: T1 T2 T3
32938 1/1 addr_hit[405] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_21_OFFSET);
Tests: T1 T2 T3
32939 1/1 addr_hit[406] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_22_OFFSET);
Tests: T1 T2 T3
32940 1/1 addr_hit[407] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_23_OFFSET);
Tests: T1 T2 T3
32941 1/1 addr_hit[408] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_24_OFFSET);
Tests: T1 T2 T3
32942 1/1 addr_hit[409] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_25_OFFSET);
Tests: T1 T2 T3
32943 1/1 addr_hit[410] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_26_OFFSET);
Tests: T1 T2 T3
32944 1/1 addr_hit[411] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_27_OFFSET);
Tests: T1 T2 T3
32945 1/1 addr_hit[412] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_28_OFFSET);
Tests: T1 T2 T3
32946 1/1 addr_hit[413] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_29_OFFSET);
Tests: T1 T2 T3
32947 1/1 addr_hit[414] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_30_OFFSET);
Tests: T1 T2 T3
32948 1/1 addr_hit[415] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_31_OFFSET);
Tests: T1 T2 T3
32949 1/1 addr_hit[416] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_32_OFFSET);
Tests: T1 T2 T3
32950 1/1 addr_hit[417] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_33_OFFSET);
Tests: T1 T2 T3
32951 1/1 addr_hit[418] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_34_OFFSET);
Tests: T1 T2 T3
32952 1/1 addr_hit[419] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_35_OFFSET);
Tests: T1 T2 T3
32953 1/1 addr_hit[420] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_36_OFFSET);
Tests: T1 T2 T3
32954 1/1 addr_hit[421] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_37_OFFSET);
Tests: T1 T2 T3
32955 1/1 addr_hit[422] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_38_OFFSET);
Tests: T1 T2 T3
32956 1/1 addr_hit[423] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_39_OFFSET);
Tests: T1 T2 T3
32957 1/1 addr_hit[424] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_40_OFFSET);
Tests: T1 T2 T3
32958 1/1 addr_hit[425] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_41_OFFSET);
Tests: T1 T2 T3
32959 1/1 addr_hit[426] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_42_OFFSET);
Tests: T1 T2 T3
32960 1/1 addr_hit[427] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_43_OFFSET);
Tests: T1 T2 T3
32961 1/1 addr_hit[428] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_44_OFFSET);
Tests: T1 T2 T3
32962 1/1 addr_hit[429] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_45_OFFSET);
Tests: T1 T2 T3
32963 1/1 addr_hit[430] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_46_OFFSET);
Tests: T1 T2 T3
32964 1/1 addr_hit[431] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_0_OFFSET);
Tests: T1 T2 T3
32965 1/1 addr_hit[432] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_1_OFFSET);
Tests: T1 T2 T3
32966 1/1 addr_hit[433] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_2_OFFSET);
Tests: T1 T2 T3
32967 1/1 addr_hit[434] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_3_OFFSET);
Tests: T1 T2 T3
32968 1/1 addr_hit[435] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_4_OFFSET);
Tests: T1 T2 T3
32969 1/1 addr_hit[436] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_5_OFFSET);
Tests: T1 T2 T3
32970 1/1 addr_hit[437] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_6_OFFSET);
Tests: T1 T2 T3
32971 1/1 addr_hit[438] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_7_OFFSET);
Tests: T1 T2 T3
32972 1/1 addr_hit[439] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_8_OFFSET);
Tests: T1 T2 T3
32973 1/1 addr_hit[440] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_9_OFFSET);
Tests: T1 T2 T3
32974 1/1 addr_hit[441] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_10_OFFSET);
Tests: T1 T2 T3
32975 1/1 addr_hit[442] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_11_OFFSET);
Tests: T1 T2 T3
32976 1/1 addr_hit[443] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_12_OFFSET);
Tests: T1 T2 T3
32977 1/1 addr_hit[444] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_13_OFFSET);
Tests: T1 T2 T3
32978 1/1 addr_hit[445] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_14_OFFSET);
Tests: T1 T2 T3
32979 1/1 addr_hit[446] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_15_OFFSET);
Tests: T1 T2 T3
32980 1/1 addr_hit[447] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_16_OFFSET);
Tests: T1 T2 T3
32981 1/1 addr_hit[448] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_17_OFFSET);
Tests: T1 T2 T3
32982 1/1 addr_hit[449] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_18_OFFSET);
Tests: T1 T2 T3
32983 1/1 addr_hit[450] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_19_OFFSET);
Tests: T1 T2 T3
32984 1/1 addr_hit[451] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_20_OFFSET);
Tests: T1 T2 T3
32985 1/1 addr_hit[452] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_21_OFFSET);
Tests: T1 T2 T3
32986 1/1 addr_hit[453] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_22_OFFSET);
Tests: T1 T2 T3
32987 1/1 addr_hit[454] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_23_OFFSET);
Tests: T1 T2 T3
32988 1/1 addr_hit[455] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_24_OFFSET);
Tests: T1 T2 T3
32989 1/1 addr_hit[456] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_25_OFFSET);
Tests: T1 T2 T3
32990 1/1 addr_hit[457] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_26_OFFSET);
Tests: T1 T2 T3
32991 1/1 addr_hit[458] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_27_OFFSET);
Tests: T1 T2 T3
32992 1/1 addr_hit[459] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_28_OFFSET);
Tests: T1 T2 T3
32993 1/1 addr_hit[460] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_29_OFFSET);
Tests: T1 T2 T3
32994 1/1 addr_hit[461] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_30_OFFSET);
Tests: T1 T2 T3
32995 1/1 addr_hit[462] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_31_OFFSET);
Tests: T1 T2 T3
32996 1/1 addr_hit[463] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_32_OFFSET);
Tests: T1 T2 T3
32997 1/1 addr_hit[464] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_33_OFFSET);
Tests: T1 T2 T3
32998 1/1 addr_hit[465] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_34_OFFSET);
Tests: T1 T2 T3
32999 1/1 addr_hit[466] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_35_OFFSET);
Tests: T1 T2 T3
33000 1/1 addr_hit[467] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_36_OFFSET);
Tests: T1 T2 T3
33001 1/1 addr_hit[468] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_37_OFFSET);
Tests: T1 T2 T3
33002 1/1 addr_hit[469] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_38_OFFSET);
Tests: T1 T2 T3
33003 1/1 addr_hit[470] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_39_OFFSET);
Tests: T1 T2 T3
33004 1/1 addr_hit[471] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_40_OFFSET);
Tests: T1 T2 T3
33005 1/1 addr_hit[472] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_41_OFFSET);
Tests: T1 T2 T3
33006 1/1 addr_hit[473] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_42_OFFSET);
Tests: T1 T2 T3
33007 1/1 addr_hit[474] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_43_OFFSET);
Tests: T1 T2 T3
33008 1/1 addr_hit[475] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_44_OFFSET);
Tests: T1 T2 T3
33009 1/1 addr_hit[476] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_45_OFFSET);
Tests: T1 T2 T3
33010 1/1 addr_hit[477] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_46_OFFSET);
Tests: T1 T2 T3
33011 1/1 addr_hit[478] = (reg_addr == PINMUX_DIO_PAD_SLEEP_STATUS_OFFSET);
Tests: T1 T2 T3
33012 1/1 addr_hit[479] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_0_OFFSET);
Tests: T1 T2 T3
33013 1/1 addr_hit[480] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_1_OFFSET);
Tests: T1 T2 T3
33014 1/1 addr_hit[481] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_2_OFFSET);
Tests: T1 T2 T3
33015 1/1 addr_hit[482] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_3_OFFSET);
Tests: T1 T2 T3
33016 1/1 addr_hit[483] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_4_OFFSET);
Tests: T1 T2 T3
33017 1/1 addr_hit[484] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_5_OFFSET);
Tests: T1 T2 T3
33018 1/1 addr_hit[485] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_6_OFFSET);
Tests: T1 T2 T3
33019 1/1 addr_hit[486] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_7_OFFSET);
Tests: T1 T2 T3
33020 1/1 addr_hit[487] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_8_OFFSET);
Tests: T1 T2 T3
33021 1/1 addr_hit[488] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_9_OFFSET);
Tests: T1 T2 T3
33022 1/1 addr_hit[489] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_10_OFFSET);
Tests: T1 T2 T3
33023 1/1 addr_hit[490] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_11_OFFSET);
Tests: T1 T2 T3
33024 1/1 addr_hit[491] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_12_OFFSET);
Tests: T1 T2 T3
33025 1/1 addr_hit[492] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_13_OFFSET);
Tests: T1 T2 T3
33026 1/1 addr_hit[493] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_14_OFFSET);
Tests: T1 T2 T3
33027 1/1 addr_hit[494] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_15_OFFSET);
Tests: T1 T2 T3
33028 1/1 addr_hit[495] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_0_OFFSET);
Tests: T1 T2 T3
33029 1/1 addr_hit[496] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_1_OFFSET);
Tests: T1 T2 T3
33030 1/1 addr_hit[497] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_2_OFFSET);
Tests: T1 T2 T3
33031 1/1 addr_hit[498] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_3_OFFSET);
Tests: T1 T2 T3
33032 1/1 addr_hit[499] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_4_OFFSET);
Tests: T1 T2 T3
33033 1/1 addr_hit[500] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_5_OFFSET);
Tests: T1 T2 T3
33034 1/1 addr_hit[501] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_6_OFFSET);
Tests: T1 T2 T3
33035 1/1 addr_hit[502] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_7_OFFSET);
Tests: T1 T2 T3
33036 1/1 addr_hit[503] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_8_OFFSET);
Tests: T1 T2 T3
33037 1/1 addr_hit[504] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_9_OFFSET);
Tests: T1 T2 T3
33038 1/1 addr_hit[505] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_10_OFFSET);
Tests: T1 T2 T3
33039 1/1 addr_hit[506] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_11_OFFSET);
Tests: T1 T2 T3
33040 1/1 addr_hit[507] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_12_OFFSET);
Tests: T1 T2 T3
33041 1/1 addr_hit[508] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_13_OFFSET);
Tests: T1 T2 T3
33042 1/1 addr_hit[509] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_14_OFFSET);
Tests: T1 T2 T3
33043 1/1 addr_hit[510] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_15_OFFSET);
Tests: T1 T2 T3
33044 1/1 addr_hit[511] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_0_OFFSET);
Tests: T1 T2 T3
33045 1/1 addr_hit[512] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_1_OFFSET);
Tests: T1 T2 T3
33046 1/1 addr_hit[513] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_2_OFFSET);
Tests: T1 T2 T3
33047 1/1 addr_hit[514] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_3_OFFSET);
Tests: T1 T2 T3
33048 1/1 addr_hit[515] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_4_OFFSET);
Tests: T1 T2 T3
33049 1/1 addr_hit[516] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_5_OFFSET);
Tests: T1 T2 T3
33050 1/1 addr_hit[517] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_6_OFFSET);
Tests: T1 T2 T3
33051 1/1 addr_hit[518] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_7_OFFSET);
Tests: T1 T2 T3
33052 1/1 addr_hit[519] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_8_OFFSET);
Tests: T1 T2 T3
33053 1/1 addr_hit[520] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_9_OFFSET);
Tests: T1 T2 T3
33054 1/1 addr_hit[521] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_10_OFFSET);
Tests: T1 T2 T3
33055 1/1 addr_hit[522] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_11_OFFSET);
Tests: T1 T2 T3
33056 1/1 addr_hit[523] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_12_OFFSET);
Tests: T1 T2 T3
33057 1/1 addr_hit[524] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_13_OFFSET);
Tests: T1 T2 T3
33058 1/1 addr_hit[525] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_14_OFFSET);
Tests: T1 T2 T3
33059 1/1 addr_hit[526] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_15_OFFSET);
Tests: T1 T2 T3
33060 1/1 addr_hit[527] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_0_OFFSET);
Tests: T1 T2 T3
33061 1/1 addr_hit[528] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_1_OFFSET);
Tests: T1 T2 T3
33062 1/1 addr_hit[529] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_2_OFFSET);
Tests: T1 T2 T3
33063 1/1 addr_hit[530] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_3_OFFSET);
Tests: T1 T2 T3
33064 1/1 addr_hit[531] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_4_OFFSET);
Tests: T1 T2 T3
33065 1/1 addr_hit[532] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_5_OFFSET);
Tests: T1 T2 T3
33066 1/1 addr_hit[533] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_6_OFFSET);
Tests: T1 T2 T3
33067 1/1 addr_hit[534] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_7_OFFSET);
Tests: T1 T2 T3
33068 1/1 addr_hit[535] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_0_OFFSET);
Tests: T1 T2 T3
33069 1/1 addr_hit[536] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_1_OFFSET);
Tests: T1 T2 T3
33070 1/1 addr_hit[537] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_2_OFFSET);
Tests: T1 T2 T3
33071 1/1 addr_hit[538] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_3_OFFSET);
Tests: T1 T2 T3
33072 1/1 addr_hit[539] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_4_OFFSET);
Tests: T1 T2 T3
33073 1/1 addr_hit[540] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_5_OFFSET);
Tests: T1 T2 T3
33074 1/1 addr_hit[541] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_6_OFFSET);
Tests: T1 T2 T3
33075 1/1 addr_hit[542] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_7_OFFSET);
Tests: T1 T2 T3
33076 1/1 addr_hit[543] = (reg_addr == PINMUX_WKUP_DETECTOR_0_OFFSET);
Tests: T1 T2 T3
33077 1/1 addr_hit[544] = (reg_addr == PINMUX_WKUP_DETECTOR_1_OFFSET);
Tests: T1 T2 T3
33078 1/1 addr_hit[545] = (reg_addr == PINMUX_WKUP_DETECTOR_2_OFFSET);
Tests: T1 T2 T3
33079 1/1 addr_hit[546] = (reg_addr == PINMUX_WKUP_DETECTOR_3_OFFSET);
Tests: T1 T2 T3
33080 1/1 addr_hit[547] = (reg_addr == PINMUX_WKUP_DETECTOR_4_OFFSET);
Tests: T1 T2 T3
33081 1/1 addr_hit[548] = (reg_addr == PINMUX_WKUP_DETECTOR_5_OFFSET);
Tests: T1 T2 T3
33082 1/1 addr_hit[549] = (reg_addr == PINMUX_WKUP_DETECTOR_6_OFFSET);
Tests: T1 T2 T3
33083 1/1 addr_hit[550] = (reg_addr == PINMUX_WKUP_DETECTOR_7_OFFSET);
Tests: T1 T2 T3
33084 1/1 addr_hit[551] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_0_OFFSET);
Tests: T1 T2 T3
33085 1/1 addr_hit[552] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_1_OFFSET);
Tests: T1 T2 T3
33086 1/1 addr_hit[553] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_2_OFFSET);
Tests: T1 T2 T3
33087 1/1 addr_hit[554] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_3_OFFSET);
Tests: T1 T2 T3
33088 1/1 addr_hit[555] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_4_OFFSET);
Tests: T1 T2 T3
33089 1/1 addr_hit[556] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_5_OFFSET);
Tests: T1 T2 T3
33090 1/1 addr_hit[557] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_6_OFFSET);
Tests: T1 T2 T3
33091 1/1 addr_hit[558] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_7_OFFSET);
Tests: T1 T2 T3
33092 1/1 addr_hit[559] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_0_OFFSET);
Tests: T1 T2 T3
33093 1/1 addr_hit[560] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_1_OFFSET);
Tests: T1 T2 T3
33094 1/1 addr_hit[561] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_2_OFFSET);
Tests: T1 T2 T3
33095 1/1 addr_hit[562] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_3_OFFSET);
Tests: T1 T2 T3
33096 1/1 addr_hit[563] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_4_OFFSET);
Tests: T1 T2 T3
33097 1/1 addr_hit[564] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_5_OFFSET);
Tests: T1 T2 T3
33098 1/1 addr_hit[565] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_6_OFFSET);
Tests: T1 T2 T3
33099 1/1 addr_hit[566] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_7_OFFSET);
Tests: T1 T2 T3
33100 1/1 addr_hit[567] = (reg_addr == PINMUX_WKUP_CAUSE_OFFSET);
Tests: T1 T2 T3
33101 end
33102
33103 1/1 assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
Tests: T1 T2 T3
33104
33105 // Check sub-word write is permitted
33106 always_comb begin
33107 1/1 wr_err = (reg_we &
Tests: T1 T2 T3
33108 ((addr_hit[ 0] & (|(PINMUX_PERMIT[ 0] & ~reg_be))) |
33109 (addr_hit[ 1] & (|(PINMUX_PERMIT[ 1] & ~reg_be))) |
33110 (addr_hit[ 2] & (|(PINMUX_PERMIT[ 2] & ~reg_be))) |
33111 (addr_hit[ 3] & (|(PINMUX_PERMIT[ 3] & ~reg_be))) |
33112 (addr_hit[ 4] & (|(PINMUX_PERMIT[ 4] & ~reg_be))) |
33113 (addr_hit[ 5] & (|(PINMUX_PERMIT[ 5] & ~reg_be))) |
33114 (addr_hit[ 6] & (|(PINMUX_PERMIT[ 6] & ~reg_be))) |
33115 (addr_hit[ 7] & (|(PINMUX_PERMIT[ 7] & ~reg_be))) |
33116 (addr_hit[ 8] & (|(PINMUX_PERMIT[ 8] & ~reg_be))) |
33117 (addr_hit[ 9] & (|(PINMUX_PERMIT[ 9] & ~reg_be))) |
33118 (addr_hit[ 10] & (|(PINMUX_PERMIT[ 10] & ~reg_be))) |
33119 (addr_hit[ 11] & (|(PINMUX_PERMIT[ 11] & ~reg_be))) |
33120 (addr_hit[ 12] & (|(PINMUX_PERMIT[ 12] & ~reg_be))) |
33121 (addr_hit[ 13] & (|(PINMUX_PERMIT[ 13] & ~reg_be))) |
33122 (addr_hit[ 14] & (|(PINMUX_PERMIT[ 14] & ~reg_be))) |
33123 (addr_hit[ 15] & (|(PINMUX_PERMIT[ 15] & ~reg_be))) |
33124 (addr_hit[ 16] & (|(PINMUX_PERMIT[ 16] & ~reg_be))) |
33125 (addr_hit[ 17] & (|(PINMUX_PERMIT[ 17] & ~reg_be))) |
33126 (addr_hit[ 18] & (|(PINMUX_PERMIT[ 18] & ~reg_be))) |
33127 (addr_hit[ 19] & (|(PINMUX_PERMIT[ 19] & ~reg_be))) |
33128 (addr_hit[ 20] & (|(PINMUX_PERMIT[ 20] & ~reg_be))) |
33129 (addr_hit[ 21] & (|(PINMUX_PERMIT[ 21] & ~reg_be))) |
33130 (addr_hit[ 22] & (|(PINMUX_PERMIT[ 22] & ~reg_be))) |
33131 (addr_hit[ 23] & (|(PINMUX_PERMIT[ 23] & ~reg_be))) |
33132 (addr_hit[ 24] & (|(PINMUX_PERMIT[ 24] & ~reg_be))) |
33133 (addr_hit[ 25] & (|(PINMUX_PERMIT[ 25] & ~reg_be))) |
33134 (addr_hit[ 26] & (|(PINMUX_PERMIT[ 26] & ~reg_be))) |
33135 (addr_hit[ 27] & (|(PINMUX_PERMIT[ 27] & ~reg_be))) |
33136 (addr_hit[ 28] & (|(PINMUX_PERMIT[ 28] & ~reg_be))) |
33137 (addr_hit[ 29] & (|(PINMUX_PERMIT[ 29] & ~reg_be))) |
33138 (addr_hit[ 30] & (|(PINMUX_PERMIT[ 30] & ~reg_be))) |
33139 (addr_hit[ 31] & (|(PINMUX_PERMIT[ 31] & ~reg_be))) |
33140 (addr_hit[ 32] & (|(PINMUX_PERMIT[ 32] & ~reg_be))) |
33141 (addr_hit[ 33] & (|(PINMUX_PERMIT[ 33] & ~reg_be))) |
33142 (addr_hit[ 34] & (|(PINMUX_PERMIT[ 34] & ~reg_be))) |
33143 (addr_hit[ 35] & (|(PINMUX_PERMIT[ 35] & ~reg_be))) |
33144 (addr_hit[ 36] & (|(PINMUX_PERMIT[ 36] & ~reg_be))) |
33145 (addr_hit[ 37] & (|(PINMUX_PERMIT[ 37] & ~reg_be))) |
33146 (addr_hit[ 38] & (|(PINMUX_PERMIT[ 38] & ~reg_be))) |
33147 (addr_hit[ 39] & (|(PINMUX_PERMIT[ 39] & ~reg_be))) |
33148 (addr_hit[ 40] & (|(PINMUX_PERMIT[ 40] & ~reg_be))) |
33149 (addr_hit[ 41] & (|(PINMUX_PERMIT[ 41] & ~reg_be))) |
33150 (addr_hit[ 42] & (|(PINMUX_PERMIT[ 42] & ~reg_be))) |
33151 (addr_hit[ 43] & (|(PINMUX_PERMIT[ 43] & ~reg_be))) |
33152 (addr_hit[ 44] & (|(PINMUX_PERMIT[ 44] & ~reg_be))) |
33153 (addr_hit[ 45] & (|(PINMUX_PERMIT[ 45] & ~reg_be))) |
33154 (addr_hit[ 46] & (|(PINMUX_PERMIT[ 46] & ~reg_be))) |
33155 (addr_hit[ 47] & (|(PINMUX_PERMIT[ 47] & ~reg_be))) |
33156 (addr_hit[ 48] & (|(PINMUX_PERMIT[ 48] & ~reg_be))) |
33157 (addr_hit[ 49] & (|(PINMUX_PERMIT[ 49] & ~reg_be))) |
33158 (addr_hit[ 50] & (|(PINMUX_PERMIT[ 50] & ~reg_be))) |
33159 (addr_hit[ 51] & (|(PINMUX_PERMIT[ 51] & ~reg_be))) |
33160 (addr_hit[ 52] & (|(PINMUX_PERMIT[ 52] & ~reg_be))) |
33161 (addr_hit[ 53] & (|(PINMUX_PERMIT[ 53] & ~reg_be))) |
33162 (addr_hit[ 54] & (|(PINMUX_PERMIT[ 54] & ~reg_be))) |
33163 (addr_hit[ 55] & (|(PINMUX_PERMIT[ 55] & ~reg_be))) |
33164 (addr_hit[ 56] & (|(PINMUX_PERMIT[ 56] & ~reg_be))) |
33165 (addr_hit[ 57] & (|(PINMUX_PERMIT[ 57] & ~reg_be))) |
33166 (addr_hit[ 58] & (|(PINMUX_PERMIT[ 58] & ~reg_be))) |
33167 (addr_hit[ 59] & (|(PINMUX_PERMIT[ 59] & ~reg_be))) |
33168 (addr_hit[ 60] & (|(PINMUX_PERMIT[ 60] & ~reg_be))) |
33169 (addr_hit[ 61] & (|(PINMUX_PERMIT[ 61] & ~reg_be))) |
33170 (addr_hit[ 62] & (|(PINMUX_PERMIT[ 62] & ~reg_be))) |
33171 (addr_hit[ 63] & (|(PINMUX_PERMIT[ 63] & ~reg_be))) |
33172 (addr_hit[ 64] & (|(PINMUX_PERMIT[ 64] & ~reg_be))) |
33173 (addr_hit[ 65] & (|(PINMUX_PERMIT[ 65] & ~reg_be))) |
33174 (addr_hit[ 66] & (|(PINMUX_PERMIT[ 66] & ~reg_be))) |
33175 (addr_hit[ 67] & (|(PINMUX_PERMIT[ 67] & ~reg_be))) |
33176 (addr_hit[ 68] & (|(PINMUX_PERMIT[ 68] & ~reg_be))) |
33177 (addr_hit[ 69] & (|(PINMUX_PERMIT[ 69] & ~reg_be))) |
33178 (addr_hit[ 70] & (|(PINMUX_PERMIT[ 70] & ~reg_be))) |
33179 (addr_hit[ 71] & (|(PINMUX_PERMIT[ 71] & ~reg_be))) |
33180 (addr_hit[ 72] & (|(PINMUX_PERMIT[ 72] & ~reg_be))) |
33181 (addr_hit[ 73] & (|(PINMUX_PERMIT[ 73] & ~reg_be))) |
33182 (addr_hit[ 74] & (|(PINMUX_PERMIT[ 74] & ~reg_be))) |
33183 (addr_hit[ 75] & (|(PINMUX_PERMIT[ 75] & ~reg_be))) |
33184 (addr_hit[ 76] & (|(PINMUX_PERMIT[ 76] & ~reg_be))) |
33185 (addr_hit[ 77] & (|(PINMUX_PERMIT[ 77] & ~reg_be))) |
33186 (addr_hit[ 78] & (|(PINMUX_PERMIT[ 78] & ~reg_be))) |
33187 (addr_hit[ 79] & (|(PINMUX_PERMIT[ 79] & ~reg_be))) |
33188 (addr_hit[ 80] & (|(PINMUX_PERMIT[ 80] & ~reg_be))) |
33189 (addr_hit[ 81] & (|(PINMUX_PERMIT[ 81] & ~reg_be))) |
33190 (addr_hit[ 82] & (|(PINMUX_PERMIT[ 82] & ~reg_be))) |
33191 (addr_hit[ 83] & (|(PINMUX_PERMIT[ 83] & ~reg_be))) |
33192 (addr_hit[ 84] & (|(PINMUX_PERMIT[ 84] & ~reg_be))) |
33193 (addr_hit[ 85] & (|(PINMUX_PERMIT[ 85] & ~reg_be))) |
33194 (addr_hit[ 86] & (|(PINMUX_PERMIT[ 86] & ~reg_be))) |
33195 (addr_hit[ 87] & (|(PINMUX_PERMIT[ 87] & ~reg_be))) |
33196 (addr_hit[ 88] & (|(PINMUX_PERMIT[ 88] & ~reg_be))) |
33197 (addr_hit[ 89] & (|(PINMUX_PERMIT[ 89] & ~reg_be))) |
33198 (addr_hit[ 90] & (|(PINMUX_PERMIT[ 90] & ~reg_be))) |
33199 (addr_hit[ 91] & (|(PINMUX_PERMIT[ 91] & ~reg_be))) |
33200 (addr_hit[ 92] & (|(PINMUX_PERMIT[ 92] & ~reg_be))) |
33201 (addr_hit[ 93] & (|(PINMUX_PERMIT[ 93] & ~reg_be))) |
33202 (addr_hit[ 94] & (|(PINMUX_PERMIT[ 94] & ~reg_be))) |
33203 (addr_hit[ 95] & (|(PINMUX_PERMIT[ 95] & ~reg_be))) |
33204 (addr_hit[ 96] & (|(PINMUX_PERMIT[ 96] & ~reg_be))) |
33205 (addr_hit[ 97] & (|(PINMUX_PERMIT[ 97] & ~reg_be))) |
33206 (addr_hit[ 98] & (|(PINMUX_PERMIT[ 98] & ~reg_be))) |
33207 (addr_hit[ 99] & (|(PINMUX_PERMIT[ 99] & ~reg_be))) |
33208 (addr_hit[100] & (|(PINMUX_PERMIT[100] & ~reg_be))) |
33209 (addr_hit[101] & (|(PINMUX_PERMIT[101] & ~reg_be))) |
33210 (addr_hit[102] & (|(PINMUX_PERMIT[102] & ~reg_be))) |
33211 (addr_hit[103] & (|(PINMUX_PERMIT[103] & ~reg_be))) |
33212 (addr_hit[104] & (|(PINMUX_PERMIT[104] & ~reg_be))) |
33213 (addr_hit[105] & (|(PINMUX_PERMIT[105] & ~reg_be))) |
33214 (addr_hit[106] & (|(PINMUX_PERMIT[106] & ~reg_be))) |
33215 (addr_hit[107] & (|(PINMUX_PERMIT[107] & ~reg_be))) |
33216 (addr_hit[108] & (|(PINMUX_PERMIT[108] & ~reg_be))) |
33217 (addr_hit[109] & (|(PINMUX_PERMIT[109] & ~reg_be))) |
33218 (addr_hit[110] & (|(PINMUX_PERMIT[110] & ~reg_be))) |
33219 (addr_hit[111] & (|(PINMUX_PERMIT[111] & ~reg_be))) |
33220 (addr_hit[112] & (|(PINMUX_PERMIT[112] & ~reg_be))) |
33221 (addr_hit[113] & (|(PINMUX_PERMIT[113] & ~reg_be))) |
33222 (addr_hit[114] & (|(PINMUX_PERMIT[114] & ~reg_be))) |
33223 (addr_hit[115] & (|(PINMUX_PERMIT[115] & ~reg_be))) |
33224 (addr_hit[116] & (|(PINMUX_PERMIT[116] & ~reg_be))) |
33225 (addr_hit[117] & (|(PINMUX_PERMIT[117] & ~reg_be))) |
33226 (addr_hit[118] & (|(PINMUX_PERMIT[118] & ~reg_be))) |
33227 (addr_hit[119] & (|(PINMUX_PERMIT[119] & ~reg_be))) |
33228 (addr_hit[120] & (|(PINMUX_PERMIT[120] & ~reg_be))) |
33229 (addr_hit[121] & (|(PINMUX_PERMIT[121] & ~reg_be))) |
33230 (addr_hit[122] & (|(PINMUX_PERMIT[122] & ~reg_be))) |
33231 (addr_hit[123] & (|(PINMUX_PERMIT[123] & ~reg_be))) |
33232 (addr_hit[124] & (|(PINMUX_PERMIT[124] & ~reg_be))) |
33233 (addr_hit[125] & (|(PINMUX_PERMIT[125] & ~reg_be))) |
33234 (addr_hit[126] & (|(PINMUX_PERMIT[126] & ~reg_be))) |
33235 (addr_hit[127] & (|(PINMUX_PERMIT[127] & ~reg_be))) |
33236 (addr_hit[128] & (|(PINMUX_PERMIT[128] & ~reg_be))) |
33237 (addr_hit[129] & (|(PINMUX_PERMIT[129] & ~reg_be))) |
33238 (addr_hit[130] & (|(PINMUX_PERMIT[130] & ~reg_be))) |
33239 (addr_hit[131] & (|(PINMUX_PERMIT[131] & ~reg_be))) |
33240 (addr_hit[132] & (|(PINMUX_PERMIT[132] & ~reg_be))) |
33241 (addr_hit[133] & (|(PINMUX_PERMIT[133] & ~reg_be))) |
33242 (addr_hit[134] & (|(PINMUX_PERMIT[134] & ~reg_be))) |
33243 (addr_hit[135] & (|(PINMUX_PERMIT[135] & ~reg_be))) |
33244 (addr_hit[136] & (|(PINMUX_PERMIT[136] & ~reg_be))) |
33245 (addr_hit[137] & (|(PINMUX_PERMIT[137] & ~reg_be))) |
33246 (addr_hit[138] & (|(PINMUX_PERMIT[138] & ~reg_be))) |
33247 (addr_hit[139] & (|(PINMUX_PERMIT[139] & ~reg_be))) |
33248 (addr_hit[140] & (|(PINMUX_PERMIT[140] & ~reg_be))) |
33249 (addr_hit[141] & (|(PINMUX_PERMIT[141] & ~reg_be))) |
33250 (addr_hit[142] & (|(PINMUX_PERMIT[142] & ~reg_be))) |
33251 (addr_hit[143] & (|(PINMUX_PERMIT[143] & ~reg_be))) |
33252 (addr_hit[144] & (|(PINMUX_PERMIT[144] & ~reg_be))) |
33253 (addr_hit[145] & (|(PINMUX_PERMIT[145] & ~reg_be))) |
33254 (addr_hit[146] & (|(PINMUX_PERMIT[146] & ~reg_be))) |
33255 (addr_hit[147] & (|(PINMUX_PERMIT[147] & ~reg_be))) |
33256 (addr_hit[148] & (|(PINMUX_PERMIT[148] & ~reg_be))) |
33257 (addr_hit[149] & (|(PINMUX_PERMIT[149] & ~reg_be))) |
33258 (addr_hit[150] & (|(PINMUX_PERMIT[150] & ~reg_be))) |
33259 (addr_hit[151] & (|(PINMUX_PERMIT[151] & ~reg_be))) |
33260 (addr_hit[152] & (|(PINMUX_PERMIT[152] & ~reg_be))) |
33261 (addr_hit[153] & (|(PINMUX_PERMIT[153] & ~reg_be))) |
33262 (addr_hit[154] & (|(PINMUX_PERMIT[154] & ~reg_be))) |
33263 (addr_hit[155] & (|(PINMUX_PERMIT[155] & ~reg_be))) |
33264 (addr_hit[156] & (|(PINMUX_PERMIT[156] & ~reg_be))) |
33265 (addr_hit[157] & (|(PINMUX_PERMIT[157] & ~reg_be))) |
33266 (addr_hit[158] & (|(PINMUX_PERMIT[158] & ~reg_be))) |
33267 (addr_hit[159] & (|(PINMUX_PERMIT[159] & ~reg_be))) |
33268 (addr_hit[160] & (|(PINMUX_PERMIT[160] & ~reg_be))) |
33269 (addr_hit[161] & (|(PINMUX_PERMIT[161] & ~reg_be))) |
33270 (addr_hit[162] & (|(PINMUX_PERMIT[162] & ~reg_be))) |
33271 (addr_hit[163] & (|(PINMUX_PERMIT[163] & ~reg_be))) |
33272 (addr_hit[164] & (|(PINMUX_PERMIT[164] & ~reg_be))) |
33273 (addr_hit[165] & (|(PINMUX_PERMIT[165] & ~reg_be))) |
33274 (addr_hit[166] & (|(PINMUX_PERMIT[166] & ~reg_be))) |
33275 (addr_hit[167] & (|(PINMUX_PERMIT[167] & ~reg_be))) |
33276 (addr_hit[168] & (|(PINMUX_PERMIT[168] & ~reg_be))) |
33277 (addr_hit[169] & (|(PINMUX_PERMIT[169] & ~reg_be))) |
33278 (addr_hit[170] & (|(PINMUX_PERMIT[170] & ~reg_be))) |
33279 (addr_hit[171] & (|(PINMUX_PERMIT[171] & ~reg_be))) |
33280 (addr_hit[172] & (|(PINMUX_PERMIT[172] & ~reg_be))) |
33281 (addr_hit[173] & (|(PINMUX_PERMIT[173] & ~reg_be))) |
33282 (addr_hit[174] & (|(PINMUX_PERMIT[174] & ~reg_be))) |
33283 (addr_hit[175] & (|(PINMUX_PERMIT[175] & ~reg_be))) |
33284 (addr_hit[176] & (|(PINMUX_PERMIT[176] & ~reg_be))) |
33285 (addr_hit[177] & (|(PINMUX_PERMIT[177] & ~reg_be))) |
33286 (addr_hit[178] & (|(PINMUX_PERMIT[178] & ~reg_be))) |
33287 (addr_hit[179] & (|(PINMUX_PERMIT[179] & ~reg_be))) |
33288 (addr_hit[180] & (|(PINMUX_PERMIT[180] & ~reg_be))) |
33289 (addr_hit[181] & (|(PINMUX_PERMIT[181] & ~reg_be))) |
33290 (addr_hit[182] & (|(PINMUX_PERMIT[182] & ~reg_be))) |
33291 (addr_hit[183] & (|(PINMUX_PERMIT[183] & ~reg_be))) |
33292 (addr_hit[184] & (|(PINMUX_PERMIT[184] & ~reg_be))) |
33293 (addr_hit[185] & (|(PINMUX_PERMIT[185] & ~reg_be))) |
33294 (addr_hit[186] & (|(PINMUX_PERMIT[186] & ~reg_be))) |
33295 (addr_hit[187] & (|(PINMUX_PERMIT[187] & ~reg_be))) |
33296 (addr_hit[188] & (|(PINMUX_PERMIT[188] & ~reg_be))) |
33297 (addr_hit[189] & (|(PINMUX_PERMIT[189] & ~reg_be))) |
33298 (addr_hit[190] & (|(PINMUX_PERMIT[190] & ~reg_be))) |
33299 (addr_hit[191] & (|(PINMUX_PERMIT[191] & ~reg_be))) |
33300 (addr_hit[192] & (|(PINMUX_PERMIT[192] & ~reg_be))) |
33301 (addr_hit[193] & (|(PINMUX_PERMIT[193] & ~reg_be))) |
33302 (addr_hit[194] & (|(PINMUX_PERMIT[194] & ~reg_be))) |
33303 (addr_hit[195] & (|(PINMUX_PERMIT[195] & ~reg_be))) |
33304 (addr_hit[196] & (|(PINMUX_PERMIT[196] & ~reg_be))) |
33305 (addr_hit[197] & (|(PINMUX_PERMIT[197] & ~reg_be))) |
33306 (addr_hit[198] & (|(PINMUX_PERMIT[198] & ~reg_be))) |
33307 (addr_hit[199] & (|(PINMUX_PERMIT[199] & ~reg_be))) |
33308 (addr_hit[200] & (|(PINMUX_PERMIT[200] & ~reg_be))) |
33309 (addr_hit[201] & (|(PINMUX_PERMIT[201] & ~reg_be))) |
33310 (addr_hit[202] & (|(PINMUX_PERMIT[202] & ~reg_be))) |
33311 (addr_hit[203] & (|(PINMUX_PERMIT[203] & ~reg_be))) |
33312 (addr_hit[204] & (|(PINMUX_PERMIT[204] & ~reg_be))) |
33313 (addr_hit[205] & (|(PINMUX_PERMIT[205] & ~reg_be))) |
33314 (addr_hit[206] & (|(PINMUX_PERMIT[206] & ~reg_be))) |
33315 (addr_hit[207] & (|(PINMUX_PERMIT[207] & ~reg_be))) |
33316 (addr_hit[208] & (|(PINMUX_PERMIT[208] & ~reg_be))) |
33317 (addr_hit[209] & (|(PINMUX_PERMIT[209] & ~reg_be))) |
33318 (addr_hit[210] & (|(PINMUX_PERMIT[210] & ~reg_be))) |
33319 (addr_hit[211] & (|(PINMUX_PERMIT[211] & ~reg_be))) |
33320 (addr_hit[212] & (|(PINMUX_PERMIT[212] & ~reg_be))) |
33321 (addr_hit[213] & (|(PINMUX_PERMIT[213] & ~reg_be))) |
33322 (addr_hit[214] & (|(PINMUX_PERMIT[214] & ~reg_be))) |
33323 (addr_hit[215] & (|(PINMUX_PERMIT[215] & ~reg_be))) |
33324 (addr_hit[216] & (|(PINMUX_PERMIT[216] & ~reg_be))) |
33325 (addr_hit[217] & (|(PINMUX_PERMIT[217] & ~reg_be))) |
33326 (addr_hit[218] & (|(PINMUX_PERMIT[218] & ~reg_be))) |
33327 (addr_hit[219] & (|(PINMUX_PERMIT[219] & ~reg_be))) |
33328 (addr_hit[220] & (|(PINMUX_PERMIT[220] & ~reg_be))) |
33329 (addr_hit[221] & (|(PINMUX_PERMIT[221] & ~reg_be))) |
33330 (addr_hit[222] & (|(PINMUX_PERMIT[222] & ~reg_be))) |
33331 (addr_hit[223] & (|(PINMUX_PERMIT[223] & ~reg_be))) |
33332 (addr_hit[224] & (|(PINMUX_PERMIT[224] & ~reg_be))) |
33333 (addr_hit[225] & (|(PINMUX_PERMIT[225] & ~reg_be))) |
33334 (addr_hit[226] & (|(PINMUX_PERMIT[226] & ~reg_be))) |
33335 (addr_hit[227] & (|(PINMUX_PERMIT[227] & ~reg_be))) |
33336 (addr_hit[228] & (|(PINMUX_PERMIT[228] & ~reg_be))) |
33337 (addr_hit[229] & (|(PINMUX_PERMIT[229] & ~reg_be))) |
33338 (addr_hit[230] & (|(PINMUX_PERMIT[230] & ~reg_be))) |
33339 (addr_hit[231] & (|(PINMUX_PERMIT[231] & ~reg_be))) |
33340 (addr_hit[232] & (|(PINMUX_PERMIT[232] & ~reg_be))) |
33341 (addr_hit[233] & (|(PINMUX_PERMIT[233] & ~reg_be))) |
33342 (addr_hit[234] & (|(PINMUX_PERMIT[234] & ~reg_be))) |
33343 (addr_hit[235] & (|(PINMUX_PERMIT[235] & ~reg_be))) |
33344 (addr_hit[236] & (|(PINMUX_PERMIT[236] & ~reg_be))) |
33345 (addr_hit[237] & (|(PINMUX_PERMIT[237] & ~reg_be))) |
33346 (addr_hit[238] & (|(PINMUX_PERMIT[238] & ~reg_be))) |
33347 (addr_hit[239] & (|(PINMUX_PERMIT[239] & ~reg_be))) |
33348 (addr_hit[240] & (|(PINMUX_PERMIT[240] & ~reg_be))) |
33349 (addr_hit[241] & (|(PINMUX_PERMIT[241] & ~reg_be))) |
33350 (addr_hit[242] & (|(PINMUX_PERMIT[242] & ~reg_be))) |
33351 (addr_hit[243] & (|(PINMUX_PERMIT[243] & ~reg_be))) |
33352 (addr_hit[244] & (|(PINMUX_PERMIT[244] & ~reg_be))) |
33353 (addr_hit[245] & (|(PINMUX_PERMIT[245] & ~reg_be))) |
33354 (addr_hit[246] & (|(PINMUX_PERMIT[246] & ~reg_be))) |
33355 (addr_hit[247] & (|(PINMUX_PERMIT[247] & ~reg_be))) |
33356 (addr_hit[248] & (|(PINMUX_PERMIT[248] & ~reg_be))) |
33357 (addr_hit[249] & (|(PINMUX_PERMIT[249] & ~reg_be))) |
33358 (addr_hit[250] & (|(PINMUX_PERMIT[250] & ~reg_be))) |
33359 (addr_hit[251] & (|(PINMUX_PERMIT[251] & ~reg_be))) |
33360 (addr_hit[252] & (|(PINMUX_PERMIT[252] & ~reg_be))) |
33361 (addr_hit[253] & (|(PINMUX_PERMIT[253] & ~reg_be))) |
33362 (addr_hit[254] & (|(PINMUX_PERMIT[254] & ~reg_be))) |
33363 (addr_hit[255] & (|(PINMUX_PERMIT[255] & ~reg_be))) |
33364 (addr_hit[256] & (|(PINMUX_PERMIT[256] & ~reg_be))) |
33365 (addr_hit[257] & (|(PINMUX_PERMIT[257] & ~reg_be))) |
33366 (addr_hit[258] & (|(PINMUX_PERMIT[258] & ~reg_be))) |
33367 (addr_hit[259] & (|(PINMUX_PERMIT[259] & ~reg_be))) |
33368 (addr_hit[260] & (|(PINMUX_PERMIT[260] & ~reg_be))) |
33369 (addr_hit[261] & (|(PINMUX_PERMIT[261] & ~reg_be))) |
33370 (addr_hit[262] & (|(PINMUX_PERMIT[262] & ~reg_be))) |
33371 (addr_hit[263] & (|(PINMUX_PERMIT[263] & ~reg_be))) |
33372 (addr_hit[264] & (|(PINMUX_PERMIT[264] & ~reg_be))) |
33373 (addr_hit[265] & (|(PINMUX_PERMIT[265] & ~reg_be))) |
33374 (addr_hit[266] & (|(PINMUX_PERMIT[266] & ~reg_be))) |
33375 (addr_hit[267] & (|(PINMUX_PERMIT[267] & ~reg_be))) |
33376 (addr_hit[268] & (|(PINMUX_PERMIT[268] & ~reg_be))) |
33377 (addr_hit[269] & (|(PINMUX_PERMIT[269] & ~reg_be))) |
33378 (addr_hit[270] & (|(PINMUX_PERMIT[270] & ~reg_be))) |
33379 (addr_hit[271] & (|(PINMUX_PERMIT[271] & ~reg_be))) |
33380 (addr_hit[272] & (|(PINMUX_PERMIT[272] & ~reg_be))) |
33381 (addr_hit[273] & (|(PINMUX_PERMIT[273] & ~reg_be))) |
33382 (addr_hit[274] & (|(PINMUX_PERMIT[274] & ~reg_be))) |
33383 (addr_hit[275] & (|(PINMUX_PERMIT[275] & ~reg_be))) |
33384 (addr_hit[276] & (|(PINMUX_PERMIT[276] & ~reg_be))) |
33385 (addr_hit[277] & (|(PINMUX_PERMIT[277] & ~reg_be))) |
33386 (addr_hit[278] & (|(PINMUX_PERMIT[278] & ~reg_be))) |
33387 (addr_hit[279] & (|(PINMUX_PERMIT[279] & ~reg_be))) |
33388 (addr_hit[280] & (|(PINMUX_PERMIT[280] & ~reg_be))) |
33389 (addr_hit[281] & (|(PINMUX_PERMIT[281] & ~reg_be))) |
33390 (addr_hit[282] & (|(PINMUX_PERMIT[282] & ~reg_be))) |
33391 (addr_hit[283] & (|(PINMUX_PERMIT[283] & ~reg_be))) |
33392 (addr_hit[284] & (|(PINMUX_PERMIT[284] & ~reg_be))) |
33393 (addr_hit[285] & (|(PINMUX_PERMIT[285] & ~reg_be))) |
33394 (addr_hit[286] & (|(PINMUX_PERMIT[286] & ~reg_be))) |
33395 (addr_hit[287] & (|(PINMUX_PERMIT[287] & ~reg_be))) |
33396 (addr_hit[288] & (|(PINMUX_PERMIT[288] & ~reg_be))) |
33397 (addr_hit[289] & (|(PINMUX_PERMIT[289] & ~reg_be))) |
33398 (addr_hit[290] & (|(PINMUX_PERMIT[290] & ~reg_be))) |
33399 (addr_hit[291] & (|(PINMUX_PERMIT[291] & ~reg_be))) |
33400 (addr_hit[292] & (|(PINMUX_PERMIT[292] & ~reg_be))) |
33401 (addr_hit[293] & (|(PINMUX_PERMIT[293] & ~reg_be))) |
33402 (addr_hit[294] & (|(PINMUX_PERMIT[294] & ~reg_be))) |
33403 (addr_hit[295] & (|(PINMUX_PERMIT[295] & ~reg_be))) |
33404 (addr_hit[296] & (|(PINMUX_PERMIT[296] & ~reg_be))) |
33405 (addr_hit[297] & (|(PINMUX_PERMIT[297] & ~reg_be))) |
33406 (addr_hit[298] & (|(PINMUX_PERMIT[298] & ~reg_be))) |
33407 (addr_hit[299] & (|(PINMUX_PERMIT[299] & ~reg_be))) |
33408 (addr_hit[300] & (|(PINMUX_PERMIT[300] & ~reg_be))) |
33409 (addr_hit[301] & (|(PINMUX_PERMIT[301] & ~reg_be))) |
33410 (addr_hit[302] & (|(PINMUX_PERMIT[302] & ~reg_be))) |
33411 (addr_hit[303] & (|(PINMUX_PERMIT[303] & ~reg_be))) |
33412 (addr_hit[304] & (|(PINMUX_PERMIT[304] & ~reg_be))) |
33413 (addr_hit[305] & (|(PINMUX_PERMIT[305] & ~reg_be))) |
33414 (addr_hit[306] & (|(PINMUX_PERMIT[306] & ~reg_be))) |
33415 (addr_hit[307] & (|(PINMUX_PERMIT[307] & ~reg_be))) |
33416 (addr_hit[308] & (|(PINMUX_PERMIT[308] & ~reg_be))) |
33417 (addr_hit[309] & (|(PINMUX_PERMIT[309] & ~reg_be))) |
33418 (addr_hit[310] & (|(PINMUX_PERMIT[310] & ~reg_be))) |
33419 (addr_hit[311] & (|(PINMUX_PERMIT[311] & ~reg_be))) |
33420 (addr_hit[312] & (|(PINMUX_PERMIT[312] & ~reg_be))) |
33421 (addr_hit[313] & (|(PINMUX_PERMIT[313] & ~reg_be))) |
33422 (addr_hit[314] & (|(PINMUX_PERMIT[314] & ~reg_be))) |
33423 (addr_hit[315] & (|(PINMUX_PERMIT[315] & ~reg_be))) |
33424 (addr_hit[316] & (|(PINMUX_PERMIT[316] & ~reg_be))) |
33425 (addr_hit[317] & (|(PINMUX_PERMIT[317] & ~reg_be))) |
33426 (addr_hit[318] & (|(PINMUX_PERMIT[318] & ~reg_be))) |
33427 (addr_hit[319] & (|(PINMUX_PERMIT[319] & ~reg_be))) |
33428 (addr_hit[320] & (|(PINMUX_PERMIT[320] & ~reg_be))) |
33429 (addr_hit[321] & (|(PINMUX_PERMIT[321] & ~reg_be))) |
33430 (addr_hit[322] & (|(PINMUX_PERMIT[322] & ~reg_be))) |
33431 (addr_hit[323] & (|(PINMUX_PERMIT[323] & ~reg_be))) |
33432 (addr_hit[324] & (|(PINMUX_PERMIT[324] & ~reg_be))) |
33433 (addr_hit[325] & (|(PINMUX_PERMIT[325] & ~reg_be))) |
33434 (addr_hit[326] & (|(PINMUX_PERMIT[326] & ~reg_be))) |
33435 (addr_hit[327] & (|(PINMUX_PERMIT[327] & ~reg_be))) |
33436 (addr_hit[328] & (|(PINMUX_PERMIT[328] & ~reg_be))) |
33437 (addr_hit[329] & (|(PINMUX_PERMIT[329] & ~reg_be))) |
33438 (addr_hit[330] & (|(PINMUX_PERMIT[330] & ~reg_be))) |
33439 (addr_hit[331] & (|(PINMUX_PERMIT[331] & ~reg_be))) |
33440 (addr_hit[332] & (|(PINMUX_PERMIT[332] & ~reg_be))) |
33441 (addr_hit[333] & (|(PINMUX_PERMIT[333] & ~reg_be))) |
33442 (addr_hit[334] & (|(PINMUX_PERMIT[334] & ~reg_be))) |
33443 (addr_hit[335] & (|(PINMUX_PERMIT[335] & ~reg_be))) |
33444 (addr_hit[336] & (|(PINMUX_PERMIT[336] & ~reg_be))) |
33445 (addr_hit[337] & (|(PINMUX_PERMIT[337] & ~reg_be))) |
33446 (addr_hit[338] & (|(PINMUX_PERMIT[338] & ~reg_be))) |
33447 (addr_hit[339] & (|(PINMUX_PERMIT[339] & ~reg_be))) |
33448 (addr_hit[340] & (|(PINMUX_PERMIT[340] & ~reg_be))) |
33449 (addr_hit[341] & (|(PINMUX_PERMIT[341] & ~reg_be))) |
33450 (addr_hit[342] & (|(PINMUX_PERMIT[342] & ~reg_be))) |
33451 (addr_hit[343] & (|(PINMUX_PERMIT[343] & ~reg_be))) |
33452 (addr_hit[344] & (|(PINMUX_PERMIT[344] & ~reg_be))) |
33453 (addr_hit[345] & (|(PINMUX_PERMIT[345] & ~reg_be))) |
33454 (addr_hit[346] & (|(PINMUX_PERMIT[346] & ~reg_be))) |
33455 (addr_hit[347] & (|(PINMUX_PERMIT[347] & ~reg_be))) |
33456 (addr_hit[348] & (|(PINMUX_PERMIT[348] & ~reg_be))) |
33457 (addr_hit[349] & (|(PINMUX_PERMIT[349] & ~reg_be))) |
33458 (addr_hit[350] & (|(PINMUX_PERMIT[350] & ~reg_be))) |
33459 (addr_hit[351] & (|(PINMUX_PERMIT[351] & ~reg_be))) |
33460 (addr_hit[352] & (|(PINMUX_PERMIT[352] & ~reg_be))) |
33461 (addr_hit[353] & (|(PINMUX_PERMIT[353] & ~reg_be))) |
33462 (addr_hit[354] & (|(PINMUX_PERMIT[354] & ~reg_be))) |
33463 (addr_hit[355] & (|(PINMUX_PERMIT[355] & ~reg_be))) |
33464 (addr_hit[356] & (|(PINMUX_PERMIT[356] & ~reg_be))) |
33465 (addr_hit[357] & (|(PINMUX_PERMIT[357] & ~reg_be))) |
33466 (addr_hit[358] & (|(PINMUX_PERMIT[358] & ~reg_be))) |
33467 (addr_hit[359] & (|(PINMUX_PERMIT[359] & ~reg_be))) |
33468 (addr_hit[360] & (|(PINMUX_PERMIT[360] & ~reg_be))) |
33469 (addr_hit[361] & (|(PINMUX_PERMIT[361] & ~reg_be))) |
33470 (addr_hit[362] & (|(PINMUX_PERMIT[362] & ~reg_be))) |
33471 (addr_hit[363] & (|(PINMUX_PERMIT[363] & ~reg_be))) |
33472 (addr_hit[364] & (|(PINMUX_PERMIT[364] & ~reg_be))) |
33473 (addr_hit[365] & (|(PINMUX_PERMIT[365] & ~reg_be))) |
33474 (addr_hit[366] & (|(PINMUX_PERMIT[366] & ~reg_be))) |
33475 (addr_hit[367] & (|(PINMUX_PERMIT[367] & ~reg_be))) |
33476 (addr_hit[368] & (|(PINMUX_PERMIT[368] & ~reg_be))) |
33477 (addr_hit[369] & (|(PINMUX_PERMIT[369] & ~reg_be))) |
33478 (addr_hit[370] & (|(PINMUX_PERMIT[370] & ~reg_be))) |
33479 (addr_hit[371] & (|(PINMUX_PERMIT[371] & ~reg_be))) |
33480 (addr_hit[372] & (|(PINMUX_PERMIT[372] & ~reg_be))) |
33481 (addr_hit[373] & (|(PINMUX_PERMIT[373] & ~reg_be))) |
33482 (addr_hit[374] & (|(PINMUX_PERMIT[374] & ~reg_be))) |
33483 (addr_hit[375] & (|(PINMUX_PERMIT[375] & ~reg_be))) |
33484 (addr_hit[376] & (|(PINMUX_PERMIT[376] & ~reg_be))) |
33485 (addr_hit[377] & (|(PINMUX_PERMIT[377] & ~reg_be))) |
33486 (addr_hit[378] & (|(PINMUX_PERMIT[378] & ~reg_be))) |
33487 (addr_hit[379] & (|(PINMUX_PERMIT[379] & ~reg_be))) |
33488 (addr_hit[380] & (|(PINMUX_PERMIT[380] & ~reg_be))) |
33489 (addr_hit[381] & (|(PINMUX_PERMIT[381] & ~reg_be))) |
33490 (addr_hit[382] & (|(PINMUX_PERMIT[382] & ~reg_be))) |
33491 (addr_hit[383] & (|(PINMUX_PERMIT[383] & ~reg_be))) |
33492 (addr_hit[384] & (|(PINMUX_PERMIT[384] & ~reg_be))) |
33493 (addr_hit[385] & (|(PINMUX_PERMIT[385] & ~reg_be))) |
33494 (addr_hit[386] & (|(PINMUX_PERMIT[386] & ~reg_be))) |
33495 (addr_hit[387] & (|(PINMUX_PERMIT[387] & ~reg_be))) |
33496 (addr_hit[388] & (|(PINMUX_PERMIT[388] & ~reg_be))) |
33497 (addr_hit[389] & (|(PINMUX_PERMIT[389] & ~reg_be))) |
33498 (addr_hit[390] & (|(PINMUX_PERMIT[390] & ~reg_be))) |
33499 (addr_hit[391] & (|(PINMUX_PERMIT[391] & ~reg_be))) |
33500 (addr_hit[392] & (|(PINMUX_PERMIT[392] & ~reg_be))) |
33501 (addr_hit[393] & (|(PINMUX_PERMIT[393] & ~reg_be))) |
33502 (addr_hit[394] & (|(PINMUX_PERMIT[394] & ~reg_be))) |
33503 (addr_hit[395] & (|(PINMUX_PERMIT[395] & ~reg_be))) |
33504 (addr_hit[396] & (|(PINMUX_PERMIT[396] & ~reg_be))) |
33505 (addr_hit[397] & (|(PINMUX_PERMIT[397] & ~reg_be))) |
33506 (addr_hit[398] & (|(PINMUX_PERMIT[398] & ~reg_be))) |
33507 (addr_hit[399] & (|(PINMUX_PERMIT[399] & ~reg_be))) |
33508 (addr_hit[400] & (|(PINMUX_PERMIT[400] & ~reg_be))) |
33509 (addr_hit[401] & (|(PINMUX_PERMIT[401] & ~reg_be))) |
33510 (addr_hit[402] & (|(PINMUX_PERMIT[402] & ~reg_be))) |
33511 (addr_hit[403] & (|(PINMUX_PERMIT[403] & ~reg_be))) |
33512 (addr_hit[404] & (|(PINMUX_PERMIT[404] & ~reg_be))) |
33513 (addr_hit[405] & (|(PINMUX_PERMIT[405] & ~reg_be))) |
33514 (addr_hit[406] & (|(PINMUX_PERMIT[406] & ~reg_be))) |
33515 (addr_hit[407] & (|(PINMUX_PERMIT[407] & ~reg_be))) |
33516 (addr_hit[408] & (|(PINMUX_PERMIT[408] & ~reg_be))) |
33517 (addr_hit[409] & (|(PINMUX_PERMIT[409] & ~reg_be))) |
33518 (addr_hit[410] & (|(PINMUX_PERMIT[410] & ~reg_be))) |
33519 (addr_hit[411] & (|(PINMUX_PERMIT[411] & ~reg_be))) |
33520 (addr_hit[412] & (|(PINMUX_PERMIT[412] & ~reg_be))) |
33521 (addr_hit[413] & (|(PINMUX_PERMIT[413] & ~reg_be))) |
33522 (addr_hit[414] & (|(PINMUX_PERMIT[414] & ~reg_be))) |
33523 (addr_hit[415] & (|(PINMUX_PERMIT[415] & ~reg_be))) |
33524 (addr_hit[416] & (|(PINMUX_PERMIT[416] & ~reg_be))) |
33525 (addr_hit[417] & (|(PINMUX_PERMIT[417] & ~reg_be))) |
33526 (addr_hit[418] & (|(PINMUX_PERMIT[418] & ~reg_be))) |
33527 (addr_hit[419] & (|(PINMUX_PERMIT[419] & ~reg_be))) |
33528 (addr_hit[420] & (|(PINMUX_PERMIT[420] & ~reg_be))) |
33529 (addr_hit[421] & (|(PINMUX_PERMIT[421] & ~reg_be))) |
33530 (addr_hit[422] & (|(PINMUX_PERMIT[422] & ~reg_be))) |
33531 (addr_hit[423] & (|(PINMUX_PERMIT[423] & ~reg_be))) |
33532 (addr_hit[424] & (|(PINMUX_PERMIT[424] & ~reg_be))) |
33533 (addr_hit[425] & (|(PINMUX_PERMIT[425] & ~reg_be))) |
33534 (addr_hit[426] & (|(PINMUX_PERMIT[426] & ~reg_be))) |
33535 (addr_hit[427] & (|(PINMUX_PERMIT[427] & ~reg_be))) |
33536 (addr_hit[428] & (|(PINMUX_PERMIT[428] & ~reg_be))) |
33537 (addr_hit[429] & (|(PINMUX_PERMIT[429] & ~reg_be))) |
33538 (addr_hit[430] & (|(PINMUX_PERMIT[430] & ~reg_be))) |
33539 (addr_hit[431] & (|(PINMUX_PERMIT[431] & ~reg_be))) |
33540 (addr_hit[432] & (|(PINMUX_PERMIT[432] & ~reg_be))) |
33541 (addr_hit[433] & (|(PINMUX_PERMIT[433] & ~reg_be))) |
33542 (addr_hit[434] & (|(PINMUX_PERMIT[434] & ~reg_be))) |
33543 (addr_hit[435] & (|(PINMUX_PERMIT[435] & ~reg_be))) |
33544 (addr_hit[436] & (|(PINMUX_PERMIT[436] & ~reg_be))) |
33545 (addr_hit[437] & (|(PINMUX_PERMIT[437] & ~reg_be))) |
33546 (addr_hit[438] & (|(PINMUX_PERMIT[438] & ~reg_be))) |
33547 (addr_hit[439] & (|(PINMUX_PERMIT[439] & ~reg_be))) |
33548 (addr_hit[440] & (|(PINMUX_PERMIT[440] & ~reg_be))) |
33549 (addr_hit[441] & (|(PINMUX_PERMIT[441] & ~reg_be))) |
33550 (addr_hit[442] & (|(PINMUX_PERMIT[442] & ~reg_be))) |
33551 (addr_hit[443] & (|(PINMUX_PERMIT[443] & ~reg_be))) |
33552 (addr_hit[444] & (|(PINMUX_PERMIT[444] & ~reg_be))) |
33553 (addr_hit[445] & (|(PINMUX_PERMIT[445] & ~reg_be))) |
33554 (addr_hit[446] & (|(PINMUX_PERMIT[446] & ~reg_be))) |
33555 (addr_hit[447] & (|(PINMUX_PERMIT[447] & ~reg_be))) |
33556 (addr_hit[448] & (|(PINMUX_PERMIT[448] & ~reg_be))) |
33557 (addr_hit[449] & (|(PINMUX_PERMIT[449] & ~reg_be))) |
33558 (addr_hit[450] & (|(PINMUX_PERMIT[450] & ~reg_be))) |
33559 (addr_hit[451] & (|(PINMUX_PERMIT[451] & ~reg_be))) |
33560 (addr_hit[452] & (|(PINMUX_PERMIT[452] & ~reg_be))) |
33561 (addr_hit[453] & (|(PINMUX_PERMIT[453] & ~reg_be))) |
33562 (addr_hit[454] & (|(PINMUX_PERMIT[454] & ~reg_be))) |
33563 (addr_hit[455] & (|(PINMUX_PERMIT[455] & ~reg_be))) |
33564 (addr_hit[456] & (|(PINMUX_PERMIT[456] & ~reg_be))) |
33565 (addr_hit[457] & (|(PINMUX_PERMIT[457] & ~reg_be))) |
33566 (addr_hit[458] & (|(PINMUX_PERMIT[458] & ~reg_be))) |
33567 (addr_hit[459] & (|(PINMUX_PERMIT[459] & ~reg_be))) |
33568 (addr_hit[460] & (|(PINMUX_PERMIT[460] & ~reg_be))) |
33569 (addr_hit[461] & (|(PINMUX_PERMIT[461] & ~reg_be))) |
33570 (addr_hit[462] & (|(PINMUX_PERMIT[462] & ~reg_be))) |
33571 (addr_hit[463] & (|(PINMUX_PERMIT[463] & ~reg_be))) |
33572 (addr_hit[464] & (|(PINMUX_PERMIT[464] & ~reg_be))) |
33573 (addr_hit[465] & (|(PINMUX_PERMIT[465] & ~reg_be))) |
33574 (addr_hit[466] & (|(PINMUX_PERMIT[466] & ~reg_be))) |
33575 (addr_hit[467] & (|(PINMUX_PERMIT[467] & ~reg_be))) |
33576 (addr_hit[468] & (|(PINMUX_PERMIT[468] & ~reg_be))) |
33577 (addr_hit[469] & (|(PINMUX_PERMIT[469] & ~reg_be))) |
33578 (addr_hit[470] & (|(PINMUX_PERMIT[470] & ~reg_be))) |
33579 (addr_hit[471] & (|(PINMUX_PERMIT[471] & ~reg_be))) |
33580 (addr_hit[472] & (|(PINMUX_PERMIT[472] & ~reg_be))) |
33581 (addr_hit[473] & (|(PINMUX_PERMIT[473] & ~reg_be))) |
33582 (addr_hit[474] & (|(PINMUX_PERMIT[474] & ~reg_be))) |
33583 (addr_hit[475] & (|(PINMUX_PERMIT[475] & ~reg_be))) |
33584 (addr_hit[476] & (|(PINMUX_PERMIT[476] & ~reg_be))) |
33585 (addr_hit[477] & (|(PINMUX_PERMIT[477] & ~reg_be))) |
33586 (addr_hit[478] & (|(PINMUX_PERMIT[478] & ~reg_be))) |
33587 (addr_hit[479] & (|(PINMUX_PERMIT[479] & ~reg_be))) |
33588 (addr_hit[480] & (|(PINMUX_PERMIT[480] & ~reg_be))) |
33589 (addr_hit[481] & (|(PINMUX_PERMIT[481] & ~reg_be))) |
33590 (addr_hit[482] & (|(PINMUX_PERMIT[482] & ~reg_be))) |
33591 (addr_hit[483] & (|(PINMUX_PERMIT[483] & ~reg_be))) |
33592 (addr_hit[484] & (|(PINMUX_PERMIT[484] & ~reg_be))) |
33593 (addr_hit[485] & (|(PINMUX_PERMIT[485] & ~reg_be))) |
33594 (addr_hit[486] & (|(PINMUX_PERMIT[486] & ~reg_be))) |
33595 (addr_hit[487] & (|(PINMUX_PERMIT[487] & ~reg_be))) |
33596 (addr_hit[488] & (|(PINMUX_PERMIT[488] & ~reg_be))) |
33597 (addr_hit[489] & (|(PINMUX_PERMIT[489] & ~reg_be))) |
33598 (addr_hit[490] & (|(PINMUX_PERMIT[490] & ~reg_be))) |
33599 (addr_hit[491] & (|(PINMUX_PERMIT[491] & ~reg_be))) |
33600 (addr_hit[492] & (|(PINMUX_PERMIT[492] & ~reg_be))) |
33601 (addr_hit[493] & (|(PINMUX_PERMIT[493] & ~reg_be))) |
33602 (addr_hit[494] & (|(PINMUX_PERMIT[494] & ~reg_be))) |
33603 (addr_hit[495] & (|(PINMUX_PERMIT[495] & ~reg_be))) |
33604 (addr_hit[496] & (|(PINMUX_PERMIT[496] & ~reg_be))) |
33605 (addr_hit[497] & (|(PINMUX_PERMIT[497] & ~reg_be))) |
33606 (addr_hit[498] & (|(PINMUX_PERMIT[498] & ~reg_be))) |
33607 (addr_hit[499] & (|(PINMUX_PERMIT[499] & ~reg_be))) |
33608 (addr_hit[500] & (|(PINMUX_PERMIT[500] & ~reg_be))) |
33609 (addr_hit[501] & (|(PINMUX_PERMIT[501] & ~reg_be))) |
33610 (addr_hit[502] & (|(PINMUX_PERMIT[502] & ~reg_be))) |
33611 (addr_hit[503] & (|(PINMUX_PERMIT[503] & ~reg_be))) |
33612 (addr_hit[504] & (|(PINMUX_PERMIT[504] & ~reg_be))) |
33613 (addr_hit[505] & (|(PINMUX_PERMIT[505] & ~reg_be))) |
33614 (addr_hit[506] & (|(PINMUX_PERMIT[506] & ~reg_be))) |
33615 (addr_hit[507] & (|(PINMUX_PERMIT[507] & ~reg_be))) |
33616 (addr_hit[508] & (|(PINMUX_PERMIT[508] & ~reg_be))) |
33617 (addr_hit[509] & (|(PINMUX_PERMIT[509] & ~reg_be))) |
33618 (addr_hit[510] & (|(PINMUX_PERMIT[510] & ~reg_be))) |
33619 (addr_hit[511] & (|(PINMUX_PERMIT[511] & ~reg_be))) |
33620 (addr_hit[512] & (|(PINMUX_PERMIT[512] & ~reg_be))) |
33621 (addr_hit[513] & (|(PINMUX_PERMIT[513] & ~reg_be))) |
33622 (addr_hit[514] & (|(PINMUX_PERMIT[514] & ~reg_be))) |
33623 (addr_hit[515] & (|(PINMUX_PERMIT[515] & ~reg_be))) |
33624 (addr_hit[516] & (|(PINMUX_PERMIT[516] & ~reg_be))) |
33625 (addr_hit[517] & (|(PINMUX_PERMIT[517] & ~reg_be))) |
33626 (addr_hit[518] & (|(PINMUX_PERMIT[518] & ~reg_be))) |
33627 (addr_hit[519] & (|(PINMUX_PERMIT[519] & ~reg_be))) |
33628 (addr_hit[520] & (|(PINMUX_PERMIT[520] & ~reg_be))) |
33629 (addr_hit[521] & (|(PINMUX_PERMIT[521] & ~reg_be))) |
33630 (addr_hit[522] & (|(PINMUX_PERMIT[522] & ~reg_be))) |
33631 (addr_hit[523] & (|(PINMUX_PERMIT[523] & ~reg_be))) |
33632 (addr_hit[524] & (|(PINMUX_PERMIT[524] & ~reg_be))) |
33633 (addr_hit[525] & (|(PINMUX_PERMIT[525] & ~reg_be))) |
33634 (addr_hit[526] & (|(PINMUX_PERMIT[526] & ~reg_be))) |
33635 (addr_hit[527] & (|(PINMUX_PERMIT[527] & ~reg_be))) |
33636 (addr_hit[528] & (|(PINMUX_PERMIT[528] & ~reg_be))) |
33637 (addr_hit[529] & (|(PINMUX_PERMIT[529] & ~reg_be))) |
33638 (addr_hit[530] & (|(PINMUX_PERMIT[530] & ~reg_be))) |
33639 (addr_hit[531] & (|(PINMUX_PERMIT[531] & ~reg_be))) |
33640 (addr_hit[532] & (|(PINMUX_PERMIT[532] & ~reg_be))) |
33641 (addr_hit[533] & (|(PINMUX_PERMIT[533] & ~reg_be))) |
33642 (addr_hit[534] & (|(PINMUX_PERMIT[534] & ~reg_be))) |
33643 (addr_hit[535] & (|(PINMUX_PERMIT[535] & ~reg_be))) |
33644 (addr_hit[536] & (|(PINMUX_PERMIT[536] & ~reg_be))) |
33645 (addr_hit[537] & (|(PINMUX_PERMIT[537] & ~reg_be))) |
33646 (addr_hit[538] & (|(PINMUX_PERMIT[538] & ~reg_be))) |
33647 (addr_hit[539] & (|(PINMUX_PERMIT[539] & ~reg_be))) |
33648 (addr_hit[540] & (|(PINMUX_PERMIT[540] & ~reg_be))) |
33649 (addr_hit[541] & (|(PINMUX_PERMIT[541] & ~reg_be))) |
33650 (addr_hit[542] & (|(PINMUX_PERMIT[542] & ~reg_be))) |
33651 (addr_hit[543] & (|(PINMUX_PERMIT[543] & ~reg_be))) |
33652 (addr_hit[544] & (|(PINMUX_PERMIT[544] & ~reg_be))) |
33653 (addr_hit[545] & (|(PINMUX_PERMIT[545] & ~reg_be))) |
33654 (addr_hit[546] & (|(PINMUX_PERMIT[546] & ~reg_be))) |
33655 (addr_hit[547] & (|(PINMUX_PERMIT[547] & ~reg_be))) |
33656 (addr_hit[548] & (|(PINMUX_PERMIT[548] & ~reg_be))) |
33657 (addr_hit[549] & (|(PINMUX_PERMIT[549] & ~reg_be))) |
33658 (addr_hit[550] & (|(PINMUX_PERMIT[550] & ~reg_be))) |
33659 (addr_hit[551] & (|(PINMUX_PERMIT[551] & ~reg_be))) |
33660 (addr_hit[552] & (|(PINMUX_PERMIT[552] & ~reg_be))) |
33661 (addr_hit[553] & (|(PINMUX_PERMIT[553] & ~reg_be))) |
33662 (addr_hit[554] & (|(PINMUX_PERMIT[554] & ~reg_be))) |
33663 (addr_hit[555] & (|(PINMUX_PERMIT[555] & ~reg_be))) |
33664 (addr_hit[556] & (|(PINMUX_PERMIT[556] & ~reg_be))) |
33665 (addr_hit[557] & (|(PINMUX_PERMIT[557] & ~reg_be))) |
33666 (addr_hit[558] & (|(PINMUX_PERMIT[558] & ~reg_be))) |
33667 (addr_hit[559] & (|(PINMUX_PERMIT[559] & ~reg_be))) |
33668 (addr_hit[560] & (|(PINMUX_PERMIT[560] & ~reg_be))) |
33669 (addr_hit[561] & (|(PINMUX_PERMIT[561] & ~reg_be))) |
33670 (addr_hit[562] & (|(PINMUX_PERMIT[562] & ~reg_be))) |
33671 (addr_hit[563] & (|(PINMUX_PERMIT[563] & ~reg_be))) |
33672 (addr_hit[564] & (|(PINMUX_PERMIT[564] & ~reg_be))) |
33673 (addr_hit[565] & (|(PINMUX_PERMIT[565] & ~reg_be))) |
33674 (addr_hit[566] & (|(PINMUX_PERMIT[566] & ~reg_be))) |
33675 (addr_hit[567] & (|(PINMUX_PERMIT[567] & ~reg_be)))));
33676 end
33677
33678 // Generate write-enables
33679 1/1 assign alert_test_we = addr_hit[0] & reg_we & !reg_error;
Tests: T1 T2 T3
33680
33681 1/1 assign alert_test_wd = reg_wdata[0];
Tests: T1 T2 T3
33682 1/1 assign mio_periph_insel_regwen_0_we = addr_hit[1] & reg_we & !reg_error;
Tests: T1 T2 T3
33683
33684 1/1 assign mio_periph_insel_regwen_0_wd = reg_wdata[0];
Tests: T1 T2 T3
33685 1/1 assign mio_periph_insel_regwen_1_we = addr_hit[2] & reg_we & !reg_error;
Tests: T1 T2 T3
33686
33687 1/1 assign mio_periph_insel_regwen_1_wd = reg_wdata[0];
Tests: T1 T2 T3
33688 1/1 assign mio_periph_insel_regwen_2_we = addr_hit[3] & reg_we & !reg_error;
Tests: T1 T2 T3
33689
33690 1/1 assign mio_periph_insel_regwen_2_wd = reg_wdata[0];
Tests: T1 T2 T3
33691 1/1 assign mio_periph_insel_regwen_3_we = addr_hit[4] & reg_we & !reg_error;
Tests: T1 T2 T3
33692
33693 1/1 assign mio_periph_insel_regwen_3_wd = reg_wdata[0];
Tests: T1 T2 T3
33694 1/1 assign mio_periph_insel_regwen_4_we = addr_hit[5] & reg_we & !reg_error;
Tests: T1 T2 T3
33695
33696 1/1 assign mio_periph_insel_regwen_4_wd = reg_wdata[0];
Tests: T1 T2 T3
33697 1/1 assign mio_periph_insel_regwen_5_we = addr_hit[6] & reg_we & !reg_error;
Tests: T1 T2 T3
33698
33699 1/1 assign mio_periph_insel_regwen_5_wd = reg_wdata[0];
Tests: T1 T2 T3
33700 1/1 assign mio_periph_insel_regwen_6_we = addr_hit[7] & reg_we & !reg_error;
Tests: T1 T2 T3
33701
33702 1/1 assign mio_periph_insel_regwen_6_wd = reg_wdata[0];
Tests: T1 T2 T3
33703 1/1 assign mio_periph_insel_regwen_7_we = addr_hit[8] & reg_we & !reg_error;
Tests: T1 T2 T3
33704
33705 1/1 assign mio_periph_insel_regwen_7_wd = reg_wdata[0];
Tests: T1 T2 T3
33706 1/1 assign mio_periph_insel_regwen_8_we = addr_hit[9] & reg_we & !reg_error;
Tests: T1 T2 T3
33707
33708 1/1 assign mio_periph_insel_regwen_8_wd = reg_wdata[0];
Tests: T1 T2 T3
33709 1/1 assign mio_periph_insel_regwen_9_we = addr_hit[10] & reg_we & !reg_error;
Tests: T1 T2 T3
33710
33711 1/1 assign mio_periph_insel_regwen_9_wd = reg_wdata[0];
Tests: T1 T2 T3
33712 1/1 assign mio_periph_insel_regwen_10_we = addr_hit[11] & reg_we & !reg_error;
Tests: T1 T2 T3
33713
33714 1/1 assign mio_periph_insel_regwen_10_wd = reg_wdata[0];
Tests: T1 T2 T3
33715 1/1 assign mio_periph_insel_regwen_11_we = addr_hit[12] & reg_we & !reg_error;
Tests: T1 T2 T3
33716
33717 1/1 assign mio_periph_insel_regwen_11_wd = reg_wdata[0];
Tests: T1 T2 T3
33718 1/1 assign mio_periph_insel_regwen_12_we = addr_hit[13] & reg_we & !reg_error;
Tests: T1 T2 T3
33719
33720 1/1 assign mio_periph_insel_regwen_12_wd = reg_wdata[0];
Tests: T1 T2 T3
33721 1/1 assign mio_periph_insel_regwen_13_we = addr_hit[14] & reg_we & !reg_error;
Tests: T1 T2 T3
33722
33723 1/1 assign mio_periph_insel_regwen_13_wd = reg_wdata[0];
Tests: T1 T2 T3
33724 1/1 assign mio_periph_insel_regwen_14_we = addr_hit[15] & reg_we & !reg_error;
Tests: T1 T2 T3
33725
33726 1/1 assign mio_periph_insel_regwen_14_wd = reg_wdata[0];
Tests: T1 T2 T3
33727 1/1 assign mio_periph_insel_regwen_15_we = addr_hit[16] & reg_we & !reg_error;
Tests: T1 T2 T3
33728
33729 1/1 assign mio_periph_insel_regwen_15_wd = reg_wdata[0];
Tests: T1 T2 T3
33730 1/1 assign mio_periph_insel_regwen_16_we = addr_hit[17] & reg_we & !reg_error;
Tests: T1 T2 T3
33731
33732 1/1 assign mio_periph_insel_regwen_16_wd = reg_wdata[0];
Tests: T1 T2 T3
33733 1/1 assign mio_periph_insel_regwen_17_we = addr_hit[18] & reg_we & !reg_error;
Tests: T1 T2 T3
33734
33735 1/1 assign mio_periph_insel_regwen_17_wd = reg_wdata[0];
Tests: T1 T2 T3
33736 1/1 assign mio_periph_insel_regwen_18_we = addr_hit[19] & reg_we & !reg_error;
Tests: T1 T2 T3
33737
33738 1/1 assign mio_periph_insel_regwen_18_wd = reg_wdata[0];
Tests: T1 T2 T3
33739 1/1 assign mio_periph_insel_regwen_19_we = addr_hit[20] & reg_we & !reg_error;
Tests: T1 T2 T3
33740
33741 1/1 assign mio_periph_insel_regwen_19_wd = reg_wdata[0];
Tests: T1 T2 T3
33742 1/1 assign mio_periph_insel_regwen_20_we = addr_hit[21] & reg_we & !reg_error;
Tests: T1 T2 T3
33743
33744 1/1 assign mio_periph_insel_regwen_20_wd = reg_wdata[0];
Tests: T1 T2 T3
33745 1/1 assign mio_periph_insel_regwen_21_we = addr_hit[22] & reg_we & !reg_error;
Tests: T1 T2 T3
33746
33747 1/1 assign mio_periph_insel_regwen_21_wd = reg_wdata[0];
Tests: T1 T2 T3
33748 1/1 assign mio_periph_insel_regwen_22_we = addr_hit[23] & reg_we & !reg_error;
Tests: T1 T2 T3
33749
33750 1/1 assign mio_periph_insel_regwen_22_wd = reg_wdata[0];
Tests: T1 T2 T3
33751 1/1 assign mio_periph_insel_regwen_23_we = addr_hit[24] & reg_we & !reg_error;
Tests: T1 T2 T3
33752
33753 1/1 assign mio_periph_insel_regwen_23_wd = reg_wdata[0];
Tests: T1 T2 T3
33754 1/1 assign mio_periph_insel_regwen_24_we = addr_hit[25] & reg_we & !reg_error;
Tests: T1 T2 T3
33755
33756 1/1 assign mio_periph_insel_regwen_24_wd = reg_wdata[0];
Tests: T1 T2 T3
33757 1/1 assign mio_periph_insel_regwen_25_we = addr_hit[26] & reg_we & !reg_error;
Tests: T1 T2 T3
33758
33759 1/1 assign mio_periph_insel_regwen_25_wd = reg_wdata[0];
Tests: T1 T2 T3
33760 1/1 assign mio_periph_insel_regwen_26_we = addr_hit[27] & reg_we & !reg_error;
Tests: T1 T2 T3
33761
33762 1/1 assign mio_periph_insel_regwen_26_wd = reg_wdata[0];
Tests: T1 T2 T3
33763 1/1 assign mio_periph_insel_regwen_27_we = addr_hit[28] & reg_we & !reg_error;
Tests: T1 T2 T3
33764
33765 1/1 assign mio_periph_insel_regwen_27_wd = reg_wdata[0];
Tests: T1 T2 T3
33766 1/1 assign mio_periph_insel_regwen_28_we = addr_hit[29] & reg_we & !reg_error;
Tests: T1 T2 T3
33767
33768 1/1 assign mio_periph_insel_regwen_28_wd = reg_wdata[0];
Tests: T1 T2 T3
33769 1/1 assign mio_periph_insel_regwen_29_we = addr_hit[30] & reg_we & !reg_error;
Tests: T1 T2 T3
33770
33771 1/1 assign mio_periph_insel_regwen_29_wd = reg_wdata[0];
Tests: T1 T2 T3
33772 1/1 assign mio_periph_insel_regwen_30_we = addr_hit[31] & reg_we & !reg_error;
Tests: T1 T2 T3
33773
33774 1/1 assign mio_periph_insel_regwen_30_wd = reg_wdata[0];
Tests: T1 T2 T3
33775 1/1 assign mio_periph_insel_regwen_31_we = addr_hit[32] & reg_we & !reg_error;
Tests: T1 T2 T3
33776
33777 1/1 assign mio_periph_insel_regwen_31_wd = reg_wdata[0];
Tests: T1 T2 T3
33778 1/1 assign mio_periph_insel_regwen_32_we = addr_hit[33] & reg_we & !reg_error;
Tests: T1 T2 T3
33779
33780 1/1 assign mio_periph_insel_regwen_32_wd = reg_wdata[0];
Tests: T1 T2 T3
33781 1/1 assign mio_periph_insel_regwen_33_we = addr_hit[34] & reg_we & !reg_error;
Tests: T1 T2 T3
33782
33783 1/1 assign mio_periph_insel_regwen_33_wd = reg_wdata[0];
Tests: T1 T2 T3
33784 1/1 assign mio_periph_insel_regwen_34_we = addr_hit[35] & reg_we & !reg_error;
Tests: T1 T2 T3
33785
33786 1/1 assign mio_periph_insel_regwen_34_wd = reg_wdata[0];
Tests: T1 T2 T3
33787 1/1 assign mio_periph_insel_regwen_35_we = addr_hit[36] & reg_we & !reg_error;
Tests: T1 T2 T3
33788
33789 1/1 assign mio_periph_insel_regwen_35_wd = reg_wdata[0];
Tests: T1 T2 T3
33790 1/1 assign mio_periph_insel_regwen_36_we = addr_hit[37] & reg_we & !reg_error;
Tests: T1 T2 T3
33791
33792 1/1 assign mio_periph_insel_regwen_36_wd = reg_wdata[0];
Tests: T1 T2 T3
33793 1/1 assign mio_periph_insel_regwen_37_we = addr_hit[38] & reg_we & !reg_error;
Tests: T1 T2 T3
33794
33795 1/1 assign mio_periph_insel_regwen_37_wd = reg_wdata[0];
Tests: T1 T2 T3
33796 1/1 assign mio_periph_insel_regwen_38_we = addr_hit[39] & reg_we & !reg_error;
Tests: T1 T2 T3
33797
33798 1/1 assign mio_periph_insel_regwen_38_wd = reg_wdata[0];
Tests: T1 T2 T3
33799 1/1 assign mio_periph_insel_regwen_39_we = addr_hit[40] & reg_we & !reg_error;
Tests: T1 T2 T3
33800
33801 1/1 assign mio_periph_insel_regwen_39_wd = reg_wdata[0];
Tests: T1 T2 T3
33802 1/1 assign mio_periph_insel_regwen_40_we = addr_hit[41] & reg_we & !reg_error;
Tests: T1 T2 T3
33803
33804 1/1 assign mio_periph_insel_regwen_40_wd = reg_wdata[0];
Tests: T1 T2 T3
33805 1/1 assign mio_periph_insel_regwen_41_we = addr_hit[42] & reg_we & !reg_error;
Tests: T1 T2 T3
33806
33807 1/1 assign mio_periph_insel_regwen_41_wd = reg_wdata[0];
Tests: T1 T2 T3
33808 1/1 assign mio_periph_insel_regwen_42_we = addr_hit[43] & reg_we & !reg_error;
Tests: T1 T2 T3
33809
33810 1/1 assign mio_periph_insel_regwen_42_wd = reg_wdata[0];
Tests: T1 T2 T3
33811 1/1 assign mio_periph_insel_regwen_43_we = addr_hit[44] & reg_we & !reg_error;
Tests: T1 T2 T3
33812
33813 1/1 assign mio_periph_insel_regwen_43_wd = reg_wdata[0];
Tests: T1 T2 T3
33814 1/1 assign mio_periph_insel_regwen_44_we = addr_hit[45] & reg_we & !reg_error;
Tests: T1 T2 T3
33815
33816 1/1 assign mio_periph_insel_regwen_44_wd = reg_wdata[0];
Tests: T1 T2 T3
33817 1/1 assign mio_periph_insel_regwen_45_we = addr_hit[46] & reg_we & !reg_error;
Tests: T1 T2 T3
33818
33819 1/1 assign mio_periph_insel_regwen_45_wd = reg_wdata[0];
Tests: T1 T2 T3
33820 1/1 assign mio_periph_insel_regwen_46_we = addr_hit[47] & reg_we & !reg_error;
Tests: T1 T2 T3
33821
33822 1/1 assign mio_periph_insel_regwen_46_wd = reg_wdata[0];
Tests: T1 T2 T3
33823 1/1 assign mio_periph_insel_regwen_47_we = addr_hit[48] & reg_we & !reg_error;
Tests: T1 T2 T3
33824
33825 1/1 assign mio_periph_insel_regwen_47_wd = reg_wdata[0];
Tests: T1 T2 T3
33826 1/1 assign mio_periph_insel_regwen_48_we = addr_hit[49] & reg_we & !reg_error;
Tests: T1 T2 T3
33827
33828 1/1 assign mio_periph_insel_regwen_48_wd = reg_wdata[0];
Tests: T1 T2 T3
33829 1/1 assign mio_periph_insel_regwen_49_we = addr_hit[50] & reg_we & !reg_error;
Tests: T1 T2 T3
33830
33831 1/1 assign mio_periph_insel_regwen_49_wd = reg_wdata[0];
Tests: T1 T2 T3
33832 1/1 assign mio_periph_insel_regwen_50_we = addr_hit[51] & reg_we & !reg_error;
Tests: T1 T2 T3
33833
33834 1/1 assign mio_periph_insel_regwen_50_wd = reg_wdata[0];
Tests: T1 T2 T3
33835 1/1 assign mio_periph_insel_regwen_51_we = addr_hit[52] & reg_we & !reg_error;
Tests: T1 T2 T3
33836
33837 1/1 assign mio_periph_insel_regwen_51_wd = reg_wdata[0];
Tests: T1 T2 T3
33838 1/1 assign mio_periph_insel_regwen_52_we = addr_hit[53] & reg_we & !reg_error;
Tests: T1 T2 T3
33839
33840 1/1 assign mio_periph_insel_regwen_52_wd = reg_wdata[0];
Tests: T1 T2 T3
33841 1/1 assign mio_periph_insel_regwen_53_we = addr_hit[54] & reg_we & !reg_error;
Tests: T1 T2 T3
33842
33843 1/1 assign mio_periph_insel_regwen_53_wd = reg_wdata[0];
Tests: T1 T2 T3
33844 1/1 assign mio_periph_insel_regwen_54_we = addr_hit[55] & reg_we & !reg_error;
Tests: T1 T2 T3
33845
33846 1/1 assign mio_periph_insel_regwen_54_wd = reg_wdata[0];
Tests: T1 T2 T3
33847 1/1 assign mio_periph_insel_regwen_55_we = addr_hit[56] & reg_we & !reg_error;
Tests: T1 T2 T3
33848
33849 1/1 assign mio_periph_insel_regwen_55_wd = reg_wdata[0];
Tests: T1 T2 T3
33850 1/1 assign mio_periph_insel_regwen_56_we = addr_hit[57] & reg_we & !reg_error;
Tests: T1 T2 T3
33851
33852 1/1 assign mio_periph_insel_regwen_56_wd = reg_wdata[0];
Tests: T1 T2 T3
33853 1/1 assign mio_periph_insel_0_we = addr_hit[58] & reg_we & !reg_error;
Tests: T1 T2 T3
33854
33855 1/1 assign mio_periph_insel_0_wd = reg_wdata[5:0];
Tests: T1 T2 T3
33856 1/1 assign mio_periph_insel_1_we = addr_hit[59] & reg_we & !reg_error;
Tests: T1 T2 T3
33857
33858 1/1 assign mio_periph_insel_1_wd = reg_wdata[5:0];
Tests: T1 T2 T3
33859 1/1 assign mio_periph_insel_2_we = addr_hit[60] & reg_we & !reg_error;
Tests: T1 T2 T3
33860
33861 1/1 assign mio_periph_insel_2_wd = reg_wdata[5:0];
Tests: T1 T2 T3
33862 1/1 assign mio_periph_insel_3_we = addr_hit[61] & reg_we & !reg_error;
Tests: T1 T2 T3
33863
33864 1/1 assign mio_periph_insel_3_wd = reg_wdata[5:0];
Tests: T1 T2 T3
33865 1/1 assign mio_periph_insel_4_we = addr_hit[62] & reg_we & !reg_error;
Tests: T1 T2 T3
33866
33867 1/1 assign mio_periph_insel_4_wd = reg_wdata[5:0];
Tests: T1 T2 T3
33868 1/1 assign mio_periph_insel_5_we = addr_hit[63] & reg_we & !reg_error;
Tests: T1 T2 T3
33869
33870 1/1 assign mio_periph_insel_5_wd = reg_wdata[5:0];
Tests: T1 T2 T3
33871 1/1 assign mio_periph_insel_6_we = addr_hit[64] & reg_we & !reg_error;
Tests: T1 T2 T3
33872
33873 1/1 assign mio_periph_insel_6_wd = reg_wdata[5:0];
Tests: T1 T2 T3
33874 1/1 assign mio_periph_insel_7_we = addr_hit[65] & reg_we & !reg_error;
Tests: T1 T2 T3
33875
33876 1/1 assign mio_periph_insel_7_wd = reg_wdata[5:0];
Tests: T1 T2 T3
33877 1/1 assign mio_periph_insel_8_we = addr_hit[66] & reg_we & !reg_error;
Tests: T1 T2 T3
33878
33879 1/1 assign mio_periph_insel_8_wd = reg_wdata[5:0];
Tests: T1 T2 T3
33880 1/1 assign mio_periph_insel_9_we = addr_hit[67] & reg_we & !reg_error;
Tests: T1 T2 T3
33881
33882 1/1 assign mio_periph_insel_9_wd = reg_wdata[5:0];
Tests: T1 T2 T3
33883 1/1 assign mio_periph_insel_10_we = addr_hit[68] & reg_we & !reg_error;
Tests: T1 T2 T3
33884
33885 1/1 assign mio_periph_insel_10_wd = reg_wdata[5:0];
Tests: T1 T2 T3
33886 1/1 assign mio_periph_insel_11_we = addr_hit[69] & reg_we & !reg_error;
Tests: T1 T2 T3
33887
33888 1/1 assign mio_periph_insel_11_wd = reg_wdata[5:0];
Tests: T1 T2 T3
33889 1/1 assign mio_periph_insel_12_we = addr_hit[70] & reg_we & !reg_error;
Tests: T1 T2 T3
33890
33891 1/1 assign mio_periph_insel_12_wd = reg_wdata[5:0];
Tests: T1 T2 T3
33892 1/1 assign mio_periph_insel_13_we = addr_hit[71] & reg_we & !reg_error;
Tests: T1 T2 T3
33893
33894 1/1 assign mio_periph_insel_13_wd = reg_wdata[5:0];
Tests: T1 T2 T3
33895 1/1 assign mio_periph_insel_14_we = addr_hit[72] & reg_we & !reg_error;
Tests: T1 T2 T3
33896
33897 1/1 assign mio_periph_insel_14_wd = reg_wdata[5:0];
Tests: T1 T2 T3
33898 1/1 assign mio_periph_insel_15_we = addr_hit[73] & reg_we & !reg_error;
Tests: T1 T2 T3
33899
33900 1/1 assign mio_periph_insel_15_wd = reg_wdata[5:0];
Tests: T1 T2 T3
33901 1/1 assign mio_periph_insel_16_we = addr_hit[74] & reg_we & !reg_error;
Tests: T1 T2 T3
33902
33903 1/1 assign mio_periph_insel_16_wd = reg_wdata[5:0];
Tests: T1 T2 T3
33904 1/1 assign mio_periph_insel_17_we = addr_hit[75] & reg_we & !reg_error;
Tests: T1 T2 T3
33905
33906 1/1 assign mio_periph_insel_17_wd = reg_wdata[5:0];
Tests: T1 T2 T3
33907 1/1 assign mio_periph_insel_18_we = addr_hit[76] & reg_we & !reg_error;
Tests: T1 T2 T3
33908
33909 1/1 assign mio_periph_insel_18_wd = reg_wdata[5:0];
Tests: T1 T2 T3
33910 1/1 assign mio_periph_insel_19_we = addr_hit[77] & reg_we & !reg_error;
Tests: T1 T2 T3
33911
33912 1/1 assign mio_periph_insel_19_wd = reg_wdata[5:0];
Tests: T1 T2 T3
33913 1/1 assign mio_periph_insel_20_we = addr_hit[78] & reg_we & !reg_error;
Tests: T1 T2 T3
33914
33915 1/1 assign mio_periph_insel_20_wd = reg_wdata[5:0];
Tests: T1 T2 T3
33916 1/1 assign mio_periph_insel_21_we = addr_hit[79] & reg_we & !reg_error;
Tests: T1 T2 T3
33917
33918 1/1 assign mio_periph_insel_21_wd = reg_wdata[5:0];
Tests: T1 T2 T3
33919 1/1 assign mio_periph_insel_22_we = addr_hit[80] & reg_we & !reg_error;
Tests: T1 T2 T3
33920
33921 1/1 assign mio_periph_insel_22_wd = reg_wdata[5:0];
Tests: T1 T2 T3
33922 1/1 assign mio_periph_insel_23_we = addr_hit[81] & reg_we & !reg_error;
Tests: T1 T2 T3
33923
33924 1/1 assign mio_periph_insel_23_wd = reg_wdata[5:0];
Tests: T1 T2 T3
33925 1/1 assign mio_periph_insel_24_we = addr_hit[82] & reg_we & !reg_error;
Tests: T1 T2 T3
33926
33927 1/1 assign mio_periph_insel_24_wd = reg_wdata[5:0];
Tests: T1 T2 T3
33928 1/1 assign mio_periph_insel_25_we = addr_hit[83] & reg_we & !reg_error;
Tests: T1 T2 T3
33929
33930 1/1 assign mio_periph_insel_25_wd = reg_wdata[5:0];
Tests: T1 T2 T3
33931 1/1 assign mio_periph_insel_26_we = addr_hit[84] & reg_we & !reg_error;
Tests: T1 T2 T3
33932
33933 1/1 assign mio_periph_insel_26_wd = reg_wdata[5:0];
Tests: T1 T2 T3
33934 1/1 assign mio_periph_insel_27_we = addr_hit[85] & reg_we & !reg_error;
Tests: T1 T2 T3
33935
33936 1/1 assign mio_periph_insel_27_wd = reg_wdata[5:0];
Tests: T1 T2 T3
33937 1/1 assign mio_periph_insel_28_we = addr_hit[86] & reg_we & !reg_error;
Tests: T1 T2 T3
33938
33939 1/1 assign mio_periph_insel_28_wd = reg_wdata[5:0];
Tests: T1 T2 T3
33940 1/1 assign mio_periph_insel_29_we = addr_hit[87] & reg_we & !reg_error;
Tests: T1 T2 T3
33941
33942 1/1 assign mio_periph_insel_29_wd = reg_wdata[5:0];
Tests: T1 T2 T3
33943 1/1 assign mio_periph_insel_30_we = addr_hit[88] & reg_we & !reg_error;
Tests: T1 T2 T3
33944
33945 1/1 assign mio_periph_insel_30_wd = reg_wdata[5:0];
Tests: T1 T2 T3
33946 1/1 assign mio_periph_insel_31_we = addr_hit[89] & reg_we & !reg_error;
Tests: T1 T2 T3
33947
33948 1/1 assign mio_periph_insel_31_wd = reg_wdata[5:0];
Tests: T1 T2 T3
33949 1/1 assign mio_periph_insel_32_we = addr_hit[90] & reg_we & !reg_error;
Tests: T1 T2 T3
33950
33951 1/1 assign mio_periph_insel_32_wd = reg_wdata[5:0];
Tests: T1 T2 T3
33952 1/1 assign mio_periph_insel_33_we = addr_hit[91] & reg_we & !reg_error;
Tests: T1 T2 T3
33953
33954 1/1 assign mio_periph_insel_33_wd = reg_wdata[5:0];
Tests: T1 T2 T3
33955 1/1 assign mio_periph_insel_34_we = addr_hit[92] & reg_we & !reg_error;
Tests: T1 T2 T3
33956
33957 1/1 assign mio_periph_insel_34_wd = reg_wdata[5:0];
Tests: T1 T2 T3
33958 1/1 assign mio_periph_insel_35_we = addr_hit[93] & reg_we & !reg_error;
Tests: T1 T2 T3
33959
33960 1/1 assign mio_periph_insel_35_wd = reg_wdata[5:0];
Tests: T1 T2 T3
33961 1/1 assign mio_periph_insel_36_we = addr_hit[94] & reg_we & !reg_error;
Tests: T1 T2 T3
33962
33963 1/1 assign mio_periph_insel_36_wd = reg_wdata[5:0];
Tests: T1 T2 T3
33964 1/1 assign mio_periph_insel_37_we = addr_hit[95] & reg_we & !reg_error;
Tests: T1 T2 T3
33965
33966 1/1 assign mio_periph_insel_37_wd = reg_wdata[5:0];
Tests: T1 T2 T3
33967 1/1 assign mio_periph_insel_38_we = addr_hit[96] & reg_we & !reg_error;
Tests: T1 T2 T3
33968
33969 1/1 assign mio_periph_insel_38_wd = reg_wdata[5:0];
Tests: T1 T2 T3
33970 1/1 assign mio_periph_insel_39_we = addr_hit[97] & reg_we & !reg_error;
Tests: T1 T2 T3
33971
33972 1/1 assign mio_periph_insel_39_wd = reg_wdata[5:0];
Tests: T1 T2 T3
33973 1/1 assign mio_periph_insel_40_we = addr_hit[98] & reg_we & !reg_error;
Tests: T1 T2 T3
33974
33975 1/1 assign mio_periph_insel_40_wd = reg_wdata[5:0];
Tests: T1 T2 T3
33976 1/1 assign mio_periph_insel_41_we = addr_hit[99] & reg_we & !reg_error;
Tests: T1 T2 T3
33977
33978 1/1 assign mio_periph_insel_41_wd = reg_wdata[5:0];
Tests: T1 T2 T3
33979 1/1 assign mio_periph_insel_42_we = addr_hit[100] & reg_we & !reg_error;
Tests: T1 T2 T3
33980
33981 1/1 assign mio_periph_insel_42_wd = reg_wdata[5:0];
Tests: T1 T2 T3
33982 1/1 assign mio_periph_insel_43_we = addr_hit[101] & reg_we & !reg_error;
Tests: T1 T2 T3
33983
33984 1/1 assign mio_periph_insel_43_wd = reg_wdata[5:0];
Tests: T1 T2 T3
33985 1/1 assign mio_periph_insel_44_we = addr_hit[102] & reg_we & !reg_error;
Tests: T1 T2 T3
33986
33987 1/1 assign mio_periph_insel_44_wd = reg_wdata[5:0];
Tests: T1 T2 T3
33988 1/1 assign mio_periph_insel_45_we = addr_hit[103] & reg_we & !reg_error;
Tests: T1 T2 T3
33989
33990 1/1 assign mio_periph_insel_45_wd = reg_wdata[5:0];
Tests: T1 T2 T3
33991 1/1 assign mio_periph_insel_46_we = addr_hit[104] & reg_we & !reg_error;
Tests: T1 T2 T3
33992
33993 1/1 assign mio_periph_insel_46_wd = reg_wdata[5:0];
Tests: T1 T2 T3
33994 1/1 assign mio_periph_insel_47_we = addr_hit[105] & reg_we & !reg_error;
Tests: T1 T2 T3
33995
33996 1/1 assign mio_periph_insel_47_wd = reg_wdata[5:0];
Tests: T1 T2 T3
33997 1/1 assign mio_periph_insel_48_we = addr_hit[106] & reg_we & !reg_error;
Tests: T1 T2 T3
33998
33999 1/1 assign mio_periph_insel_48_wd = reg_wdata[5:0];
Tests: T1 T2 T3
34000 1/1 assign mio_periph_insel_49_we = addr_hit[107] & reg_we & !reg_error;
Tests: T1 T2 T3
34001
34002 1/1 assign mio_periph_insel_49_wd = reg_wdata[5:0];
Tests: T1 T2 T3
34003 1/1 assign mio_periph_insel_50_we = addr_hit[108] & reg_we & !reg_error;
Tests: T1 T2 T3
34004
34005 1/1 assign mio_periph_insel_50_wd = reg_wdata[5:0];
Tests: T1 T2 T3
34006 1/1 assign mio_periph_insel_51_we = addr_hit[109] & reg_we & !reg_error;
Tests: T1 T2 T3
34007
34008 1/1 assign mio_periph_insel_51_wd = reg_wdata[5:0];
Tests: T1 T2 T3
34009 1/1 assign mio_periph_insel_52_we = addr_hit[110] & reg_we & !reg_error;
Tests: T1 T2 T3
34010
34011 1/1 assign mio_periph_insel_52_wd = reg_wdata[5:0];
Tests: T1 T2 T3
34012 1/1 assign mio_periph_insel_53_we = addr_hit[111] & reg_we & !reg_error;
Tests: T1 T2 T3
34013
34014 1/1 assign mio_periph_insel_53_wd = reg_wdata[5:0];
Tests: T1 T2 T3
34015 1/1 assign mio_periph_insel_54_we = addr_hit[112] & reg_we & !reg_error;
Tests: T1 T2 T3
34016
34017 1/1 assign mio_periph_insel_54_wd = reg_wdata[5:0];
Tests: T1 T2 T3
34018 1/1 assign mio_periph_insel_55_we = addr_hit[113] & reg_we & !reg_error;
Tests: T1 T2 T3
34019
34020 1/1 assign mio_periph_insel_55_wd = reg_wdata[5:0];
Tests: T1 T2 T3
34021 1/1 assign mio_periph_insel_56_we = addr_hit[114] & reg_we & !reg_error;
Tests: T1 T2 T3
34022
34023 1/1 assign mio_periph_insel_56_wd = reg_wdata[5:0];
Tests: T1 T2 T3
34024 1/1 assign mio_outsel_regwen_0_we = addr_hit[115] & reg_we & !reg_error;
Tests: T1 T2 T3
34025
34026 1/1 assign mio_outsel_regwen_0_wd = reg_wdata[0];
Tests: T1 T2 T3
34027 1/1 assign mio_outsel_regwen_1_we = addr_hit[116] & reg_we & !reg_error;
Tests: T1 T2 T3
34028
34029 1/1 assign mio_outsel_regwen_1_wd = reg_wdata[0];
Tests: T1 T2 T3
34030 1/1 assign mio_outsel_regwen_2_we = addr_hit[117] & reg_we & !reg_error;
Tests: T1 T2 T3
34031
34032 1/1 assign mio_outsel_regwen_2_wd = reg_wdata[0];
Tests: T1 T2 T3
34033 1/1 assign mio_outsel_regwen_3_we = addr_hit[118] & reg_we & !reg_error;
Tests: T1 T2 T3
34034
34035 1/1 assign mio_outsel_regwen_3_wd = reg_wdata[0];
Tests: T1 T2 T3
34036 1/1 assign mio_outsel_regwen_4_we = addr_hit[119] & reg_we & !reg_error;
Tests: T1 T2 T3
34037
34038 1/1 assign mio_outsel_regwen_4_wd = reg_wdata[0];
Tests: T1 T2 T3
34039 1/1 assign mio_outsel_regwen_5_we = addr_hit[120] & reg_we & !reg_error;
Tests: T1 T2 T3
34040
34041 1/1 assign mio_outsel_regwen_5_wd = reg_wdata[0];
Tests: T1 T2 T3
34042 1/1 assign mio_outsel_regwen_6_we = addr_hit[121] & reg_we & !reg_error;
Tests: T1 T2 T3
34043
34044 1/1 assign mio_outsel_regwen_6_wd = reg_wdata[0];
Tests: T1 T2 T3
34045 1/1 assign mio_outsel_regwen_7_we = addr_hit[122] & reg_we & !reg_error;
Tests: T1 T2 T3
34046
34047 1/1 assign mio_outsel_regwen_7_wd = reg_wdata[0];
Tests: T1 T2 T3
34048 1/1 assign mio_outsel_regwen_8_we = addr_hit[123] & reg_we & !reg_error;
Tests: T1 T2 T3
34049
34050 1/1 assign mio_outsel_regwen_8_wd = reg_wdata[0];
Tests: T1 T2 T3
34051 1/1 assign mio_outsel_regwen_9_we = addr_hit[124] & reg_we & !reg_error;
Tests: T1 T2 T3
34052
34053 1/1 assign mio_outsel_regwen_9_wd = reg_wdata[0];
Tests: T1 T2 T3
34054 1/1 assign mio_outsel_regwen_10_we = addr_hit[125] & reg_we & !reg_error;
Tests: T1 T2 T3
34055
34056 1/1 assign mio_outsel_regwen_10_wd = reg_wdata[0];
Tests: T1 T2 T3
34057 1/1 assign mio_outsel_regwen_11_we = addr_hit[126] & reg_we & !reg_error;
Tests: T1 T2 T3
34058
34059 1/1 assign mio_outsel_regwen_11_wd = reg_wdata[0];
Tests: T1 T2 T3
34060 1/1 assign mio_outsel_regwen_12_we = addr_hit[127] & reg_we & !reg_error;
Tests: T1 T2 T3
34061
34062 1/1 assign mio_outsel_regwen_12_wd = reg_wdata[0];
Tests: T1 T2 T3
34063 1/1 assign mio_outsel_regwen_13_we = addr_hit[128] & reg_we & !reg_error;
Tests: T1 T2 T3
34064
34065 1/1 assign mio_outsel_regwen_13_wd = reg_wdata[0];
Tests: T1 T2 T3
34066 1/1 assign mio_outsel_regwen_14_we = addr_hit[129] & reg_we & !reg_error;
Tests: T1 T2 T3
34067
34068 1/1 assign mio_outsel_regwen_14_wd = reg_wdata[0];
Tests: T1 T2 T3
34069 1/1 assign mio_outsel_regwen_15_we = addr_hit[130] & reg_we & !reg_error;
Tests: T1 T2 T3
34070
34071 1/1 assign mio_outsel_regwen_15_wd = reg_wdata[0];
Tests: T1 T2 T3
34072 1/1 assign mio_outsel_regwen_16_we = addr_hit[131] & reg_we & !reg_error;
Tests: T1 T2 T3
34073
34074 1/1 assign mio_outsel_regwen_16_wd = reg_wdata[0];
Tests: T1 T2 T3
34075 1/1 assign mio_outsel_regwen_17_we = addr_hit[132] & reg_we & !reg_error;
Tests: T1 T2 T3
34076
34077 1/1 assign mio_outsel_regwen_17_wd = reg_wdata[0];
Tests: T1 T2 T3
34078 1/1 assign mio_outsel_regwen_18_we = addr_hit[133] & reg_we & !reg_error;
Tests: T1 T2 T3
34079
34080 1/1 assign mio_outsel_regwen_18_wd = reg_wdata[0];
Tests: T1 T2 T3
34081 1/1 assign mio_outsel_regwen_19_we = addr_hit[134] & reg_we & !reg_error;
Tests: T1 T2 T3
34082
34083 1/1 assign mio_outsel_regwen_19_wd = reg_wdata[0];
Tests: T1 T2 T3
34084 1/1 assign mio_outsel_regwen_20_we = addr_hit[135] & reg_we & !reg_error;
Tests: T1 T2 T3
34085
34086 1/1 assign mio_outsel_regwen_20_wd = reg_wdata[0];
Tests: T1 T2 T3
34087 1/1 assign mio_outsel_regwen_21_we = addr_hit[136] & reg_we & !reg_error;
Tests: T1 T2 T3
34088
34089 1/1 assign mio_outsel_regwen_21_wd = reg_wdata[0];
Tests: T1 T2 T3
34090 1/1 assign mio_outsel_regwen_22_we = addr_hit[137] & reg_we & !reg_error;
Tests: T1 T2 T3
34091
34092 1/1 assign mio_outsel_regwen_22_wd = reg_wdata[0];
Tests: T1 T2 T3
34093 1/1 assign mio_outsel_regwen_23_we = addr_hit[138] & reg_we & !reg_error;
Tests: T1 T2 T3
34094
34095 1/1 assign mio_outsel_regwen_23_wd = reg_wdata[0];
Tests: T1 T2 T3
34096 1/1 assign mio_outsel_regwen_24_we = addr_hit[139] & reg_we & !reg_error;
Tests: T1 T2 T3
34097
34098 1/1 assign mio_outsel_regwen_24_wd = reg_wdata[0];
Tests: T1 T2 T3
34099 1/1 assign mio_outsel_regwen_25_we = addr_hit[140] & reg_we & !reg_error;
Tests: T1 T2 T3
34100
34101 1/1 assign mio_outsel_regwen_25_wd = reg_wdata[0];
Tests: T1 T2 T3
34102 1/1 assign mio_outsel_regwen_26_we = addr_hit[141] & reg_we & !reg_error;
Tests: T1 T2 T3
34103
34104 1/1 assign mio_outsel_regwen_26_wd = reg_wdata[0];
Tests: T1 T2 T3
34105 1/1 assign mio_outsel_regwen_27_we = addr_hit[142] & reg_we & !reg_error;
Tests: T1 T2 T3
34106
34107 1/1 assign mio_outsel_regwen_27_wd = reg_wdata[0];
Tests: T1 T2 T3
34108 1/1 assign mio_outsel_regwen_28_we = addr_hit[143] & reg_we & !reg_error;
Tests: T1 T2 T3
34109
34110 1/1 assign mio_outsel_regwen_28_wd = reg_wdata[0];
Tests: T1 T2 T3
34111 1/1 assign mio_outsel_regwen_29_we = addr_hit[144] & reg_we & !reg_error;
Tests: T1 T2 T3
34112
34113 1/1 assign mio_outsel_regwen_29_wd = reg_wdata[0];
Tests: T1 T2 T3
34114 1/1 assign mio_outsel_regwen_30_we = addr_hit[145] & reg_we & !reg_error;
Tests: T1 T2 T3
34115
34116 1/1 assign mio_outsel_regwen_30_wd = reg_wdata[0];
Tests: T1 T2 T3
34117 1/1 assign mio_outsel_regwen_31_we = addr_hit[146] & reg_we & !reg_error;
Tests: T1 T2 T3
34118
34119 1/1 assign mio_outsel_regwen_31_wd = reg_wdata[0];
Tests: T1 T2 T3
34120 1/1 assign mio_outsel_regwen_32_we = addr_hit[147] & reg_we & !reg_error;
Tests: T1 T2 T3
34121
34122 1/1 assign mio_outsel_regwen_32_wd = reg_wdata[0];
Tests: T1 T2 T3
34123 1/1 assign mio_outsel_regwen_33_we = addr_hit[148] & reg_we & !reg_error;
Tests: T1 T2 T3
34124
34125 1/1 assign mio_outsel_regwen_33_wd = reg_wdata[0];
Tests: T1 T2 T3
34126 1/1 assign mio_outsel_regwen_34_we = addr_hit[149] & reg_we & !reg_error;
Tests: T1 T2 T3
34127
34128 1/1 assign mio_outsel_regwen_34_wd = reg_wdata[0];
Tests: T1 T2 T3
34129 1/1 assign mio_outsel_regwen_35_we = addr_hit[150] & reg_we & !reg_error;
Tests: T1 T2 T3
34130
34131 1/1 assign mio_outsel_regwen_35_wd = reg_wdata[0];
Tests: T1 T2 T3
34132 1/1 assign mio_outsel_regwen_36_we = addr_hit[151] & reg_we & !reg_error;
Tests: T1 T2 T3
34133
34134 1/1 assign mio_outsel_regwen_36_wd = reg_wdata[0];
Tests: T1 T2 T3
34135 1/1 assign mio_outsel_regwen_37_we = addr_hit[152] & reg_we & !reg_error;
Tests: T1 T2 T3
34136
34137 1/1 assign mio_outsel_regwen_37_wd = reg_wdata[0];
Tests: T1 T2 T3
34138 1/1 assign mio_outsel_regwen_38_we = addr_hit[153] & reg_we & !reg_error;
Tests: T1 T2 T3
34139
34140 1/1 assign mio_outsel_regwen_38_wd = reg_wdata[0];
Tests: T1 T2 T3
34141 1/1 assign mio_outsel_regwen_39_we = addr_hit[154] & reg_we & !reg_error;
Tests: T1 T2 T3
34142
34143 1/1 assign mio_outsel_regwen_39_wd = reg_wdata[0];
Tests: T1 T2 T3
34144 1/1 assign mio_outsel_regwen_40_we = addr_hit[155] & reg_we & !reg_error;
Tests: T1 T2 T3
34145
34146 1/1 assign mio_outsel_regwen_40_wd = reg_wdata[0];
Tests: T1 T2 T3
34147 1/1 assign mio_outsel_regwen_41_we = addr_hit[156] & reg_we & !reg_error;
Tests: T1 T2 T3
34148
34149 1/1 assign mio_outsel_regwen_41_wd = reg_wdata[0];
Tests: T1 T2 T3
34150 1/1 assign mio_outsel_regwen_42_we = addr_hit[157] & reg_we & !reg_error;
Tests: T1 T2 T3
34151
34152 1/1 assign mio_outsel_regwen_42_wd = reg_wdata[0];
Tests: T1 T2 T3
34153 1/1 assign mio_outsel_regwen_43_we = addr_hit[158] & reg_we & !reg_error;
Tests: T1 T2 T3
34154
34155 1/1 assign mio_outsel_regwen_43_wd = reg_wdata[0];
Tests: T1 T2 T3
34156 1/1 assign mio_outsel_regwen_44_we = addr_hit[159] & reg_we & !reg_error;
Tests: T1 T2 T3
34157
34158 1/1 assign mio_outsel_regwen_44_wd = reg_wdata[0];
Tests: T1 T2 T3
34159 1/1 assign mio_outsel_regwen_45_we = addr_hit[160] & reg_we & !reg_error;
Tests: T1 T2 T3
34160
34161 1/1 assign mio_outsel_regwen_45_wd = reg_wdata[0];
Tests: T1 T2 T3
34162 1/1 assign mio_outsel_regwen_46_we = addr_hit[161] & reg_we & !reg_error;
Tests: T1 T2 T3
34163
34164 1/1 assign mio_outsel_regwen_46_wd = reg_wdata[0];
Tests: T1 T2 T3
34165 1/1 assign mio_outsel_0_we = addr_hit[162] & reg_we & !reg_error;
Tests: T1 T2 T3
34166
34167 1/1 assign mio_outsel_0_wd = reg_wdata[6:0];
Tests: T1 T2 T3
34168 1/1 assign mio_outsel_1_we = addr_hit[163] & reg_we & !reg_error;
Tests: T1 T2 T3
34169
34170 1/1 assign mio_outsel_1_wd = reg_wdata[6:0];
Tests: T1 T2 T3
34171 1/1 assign mio_outsel_2_we = addr_hit[164] & reg_we & !reg_error;
Tests: T1 T2 T3
34172
34173 1/1 assign mio_outsel_2_wd = reg_wdata[6:0];
Tests: T1 T2 T3
34174 1/1 assign mio_outsel_3_we = addr_hit[165] & reg_we & !reg_error;
Tests: T1 T2 T3
34175
34176 1/1 assign mio_outsel_3_wd = reg_wdata[6:0];
Tests: T1 T2 T3
34177 1/1 assign mio_outsel_4_we = addr_hit[166] & reg_we & !reg_error;
Tests: T1 T2 T3
34178
34179 1/1 assign mio_outsel_4_wd = reg_wdata[6:0];
Tests: T1 T2 T3
34180 1/1 assign mio_outsel_5_we = addr_hit[167] & reg_we & !reg_error;
Tests: T1 T2 T3
34181
34182 1/1 assign mio_outsel_5_wd = reg_wdata[6:0];
Tests: T1 T2 T3
34183 1/1 assign mio_outsel_6_we = addr_hit[168] & reg_we & !reg_error;
Tests: T1 T2 T3
34184
34185 1/1 assign mio_outsel_6_wd = reg_wdata[6:0];
Tests: T1 T2 T3
34186 1/1 assign mio_outsel_7_we = addr_hit[169] & reg_we & !reg_error;
Tests: T1 T2 T3
34187
34188 1/1 assign mio_outsel_7_wd = reg_wdata[6:0];
Tests: T1 T2 T3
34189 1/1 assign mio_outsel_8_we = addr_hit[170] & reg_we & !reg_error;
Tests: T1 T2 T3
34190
34191 1/1 assign mio_outsel_8_wd = reg_wdata[6:0];
Tests: T1 T2 T3
34192 1/1 assign mio_outsel_9_we = addr_hit[171] & reg_we & !reg_error;
Tests: T1 T2 T3
34193
34194 1/1 assign mio_outsel_9_wd = reg_wdata[6:0];
Tests: T1 T2 T3
34195 1/1 assign mio_outsel_10_we = addr_hit[172] & reg_we & !reg_error;
Tests: T1 T2 T3
34196
34197 1/1 assign mio_outsel_10_wd = reg_wdata[6:0];
Tests: T1 T2 T3
34198 1/1 assign mio_outsel_11_we = addr_hit[173] & reg_we & !reg_error;
Tests: T1 T2 T3
34199
34200 1/1 assign mio_outsel_11_wd = reg_wdata[6:0];
Tests: T1 T2 T3
34201 1/1 assign mio_outsel_12_we = addr_hit[174] & reg_we & !reg_error;
Tests: T1 T2 T3
34202
34203 1/1 assign mio_outsel_12_wd = reg_wdata[6:0];
Tests: T1 T2 T3
34204 1/1 assign mio_outsel_13_we = addr_hit[175] & reg_we & !reg_error;
Tests: T1 T2 T3
34205
34206 1/1 assign mio_outsel_13_wd = reg_wdata[6:0];
Tests: T1 T2 T3
34207 1/1 assign mio_outsel_14_we = addr_hit[176] & reg_we & !reg_error;
Tests: T1 T2 T3
34208
34209 1/1 assign mio_outsel_14_wd = reg_wdata[6:0];
Tests: T1 T2 T3
34210 1/1 assign mio_outsel_15_we = addr_hit[177] & reg_we & !reg_error;
Tests: T1 T2 T3
34211
34212 1/1 assign mio_outsel_15_wd = reg_wdata[6:0];
Tests: T1 T2 T3
34213 1/1 assign mio_outsel_16_we = addr_hit[178] & reg_we & !reg_error;
Tests: T1 T2 T3
34214
34215 1/1 assign mio_outsel_16_wd = reg_wdata[6:0];
Tests: T1 T2 T3
34216 1/1 assign mio_outsel_17_we = addr_hit[179] & reg_we & !reg_error;
Tests: T1 T2 T3
34217
34218 1/1 assign mio_outsel_17_wd = reg_wdata[6:0];
Tests: T1 T2 T3
34219 1/1 assign mio_outsel_18_we = addr_hit[180] & reg_we & !reg_error;
Tests: T1 T2 T3
34220
34221 1/1 assign mio_outsel_18_wd = reg_wdata[6:0];
Tests: T1 T2 T3
34222 1/1 assign mio_outsel_19_we = addr_hit[181] & reg_we & !reg_error;
Tests: T1 T2 T3
34223
34224 1/1 assign mio_outsel_19_wd = reg_wdata[6:0];
Tests: T1 T2 T3
34225 1/1 assign mio_outsel_20_we = addr_hit[182] & reg_we & !reg_error;
Tests: T1 T2 T3
34226
34227 1/1 assign mio_outsel_20_wd = reg_wdata[6:0];
Tests: T1 T2 T3
34228 1/1 assign mio_outsel_21_we = addr_hit[183] & reg_we & !reg_error;
Tests: T1 T2 T3
34229
34230 1/1 assign mio_outsel_21_wd = reg_wdata[6:0];
Tests: T1 T2 T3
34231 1/1 assign mio_outsel_22_we = addr_hit[184] & reg_we & !reg_error;
Tests: T1 T2 T3
34232
34233 1/1 assign mio_outsel_22_wd = reg_wdata[6:0];
Tests: T1 T2 T3
34234 1/1 assign mio_outsel_23_we = addr_hit[185] & reg_we & !reg_error;
Tests: T1 T2 T3
34235
34236 1/1 assign mio_outsel_23_wd = reg_wdata[6:0];
Tests: T1 T2 T3
34237 1/1 assign mio_outsel_24_we = addr_hit[186] & reg_we & !reg_error;
Tests: T1 T2 T3
34238
34239 1/1 assign mio_outsel_24_wd = reg_wdata[6:0];
Tests: T1 T2 T3
34240 1/1 assign mio_outsel_25_we = addr_hit[187] & reg_we & !reg_error;
Tests: T1 T2 T3
34241
34242 1/1 assign mio_outsel_25_wd = reg_wdata[6:0];
Tests: T1 T2 T3
34243 1/1 assign mio_outsel_26_we = addr_hit[188] & reg_we & !reg_error;
Tests: T1 T2 T3
34244
34245 1/1 assign mio_outsel_26_wd = reg_wdata[6:0];
Tests: T1 T2 T3
34246 1/1 assign mio_outsel_27_we = addr_hit[189] & reg_we & !reg_error;
Tests: T1 T2 T3
34247
34248 1/1 assign mio_outsel_27_wd = reg_wdata[6:0];
Tests: T1 T2 T3
34249 1/1 assign mio_outsel_28_we = addr_hit[190] & reg_we & !reg_error;
Tests: T1 T2 T3
34250
34251 1/1 assign mio_outsel_28_wd = reg_wdata[6:0];
Tests: T1 T2 T3
34252 1/1 assign mio_outsel_29_we = addr_hit[191] & reg_we & !reg_error;
Tests: T1 T2 T3
34253
34254 1/1 assign mio_outsel_29_wd = reg_wdata[6:0];
Tests: T1 T2 T3
34255 1/1 assign mio_outsel_30_we = addr_hit[192] & reg_we & !reg_error;
Tests: T1 T2 T3
34256
34257 1/1 assign mio_outsel_30_wd = reg_wdata[6:0];
Tests: T1 T2 T3
34258 1/1 assign mio_outsel_31_we = addr_hit[193] & reg_we & !reg_error;
Tests: T1 T2 T3
34259
34260 1/1 assign mio_outsel_31_wd = reg_wdata[6:0];
Tests: T1 T2 T3
34261 1/1 assign mio_outsel_32_we = addr_hit[194] & reg_we & !reg_error;
Tests: T1 T2 T3
34262
34263 1/1 assign mio_outsel_32_wd = reg_wdata[6:0];
Tests: T1 T2 T3
34264 1/1 assign mio_outsel_33_we = addr_hit[195] & reg_we & !reg_error;
Tests: T1 T2 T3
34265
34266 1/1 assign mio_outsel_33_wd = reg_wdata[6:0];
Tests: T1 T2 T3
34267 1/1 assign mio_outsel_34_we = addr_hit[196] & reg_we & !reg_error;
Tests: T1 T2 T3
34268
34269 1/1 assign mio_outsel_34_wd = reg_wdata[6:0];
Tests: T1 T2 T3
34270 1/1 assign mio_outsel_35_we = addr_hit[197] & reg_we & !reg_error;
Tests: T1 T2 T3
34271
34272 1/1 assign mio_outsel_35_wd = reg_wdata[6:0];
Tests: T1 T2 T3
34273 1/1 assign mio_outsel_36_we = addr_hit[198] & reg_we & !reg_error;
Tests: T1 T2 T3
34274
34275 1/1 assign mio_outsel_36_wd = reg_wdata[6:0];
Tests: T1 T2 T3
34276 1/1 assign mio_outsel_37_we = addr_hit[199] & reg_we & !reg_error;
Tests: T1 T2 T3
34277
34278 1/1 assign mio_outsel_37_wd = reg_wdata[6:0];
Tests: T1 T2 T3
34279 1/1 assign mio_outsel_38_we = addr_hit[200] & reg_we & !reg_error;
Tests: T1 T2 T3
34280
34281 1/1 assign mio_outsel_38_wd = reg_wdata[6:0];
Tests: T1 T2 T3
34282 1/1 assign mio_outsel_39_we = addr_hit[201] & reg_we & !reg_error;
Tests: T1 T2 T3
34283
34284 1/1 assign mio_outsel_39_wd = reg_wdata[6:0];
Tests: T1 T2 T3
34285 1/1 assign mio_outsel_40_we = addr_hit[202] & reg_we & !reg_error;
Tests: T1 T2 T3
34286
34287 1/1 assign mio_outsel_40_wd = reg_wdata[6:0];
Tests: T1 T2 T3
34288 1/1 assign mio_outsel_41_we = addr_hit[203] & reg_we & !reg_error;
Tests: T1 T2 T3
34289
34290 1/1 assign mio_outsel_41_wd = reg_wdata[6:0];
Tests: T1 T2 T3
34291 1/1 assign mio_outsel_42_we = addr_hit[204] & reg_we & !reg_error;
Tests: T1 T2 T3
34292
34293 1/1 assign mio_outsel_42_wd = reg_wdata[6:0];
Tests: T1 T2 T3
34294 1/1 assign mio_outsel_43_we = addr_hit[205] & reg_we & !reg_error;
Tests: T1 T2 T3
34295
34296 1/1 assign mio_outsel_43_wd = reg_wdata[6:0];
Tests: T1 T2 T3
34297 1/1 assign mio_outsel_44_we = addr_hit[206] & reg_we & !reg_error;
Tests: T1 T2 T3
34298
34299 1/1 assign mio_outsel_44_wd = reg_wdata[6:0];
Tests: T1 T2 T3
34300 1/1 assign mio_outsel_45_we = addr_hit[207] & reg_we & !reg_error;
Tests: T1 T2 T3
34301
34302 1/1 assign mio_outsel_45_wd = reg_wdata[6:0];
Tests: T1 T2 T3
34303 1/1 assign mio_outsel_46_we = addr_hit[208] & reg_we & !reg_error;
Tests: T1 T2 T3
34304
34305 1/1 assign mio_outsel_46_wd = reg_wdata[6:0];
Tests: T1 T2 T3
34306 1/1 assign mio_pad_attr_regwen_0_we = addr_hit[209] & reg_we & !reg_error;
Tests: T1 T2 T3
34307
34308 1/1 assign mio_pad_attr_regwen_0_wd = reg_wdata[0];
Tests: T1 T2 T3
34309 1/1 assign mio_pad_attr_regwen_1_we = addr_hit[210] & reg_we & !reg_error;
Tests: T1 T2 T3
34310
34311 1/1 assign mio_pad_attr_regwen_1_wd = reg_wdata[0];
Tests: T1 T2 T3
34312 1/1 assign mio_pad_attr_regwen_2_we = addr_hit[211] & reg_we & !reg_error;
Tests: T1 T2 T3
34313
34314 1/1 assign mio_pad_attr_regwen_2_wd = reg_wdata[0];
Tests: T1 T2 T3
34315 1/1 assign mio_pad_attr_regwen_3_we = addr_hit[212] & reg_we & !reg_error;
Tests: T1 T2 T3
34316
34317 1/1 assign mio_pad_attr_regwen_3_wd = reg_wdata[0];
Tests: T1 T2 T3
34318 1/1 assign mio_pad_attr_regwen_4_we = addr_hit[213] & reg_we & !reg_error;
Tests: T1 T2 T3
34319
34320 1/1 assign mio_pad_attr_regwen_4_wd = reg_wdata[0];
Tests: T1 T2 T3
34321 1/1 assign mio_pad_attr_regwen_5_we = addr_hit[214] & reg_we & !reg_error;
Tests: T1 T2 T3
34322
34323 1/1 assign mio_pad_attr_regwen_5_wd = reg_wdata[0];
Tests: T1 T2 T3
34324 1/1 assign mio_pad_attr_regwen_6_we = addr_hit[215] & reg_we & !reg_error;
Tests: T1 T2 T3
34325
34326 1/1 assign mio_pad_attr_regwen_6_wd = reg_wdata[0];
Tests: T1 T2 T3
34327 1/1 assign mio_pad_attr_regwen_7_we = addr_hit[216] & reg_we & !reg_error;
Tests: T1 T2 T3
34328
34329 1/1 assign mio_pad_attr_regwen_7_wd = reg_wdata[0];
Tests: T1 T2 T3
34330 1/1 assign mio_pad_attr_regwen_8_we = addr_hit[217] & reg_we & !reg_error;
Tests: T1 T2 T3
34331
34332 1/1 assign mio_pad_attr_regwen_8_wd = reg_wdata[0];
Tests: T1 T2 T3
34333 1/1 assign mio_pad_attr_regwen_9_we = addr_hit[218] & reg_we & !reg_error;
Tests: T1 T2 T3
34334
34335 1/1 assign mio_pad_attr_regwen_9_wd = reg_wdata[0];
Tests: T1 T2 T3
34336 1/1 assign mio_pad_attr_regwen_10_we = addr_hit[219] & reg_we & !reg_error;
Tests: T1 T2 T3
34337
34338 1/1 assign mio_pad_attr_regwen_10_wd = reg_wdata[0];
Tests: T1 T2 T3
34339 1/1 assign mio_pad_attr_regwen_11_we = addr_hit[220] & reg_we & !reg_error;
Tests: T1 T2 T3
34340
34341 1/1 assign mio_pad_attr_regwen_11_wd = reg_wdata[0];
Tests: T1 T2 T3
34342 1/1 assign mio_pad_attr_regwen_12_we = addr_hit[221] & reg_we & !reg_error;
Tests: T1 T2 T3
34343
34344 1/1 assign mio_pad_attr_regwen_12_wd = reg_wdata[0];
Tests: T1 T2 T3
34345 1/1 assign mio_pad_attr_regwen_13_we = addr_hit[222] & reg_we & !reg_error;
Tests: T1 T2 T3
34346
34347 1/1 assign mio_pad_attr_regwen_13_wd = reg_wdata[0];
Tests: T1 T2 T3
34348 1/1 assign mio_pad_attr_regwen_14_we = addr_hit[223] & reg_we & !reg_error;
Tests: T1 T2 T3
34349
34350 1/1 assign mio_pad_attr_regwen_14_wd = reg_wdata[0];
Tests: T1 T2 T3
34351 1/1 assign mio_pad_attr_regwen_15_we = addr_hit[224] & reg_we & !reg_error;
Tests: T1 T2 T3
34352
34353 1/1 assign mio_pad_attr_regwen_15_wd = reg_wdata[0];
Tests: T1 T2 T3
34354 1/1 assign mio_pad_attr_regwen_16_we = addr_hit[225] & reg_we & !reg_error;
Tests: T1 T2 T3
34355
34356 1/1 assign mio_pad_attr_regwen_16_wd = reg_wdata[0];
Tests: T1 T2 T3
34357 1/1 assign mio_pad_attr_regwen_17_we = addr_hit[226] & reg_we & !reg_error;
Tests: T1 T2 T3
34358
34359 1/1 assign mio_pad_attr_regwen_17_wd = reg_wdata[0];
Tests: T1 T2 T3
34360 1/1 assign mio_pad_attr_regwen_18_we = addr_hit[227] & reg_we & !reg_error;
Tests: T1 T2 T3
34361
34362 1/1 assign mio_pad_attr_regwen_18_wd = reg_wdata[0];
Tests: T1 T2 T3
34363 1/1 assign mio_pad_attr_regwen_19_we = addr_hit[228] & reg_we & !reg_error;
Tests: T1 T2 T3
34364
34365 1/1 assign mio_pad_attr_regwen_19_wd = reg_wdata[0];
Tests: T1 T2 T3
34366 1/1 assign mio_pad_attr_regwen_20_we = addr_hit[229] & reg_we & !reg_error;
Tests: T1 T2 T3
34367
34368 1/1 assign mio_pad_attr_regwen_20_wd = reg_wdata[0];
Tests: T1 T2 T3
34369 1/1 assign mio_pad_attr_regwen_21_we = addr_hit[230] & reg_we & !reg_error;
Tests: T1 T2 T3
34370
34371 1/1 assign mio_pad_attr_regwen_21_wd = reg_wdata[0];
Tests: T1 T2 T3
34372 1/1 assign mio_pad_attr_regwen_22_we = addr_hit[231] & reg_we & !reg_error;
Tests: T1 T2 T3
34373
34374 1/1 assign mio_pad_attr_regwen_22_wd = reg_wdata[0];
Tests: T1 T2 T3
34375 1/1 assign mio_pad_attr_regwen_23_we = addr_hit[232] & reg_we & !reg_error;
Tests: T1 T2 T3
34376
34377 1/1 assign mio_pad_attr_regwen_23_wd = reg_wdata[0];
Tests: T1 T2 T3
34378 1/1 assign mio_pad_attr_regwen_24_we = addr_hit[233] & reg_we & !reg_error;
Tests: T1 T2 T3
34379
34380 1/1 assign mio_pad_attr_regwen_24_wd = reg_wdata[0];
Tests: T1 T2 T3
34381 1/1 assign mio_pad_attr_regwen_25_we = addr_hit[234] & reg_we & !reg_error;
Tests: T1 T2 T3
34382
34383 1/1 assign mio_pad_attr_regwen_25_wd = reg_wdata[0];
Tests: T1 T2 T3
34384 1/1 assign mio_pad_attr_regwen_26_we = addr_hit[235] & reg_we & !reg_error;
Tests: T1 T2 T3
34385
34386 1/1 assign mio_pad_attr_regwen_26_wd = reg_wdata[0];
Tests: T1 T2 T3
34387 1/1 assign mio_pad_attr_regwen_27_we = addr_hit[236] & reg_we & !reg_error;
Tests: T1 T2 T3
34388
34389 1/1 assign mio_pad_attr_regwen_27_wd = reg_wdata[0];
Tests: T1 T2 T3
34390 1/1 assign mio_pad_attr_regwen_28_we = addr_hit[237] & reg_we & !reg_error;
Tests: T1 T2 T3
34391
34392 1/1 assign mio_pad_attr_regwen_28_wd = reg_wdata[0];
Tests: T1 T2 T3
34393 1/1 assign mio_pad_attr_regwen_29_we = addr_hit[238] & reg_we & !reg_error;
Tests: T1 T2 T3
34394
34395 1/1 assign mio_pad_attr_regwen_29_wd = reg_wdata[0];
Tests: T1 T2 T3
34396 1/1 assign mio_pad_attr_regwen_30_we = addr_hit[239] & reg_we & !reg_error;
Tests: T1 T2 T3
34397
34398 1/1 assign mio_pad_attr_regwen_30_wd = reg_wdata[0];
Tests: T1 T2 T3
34399 1/1 assign mio_pad_attr_regwen_31_we = addr_hit[240] & reg_we & !reg_error;
Tests: T1 T2 T3
34400
34401 1/1 assign mio_pad_attr_regwen_31_wd = reg_wdata[0];
Tests: T1 T2 T3
34402 1/1 assign mio_pad_attr_regwen_32_we = addr_hit[241] & reg_we & !reg_error;
Tests: T1 T2 T3
34403
34404 1/1 assign mio_pad_attr_regwen_32_wd = reg_wdata[0];
Tests: T1 T2 T3
34405 1/1 assign mio_pad_attr_regwen_33_we = addr_hit[242] & reg_we & !reg_error;
Tests: T1 T2 T3
34406
34407 1/1 assign mio_pad_attr_regwen_33_wd = reg_wdata[0];
Tests: T1 T2 T3
34408 1/1 assign mio_pad_attr_regwen_34_we = addr_hit[243] & reg_we & !reg_error;
Tests: T1 T2 T3
34409
34410 1/1 assign mio_pad_attr_regwen_34_wd = reg_wdata[0];
Tests: T1 T2 T3
34411 1/1 assign mio_pad_attr_regwen_35_we = addr_hit[244] & reg_we & !reg_error;
Tests: T1 T2 T3
34412
34413 1/1 assign mio_pad_attr_regwen_35_wd = reg_wdata[0];
Tests: T1 T2 T3
34414 1/1 assign mio_pad_attr_regwen_36_we = addr_hit[245] & reg_we & !reg_error;
Tests: T1 T2 T3
34415
34416 1/1 assign mio_pad_attr_regwen_36_wd = reg_wdata[0];
Tests: T1 T2 T3
34417 1/1 assign mio_pad_attr_regwen_37_we = addr_hit[246] & reg_we & !reg_error;
Tests: T1 T2 T3
34418
34419 1/1 assign mio_pad_attr_regwen_37_wd = reg_wdata[0];
Tests: T1 T2 T3
34420 1/1 assign mio_pad_attr_regwen_38_we = addr_hit[247] & reg_we & !reg_error;
Tests: T1 T2 T3
34421
34422 1/1 assign mio_pad_attr_regwen_38_wd = reg_wdata[0];
Tests: T1 T2 T3
34423 1/1 assign mio_pad_attr_regwen_39_we = addr_hit[248] & reg_we & !reg_error;
Tests: T1 T2 T3
34424
34425 1/1 assign mio_pad_attr_regwen_39_wd = reg_wdata[0];
Tests: T1 T2 T3
34426 1/1 assign mio_pad_attr_regwen_40_we = addr_hit[249] & reg_we & !reg_error;
Tests: T1 T2 T3
34427
34428 1/1 assign mio_pad_attr_regwen_40_wd = reg_wdata[0];
Tests: T1 T2 T3
34429 1/1 assign mio_pad_attr_regwen_41_we = addr_hit[250] & reg_we & !reg_error;
Tests: T1 T2 T3
34430
34431 1/1 assign mio_pad_attr_regwen_41_wd = reg_wdata[0];
Tests: T1 T2 T3
34432 1/1 assign mio_pad_attr_regwen_42_we = addr_hit[251] & reg_we & !reg_error;
Tests: T1 T2 T3
34433
34434 1/1 assign mio_pad_attr_regwen_42_wd = reg_wdata[0];
Tests: T1 T2 T3
34435 1/1 assign mio_pad_attr_regwen_43_we = addr_hit[252] & reg_we & !reg_error;
Tests: T1 T2 T3
34436
34437 1/1 assign mio_pad_attr_regwen_43_wd = reg_wdata[0];
Tests: T1 T2 T3
34438 1/1 assign mio_pad_attr_regwen_44_we = addr_hit[253] & reg_we & !reg_error;
Tests: T1 T2 T3
34439
34440 1/1 assign mio_pad_attr_regwen_44_wd = reg_wdata[0];
Tests: T1 T2 T3
34441 1/1 assign mio_pad_attr_regwen_45_we = addr_hit[254] & reg_we & !reg_error;
Tests: T1 T2 T3
34442
34443 1/1 assign mio_pad_attr_regwen_45_wd = reg_wdata[0];
Tests: T1 T2 T3
34444 1/1 assign mio_pad_attr_regwen_46_we = addr_hit[255] & reg_we & !reg_error;
Tests: T1 T2 T3
34445
34446 1/1 assign mio_pad_attr_regwen_46_wd = reg_wdata[0];
Tests: T1 T2 T3
34447 1/1 assign mio_pad_attr_0_re = addr_hit[256] & reg_re & !reg_error;
Tests: T1 T2 T3
34448 1/1 assign mio_pad_attr_0_we = addr_hit[256] & reg_we & !reg_error;
Tests: T1 T2 T3
34449
34450 1/1 assign mio_pad_attr_0_invert_0_wd = reg_wdata[0];
Tests: T1 T2 T3
34451
34452 1/1 assign mio_pad_attr_0_virtual_od_en_0_wd = reg_wdata[1];
Tests: T1 T2 T3
34453
34454 1/1 assign mio_pad_attr_0_pull_en_0_wd = reg_wdata[2];
Tests: T1 T2 T3
34455
34456 1/1 assign mio_pad_attr_0_pull_select_0_wd = reg_wdata[3];
Tests: T1 T2 T3
34457
34458 1/1 assign mio_pad_attr_0_keeper_en_0_wd = reg_wdata[4];
Tests: T1 T2 T3
34459
34460 1/1 assign mio_pad_attr_0_schmitt_en_0_wd = reg_wdata[5];
Tests: T1 T2 T3
34461
34462 1/1 assign mio_pad_attr_0_od_en_0_wd = reg_wdata[6];
Tests: T1 T2 T3
34463
34464 1/1 assign mio_pad_attr_0_input_disable_0_wd = reg_wdata[7];
Tests: T1 T2 T3
34465
34466 1/1 assign mio_pad_attr_0_slew_rate_0_wd = reg_wdata[17:16];
Tests: T1 T2 T3
34467
34468 1/1 assign mio_pad_attr_0_drive_strength_0_wd = reg_wdata[23:20];
Tests: T1 T2 T3
34469 1/1 assign mio_pad_attr_1_re = addr_hit[257] & reg_re & !reg_error;
Tests: T1 T2 T3
34470 1/1 assign mio_pad_attr_1_we = addr_hit[257] & reg_we & !reg_error;
Tests: T1 T2 T3
34471
34472 1/1 assign mio_pad_attr_1_invert_1_wd = reg_wdata[0];
Tests: T1 T2 T3
34473
34474 1/1 assign mio_pad_attr_1_virtual_od_en_1_wd = reg_wdata[1];
Tests: T1 T2 T3
34475
34476 1/1 assign mio_pad_attr_1_pull_en_1_wd = reg_wdata[2];
Tests: T1 T2 T3
34477
34478 1/1 assign mio_pad_attr_1_pull_select_1_wd = reg_wdata[3];
Tests: T1 T2 T3
34479
34480 1/1 assign mio_pad_attr_1_keeper_en_1_wd = reg_wdata[4];
Tests: T1 T2 T3
34481
34482 1/1 assign mio_pad_attr_1_schmitt_en_1_wd = reg_wdata[5];
Tests: T1 T2 T3
34483
34484 1/1 assign mio_pad_attr_1_od_en_1_wd = reg_wdata[6];
Tests: T1 T2 T3
34485
34486 1/1 assign mio_pad_attr_1_input_disable_1_wd = reg_wdata[7];
Tests: T1 T2 T3
34487
34488 1/1 assign mio_pad_attr_1_slew_rate_1_wd = reg_wdata[17:16];
Tests: T1 T2 T3
34489
34490 1/1 assign mio_pad_attr_1_drive_strength_1_wd = reg_wdata[23:20];
Tests: T1 T2 T3
34491 1/1 assign mio_pad_attr_2_re = addr_hit[258] & reg_re & !reg_error;
Tests: T1 T2 T3
34492 1/1 assign mio_pad_attr_2_we = addr_hit[258] & reg_we & !reg_error;
Tests: T1 T2 T3
34493
34494 1/1 assign mio_pad_attr_2_invert_2_wd = reg_wdata[0];
Tests: T1 T2 T3
34495
34496 1/1 assign mio_pad_attr_2_virtual_od_en_2_wd = reg_wdata[1];
Tests: T1 T2 T3
34497
34498 1/1 assign mio_pad_attr_2_pull_en_2_wd = reg_wdata[2];
Tests: T1 T2 T3
34499
34500 1/1 assign mio_pad_attr_2_pull_select_2_wd = reg_wdata[3];
Tests: T1 T2 T3
34501
34502 1/1 assign mio_pad_attr_2_keeper_en_2_wd = reg_wdata[4];
Tests: T1 T2 T3
34503
34504 1/1 assign mio_pad_attr_2_schmitt_en_2_wd = reg_wdata[5];
Tests: T1 T2 T3
34505
34506 1/1 assign mio_pad_attr_2_od_en_2_wd = reg_wdata[6];
Tests: T1 T2 T3
34507
34508 1/1 assign mio_pad_attr_2_input_disable_2_wd = reg_wdata[7];
Tests: T1 T2 T3
34509
34510 1/1 assign mio_pad_attr_2_slew_rate_2_wd = reg_wdata[17:16];
Tests: T1 T2 T3
34511
34512 1/1 assign mio_pad_attr_2_drive_strength_2_wd = reg_wdata[23:20];
Tests: T1 T2 T3
34513 1/1 assign mio_pad_attr_3_re = addr_hit[259] & reg_re & !reg_error;
Tests: T1 T2 T3
34514 1/1 assign mio_pad_attr_3_we = addr_hit[259] & reg_we & !reg_error;
Tests: T1 T2 T3
34515
34516 1/1 assign mio_pad_attr_3_invert_3_wd = reg_wdata[0];
Tests: T1 T2 T3
34517
34518 1/1 assign mio_pad_attr_3_virtual_od_en_3_wd = reg_wdata[1];
Tests: T1 T2 T3
34519
34520 1/1 assign mio_pad_attr_3_pull_en_3_wd = reg_wdata[2];
Tests: T1 T2 T3
34521
34522 1/1 assign mio_pad_attr_3_pull_select_3_wd = reg_wdata[3];
Tests: T1 T2 T3
34523
34524 1/1 assign mio_pad_attr_3_keeper_en_3_wd = reg_wdata[4];
Tests: T1 T2 T3
34525
34526 1/1 assign mio_pad_attr_3_schmitt_en_3_wd = reg_wdata[5];
Tests: T1 T2 T3
34527
34528 1/1 assign mio_pad_attr_3_od_en_3_wd = reg_wdata[6];
Tests: T1 T2 T3
34529
34530 1/1 assign mio_pad_attr_3_input_disable_3_wd = reg_wdata[7];
Tests: T1 T2 T3
34531
34532 1/1 assign mio_pad_attr_3_slew_rate_3_wd = reg_wdata[17:16];
Tests: T1 T2 T3
34533
34534 1/1 assign mio_pad_attr_3_drive_strength_3_wd = reg_wdata[23:20];
Tests: T1 T2 T3
34535 1/1 assign mio_pad_attr_4_re = addr_hit[260] & reg_re & !reg_error;
Tests: T1 T2 T3
34536 1/1 assign mio_pad_attr_4_we = addr_hit[260] & reg_we & !reg_error;
Tests: T1 T2 T3
34537
34538 1/1 assign mio_pad_attr_4_invert_4_wd = reg_wdata[0];
Tests: T1 T2 T3
34539
34540 1/1 assign mio_pad_attr_4_virtual_od_en_4_wd = reg_wdata[1];
Tests: T1 T2 T3
34541
34542 1/1 assign mio_pad_attr_4_pull_en_4_wd = reg_wdata[2];
Tests: T1 T2 T3
34543
34544 1/1 assign mio_pad_attr_4_pull_select_4_wd = reg_wdata[3];
Tests: T1 T2 T3
34545
34546 1/1 assign mio_pad_attr_4_keeper_en_4_wd = reg_wdata[4];
Tests: T1 T2 T3
34547
34548 1/1 assign mio_pad_attr_4_schmitt_en_4_wd = reg_wdata[5];
Tests: T1 T2 T3
34549
34550 1/1 assign mio_pad_attr_4_od_en_4_wd = reg_wdata[6];
Tests: T1 T2 T3
34551
34552 1/1 assign mio_pad_attr_4_input_disable_4_wd = reg_wdata[7];
Tests: T1 T2 T3
34553
34554 1/1 assign mio_pad_attr_4_slew_rate_4_wd = reg_wdata[17:16];
Tests: T1 T2 T3
34555
34556 1/1 assign mio_pad_attr_4_drive_strength_4_wd = reg_wdata[23:20];
Tests: T1 T2 T3
34557 1/1 assign mio_pad_attr_5_re = addr_hit[261] & reg_re & !reg_error;
Tests: T1 T2 T3
34558 1/1 assign mio_pad_attr_5_we = addr_hit[261] & reg_we & !reg_error;
Tests: T1 T2 T3
34559
34560 1/1 assign mio_pad_attr_5_invert_5_wd = reg_wdata[0];
Tests: T1 T2 T3
34561
34562 1/1 assign mio_pad_attr_5_virtual_od_en_5_wd = reg_wdata[1];
Tests: T1 T2 T3
34563
34564 1/1 assign mio_pad_attr_5_pull_en_5_wd = reg_wdata[2];
Tests: T1 T2 T3
34565
34566 1/1 assign mio_pad_attr_5_pull_select_5_wd = reg_wdata[3];
Tests: T1 T2 T3
34567
34568 1/1 assign mio_pad_attr_5_keeper_en_5_wd = reg_wdata[4];
Tests: T1 T2 T3
34569
34570 1/1 assign mio_pad_attr_5_schmitt_en_5_wd = reg_wdata[5];
Tests: T1 T2 T3
34571
34572 1/1 assign mio_pad_attr_5_od_en_5_wd = reg_wdata[6];
Tests: T1 T2 T3
34573
34574 1/1 assign mio_pad_attr_5_input_disable_5_wd = reg_wdata[7];
Tests: T1 T2 T3
34575
34576 1/1 assign mio_pad_attr_5_slew_rate_5_wd = reg_wdata[17:16];
Tests: T1 T2 T3
34577
34578 1/1 assign mio_pad_attr_5_drive_strength_5_wd = reg_wdata[23:20];
Tests: T1 T2 T3
34579 1/1 assign mio_pad_attr_6_re = addr_hit[262] & reg_re & !reg_error;
Tests: T1 T2 T3
34580 1/1 assign mio_pad_attr_6_we = addr_hit[262] & reg_we & !reg_error;
Tests: T1 T2 T3
34581
34582 1/1 assign mio_pad_attr_6_invert_6_wd = reg_wdata[0];
Tests: T1 T2 T3
34583
34584 1/1 assign mio_pad_attr_6_virtual_od_en_6_wd = reg_wdata[1];
Tests: T1 T2 T3
34585
34586 1/1 assign mio_pad_attr_6_pull_en_6_wd = reg_wdata[2];
Tests: T1 T2 T3
34587
34588 1/1 assign mio_pad_attr_6_pull_select_6_wd = reg_wdata[3];
Tests: T1 T2 T3
34589
34590 1/1 assign mio_pad_attr_6_keeper_en_6_wd = reg_wdata[4];
Tests: T1 T2 T3
34591
34592 1/1 assign mio_pad_attr_6_schmitt_en_6_wd = reg_wdata[5];
Tests: T1 T2 T3
34593
34594 1/1 assign mio_pad_attr_6_od_en_6_wd = reg_wdata[6];
Tests: T1 T2 T3
34595
34596 1/1 assign mio_pad_attr_6_input_disable_6_wd = reg_wdata[7];
Tests: T1 T2 T3
34597
34598 1/1 assign mio_pad_attr_6_slew_rate_6_wd = reg_wdata[17:16];
Tests: T1 T2 T3
34599
34600 1/1 assign mio_pad_attr_6_drive_strength_6_wd = reg_wdata[23:20];
Tests: T1 T2 T3
34601 1/1 assign mio_pad_attr_7_re = addr_hit[263] & reg_re & !reg_error;
Tests: T1 T2 T3
34602 1/1 assign mio_pad_attr_7_we = addr_hit[263] & reg_we & !reg_error;
Tests: T1 T2 T3
34603
34604 1/1 assign mio_pad_attr_7_invert_7_wd = reg_wdata[0];
Tests: T1 T2 T3
34605
34606 1/1 assign mio_pad_attr_7_virtual_od_en_7_wd = reg_wdata[1];
Tests: T1 T2 T3
34607
34608 1/1 assign mio_pad_attr_7_pull_en_7_wd = reg_wdata[2];
Tests: T1 T2 T3
34609
34610 1/1 assign mio_pad_attr_7_pull_select_7_wd = reg_wdata[3];
Tests: T1 T2 T3
34611
34612 1/1 assign mio_pad_attr_7_keeper_en_7_wd = reg_wdata[4];
Tests: T1 T2 T3
34613
34614 1/1 assign mio_pad_attr_7_schmitt_en_7_wd = reg_wdata[5];
Tests: T1 T2 T3
34615
34616 1/1 assign mio_pad_attr_7_od_en_7_wd = reg_wdata[6];
Tests: T1 T2 T3
34617
34618 1/1 assign mio_pad_attr_7_input_disable_7_wd = reg_wdata[7];
Tests: T1 T2 T3
34619
34620 1/1 assign mio_pad_attr_7_slew_rate_7_wd = reg_wdata[17:16];
Tests: T1 T2 T3
34621
34622 1/1 assign mio_pad_attr_7_drive_strength_7_wd = reg_wdata[23:20];
Tests: T1 T2 T3
34623 1/1 assign mio_pad_attr_8_re = addr_hit[264] & reg_re & !reg_error;
Tests: T1 T2 T3
34624 1/1 assign mio_pad_attr_8_we = addr_hit[264] & reg_we & !reg_error;
Tests: T1 T2 T3
34625
34626 1/1 assign mio_pad_attr_8_invert_8_wd = reg_wdata[0];
Tests: T1 T2 T3
34627
34628 1/1 assign mio_pad_attr_8_virtual_od_en_8_wd = reg_wdata[1];
Tests: T1 T2 T3
34629
34630 1/1 assign mio_pad_attr_8_pull_en_8_wd = reg_wdata[2];
Tests: T1 T2 T3
34631
34632 1/1 assign mio_pad_attr_8_pull_select_8_wd = reg_wdata[3];
Tests: T1 T2 T3
34633
34634 1/1 assign mio_pad_attr_8_keeper_en_8_wd = reg_wdata[4];
Tests: T1 T2 T3
34635
34636 1/1 assign mio_pad_attr_8_schmitt_en_8_wd = reg_wdata[5];
Tests: T1 T2 T3
34637
34638 1/1 assign mio_pad_attr_8_od_en_8_wd = reg_wdata[6];
Tests: T1 T2 T3
34639
34640 1/1 assign mio_pad_attr_8_input_disable_8_wd = reg_wdata[7];
Tests: T1 T2 T3
34641
34642 1/1 assign mio_pad_attr_8_slew_rate_8_wd = reg_wdata[17:16];
Tests: T1 T2 T3
34643
34644 1/1 assign mio_pad_attr_8_drive_strength_8_wd = reg_wdata[23:20];
Tests: T1 T2 T3
34645 1/1 assign mio_pad_attr_9_re = addr_hit[265] & reg_re & !reg_error;
Tests: T1 T2 T3
34646 1/1 assign mio_pad_attr_9_we = addr_hit[265] & reg_we & !reg_error;
Tests: T1 T2 T3
34647
34648 1/1 assign mio_pad_attr_9_invert_9_wd = reg_wdata[0];
Tests: T1 T2 T3
34649
34650 1/1 assign mio_pad_attr_9_virtual_od_en_9_wd = reg_wdata[1];
Tests: T1 T2 T3
34651
34652 1/1 assign mio_pad_attr_9_pull_en_9_wd = reg_wdata[2];
Tests: T1 T2 T3
34653
34654 1/1 assign mio_pad_attr_9_pull_select_9_wd = reg_wdata[3];
Tests: T1 T2 T3
34655
34656 1/1 assign mio_pad_attr_9_keeper_en_9_wd = reg_wdata[4];
Tests: T1 T2 T3
34657
34658 1/1 assign mio_pad_attr_9_schmitt_en_9_wd = reg_wdata[5];
Tests: T1 T2 T3
34659
34660 1/1 assign mio_pad_attr_9_od_en_9_wd = reg_wdata[6];
Tests: T1 T2 T3
34661
34662 1/1 assign mio_pad_attr_9_input_disable_9_wd = reg_wdata[7];
Tests: T1 T2 T3
34663
34664 1/1 assign mio_pad_attr_9_slew_rate_9_wd = reg_wdata[17:16];
Tests: T1 T2 T3
34665
34666 1/1 assign mio_pad_attr_9_drive_strength_9_wd = reg_wdata[23:20];
Tests: T1 T2 T3
34667 1/1 assign mio_pad_attr_10_re = addr_hit[266] & reg_re & !reg_error;
Tests: T1 T2 T3
34668 1/1 assign mio_pad_attr_10_we = addr_hit[266] & reg_we & !reg_error;
Tests: T1 T2 T3
34669
34670 1/1 assign mio_pad_attr_10_invert_10_wd = reg_wdata[0];
Tests: T1 T2 T3
34671
34672 1/1 assign mio_pad_attr_10_virtual_od_en_10_wd = reg_wdata[1];
Tests: T1 T2 T3
34673
34674 1/1 assign mio_pad_attr_10_pull_en_10_wd = reg_wdata[2];
Tests: T1 T2 T3
34675
34676 1/1 assign mio_pad_attr_10_pull_select_10_wd = reg_wdata[3];
Tests: T1 T2 T3
34677
34678 1/1 assign mio_pad_attr_10_keeper_en_10_wd = reg_wdata[4];
Tests: T1 T2 T3
34679
34680 1/1 assign mio_pad_attr_10_schmitt_en_10_wd = reg_wdata[5];
Tests: T1 T2 T3
34681
34682 1/1 assign mio_pad_attr_10_od_en_10_wd = reg_wdata[6];
Tests: T1 T2 T3
34683
34684 1/1 assign mio_pad_attr_10_input_disable_10_wd = reg_wdata[7];
Tests: T1 T2 T3
34685
34686 1/1 assign mio_pad_attr_10_slew_rate_10_wd = reg_wdata[17:16];
Tests: T1 T2 T3
34687
34688 1/1 assign mio_pad_attr_10_drive_strength_10_wd = reg_wdata[23:20];
Tests: T1 T2 T3
34689 1/1 assign mio_pad_attr_11_re = addr_hit[267] & reg_re & !reg_error;
Tests: T1 T2 T3
34690 1/1 assign mio_pad_attr_11_we = addr_hit[267] & reg_we & !reg_error;
Tests: T1 T2 T3
34691
34692 1/1 assign mio_pad_attr_11_invert_11_wd = reg_wdata[0];
Tests: T1 T2 T3
34693
34694 1/1 assign mio_pad_attr_11_virtual_od_en_11_wd = reg_wdata[1];
Tests: T1 T2 T3
34695
34696 1/1 assign mio_pad_attr_11_pull_en_11_wd = reg_wdata[2];
Tests: T1 T2 T3
34697
34698 1/1 assign mio_pad_attr_11_pull_select_11_wd = reg_wdata[3];
Tests: T1 T2 T3
34699
34700 1/1 assign mio_pad_attr_11_keeper_en_11_wd = reg_wdata[4];
Tests: T1 T2 T3
34701
34702 1/1 assign mio_pad_attr_11_schmitt_en_11_wd = reg_wdata[5];
Tests: T1 T2 T3
34703
34704 1/1 assign mio_pad_attr_11_od_en_11_wd = reg_wdata[6];
Tests: T1 T2 T3
34705
34706 1/1 assign mio_pad_attr_11_input_disable_11_wd = reg_wdata[7];
Tests: T1 T2 T3
34707
34708 1/1 assign mio_pad_attr_11_slew_rate_11_wd = reg_wdata[17:16];
Tests: T1 T2 T3
34709
34710 1/1 assign mio_pad_attr_11_drive_strength_11_wd = reg_wdata[23:20];
Tests: T1 T2 T3
34711 1/1 assign mio_pad_attr_12_re = addr_hit[268] & reg_re & !reg_error;
Tests: T1 T2 T3
34712 1/1 assign mio_pad_attr_12_we = addr_hit[268] & reg_we & !reg_error;
Tests: T1 T2 T3
34713
34714 1/1 assign mio_pad_attr_12_invert_12_wd = reg_wdata[0];
Tests: T1 T2 T3
34715
34716 1/1 assign mio_pad_attr_12_virtual_od_en_12_wd = reg_wdata[1];
Tests: T1 T2 T3
34717
34718 1/1 assign mio_pad_attr_12_pull_en_12_wd = reg_wdata[2];
Tests: T1 T2 T3
34719
34720 1/1 assign mio_pad_attr_12_pull_select_12_wd = reg_wdata[3];
Tests: T1 T2 T3
34721
34722 1/1 assign mio_pad_attr_12_keeper_en_12_wd = reg_wdata[4];
Tests: T1 T2 T3
34723
34724 1/1 assign mio_pad_attr_12_schmitt_en_12_wd = reg_wdata[5];
Tests: T1 T2 T3
34725
34726 1/1 assign mio_pad_attr_12_od_en_12_wd = reg_wdata[6];
Tests: T1 T2 T3
34727
34728 1/1 assign mio_pad_attr_12_input_disable_12_wd = reg_wdata[7];
Tests: T1 T2 T3
34729
34730 1/1 assign mio_pad_attr_12_slew_rate_12_wd = reg_wdata[17:16];
Tests: T1 T2 T3
34731
34732 1/1 assign mio_pad_attr_12_drive_strength_12_wd = reg_wdata[23:20];
Tests: T1 T2 T3
34733 1/1 assign mio_pad_attr_13_re = addr_hit[269] & reg_re & !reg_error;
Tests: T1 T2 T3
34734 1/1 assign mio_pad_attr_13_we = addr_hit[269] & reg_we & !reg_error;
Tests: T1 T2 T3
34735
34736 1/1 assign mio_pad_attr_13_invert_13_wd = reg_wdata[0];
Tests: T1 T2 T3
34737
34738 1/1 assign mio_pad_attr_13_virtual_od_en_13_wd = reg_wdata[1];
Tests: T1 T2 T3
34739
34740 1/1 assign mio_pad_attr_13_pull_en_13_wd = reg_wdata[2];
Tests: T1 T2 T3
34741
34742 1/1 assign mio_pad_attr_13_pull_select_13_wd = reg_wdata[3];
Tests: T1 T2 T3
34743
34744 1/1 assign mio_pad_attr_13_keeper_en_13_wd = reg_wdata[4];
Tests: T1 T2 T3
34745
34746 1/1 assign mio_pad_attr_13_schmitt_en_13_wd = reg_wdata[5];
Tests: T1 T2 T3
34747
34748 1/1 assign mio_pad_attr_13_od_en_13_wd = reg_wdata[6];
Tests: T1 T2 T3
34749
34750 1/1 assign mio_pad_attr_13_input_disable_13_wd = reg_wdata[7];
Tests: T1 T2 T3
34751
34752 1/1 assign mio_pad_attr_13_slew_rate_13_wd = reg_wdata[17:16];
Tests: T1 T2 T3
34753
34754 1/1 assign mio_pad_attr_13_drive_strength_13_wd = reg_wdata[23:20];
Tests: T1 T2 T3
34755 1/1 assign mio_pad_attr_14_re = addr_hit[270] & reg_re & !reg_error;
Tests: T1 T2 T3
34756 1/1 assign mio_pad_attr_14_we = addr_hit[270] & reg_we & !reg_error;
Tests: T1 T2 T3
34757
34758 1/1 assign mio_pad_attr_14_invert_14_wd = reg_wdata[0];
Tests: T1 T2 T3
34759
34760 1/1 assign mio_pad_attr_14_virtual_od_en_14_wd = reg_wdata[1];
Tests: T1 T2 T3
34761
34762 1/1 assign mio_pad_attr_14_pull_en_14_wd = reg_wdata[2];
Tests: T1 T2 T3
34763
34764 1/1 assign mio_pad_attr_14_pull_select_14_wd = reg_wdata[3];
Tests: T1 T2 T3
34765
34766 1/1 assign mio_pad_attr_14_keeper_en_14_wd = reg_wdata[4];
Tests: T1 T2 T3
34767
34768 1/1 assign mio_pad_attr_14_schmitt_en_14_wd = reg_wdata[5];
Tests: T1 T2 T3
34769
34770 1/1 assign mio_pad_attr_14_od_en_14_wd = reg_wdata[6];
Tests: T1 T2 T3
34771
34772 1/1 assign mio_pad_attr_14_input_disable_14_wd = reg_wdata[7];
Tests: T1 T2 T3
34773
34774 1/1 assign mio_pad_attr_14_slew_rate_14_wd = reg_wdata[17:16];
Tests: T1 T2 T3
34775
34776 1/1 assign mio_pad_attr_14_drive_strength_14_wd = reg_wdata[23:20];
Tests: T1 T2 T3
34777 1/1 assign mio_pad_attr_15_re = addr_hit[271] & reg_re & !reg_error;
Tests: T1 T2 T3
34778 1/1 assign mio_pad_attr_15_we = addr_hit[271] & reg_we & !reg_error;
Tests: T1 T2 T3
34779
34780 1/1 assign mio_pad_attr_15_invert_15_wd = reg_wdata[0];
Tests: T1 T2 T3
34781
34782 1/1 assign mio_pad_attr_15_virtual_od_en_15_wd = reg_wdata[1];
Tests: T1 T2 T3
34783
34784 1/1 assign mio_pad_attr_15_pull_en_15_wd = reg_wdata[2];
Tests: T1 T2 T3
34785
34786 1/1 assign mio_pad_attr_15_pull_select_15_wd = reg_wdata[3];
Tests: T1 T2 T3
34787
34788 1/1 assign mio_pad_attr_15_keeper_en_15_wd = reg_wdata[4];
Tests: T1 T2 T3
34789
34790 1/1 assign mio_pad_attr_15_schmitt_en_15_wd = reg_wdata[5];
Tests: T1 T2 T3
34791
34792 1/1 assign mio_pad_attr_15_od_en_15_wd = reg_wdata[6];
Tests: T1 T2 T3
34793
34794 1/1 assign mio_pad_attr_15_input_disable_15_wd = reg_wdata[7];
Tests: T1 T2 T3
34795
34796 1/1 assign mio_pad_attr_15_slew_rate_15_wd = reg_wdata[17:16];
Tests: T1 T2 T3
34797
34798 1/1 assign mio_pad_attr_15_drive_strength_15_wd = reg_wdata[23:20];
Tests: T1 T2 T3
34799 1/1 assign mio_pad_attr_16_re = addr_hit[272] & reg_re & !reg_error;
Tests: T1 T2 T3
34800 1/1 assign mio_pad_attr_16_we = addr_hit[272] & reg_we & !reg_error;
Tests: T1 T2 T3
34801
34802 1/1 assign mio_pad_attr_16_invert_16_wd = reg_wdata[0];
Tests: T1 T2 T3
34803
34804 1/1 assign mio_pad_attr_16_virtual_od_en_16_wd = reg_wdata[1];
Tests: T1 T2 T3
34805
34806 1/1 assign mio_pad_attr_16_pull_en_16_wd = reg_wdata[2];
Tests: T1 T2 T3
34807
34808 1/1 assign mio_pad_attr_16_pull_select_16_wd = reg_wdata[3];
Tests: T1 T2 T3
34809
34810 1/1 assign mio_pad_attr_16_keeper_en_16_wd = reg_wdata[4];
Tests: T1 T2 T3
34811
34812 1/1 assign mio_pad_attr_16_schmitt_en_16_wd = reg_wdata[5];
Tests: T1 T2 T3
34813
34814 1/1 assign mio_pad_attr_16_od_en_16_wd = reg_wdata[6];
Tests: T1 T2 T3
34815
34816 1/1 assign mio_pad_attr_16_input_disable_16_wd = reg_wdata[7];
Tests: T1 T2 T3
34817
34818 1/1 assign mio_pad_attr_16_slew_rate_16_wd = reg_wdata[17:16];
Tests: T1 T2 T3
34819
34820 1/1 assign mio_pad_attr_16_drive_strength_16_wd = reg_wdata[23:20];
Tests: T1 T2 T3
34821 1/1 assign mio_pad_attr_17_re = addr_hit[273] & reg_re & !reg_error;
Tests: T1 T2 T3
34822 1/1 assign mio_pad_attr_17_we = addr_hit[273] & reg_we & !reg_error;
Tests: T1 T2 T3
34823
34824 1/1 assign mio_pad_attr_17_invert_17_wd = reg_wdata[0];
Tests: T1 T2 T3
34825
34826 1/1 assign mio_pad_attr_17_virtual_od_en_17_wd = reg_wdata[1];
Tests: T1 T2 T3
34827
34828 1/1 assign mio_pad_attr_17_pull_en_17_wd = reg_wdata[2];
Tests: T1 T2 T3
34829
34830 1/1 assign mio_pad_attr_17_pull_select_17_wd = reg_wdata[3];
Tests: T1 T2 T3
34831
34832 1/1 assign mio_pad_attr_17_keeper_en_17_wd = reg_wdata[4];
Tests: T1 T2 T3
34833
34834 1/1 assign mio_pad_attr_17_schmitt_en_17_wd = reg_wdata[5];
Tests: T1 T2 T3
34835
34836 1/1 assign mio_pad_attr_17_od_en_17_wd = reg_wdata[6];
Tests: T1 T2 T3
34837
34838 1/1 assign mio_pad_attr_17_input_disable_17_wd = reg_wdata[7];
Tests: T1 T2 T3
34839
34840 1/1 assign mio_pad_attr_17_slew_rate_17_wd = reg_wdata[17:16];
Tests: T1 T2 T3
34841
34842 1/1 assign mio_pad_attr_17_drive_strength_17_wd = reg_wdata[23:20];
Tests: T1 T2 T3
34843 1/1 assign mio_pad_attr_18_re = addr_hit[274] & reg_re & !reg_error;
Tests: T1 T2 T3
34844 1/1 assign mio_pad_attr_18_we = addr_hit[274] & reg_we & !reg_error;
Tests: T1 T2 T3
34845
34846 1/1 assign mio_pad_attr_18_invert_18_wd = reg_wdata[0];
Tests: T1 T2 T3
34847
34848 1/1 assign mio_pad_attr_18_virtual_od_en_18_wd = reg_wdata[1];
Tests: T1 T2 T3
34849
34850 1/1 assign mio_pad_attr_18_pull_en_18_wd = reg_wdata[2];
Tests: T1 T2 T3
34851
34852 1/1 assign mio_pad_attr_18_pull_select_18_wd = reg_wdata[3];
Tests: T1 T2 T3
34853
34854 1/1 assign mio_pad_attr_18_keeper_en_18_wd = reg_wdata[4];
Tests: T1 T2 T3
34855
34856 1/1 assign mio_pad_attr_18_schmitt_en_18_wd = reg_wdata[5];
Tests: T1 T2 T3
34857
34858 1/1 assign mio_pad_attr_18_od_en_18_wd = reg_wdata[6];
Tests: T1 T2 T3
34859
34860 1/1 assign mio_pad_attr_18_input_disable_18_wd = reg_wdata[7];
Tests: T1 T2 T3
34861
34862 1/1 assign mio_pad_attr_18_slew_rate_18_wd = reg_wdata[17:16];
Tests: T1 T2 T3
34863
34864 1/1 assign mio_pad_attr_18_drive_strength_18_wd = reg_wdata[23:20];
Tests: T1 T2 T3
34865 1/1 assign mio_pad_attr_19_re = addr_hit[275] & reg_re & !reg_error;
Tests: T1 T2 T3
34866 1/1 assign mio_pad_attr_19_we = addr_hit[275] & reg_we & !reg_error;
Tests: T1 T2 T3
34867
34868 1/1 assign mio_pad_attr_19_invert_19_wd = reg_wdata[0];
Tests: T1 T2 T3
34869
34870 1/1 assign mio_pad_attr_19_virtual_od_en_19_wd = reg_wdata[1];
Tests: T1 T2 T3
34871
34872 1/1 assign mio_pad_attr_19_pull_en_19_wd = reg_wdata[2];
Tests: T1 T2 T3
34873
34874 1/1 assign mio_pad_attr_19_pull_select_19_wd = reg_wdata[3];
Tests: T1 T2 T3
34875
34876 1/1 assign mio_pad_attr_19_keeper_en_19_wd = reg_wdata[4];
Tests: T1 T2 T3
34877
34878 1/1 assign mio_pad_attr_19_schmitt_en_19_wd = reg_wdata[5];
Tests: T1 T2 T3
34879
34880 1/1 assign mio_pad_attr_19_od_en_19_wd = reg_wdata[6];
Tests: T1 T2 T3
34881
34882 1/1 assign mio_pad_attr_19_input_disable_19_wd = reg_wdata[7];
Tests: T1 T2 T3
34883
34884 1/1 assign mio_pad_attr_19_slew_rate_19_wd = reg_wdata[17:16];
Tests: T1 T2 T3
34885
34886 1/1 assign mio_pad_attr_19_drive_strength_19_wd = reg_wdata[23:20];
Tests: T1 T2 T3
34887 1/1 assign mio_pad_attr_20_re = addr_hit[276] & reg_re & !reg_error;
Tests: T1 T2 T3
34888 1/1 assign mio_pad_attr_20_we = addr_hit[276] & reg_we & !reg_error;
Tests: T1 T2 T3
34889
34890 1/1 assign mio_pad_attr_20_invert_20_wd = reg_wdata[0];
Tests: T1 T2 T3
34891
34892 1/1 assign mio_pad_attr_20_virtual_od_en_20_wd = reg_wdata[1];
Tests: T1 T2 T3
34893
34894 1/1 assign mio_pad_attr_20_pull_en_20_wd = reg_wdata[2];
Tests: T1 T2 T3
34895
34896 1/1 assign mio_pad_attr_20_pull_select_20_wd = reg_wdata[3];
Tests: T1 T2 T3
34897
34898 1/1 assign mio_pad_attr_20_keeper_en_20_wd = reg_wdata[4];
Tests: T1 T2 T3
34899
34900 1/1 assign mio_pad_attr_20_schmitt_en_20_wd = reg_wdata[5];
Tests: T1 T2 T3
34901
34902 1/1 assign mio_pad_attr_20_od_en_20_wd = reg_wdata[6];
Tests: T1 T2 T3
34903
34904 1/1 assign mio_pad_attr_20_input_disable_20_wd = reg_wdata[7];
Tests: T1 T2 T3
34905
34906 1/1 assign mio_pad_attr_20_slew_rate_20_wd = reg_wdata[17:16];
Tests: T1 T2 T3
34907
34908 1/1 assign mio_pad_attr_20_drive_strength_20_wd = reg_wdata[23:20];
Tests: T1 T2 T3
34909 1/1 assign mio_pad_attr_21_re = addr_hit[277] & reg_re & !reg_error;
Tests: T1 T2 T3
34910 1/1 assign mio_pad_attr_21_we = addr_hit[277] & reg_we & !reg_error;
Tests: T1 T2 T3
34911
34912 1/1 assign mio_pad_attr_21_invert_21_wd = reg_wdata[0];
Tests: T1 T2 T3
34913
34914 1/1 assign mio_pad_attr_21_virtual_od_en_21_wd = reg_wdata[1];
Tests: T1 T2 T3
34915
34916 1/1 assign mio_pad_attr_21_pull_en_21_wd = reg_wdata[2];
Tests: T1 T2 T3
34917
34918 1/1 assign mio_pad_attr_21_pull_select_21_wd = reg_wdata[3];
Tests: T1 T2 T3
34919
34920 1/1 assign mio_pad_attr_21_keeper_en_21_wd = reg_wdata[4];
Tests: T1 T2 T3
34921
34922 1/1 assign mio_pad_attr_21_schmitt_en_21_wd = reg_wdata[5];
Tests: T1 T2 T3
34923
34924 1/1 assign mio_pad_attr_21_od_en_21_wd = reg_wdata[6];
Tests: T1 T2 T3
34925
34926 1/1 assign mio_pad_attr_21_input_disable_21_wd = reg_wdata[7];
Tests: T1 T2 T3
34927
34928 1/1 assign mio_pad_attr_21_slew_rate_21_wd = reg_wdata[17:16];
Tests: T1 T2 T3
34929
34930 1/1 assign mio_pad_attr_21_drive_strength_21_wd = reg_wdata[23:20];
Tests: T1 T2 T3
34931 1/1 assign mio_pad_attr_22_re = addr_hit[278] & reg_re & !reg_error;
Tests: T1 T2 T3
34932 1/1 assign mio_pad_attr_22_we = addr_hit[278] & reg_we & !reg_error;
Tests: T1 T2 T3
34933
34934 1/1 assign mio_pad_attr_22_invert_22_wd = reg_wdata[0];
Tests: T1 T2 T3
34935
34936 1/1 assign mio_pad_attr_22_virtual_od_en_22_wd = reg_wdata[1];
Tests: T1 T2 T3
34937
34938 1/1 assign mio_pad_attr_22_pull_en_22_wd = reg_wdata[2];
Tests: T1 T2 T3
34939
34940 1/1 assign mio_pad_attr_22_pull_select_22_wd = reg_wdata[3];
Tests: T1 T2 T3
34941
34942 1/1 assign mio_pad_attr_22_keeper_en_22_wd = reg_wdata[4];
Tests: T1 T2 T3
34943
34944 1/1 assign mio_pad_attr_22_schmitt_en_22_wd = reg_wdata[5];
Tests: T1 T2 T3
34945
34946 1/1 assign mio_pad_attr_22_od_en_22_wd = reg_wdata[6];
Tests: T1 T2 T3
34947
34948 1/1 assign mio_pad_attr_22_input_disable_22_wd = reg_wdata[7];
Tests: T1 T2 T3
34949
34950 1/1 assign mio_pad_attr_22_slew_rate_22_wd = reg_wdata[17:16];
Tests: T1 T2 T3
34951
34952 1/1 assign mio_pad_attr_22_drive_strength_22_wd = reg_wdata[23:20];
Tests: T1 T2 T3
34953 1/1 assign mio_pad_attr_23_re = addr_hit[279] & reg_re & !reg_error;
Tests: T1 T2 T3
34954 1/1 assign mio_pad_attr_23_we = addr_hit[279] & reg_we & !reg_error;
Tests: T1 T2 T3
34955
34956 1/1 assign mio_pad_attr_23_invert_23_wd = reg_wdata[0];
Tests: T1 T2 T3
34957
34958 1/1 assign mio_pad_attr_23_virtual_od_en_23_wd = reg_wdata[1];
Tests: T1 T2 T3
34959
34960 1/1 assign mio_pad_attr_23_pull_en_23_wd = reg_wdata[2];
Tests: T1 T2 T3
34961
34962 1/1 assign mio_pad_attr_23_pull_select_23_wd = reg_wdata[3];
Tests: T1 T2 T3
34963
34964 1/1 assign mio_pad_attr_23_keeper_en_23_wd = reg_wdata[4];
Tests: T1 T2 T3
34965
34966 1/1 assign mio_pad_attr_23_schmitt_en_23_wd = reg_wdata[5];
Tests: T1 T2 T3
34967
34968 1/1 assign mio_pad_attr_23_od_en_23_wd = reg_wdata[6];
Tests: T1 T2 T3
34969
34970 1/1 assign mio_pad_attr_23_input_disable_23_wd = reg_wdata[7];
Tests: T1 T2 T3
34971
34972 1/1 assign mio_pad_attr_23_slew_rate_23_wd = reg_wdata[17:16];
Tests: T1 T2 T3
34973
34974 1/1 assign mio_pad_attr_23_drive_strength_23_wd = reg_wdata[23:20];
Tests: T1 T2 T3
34975 1/1 assign mio_pad_attr_24_re = addr_hit[280] & reg_re & !reg_error;
Tests: T1 T2 T3
34976 1/1 assign mio_pad_attr_24_we = addr_hit[280] & reg_we & !reg_error;
Tests: T1 T2 T3
34977
34978 1/1 assign mio_pad_attr_24_invert_24_wd = reg_wdata[0];
Tests: T1 T2 T3
34979
34980 1/1 assign mio_pad_attr_24_virtual_od_en_24_wd = reg_wdata[1];
Tests: T1 T2 T3
34981
34982 1/1 assign mio_pad_attr_24_pull_en_24_wd = reg_wdata[2];
Tests: T1 T2 T3
34983
34984 1/1 assign mio_pad_attr_24_pull_select_24_wd = reg_wdata[3];
Tests: T1 T2 T3
34985
34986 1/1 assign mio_pad_attr_24_keeper_en_24_wd = reg_wdata[4];
Tests: T1 T2 T3
34987
34988 1/1 assign mio_pad_attr_24_schmitt_en_24_wd = reg_wdata[5];
Tests: T1 T2 T3
34989
34990 1/1 assign mio_pad_attr_24_od_en_24_wd = reg_wdata[6];
Tests: T1 T2 T3
34991
34992 1/1 assign mio_pad_attr_24_input_disable_24_wd = reg_wdata[7];
Tests: T1 T2 T3
34993
34994 1/1 assign mio_pad_attr_24_slew_rate_24_wd = reg_wdata[17:16];
Tests: T1 T2 T3
34995
34996 1/1 assign mio_pad_attr_24_drive_strength_24_wd = reg_wdata[23:20];
Tests: T1 T2 T3
34997 1/1 assign mio_pad_attr_25_re = addr_hit[281] & reg_re & !reg_error;
Tests: T1 T2 T3
34998 1/1 assign mio_pad_attr_25_we = addr_hit[281] & reg_we & !reg_error;
Tests: T1 T2 T3
34999
35000 1/1 assign mio_pad_attr_25_invert_25_wd = reg_wdata[0];
Tests: T1 T2 T3
35001
35002 1/1 assign mio_pad_attr_25_virtual_od_en_25_wd = reg_wdata[1];
Tests: T1 T2 T3
35003
35004 1/1 assign mio_pad_attr_25_pull_en_25_wd = reg_wdata[2];
Tests: T1 T2 T3
35005
35006 1/1 assign mio_pad_attr_25_pull_select_25_wd = reg_wdata[3];
Tests: T1 T2 T3
35007
35008 1/1 assign mio_pad_attr_25_keeper_en_25_wd = reg_wdata[4];
Tests: T1 T2 T3
35009
35010 1/1 assign mio_pad_attr_25_schmitt_en_25_wd = reg_wdata[5];
Tests: T1 T2 T3
35011
35012 1/1 assign mio_pad_attr_25_od_en_25_wd = reg_wdata[6];
Tests: T1 T2 T3
35013
35014 1/1 assign mio_pad_attr_25_input_disable_25_wd = reg_wdata[7];
Tests: T1 T2 T3
35015
35016 1/1 assign mio_pad_attr_25_slew_rate_25_wd = reg_wdata[17:16];
Tests: T1 T2 T3
35017
35018 1/1 assign mio_pad_attr_25_drive_strength_25_wd = reg_wdata[23:20];
Tests: T1 T2 T3
35019 1/1 assign mio_pad_attr_26_re = addr_hit[282] & reg_re & !reg_error;
Tests: T1 T2 T3
35020 1/1 assign mio_pad_attr_26_we = addr_hit[282] & reg_we & !reg_error;
Tests: T1 T2 T3
35021
35022 1/1 assign mio_pad_attr_26_invert_26_wd = reg_wdata[0];
Tests: T1 T2 T3
35023
35024 1/1 assign mio_pad_attr_26_virtual_od_en_26_wd = reg_wdata[1];
Tests: T1 T2 T3
35025
35026 1/1 assign mio_pad_attr_26_pull_en_26_wd = reg_wdata[2];
Tests: T1 T2 T3
35027
35028 1/1 assign mio_pad_attr_26_pull_select_26_wd = reg_wdata[3];
Tests: T1 T2 T3
35029
35030 1/1 assign mio_pad_attr_26_keeper_en_26_wd = reg_wdata[4];
Tests: T1 T2 T3
35031
35032 1/1 assign mio_pad_attr_26_schmitt_en_26_wd = reg_wdata[5];
Tests: T1 T2 T3
35033
35034 1/1 assign mio_pad_attr_26_od_en_26_wd = reg_wdata[6];
Tests: T1 T2 T3
35035
35036 1/1 assign mio_pad_attr_26_input_disable_26_wd = reg_wdata[7];
Tests: T1 T2 T3
35037
35038 1/1 assign mio_pad_attr_26_slew_rate_26_wd = reg_wdata[17:16];
Tests: T1 T2 T3
35039
35040 1/1 assign mio_pad_attr_26_drive_strength_26_wd = reg_wdata[23:20];
Tests: T1 T2 T3
35041 1/1 assign mio_pad_attr_27_re = addr_hit[283] & reg_re & !reg_error;
Tests: T1 T2 T3
35042 1/1 assign mio_pad_attr_27_we = addr_hit[283] & reg_we & !reg_error;
Tests: T1 T2 T3
35043
35044 1/1 assign mio_pad_attr_27_invert_27_wd = reg_wdata[0];
Tests: T1 T2 T3
35045
35046 1/1 assign mio_pad_attr_27_virtual_od_en_27_wd = reg_wdata[1];
Tests: T1 T2 T3
35047
35048 1/1 assign mio_pad_attr_27_pull_en_27_wd = reg_wdata[2];
Tests: T1 T2 T3
35049
35050 1/1 assign mio_pad_attr_27_pull_select_27_wd = reg_wdata[3];
Tests: T1 T2 T3
35051
35052 1/1 assign mio_pad_attr_27_keeper_en_27_wd = reg_wdata[4];
Tests: T1 T2 T3
35053
35054 1/1 assign mio_pad_attr_27_schmitt_en_27_wd = reg_wdata[5];
Tests: T1 T2 T3
35055
35056 1/1 assign mio_pad_attr_27_od_en_27_wd = reg_wdata[6];
Tests: T1 T2 T3
35057
35058 1/1 assign mio_pad_attr_27_input_disable_27_wd = reg_wdata[7];
Tests: T1 T2 T3
35059
35060 1/1 assign mio_pad_attr_27_slew_rate_27_wd = reg_wdata[17:16];
Tests: T1 T2 T3
35061
35062 1/1 assign mio_pad_attr_27_drive_strength_27_wd = reg_wdata[23:20];
Tests: T1 T2 T3
35063 1/1 assign mio_pad_attr_28_re = addr_hit[284] & reg_re & !reg_error;
Tests: T1 T2 T3
35064 1/1 assign mio_pad_attr_28_we = addr_hit[284] & reg_we & !reg_error;
Tests: T1 T2 T3
35065
35066 1/1 assign mio_pad_attr_28_invert_28_wd = reg_wdata[0];
Tests: T1 T2 T3
35067
35068 1/1 assign mio_pad_attr_28_virtual_od_en_28_wd = reg_wdata[1];
Tests: T1 T2 T3
35069
35070 1/1 assign mio_pad_attr_28_pull_en_28_wd = reg_wdata[2];
Tests: T1 T2 T3
35071
35072 1/1 assign mio_pad_attr_28_pull_select_28_wd = reg_wdata[3];
Tests: T1 T2 T3
35073
35074 1/1 assign mio_pad_attr_28_keeper_en_28_wd = reg_wdata[4];
Tests: T1 T2 T3
35075
35076 1/1 assign mio_pad_attr_28_schmitt_en_28_wd = reg_wdata[5];
Tests: T1 T2 T3
35077
35078 1/1 assign mio_pad_attr_28_od_en_28_wd = reg_wdata[6];
Tests: T1 T2 T3
35079
35080 1/1 assign mio_pad_attr_28_input_disable_28_wd = reg_wdata[7];
Tests: T1 T2 T3
35081
35082 1/1 assign mio_pad_attr_28_slew_rate_28_wd = reg_wdata[17:16];
Tests: T1 T2 T3
35083
35084 1/1 assign mio_pad_attr_28_drive_strength_28_wd = reg_wdata[23:20];
Tests: T1 T2 T3
35085 1/1 assign mio_pad_attr_29_re = addr_hit[285] & reg_re & !reg_error;
Tests: T1 T2 T3
35086 1/1 assign mio_pad_attr_29_we = addr_hit[285] & reg_we & !reg_error;
Tests: T1 T2 T3
35087
35088 1/1 assign mio_pad_attr_29_invert_29_wd = reg_wdata[0];
Tests: T1 T2 T3
35089
35090 1/1 assign mio_pad_attr_29_virtual_od_en_29_wd = reg_wdata[1];
Tests: T1 T2 T3
35091
35092 1/1 assign mio_pad_attr_29_pull_en_29_wd = reg_wdata[2];
Tests: T1 T2 T3
35093
35094 1/1 assign mio_pad_attr_29_pull_select_29_wd = reg_wdata[3];
Tests: T1 T2 T3
35095
35096 1/1 assign mio_pad_attr_29_keeper_en_29_wd = reg_wdata[4];
Tests: T1 T2 T3
35097
35098 1/1 assign mio_pad_attr_29_schmitt_en_29_wd = reg_wdata[5];
Tests: T1 T2 T3
35099
35100 1/1 assign mio_pad_attr_29_od_en_29_wd = reg_wdata[6];
Tests: T1 T2 T3
35101
35102 1/1 assign mio_pad_attr_29_input_disable_29_wd = reg_wdata[7];
Tests: T1 T2 T3
35103
35104 1/1 assign mio_pad_attr_29_slew_rate_29_wd = reg_wdata[17:16];
Tests: T1 T2 T3
35105
35106 1/1 assign mio_pad_attr_29_drive_strength_29_wd = reg_wdata[23:20];
Tests: T1 T2 T3
35107 1/1 assign mio_pad_attr_30_re = addr_hit[286] & reg_re & !reg_error;
Tests: T1 T2 T3
35108 1/1 assign mio_pad_attr_30_we = addr_hit[286] & reg_we & !reg_error;
Tests: T1 T2 T3
35109
35110 1/1 assign mio_pad_attr_30_invert_30_wd = reg_wdata[0];
Tests: T1 T2 T3
35111
35112 1/1 assign mio_pad_attr_30_virtual_od_en_30_wd = reg_wdata[1];
Tests: T1 T2 T3
35113
35114 1/1 assign mio_pad_attr_30_pull_en_30_wd = reg_wdata[2];
Tests: T1 T2 T3
35115
35116 1/1 assign mio_pad_attr_30_pull_select_30_wd = reg_wdata[3];
Tests: T1 T2 T3
35117
35118 1/1 assign mio_pad_attr_30_keeper_en_30_wd = reg_wdata[4];
Tests: T1 T2 T3
35119
35120 1/1 assign mio_pad_attr_30_schmitt_en_30_wd = reg_wdata[5];
Tests: T1 T2 T3
35121
35122 1/1 assign mio_pad_attr_30_od_en_30_wd = reg_wdata[6];
Tests: T1 T2 T3
35123
35124 1/1 assign mio_pad_attr_30_input_disable_30_wd = reg_wdata[7];
Tests: T1 T2 T3
35125
35126 1/1 assign mio_pad_attr_30_slew_rate_30_wd = reg_wdata[17:16];
Tests: T1 T2 T3
35127
35128 1/1 assign mio_pad_attr_30_drive_strength_30_wd = reg_wdata[23:20];
Tests: T1 T2 T3
35129 1/1 assign mio_pad_attr_31_re = addr_hit[287] & reg_re & !reg_error;
Tests: T1 T2 T3
35130 1/1 assign mio_pad_attr_31_we = addr_hit[287] & reg_we & !reg_error;
Tests: T1 T2 T3
35131
35132 1/1 assign mio_pad_attr_31_invert_31_wd = reg_wdata[0];
Tests: T1 T2 T3
35133
35134 1/1 assign mio_pad_attr_31_virtual_od_en_31_wd = reg_wdata[1];
Tests: T1 T2 T3
35135
35136 1/1 assign mio_pad_attr_31_pull_en_31_wd = reg_wdata[2];
Tests: T1 T2 T3
35137
35138 1/1 assign mio_pad_attr_31_pull_select_31_wd = reg_wdata[3];
Tests: T1 T2 T3
35139
35140 1/1 assign mio_pad_attr_31_keeper_en_31_wd = reg_wdata[4];
Tests: T1 T2 T3
35141
35142 1/1 assign mio_pad_attr_31_schmitt_en_31_wd = reg_wdata[5];
Tests: T1 T2 T3
35143
35144 1/1 assign mio_pad_attr_31_od_en_31_wd = reg_wdata[6];
Tests: T1 T2 T3
35145
35146 1/1 assign mio_pad_attr_31_input_disable_31_wd = reg_wdata[7];
Tests: T1 T2 T3
35147
35148 1/1 assign mio_pad_attr_31_slew_rate_31_wd = reg_wdata[17:16];
Tests: T1 T2 T3
35149
35150 1/1 assign mio_pad_attr_31_drive_strength_31_wd = reg_wdata[23:20];
Tests: T1 T2 T3
35151 1/1 assign mio_pad_attr_32_re = addr_hit[288] & reg_re & !reg_error;
Tests: T1 T2 T3
35152 1/1 assign mio_pad_attr_32_we = addr_hit[288] & reg_we & !reg_error;
Tests: T1 T2 T3
35153
35154 1/1 assign mio_pad_attr_32_invert_32_wd = reg_wdata[0];
Tests: T1 T2 T3
35155
35156 1/1 assign mio_pad_attr_32_virtual_od_en_32_wd = reg_wdata[1];
Tests: T1 T2 T3
35157
35158 1/1 assign mio_pad_attr_32_pull_en_32_wd = reg_wdata[2];
Tests: T1 T2 T3
35159
35160 1/1 assign mio_pad_attr_32_pull_select_32_wd = reg_wdata[3];
Tests: T1 T2 T3
35161
35162 1/1 assign mio_pad_attr_32_keeper_en_32_wd = reg_wdata[4];
Tests: T1 T2 T3
35163
35164 1/1 assign mio_pad_attr_32_schmitt_en_32_wd = reg_wdata[5];
Tests: T1 T2 T3
35165
35166 1/1 assign mio_pad_attr_32_od_en_32_wd = reg_wdata[6];
Tests: T1 T2 T3
35167
35168 1/1 assign mio_pad_attr_32_input_disable_32_wd = reg_wdata[7];
Tests: T1 T2 T3
35169
35170 1/1 assign mio_pad_attr_32_slew_rate_32_wd = reg_wdata[17:16];
Tests: T1 T2 T3
35171
35172 1/1 assign mio_pad_attr_32_drive_strength_32_wd = reg_wdata[23:20];
Tests: T1 T2 T3
35173 1/1 assign mio_pad_attr_33_re = addr_hit[289] & reg_re & !reg_error;
Tests: T1 T2 T3
35174 1/1 assign mio_pad_attr_33_we = addr_hit[289] & reg_we & !reg_error;
Tests: T1 T2 T3
35175
35176 1/1 assign mio_pad_attr_33_invert_33_wd = reg_wdata[0];
Tests: T1 T2 T3
35177
35178 1/1 assign mio_pad_attr_33_virtual_od_en_33_wd = reg_wdata[1];
Tests: T1 T2 T3
35179
35180 1/1 assign mio_pad_attr_33_pull_en_33_wd = reg_wdata[2];
Tests: T1 T2 T3
35181
35182 1/1 assign mio_pad_attr_33_pull_select_33_wd = reg_wdata[3];
Tests: T1 T2 T3
35183
35184 1/1 assign mio_pad_attr_33_keeper_en_33_wd = reg_wdata[4];
Tests: T1 T2 T3
35185
35186 1/1 assign mio_pad_attr_33_schmitt_en_33_wd = reg_wdata[5];
Tests: T1 T2 T3
35187
35188 1/1 assign mio_pad_attr_33_od_en_33_wd = reg_wdata[6];
Tests: T1 T2 T3
35189
35190 1/1 assign mio_pad_attr_33_input_disable_33_wd = reg_wdata[7];
Tests: T1 T2 T3
35191
35192 1/1 assign mio_pad_attr_33_slew_rate_33_wd = reg_wdata[17:16];
Tests: T1 T2 T3
35193
35194 1/1 assign mio_pad_attr_33_drive_strength_33_wd = reg_wdata[23:20];
Tests: T1 T2 T3
35195 1/1 assign mio_pad_attr_34_re = addr_hit[290] & reg_re & !reg_error;
Tests: T1 T2 T3
35196 1/1 assign mio_pad_attr_34_we = addr_hit[290] & reg_we & !reg_error;
Tests: T1 T2 T3
35197
35198 1/1 assign mio_pad_attr_34_invert_34_wd = reg_wdata[0];
Tests: T1 T2 T3
35199
35200 1/1 assign mio_pad_attr_34_virtual_od_en_34_wd = reg_wdata[1];
Tests: T1 T2 T3
35201
35202 1/1 assign mio_pad_attr_34_pull_en_34_wd = reg_wdata[2];
Tests: T1 T2 T3
35203
35204 1/1 assign mio_pad_attr_34_pull_select_34_wd = reg_wdata[3];
Tests: T1 T2 T3
35205
35206 1/1 assign mio_pad_attr_34_keeper_en_34_wd = reg_wdata[4];
Tests: T1 T2 T3
35207
35208 1/1 assign mio_pad_attr_34_schmitt_en_34_wd = reg_wdata[5];
Tests: T1 T2 T3
35209
35210 1/1 assign mio_pad_attr_34_od_en_34_wd = reg_wdata[6];
Tests: T1 T2 T3
35211
35212 1/1 assign mio_pad_attr_34_input_disable_34_wd = reg_wdata[7];
Tests: T1 T2 T3
35213
35214 1/1 assign mio_pad_attr_34_slew_rate_34_wd = reg_wdata[17:16];
Tests: T1 T2 T3
35215
35216 1/1 assign mio_pad_attr_34_drive_strength_34_wd = reg_wdata[23:20];
Tests: T1 T2 T3
35217 1/1 assign mio_pad_attr_35_re = addr_hit[291] & reg_re & !reg_error;
Tests: T1 T2 T3
35218 1/1 assign mio_pad_attr_35_we = addr_hit[291] & reg_we & !reg_error;
Tests: T1 T2 T3
35219
35220 1/1 assign mio_pad_attr_35_invert_35_wd = reg_wdata[0];
Tests: T1 T2 T3
35221
35222 1/1 assign mio_pad_attr_35_virtual_od_en_35_wd = reg_wdata[1];
Tests: T1 T2 T3
35223
35224 1/1 assign mio_pad_attr_35_pull_en_35_wd = reg_wdata[2];
Tests: T1 T2 T3
35225
35226 1/1 assign mio_pad_attr_35_pull_select_35_wd = reg_wdata[3];
Tests: T1 T2 T3
35227
35228 1/1 assign mio_pad_attr_35_keeper_en_35_wd = reg_wdata[4];
Tests: T1 T2 T3
35229
35230 1/1 assign mio_pad_attr_35_schmitt_en_35_wd = reg_wdata[5];
Tests: T1 T2 T3
35231
35232 1/1 assign mio_pad_attr_35_od_en_35_wd = reg_wdata[6];
Tests: T1 T2 T3
35233
35234 1/1 assign mio_pad_attr_35_input_disable_35_wd = reg_wdata[7];
Tests: T1 T2 T3
35235
35236 1/1 assign mio_pad_attr_35_slew_rate_35_wd = reg_wdata[17:16];
Tests: T1 T2 T3
35237
35238 1/1 assign mio_pad_attr_35_drive_strength_35_wd = reg_wdata[23:20];
Tests: T1 T2 T3
35239 1/1 assign mio_pad_attr_36_re = addr_hit[292] & reg_re & !reg_error;
Tests: T1 T2 T3
35240 1/1 assign mio_pad_attr_36_we = addr_hit[292] & reg_we & !reg_error;
Tests: T1 T2 T3
35241
35242 1/1 assign mio_pad_attr_36_invert_36_wd = reg_wdata[0];
Tests: T1 T2 T3
35243
35244 1/1 assign mio_pad_attr_36_virtual_od_en_36_wd = reg_wdata[1];
Tests: T1 T2 T3
35245
35246 1/1 assign mio_pad_attr_36_pull_en_36_wd = reg_wdata[2];
Tests: T1 T2 T3
35247
35248 1/1 assign mio_pad_attr_36_pull_select_36_wd = reg_wdata[3];
Tests: T1 T2 T3
35249
35250 1/1 assign mio_pad_attr_36_keeper_en_36_wd = reg_wdata[4];
Tests: T1 T2 T3
35251
35252 1/1 assign mio_pad_attr_36_schmitt_en_36_wd = reg_wdata[5];
Tests: T1 T2 T3
35253
35254 1/1 assign mio_pad_attr_36_od_en_36_wd = reg_wdata[6];
Tests: T1 T2 T3
35255
35256 1/1 assign mio_pad_attr_36_input_disable_36_wd = reg_wdata[7];
Tests: T1 T2 T3
35257
35258 1/1 assign mio_pad_attr_36_slew_rate_36_wd = reg_wdata[17:16];
Tests: T1 T2 T3
35259
35260 1/1 assign mio_pad_attr_36_drive_strength_36_wd = reg_wdata[23:20];
Tests: T1 T2 T3
35261 1/1 assign mio_pad_attr_37_re = addr_hit[293] & reg_re & !reg_error;
Tests: T1 T2 T3
35262 1/1 assign mio_pad_attr_37_we = addr_hit[293] & reg_we & !reg_error;
Tests: T1 T2 T3
35263
35264 1/1 assign mio_pad_attr_37_invert_37_wd = reg_wdata[0];
Tests: T1 T2 T3
35265
35266 1/1 assign mio_pad_attr_37_virtual_od_en_37_wd = reg_wdata[1];
Tests: T1 T2 T3
35267
35268 1/1 assign mio_pad_attr_37_pull_en_37_wd = reg_wdata[2];
Tests: T1 T2 T3
35269
35270 1/1 assign mio_pad_attr_37_pull_select_37_wd = reg_wdata[3];
Tests: T1 T2 T3
35271
35272 1/1 assign mio_pad_attr_37_keeper_en_37_wd = reg_wdata[4];
Tests: T1 T2 T3
35273
35274 1/1 assign mio_pad_attr_37_schmitt_en_37_wd = reg_wdata[5];
Tests: T1 T2 T3
35275
35276 1/1 assign mio_pad_attr_37_od_en_37_wd = reg_wdata[6];
Tests: T1 T2 T3
35277
35278 1/1 assign mio_pad_attr_37_input_disable_37_wd = reg_wdata[7];
Tests: T1 T2 T3
35279
35280 1/1 assign mio_pad_attr_37_slew_rate_37_wd = reg_wdata[17:16];
Tests: T1 T2 T3
35281
35282 1/1 assign mio_pad_attr_37_drive_strength_37_wd = reg_wdata[23:20];
Tests: T1 T2 T3
35283 1/1 assign mio_pad_attr_38_re = addr_hit[294] & reg_re & !reg_error;
Tests: T1 T2 T3
35284 1/1 assign mio_pad_attr_38_we = addr_hit[294] & reg_we & !reg_error;
Tests: T1 T2 T3
35285
35286 1/1 assign mio_pad_attr_38_invert_38_wd = reg_wdata[0];
Tests: T1 T2 T3
35287
35288 1/1 assign mio_pad_attr_38_virtual_od_en_38_wd = reg_wdata[1];
Tests: T1 T2 T3
35289
35290 1/1 assign mio_pad_attr_38_pull_en_38_wd = reg_wdata[2];
Tests: T1 T2 T3
35291
35292 1/1 assign mio_pad_attr_38_pull_select_38_wd = reg_wdata[3];
Tests: T1 T2 T3
35293
35294 1/1 assign mio_pad_attr_38_keeper_en_38_wd = reg_wdata[4];
Tests: T1 T2 T3
35295
35296 1/1 assign mio_pad_attr_38_schmitt_en_38_wd = reg_wdata[5];
Tests: T1 T2 T3
35297
35298 1/1 assign mio_pad_attr_38_od_en_38_wd = reg_wdata[6];
Tests: T1 T2 T3
35299
35300 1/1 assign mio_pad_attr_38_input_disable_38_wd = reg_wdata[7];
Tests: T1 T2 T3
35301
35302 1/1 assign mio_pad_attr_38_slew_rate_38_wd = reg_wdata[17:16];
Tests: T1 T2 T3
35303
35304 1/1 assign mio_pad_attr_38_drive_strength_38_wd = reg_wdata[23:20];
Tests: T1 T2 T3
35305 1/1 assign mio_pad_attr_39_re = addr_hit[295] & reg_re & !reg_error;
Tests: T1 T2 T3
35306 1/1 assign mio_pad_attr_39_we = addr_hit[295] & reg_we & !reg_error;
Tests: T1 T2 T3
35307
35308 1/1 assign mio_pad_attr_39_invert_39_wd = reg_wdata[0];
Tests: T1 T2 T3
35309
35310 1/1 assign mio_pad_attr_39_virtual_od_en_39_wd = reg_wdata[1];
Tests: T1 T2 T3
35311
35312 1/1 assign mio_pad_attr_39_pull_en_39_wd = reg_wdata[2];
Tests: T1 T2 T3
35313
35314 1/1 assign mio_pad_attr_39_pull_select_39_wd = reg_wdata[3];
Tests: T1 T2 T3
35315
35316 1/1 assign mio_pad_attr_39_keeper_en_39_wd = reg_wdata[4];
Tests: T1 T2 T3
35317
35318 1/1 assign mio_pad_attr_39_schmitt_en_39_wd = reg_wdata[5];
Tests: T1 T2 T3
35319
35320 1/1 assign mio_pad_attr_39_od_en_39_wd = reg_wdata[6];
Tests: T1 T2 T3
35321
35322 1/1 assign mio_pad_attr_39_input_disable_39_wd = reg_wdata[7];
Tests: T1 T2 T3
35323
35324 1/1 assign mio_pad_attr_39_slew_rate_39_wd = reg_wdata[17:16];
Tests: T1 T2 T3
35325
35326 1/1 assign mio_pad_attr_39_drive_strength_39_wd = reg_wdata[23:20];
Tests: T1 T2 T3
35327 1/1 assign mio_pad_attr_40_re = addr_hit[296] & reg_re & !reg_error;
Tests: T1 T2 T3
35328 1/1 assign mio_pad_attr_40_we = addr_hit[296] & reg_we & !reg_error;
Tests: T1 T2 T3
35329
35330 1/1 assign mio_pad_attr_40_invert_40_wd = reg_wdata[0];
Tests: T1 T2 T3
35331
35332 1/1 assign mio_pad_attr_40_virtual_od_en_40_wd = reg_wdata[1];
Tests: T1 T2 T3
35333
35334 1/1 assign mio_pad_attr_40_pull_en_40_wd = reg_wdata[2];
Tests: T1 T2 T3
35335
35336 1/1 assign mio_pad_attr_40_pull_select_40_wd = reg_wdata[3];
Tests: T1 T2 T3
35337
35338 1/1 assign mio_pad_attr_40_keeper_en_40_wd = reg_wdata[4];
Tests: T1 T2 T3
35339
35340 1/1 assign mio_pad_attr_40_schmitt_en_40_wd = reg_wdata[5];
Tests: T1 T2 T3
35341
35342 1/1 assign mio_pad_attr_40_od_en_40_wd = reg_wdata[6];
Tests: T1 T2 T3
35343
35344 1/1 assign mio_pad_attr_40_input_disable_40_wd = reg_wdata[7];
Tests: T1 T2 T3
35345
35346 1/1 assign mio_pad_attr_40_slew_rate_40_wd = reg_wdata[17:16];
Tests: T1 T2 T3
35347
35348 1/1 assign mio_pad_attr_40_drive_strength_40_wd = reg_wdata[23:20];
Tests: T1 T2 T3
35349 1/1 assign mio_pad_attr_41_re = addr_hit[297] & reg_re & !reg_error;
Tests: T1 T2 T3
35350 1/1 assign mio_pad_attr_41_we = addr_hit[297] & reg_we & !reg_error;
Tests: T1 T2 T3
35351
35352 1/1 assign mio_pad_attr_41_invert_41_wd = reg_wdata[0];
Tests: T1 T2 T3
35353
35354 1/1 assign mio_pad_attr_41_virtual_od_en_41_wd = reg_wdata[1];
Tests: T1 T2 T3
35355
35356 1/1 assign mio_pad_attr_41_pull_en_41_wd = reg_wdata[2];
Tests: T1 T2 T3
35357
35358 1/1 assign mio_pad_attr_41_pull_select_41_wd = reg_wdata[3];
Tests: T1 T2 T3
35359
35360 1/1 assign mio_pad_attr_41_keeper_en_41_wd = reg_wdata[4];
Tests: T1 T2 T3
35361
35362 1/1 assign mio_pad_attr_41_schmitt_en_41_wd = reg_wdata[5];
Tests: T1 T2 T3
35363
35364 1/1 assign mio_pad_attr_41_od_en_41_wd = reg_wdata[6];
Tests: T1 T2 T3
35365
35366 1/1 assign mio_pad_attr_41_input_disable_41_wd = reg_wdata[7];
Tests: T1 T2 T3
35367
35368 1/1 assign mio_pad_attr_41_slew_rate_41_wd = reg_wdata[17:16];
Tests: T1 T2 T3
35369
35370 1/1 assign mio_pad_attr_41_drive_strength_41_wd = reg_wdata[23:20];
Tests: T1 T2 T3
35371 1/1 assign mio_pad_attr_42_re = addr_hit[298] & reg_re & !reg_error;
Tests: T1 T2 T3
35372 1/1 assign mio_pad_attr_42_we = addr_hit[298] & reg_we & !reg_error;
Tests: T1 T2 T3
35373
35374 1/1 assign mio_pad_attr_42_invert_42_wd = reg_wdata[0];
Tests: T1 T2 T3
35375
35376 1/1 assign mio_pad_attr_42_virtual_od_en_42_wd = reg_wdata[1];
Tests: T1 T2 T3
35377
35378 1/1 assign mio_pad_attr_42_pull_en_42_wd = reg_wdata[2];
Tests: T1 T2 T3
35379
35380 1/1 assign mio_pad_attr_42_pull_select_42_wd = reg_wdata[3];
Tests: T1 T2 T3
35381
35382 1/1 assign mio_pad_attr_42_keeper_en_42_wd = reg_wdata[4];
Tests: T1 T2 T3
35383
35384 1/1 assign mio_pad_attr_42_schmitt_en_42_wd = reg_wdata[5];
Tests: T1 T2 T3
35385
35386 1/1 assign mio_pad_attr_42_od_en_42_wd = reg_wdata[6];
Tests: T1 T2 T3
35387
35388 1/1 assign mio_pad_attr_42_input_disable_42_wd = reg_wdata[7];
Tests: T1 T2 T3
35389
35390 1/1 assign mio_pad_attr_42_slew_rate_42_wd = reg_wdata[17:16];
Tests: T1 T2 T3
35391
35392 1/1 assign mio_pad_attr_42_drive_strength_42_wd = reg_wdata[23:20];
Tests: T1 T2 T3
35393 1/1 assign mio_pad_attr_43_re = addr_hit[299] & reg_re & !reg_error;
Tests: T1 T2 T3
35394 1/1 assign mio_pad_attr_43_we = addr_hit[299] & reg_we & !reg_error;
Tests: T1 T2 T3
35395
35396 1/1 assign mio_pad_attr_43_invert_43_wd = reg_wdata[0];
Tests: T1 T2 T3
35397
35398 1/1 assign mio_pad_attr_43_virtual_od_en_43_wd = reg_wdata[1];
Tests: T1 T2 T3
35399
35400 1/1 assign mio_pad_attr_43_pull_en_43_wd = reg_wdata[2];
Tests: T1 T2 T3
35401
35402 1/1 assign mio_pad_attr_43_pull_select_43_wd = reg_wdata[3];
Tests: T1 T2 T3
35403
35404 1/1 assign mio_pad_attr_43_keeper_en_43_wd = reg_wdata[4];
Tests: T1 T2 T3
35405
35406 1/1 assign mio_pad_attr_43_schmitt_en_43_wd = reg_wdata[5];
Tests: T1 T2 T3
35407
35408 1/1 assign mio_pad_attr_43_od_en_43_wd = reg_wdata[6];
Tests: T1 T2 T3
35409
35410 1/1 assign mio_pad_attr_43_input_disable_43_wd = reg_wdata[7];
Tests: T1 T2 T3
35411
35412 1/1 assign mio_pad_attr_43_slew_rate_43_wd = reg_wdata[17:16];
Tests: T1 T2 T3
35413
35414 1/1 assign mio_pad_attr_43_drive_strength_43_wd = reg_wdata[23:20];
Tests: T1 T2 T3
35415 1/1 assign mio_pad_attr_44_re = addr_hit[300] & reg_re & !reg_error;
Tests: T1 T2 T3
35416 1/1 assign mio_pad_attr_44_we = addr_hit[300] & reg_we & !reg_error;
Tests: T1 T2 T3
35417
35418 1/1 assign mio_pad_attr_44_invert_44_wd = reg_wdata[0];
Tests: T1 T2 T3
35419
35420 1/1 assign mio_pad_attr_44_virtual_od_en_44_wd = reg_wdata[1];
Tests: T1 T2 T3
35421
35422 1/1 assign mio_pad_attr_44_pull_en_44_wd = reg_wdata[2];
Tests: T1 T2 T3
35423
35424 1/1 assign mio_pad_attr_44_pull_select_44_wd = reg_wdata[3];
Tests: T1 T2 T3
35425
35426 1/1 assign mio_pad_attr_44_keeper_en_44_wd = reg_wdata[4];
Tests: T1 T2 T3
35427
35428 1/1 assign mio_pad_attr_44_schmitt_en_44_wd = reg_wdata[5];
Tests: T1 T2 T3
35429
35430 1/1 assign mio_pad_attr_44_od_en_44_wd = reg_wdata[6];
Tests: T1 T2 T3
35431
35432 1/1 assign mio_pad_attr_44_input_disable_44_wd = reg_wdata[7];
Tests: T1 T2 T3
35433
35434 1/1 assign mio_pad_attr_44_slew_rate_44_wd = reg_wdata[17:16];
Tests: T1 T2 T3
35435
35436 1/1 assign mio_pad_attr_44_drive_strength_44_wd = reg_wdata[23:20];
Tests: T1 T2 T3
35437 1/1 assign mio_pad_attr_45_re = addr_hit[301] & reg_re & !reg_error;
Tests: T1 T2 T3
35438 1/1 assign mio_pad_attr_45_we = addr_hit[301] & reg_we & !reg_error;
Tests: T1 T2 T3
35439
35440 1/1 assign mio_pad_attr_45_invert_45_wd = reg_wdata[0];
Tests: T1 T2 T3
35441
35442 1/1 assign mio_pad_attr_45_virtual_od_en_45_wd = reg_wdata[1];
Tests: T1 T2 T3
35443
35444 1/1 assign mio_pad_attr_45_pull_en_45_wd = reg_wdata[2];
Tests: T1 T2 T3
35445
35446 1/1 assign mio_pad_attr_45_pull_select_45_wd = reg_wdata[3];
Tests: T1 T2 T3
35447
35448 1/1 assign mio_pad_attr_45_keeper_en_45_wd = reg_wdata[4];
Tests: T1 T2 T3
35449
35450 1/1 assign mio_pad_attr_45_schmitt_en_45_wd = reg_wdata[5];
Tests: T1 T2 T3
35451
35452 1/1 assign mio_pad_attr_45_od_en_45_wd = reg_wdata[6];
Tests: T1 T2 T3
35453
35454 1/1 assign mio_pad_attr_45_input_disable_45_wd = reg_wdata[7];
Tests: T1 T2 T3
35455
35456 1/1 assign mio_pad_attr_45_slew_rate_45_wd = reg_wdata[17:16];
Tests: T1 T2 T3
35457
35458 1/1 assign mio_pad_attr_45_drive_strength_45_wd = reg_wdata[23:20];
Tests: T1 T2 T3
35459 1/1 assign mio_pad_attr_46_re = addr_hit[302] & reg_re & !reg_error;
Tests: T1 T2 T3
35460 1/1 assign mio_pad_attr_46_we = addr_hit[302] & reg_we & !reg_error;
Tests: T1 T2 T3
35461
35462 1/1 assign mio_pad_attr_46_invert_46_wd = reg_wdata[0];
Tests: T1 T2 T3
35463
35464 1/1 assign mio_pad_attr_46_virtual_od_en_46_wd = reg_wdata[1];
Tests: T1 T2 T3
35465
35466 1/1 assign mio_pad_attr_46_pull_en_46_wd = reg_wdata[2];
Tests: T1 T2 T3
35467
35468 1/1 assign mio_pad_attr_46_pull_select_46_wd = reg_wdata[3];
Tests: T1 T2 T3
35469
35470 1/1 assign mio_pad_attr_46_keeper_en_46_wd = reg_wdata[4];
Tests: T1 T2 T3
35471
35472 1/1 assign mio_pad_attr_46_schmitt_en_46_wd = reg_wdata[5];
Tests: T1 T2 T3
35473
35474 1/1 assign mio_pad_attr_46_od_en_46_wd = reg_wdata[6];
Tests: T1 T2 T3
35475
35476 1/1 assign mio_pad_attr_46_input_disable_46_wd = reg_wdata[7];
Tests: T1 T2 T3
35477
35478 1/1 assign mio_pad_attr_46_slew_rate_46_wd = reg_wdata[17:16];
Tests: T1 T2 T3
35479
35480 1/1 assign mio_pad_attr_46_drive_strength_46_wd = reg_wdata[23:20];
Tests: T1 T2 T3
35481 1/1 assign dio_pad_attr_regwen_0_we = addr_hit[303] & reg_we & !reg_error;
Tests: T1 T2 T3
35482
35483 1/1 assign dio_pad_attr_regwen_0_wd = reg_wdata[0];
Tests: T1 T2 T3
35484 1/1 assign dio_pad_attr_regwen_1_we = addr_hit[304] & reg_we & !reg_error;
Tests: T1 T2 T3
35485
35486 1/1 assign dio_pad_attr_regwen_1_wd = reg_wdata[0];
Tests: T1 T2 T3
35487 1/1 assign dio_pad_attr_regwen_2_we = addr_hit[305] & reg_we & !reg_error;
Tests: T1 T2 T3
35488
35489 1/1 assign dio_pad_attr_regwen_2_wd = reg_wdata[0];
Tests: T1 T2 T3
35490 1/1 assign dio_pad_attr_regwen_3_we = addr_hit[306] & reg_we & !reg_error;
Tests: T1 T2 T3
35491
35492 1/1 assign dio_pad_attr_regwen_3_wd = reg_wdata[0];
Tests: T1 T2 T3
35493 1/1 assign dio_pad_attr_regwen_4_we = addr_hit[307] & reg_we & !reg_error;
Tests: T1 T2 T3
35494
35495 1/1 assign dio_pad_attr_regwen_4_wd = reg_wdata[0];
Tests: T1 T2 T3
35496 1/1 assign dio_pad_attr_regwen_5_we = addr_hit[308] & reg_we & !reg_error;
Tests: T1 T2 T3
35497
35498 1/1 assign dio_pad_attr_regwen_5_wd = reg_wdata[0];
Tests: T1 T2 T3
35499 1/1 assign dio_pad_attr_regwen_6_we = addr_hit[309] & reg_we & !reg_error;
Tests: T1 T2 T3
35500
35501 1/1 assign dio_pad_attr_regwen_6_wd = reg_wdata[0];
Tests: T1 T2 T3
35502 1/1 assign dio_pad_attr_regwen_7_we = addr_hit[310] & reg_we & !reg_error;
Tests: T1 T2 T3
35503
35504 1/1 assign dio_pad_attr_regwen_7_wd = reg_wdata[0];
Tests: T1 T2 T3
35505 1/1 assign dio_pad_attr_regwen_8_we = addr_hit[311] & reg_we & !reg_error;
Tests: T1 T2 T3
35506
35507 1/1 assign dio_pad_attr_regwen_8_wd = reg_wdata[0];
Tests: T1 T2 T3
35508 1/1 assign dio_pad_attr_regwen_9_we = addr_hit[312] & reg_we & !reg_error;
Tests: T1 T2 T3
35509
35510 1/1 assign dio_pad_attr_regwen_9_wd = reg_wdata[0];
Tests: T1 T2 T3
35511 1/1 assign dio_pad_attr_regwen_10_we = addr_hit[313] & reg_we & !reg_error;
Tests: T1 T2 T3
35512
35513 1/1 assign dio_pad_attr_regwen_10_wd = reg_wdata[0];
Tests: T1 T2 T3
35514 1/1 assign dio_pad_attr_regwen_11_we = addr_hit[314] & reg_we & !reg_error;
Tests: T1 T2 T3
35515
35516 1/1 assign dio_pad_attr_regwen_11_wd = reg_wdata[0];
Tests: T1 T2 T3
35517 1/1 assign dio_pad_attr_regwen_12_we = addr_hit[315] & reg_we & !reg_error;
Tests: T1 T2 T3
35518
35519 1/1 assign dio_pad_attr_regwen_12_wd = reg_wdata[0];
Tests: T1 T2 T3
35520 1/1 assign dio_pad_attr_regwen_13_we = addr_hit[316] & reg_we & !reg_error;
Tests: T1 T2 T3
35521
35522 1/1 assign dio_pad_attr_regwen_13_wd = reg_wdata[0];
Tests: T1 T2 T3
35523 1/1 assign dio_pad_attr_regwen_14_we = addr_hit[317] & reg_we & !reg_error;
Tests: T1 T2 T3
35524
35525 1/1 assign dio_pad_attr_regwen_14_wd = reg_wdata[0];
Tests: T1 T2 T3
35526 1/1 assign dio_pad_attr_regwen_15_we = addr_hit[318] & reg_we & !reg_error;
Tests: T1 T2 T3
35527
35528 1/1 assign dio_pad_attr_regwen_15_wd = reg_wdata[0];
Tests: T1 T2 T3
35529 1/1 assign dio_pad_attr_0_re = addr_hit[319] & reg_re & !reg_error;
Tests: T1 T2 T3
35530 1/1 assign dio_pad_attr_0_we = addr_hit[319] & reg_we & !reg_error;
Tests: T1 T2 T3
35531
35532 1/1 assign dio_pad_attr_0_invert_0_wd = reg_wdata[0];
Tests: T1 T2 T3
35533
35534 1/1 assign dio_pad_attr_0_virtual_od_en_0_wd = reg_wdata[1];
Tests: T1 T2 T3
35535
35536 1/1 assign dio_pad_attr_0_pull_en_0_wd = reg_wdata[2];
Tests: T1 T2 T3
35537
35538 1/1 assign dio_pad_attr_0_pull_select_0_wd = reg_wdata[3];
Tests: T1 T2 T3
35539
35540 1/1 assign dio_pad_attr_0_keeper_en_0_wd = reg_wdata[4];
Tests: T1 T2 T3
35541
35542 1/1 assign dio_pad_attr_0_schmitt_en_0_wd = reg_wdata[5];
Tests: T1 T2 T3
35543
35544 1/1 assign dio_pad_attr_0_od_en_0_wd = reg_wdata[6];
Tests: T1 T2 T3
35545
35546 1/1 assign dio_pad_attr_0_input_disable_0_wd = reg_wdata[7];
Tests: T1 T2 T3
35547
35548 1/1 assign dio_pad_attr_0_slew_rate_0_wd = reg_wdata[17:16];
Tests: T1 T2 T3
35549
35550 1/1 assign dio_pad_attr_0_drive_strength_0_wd = reg_wdata[23:20];
Tests: T1 T2 T3
35551 1/1 assign dio_pad_attr_1_re = addr_hit[320] & reg_re & !reg_error;
Tests: T1 T2 T3
35552 1/1 assign dio_pad_attr_1_we = addr_hit[320] & reg_we & !reg_error;
Tests: T1 T2 T3
35553
35554 1/1 assign dio_pad_attr_1_invert_1_wd = reg_wdata[0];
Tests: T1 T2 T3
35555
35556 1/1 assign dio_pad_attr_1_virtual_od_en_1_wd = reg_wdata[1];
Tests: T1 T2 T3
35557
35558 1/1 assign dio_pad_attr_1_pull_en_1_wd = reg_wdata[2];
Tests: T1 T2 T3
35559
35560 1/1 assign dio_pad_attr_1_pull_select_1_wd = reg_wdata[3];
Tests: T1 T2 T3
35561
35562 1/1 assign dio_pad_attr_1_keeper_en_1_wd = reg_wdata[4];
Tests: T1 T2 T3
35563
35564 1/1 assign dio_pad_attr_1_schmitt_en_1_wd = reg_wdata[5];
Tests: T1 T2 T3
35565
35566 1/1 assign dio_pad_attr_1_od_en_1_wd = reg_wdata[6];
Tests: T1 T2 T3
35567
35568 1/1 assign dio_pad_attr_1_input_disable_1_wd = reg_wdata[7];
Tests: T1 T2 T3
35569
35570 1/1 assign dio_pad_attr_1_slew_rate_1_wd = reg_wdata[17:16];
Tests: T1 T2 T3
35571
35572 1/1 assign dio_pad_attr_1_drive_strength_1_wd = reg_wdata[23:20];
Tests: T1 T2 T3
35573 1/1 assign dio_pad_attr_2_re = addr_hit[321] & reg_re & !reg_error;
Tests: T1 T2 T3
35574 1/1 assign dio_pad_attr_2_we = addr_hit[321] & reg_we & !reg_error;
Tests: T1 T2 T3
35575
35576 1/1 assign dio_pad_attr_2_invert_2_wd = reg_wdata[0];
Tests: T1 T2 T3
35577
35578 1/1 assign dio_pad_attr_2_virtual_od_en_2_wd = reg_wdata[1];
Tests: T1 T2 T3
35579
35580 1/1 assign dio_pad_attr_2_pull_en_2_wd = reg_wdata[2];
Tests: T1 T2 T3
35581
35582 1/1 assign dio_pad_attr_2_pull_select_2_wd = reg_wdata[3];
Tests: T1 T2 T3
35583
35584 1/1 assign dio_pad_attr_2_keeper_en_2_wd = reg_wdata[4];
Tests: T1 T2 T3
35585
35586 1/1 assign dio_pad_attr_2_schmitt_en_2_wd = reg_wdata[5];
Tests: T1 T2 T3
35587
35588 1/1 assign dio_pad_attr_2_od_en_2_wd = reg_wdata[6];
Tests: T1 T2 T3
35589
35590 1/1 assign dio_pad_attr_2_input_disable_2_wd = reg_wdata[7];
Tests: T1 T2 T3
35591
35592 1/1 assign dio_pad_attr_2_slew_rate_2_wd = reg_wdata[17:16];
Tests: T1 T2 T3
35593
35594 1/1 assign dio_pad_attr_2_drive_strength_2_wd = reg_wdata[23:20];
Tests: T1 T2 T3
35595 1/1 assign dio_pad_attr_3_re = addr_hit[322] & reg_re & !reg_error;
Tests: T1 T2 T3
35596 1/1 assign dio_pad_attr_3_we = addr_hit[322] & reg_we & !reg_error;
Tests: T1 T2 T3
35597
35598 1/1 assign dio_pad_attr_3_invert_3_wd = reg_wdata[0];
Tests: T1 T2 T3
35599
35600 1/1 assign dio_pad_attr_3_virtual_od_en_3_wd = reg_wdata[1];
Tests: T1 T2 T3
35601
35602 1/1 assign dio_pad_attr_3_pull_en_3_wd = reg_wdata[2];
Tests: T1 T2 T3
35603
35604 1/1 assign dio_pad_attr_3_pull_select_3_wd = reg_wdata[3];
Tests: T1 T2 T3
35605
35606 1/1 assign dio_pad_attr_3_keeper_en_3_wd = reg_wdata[4];
Tests: T1 T2 T3
35607
35608 1/1 assign dio_pad_attr_3_schmitt_en_3_wd = reg_wdata[5];
Tests: T1 T2 T3
35609
35610 1/1 assign dio_pad_attr_3_od_en_3_wd = reg_wdata[6];
Tests: T1 T2 T3
35611
35612 1/1 assign dio_pad_attr_3_input_disable_3_wd = reg_wdata[7];
Tests: T1 T2 T3
35613
35614 1/1 assign dio_pad_attr_3_slew_rate_3_wd = reg_wdata[17:16];
Tests: T1 T2 T3
35615
35616 1/1 assign dio_pad_attr_3_drive_strength_3_wd = reg_wdata[23:20];
Tests: T1 T2 T3
35617 1/1 assign dio_pad_attr_4_re = addr_hit[323] & reg_re & !reg_error;
Tests: T1 T2 T3
35618 1/1 assign dio_pad_attr_4_we = addr_hit[323] & reg_we & !reg_error;
Tests: T1 T2 T3
35619
35620 1/1 assign dio_pad_attr_4_invert_4_wd = reg_wdata[0];
Tests: T1 T2 T3
35621
35622 1/1 assign dio_pad_attr_4_virtual_od_en_4_wd = reg_wdata[1];
Tests: T1 T2 T3
35623
35624 1/1 assign dio_pad_attr_4_pull_en_4_wd = reg_wdata[2];
Tests: T1 T2 T3
35625
35626 1/1 assign dio_pad_attr_4_pull_select_4_wd = reg_wdata[3];
Tests: T1 T2 T3
35627
35628 1/1 assign dio_pad_attr_4_keeper_en_4_wd = reg_wdata[4];
Tests: T1 T2 T3
35629
35630 1/1 assign dio_pad_attr_4_schmitt_en_4_wd = reg_wdata[5];
Tests: T1 T2 T3
35631
35632 1/1 assign dio_pad_attr_4_od_en_4_wd = reg_wdata[6];
Tests: T1 T2 T3
35633
35634 1/1 assign dio_pad_attr_4_input_disable_4_wd = reg_wdata[7];
Tests: T1 T2 T3
35635
35636 1/1 assign dio_pad_attr_4_slew_rate_4_wd = reg_wdata[17:16];
Tests: T1 T2 T3
35637
35638 1/1 assign dio_pad_attr_4_drive_strength_4_wd = reg_wdata[23:20];
Tests: T1 T2 T3
35639 1/1 assign dio_pad_attr_5_re = addr_hit[324] & reg_re & !reg_error;
Tests: T1 T2 T3
35640 1/1 assign dio_pad_attr_5_we = addr_hit[324] & reg_we & !reg_error;
Tests: T1 T2 T3
35641
35642 1/1 assign dio_pad_attr_5_invert_5_wd = reg_wdata[0];
Tests: T1 T2 T3
35643
35644 1/1 assign dio_pad_attr_5_virtual_od_en_5_wd = reg_wdata[1];
Tests: T1 T2 T3
35645
35646 1/1 assign dio_pad_attr_5_pull_en_5_wd = reg_wdata[2];
Tests: T1 T2 T3
35647
35648 1/1 assign dio_pad_attr_5_pull_select_5_wd = reg_wdata[3];
Tests: T1 T2 T3
35649
35650 1/1 assign dio_pad_attr_5_keeper_en_5_wd = reg_wdata[4];
Tests: T1 T2 T3
35651
35652 1/1 assign dio_pad_attr_5_schmitt_en_5_wd = reg_wdata[5];
Tests: T1 T2 T3
35653
35654 1/1 assign dio_pad_attr_5_od_en_5_wd = reg_wdata[6];
Tests: T1 T2 T3
35655
35656 1/1 assign dio_pad_attr_5_input_disable_5_wd = reg_wdata[7];
Tests: T1 T2 T3
35657
35658 1/1 assign dio_pad_attr_5_slew_rate_5_wd = reg_wdata[17:16];
Tests: T1 T2 T3
35659
35660 1/1 assign dio_pad_attr_5_drive_strength_5_wd = reg_wdata[23:20];
Tests: T1 T2 T3
35661 1/1 assign dio_pad_attr_6_re = addr_hit[325] & reg_re & !reg_error;
Tests: T1 T2 T3
35662 1/1 assign dio_pad_attr_6_we = addr_hit[325] & reg_we & !reg_error;
Tests: T1 T2 T3
35663
35664 1/1 assign dio_pad_attr_6_invert_6_wd = reg_wdata[0];
Tests: T1 T2 T3
35665
35666 1/1 assign dio_pad_attr_6_virtual_od_en_6_wd = reg_wdata[1];
Tests: T1 T2 T3
35667
35668 1/1 assign dio_pad_attr_6_pull_en_6_wd = reg_wdata[2];
Tests: T1 T2 T3
35669
35670 1/1 assign dio_pad_attr_6_pull_select_6_wd = reg_wdata[3];
Tests: T1 T2 T3
35671
35672 1/1 assign dio_pad_attr_6_keeper_en_6_wd = reg_wdata[4];
Tests: T1 T2 T3
35673
35674 1/1 assign dio_pad_attr_6_schmitt_en_6_wd = reg_wdata[5];
Tests: T1 T2 T3
35675
35676 1/1 assign dio_pad_attr_6_od_en_6_wd = reg_wdata[6];
Tests: T1 T2 T3
35677
35678 1/1 assign dio_pad_attr_6_input_disable_6_wd = reg_wdata[7];
Tests: T1 T2 T3
35679
35680 1/1 assign dio_pad_attr_6_slew_rate_6_wd = reg_wdata[17:16];
Tests: T1 T2 T3
35681
35682 1/1 assign dio_pad_attr_6_drive_strength_6_wd = reg_wdata[23:20];
Tests: T1 T2 T3
35683 1/1 assign dio_pad_attr_7_re = addr_hit[326] & reg_re & !reg_error;
Tests: T1 T2 T3
35684 1/1 assign dio_pad_attr_7_we = addr_hit[326] & reg_we & !reg_error;
Tests: T1 T2 T3
35685
35686 1/1 assign dio_pad_attr_7_invert_7_wd = reg_wdata[0];
Tests: T1 T2 T3
35687
35688 1/1 assign dio_pad_attr_7_virtual_od_en_7_wd = reg_wdata[1];
Tests: T1 T2 T3
35689
35690 1/1 assign dio_pad_attr_7_pull_en_7_wd = reg_wdata[2];
Tests: T1 T2 T3
35691
35692 1/1 assign dio_pad_attr_7_pull_select_7_wd = reg_wdata[3];
Tests: T1 T2 T3
35693
35694 1/1 assign dio_pad_attr_7_keeper_en_7_wd = reg_wdata[4];
Tests: T1 T2 T3
35695
35696 1/1 assign dio_pad_attr_7_schmitt_en_7_wd = reg_wdata[5];
Tests: T1 T2 T3
35697
35698 1/1 assign dio_pad_attr_7_od_en_7_wd = reg_wdata[6];
Tests: T1 T2 T3
35699
35700 1/1 assign dio_pad_attr_7_input_disable_7_wd = reg_wdata[7];
Tests: T1 T2 T3
35701
35702 1/1 assign dio_pad_attr_7_slew_rate_7_wd = reg_wdata[17:16];
Tests: T1 T2 T3
35703
35704 1/1 assign dio_pad_attr_7_drive_strength_7_wd = reg_wdata[23:20];
Tests: T1 T2 T3
35705 1/1 assign dio_pad_attr_8_re = addr_hit[327] & reg_re & !reg_error;
Tests: T1 T2 T3
35706 1/1 assign dio_pad_attr_8_we = addr_hit[327] & reg_we & !reg_error;
Tests: T1 T2 T3
35707
35708 1/1 assign dio_pad_attr_8_invert_8_wd = reg_wdata[0];
Tests: T1 T2 T3
35709
35710 1/1 assign dio_pad_attr_8_virtual_od_en_8_wd = reg_wdata[1];
Tests: T1 T2 T3
35711
35712 1/1 assign dio_pad_attr_8_pull_en_8_wd = reg_wdata[2];
Tests: T1 T2 T3
35713
35714 1/1 assign dio_pad_attr_8_pull_select_8_wd = reg_wdata[3];
Tests: T1 T2 T3
35715
35716 1/1 assign dio_pad_attr_8_keeper_en_8_wd = reg_wdata[4];
Tests: T1 T2 T3
35717
35718 1/1 assign dio_pad_attr_8_schmitt_en_8_wd = reg_wdata[5];
Tests: T1 T2 T3
35719
35720 1/1 assign dio_pad_attr_8_od_en_8_wd = reg_wdata[6];
Tests: T1 T2 T3
35721
35722 1/1 assign dio_pad_attr_8_input_disable_8_wd = reg_wdata[7];
Tests: T1 T2 T3
35723
35724 1/1 assign dio_pad_attr_8_slew_rate_8_wd = reg_wdata[17:16];
Tests: T1 T2 T3
35725
35726 1/1 assign dio_pad_attr_8_drive_strength_8_wd = reg_wdata[23:20];
Tests: T1 T2 T3
35727 1/1 assign dio_pad_attr_9_re = addr_hit[328] & reg_re & !reg_error;
Tests: T1 T2 T3
35728 1/1 assign dio_pad_attr_9_we = addr_hit[328] & reg_we & !reg_error;
Tests: T1 T2 T3
35729
35730 1/1 assign dio_pad_attr_9_invert_9_wd = reg_wdata[0];
Tests: T1 T2 T3
35731
35732 1/1 assign dio_pad_attr_9_virtual_od_en_9_wd = reg_wdata[1];
Tests: T1 T2 T3
35733
35734 1/1 assign dio_pad_attr_9_pull_en_9_wd = reg_wdata[2];
Tests: T1 T2 T3
35735
35736 1/1 assign dio_pad_attr_9_pull_select_9_wd = reg_wdata[3];
Tests: T1 T2 T3
35737
35738 1/1 assign dio_pad_attr_9_keeper_en_9_wd = reg_wdata[4];
Tests: T1 T2 T3
35739
35740 1/1 assign dio_pad_attr_9_schmitt_en_9_wd = reg_wdata[5];
Tests: T1 T2 T3
35741
35742 1/1 assign dio_pad_attr_9_od_en_9_wd = reg_wdata[6];
Tests: T1 T2 T3
35743
35744 1/1 assign dio_pad_attr_9_input_disable_9_wd = reg_wdata[7];
Tests: T1 T2 T3
35745
35746 1/1 assign dio_pad_attr_9_slew_rate_9_wd = reg_wdata[17:16];
Tests: T1 T2 T3
35747
35748 1/1 assign dio_pad_attr_9_drive_strength_9_wd = reg_wdata[23:20];
Tests: T1 T2 T3
35749 1/1 assign dio_pad_attr_10_re = addr_hit[329] & reg_re & !reg_error;
Tests: T1 T2 T3
35750 1/1 assign dio_pad_attr_10_we = addr_hit[329] & reg_we & !reg_error;
Tests: T1 T2 T3
35751
35752 1/1 assign dio_pad_attr_10_invert_10_wd = reg_wdata[0];
Tests: T1 T2 T3
35753
35754 1/1 assign dio_pad_attr_10_virtual_od_en_10_wd = reg_wdata[1];
Tests: T1 T2 T3
35755
35756 1/1 assign dio_pad_attr_10_pull_en_10_wd = reg_wdata[2];
Tests: T1 T2 T3
35757
35758 1/1 assign dio_pad_attr_10_pull_select_10_wd = reg_wdata[3];
Tests: T1 T2 T3
35759
35760 1/1 assign dio_pad_attr_10_keeper_en_10_wd = reg_wdata[4];
Tests: T1 T2 T3
35761
35762 1/1 assign dio_pad_attr_10_schmitt_en_10_wd = reg_wdata[5];
Tests: T1 T2 T3
35763
35764 1/1 assign dio_pad_attr_10_od_en_10_wd = reg_wdata[6];
Tests: T1 T2 T3
35765
35766 1/1 assign dio_pad_attr_10_input_disable_10_wd = reg_wdata[7];
Tests: T1 T2 T3
35767
35768 1/1 assign dio_pad_attr_10_slew_rate_10_wd = reg_wdata[17:16];
Tests: T1 T2 T3
35769
35770 1/1 assign dio_pad_attr_10_drive_strength_10_wd = reg_wdata[23:20];
Tests: T1 T2 T3
35771 1/1 assign dio_pad_attr_11_re = addr_hit[330] & reg_re & !reg_error;
Tests: T1 T2 T3
35772 1/1 assign dio_pad_attr_11_we = addr_hit[330] & reg_we & !reg_error;
Tests: T1 T2 T3
35773
35774 1/1 assign dio_pad_attr_11_invert_11_wd = reg_wdata[0];
Tests: T1 T2 T3
35775
35776 1/1 assign dio_pad_attr_11_virtual_od_en_11_wd = reg_wdata[1];
Tests: T1 T2 T3
35777
35778 1/1 assign dio_pad_attr_11_pull_en_11_wd = reg_wdata[2];
Tests: T1 T2 T3
35779
35780 1/1 assign dio_pad_attr_11_pull_select_11_wd = reg_wdata[3];
Tests: T1 T2 T3
35781
35782 1/1 assign dio_pad_attr_11_keeper_en_11_wd = reg_wdata[4];
Tests: T1 T2 T3
35783
35784 1/1 assign dio_pad_attr_11_schmitt_en_11_wd = reg_wdata[5];
Tests: T1 T2 T3
35785
35786 1/1 assign dio_pad_attr_11_od_en_11_wd = reg_wdata[6];
Tests: T1 T2 T3
35787
35788 1/1 assign dio_pad_attr_11_input_disable_11_wd = reg_wdata[7];
Tests: T1 T2 T3
35789
35790 1/1 assign dio_pad_attr_11_slew_rate_11_wd = reg_wdata[17:16];
Tests: T1 T2 T3
35791
35792 1/1 assign dio_pad_attr_11_drive_strength_11_wd = reg_wdata[23:20];
Tests: T1 T2 T3
35793 1/1 assign dio_pad_attr_12_re = addr_hit[331] & reg_re & !reg_error;
Tests: T1 T2 T3
35794 1/1 assign dio_pad_attr_12_we = addr_hit[331] & reg_we & !reg_error;
Tests: T1 T2 T3
35795
35796 1/1 assign dio_pad_attr_12_invert_12_wd = reg_wdata[0];
Tests: T1 T2 T3
35797
35798 1/1 assign dio_pad_attr_12_virtual_od_en_12_wd = reg_wdata[1];
Tests: T1 T2 T3
35799
35800 1/1 assign dio_pad_attr_12_pull_en_12_wd = reg_wdata[2];
Tests: T1 T2 T3
35801
35802 1/1 assign dio_pad_attr_12_pull_select_12_wd = reg_wdata[3];
Tests: T1 T2 T3
35803
35804 1/1 assign dio_pad_attr_12_keeper_en_12_wd = reg_wdata[4];
Tests: T1 T2 T3
35805
35806 1/1 assign dio_pad_attr_12_schmitt_en_12_wd = reg_wdata[5];
Tests: T1 T2 T3
35807
35808 1/1 assign dio_pad_attr_12_od_en_12_wd = reg_wdata[6];
Tests: T1 T2 T3
35809
35810 1/1 assign dio_pad_attr_12_input_disable_12_wd = reg_wdata[7];
Tests: T1 T2 T3
35811
35812 1/1 assign dio_pad_attr_12_slew_rate_12_wd = reg_wdata[17:16];
Tests: T1 T2 T3
35813
35814 1/1 assign dio_pad_attr_12_drive_strength_12_wd = reg_wdata[23:20];
Tests: T1 T2 T3
35815 1/1 assign dio_pad_attr_13_re = addr_hit[332] & reg_re & !reg_error;
Tests: T1 T2 T3
35816 1/1 assign dio_pad_attr_13_we = addr_hit[332] & reg_we & !reg_error;
Tests: T1 T2 T3
35817
35818 1/1 assign dio_pad_attr_13_invert_13_wd = reg_wdata[0];
Tests: T1 T2 T3
35819
35820 1/1 assign dio_pad_attr_13_virtual_od_en_13_wd = reg_wdata[1];
Tests: T1 T2 T3
35821
35822 1/1 assign dio_pad_attr_13_pull_en_13_wd = reg_wdata[2];
Tests: T1 T2 T3
35823
35824 1/1 assign dio_pad_attr_13_pull_select_13_wd = reg_wdata[3];
Tests: T1 T2 T3
35825
35826 1/1 assign dio_pad_attr_13_keeper_en_13_wd = reg_wdata[4];
Tests: T1 T2 T3
35827
35828 1/1 assign dio_pad_attr_13_schmitt_en_13_wd = reg_wdata[5];
Tests: T1 T2 T3
35829
35830 1/1 assign dio_pad_attr_13_od_en_13_wd = reg_wdata[6];
Tests: T1 T2 T3
35831
35832 1/1 assign dio_pad_attr_13_input_disable_13_wd = reg_wdata[7];
Tests: T1 T2 T3
35833
35834 1/1 assign dio_pad_attr_13_slew_rate_13_wd = reg_wdata[17:16];
Tests: T1 T2 T3
35835
35836 1/1 assign dio_pad_attr_13_drive_strength_13_wd = reg_wdata[23:20];
Tests: T1 T2 T3
35837 1/1 assign dio_pad_attr_14_re = addr_hit[333] & reg_re & !reg_error;
Tests: T1 T2 T3
35838 1/1 assign dio_pad_attr_14_we = addr_hit[333] & reg_we & !reg_error;
Tests: T1 T2 T3
35839
35840 1/1 assign dio_pad_attr_14_invert_14_wd = reg_wdata[0];
Tests: T1 T2 T3
35841
35842 1/1 assign dio_pad_attr_14_virtual_od_en_14_wd = reg_wdata[1];
Tests: T1 T2 T3
35843
35844 1/1 assign dio_pad_attr_14_pull_en_14_wd = reg_wdata[2];
Tests: T1 T2 T3
35845
35846 1/1 assign dio_pad_attr_14_pull_select_14_wd = reg_wdata[3];
Tests: T1 T2 T3
35847
35848 1/1 assign dio_pad_attr_14_keeper_en_14_wd = reg_wdata[4];
Tests: T1 T2 T3
35849
35850 1/1 assign dio_pad_attr_14_schmitt_en_14_wd = reg_wdata[5];
Tests: T1 T2 T3
35851
35852 1/1 assign dio_pad_attr_14_od_en_14_wd = reg_wdata[6];
Tests: T1 T2 T3
35853
35854 1/1 assign dio_pad_attr_14_input_disable_14_wd = reg_wdata[7];
Tests: T1 T2 T3
35855
35856 1/1 assign dio_pad_attr_14_slew_rate_14_wd = reg_wdata[17:16];
Tests: T1 T2 T3
35857
35858 1/1 assign dio_pad_attr_14_drive_strength_14_wd = reg_wdata[23:20];
Tests: T1 T2 T3
35859 1/1 assign dio_pad_attr_15_re = addr_hit[334] & reg_re & !reg_error;
Tests: T1 T2 T3
35860 1/1 assign dio_pad_attr_15_we = addr_hit[334] & reg_we & !reg_error;
Tests: T1 T2 T3
35861
35862 1/1 assign dio_pad_attr_15_invert_15_wd = reg_wdata[0];
Tests: T1 T2 T3
35863
35864 1/1 assign dio_pad_attr_15_virtual_od_en_15_wd = reg_wdata[1];
Tests: T1 T2 T3
35865
35866 1/1 assign dio_pad_attr_15_pull_en_15_wd = reg_wdata[2];
Tests: T1 T2 T3
35867
35868 1/1 assign dio_pad_attr_15_pull_select_15_wd = reg_wdata[3];
Tests: T1 T2 T3
35869
35870 1/1 assign dio_pad_attr_15_keeper_en_15_wd = reg_wdata[4];
Tests: T1 T2 T3
35871
35872 1/1 assign dio_pad_attr_15_schmitt_en_15_wd = reg_wdata[5];
Tests: T1 T2 T3
35873
35874 1/1 assign dio_pad_attr_15_od_en_15_wd = reg_wdata[6];
Tests: T1 T2 T3
35875
35876 1/1 assign dio_pad_attr_15_input_disable_15_wd = reg_wdata[7];
Tests: T1 T2 T3
35877
35878 1/1 assign dio_pad_attr_15_slew_rate_15_wd = reg_wdata[17:16];
Tests: T1 T2 T3
35879
35880 1/1 assign dio_pad_attr_15_drive_strength_15_wd = reg_wdata[23:20];
Tests: T1 T2 T3
35881 1/1 assign mio_pad_sleep_status_0_we = addr_hit[335] & reg_we & !reg_error;
Tests: T1 T2 T3
35882
35883 1/1 assign mio_pad_sleep_status_0_en_0_wd = reg_wdata[0];
Tests: T1 T2 T3
35884
35885 1/1 assign mio_pad_sleep_status_0_en_1_wd = reg_wdata[1];
Tests: T1 T2 T3
35886
35887 1/1 assign mio_pad_sleep_status_0_en_2_wd = reg_wdata[2];
Tests: T1 T2 T3
35888
35889 1/1 assign mio_pad_sleep_status_0_en_3_wd = reg_wdata[3];
Tests: T1 T2 T3
35890
35891 1/1 assign mio_pad_sleep_status_0_en_4_wd = reg_wdata[4];
Tests: T1 T2 T3
35892
35893 1/1 assign mio_pad_sleep_status_0_en_5_wd = reg_wdata[5];
Tests: T1 T2 T3
35894
35895 1/1 assign mio_pad_sleep_status_0_en_6_wd = reg_wdata[6];
Tests: T1 T2 T3
35896
35897 1/1 assign mio_pad_sleep_status_0_en_7_wd = reg_wdata[7];
Tests: T1 T2 T3
35898
35899 1/1 assign mio_pad_sleep_status_0_en_8_wd = reg_wdata[8];
Tests: T1 T2 T3
35900
35901 1/1 assign mio_pad_sleep_status_0_en_9_wd = reg_wdata[9];
Tests: T1 T2 T3
35902
35903 1/1 assign mio_pad_sleep_status_0_en_10_wd = reg_wdata[10];
Tests: T1 T2 T3
35904
35905 1/1 assign mio_pad_sleep_status_0_en_11_wd = reg_wdata[11];
Tests: T1 T2 T3
35906
35907 1/1 assign mio_pad_sleep_status_0_en_12_wd = reg_wdata[12];
Tests: T1 T2 T3
35908
35909 1/1 assign mio_pad_sleep_status_0_en_13_wd = reg_wdata[13];
Tests: T1 T2 T3
35910
35911 1/1 assign mio_pad_sleep_status_0_en_14_wd = reg_wdata[14];
Tests: T1 T2 T3
35912
35913 1/1 assign mio_pad_sleep_status_0_en_15_wd = reg_wdata[15];
Tests: T1 T2 T3
35914
35915 1/1 assign mio_pad_sleep_status_0_en_16_wd = reg_wdata[16];
Tests: T1 T2 T3
35916
35917 1/1 assign mio_pad_sleep_status_0_en_17_wd = reg_wdata[17];
Tests: T1 T2 T3
35918
35919 1/1 assign mio_pad_sleep_status_0_en_18_wd = reg_wdata[18];
Tests: T1 T2 T3
35920
35921 1/1 assign mio_pad_sleep_status_0_en_19_wd = reg_wdata[19];
Tests: T1 T2 T3
35922
35923 1/1 assign mio_pad_sleep_status_0_en_20_wd = reg_wdata[20];
Tests: T1 T2 T3
35924
35925 1/1 assign mio_pad_sleep_status_0_en_21_wd = reg_wdata[21];
Tests: T1 T2 T3
35926
35927 1/1 assign mio_pad_sleep_status_0_en_22_wd = reg_wdata[22];
Tests: T1 T2 T3
35928
35929 1/1 assign mio_pad_sleep_status_0_en_23_wd = reg_wdata[23];
Tests: T1 T2 T3
35930
35931 1/1 assign mio_pad_sleep_status_0_en_24_wd = reg_wdata[24];
Tests: T1 T2 T3
35932
35933 1/1 assign mio_pad_sleep_status_0_en_25_wd = reg_wdata[25];
Tests: T1 T2 T3
35934
35935 1/1 assign mio_pad_sleep_status_0_en_26_wd = reg_wdata[26];
Tests: T1 T2 T3
35936
35937 1/1 assign mio_pad_sleep_status_0_en_27_wd = reg_wdata[27];
Tests: T1 T2 T3
35938
35939 1/1 assign mio_pad_sleep_status_0_en_28_wd = reg_wdata[28];
Tests: T1 T2 T3
35940
35941 1/1 assign mio_pad_sleep_status_0_en_29_wd = reg_wdata[29];
Tests: T1 T2 T3
35942
35943 1/1 assign mio_pad_sleep_status_0_en_30_wd = reg_wdata[30];
Tests: T1 T2 T3
35944
35945 1/1 assign mio_pad_sleep_status_0_en_31_wd = reg_wdata[31];
Tests: T1 T2 T3
35946 1/1 assign mio_pad_sleep_status_1_we = addr_hit[336] & reg_we & !reg_error;
Tests: T1 T2 T3
35947
35948 1/1 assign mio_pad_sleep_status_1_en_32_wd = reg_wdata[0];
Tests: T1 T2 T3
35949
35950 1/1 assign mio_pad_sleep_status_1_en_33_wd = reg_wdata[1];
Tests: T1 T2 T3
35951
35952 1/1 assign mio_pad_sleep_status_1_en_34_wd = reg_wdata[2];
Tests: T1 T2 T3
35953
35954 1/1 assign mio_pad_sleep_status_1_en_35_wd = reg_wdata[3];
Tests: T1 T2 T3
35955
35956 1/1 assign mio_pad_sleep_status_1_en_36_wd = reg_wdata[4];
Tests: T1 T2 T3
35957
35958 1/1 assign mio_pad_sleep_status_1_en_37_wd = reg_wdata[5];
Tests: T1 T2 T3
35959
35960 1/1 assign mio_pad_sleep_status_1_en_38_wd = reg_wdata[6];
Tests: T1 T2 T3
35961
35962 1/1 assign mio_pad_sleep_status_1_en_39_wd = reg_wdata[7];
Tests: T1 T2 T3
35963
35964 1/1 assign mio_pad_sleep_status_1_en_40_wd = reg_wdata[8];
Tests: T1 T2 T3
35965
35966 1/1 assign mio_pad_sleep_status_1_en_41_wd = reg_wdata[9];
Tests: T1 T2 T3
35967
35968 1/1 assign mio_pad_sleep_status_1_en_42_wd = reg_wdata[10];
Tests: T1 T2 T3
35969
35970 1/1 assign mio_pad_sleep_status_1_en_43_wd = reg_wdata[11];
Tests: T1 T2 T3
35971
35972 1/1 assign mio_pad_sleep_status_1_en_44_wd = reg_wdata[12];
Tests: T1 T2 T3
35973
35974 1/1 assign mio_pad_sleep_status_1_en_45_wd = reg_wdata[13];
Tests: T1 T2 T3
35975
35976 1/1 assign mio_pad_sleep_status_1_en_46_wd = reg_wdata[14];
Tests: T1 T2 T3
35977 1/1 assign mio_pad_sleep_regwen_0_we = addr_hit[337] & reg_we & !reg_error;
Tests: T1 T2 T3
35978
35979 1/1 assign mio_pad_sleep_regwen_0_wd = reg_wdata[0];
Tests: T1 T2 T3
35980 1/1 assign mio_pad_sleep_regwen_1_we = addr_hit[338] & reg_we & !reg_error;
Tests: T1 T2 T3
35981
35982 1/1 assign mio_pad_sleep_regwen_1_wd = reg_wdata[0];
Tests: T1 T2 T3
35983 1/1 assign mio_pad_sleep_regwen_2_we = addr_hit[339] & reg_we & !reg_error;
Tests: T1 T2 T3
35984
35985 1/1 assign mio_pad_sleep_regwen_2_wd = reg_wdata[0];
Tests: T1 T2 T3
35986 1/1 assign mio_pad_sleep_regwen_3_we = addr_hit[340] & reg_we & !reg_error;
Tests: T1 T2 T3
35987
35988 1/1 assign mio_pad_sleep_regwen_3_wd = reg_wdata[0];
Tests: T1 T2 T3
35989 1/1 assign mio_pad_sleep_regwen_4_we = addr_hit[341] & reg_we & !reg_error;
Tests: T1 T2 T3
35990
35991 1/1 assign mio_pad_sleep_regwen_4_wd = reg_wdata[0];
Tests: T1 T2 T3
35992 1/1 assign mio_pad_sleep_regwen_5_we = addr_hit[342] & reg_we & !reg_error;
Tests: T1 T2 T3
35993
35994 1/1 assign mio_pad_sleep_regwen_5_wd = reg_wdata[0];
Tests: T1 T2 T3
35995 1/1 assign mio_pad_sleep_regwen_6_we = addr_hit[343] & reg_we & !reg_error;
Tests: T1 T2 T3
35996
35997 1/1 assign mio_pad_sleep_regwen_6_wd = reg_wdata[0];
Tests: T1 T2 T3
35998 1/1 assign mio_pad_sleep_regwen_7_we = addr_hit[344] & reg_we & !reg_error;
Tests: T1 T2 T3
35999
36000 1/1 assign mio_pad_sleep_regwen_7_wd = reg_wdata[0];
Tests: T1 T2 T3
36001 1/1 assign mio_pad_sleep_regwen_8_we = addr_hit[345] & reg_we & !reg_error;
Tests: T1 T2 T3
36002
36003 1/1 assign mio_pad_sleep_regwen_8_wd = reg_wdata[0];
Tests: T1 T2 T3
36004 1/1 assign mio_pad_sleep_regwen_9_we = addr_hit[346] & reg_we & !reg_error;
Tests: T1 T2 T3
36005
36006 1/1 assign mio_pad_sleep_regwen_9_wd = reg_wdata[0];
Tests: T1 T2 T3
36007 1/1 assign mio_pad_sleep_regwen_10_we = addr_hit[347] & reg_we & !reg_error;
Tests: T1 T2 T3
36008
36009 1/1 assign mio_pad_sleep_regwen_10_wd = reg_wdata[0];
Tests: T1 T2 T3
36010 1/1 assign mio_pad_sleep_regwen_11_we = addr_hit[348] & reg_we & !reg_error;
Tests: T1 T2 T3
36011
36012 1/1 assign mio_pad_sleep_regwen_11_wd = reg_wdata[0];
Tests: T1 T2 T3
36013 1/1 assign mio_pad_sleep_regwen_12_we = addr_hit[349] & reg_we & !reg_error;
Tests: T1 T2 T3
36014
36015 1/1 assign mio_pad_sleep_regwen_12_wd = reg_wdata[0];
Tests: T1 T2 T3
36016 1/1 assign mio_pad_sleep_regwen_13_we = addr_hit[350] & reg_we & !reg_error;
Tests: T1 T2 T3
36017
36018 1/1 assign mio_pad_sleep_regwen_13_wd = reg_wdata[0];
Tests: T1 T2 T3
36019 1/1 assign mio_pad_sleep_regwen_14_we = addr_hit[351] & reg_we & !reg_error;
Tests: T1 T2 T3
36020
36021 1/1 assign mio_pad_sleep_regwen_14_wd = reg_wdata[0];
Tests: T1 T2 T3
36022 1/1 assign mio_pad_sleep_regwen_15_we = addr_hit[352] & reg_we & !reg_error;
Tests: T1 T2 T3
36023
36024 1/1 assign mio_pad_sleep_regwen_15_wd = reg_wdata[0];
Tests: T1 T2 T3
36025 1/1 assign mio_pad_sleep_regwen_16_we = addr_hit[353] & reg_we & !reg_error;
Tests: T1 T2 T3
36026
36027 1/1 assign mio_pad_sleep_regwen_16_wd = reg_wdata[0];
Tests: T1 T2 T3
36028 1/1 assign mio_pad_sleep_regwen_17_we = addr_hit[354] & reg_we & !reg_error;
Tests: T1 T2 T3
36029
36030 1/1 assign mio_pad_sleep_regwen_17_wd = reg_wdata[0];
Tests: T1 T2 T3
36031 1/1 assign mio_pad_sleep_regwen_18_we = addr_hit[355] & reg_we & !reg_error;
Tests: T1 T2 T3
36032
36033 1/1 assign mio_pad_sleep_regwen_18_wd = reg_wdata[0];
Tests: T1 T2 T3
36034 1/1 assign mio_pad_sleep_regwen_19_we = addr_hit[356] & reg_we & !reg_error;
Tests: T1 T2 T3
36035
36036 1/1 assign mio_pad_sleep_regwen_19_wd = reg_wdata[0];
Tests: T1 T2 T3
36037 1/1 assign mio_pad_sleep_regwen_20_we = addr_hit[357] & reg_we & !reg_error;
Tests: T1 T2 T3
36038
36039 1/1 assign mio_pad_sleep_regwen_20_wd = reg_wdata[0];
Tests: T1 T2 T3
36040 1/1 assign mio_pad_sleep_regwen_21_we = addr_hit[358] & reg_we & !reg_error;
Tests: T1 T2 T3
36041
36042 1/1 assign mio_pad_sleep_regwen_21_wd = reg_wdata[0];
Tests: T1 T2 T3
36043 1/1 assign mio_pad_sleep_regwen_22_we = addr_hit[359] & reg_we & !reg_error;
Tests: T1 T2 T3
36044
36045 1/1 assign mio_pad_sleep_regwen_22_wd = reg_wdata[0];
Tests: T1 T2 T3
36046 1/1 assign mio_pad_sleep_regwen_23_we = addr_hit[360] & reg_we & !reg_error;
Tests: T1 T2 T3
36047
36048 1/1 assign mio_pad_sleep_regwen_23_wd = reg_wdata[0];
Tests: T1 T2 T3
36049 1/1 assign mio_pad_sleep_regwen_24_we = addr_hit[361] & reg_we & !reg_error;
Tests: T1 T2 T3
36050
36051 1/1 assign mio_pad_sleep_regwen_24_wd = reg_wdata[0];
Tests: T1 T2 T3
36052 1/1 assign mio_pad_sleep_regwen_25_we = addr_hit[362] & reg_we & !reg_error;
Tests: T1 T2 T3
36053
36054 1/1 assign mio_pad_sleep_regwen_25_wd = reg_wdata[0];
Tests: T1 T2 T3
36055 1/1 assign mio_pad_sleep_regwen_26_we = addr_hit[363] & reg_we & !reg_error;
Tests: T1 T2 T3
36056
36057 1/1 assign mio_pad_sleep_regwen_26_wd = reg_wdata[0];
Tests: T1 T2 T3
36058 1/1 assign mio_pad_sleep_regwen_27_we = addr_hit[364] & reg_we & !reg_error;
Tests: T1 T2 T3
36059
36060 1/1 assign mio_pad_sleep_regwen_27_wd = reg_wdata[0];
Tests: T1 T2 T3
36061 1/1 assign mio_pad_sleep_regwen_28_we = addr_hit[365] & reg_we & !reg_error;
Tests: T1 T2 T3
36062
36063 1/1 assign mio_pad_sleep_regwen_28_wd = reg_wdata[0];
Tests: T1 T2 T3
36064 1/1 assign mio_pad_sleep_regwen_29_we = addr_hit[366] & reg_we & !reg_error;
Tests: T1 T2 T3
36065
36066 1/1 assign mio_pad_sleep_regwen_29_wd = reg_wdata[0];
Tests: T1 T2 T3
36067 1/1 assign mio_pad_sleep_regwen_30_we = addr_hit[367] & reg_we & !reg_error;
Tests: T1 T2 T3
36068
36069 1/1 assign mio_pad_sleep_regwen_30_wd = reg_wdata[0];
Tests: T1 T2 T3
36070 1/1 assign mio_pad_sleep_regwen_31_we = addr_hit[368] & reg_we & !reg_error;
Tests: T1 T2 T3
36071
36072 1/1 assign mio_pad_sleep_regwen_31_wd = reg_wdata[0];
Tests: T1 T2 T3
36073 1/1 assign mio_pad_sleep_regwen_32_we = addr_hit[369] & reg_we & !reg_error;
Tests: T1 T2 T3
36074
36075 1/1 assign mio_pad_sleep_regwen_32_wd = reg_wdata[0];
Tests: T1 T2 T3
36076 1/1 assign mio_pad_sleep_regwen_33_we = addr_hit[370] & reg_we & !reg_error;
Tests: T1 T2 T3
36077
36078 1/1 assign mio_pad_sleep_regwen_33_wd = reg_wdata[0];
Tests: T1 T2 T3
36079 1/1 assign mio_pad_sleep_regwen_34_we = addr_hit[371] & reg_we & !reg_error;
Tests: T1 T2 T3
36080
36081 1/1 assign mio_pad_sleep_regwen_34_wd = reg_wdata[0];
Tests: T1 T2 T3
36082 1/1 assign mio_pad_sleep_regwen_35_we = addr_hit[372] & reg_we & !reg_error;
Tests: T1 T2 T3
36083
36084 1/1 assign mio_pad_sleep_regwen_35_wd = reg_wdata[0];
Tests: T1 T2 T3
36085 1/1 assign mio_pad_sleep_regwen_36_we = addr_hit[373] & reg_we & !reg_error;
Tests: T1 T2 T3
36086
36087 1/1 assign mio_pad_sleep_regwen_36_wd = reg_wdata[0];
Tests: T1 T2 T3
36088 1/1 assign mio_pad_sleep_regwen_37_we = addr_hit[374] & reg_we & !reg_error;
Tests: T1 T2 T3
36089
36090 1/1 assign mio_pad_sleep_regwen_37_wd = reg_wdata[0];
Tests: T1 T2 T3
36091 1/1 assign mio_pad_sleep_regwen_38_we = addr_hit[375] & reg_we & !reg_error;
Tests: T1 T2 T3
36092
36093 1/1 assign mio_pad_sleep_regwen_38_wd = reg_wdata[0];
Tests: T1 T2 T3
36094 1/1 assign mio_pad_sleep_regwen_39_we = addr_hit[376] & reg_we & !reg_error;
Tests: T1 T2 T3
36095
36096 1/1 assign mio_pad_sleep_regwen_39_wd = reg_wdata[0];
Tests: T1 T2 T3
36097 1/1 assign mio_pad_sleep_regwen_40_we = addr_hit[377] & reg_we & !reg_error;
Tests: T1 T2 T3
36098
36099 1/1 assign mio_pad_sleep_regwen_40_wd = reg_wdata[0];
Tests: T1 T2 T3
36100 1/1 assign mio_pad_sleep_regwen_41_we = addr_hit[378] & reg_we & !reg_error;
Tests: T1 T2 T3
36101
36102 1/1 assign mio_pad_sleep_regwen_41_wd = reg_wdata[0];
Tests: T1 T2 T3
36103 1/1 assign mio_pad_sleep_regwen_42_we = addr_hit[379] & reg_we & !reg_error;
Tests: T1 T2 T3
36104
36105 1/1 assign mio_pad_sleep_regwen_42_wd = reg_wdata[0];
Tests: T1 T2 T3
36106 1/1 assign mio_pad_sleep_regwen_43_we = addr_hit[380] & reg_we & !reg_error;
Tests: T1 T2 T3
36107
36108 1/1 assign mio_pad_sleep_regwen_43_wd = reg_wdata[0];
Tests: T1 T2 T3
36109 1/1 assign mio_pad_sleep_regwen_44_we = addr_hit[381] & reg_we & !reg_error;
Tests: T1 T2 T3
36110
36111 1/1 assign mio_pad_sleep_regwen_44_wd = reg_wdata[0];
Tests: T1 T2 T3
36112 1/1 assign mio_pad_sleep_regwen_45_we = addr_hit[382] & reg_we & !reg_error;
Tests: T1 T2 T3
36113
36114 1/1 assign mio_pad_sleep_regwen_45_wd = reg_wdata[0];
Tests: T1 T2 T3
36115 1/1 assign mio_pad_sleep_regwen_46_we = addr_hit[383] & reg_we & !reg_error;
Tests: T1 T2 T3
36116
36117 1/1 assign mio_pad_sleep_regwen_46_wd = reg_wdata[0];
Tests: T1 T2 T3
36118 1/1 assign mio_pad_sleep_en_0_we = addr_hit[384] & reg_we & !reg_error;
Tests: T1 T2 T3
36119
36120 1/1 assign mio_pad_sleep_en_0_wd = reg_wdata[0];
Tests: T1 T2 T3
36121 1/1 assign mio_pad_sleep_en_1_we = addr_hit[385] & reg_we & !reg_error;
Tests: T1 T2 T3
36122
36123 1/1 assign mio_pad_sleep_en_1_wd = reg_wdata[0];
Tests: T1 T2 T3
36124 1/1 assign mio_pad_sleep_en_2_we = addr_hit[386] & reg_we & !reg_error;
Tests: T1 T2 T3
36125
36126 1/1 assign mio_pad_sleep_en_2_wd = reg_wdata[0];
Tests: T1 T2 T3
36127 1/1 assign mio_pad_sleep_en_3_we = addr_hit[387] & reg_we & !reg_error;
Tests: T1 T2 T3
36128
36129 1/1 assign mio_pad_sleep_en_3_wd = reg_wdata[0];
Tests: T1 T2 T3
36130 1/1 assign mio_pad_sleep_en_4_we = addr_hit[388] & reg_we & !reg_error;
Tests: T1 T2 T3
36131
36132 1/1 assign mio_pad_sleep_en_4_wd = reg_wdata[0];
Tests: T1 T2 T3
36133 1/1 assign mio_pad_sleep_en_5_we = addr_hit[389] & reg_we & !reg_error;
Tests: T1 T2 T3
36134
36135 1/1 assign mio_pad_sleep_en_5_wd = reg_wdata[0];
Tests: T1 T2 T3
36136 1/1 assign mio_pad_sleep_en_6_we = addr_hit[390] & reg_we & !reg_error;
Tests: T1 T2 T3
36137
36138 1/1 assign mio_pad_sleep_en_6_wd = reg_wdata[0];
Tests: T1 T2 T3
36139 1/1 assign mio_pad_sleep_en_7_we = addr_hit[391] & reg_we & !reg_error;
Tests: T1 T2 T3
36140
36141 1/1 assign mio_pad_sleep_en_7_wd = reg_wdata[0];
Tests: T1 T2 T3
36142 1/1 assign mio_pad_sleep_en_8_we = addr_hit[392] & reg_we & !reg_error;
Tests: T1 T2 T3
36143
36144 1/1 assign mio_pad_sleep_en_8_wd = reg_wdata[0];
Tests: T1 T2 T3
36145 1/1 assign mio_pad_sleep_en_9_we = addr_hit[393] & reg_we & !reg_error;
Tests: T1 T2 T3
36146
36147 1/1 assign mio_pad_sleep_en_9_wd = reg_wdata[0];
Tests: T1 T2 T3
36148 1/1 assign mio_pad_sleep_en_10_we = addr_hit[394] & reg_we & !reg_error;
Tests: T1 T2 T3
36149
36150 1/1 assign mio_pad_sleep_en_10_wd = reg_wdata[0];
Tests: T1 T2 T3
36151 1/1 assign mio_pad_sleep_en_11_we = addr_hit[395] & reg_we & !reg_error;
Tests: T1 T2 T3
36152
36153 1/1 assign mio_pad_sleep_en_11_wd = reg_wdata[0];
Tests: T1 T2 T3
36154 1/1 assign mio_pad_sleep_en_12_we = addr_hit[396] & reg_we & !reg_error;
Tests: T1 T2 T3
36155
36156 1/1 assign mio_pad_sleep_en_12_wd = reg_wdata[0];
Tests: T1 T2 T3
36157 1/1 assign mio_pad_sleep_en_13_we = addr_hit[397] & reg_we & !reg_error;
Tests: T1 T2 T3
36158
36159 1/1 assign mio_pad_sleep_en_13_wd = reg_wdata[0];
Tests: T1 T2 T3
36160 1/1 assign mio_pad_sleep_en_14_we = addr_hit[398] & reg_we & !reg_error;
Tests: T1 T2 T3
36161
36162 1/1 assign mio_pad_sleep_en_14_wd = reg_wdata[0];
Tests: T1 T2 T3
36163 1/1 assign mio_pad_sleep_en_15_we = addr_hit[399] & reg_we & !reg_error;
Tests: T1 T2 T3
36164
36165 1/1 assign mio_pad_sleep_en_15_wd = reg_wdata[0];
Tests: T1 T2 T3
36166 1/1 assign mio_pad_sleep_en_16_we = addr_hit[400] & reg_we & !reg_error;
Tests: T1 T2 T3
36167
36168 1/1 assign mio_pad_sleep_en_16_wd = reg_wdata[0];
Tests: T1 T2 T3
36169 1/1 assign mio_pad_sleep_en_17_we = addr_hit[401] & reg_we & !reg_error;
Tests: T1 T2 T3
36170
36171 1/1 assign mio_pad_sleep_en_17_wd = reg_wdata[0];
Tests: T1 T2 T3
36172 1/1 assign mio_pad_sleep_en_18_we = addr_hit[402] & reg_we & !reg_error;
Tests: T1 T2 T3
36173
36174 1/1 assign mio_pad_sleep_en_18_wd = reg_wdata[0];
Tests: T1 T2 T3
36175 1/1 assign mio_pad_sleep_en_19_we = addr_hit[403] & reg_we & !reg_error;
Tests: T1 T2 T3
36176
36177 1/1 assign mio_pad_sleep_en_19_wd = reg_wdata[0];
Tests: T1 T2 T3
36178 1/1 assign mio_pad_sleep_en_20_we = addr_hit[404] & reg_we & !reg_error;
Tests: T1 T2 T3
36179
36180 1/1 assign mio_pad_sleep_en_20_wd = reg_wdata[0];
Tests: T1 T2 T3
36181 1/1 assign mio_pad_sleep_en_21_we = addr_hit[405] & reg_we & !reg_error;
Tests: T1 T2 T3
36182
36183 1/1 assign mio_pad_sleep_en_21_wd = reg_wdata[0];
Tests: T1 T2 T3
36184 1/1 assign mio_pad_sleep_en_22_we = addr_hit[406] & reg_we & !reg_error;
Tests: T1 T2 T3
36185
36186 1/1 assign mio_pad_sleep_en_22_wd = reg_wdata[0];
Tests: T1 T2 T3
36187 1/1 assign mio_pad_sleep_en_23_we = addr_hit[407] & reg_we & !reg_error;
Tests: T1 T2 T3
36188
36189 1/1 assign mio_pad_sleep_en_23_wd = reg_wdata[0];
Tests: T1 T2 T3
36190 1/1 assign mio_pad_sleep_en_24_we = addr_hit[408] & reg_we & !reg_error;
Tests: T1 T2 T3
36191
36192 1/1 assign mio_pad_sleep_en_24_wd = reg_wdata[0];
Tests: T1 T2 T3
36193 1/1 assign mio_pad_sleep_en_25_we = addr_hit[409] & reg_we & !reg_error;
Tests: T1 T2 T3
36194
36195 1/1 assign mio_pad_sleep_en_25_wd = reg_wdata[0];
Tests: T1 T2 T3
36196 1/1 assign mio_pad_sleep_en_26_we = addr_hit[410] & reg_we & !reg_error;
Tests: T1 T2 T3
36197
36198 1/1 assign mio_pad_sleep_en_26_wd = reg_wdata[0];
Tests: T1 T2 T3
36199 1/1 assign mio_pad_sleep_en_27_we = addr_hit[411] & reg_we & !reg_error;
Tests: T1 T2 T3
36200
36201 1/1 assign mio_pad_sleep_en_27_wd = reg_wdata[0];
Tests: T1 T2 T3
36202 1/1 assign mio_pad_sleep_en_28_we = addr_hit[412] & reg_we & !reg_error;
Tests: T1 T2 T3
36203
36204 1/1 assign mio_pad_sleep_en_28_wd = reg_wdata[0];
Tests: T1 T2 T3
36205 1/1 assign mio_pad_sleep_en_29_we = addr_hit[413] & reg_we & !reg_error;
Tests: T1 T2 T3
36206
36207 1/1 assign mio_pad_sleep_en_29_wd = reg_wdata[0];
Tests: T1 T2 T3
36208 1/1 assign mio_pad_sleep_en_30_we = addr_hit[414] & reg_we & !reg_error;
Tests: T1 T2 T3
36209
36210 1/1 assign mio_pad_sleep_en_30_wd = reg_wdata[0];
Tests: T1 T2 T3
36211 1/1 assign mio_pad_sleep_en_31_we = addr_hit[415] & reg_we & !reg_error;
Tests: T1 T2 T3
36212
36213 1/1 assign mio_pad_sleep_en_31_wd = reg_wdata[0];
Tests: T1 T2 T3
36214 1/1 assign mio_pad_sleep_en_32_we = addr_hit[416] & reg_we & !reg_error;
Tests: T1 T2 T3
36215
36216 1/1 assign mio_pad_sleep_en_32_wd = reg_wdata[0];
Tests: T1 T2 T3
36217 1/1 assign mio_pad_sleep_en_33_we = addr_hit[417] & reg_we & !reg_error;
Tests: T1 T2 T3
36218
36219 1/1 assign mio_pad_sleep_en_33_wd = reg_wdata[0];
Tests: T1 T2 T3
36220 1/1 assign mio_pad_sleep_en_34_we = addr_hit[418] & reg_we & !reg_error;
Tests: T1 T2 T3
36221
36222 1/1 assign mio_pad_sleep_en_34_wd = reg_wdata[0];
Tests: T1 T2 T3
36223 1/1 assign mio_pad_sleep_en_35_we = addr_hit[419] & reg_we & !reg_error;
Tests: T1 T2 T3
36224
36225 1/1 assign mio_pad_sleep_en_35_wd = reg_wdata[0];
Tests: T1 T2 T3
36226 1/1 assign mio_pad_sleep_en_36_we = addr_hit[420] & reg_we & !reg_error;
Tests: T1 T2 T3
36227
36228 1/1 assign mio_pad_sleep_en_36_wd = reg_wdata[0];
Tests: T1 T2 T3
36229 1/1 assign mio_pad_sleep_en_37_we = addr_hit[421] & reg_we & !reg_error;
Tests: T1 T2 T3
36230
36231 1/1 assign mio_pad_sleep_en_37_wd = reg_wdata[0];
Tests: T1 T2 T3
36232 1/1 assign mio_pad_sleep_en_38_we = addr_hit[422] & reg_we & !reg_error;
Tests: T1 T2 T3
36233
36234 1/1 assign mio_pad_sleep_en_38_wd = reg_wdata[0];
Tests: T1 T2 T3
36235 1/1 assign mio_pad_sleep_en_39_we = addr_hit[423] & reg_we & !reg_error;
Tests: T1 T2 T3
36236
36237 1/1 assign mio_pad_sleep_en_39_wd = reg_wdata[0];
Tests: T1 T2 T3
36238 1/1 assign mio_pad_sleep_en_40_we = addr_hit[424] & reg_we & !reg_error;
Tests: T1 T2 T3
36239
36240 1/1 assign mio_pad_sleep_en_40_wd = reg_wdata[0];
Tests: T1 T2 T3
36241 1/1 assign mio_pad_sleep_en_41_we = addr_hit[425] & reg_we & !reg_error;
Tests: T1 T2 T3
36242
36243 1/1 assign mio_pad_sleep_en_41_wd = reg_wdata[0];
Tests: T1 T2 T3
36244 1/1 assign mio_pad_sleep_en_42_we = addr_hit[426] & reg_we & !reg_error;
Tests: T1 T2 T3
36245
36246 1/1 assign mio_pad_sleep_en_42_wd = reg_wdata[0];
Tests: T1 T2 T3
36247 1/1 assign mio_pad_sleep_en_43_we = addr_hit[427] & reg_we & !reg_error;
Tests: T1 T2 T3
36248
36249 1/1 assign mio_pad_sleep_en_43_wd = reg_wdata[0];
Tests: T1 T2 T3
36250 1/1 assign mio_pad_sleep_en_44_we = addr_hit[428] & reg_we & !reg_error;
Tests: T1 T2 T3
36251
36252 1/1 assign mio_pad_sleep_en_44_wd = reg_wdata[0];
Tests: T1 T2 T3
36253 1/1 assign mio_pad_sleep_en_45_we = addr_hit[429] & reg_we & !reg_error;
Tests: T1 T2 T3
36254
36255 1/1 assign mio_pad_sleep_en_45_wd = reg_wdata[0];
Tests: T1 T2 T3
36256 1/1 assign mio_pad_sleep_en_46_we = addr_hit[430] & reg_we & !reg_error;
Tests: T1 T2 T3
36257
36258 1/1 assign mio_pad_sleep_en_46_wd = reg_wdata[0];
Tests: T1 T2 T3
36259 1/1 assign mio_pad_sleep_mode_0_we = addr_hit[431] & reg_we & !reg_error;
Tests: T1 T2 T3
36260
36261 1/1 assign mio_pad_sleep_mode_0_wd = reg_wdata[1:0];
Tests: T1 T2 T3
36262 1/1 assign mio_pad_sleep_mode_1_we = addr_hit[432] & reg_we & !reg_error;
Tests: T1 T2 T3
36263
36264 1/1 assign mio_pad_sleep_mode_1_wd = reg_wdata[1:0];
Tests: T1 T2 T3
36265 1/1 assign mio_pad_sleep_mode_2_we = addr_hit[433] & reg_we & !reg_error;
Tests: T1 T2 T3
36266
36267 1/1 assign mio_pad_sleep_mode_2_wd = reg_wdata[1:0];
Tests: T1 T2 T3
36268 1/1 assign mio_pad_sleep_mode_3_we = addr_hit[434] & reg_we & !reg_error;
Tests: T1 T2 T3
36269
36270 1/1 assign mio_pad_sleep_mode_3_wd = reg_wdata[1:0];
Tests: T1 T2 T3
36271 1/1 assign mio_pad_sleep_mode_4_we = addr_hit[435] & reg_we & !reg_error;
Tests: T1 T2 T3
36272
36273 1/1 assign mio_pad_sleep_mode_4_wd = reg_wdata[1:0];
Tests: T1 T2 T3
36274 1/1 assign mio_pad_sleep_mode_5_we = addr_hit[436] & reg_we & !reg_error;
Tests: T1 T2 T3
36275
36276 1/1 assign mio_pad_sleep_mode_5_wd = reg_wdata[1:0];
Tests: T1 T2 T3
36277 1/1 assign mio_pad_sleep_mode_6_we = addr_hit[437] & reg_we & !reg_error;
Tests: T1 T2 T3
36278
36279 1/1 assign mio_pad_sleep_mode_6_wd = reg_wdata[1:0];
Tests: T1 T2 T3
36280 1/1 assign mio_pad_sleep_mode_7_we = addr_hit[438] & reg_we & !reg_error;
Tests: T1 T2 T3
36281
36282 1/1 assign mio_pad_sleep_mode_7_wd = reg_wdata[1:0];
Tests: T1 T2 T3
36283 1/1 assign mio_pad_sleep_mode_8_we = addr_hit[439] & reg_we & !reg_error;
Tests: T1 T2 T3
36284
36285 1/1 assign mio_pad_sleep_mode_8_wd = reg_wdata[1:0];
Tests: T1 T2 T3
36286 1/1 assign mio_pad_sleep_mode_9_we = addr_hit[440] & reg_we & !reg_error;
Tests: T1 T2 T3
36287
36288 1/1 assign mio_pad_sleep_mode_9_wd = reg_wdata[1:0];
Tests: T1 T2 T3
36289 1/1 assign mio_pad_sleep_mode_10_we = addr_hit[441] & reg_we & !reg_error;
Tests: T1 T2 T3
36290
36291 1/1 assign mio_pad_sleep_mode_10_wd = reg_wdata[1:0];
Tests: T1 T2 T3
36292 1/1 assign mio_pad_sleep_mode_11_we = addr_hit[442] & reg_we & !reg_error;
Tests: T1 T2 T3
36293
36294 1/1 assign mio_pad_sleep_mode_11_wd = reg_wdata[1:0];
Tests: T1 T2 T3
36295 1/1 assign mio_pad_sleep_mode_12_we = addr_hit[443] & reg_we & !reg_error;
Tests: T1 T2 T3
36296
36297 1/1 assign mio_pad_sleep_mode_12_wd = reg_wdata[1:0];
Tests: T1 T2 T3
36298 1/1 assign mio_pad_sleep_mode_13_we = addr_hit[444] & reg_we & !reg_error;
Tests: T1 T2 T3
36299
36300 1/1 assign mio_pad_sleep_mode_13_wd = reg_wdata[1:0];
Tests: T1 T2 T3
36301 1/1 assign mio_pad_sleep_mode_14_we = addr_hit[445] & reg_we & !reg_error;
Tests: T1 T2 T3
36302
36303 1/1 assign mio_pad_sleep_mode_14_wd = reg_wdata[1:0];
Tests: T1 T2 T3
36304 1/1 assign mio_pad_sleep_mode_15_we = addr_hit[446] & reg_we & !reg_error;
Tests: T1 T2 T3
36305
36306 1/1 assign mio_pad_sleep_mode_15_wd = reg_wdata[1:0];
Tests: T1 T2 T3
36307 1/1 assign mio_pad_sleep_mode_16_we = addr_hit[447] & reg_we & !reg_error;
Tests: T1 T2 T3
36308
36309 1/1 assign mio_pad_sleep_mode_16_wd = reg_wdata[1:0];
Tests: T1 T2 T3
36310 1/1 assign mio_pad_sleep_mode_17_we = addr_hit[448] & reg_we & !reg_error;
Tests: T1 T2 T3
36311
36312 1/1 assign mio_pad_sleep_mode_17_wd = reg_wdata[1:0];
Tests: T1 T2 T3
36313 1/1 assign mio_pad_sleep_mode_18_we = addr_hit[449] & reg_we & !reg_error;
Tests: T1 T2 T3
36314
36315 1/1 assign mio_pad_sleep_mode_18_wd = reg_wdata[1:0];
Tests: T1 T2 T3
36316 1/1 assign mio_pad_sleep_mode_19_we = addr_hit[450] & reg_we & !reg_error;
Tests: T1 T2 T3
36317
36318 1/1 assign mio_pad_sleep_mode_19_wd = reg_wdata[1:0];
Tests: T1 T2 T3
36319 1/1 assign mio_pad_sleep_mode_20_we = addr_hit[451] & reg_we & !reg_error;
Tests: T1 T2 T3
36320
36321 1/1 assign mio_pad_sleep_mode_20_wd = reg_wdata[1:0];
Tests: T1 T2 T3
36322 1/1 assign mio_pad_sleep_mode_21_we = addr_hit[452] & reg_we & !reg_error;
Tests: T1 T2 T3
36323
36324 1/1 assign mio_pad_sleep_mode_21_wd = reg_wdata[1:0];
Tests: T1 T2 T3
36325 1/1 assign mio_pad_sleep_mode_22_we = addr_hit[453] & reg_we & !reg_error;
Tests: T1 T2 T3
36326
36327 1/1 assign mio_pad_sleep_mode_22_wd = reg_wdata[1:0];
Tests: T1 T2 T3
36328 1/1 assign mio_pad_sleep_mode_23_we = addr_hit[454] & reg_we & !reg_error;
Tests: T1 T2 T3
36329
36330 1/1 assign mio_pad_sleep_mode_23_wd = reg_wdata[1:0];
Tests: T1 T2 T3
36331 1/1 assign mio_pad_sleep_mode_24_we = addr_hit[455] & reg_we & !reg_error;
Tests: T1 T2 T3
36332
36333 1/1 assign mio_pad_sleep_mode_24_wd = reg_wdata[1:0];
Tests: T1 T2 T3
36334 1/1 assign mio_pad_sleep_mode_25_we = addr_hit[456] & reg_we & !reg_error;
Tests: T1 T2 T3
36335
36336 1/1 assign mio_pad_sleep_mode_25_wd = reg_wdata[1:0];
Tests: T1 T2 T3
36337 1/1 assign mio_pad_sleep_mode_26_we = addr_hit[457] & reg_we & !reg_error;
Tests: T1 T2 T3
36338
36339 1/1 assign mio_pad_sleep_mode_26_wd = reg_wdata[1:0];
Tests: T1 T2 T3
36340 1/1 assign mio_pad_sleep_mode_27_we = addr_hit[458] & reg_we & !reg_error;
Tests: T1 T2 T3
36341
36342 1/1 assign mio_pad_sleep_mode_27_wd = reg_wdata[1:0];
Tests: T1 T2 T3
36343 1/1 assign mio_pad_sleep_mode_28_we = addr_hit[459] & reg_we & !reg_error;
Tests: T1 T2 T3
36344
36345 1/1 assign mio_pad_sleep_mode_28_wd = reg_wdata[1:0];
Tests: T1 T2 T3
36346 1/1 assign mio_pad_sleep_mode_29_we = addr_hit[460] & reg_we & !reg_error;
Tests: T1 T2 T3
36347
36348 1/1 assign mio_pad_sleep_mode_29_wd = reg_wdata[1:0];
Tests: T1 T2 T3
36349 1/1 assign mio_pad_sleep_mode_30_we = addr_hit[461] & reg_we & !reg_error;
Tests: T1 T2 T3
36350
36351 1/1 assign mio_pad_sleep_mode_30_wd = reg_wdata[1:0];
Tests: T1 T2 T3
36352 1/1 assign mio_pad_sleep_mode_31_we = addr_hit[462] & reg_we & !reg_error;
Tests: T1 T2 T3
36353
36354 1/1 assign mio_pad_sleep_mode_31_wd = reg_wdata[1:0];
Tests: T1 T2 T3
36355 1/1 assign mio_pad_sleep_mode_32_we = addr_hit[463] & reg_we & !reg_error;
Tests: T1 T2 T3
36356
36357 1/1 assign mio_pad_sleep_mode_32_wd = reg_wdata[1:0];
Tests: T1 T2 T3
36358 1/1 assign mio_pad_sleep_mode_33_we = addr_hit[464] & reg_we & !reg_error;
Tests: T1 T2 T3
36359
36360 1/1 assign mio_pad_sleep_mode_33_wd = reg_wdata[1:0];
Tests: T1 T2 T3
36361 1/1 assign mio_pad_sleep_mode_34_we = addr_hit[465] & reg_we & !reg_error;
Tests: T1 T2 T3
36362
36363 1/1 assign mio_pad_sleep_mode_34_wd = reg_wdata[1:0];
Tests: T1 T2 T3
36364 1/1 assign mio_pad_sleep_mode_35_we = addr_hit[466] & reg_we & !reg_error;
Tests: T1 T2 T3
36365
36366 1/1 assign mio_pad_sleep_mode_35_wd = reg_wdata[1:0];
Tests: T1 T2 T3
36367 1/1 assign mio_pad_sleep_mode_36_we = addr_hit[467] & reg_we & !reg_error;
Tests: T1 T2 T3
36368
36369 1/1 assign mio_pad_sleep_mode_36_wd = reg_wdata[1:0];
Tests: T1 T2 T3
36370 1/1 assign mio_pad_sleep_mode_37_we = addr_hit[468] & reg_we & !reg_error;
Tests: T1 T2 T3
36371
36372 1/1 assign mio_pad_sleep_mode_37_wd = reg_wdata[1:0];
Tests: T1 T2 T3
36373 1/1 assign mio_pad_sleep_mode_38_we = addr_hit[469] & reg_we & !reg_error;
Tests: T1 T2 T3
36374
36375 1/1 assign mio_pad_sleep_mode_38_wd = reg_wdata[1:0];
Tests: T1 T2 T3
36376 1/1 assign mio_pad_sleep_mode_39_we = addr_hit[470] & reg_we & !reg_error;
Tests: T1 T2 T3
36377
36378 1/1 assign mio_pad_sleep_mode_39_wd = reg_wdata[1:0];
Tests: T1 T2 T3
36379 1/1 assign mio_pad_sleep_mode_40_we = addr_hit[471] & reg_we & !reg_error;
Tests: T1 T2 T3
36380
36381 1/1 assign mio_pad_sleep_mode_40_wd = reg_wdata[1:0];
Tests: T1 T2 T3
36382 1/1 assign mio_pad_sleep_mode_41_we = addr_hit[472] & reg_we & !reg_error;
Tests: T1 T2 T3
36383
36384 1/1 assign mio_pad_sleep_mode_41_wd = reg_wdata[1:0];
Tests: T1 T2 T3
36385 1/1 assign mio_pad_sleep_mode_42_we = addr_hit[473] & reg_we & !reg_error;
Tests: T1 T2 T3
36386
36387 1/1 assign mio_pad_sleep_mode_42_wd = reg_wdata[1:0];
Tests: T1 T2 T3
36388 1/1 assign mio_pad_sleep_mode_43_we = addr_hit[474] & reg_we & !reg_error;
Tests: T1 T2 T3
36389
36390 1/1 assign mio_pad_sleep_mode_43_wd = reg_wdata[1:0];
Tests: T1 T2 T3
36391 1/1 assign mio_pad_sleep_mode_44_we = addr_hit[475] & reg_we & !reg_error;
Tests: T1 T2 T3
36392
36393 1/1 assign mio_pad_sleep_mode_44_wd = reg_wdata[1:0];
Tests: T1 T2 T3
36394 1/1 assign mio_pad_sleep_mode_45_we = addr_hit[476] & reg_we & !reg_error;
Tests: T1 T2 T3
36395
36396 1/1 assign mio_pad_sleep_mode_45_wd = reg_wdata[1:0];
Tests: T1 T2 T3
36397 1/1 assign mio_pad_sleep_mode_46_we = addr_hit[477] & reg_we & !reg_error;
Tests: T1 T2 T3
36398
36399 1/1 assign mio_pad_sleep_mode_46_wd = reg_wdata[1:0];
Tests: T1 T2 T3
36400 1/1 assign dio_pad_sleep_status_we = addr_hit[478] & reg_we & !reg_error;
Tests: T1 T2 T3
36401
36402 1/1 assign dio_pad_sleep_status_en_0_wd = reg_wdata[0];
Tests: T1 T2 T3
36403
36404 1/1 assign dio_pad_sleep_status_en_1_wd = reg_wdata[1];
Tests: T1 T2 T3
36405
36406 1/1 assign dio_pad_sleep_status_en_2_wd = reg_wdata[2];
Tests: T1 T2 T3
36407
36408 1/1 assign dio_pad_sleep_status_en_3_wd = reg_wdata[3];
Tests: T1 T2 T3
36409
36410 1/1 assign dio_pad_sleep_status_en_4_wd = reg_wdata[4];
Tests: T1 T2 T3
36411
36412 1/1 assign dio_pad_sleep_status_en_5_wd = reg_wdata[5];
Tests: T1 T2 T3
36413
36414 1/1 assign dio_pad_sleep_status_en_6_wd = reg_wdata[6];
Tests: T1 T2 T3
36415
36416 1/1 assign dio_pad_sleep_status_en_7_wd = reg_wdata[7];
Tests: T1 T2 T3
36417
36418 1/1 assign dio_pad_sleep_status_en_8_wd = reg_wdata[8];
Tests: T1 T2 T3
36419
36420 1/1 assign dio_pad_sleep_status_en_9_wd = reg_wdata[9];
Tests: T1 T2 T3
36421
36422 1/1 assign dio_pad_sleep_status_en_10_wd = reg_wdata[10];
Tests: T1 T2 T3
36423
36424 1/1 assign dio_pad_sleep_status_en_11_wd = reg_wdata[11];
Tests: T1 T2 T3
36425
36426 1/1 assign dio_pad_sleep_status_en_12_wd = reg_wdata[12];
Tests: T1 T2 T3
36427
36428 1/1 assign dio_pad_sleep_status_en_13_wd = reg_wdata[13];
Tests: T1 T2 T3
36429
36430 1/1 assign dio_pad_sleep_status_en_14_wd = reg_wdata[14];
Tests: T1 T2 T3
36431
36432 1/1 assign dio_pad_sleep_status_en_15_wd = reg_wdata[15];
Tests: T1 T2 T3
36433 1/1 assign dio_pad_sleep_regwen_0_we = addr_hit[479] & reg_we & !reg_error;
Tests: T1 T2 T3
36434
36435 1/1 assign dio_pad_sleep_regwen_0_wd = reg_wdata[0];
Tests: T1 T2 T3
36436 1/1 assign dio_pad_sleep_regwen_1_we = addr_hit[480] & reg_we & !reg_error;
Tests: T1 T2 T3
36437
36438 1/1 assign dio_pad_sleep_regwen_1_wd = reg_wdata[0];
Tests: T1 T2 T3
36439 1/1 assign dio_pad_sleep_regwen_2_we = addr_hit[481] & reg_we & !reg_error;
Tests: T1 T2 T3
36440
36441 1/1 assign dio_pad_sleep_regwen_2_wd = reg_wdata[0];
Tests: T1 T2 T3
36442 1/1 assign dio_pad_sleep_regwen_3_we = addr_hit[482] & reg_we & !reg_error;
Tests: T1 T2 T3
36443
36444 1/1 assign dio_pad_sleep_regwen_3_wd = reg_wdata[0];
Tests: T1 T2 T3
36445 1/1 assign dio_pad_sleep_regwen_4_we = addr_hit[483] & reg_we & !reg_error;
Tests: T1 T2 T3
36446
36447 1/1 assign dio_pad_sleep_regwen_4_wd = reg_wdata[0];
Tests: T1 T2 T3
36448 1/1 assign dio_pad_sleep_regwen_5_we = addr_hit[484] & reg_we & !reg_error;
Tests: T1 T2 T3
36449
36450 1/1 assign dio_pad_sleep_regwen_5_wd = reg_wdata[0];
Tests: T1 T2 T3
36451 1/1 assign dio_pad_sleep_regwen_6_we = addr_hit[485] & reg_we & !reg_error;
Tests: T1 T2 T3
36452
36453 1/1 assign dio_pad_sleep_regwen_6_wd = reg_wdata[0];
Tests: T1 T2 T3
36454 1/1 assign dio_pad_sleep_regwen_7_we = addr_hit[486] & reg_we & !reg_error;
Tests: T1 T2 T3
36455
36456 1/1 assign dio_pad_sleep_regwen_7_wd = reg_wdata[0];
Tests: T1 T2 T3
36457 1/1 assign dio_pad_sleep_regwen_8_we = addr_hit[487] & reg_we & !reg_error;
Tests: T1 T2 T3
36458
36459 1/1 assign dio_pad_sleep_regwen_8_wd = reg_wdata[0];
Tests: T1 T2 T3
36460 1/1 assign dio_pad_sleep_regwen_9_we = addr_hit[488] & reg_we & !reg_error;
Tests: T1 T2 T3
36461
36462 1/1 assign dio_pad_sleep_regwen_9_wd = reg_wdata[0];
Tests: T1 T2 T3
36463 1/1 assign dio_pad_sleep_regwen_10_we = addr_hit[489] & reg_we & !reg_error;
Tests: T1 T2 T3
36464
36465 1/1 assign dio_pad_sleep_regwen_10_wd = reg_wdata[0];
Tests: T1 T2 T3
36466 1/1 assign dio_pad_sleep_regwen_11_we = addr_hit[490] & reg_we & !reg_error;
Tests: T1 T2 T3
36467
36468 1/1 assign dio_pad_sleep_regwen_11_wd = reg_wdata[0];
Tests: T1 T2 T3
36469 1/1 assign dio_pad_sleep_regwen_12_we = addr_hit[491] & reg_we & !reg_error;
Tests: T1 T2 T3
36470
36471 1/1 assign dio_pad_sleep_regwen_12_wd = reg_wdata[0];
Tests: T1 T2 T3
36472 1/1 assign dio_pad_sleep_regwen_13_we = addr_hit[492] & reg_we & !reg_error;
Tests: T1 T2 T3
36473
36474 1/1 assign dio_pad_sleep_regwen_13_wd = reg_wdata[0];
Tests: T1 T2 T3
36475 1/1 assign dio_pad_sleep_regwen_14_we = addr_hit[493] & reg_we & !reg_error;
Tests: T1 T2 T3
36476
36477 1/1 assign dio_pad_sleep_regwen_14_wd = reg_wdata[0];
Tests: T1 T2 T3
36478 1/1 assign dio_pad_sleep_regwen_15_we = addr_hit[494] & reg_we & !reg_error;
Tests: T1 T2 T3
36479
36480 1/1 assign dio_pad_sleep_regwen_15_wd = reg_wdata[0];
Tests: T1 T2 T3
36481 1/1 assign dio_pad_sleep_en_0_we = addr_hit[495] & reg_we & !reg_error;
Tests: T1 T2 T3
36482
36483 1/1 assign dio_pad_sleep_en_0_wd = reg_wdata[0];
Tests: T1 T2 T3
36484 1/1 assign dio_pad_sleep_en_1_we = addr_hit[496] & reg_we & !reg_error;
Tests: T1 T2 T3
36485
36486 1/1 assign dio_pad_sleep_en_1_wd = reg_wdata[0];
Tests: T1 T2 T3
36487 1/1 assign dio_pad_sleep_en_2_we = addr_hit[497] & reg_we & !reg_error;
Tests: T1 T2 T3
36488
36489 1/1 assign dio_pad_sleep_en_2_wd = reg_wdata[0];
Tests: T1 T2 T3
36490 1/1 assign dio_pad_sleep_en_3_we = addr_hit[498] & reg_we & !reg_error;
Tests: T1 T2 T3
36491
36492 1/1 assign dio_pad_sleep_en_3_wd = reg_wdata[0];
Tests: T1 T2 T3
36493 1/1 assign dio_pad_sleep_en_4_we = addr_hit[499] & reg_we & !reg_error;
Tests: T1 T2 T3
36494
36495 1/1 assign dio_pad_sleep_en_4_wd = reg_wdata[0];
Tests: T1 T2 T3
36496 1/1 assign dio_pad_sleep_en_5_we = addr_hit[500] & reg_we & !reg_error;
Tests: T1 T2 T3
36497
36498 1/1 assign dio_pad_sleep_en_5_wd = reg_wdata[0];
Tests: T1 T2 T3
36499 1/1 assign dio_pad_sleep_en_6_we = addr_hit[501] & reg_we & !reg_error;
Tests: T1 T2 T3
36500
36501 1/1 assign dio_pad_sleep_en_6_wd = reg_wdata[0];
Tests: T1 T2 T3
36502 1/1 assign dio_pad_sleep_en_7_we = addr_hit[502] & reg_we & !reg_error;
Tests: T1 T2 T3
36503
36504 1/1 assign dio_pad_sleep_en_7_wd = reg_wdata[0];
Tests: T1 T2 T3
36505 1/1 assign dio_pad_sleep_en_8_we = addr_hit[503] & reg_we & !reg_error;
Tests: T1 T2 T3
36506
36507 1/1 assign dio_pad_sleep_en_8_wd = reg_wdata[0];
Tests: T1 T2 T3
36508 1/1 assign dio_pad_sleep_en_9_we = addr_hit[504] & reg_we & !reg_error;
Tests: T1 T2 T3
36509
36510 1/1 assign dio_pad_sleep_en_9_wd = reg_wdata[0];
Tests: T1 T2 T3
36511 1/1 assign dio_pad_sleep_en_10_we = addr_hit[505] & reg_we & !reg_error;
Tests: T1 T2 T3
36512
36513 1/1 assign dio_pad_sleep_en_10_wd = reg_wdata[0];
Tests: T1 T2 T3
36514 1/1 assign dio_pad_sleep_en_11_we = addr_hit[506] & reg_we & !reg_error;
Tests: T1 T2 T3
36515
36516 1/1 assign dio_pad_sleep_en_11_wd = reg_wdata[0];
Tests: T1 T2 T3
36517 1/1 assign dio_pad_sleep_en_12_we = addr_hit[507] & reg_we & !reg_error;
Tests: T1 T2 T3
36518
36519 1/1 assign dio_pad_sleep_en_12_wd = reg_wdata[0];
Tests: T1 T2 T3
36520 1/1 assign dio_pad_sleep_en_13_we = addr_hit[508] & reg_we & !reg_error;
Tests: T1 T2 T3
36521
36522 1/1 assign dio_pad_sleep_en_13_wd = reg_wdata[0];
Tests: T1 T2 T3
36523 1/1 assign dio_pad_sleep_en_14_we = addr_hit[509] & reg_we & !reg_error;
Tests: T1 T2 T3
36524
36525 1/1 assign dio_pad_sleep_en_14_wd = reg_wdata[0];
Tests: T1 T2 T3
36526 1/1 assign dio_pad_sleep_en_15_we = addr_hit[510] & reg_we & !reg_error;
Tests: T1 T2 T3
36527
36528 1/1 assign dio_pad_sleep_en_15_wd = reg_wdata[0];
Tests: T1 T2 T3
36529 1/1 assign dio_pad_sleep_mode_0_we = addr_hit[511] & reg_we & !reg_error;
Tests: T1 T2 T3
36530
36531 1/1 assign dio_pad_sleep_mode_0_wd = reg_wdata[1:0];
Tests: T1 T2 T3
36532 1/1 assign dio_pad_sleep_mode_1_we = addr_hit[512] & reg_we & !reg_error;
Tests: T1 T2 T3
36533
36534 1/1 assign dio_pad_sleep_mode_1_wd = reg_wdata[1:0];
Tests: T1 T2 T3
36535 1/1 assign dio_pad_sleep_mode_2_we = addr_hit[513] & reg_we & !reg_error;
Tests: T1 T2 T3
36536
36537 1/1 assign dio_pad_sleep_mode_2_wd = reg_wdata[1:0];
Tests: T1 T2 T3
36538 1/1 assign dio_pad_sleep_mode_3_we = addr_hit[514] & reg_we & !reg_error;
Tests: T1 T2 T3
36539
36540 1/1 assign dio_pad_sleep_mode_3_wd = reg_wdata[1:0];
Tests: T1 T2 T3
36541 1/1 assign dio_pad_sleep_mode_4_we = addr_hit[515] & reg_we & !reg_error;
Tests: T1 T2 T3
36542
36543 1/1 assign dio_pad_sleep_mode_4_wd = reg_wdata[1:0];
Tests: T1 T2 T3
36544 1/1 assign dio_pad_sleep_mode_5_we = addr_hit[516] & reg_we & !reg_error;
Tests: T1 T2 T3
36545
36546 1/1 assign dio_pad_sleep_mode_5_wd = reg_wdata[1:0];
Tests: T1 T2 T3
36547 1/1 assign dio_pad_sleep_mode_6_we = addr_hit[517] & reg_we & !reg_error;
Tests: T1 T2 T3
36548
36549 1/1 assign dio_pad_sleep_mode_6_wd = reg_wdata[1:0];
Tests: T1 T2 T3
36550 1/1 assign dio_pad_sleep_mode_7_we = addr_hit[518] & reg_we & !reg_error;
Tests: T1 T2 T3
36551
36552 1/1 assign dio_pad_sleep_mode_7_wd = reg_wdata[1:0];
Tests: T1 T2 T3
36553 1/1 assign dio_pad_sleep_mode_8_we = addr_hit[519] & reg_we & !reg_error;
Tests: T1 T2 T3
36554
36555 1/1 assign dio_pad_sleep_mode_8_wd = reg_wdata[1:0];
Tests: T1 T2 T3
36556 1/1 assign dio_pad_sleep_mode_9_we = addr_hit[520] & reg_we & !reg_error;
Tests: T1 T2 T3
36557
36558 1/1 assign dio_pad_sleep_mode_9_wd = reg_wdata[1:0];
Tests: T1 T2 T3
36559 1/1 assign dio_pad_sleep_mode_10_we = addr_hit[521] & reg_we & !reg_error;
Tests: T1 T2 T3
36560
36561 1/1 assign dio_pad_sleep_mode_10_wd = reg_wdata[1:0];
Tests: T1 T2 T3
36562 1/1 assign dio_pad_sleep_mode_11_we = addr_hit[522] & reg_we & !reg_error;
Tests: T1 T2 T3
36563
36564 1/1 assign dio_pad_sleep_mode_11_wd = reg_wdata[1:0];
Tests: T1 T2 T3
36565 1/1 assign dio_pad_sleep_mode_12_we = addr_hit[523] & reg_we & !reg_error;
Tests: T1 T2 T3
36566
36567 1/1 assign dio_pad_sleep_mode_12_wd = reg_wdata[1:0];
Tests: T1 T2 T3
36568 1/1 assign dio_pad_sleep_mode_13_we = addr_hit[524] & reg_we & !reg_error;
Tests: T1 T2 T3
36569
36570 1/1 assign dio_pad_sleep_mode_13_wd = reg_wdata[1:0];
Tests: T1 T2 T3
36571 1/1 assign dio_pad_sleep_mode_14_we = addr_hit[525] & reg_we & !reg_error;
Tests: T1 T2 T3
36572
36573 1/1 assign dio_pad_sleep_mode_14_wd = reg_wdata[1:0];
Tests: T1 T2 T3
36574 1/1 assign dio_pad_sleep_mode_15_we = addr_hit[526] & reg_we & !reg_error;
Tests: T1 T2 T3
36575
36576 1/1 assign dio_pad_sleep_mode_15_wd = reg_wdata[1:0];
Tests: T1 T2 T3
36577 1/1 assign wkup_detector_regwen_0_we = addr_hit[527] & reg_we & !reg_error;
Tests: T1 T2 T3
36578
36579 1/1 assign wkup_detector_regwen_0_wd = reg_wdata[0];
Tests: T1 T2 T3
36580 1/1 assign wkup_detector_regwen_1_we = addr_hit[528] & reg_we & !reg_error;
Tests: T1 T2 T3
36581
36582 1/1 assign wkup_detector_regwen_1_wd = reg_wdata[0];
Tests: T1 T2 T3
36583 1/1 assign wkup_detector_regwen_2_we = addr_hit[529] & reg_we & !reg_error;
Tests: T1 T2 T3
36584
36585 1/1 assign wkup_detector_regwen_2_wd = reg_wdata[0];
Tests: T1 T2 T3
36586 1/1 assign wkup_detector_regwen_3_we = addr_hit[530] & reg_we & !reg_error;
Tests: T1 T2 T3
36587
36588 1/1 assign wkup_detector_regwen_3_wd = reg_wdata[0];
Tests: T1 T2 T3
36589 1/1 assign wkup_detector_regwen_4_we = addr_hit[531] & reg_we & !reg_error;
Tests: T1 T2 T3
36590
36591 1/1 assign wkup_detector_regwen_4_wd = reg_wdata[0];
Tests: T1 T2 T3
36592 1/1 assign wkup_detector_regwen_5_we = addr_hit[532] & reg_we & !reg_error;
Tests: T1 T2 T3
36593
36594 1/1 assign wkup_detector_regwen_5_wd = reg_wdata[0];
Tests: T1 T2 T3
36595 1/1 assign wkup_detector_regwen_6_we = addr_hit[533] & reg_we & !reg_error;
Tests: T1 T2 T3
36596
36597 1/1 assign wkup_detector_regwen_6_wd = reg_wdata[0];
Tests: T1 T2 T3
36598 1/1 assign wkup_detector_regwen_7_we = addr_hit[534] & reg_we & !reg_error;
Tests: T1 T2 T3
36599
36600 1/1 assign wkup_detector_regwen_7_wd = reg_wdata[0];
Tests: T1 T2 T3
36601 1/1 assign wkup_detector_en_0_we = addr_hit[535] & reg_we & !reg_error;
Tests: T1 T2 T3
36602
36603 1/1 assign wkup_detector_en_1_we = addr_hit[536] & reg_we & !reg_error;
Tests: T1 T2 T3
36604
36605 1/1 assign wkup_detector_en_2_we = addr_hit[537] & reg_we & !reg_error;
Tests: T1 T2 T3
36606
36607 1/1 assign wkup_detector_en_3_we = addr_hit[538] & reg_we & !reg_error;
Tests: T1 T2 T3
36608
36609 1/1 assign wkup_detector_en_4_we = addr_hit[539] & reg_we & !reg_error;
Tests: T1 T2 T3
36610
36611 1/1 assign wkup_detector_en_5_we = addr_hit[540] & reg_we & !reg_error;
Tests: T1 T2 T3
36612
36613 1/1 assign wkup_detector_en_6_we = addr_hit[541] & reg_we & !reg_error;
Tests: T1 T2 T3
36614
36615 1/1 assign wkup_detector_en_7_we = addr_hit[542] & reg_we & !reg_error;
Tests: T1 T2 T3
36616
36617 1/1 assign wkup_detector_0_we = addr_hit[543] & reg_we & !reg_error;
Tests: T1 T2 T3
36618
36619
36620
36621 1/1 assign wkup_detector_1_we = addr_hit[544] & reg_we & !reg_error;
Tests: T1 T2 T3
36622
36623
36624
36625 1/1 assign wkup_detector_2_we = addr_hit[545] & reg_we & !reg_error;
Tests: T1 T2 T3
36626
36627
36628
36629 1/1 assign wkup_detector_3_we = addr_hit[546] & reg_we & !reg_error;
Tests: T1 T2 T3
36630
36631
36632
36633 1/1 assign wkup_detector_4_we = addr_hit[547] & reg_we & !reg_error;
Tests: T1 T2 T3
36634
36635
36636
36637 1/1 assign wkup_detector_5_we = addr_hit[548] & reg_we & !reg_error;
Tests: T1 T2 T3
36638
36639
36640
36641 1/1 assign wkup_detector_6_we = addr_hit[549] & reg_we & !reg_error;
Tests: T1 T2 T3
36642
36643
36644
36645 1/1 assign wkup_detector_7_we = addr_hit[550] & reg_we & !reg_error;
Tests: T1 T2 T3
36646
36647
36648
36649 1/1 assign wkup_detector_cnt_th_0_we = addr_hit[551] & reg_we & !reg_error;
Tests: T1 T2 T3
36650
36651 1/1 assign wkup_detector_cnt_th_1_we = addr_hit[552] & reg_we & !reg_error;
Tests: T1 T2 T3
36652
36653 1/1 assign wkup_detector_cnt_th_2_we = addr_hit[553] & reg_we & !reg_error;
Tests: T1 T2 T3
36654
36655 1/1 assign wkup_detector_cnt_th_3_we = addr_hit[554] & reg_we & !reg_error;
Tests: T1 T2 T3
36656
36657 1/1 assign wkup_detector_cnt_th_4_we = addr_hit[555] & reg_we & !reg_error;
Tests: T1 T2 T3
36658
36659 1/1 assign wkup_detector_cnt_th_5_we = addr_hit[556] & reg_we & !reg_error;
Tests: T1 T2 T3
36660
36661 1/1 assign wkup_detector_cnt_th_6_we = addr_hit[557] & reg_we & !reg_error;
Tests: T1 T2 T3
36662
36663 1/1 assign wkup_detector_cnt_th_7_we = addr_hit[558] & reg_we & !reg_error;
Tests: T1 T2 T3
36664
36665 1/1 assign wkup_detector_padsel_0_we = addr_hit[559] & reg_we & !reg_error;
Tests: T1 T2 T3
36666
36667 1/1 assign wkup_detector_padsel_0_wd = reg_wdata[5:0];
Tests: T1 T2 T3
36668 1/1 assign wkup_detector_padsel_1_we = addr_hit[560] & reg_we & !reg_error;
Tests: T1 T2 T3
36669
36670 1/1 assign wkup_detector_padsel_1_wd = reg_wdata[5:0];
Tests: T1 T2 T3
36671 1/1 assign wkup_detector_padsel_2_we = addr_hit[561] & reg_we & !reg_error;
Tests: T1 T2 T3
36672
36673 1/1 assign wkup_detector_padsel_2_wd = reg_wdata[5:0];
Tests: T1 T2 T3
36674 1/1 assign wkup_detector_padsel_3_we = addr_hit[562] & reg_we & !reg_error;
Tests: T1 T2 T3
36675
36676 1/1 assign wkup_detector_padsel_3_wd = reg_wdata[5:0];
Tests: T1 T2 T3
36677 1/1 assign wkup_detector_padsel_4_we = addr_hit[563] & reg_we & !reg_error;
Tests: T1 T2 T3
36678
36679 1/1 assign wkup_detector_padsel_4_wd = reg_wdata[5:0];
Tests: T1 T2 T3
36680 1/1 assign wkup_detector_padsel_5_we = addr_hit[564] & reg_we & !reg_error;
Tests: T1 T2 T3
36681
36682 1/1 assign wkup_detector_padsel_5_wd = reg_wdata[5:0];
Tests: T1 T2 T3
36683 1/1 assign wkup_detector_padsel_6_we = addr_hit[565] & reg_we & !reg_error;
Tests: T1 T2 T3
36684
36685 1/1 assign wkup_detector_padsel_6_wd = reg_wdata[5:0];
Tests: T1 T2 T3
36686 1/1 assign wkup_detector_padsel_7_we = addr_hit[566] & reg_we & !reg_error;
Tests: T1 T2 T3
36687
36688 1/1 assign wkup_detector_padsel_7_wd = reg_wdata[5:0];
Tests: T1 T2 T3
36689 1/1 assign wkup_cause_we = addr_hit[567] & reg_we & !reg_error;
Tests: T1 T2 T3
36690
36691
36692
36693
36694
36695
36696
36697
36698
36699 // Assign write-enables to checker logic vector.
36700 always_comb begin
36701 1/1 reg_we_check = '0;
Tests: T1 T2 T3
36702 1/1 reg_we_check[0] = alert_test_we;
Tests: T1 T2 T3
36703 1/1 reg_we_check[1] = mio_periph_insel_regwen_0_we;
Tests: T1 T2 T3
36704 1/1 reg_we_check[2] = mio_periph_insel_regwen_1_we;
Tests: T1 T2 T3
36705 1/1 reg_we_check[3] = mio_periph_insel_regwen_2_we;
Tests: T1 T2 T3
36706 1/1 reg_we_check[4] = mio_periph_insel_regwen_3_we;
Tests: T1 T2 T3
36707 1/1 reg_we_check[5] = mio_periph_insel_regwen_4_we;
Tests: T1 T2 T3
36708 1/1 reg_we_check[6] = mio_periph_insel_regwen_5_we;
Tests: T1 T2 T3
36709 1/1 reg_we_check[7] = mio_periph_insel_regwen_6_we;
Tests: T1 T2 T3
36710 1/1 reg_we_check[8] = mio_periph_insel_regwen_7_we;
Tests: T1 T2 T3
36711 1/1 reg_we_check[9] = mio_periph_insel_regwen_8_we;
Tests: T1 T2 T3
36712 1/1 reg_we_check[10] = mio_periph_insel_regwen_9_we;
Tests: T1 T2 T3
36713 1/1 reg_we_check[11] = mio_periph_insel_regwen_10_we;
Tests: T1 T2 T3
36714 1/1 reg_we_check[12] = mio_periph_insel_regwen_11_we;
Tests: T1 T2 T3
36715 1/1 reg_we_check[13] = mio_periph_insel_regwen_12_we;
Tests: T1 T2 T3
36716 1/1 reg_we_check[14] = mio_periph_insel_regwen_13_we;
Tests: T1 T2 T3
36717 1/1 reg_we_check[15] = mio_periph_insel_regwen_14_we;
Tests: T1 T2 T3
36718 1/1 reg_we_check[16] = mio_periph_insel_regwen_15_we;
Tests: T1 T2 T3
36719 1/1 reg_we_check[17] = mio_periph_insel_regwen_16_we;
Tests: T1 T2 T3
36720 1/1 reg_we_check[18] = mio_periph_insel_regwen_17_we;
Tests: T1 T2 T3
36721 1/1 reg_we_check[19] = mio_periph_insel_regwen_18_we;
Tests: T1 T2 T3
36722 1/1 reg_we_check[20] = mio_periph_insel_regwen_19_we;
Tests: T1 T2 T3
36723 1/1 reg_we_check[21] = mio_periph_insel_regwen_20_we;
Tests: T1 T2 T3
36724 1/1 reg_we_check[22] = mio_periph_insel_regwen_21_we;
Tests: T1 T2 T3
36725 1/1 reg_we_check[23] = mio_periph_insel_regwen_22_we;
Tests: T1 T2 T3
36726 1/1 reg_we_check[24] = mio_periph_insel_regwen_23_we;
Tests: T1 T2 T3
36727 1/1 reg_we_check[25] = mio_periph_insel_regwen_24_we;
Tests: T1 T2 T3
36728 1/1 reg_we_check[26] = mio_periph_insel_regwen_25_we;
Tests: T1 T2 T3
36729 1/1 reg_we_check[27] = mio_periph_insel_regwen_26_we;
Tests: T1 T2 T3
36730 1/1 reg_we_check[28] = mio_periph_insel_regwen_27_we;
Tests: T1 T2 T3
36731 1/1 reg_we_check[29] = mio_periph_insel_regwen_28_we;
Tests: T1 T2 T3
36732 1/1 reg_we_check[30] = mio_periph_insel_regwen_29_we;
Tests: T1 T2 T3
36733 1/1 reg_we_check[31] = mio_periph_insel_regwen_30_we;
Tests: T1 T2 T3
36734 1/1 reg_we_check[32] = mio_periph_insel_regwen_31_we;
Tests: T1 T2 T3
36735 1/1 reg_we_check[33] = mio_periph_insel_regwen_32_we;
Tests: T1 T2 T3
36736 1/1 reg_we_check[34] = mio_periph_insel_regwen_33_we;
Tests: T1 T2 T3
36737 1/1 reg_we_check[35] = mio_periph_insel_regwen_34_we;
Tests: T1 T2 T3
36738 1/1 reg_we_check[36] = mio_periph_insel_regwen_35_we;
Tests: T1 T2 T3
36739 1/1 reg_we_check[37] = mio_periph_insel_regwen_36_we;
Tests: T1 T2 T3
36740 1/1 reg_we_check[38] = mio_periph_insel_regwen_37_we;
Tests: T1 T2 T3
36741 1/1 reg_we_check[39] = mio_periph_insel_regwen_38_we;
Tests: T1 T2 T3
36742 1/1 reg_we_check[40] = mio_periph_insel_regwen_39_we;
Tests: T1 T2 T3
36743 1/1 reg_we_check[41] = mio_periph_insel_regwen_40_we;
Tests: T1 T2 T3
36744 1/1 reg_we_check[42] = mio_periph_insel_regwen_41_we;
Tests: T1 T2 T3
36745 1/1 reg_we_check[43] = mio_periph_insel_regwen_42_we;
Tests: T1 T2 T3
36746 1/1 reg_we_check[44] = mio_periph_insel_regwen_43_we;
Tests: T1 T2 T3
36747 1/1 reg_we_check[45] = mio_periph_insel_regwen_44_we;
Tests: T1 T2 T3
36748 1/1 reg_we_check[46] = mio_periph_insel_regwen_45_we;
Tests: T1 T2 T3
36749 1/1 reg_we_check[47] = mio_periph_insel_regwen_46_we;
Tests: T1 T2 T3
36750 1/1 reg_we_check[48] = mio_periph_insel_regwen_47_we;
Tests: T1 T2 T3
36751 1/1 reg_we_check[49] = mio_periph_insel_regwen_48_we;
Tests: T1 T2 T3
36752 1/1 reg_we_check[50] = mio_periph_insel_regwen_49_we;
Tests: T1 T2 T3
36753 1/1 reg_we_check[51] = mio_periph_insel_regwen_50_we;
Tests: T1 T2 T3
36754 1/1 reg_we_check[52] = mio_periph_insel_regwen_51_we;
Tests: T1 T2 T3
36755 1/1 reg_we_check[53] = mio_periph_insel_regwen_52_we;
Tests: T1 T2 T3
36756 1/1 reg_we_check[54] = mio_periph_insel_regwen_53_we;
Tests: T1 T2 T3
36757 1/1 reg_we_check[55] = mio_periph_insel_regwen_54_we;
Tests: T1 T2 T3
36758 1/1 reg_we_check[56] = mio_periph_insel_regwen_55_we;
Tests: T1 T2 T3
36759 1/1 reg_we_check[57] = mio_periph_insel_regwen_56_we;
Tests: T1 T2 T3
36760 1/1 reg_we_check[58] = mio_periph_insel_0_gated_we;
Tests: T1 T2 T3
36761 1/1 reg_we_check[59] = mio_periph_insel_1_gated_we;
Tests: T1 T2 T3
36762 1/1 reg_we_check[60] = mio_periph_insel_2_gated_we;
Tests: T1 T2 T3
36763 1/1 reg_we_check[61] = mio_periph_insel_3_gated_we;
Tests: T1 T2 T3
36764 1/1 reg_we_check[62] = mio_periph_insel_4_gated_we;
Tests: T1 T2 T3
36765 1/1 reg_we_check[63] = mio_periph_insel_5_gated_we;
Tests: T1 T2 T3
36766 1/1 reg_we_check[64] = mio_periph_insel_6_gated_we;
Tests: T1 T2 T3
36767 1/1 reg_we_check[65] = mio_periph_insel_7_gated_we;
Tests: T1 T2 T3
36768 1/1 reg_we_check[66] = mio_periph_insel_8_gated_we;
Tests: T1 T2 T3
36769 1/1 reg_we_check[67] = mio_periph_insel_9_gated_we;
Tests: T1 T2 T3
36770 1/1 reg_we_check[68] = mio_periph_insel_10_gated_we;
Tests: T1 T2 T3
36771 1/1 reg_we_check[69] = mio_periph_insel_11_gated_we;
Tests: T1 T2 T3
36772 1/1 reg_we_check[70] = mio_periph_insel_12_gated_we;
Tests: T1 T2 T3
36773 1/1 reg_we_check[71] = mio_periph_insel_13_gated_we;
Tests: T1 T2 T3
36774 1/1 reg_we_check[72] = mio_periph_insel_14_gated_we;
Tests: T1 T2 T3
36775 1/1 reg_we_check[73] = mio_periph_insel_15_gated_we;
Tests: T1 T2 T3
36776 1/1 reg_we_check[74] = mio_periph_insel_16_gated_we;
Tests: T1 T2 T3
36777 1/1 reg_we_check[75] = mio_periph_insel_17_gated_we;
Tests: T1 T2 T3
36778 1/1 reg_we_check[76] = mio_periph_insel_18_gated_we;
Tests: T1 T2 T3
36779 1/1 reg_we_check[77] = mio_periph_insel_19_gated_we;
Tests: T1 T2 T3
36780 1/1 reg_we_check[78] = mio_periph_insel_20_gated_we;
Tests: T1 T2 T3
36781 1/1 reg_we_check[79] = mio_periph_insel_21_gated_we;
Tests: T1 T2 T3
36782 1/1 reg_we_check[80] = mio_periph_insel_22_gated_we;
Tests: T1 T2 T3
36783 1/1 reg_we_check[81] = mio_periph_insel_23_gated_we;
Tests: T1 T2 T3
36784 1/1 reg_we_check[82] = mio_periph_insel_24_gated_we;
Tests: T1 T2 T3
36785 1/1 reg_we_check[83] = mio_periph_insel_25_gated_we;
Tests: T1 T2 T3
36786 1/1 reg_we_check[84] = mio_periph_insel_26_gated_we;
Tests: T1 T2 T3
36787 1/1 reg_we_check[85] = mio_periph_insel_27_gated_we;
Tests: T1 T2 T3
36788 1/1 reg_we_check[86] = mio_periph_insel_28_gated_we;
Tests: T1 T2 T3
36789 1/1 reg_we_check[87] = mio_periph_insel_29_gated_we;
Tests: T1 T2 T3
36790 1/1 reg_we_check[88] = mio_periph_insel_30_gated_we;
Tests: T1 T2 T3
36791 1/1 reg_we_check[89] = mio_periph_insel_31_gated_we;
Tests: T1 T2 T3
36792 1/1 reg_we_check[90] = mio_periph_insel_32_gated_we;
Tests: T1 T2 T3
36793 1/1 reg_we_check[91] = mio_periph_insel_33_gated_we;
Tests: T1 T2 T3
36794 1/1 reg_we_check[92] = mio_periph_insel_34_gated_we;
Tests: T1 T2 T3
36795 1/1 reg_we_check[93] = mio_periph_insel_35_gated_we;
Tests: T1 T2 T3
36796 1/1 reg_we_check[94] = mio_periph_insel_36_gated_we;
Tests: T1 T2 T3
36797 1/1 reg_we_check[95] = mio_periph_insel_37_gated_we;
Tests: T1 T2 T3
36798 1/1 reg_we_check[96] = mio_periph_insel_38_gated_we;
Tests: T1 T2 T3
36799 1/1 reg_we_check[97] = mio_periph_insel_39_gated_we;
Tests: T1 T2 T3
36800 1/1 reg_we_check[98] = mio_periph_insel_40_gated_we;
Tests: T1 T2 T3
36801 1/1 reg_we_check[99] = mio_periph_insel_41_gated_we;
Tests: T1 T2 T3
36802 1/1 reg_we_check[100] = mio_periph_insel_42_gated_we;
Tests: T1 T2 T3
36803 1/1 reg_we_check[101] = mio_periph_insel_43_gated_we;
Tests: T1 T2 T3
36804 1/1 reg_we_check[102] = mio_periph_insel_44_gated_we;
Tests: T1 T2 T3
36805 1/1 reg_we_check[103] = mio_periph_insel_45_gated_we;
Tests: T1 T2 T3
36806 1/1 reg_we_check[104] = mio_periph_insel_46_gated_we;
Tests: T1 T2 T3
36807 1/1 reg_we_check[105] = mio_periph_insel_47_gated_we;
Tests: T1 T2 T3
36808 1/1 reg_we_check[106] = mio_periph_insel_48_gated_we;
Tests: T1 T2 T3
36809 1/1 reg_we_check[107] = mio_periph_insel_49_gated_we;
Tests: T1 T2 T3
36810 1/1 reg_we_check[108] = mio_periph_insel_50_gated_we;
Tests: T1 T2 T3
36811 1/1 reg_we_check[109] = mio_periph_insel_51_gated_we;
Tests: T1 T2 T3
36812 1/1 reg_we_check[110] = mio_periph_insel_52_gated_we;
Tests: T1 T2 T3
36813 1/1 reg_we_check[111] = mio_periph_insel_53_gated_we;
Tests: T1 T2 T3
36814 1/1 reg_we_check[112] = mio_periph_insel_54_gated_we;
Tests: T1 T2 T3
36815 1/1 reg_we_check[113] = mio_periph_insel_55_gated_we;
Tests: T1 T2 T3
36816 1/1 reg_we_check[114] = mio_periph_insel_56_gated_we;
Tests: T1 T2 T3
36817 1/1 reg_we_check[115] = mio_outsel_regwen_0_we;
Tests: T1 T2 T3
36818 1/1 reg_we_check[116] = mio_outsel_regwen_1_we;
Tests: T1 T2 T3
36819 1/1 reg_we_check[117] = mio_outsel_regwen_2_we;
Tests: T1 T2 T3
36820 1/1 reg_we_check[118] = mio_outsel_regwen_3_we;
Tests: T1 T2 T3
36821 1/1 reg_we_check[119] = mio_outsel_regwen_4_we;
Tests: T1 T2 T3
36822 1/1 reg_we_check[120] = mio_outsel_regwen_5_we;
Tests: T1 T2 T3
36823 1/1 reg_we_check[121] = mio_outsel_regwen_6_we;
Tests: T1 T2 T3
36824 1/1 reg_we_check[122] = mio_outsel_regwen_7_we;
Tests: T1 T2 T3
36825 1/1 reg_we_check[123] = mio_outsel_regwen_8_we;
Tests: T1 T2 T3
36826 1/1 reg_we_check[124] = mio_outsel_regwen_9_we;
Tests: T1 T2 T3
36827 1/1 reg_we_check[125] = mio_outsel_regwen_10_we;
Tests: T1 T2 T3
36828 1/1 reg_we_check[126] = mio_outsel_regwen_11_we;
Tests: T1 T2 T3
36829 1/1 reg_we_check[127] = mio_outsel_regwen_12_we;
Tests: T1 T2 T3
36830 1/1 reg_we_check[128] = mio_outsel_regwen_13_we;
Tests: T1 T2 T3
36831 1/1 reg_we_check[129] = mio_outsel_regwen_14_we;
Tests: T1 T2 T3
36832 1/1 reg_we_check[130] = mio_outsel_regwen_15_we;
Tests: T1 T2 T3
36833 1/1 reg_we_check[131] = mio_outsel_regwen_16_we;
Tests: T1 T2 T3
36834 1/1 reg_we_check[132] = mio_outsel_regwen_17_we;
Tests: T1 T2 T3
36835 1/1 reg_we_check[133] = mio_outsel_regwen_18_we;
Tests: T1 T2 T3
36836 1/1 reg_we_check[134] = mio_outsel_regwen_19_we;
Tests: T1 T2 T3
36837 1/1 reg_we_check[135] = mio_outsel_regwen_20_we;
Tests: T1 T2 T3
36838 1/1 reg_we_check[136] = mio_outsel_regwen_21_we;
Tests: T1 T2 T3
36839 1/1 reg_we_check[137] = mio_outsel_regwen_22_we;
Tests: T1 T2 T3
36840 1/1 reg_we_check[138] = mio_outsel_regwen_23_we;
Tests: T1 T2 T3
36841 1/1 reg_we_check[139] = mio_outsel_regwen_24_we;
Tests: T1 T2 T3
36842 1/1 reg_we_check[140] = mio_outsel_regwen_25_we;
Tests: T1 T2 T3
36843 1/1 reg_we_check[141] = mio_outsel_regwen_26_we;
Tests: T1 T2 T3
36844 1/1 reg_we_check[142] = mio_outsel_regwen_27_we;
Tests: T1 T2 T3
36845 1/1 reg_we_check[143] = mio_outsel_regwen_28_we;
Tests: T1 T2 T3
36846 1/1 reg_we_check[144] = mio_outsel_regwen_29_we;
Tests: T1 T2 T3
36847 1/1 reg_we_check[145] = mio_outsel_regwen_30_we;
Tests: T1 T2 T3
36848 1/1 reg_we_check[146] = mio_outsel_regwen_31_we;
Tests: T1 T2 T3
36849 1/1 reg_we_check[147] = mio_outsel_regwen_32_we;
Tests: T1 T2 T3
36850 1/1 reg_we_check[148] = mio_outsel_regwen_33_we;
Tests: T1 T2 T3
36851 1/1 reg_we_check[149] = mio_outsel_regwen_34_we;
Tests: T1 T2 T3
36852 1/1 reg_we_check[150] = mio_outsel_regwen_35_we;
Tests: T1 T2 T3
36853 1/1 reg_we_check[151] = mio_outsel_regwen_36_we;
Tests: T1 T2 T3
36854 1/1 reg_we_check[152] = mio_outsel_regwen_37_we;
Tests: T1 T2 T3
36855 1/1 reg_we_check[153] = mio_outsel_regwen_38_we;
Tests: T1 T2 T3
36856 1/1 reg_we_check[154] = mio_outsel_regwen_39_we;
Tests: T1 T2 T3
36857 1/1 reg_we_check[155] = mio_outsel_regwen_40_we;
Tests: T1 T2 T3
36858 1/1 reg_we_check[156] = mio_outsel_regwen_41_we;
Tests: T1 T2 T3
36859 1/1 reg_we_check[157] = mio_outsel_regwen_42_we;
Tests: T1 T2 T3
36860 1/1 reg_we_check[158] = mio_outsel_regwen_43_we;
Tests: T1 T2 T3
36861 1/1 reg_we_check[159] = mio_outsel_regwen_44_we;
Tests: T1 T2 T3
36862 1/1 reg_we_check[160] = mio_outsel_regwen_45_we;
Tests: T1 T2 T3
36863 1/1 reg_we_check[161] = mio_outsel_regwen_46_we;
Tests: T1 T2 T3
36864 1/1 reg_we_check[162] = mio_outsel_0_gated_we;
Tests: T1 T2 T3
36865 1/1 reg_we_check[163] = mio_outsel_1_gated_we;
Tests: T1 T2 T3
36866 1/1 reg_we_check[164] = mio_outsel_2_gated_we;
Tests: T1 T2 T3
36867 1/1 reg_we_check[165] = mio_outsel_3_gated_we;
Tests: T1 T2 T3
36868 1/1 reg_we_check[166] = mio_outsel_4_gated_we;
Tests: T1 T2 T3
36869 1/1 reg_we_check[167] = mio_outsel_5_gated_we;
Tests: T1 T2 T3
36870 1/1 reg_we_check[168] = mio_outsel_6_gated_we;
Tests: T1 T2 T3
36871 1/1 reg_we_check[169] = mio_outsel_7_gated_we;
Tests: T1 T2 T3
36872 1/1 reg_we_check[170] = mio_outsel_8_gated_we;
Tests: T1 T2 T3
36873 1/1 reg_we_check[171] = mio_outsel_9_gated_we;
Tests: T1 T2 T3
36874 1/1 reg_we_check[172] = mio_outsel_10_gated_we;
Tests: T1 T2 T3
36875 1/1 reg_we_check[173] = mio_outsel_11_gated_we;
Tests: T1 T2 T3
36876 1/1 reg_we_check[174] = mio_outsel_12_gated_we;
Tests: T1 T2 T3
36877 1/1 reg_we_check[175] = mio_outsel_13_gated_we;
Tests: T1 T2 T3
36878 1/1 reg_we_check[176] = mio_outsel_14_gated_we;
Tests: T1 T2 T3
36879 1/1 reg_we_check[177] = mio_outsel_15_gated_we;
Tests: T1 T2 T3
36880 1/1 reg_we_check[178] = mio_outsel_16_gated_we;
Tests: T1 T2 T3
36881 1/1 reg_we_check[179] = mio_outsel_17_gated_we;
Tests: T1 T2 T3
36882 1/1 reg_we_check[180] = mio_outsel_18_gated_we;
Tests: T1 T2 T3
36883 1/1 reg_we_check[181] = mio_outsel_19_gated_we;
Tests: T1 T2 T3
36884 1/1 reg_we_check[182] = mio_outsel_20_gated_we;
Tests: T1 T2 T3
36885 1/1 reg_we_check[183] = mio_outsel_21_gated_we;
Tests: T1 T2 T3
36886 1/1 reg_we_check[184] = mio_outsel_22_gated_we;
Tests: T1 T2 T3
36887 1/1 reg_we_check[185] = mio_outsel_23_gated_we;
Tests: T1 T2 T3
36888 1/1 reg_we_check[186] = mio_outsel_24_gated_we;
Tests: T1 T2 T3
36889 1/1 reg_we_check[187] = mio_outsel_25_gated_we;
Tests: T1 T2 T3
36890 1/1 reg_we_check[188] = mio_outsel_26_gated_we;
Tests: T1 T2 T3
36891 1/1 reg_we_check[189] = mio_outsel_27_gated_we;
Tests: T1 T2 T3
36892 1/1 reg_we_check[190] = mio_outsel_28_gated_we;
Tests: T1 T2 T3
36893 1/1 reg_we_check[191] = mio_outsel_29_gated_we;
Tests: T1 T2 T3
36894 1/1 reg_we_check[192] = mio_outsel_30_gated_we;
Tests: T1 T2 T3
36895 1/1 reg_we_check[193] = mio_outsel_31_gated_we;
Tests: T1 T2 T3
36896 1/1 reg_we_check[194] = mio_outsel_32_gated_we;
Tests: T1 T2 T3
36897 1/1 reg_we_check[195] = mio_outsel_33_gated_we;
Tests: T1 T2 T3
36898 1/1 reg_we_check[196] = mio_outsel_34_gated_we;
Tests: T1 T2 T3
36899 1/1 reg_we_check[197] = mio_outsel_35_gated_we;
Tests: T1 T2 T3
36900 1/1 reg_we_check[198] = mio_outsel_36_gated_we;
Tests: T1 T2 T3
36901 1/1 reg_we_check[199] = mio_outsel_37_gated_we;
Tests: T1 T2 T3
36902 1/1 reg_we_check[200] = mio_outsel_38_gated_we;
Tests: T1 T2 T3
36903 1/1 reg_we_check[201] = mio_outsel_39_gated_we;
Tests: T1 T2 T3
36904 1/1 reg_we_check[202] = mio_outsel_40_gated_we;
Tests: T1 T2 T3
36905 1/1 reg_we_check[203] = mio_outsel_41_gated_we;
Tests: T1 T2 T3
36906 1/1 reg_we_check[204] = mio_outsel_42_gated_we;
Tests: T1 T2 T3
36907 1/1 reg_we_check[205] = mio_outsel_43_gated_we;
Tests: T1 T2 T3
36908 1/1 reg_we_check[206] = mio_outsel_44_gated_we;
Tests: T1 T2 T3
36909 1/1 reg_we_check[207] = mio_outsel_45_gated_we;
Tests: T1 T2 T3
36910 1/1 reg_we_check[208] = mio_outsel_46_gated_we;
Tests: T1 T2 T3
36911 1/1 reg_we_check[209] = mio_pad_attr_regwen_0_we;
Tests: T1 T2 T3
36912 1/1 reg_we_check[210] = mio_pad_attr_regwen_1_we;
Tests: T1 T2 T3
36913 1/1 reg_we_check[211] = mio_pad_attr_regwen_2_we;
Tests: T1 T2 T3
36914 1/1 reg_we_check[212] = mio_pad_attr_regwen_3_we;
Tests: T1 T2 T3
36915 1/1 reg_we_check[213] = mio_pad_attr_regwen_4_we;
Tests: T1 T2 T3
36916 1/1 reg_we_check[214] = mio_pad_attr_regwen_5_we;
Tests: T1 T2 T3
36917 1/1 reg_we_check[215] = mio_pad_attr_regwen_6_we;
Tests: T1 T2 T3
36918 1/1 reg_we_check[216] = mio_pad_attr_regwen_7_we;
Tests: T1 T2 T3
36919 1/1 reg_we_check[217] = mio_pad_attr_regwen_8_we;
Tests: T1 T2 T3
36920 1/1 reg_we_check[218] = mio_pad_attr_regwen_9_we;
Tests: T1 T2 T3
36921 1/1 reg_we_check[219] = mio_pad_attr_regwen_10_we;
Tests: T1 T2 T3
36922 1/1 reg_we_check[220] = mio_pad_attr_regwen_11_we;
Tests: T1 T2 T3
36923 1/1 reg_we_check[221] = mio_pad_attr_regwen_12_we;
Tests: T1 T2 T3
36924 1/1 reg_we_check[222] = mio_pad_attr_regwen_13_we;
Tests: T1 T2 T3
36925 1/1 reg_we_check[223] = mio_pad_attr_regwen_14_we;
Tests: T1 T2 T3
36926 1/1 reg_we_check[224] = mio_pad_attr_regwen_15_we;
Tests: T1 T2 T3
36927 1/1 reg_we_check[225] = mio_pad_attr_regwen_16_we;
Tests: T1 T2 T3
36928 1/1 reg_we_check[226] = mio_pad_attr_regwen_17_we;
Tests: T1 T2 T3
36929 1/1 reg_we_check[227] = mio_pad_attr_regwen_18_we;
Tests: T1 T2 T3
36930 1/1 reg_we_check[228] = mio_pad_attr_regwen_19_we;
Tests: T1 T2 T3
36931 1/1 reg_we_check[229] = mio_pad_attr_regwen_20_we;
Tests: T1 T2 T3
36932 1/1 reg_we_check[230] = mio_pad_attr_regwen_21_we;
Tests: T1 T2 T3
36933 1/1 reg_we_check[231] = mio_pad_attr_regwen_22_we;
Tests: T1 T2 T3
36934 1/1 reg_we_check[232] = mio_pad_attr_regwen_23_we;
Tests: T1 T2 T3
36935 1/1 reg_we_check[233] = mio_pad_attr_regwen_24_we;
Tests: T1 T2 T3
36936 1/1 reg_we_check[234] = mio_pad_attr_regwen_25_we;
Tests: T1 T2 T3
36937 1/1 reg_we_check[235] = mio_pad_attr_regwen_26_we;
Tests: T1 T2 T3
36938 1/1 reg_we_check[236] = mio_pad_attr_regwen_27_we;
Tests: T1 T2 T3
36939 1/1 reg_we_check[237] = mio_pad_attr_regwen_28_we;
Tests: T1 T2 T3
36940 1/1 reg_we_check[238] = mio_pad_attr_regwen_29_we;
Tests: T1 T2 T3
36941 1/1 reg_we_check[239] = mio_pad_attr_regwen_30_we;
Tests: T1 T2 T3
36942 1/1 reg_we_check[240] = mio_pad_attr_regwen_31_we;
Tests: T1 T2 T3
36943 1/1 reg_we_check[241] = mio_pad_attr_regwen_32_we;
Tests: T1 T2 T3
36944 1/1 reg_we_check[242] = mio_pad_attr_regwen_33_we;
Tests: T1 T2 T3
36945 1/1 reg_we_check[243] = mio_pad_attr_regwen_34_we;
Tests: T1 T2 T3
36946 1/1 reg_we_check[244] = mio_pad_attr_regwen_35_we;
Tests: T1 T2 T3
36947 1/1 reg_we_check[245] = mio_pad_attr_regwen_36_we;
Tests: T1 T2 T3
36948 1/1 reg_we_check[246] = mio_pad_attr_regwen_37_we;
Tests: T1 T2 T3
36949 1/1 reg_we_check[247] = mio_pad_attr_regwen_38_we;
Tests: T1 T2 T3
36950 1/1 reg_we_check[248] = mio_pad_attr_regwen_39_we;
Tests: T1 T2 T3
36951 1/1 reg_we_check[249] = mio_pad_attr_regwen_40_we;
Tests: T1 T2 T3
36952 1/1 reg_we_check[250] = mio_pad_attr_regwen_41_we;
Tests: T1 T2 T3
36953 1/1 reg_we_check[251] = mio_pad_attr_regwen_42_we;
Tests: T1 T2 T3
36954 1/1 reg_we_check[252] = mio_pad_attr_regwen_43_we;
Tests: T1 T2 T3
36955 1/1 reg_we_check[253] = mio_pad_attr_regwen_44_we;
Tests: T1 T2 T3
36956 1/1 reg_we_check[254] = mio_pad_attr_regwen_45_we;
Tests: T1 T2 T3
36957 1/1 reg_we_check[255] = mio_pad_attr_regwen_46_we;
Tests: T1 T2 T3
36958 1/1 reg_we_check[256] = mio_pad_attr_0_gated_we;
Tests: T1 T2 T3
36959 1/1 reg_we_check[257] = mio_pad_attr_1_gated_we;
Tests: T1 T2 T3
36960 1/1 reg_we_check[258] = mio_pad_attr_2_gated_we;
Tests: T1 T2 T3
36961 1/1 reg_we_check[259] = mio_pad_attr_3_gated_we;
Tests: T1 T2 T3
36962 1/1 reg_we_check[260] = mio_pad_attr_4_gated_we;
Tests: T1 T2 T3
36963 1/1 reg_we_check[261] = mio_pad_attr_5_gated_we;
Tests: T1 T2 T3
36964 1/1 reg_we_check[262] = mio_pad_attr_6_gated_we;
Tests: T1 T2 T3
36965 1/1 reg_we_check[263] = mio_pad_attr_7_gated_we;
Tests: T1 T2 T3
36966 1/1 reg_we_check[264] = mio_pad_attr_8_gated_we;
Tests: T1 T2 T3
36967 1/1 reg_we_check[265] = mio_pad_attr_9_gated_we;
Tests: T1 T2 T3
36968 1/1 reg_we_check[266] = mio_pad_attr_10_gated_we;
Tests: T1 T2 T3
36969 1/1 reg_we_check[267] = mio_pad_attr_11_gated_we;
Tests: T1 T2 T3
36970 1/1 reg_we_check[268] = mio_pad_attr_12_gated_we;
Tests: T1 T2 T3
36971 1/1 reg_we_check[269] = mio_pad_attr_13_gated_we;
Tests: T1 T2 T3
36972 1/1 reg_we_check[270] = mio_pad_attr_14_gated_we;
Tests: T1 T2 T3
36973 1/1 reg_we_check[271] = mio_pad_attr_15_gated_we;
Tests: T1 T2 T3
36974 1/1 reg_we_check[272] = mio_pad_attr_16_gated_we;
Tests: T1 T2 T3
36975 1/1 reg_we_check[273] = mio_pad_attr_17_gated_we;
Tests: T1 T2 T3
36976 1/1 reg_we_check[274] = mio_pad_attr_18_gated_we;
Tests: T1 T2 T3
36977 1/1 reg_we_check[275] = mio_pad_attr_19_gated_we;
Tests: T1 T2 T3
36978 1/1 reg_we_check[276] = mio_pad_attr_20_gated_we;
Tests: T1 T2 T3
36979 1/1 reg_we_check[277] = mio_pad_attr_21_gated_we;
Tests: T1 T2 T3
36980 1/1 reg_we_check[278] = mio_pad_attr_22_gated_we;
Tests: T1 T2 T3
36981 1/1 reg_we_check[279] = mio_pad_attr_23_gated_we;
Tests: T1 T2 T3
36982 1/1 reg_we_check[280] = mio_pad_attr_24_gated_we;
Tests: T1 T2 T3
36983 1/1 reg_we_check[281] = mio_pad_attr_25_gated_we;
Tests: T1 T2 T3
36984 1/1 reg_we_check[282] = mio_pad_attr_26_gated_we;
Tests: T1 T2 T3
36985 1/1 reg_we_check[283] = mio_pad_attr_27_gated_we;
Tests: T1 T2 T3
36986 1/1 reg_we_check[284] = mio_pad_attr_28_gated_we;
Tests: T1 T2 T3
36987 1/1 reg_we_check[285] = mio_pad_attr_29_gated_we;
Tests: T1 T2 T3
36988 1/1 reg_we_check[286] = mio_pad_attr_30_gated_we;
Tests: T1 T2 T3
36989 1/1 reg_we_check[287] = mio_pad_attr_31_gated_we;
Tests: T1 T2 T3
36990 1/1 reg_we_check[288] = mio_pad_attr_32_gated_we;
Tests: T1 T2 T3
36991 1/1 reg_we_check[289] = mio_pad_attr_33_gated_we;
Tests: T1 T2 T3
36992 1/1 reg_we_check[290] = mio_pad_attr_34_gated_we;
Tests: T1 T2 T3
36993 1/1 reg_we_check[291] = mio_pad_attr_35_gated_we;
Tests: T1 T2 T3
36994 1/1 reg_we_check[292] = mio_pad_attr_36_gated_we;
Tests: T1 T2 T3
36995 1/1 reg_we_check[293] = mio_pad_attr_37_gated_we;
Tests: T1 T2 T3
36996 1/1 reg_we_check[294] = mio_pad_attr_38_gated_we;
Tests: T1 T2 T3
36997 1/1 reg_we_check[295] = mio_pad_attr_39_gated_we;
Tests: T1 T2 T3
36998 1/1 reg_we_check[296] = mio_pad_attr_40_gated_we;
Tests: T1 T2 T3
36999 1/1 reg_we_check[297] = mio_pad_attr_41_gated_we;
Tests: T1 T2 T3
37000 1/1 reg_we_check[298] = mio_pad_attr_42_gated_we;
Tests: T1 T2 T3
37001 1/1 reg_we_check[299] = mio_pad_attr_43_gated_we;
Tests: T1 T2 T3
37002 1/1 reg_we_check[300] = mio_pad_attr_44_gated_we;
Tests: T1 T2 T3
37003 1/1 reg_we_check[301] = mio_pad_attr_45_gated_we;
Tests: T1 T2 T3
37004 1/1 reg_we_check[302] = mio_pad_attr_46_gated_we;
Tests: T1 T2 T3
37005 1/1 reg_we_check[303] = dio_pad_attr_regwen_0_we;
Tests: T1 T2 T3
37006 1/1 reg_we_check[304] = dio_pad_attr_regwen_1_we;
Tests: T1 T2 T3
37007 1/1 reg_we_check[305] = dio_pad_attr_regwen_2_we;
Tests: T1 T2 T3
37008 1/1 reg_we_check[306] = dio_pad_attr_regwen_3_we;
Tests: T1 T2 T3
37009 1/1 reg_we_check[307] = dio_pad_attr_regwen_4_we;
Tests: T1 T2 T3
37010 1/1 reg_we_check[308] = dio_pad_attr_regwen_5_we;
Tests: T1 T2 T3
37011 1/1 reg_we_check[309] = dio_pad_attr_regwen_6_we;
Tests: T1 T2 T3
37012 1/1 reg_we_check[310] = dio_pad_attr_regwen_7_we;
Tests: T1 T2 T3
37013 1/1 reg_we_check[311] = dio_pad_attr_regwen_8_we;
Tests: T1 T2 T3
37014 1/1 reg_we_check[312] = dio_pad_attr_regwen_9_we;
Tests: T1 T2 T3
37015 1/1 reg_we_check[313] = dio_pad_attr_regwen_10_we;
Tests: T1 T2 T3
37016 1/1 reg_we_check[314] = dio_pad_attr_regwen_11_we;
Tests: T1 T2 T3
37017 1/1 reg_we_check[315] = dio_pad_attr_regwen_12_we;
Tests: T1 T2 T3
37018 1/1 reg_we_check[316] = dio_pad_attr_regwen_13_we;
Tests: T1 T2 T3
37019 1/1 reg_we_check[317] = dio_pad_attr_regwen_14_we;
Tests: T1 T2 T3
37020 1/1 reg_we_check[318] = dio_pad_attr_regwen_15_we;
Tests: T1 T2 T3
37021 1/1 reg_we_check[319] = dio_pad_attr_0_gated_we;
Tests: T1 T2 T3
37022 1/1 reg_we_check[320] = dio_pad_attr_1_gated_we;
Tests: T1 T2 T3
37023 1/1 reg_we_check[321] = dio_pad_attr_2_gated_we;
Tests: T1 T2 T3
37024 1/1 reg_we_check[322] = dio_pad_attr_3_gated_we;
Tests: T1 T2 T3
37025 1/1 reg_we_check[323] = dio_pad_attr_4_gated_we;
Tests: T1 T2 T3
37026 1/1 reg_we_check[324] = dio_pad_attr_5_gated_we;
Tests: T1 T2 T3
37027 1/1 reg_we_check[325] = dio_pad_attr_6_gated_we;
Tests: T1 T2 T3
37028 1/1 reg_we_check[326] = dio_pad_attr_7_gated_we;
Tests: T1 T2 T3
37029 1/1 reg_we_check[327] = dio_pad_attr_8_gated_we;
Tests: T1 T2 T3
37030 1/1 reg_we_check[328] = dio_pad_attr_9_gated_we;
Tests: T1 T2 T3
37031 1/1 reg_we_check[329] = dio_pad_attr_10_gated_we;
Tests: T1 T2 T3
37032 1/1 reg_we_check[330] = dio_pad_attr_11_gated_we;
Tests: T1 T2 T3
37033 1/1 reg_we_check[331] = dio_pad_attr_12_gated_we;
Tests: T1 T2 T3
37034 1/1 reg_we_check[332] = dio_pad_attr_13_gated_we;
Tests: T1 T2 T3
37035 1/1 reg_we_check[333] = dio_pad_attr_14_gated_we;
Tests: T1 T2 T3
37036 1/1 reg_we_check[334] = dio_pad_attr_15_gated_we;
Tests: T1 T2 T3
37037 1/1 reg_we_check[335] = mio_pad_sleep_status_0_we;
Tests: T1 T2 T3
37038 1/1 reg_we_check[336] = mio_pad_sleep_status_1_we;
Tests: T1 T2 T3
37039 1/1 reg_we_check[337] = mio_pad_sleep_regwen_0_we;
Tests: T1 T2 T3
37040 1/1 reg_we_check[338] = mio_pad_sleep_regwen_1_we;
Tests: T1 T2 T3
37041 1/1 reg_we_check[339] = mio_pad_sleep_regwen_2_we;
Tests: T1 T2 T3
37042 1/1 reg_we_check[340] = mio_pad_sleep_regwen_3_we;
Tests: T1 T2 T3
37043 1/1 reg_we_check[341] = mio_pad_sleep_regwen_4_we;
Tests: T1 T2 T3
37044 1/1 reg_we_check[342] = mio_pad_sleep_regwen_5_we;
Tests: T1 T2 T3
37045 1/1 reg_we_check[343] = mio_pad_sleep_regwen_6_we;
Tests: T1 T2 T3
37046 1/1 reg_we_check[344] = mio_pad_sleep_regwen_7_we;
Tests: T1 T2 T3
37047 1/1 reg_we_check[345] = mio_pad_sleep_regwen_8_we;
Tests: T1 T2 T3
37048 1/1 reg_we_check[346] = mio_pad_sleep_regwen_9_we;
Tests: T1 T2 T3
37049 1/1 reg_we_check[347] = mio_pad_sleep_regwen_10_we;
Tests: T1 T2 T3
37050 1/1 reg_we_check[348] = mio_pad_sleep_regwen_11_we;
Tests: T1 T2 T3
37051 1/1 reg_we_check[349] = mio_pad_sleep_regwen_12_we;
Tests: T1 T2 T3
37052 1/1 reg_we_check[350] = mio_pad_sleep_regwen_13_we;
Tests: T1 T2 T3
37053 1/1 reg_we_check[351] = mio_pad_sleep_regwen_14_we;
Tests: T1 T2 T3
37054 1/1 reg_we_check[352] = mio_pad_sleep_regwen_15_we;
Tests: T1 T2 T3
37055 1/1 reg_we_check[353] = mio_pad_sleep_regwen_16_we;
Tests: T1 T2 T3
37056 1/1 reg_we_check[354] = mio_pad_sleep_regwen_17_we;
Tests: T1 T2 T3
37057 1/1 reg_we_check[355] = mio_pad_sleep_regwen_18_we;
Tests: T1 T2 T3
37058 1/1 reg_we_check[356] = mio_pad_sleep_regwen_19_we;
Tests: T1 T2 T3
37059 1/1 reg_we_check[357] = mio_pad_sleep_regwen_20_we;
Tests: T1 T2 T3
37060 1/1 reg_we_check[358] = mio_pad_sleep_regwen_21_we;
Tests: T1 T2 T3
37061 1/1 reg_we_check[359] = mio_pad_sleep_regwen_22_we;
Tests: T1 T2 T3
37062 1/1 reg_we_check[360] = mio_pad_sleep_regwen_23_we;
Tests: T1 T2 T3
37063 1/1 reg_we_check[361] = mio_pad_sleep_regwen_24_we;
Tests: T1 T2 T3
37064 1/1 reg_we_check[362] = mio_pad_sleep_regwen_25_we;
Tests: T1 T2 T3
37065 1/1 reg_we_check[363] = mio_pad_sleep_regwen_26_we;
Tests: T1 T2 T3
37066 1/1 reg_we_check[364] = mio_pad_sleep_regwen_27_we;
Tests: T1 T2 T3
37067 1/1 reg_we_check[365] = mio_pad_sleep_regwen_28_we;
Tests: T1 T2 T3
37068 1/1 reg_we_check[366] = mio_pad_sleep_regwen_29_we;
Tests: T1 T2 T3
37069 1/1 reg_we_check[367] = mio_pad_sleep_regwen_30_we;
Tests: T1 T2 T3
37070 1/1 reg_we_check[368] = mio_pad_sleep_regwen_31_we;
Tests: T1 T2 T3
37071 1/1 reg_we_check[369] = mio_pad_sleep_regwen_32_we;
Tests: T1 T2 T3
37072 1/1 reg_we_check[370] = mio_pad_sleep_regwen_33_we;
Tests: T1 T2 T3
37073 1/1 reg_we_check[371] = mio_pad_sleep_regwen_34_we;
Tests: T1 T2 T3
37074 1/1 reg_we_check[372] = mio_pad_sleep_regwen_35_we;
Tests: T1 T2 T3
37075 1/1 reg_we_check[373] = mio_pad_sleep_regwen_36_we;
Tests: T1 T2 T3
37076 1/1 reg_we_check[374] = mio_pad_sleep_regwen_37_we;
Tests: T1 T2 T3
37077 1/1 reg_we_check[375] = mio_pad_sleep_regwen_38_we;
Tests: T1 T2 T3
37078 1/1 reg_we_check[376] = mio_pad_sleep_regwen_39_we;
Tests: T1 T2 T3
37079 1/1 reg_we_check[377] = mio_pad_sleep_regwen_40_we;
Tests: T1 T2 T3
37080 1/1 reg_we_check[378] = mio_pad_sleep_regwen_41_we;
Tests: T1 T2 T3
37081 1/1 reg_we_check[379] = mio_pad_sleep_regwen_42_we;
Tests: T1 T2 T3
37082 1/1 reg_we_check[380] = mio_pad_sleep_regwen_43_we;
Tests: T1 T2 T3
37083 1/1 reg_we_check[381] = mio_pad_sleep_regwen_44_we;
Tests: T1 T2 T3
37084 1/1 reg_we_check[382] = mio_pad_sleep_regwen_45_we;
Tests: T1 T2 T3
37085 1/1 reg_we_check[383] = mio_pad_sleep_regwen_46_we;
Tests: T1 T2 T3
37086 1/1 reg_we_check[384] = mio_pad_sleep_en_0_gated_we;
Tests: T1 T2 T3
37087 1/1 reg_we_check[385] = mio_pad_sleep_en_1_gated_we;
Tests: T1 T2 T3
37088 1/1 reg_we_check[386] = mio_pad_sleep_en_2_gated_we;
Tests: T1 T2 T3
37089 1/1 reg_we_check[387] = mio_pad_sleep_en_3_gated_we;
Tests: T1 T2 T3
37090 1/1 reg_we_check[388] = mio_pad_sleep_en_4_gated_we;
Tests: T1 T2 T3
37091 1/1 reg_we_check[389] = mio_pad_sleep_en_5_gated_we;
Tests: T1 T2 T3
37092 1/1 reg_we_check[390] = mio_pad_sleep_en_6_gated_we;
Tests: T1 T2 T3
37093 1/1 reg_we_check[391] = mio_pad_sleep_en_7_gated_we;
Tests: T1 T2 T3
37094 1/1 reg_we_check[392] = mio_pad_sleep_en_8_gated_we;
Tests: T1 T2 T3
37095 1/1 reg_we_check[393] = mio_pad_sleep_en_9_gated_we;
Tests: T1 T2 T3
37096 1/1 reg_we_check[394] = mio_pad_sleep_en_10_gated_we;
Tests: T1 T2 T3
37097 1/1 reg_we_check[395] = mio_pad_sleep_en_11_gated_we;
Tests: T1 T2 T3
37098 1/1 reg_we_check[396] = mio_pad_sleep_en_12_gated_we;
Tests: T1 T2 T3
37099 1/1 reg_we_check[397] = mio_pad_sleep_en_13_gated_we;
Tests: T1 T2 T3
37100 1/1 reg_we_check[398] = mio_pad_sleep_en_14_gated_we;
Tests: T1 T2 T3
37101 1/1 reg_we_check[399] = mio_pad_sleep_en_15_gated_we;
Tests: T1 T2 T3
37102 1/1 reg_we_check[400] = mio_pad_sleep_en_16_gated_we;
Tests: T1 T2 T3
37103 1/1 reg_we_check[401] = mio_pad_sleep_en_17_gated_we;
Tests: T1 T2 T3
37104 1/1 reg_we_check[402] = mio_pad_sleep_en_18_gated_we;
Tests: T1 T2 T3
37105 1/1 reg_we_check[403] = mio_pad_sleep_en_19_gated_we;
Tests: T1 T2 T3
37106 1/1 reg_we_check[404] = mio_pad_sleep_en_20_gated_we;
Tests: T1 T2 T3
37107 1/1 reg_we_check[405] = mio_pad_sleep_en_21_gated_we;
Tests: T1 T2 T3
37108 1/1 reg_we_check[406] = mio_pad_sleep_en_22_gated_we;
Tests: T1 T2 T3
37109 1/1 reg_we_check[407] = mio_pad_sleep_en_23_gated_we;
Tests: T1 T2 T3
37110 1/1 reg_we_check[408] = mio_pad_sleep_en_24_gated_we;
Tests: T1 T2 T3
37111 1/1 reg_we_check[409] = mio_pad_sleep_en_25_gated_we;
Tests: T1 T2 T3
37112 1/1 reg_we_check[410] = mio_pad_sleep_en_26_gated_we;
Tests: T1 T2 T3
37113 1/1 reg_we_check[411] = mio_pad_sleep_en_27_gated_we;
Tests: T1 T2 T3
37114 1/1 reg_we_check[412] = mio_pad_sleep_en_28_gated_we;
Tests: T1 T2 T3
37115 1/1 reg_we_check[413] = mio_pad_sleep_en_29_gated_we;
Tests: T1 T2 T3
37116 1/1 reg_we_check[414] = mio_pad_sleep_en_30_gated_we;
Tests: T1 T2 T3
37117 1/1 reg_we_check[415] = mio_pad_sleep_en_31_gated_we;
Tests: T1 T2 T3
37118 1/1 reg_we_check[416] = mio_pad_sleep_en_32_gated_we;
Tests: T1 T2 T3
37119 1/1 reg_we_check[417] = mio_pad_sleep_en_33_gated_we;
Tests: T1 T2 T3
37120 1/1 reg_we_check[418] = mio_pad_sleep_en_34_gated_we;
Tests: T1 T2 T3
37121 1/1 reg_we_check[419] = mio_pad_sleep_en_35_gated_we;
Tests: T1 T2 T3
37122 1/1 reg_we_check[420] = mio_pad_sleep_en_36_gated_we;
Tests: T1 T2 T3
37123 1/1 reg_we_check[421] = mio_pad_sleep_en_37_gated_we;
Tests: T1 T2 T3
37124 1/1 reg_we_check[422] = mio_pad_sleep_en_38_gated_we;
Tests: T1 T2 T3
37125 1/1 reg_we_check[423] = mio_pad_sleep_en_39_gated_we;
Tests: T1 T2 T3
37126 1/1 reg_we_check[424] = mio_pad_sleep_en_40_gated_we;
Tests: T1 T2 T3
37127 1/1 reg_we_check[425] = mio_pad_sleep_en_41_gated_we;
Tests: T1 T2 T3
37128 1/1 reg_we_check[426] = mio_pad_sleep_en_42_gated_we;
Tests: T1 T2 T3
37129 1/1 reg_we_check[427] = mio_pad_sleep_en_43_gated_we;
Tests: T1 T2 T3
37130 1/1 reg_we_check[428] = mio_pad_sleep_en_44_gated_we;
Tests: T1 T2 T3
37131 1/1 reg_we_check[429] = mio_pad_sleep_en_45_gated_we;
Tests: T1 T2 T3
37132 1/1 reg_we_check[430] = mio_pad_sleep_en_46_gated_we;
Tests: T1 T2 T3
37133 1/1 reg_we_check[431] = mio_pad_sleep_mode_0_gated_we;
Tests: T1 T2 T3
37134 1/1 reg_we_check[432] = mio_pad_sleep_mode_1_gated_we;
Tests: T1 T2 T3
37135 1/1 reg_we_check[433] = mio_pad_sleep_mode_2_gated_we;
Tests: T1 T2 T3
37136 1/1 reg_we_check[434] = mio_pad_sleep_mode_3_gated_we;
Tests: T1 T2 T3
37137 1/1 reg_we_check[435] = mio_pad_sleep_mode_4_gated_we;
Tests: T1 T2 T3
37138 1/1 reg_we_check[436] = mio_pad_sleep_mode_5_gated_we;
Tests: T1 T2 T3
37139 1/1 reg_we_check[437] = mio_pad_sleep_mode_6_gated_we;
Tests: T1 T2 T3
37140 1/1 reg_we_check[438] = mio_pad_sleep_mode_7_gated_we;
Tests: T1 T2 T3
37141 1/1 reg_we_check[439] = mio_pad_sleep_mode_8_gated_we;
Tests: T1 T2 T3
37142 1/1 reg_we_check[440] = mio_pad_sleep_mode_9_gated_we;
Tests: T1 T2 T3
37143 1/1 reg_we_check[441] = mio_pad_sleep_mode_10_gated_we;
Tests: T1 T2 T3
37144 1/1 reg_we_check[442] = mio_pad_sleep_mode_11_gated_we;
Tests: T1 T2 T3
37145 1/1 reg_we_check[443] = mio_pad_sleep_mode_12_gated_we;
Tests: T1 T2 T3
37146 1/1 reg_we_check[444] = mio_pad_sleep_mode_13_gated_we;
Tests: T1 T2 T3
37147 1/1 reg_we_check[445] = mio_pad_sleep_mode_14_gated_we;
Tests: T1 T2 T3
37148 1/1 reg_we_check[446] = mio_pad_sleep_mode_15_gated_we;
Tests: T1 T2 T3
37149 1/1 reg_we_check[447] = mio_pad_sleep_mode_16_gated_we;
Tests: T1 T2 T3
37150 1/1 reg_we_check[448] = mio_pad_sleep_mode_17_gated_we;
Tests: T1 T2 T3
37151 1/1 reg_we_check[449] = mio_pad_sleep_mode_18_gated_we;
Tests: T1 T2 T3
37152 1/1 reg_we_check[450] = mio_pad_sleep_mode_19_gated_we;
Tests: T1 T2 T3
37153 1/1 reg_we_check[451] = mio_pad_sleep_mode_20_gated_we;
Tests: T1 T2 T3
37154 1/1 reg_we_check[452] = mio_pad_sleep_mode_21_gated_we;
Tests: T1 T2 T3
37155 1/1 reg_we_check[453] = mio_pad_sleep_mode_22_gated_we;
Tests: T1 T2 T3
37156 1/1 reg_we_check[454] = mio_pad_sleep_mode_23_gated_we;
Tests: T1 T2 T3
37157 1/1 reg_we_check[455] = mio_pad_sleep_mode_24_gated_we;
Tests: T1 T2 T3
37158 1/1 reg_we_check[456] = mio_pad_sleep_mode_25_gated_we;
Tests: T1 T2 T3
37159 1/1 reg_we_check[457] = mio_pad_sleep_mode_26_gated_we;
Tests: T1 T2 T3
37160 1/1 reg_we_check[458] = mio_pad_sleep_mode_27_gated_we;
Tests: T1 T2 T3
37161 1/1 reg_we_check[459] = mio_pad_sleep_mode_28_gated_we;
Tests: T1 T2 T3
37162 1/1 reg_we_check[460] = mio_pad_sleep_mode_29_gated_we;
Tests: T1 T2 T3
37163 1/1 reg_we_check[461] = mio_pad_sleep_mode_30_gated_we;
Tests: T1 T2 T3
37164 1/1 reg_we_check[462] = mio_pad_sleep_mode_31_gated_we;
Tests: T1 T2 T3
37165 1/1 reg_we_check[463] = mio_pad_sleep_mode_32_gated_we;
Tests: T1 T2 T3
37166 1/1 reg_we_check[464] = mio_pad_sleep_mode_33_gated_we;
Tests: T1 T2 T3
37167 1/1 reg_we_check[465] = mio_pad_sleep_mode_34_gated_we;
Tests: T1 T2 T3
37168 1/1 reg_we_check[466] = mio_pad_sleep_mode_35_gated_we;
Tests: T1 T2 T3
37169 1/1 reg_we_check[467] = mio_pad_sleep_mode_36_gated_we;
Tests: T1 T2 T3
37170 1/1 reg_we_check[468] = mio_pad_sleep_mode_37_gated_we;
Tests: T1 T2 T3
37171 1/1 reg_we_check[469] = mio_pad_sleep_mode_38_gated_we;
Tests: T1 T2 T3
37172 1/1 reg_we_check[470] = mio_pad_sleep_mode_39_gated_we;
Tests: T1 T2 T3
37173 1/1 reg_we_check[471] = mio_pad_sleep_mode_40_gated_we;
Tests: T1 T2 T3
37174 1/1 reg_we_check[472] = mio_pad_sleep_mode_41_gated_we;
Tests: T1 T2 T3
37175 1/1 reg_we_check[473] = mio_pad_sleep_mode_42_gated_we;
Tests: T1 T2 T3
37176 1/1 reg_we_check[474] = mio_pad_sleep_mode_43_gated_we;
Tests: T1 T2 T3
37177 1/1 reg_we_check[475] = mio_pad_sleep_mode_44_gated_we;
Tests: T1 T2 T3
37178 1/1 reg_we_check[476] = mio_pad_sleep_mode_45_gated_we;
Tests: T1 T2 T3
37179 1/1 reg_we_check[477] = mio_pad_sleep_mode_46_gated_we;
Tests: T1 T2 T3
37180 1/1 reg_we_check[478] = dio_pad_sleep_status_we;
Tests: T1 T2 T3
37181 1/1 reg_we_check[479] = dio_pad_sleep_regwen_0_we;
Tests: T1 T2 T3
37182 1/1 reg_we_check[480] = dio_pad_sleep_regwen_1_we;
Tests: T1 T2 T3
37183 1/1 reg_we_check[481] = dio_pad_sleep_regwen_2_we;
Tests: T1 T2 T3
37184 1/1 reg_we_check[482] = dio_pad_sleep_regwen_3_we;
Tests: T1 T2 T3
37185 1/1 reg_we_check[483] = dio_pad_sleep_regwen_4_we;
Tests: T1 T2 T3
37186 1/1 reg_we_check[484] = dio_pad_sleep_regwen_5_we;
Tests: T1 T2 T3
37187 1/1 reg_we_check[485] = dio_pad_sleep_regwen_6_we;
Tests: T1 T2 T3
37188 1/1 reg_we_check[486] = dio_pad_sleep_regwen_7_we;
Tests: T1 T2 T3
37189 1/1 reg_we_check[487] = dio_pad_sleep_regwen_8_we;
Tests: T1 T2 T3
37190 1/1 reg_we_check[488] = dio_pad_sleep_regwen_9_we;
Tests: T1 T2 T3
37191 1/1 reg_we_check[489] = dio_pad_sleep_regwen_10_we;
Tests: T1 T2 T3
37192 1/1 reg_we_check[490] = dio_pad_sleep_regwen_11_we;
Tests: T1 T2 T3
37193 1/1 reg_we_check[491] = dio_pad_sleep_regwen_12_we;
Tests: T1 T2 T3
37194 1/1 reg_we_check[492] = dio_pad_sleep_regwen_13_we;
Tests: T1 T2 T3
37195 1/1 reg_we_check[493] = dio_pad_sleep_regwen_14_we;
Tests: T1 T2 T3
37196 1/1 reg_we_check[494] = dio_pad_sleep_regwen_15_we;
Tests: T1 T2 T3
37197 1/1 reg_we_check[495] = dio_pad_sleep_en_0_gated_we;
Tests: T1 T2 T3
37198 1/1 reg_we_check[496] = dio_pad_sleep_en_1_gated_we;
Tests: T1 T2 T3
37199 1/1 reg_we_check[497] = dio_pad_sleep_en_2_gated_we;
Tests: T1 T2 T3
37200 1/1 reg_we_check[498] = dio_pad_sleep_en_3_gated_we;
Tests: T1 T2 T3
37201 1/1 reg_we_check[499] = dio_pad_sleep_en_4_gated_we;
Tests: T1 T2 T3
37202 1/1 reg_we_check[500] = dio_pad_sleep_en_5_gated_we;
Tests: T1 T2 T3
37203 1/1 reg_we_check[501] = dio_pad_sleep_en_6_gated_we;
Tests: T1 T2 T3
37204 1/1 reg_we_check[502] = dio_pad_sleep_en_7_gated_we;
Tests: T1 T2 T3
37205 1/1 reg_we_check[503] = dio_pad_sleep_en_8_gated_we;
Tests: T1 T2 T3
37206 1/1 reg_we_check[504] = dio_pad_sleep_en_9_gated_we;
Tests: T1 T2 T3
37207 1/1 reg_we_check[505] = dio_pad_sleep_en_10_gated_we;
Tests: T1 T2 T3
37208 1/1 reg_we_check[506] = dio_pad_sleep_en_11_gated_we;
Tests: T1 T2 T3
37209 1/1 reg_we_check[507] = dio_pad_sleep_en_12_gated_we;
Tests: T1 T2 T3
37210 1/1 reg_we_check[508] = dio_pad_sleep_en_13_gated_we;
Tests: T1 T2 T3
37211 1/1 reg_we_check[509] = dio_pad_sleep_en_14_gated_we;
Tests: T1 T2 T3
37212 1/1 reg_we_check[510] = dio_pad_sleep_en_15_gated_we;
Tests: T1 T2 T3
37213 1/1 reg_we_check[511] = dio_pad_sleep_mode_0_gated_we;
Tests: T1 T2 T3
37214 1/1 reg_we_check[512] = dio_pad_sleep_mode_1_gated_we;
Tests: T1 T2 T3
37215 1/1 reg_we_check[513] = dio_pad_sleep_mode_2_gated_we;
Tests: T1 T2 T3
37216 1/1 reg_we_check[514] = dio_pad_sleep_mode_3_gated_we;
Tests: T1 T2 T3
37217 1/1 reg_we_check[515] = dio_pad_sleep_mode_4_gated_we;
Tests: T1 T2 T3
37218 1/1 reg_we_check[516] = dio_pad_sleep_mode_5_gated_we;
Tests: T1 T2 T3
37219 1/1 reg_we_check[517] = dio_pad_sleep_mode_6_gated_we;
Tests: T1 T2 T3
37220 1/1 reg_we_check[518] = dio_pad_sleep_mode_7_gated_we;
Tests: T1 T2 T3
37221 1/1 reg_we_check[519] = dio_pad_sleep_mode_8_gated_we;
Tests: T1 T2 T3
37222 1/1 reg_we_check[520] = dio_pad_sleep_mode_9_gated_we;
Tests: T1 T2 T3
37223 1/1 reg_we_check[521] = dio_pad_sleep_mode_10_gated_we;
Tests: T1 T2 T3
37224 1/1 reg_we_check[522] = dio_pad_sleep_mode_11_gated_we;
Tests: T1 T2 T3
37225 1/1 reg_we_check[523] = dio_pad_sleep_mode_12_gated_we;
Tests: T1 T2 T3
37226 1/1 reg_we_check[524] = dio_pad_sleep_mode_13_gated_we;
Tests: T1 T2 T3
37227 1/1 reg_we_check[525] = dio_pad_sleep_mode_14_gated_we;
Tests: T1 T2 T3
37228 1/1 reg_we_check[526] = dio_pad_sleep_mode_15_gated_we;
Tests: T1 T2 T3
37229 1/1 reg_we_check[527] = wkup_detector_regwen_0_we;
Tests: T1 T2 T3
37230 1/1 reg_we_check[528] = wkup_detector_regwen_1_we;
Tests: T1 T2 T3
37231 1/1 reg_we_check[529] = wkup_detector_regwen_2_we;
Tests: T1 T2 T3
37232 1/1 reg_we_check[530] = wkup_detector_regwen_3_we;
Tests: T1 T2 T3
37233 1/1 reg_we_check[531] = wkup_detector_regwen_4_we;
Tests: T1 T2 T3
37234 1/1 reg_we_check[532] = wkup_detector_regwen_5_we;
Tests: T1 T2 T3
37235 1/1 reg_we_check[533] = wkup_detector_regwen_6_we;
Tests: T1 T2 T3
37236 1/1 reg_we_check[534] = wkup_detector_regwen_7_we;
Tests: T1 T2 T3
37237 1/1 reg_we_check[535] = wkup_detector_en_0_we;
Tests: T1 T2 T3
37238 1/1 reg_we_check[536] = wkup_detector_en_1_we;
Tests: T1 T2 T3
37239 1/1 reg_we_check[537] = wkup_detector_en_2_we;
Tests: T1 T2 T3
37240 1/1 reg_we_check[538] = wkup_detector_en_3_we;
Tests: T1 T2 T3
37241 1/1 reg_we_check[539] = wkup_detector_en_4_we;
Tests: T1 T2 T3
37242 1/1 reg_we_check[540] = wkup_detector_en_5_we;
Tests: T1 T2 T3
37243 1/1 reg_we_check[541] = wkup_detector_en_6_we;
Tests: T1 T2 T3
37244 1/1 reg_we_check[542] = wkup_detector_en_7_we;
Tests: T1 T2 T3
37245 1/1 reg_we_check[543] = wkup_detector_0_we;
Tests: T1 T2 T3
37246 1/1 reg_we_check[544] = wkup_detector_1_we;
Tests: T1 T2 T3
37247 1/1 reg_we_check[545] = wkup_detector_2_we;
Tests: T1 T2 T3
37248 1/1 reg_we_check[546] = wkup_detector_3_we;
Tests: T1 T2 T3
37249 1/1 reg_we_check[547] = wkup_detector_4_we;
Tests: T1 T2 T3
37250 1/1 reg_we_check[548] = wkup_detector_5_we;
Tests: T1 T2 T3
37251 1/1 reg_we_check[549] = wkup_detector_6_we;
Tests: T1 T2 T3
37252 1/1 reg_we_check[550] = wkup_detector_7_we;
Tests: T1 T2 T3
37253 1/1 reg_we_check[551] = wkup_detector_cnt_th_0_we;
Tests: T1 T2 T3
37254 1/1 reg_we_check[552] = wkup_detector_cnt_th_1_we;
Tests: T1 T2 T3
37255 1/1 reg_we_check[553] = wkup_detector_cnt_th_2_we;
Tests: T1 T2 T3
37256 1/1 reg_we_check[554] = wkup_detector_cnt_th_3_we;
Tests: T1 T2 T3
37257 1/1 reg_we_check[555] = wkup_detector_cnt_th_4_we;
Tests: T1 T2 T3
37258 1/1 reg_we_check[556] = wkup_detector_cnt_th_5_we;
Tests: T1 T2 T3
37259 1/1 reg_we_check[557] = wkup_detector_cnt_th_6_we;
Tests: T1 T2 T3
37260 1/1 reg_we_check[558] = wkup_detector_cnt_th_7_we;
Tests: T1 T2 T3
37261 1/1 reg_we_check[559] = wkup_detector_padsel_0_gated_we;
Tests: T1 T2 T3
37262 1/1 reg_we_check[560] = wkup_detector_padsel_1_gated_we;
Tests: T1 T2 T3
37263 1/1 reg_we_check[561] = wkup_detector_padsel_2_gated_we;
Tests: T1 T2 T3
37264 1/1 reg_we_check[562] = wkup_detector_padsel_3_gated_we;
Tests: T1 T2 T3
37265 1/1 reg_we_check[563] = wkup_detector_padsel_4_gated_we;
Tests: T1 T2 T3
37266 1/1 reg_we_check[564] = wkup_detector_padsel_5_gated_we;
Tests: T1 T2 T3
37267 1/1 reg_we_check[565] = wkup_detector_padsel_6_gated_we;
Tests: T1 T2 T3
37268 1/1 reg_we_check[566] = wkup_detector_padsel_7_gated_we;
Tests: T1 T2 T3
37269 1/1 reg_we_check[567] = wkup_cause_we;
Tests: T1 T2 T3
37270 end
37271
37272 // Read data return
37273 always_comb begin
37274 1/1 reg_rdata_next = '0;
Tests: T1 T2 T3
37275 1/1 unique case (1'b1)
Tests: T1 T2 T3
37276 addr_hit[0]: begin
37277 1/1 reg_rdata_next[0] = '0;
Tests: T1 T2 T3
37278 end
37279
37280 addr_hit[1]: begin
37281 1/1 reg_rdata_next[0] = mio_periph_insel_regwen_0_qs;
Tests: T1 T2 T3
37282 end
37283
37284 addr_hit[2]: begin
37285 1/1 reg_rdata_next[0] = mio_periph_insel_regwen_1_qs;
Tests: T1 T2 T3
37286 end
37287
37288 addr_hit[3]: begin
37289 1/1 reg_rdata_next[0] = mio_periph_insel_regwen_2_qs;
Tests: T1 T2 T3
37290 end
37291
37292 addr_hit[4]: begin
37293 1/1 reg_rdata_next[0] = mio_periph_insel_regwen_3_qs;
Tests: T1 T2 T3
37294 end
37295
37296 addr_hit[5]: begin
37297 1/1 reg_rdata_next[0] = mio_periph_insel_regwen_4_qs;
Tests: T1 T2 T3
37298 end
37299
37300 addr_hit[6]: begin
37301 1/1 reg_rdata_next[0] = mio_periph_insel_regwen_5_qs;
Tests: T1 T2 T3
37302 end
37303
37304 addr_hit[7]: begin
37305 1/1 reg_rdata_next[0] = mio_periph_insel_regwen_6_qs;
Tests: T1 T2 T3
37306 end
37307
37308 addr_hit[8]: begin
37309 1/1 reg_rdata_next[0] = mio_periph_insel_regwen_7_qs;
Tests: T1 T2 T3
37310 end
37311
37312 addr_hit[9]: begin
37313 1/1 reg_rdata_next[0] = mio_periph_insel_regwen_8_qs;
Tests: T1 T2 T3
37314 end
37315
37316 addr_hit[10]: begin
37317 1/1 reg_rdata_next[0] = mio_periph_insel_regwen_9_qs;
Tests: T1 T2 T3
37318 end
37319
37320 addr_hit[11]: begin
37321 1/1 reg_rdata_next[0] = mio_periph_insel_regwen_10_qs;
Tests: T1 T2 T3
37322 end
37323
37324 addr_hit[12]: begin
37325 1/1 reg_rdata_next[0] = mio_periph_insel_regwen_11_qs;
Tests: T1 T2 T3
37326 end
37327
37328 addr_hit[13]: begin
37329 1/1 reg_rdata_next[0] = mio_periph_insel_regwen_12_qs;
Tests: T1 T2 T3
37330 end
37331
37332 addr_hit[14]: begin
37333 1/1 reg_rdata_next[0] = mio_periph_insel_regwen_13_qs;
Tests: T1 T2 T3
37334 end
37335
37336 addr_hit[15]: begin
37337 1/1 reg_rdata_next[0] = mio_periph_insel_regwen_14_qs;
Tests: T1 T2 T3
37338 end
37339
37340 addr_hit[16]: begin
37341 1/1 reg_rdata_next[0] = mio_periph_insel_regwen_15_qs;
Tests: T1 T2 T3
37342 end
37343
37344 addr_hit[17]: begin
37345 1/1 reg_rdata_next[0] = mio_periph_insel_regwen_16_qs;
Tests: T1 T2 T3
37346 end
37347
37348 addr_hit[18]: begin
37349 1/1 reg_rdata_next[0] = mio_periph_insel_regwen_17_qs;
Tests: T1 T2 T3
37350 end
37351
37352 addr_hit[19]: begin
37353 1/1 reg_rdata_next[0] = mio_periph_insel_regwen_18_qs;
Tests: T1 T2 T3
37354 end
37355
37356 addr_hit[20]: begin
37357 1/1 reg_rdata_next[0] = mio_periph_insel_regwen_19_qs;
Tests: T1 T2 T3
37358 end
37359
37360 addr_hit[21]: begin
37361 1/1 reg_rdata_next[0] = mio_periph_insel_regwen_20_qs;
Tests: T1 T2 T3
37362 end
37363
37364 addr_hit[22]: begin
37365 1/1 reg_rdata_next[0] = mio_periph_insel_regwen_21_qs;
Tests: T1 T2 T3
37366 end
37367
37368 addr_hit[23]: begin
37369 1/1 reg_rdata_next[0] = mio_periph_insel_regwen_22_qs;
Tests: T1 T2 T3
37370 end
37371
37372 addr_hit[24]: begin
37373 1/1 reg_rdata_next[0] = mio_periph_insel_regwen_23_qs;
Tests: T1 T2 T3
37374 end
37375
37376 addr_hit[25]: begin
37377 1/1 reg_rdata_next[0] = mio_periph_insel_regwen_24_qs;
Tests: T1 T2 T3
37378 end
37379
37380 addr_hit[26]: begin
37381 1/1 reg_rdata_next[0] = mio_periph_insel_regwen_25_qs;
Tests: T1 T2 T3
37382 end
37383
37384 addr_hit[27]: begin
37385 1/1 reg_rdata_next[0] = mio_periph_insel_regwen_26_qs;
Tests: T1 T2 T3
37386 end
37387
37388 addr_hit[28]: begin
37389 1/1 reg_rdata_next[0] = mio_periph_insel_regwen_27_qs;
Tests: T1 T2 T3
37390 end
37391
37392 addr_hit[29]: begin
37393 1/1 reg_rdata_next[0] = mio_periph_insel_regwen_28_qs;
Tests: T1 T2 T3
37394 end
37395
37396 addr_hit[30]: begin
37397 1/1 reg_rdata_next[0] = mio_periph_insel_regwen_29_qs;
Tests: T1 T2 T3
37398 end
37399
37400 addr_hit[31]: begin
37401 1/1 reg_rdata_next[0] = mio_periph_insel_regwen_30_qs;
Tests: T1 T2 T3
37402 end
37403
37404 addr_hit[32]: begin
37405 1/1 reg_rdata_next[0] = mio_periph_insel_regwen_31_qs;
Tests: T1 T2 T3
37406 end
37407
37408 addr_hit[33]: begin
37409 1/1 reg_rdata_next[0] = mio_periph_insel_regwen_32_qs;
Tests: T1 T2 T3
37410 end
37411
37412 addr_hit[34]: begin
37413 1/1 reg_rdata_next[0] = mio_periph_insel_regwen_33_qs;
Tests: T1 T2 T3
37414 end
37415
37416 addr_hit[35]: begin
37417 1/1 reg_rdata_next[0] = mio_periph_insel_regwen_34_qs;
Tests: T1 T2 T3
37418 end
37419
37420 addr_hit[36]: begin
37421 1/1 reg_rdata_next[0] = mio_periph_insel_regwen_35_qs;
Tests: T1 T2 T3
37422 end
37423
37424 addr_hit[37]: begin
37425 1/1 reg_rdata_next[0] = mio_periph_insel_regwen_36_qs;
Tests: T1 T2 T3
37426 end
37427
37428 addr_hit[38]: begin
37429 1/1 reg_rdata_next[0] = mio_periph_insel_regwen_37_qs;
Tests: T1 T2 T3
37430 end
37431
37432 addr_hit[39]: begin
37433 1/1 reg_rdata_next[0] = mio_periph_insel_regwen_38_qs;
Tests: T9 T10 T11
37434 end
37435
37436 addr_hit[40]: begin
37437 1/1 reg_rdata_next[0] = mio_periph_insel_regwen_39_qs;
Tests: T9 T10 T11
37438 end
37439
37440 addr_hit[41]: begin
37441 1/1 reg_rdata_next[0] = mio_periph_insel_regwen_40_qs;
Tests: T9 T10 T11
37442 end
37443
37444 addr_hit[42]: begin
37445 1/1 reg_rdata_next[0] = mio_periph_insel_regwen_41_qs;
Tests: T9 T10 T11
37446 end
37447
37448 addr_hit[43]: begin
37449 1/1 reg_rdata_next[0] = mio_periph_insel_regwen_42_qs;
Tests: T1 T2 T3
37450 end
37451
37452 addr_hit[44]: begin
37453 1/1 reg_rdata_next[0] = mio_periph_insel_regwen_43_qs;
Tests: T1 T2 T3
37454 end
37455
37456 addr_hit[45]: begin
37457 1/1 reg_rdata_next[0] = mio_periph_insel_regwen_44_qs;
Tests: T10 T68 T11
37458 end
37459
37460 addr_hit[46]: begin
37461 1/1 reg_rdata_next[0] = mio_periph_insel_regwen_45_qs;
Tests: T26 T10 T11
37462 end
37463
37464 addr_hit[47]: begin
37465 1/1 reg_rdata_next[0] = mio_periph_insel_regwen_46_qs;
Tests: T12 T10 T11
37466 end
37467
37468 addr_hit[48]: begin
37469 1/1 reg_rdata_next[0] = mio_periph_insel_regwen_47_qs;
Tests: T10 T11 T80
37470 end
37471
37472 addr_hit[49]: begin
37473 1/1 reg_rdata_next[0] = mio_periph_insel_regwen_48_qs;
Tests: T10 T11 T80
37474 end
37475
37476 addr_hit[50]: begin
37477 1/1 reg_rdata_next[0] = mio_periph_insel_regwen_49_qs;
Tests: T10 T11 T80
37478 end
37479
37480 addr_hit[51]: begin
37481 1/1 reg_rdata_next[0] = mio_periph_insel_regwen_50_qs;
Tests: T10 T11 T28
37482 end
37483
37484 addr_hit[52]: begin
37485 1/1 reg_rdata_next[0] = mio_periph_insel_regwen_51_qs;
Tests: T10 T11 T28
37486 end
37487
37488 addr_hit[53]: begin
37489 1/1 reg_rdata_next[0] = mio_periph_insel_regwen_52_qs;
Tests: T10 T11 T28
37490 end
37491
37492 addr_hit[54]: begin
37493 1/1 reg_rdata_next[0] = mio_periph_insel_regwen_53_qs;
Tests: T10 T11 T28
37494 end
37495
37496 addr_hit[55]: begin
37497 1/1 reg_rdata_next[0] = mio_periph_insel_regwen_54_qs;
Tests: T10 T11 T28
37498 end
37499
37500 addr_hit[56]: begin
37501 1/1 reg_rdata_next[0] = mio_periph_insel_regwen_55_qs;
Tests: T10 T11 T28
37502 end
37503
37504 addr_hit[57]: begin
37505 1/1 reg_rdata_next[0] = mio_periph_insel_regwen_56_qs;
Tests: T7 T31 T8
37506 end
37507
37508 addr_hit[58]: begin
37509 1/1 reg_rdata_next[5:0] = mio_periph_insel_0_qs;
Tests: T6 T25 T27
37510 end
37511
37512 addr_hit[59]: begin
37513 1/1 reg_rdata_next[5:0] = mio_periph_insel_1_qs;
Tests: T25 T27 T80
37514 end
37515
37516 addr_hit[60]: begin
37517 1/1 reg_rdata_next[5:0] = mio_periph_insel_2_qs;
Tests: T25 T27 T80
37518 end
37519
37520 addr_hit[61]: begin
37521 1/1 reg_rdata_next[5:0] = mio_periph_insel_3_qs;
Tests: T25 T27 T80
37522 end
37523
37524 addr_hit[62]: begin
37525 1/1 reg_rdata_next[5:0] = mio_periph_insel_4_qs;
Tests: T25 T27 T80
37526 end
37527
37528 addr_hit[63]: begin
37529 1/1 reg_rdata_next[5:0] = mio_periph_insel_5_qs;
Tests: T25 T27 T80
37530 end
37531
37532 addr_hit[64]: begin
37533 1/1 reg_rdata_next[5:0] = mio_periph_insel_6_qs;
Tests: T25 T27 T86
37534 end
37535
37536 addr_hit[65]: begin
37537 1/1 reg_rdata_next[5:0] = mio_periph_insel_7_qs;
Tests: T25 T27 T130
37538 end
37539
37540 addr_hit[66]: begin
37541 1/1 reg_rdata_next[5:0] = mio_periph_insel_8_qs;
Tests: T25 T27 T80
37542 end
37543
37544 addr_hit[67]: begin
37545 1/1 reg_rdata_next[5:0] = mio_periph_insel_9_qs;
Tests: T27 T130 T270
37546 end
37547
37548 addr_hit[68]: begin
37549 1/1 reg_rdata_next[5:0] = mio_periph_insel_10_qs;
Tests: T27 T130 T270
37550 end
37551
37552 addr_hit[69]: begin
37553 1/1 reg_rdata_next[5:0] = mio_periph_insel_11_qs;
Tests: T27 T87 T130
37554 end
37555
37556 addr_hit[70]: begin
37557 1/1 reg_rdata_next[5:0] = mio_periph_insel_12_qs;
Tests: T27 T130 T270
37558 end
37559
37560 addr_hit[71]: begin
37561 1/1 reg_rdata_next[5:0] = mio_periph_insel_13_qs;
Tests: T27 T130 T270
37562 end
37563
37564 addr_hit[72]: begin
37565 1/1 reg_rdata_next[5:0] = mio_periph_insel_14_qs;
Tests: T27 T80 T104
37566 end
37567
37568 addr_hit[73]: begin
37569 1/1 reg_rdata_next[5:0] = mio_periph_insel_15_qs;
Tests: T27 T80 T104
37570 end
37571
37572 addr_hit[74]: begin
37573 1/1 reg_rdata_next[5:0] = mio_periph_insel_16_qs;
Tests: T27 T80 T104
37574 end
37575
37576 addr_hit[75]: begin
37577 1/1 reg_rdata_next[5:0] = mio_periph_insel_17_qs;
Tests: T27 T80 T104
37578 end
37579
37580 addr_hit[76]: begin
37581 1/1 reg_rdata_next[5:0] = mio_periph_insel_18_qs;
Tests: T27 T80 T104
37582 end
37583
37584 addr_hit[77]: begin
37585 1/1 reg_rdata_next[5:0] = mio_periph_insel_19_qs;
Tests: T27 T80 T104
37586 end
37587
37588 addr_hit[78]: begin
37589 1/1 reg_rdata_next[5:0] = mio_periph_insel_20_qs;
Tests: T27 T80 T104
37590 end
37591
37592 addr_hit[79]: begin
37593 1/1 reg_rdata_next[5:0] = mio_periph_insel_21_qs;
Tests: T27 T80 T104
37594 end
37595
37596 addr_hit[80]: begin
37597 1/1 reg_rdata_next[5:0] = mio_periph_insel_22_qs;
Tests: T1 T2 T3
37598 end
37599
37600 addr_hit[81]: begin
37601 1/1 reg_rdata_next[5:0] = mio_periph_insel_23_qs;
Tests: T1 T2 T3
37602 end
37603
37604 addr_hit[82]: begin
37605 1/1 reg_rdata_next[5:0] = mio_periph_insel_24_qs;
Tests: T1 T2 T3
37606 end
37607
37608 addr_hit[83]: begin
37609 1/1 reg_rdata_next[5:0] = mio_periph_insel_25_qs;
Tests: T27 T80 T104
37610 end
37611
37612 addr_hit[84]: begin
37613 1/1 reg_rdata_next[5:0] = mio_periph_insel_26_qs;
Tests: T27 T80 T104
37614 end
37615
37616 addr_hit[85]: begin
37617 1/1 reg_rdata_next[5:0] = mio_periph_insel_27_qs;
Tests: T27 T80 T104
37618 end
37619
37620 addr_hit[86]: begin
37621 1/1 reg_rdata_next[5:0] = mio_periph_insel_28_qs;
Tests: T27 T80 T104
37622 end
37623
37624 addr_hit[87]: begin
37625 1/1 reg_rdata_next[5:0] = mio_periph_insel_29_qs;
Tests: T27 T80 T104
37626 end
37627
37628 addr_hit[88]: begin
37629 1/1 reg_rdata_next[5:0] = mio_periph_insel_30_qs;
Tests: T27 T80 T104
37630 end
37631
37632 addr_hit[89]: begin
37633 1/1 reg_rdata_next[5:0] = mio_periph_insel_31_qs;
Tests: T27 T80 T104
37634 end
37635
37636 addr_hit[90]: begin
37637 1/1 reg_rdata_next[5:0] = mio_periph_insel_32_qs;
Tests: T62 T80 T104
37638 end
37639
37640 addr_hit[91]: begin
37641 1/1 reg_rdata_next[5:0] = mio_periph_insel_33_qs;
Tests: T62 T80 T104
37642 end
37643
37644 addr_hit[92]: begin
37645 1/1 reg_rdata_next[5:0] = mio_periph_insel_34_qs;
Tests: T64 T65 T80
37646 end
37647
37648 addr_hit[93]: begin
37649 1/1 reg_rdata_next[5:0] = mio_periph_insel_35_qs;
Tests: T64 T65 T80
37650 end
37651
37652 addr_hit[94]: begin
37653 1/1 reg_rdata_next[5:0] = mio_periph_insel_36_qs;
Tests: T66 T80 T104
37654 end
37655
37656 addr_hit[95]: begin
37657 1/1 reg_rdata_next[5:0] = mio_periph_insel_37_qs;
Tests: T45 T66 T80
37658 end
37659
37660 addr_hit[96]: begin
37661 1/1 reg_rdata_next[5:0] = mio_periph_insel_38_qs;
Tests: T9 T80 T104
37662 end
37663
37664 addr_hit[97]: begin
37665 1/1 reg_rdata_next[5:0] = mio_periph_insel_39_qs;
Tests: T9 T80 T104
37666 end
37667
37668 addr_hit[98]: begin
37669 1/1 reg_rdata_next[5:0] = mio_periph_insel_40_qs;
Tests: T9 T80 T104
37670 end
37671
37672 addr_hit[99]: begin
37673 1/1 reg_rdata_next[5:0] = mio_periph_insel_41_qs;
Tests: T9 T10 T11
37674 end
37675
37676 addr_hit[100]: begin
37677 1/1 reg_rdata_next[5:0] = mio_periph_insel_42_qs;
Tests: T1 T2 T3
37678 end
37679
37680 addr_hit[101]: begin
37681 1/1 reg_rdata_next[5:0] = mio_periph_insel_43_qs;
Tests: T1 T2 T3
37682 end
37683
37684 addr_hit[102]: begin
37685 1/1 reg_rdata_next[5:0] = mio_periph_insel_44_qs;
Tests: T68 T80 T104
37686 end
37687
37688 addr_hit[103]: begin
37689 1/1 reg_rdata_next[5:0] = mio_periph_insel_45_qs;
Tests: T26 T70 T80
37690 end
37691
37692 addr_hit[104]: begin
37693 1/1 reg_rdata_next[5:0] = mio_periph_insel_46_qs;
Tests: T12 T80 T104
37694 end
37695
37696 addr_hit[105]: begin
37697 1/1 reg_rdata_next[5:0] = mio_periph_insel_47_qs;
Tests: T80 T104 T265
37698 end
37699
37700 addr_hit[106]: begin
37701 1/1 reg_rdata_next[5:0] = mio_periph_insel_48_qs;
Tests: T80 T104 T265
37702 end
37703
37704 addr_hit[107]: begin
37705 1/1 reg_rdata_next[5:0] = mio_periph_insel_49_qs;
Tests: T80 T104 T265
37706 end
37707
37708 addr_hit[108]: begin
37709 1/1 reg_rdata_next[5:0] = mio_periph_insel_50_qs;
Tests: T28 T15 T80
37710 end
37711
37712 addr_hit[109]: begin
37713 1/1 reg_rdata_next[5:0] = mio_periph_insel_51_qs;
Tests: T28 T13 T80
37714 end
37715
37716 addr_hit[110]: begin
37717 1/1 reg_rdata_next[5:0] = mio_periph_insel_52_qs;
Tests: T28 T13 T80
37718 end
37719
37720 addr_hit[111]: begin
37721 1/1 reg_rdata_next[5:0] = mio_periph_insel_53_qs;
Tests: T28 T13 T80
37722 end
37723
37724 addr_hit[112]: begin
37725 1/1 reg_rdata_next[5:0] = mio_periph_insel_54_qs;
Tests: T28 T13 T15
37726 end
37727
37728 addr_hit[113]: begin
37729 1/1 reg_rdata_next[5:0] = mio_periph_insel_55_qs;
Tests: T28 T15 T80
37730 end
37731
37732 addr_hit[114]: begin
37733 1/1 reg_rdata_next[5:0] = mio_periph_insel_56_qs;
Tests: T7 T31 T8
37734 end
37735
37736 addr_hit[115]: begin
37737 1/1 reg_rdata_next[0] = mio_outsel_regwen_0_qs;
Tests: T25 T27 T80
37738 end
37739
37740 addr_hit[116]: begin
37741 1/1 reg_rdata_next[0] = mio_outsel_regwen_1_qs;
Tests: T25 T26 T27
37742 end
37743
37744 addr_hit[117]: begin
37745 1/1 reg_rdata_next[0] = mio_outsel_regwen_2_qs;
Tests: T25 T27 T80
37746 end
37747
37748 addr_hit[118]: begin
37749 1/1 reg_rdata_next[0] = mio_outsel_regwen_3_qs;
Tests: T25 T27 T80
37750 end
37751
37752 addr_hit[119]: begin
37753 1/1 reg_rdata_next[0] = mio_outsel_regwen_4_qs;
Tests: T25 T27 T80
37754 end
37755
37756 addr_hit[120]: begin
37757 1/1 reg_rdata_next[0] = mio_outsel_regwen_5_qs;
Tests: T4 T25 T27
37758 end
37759
37760 addr_hit[121]: begin
37761 1/1 reg_rdata_next[0] = mio_outsel_regwen_6_qs;
Tests: T25 T27 T80
37762 end
37763
37764 addr_hit[122]: begin
37765 1/1 reg_rdata_next[0] = mio_outsel_regwen_7_qs;
Tests: T25 T27 T62
37766 end
37767
37768 addr_hit[123]: begin
37769 1/1 reg_rdata_next[0] = mio_outsel_regwen_8_qs;
Tests: T27 T62 T80
37770 end
37771
37772 addr_hit[124]: begin
37773 1/1 reg_rdata_next[0] = mio_outsel_regwen_9_qs;
Tests: T9 T10 T11
37774 end
37775
37776 addr_hit[125]: begin
37777 1/1 reg_rdata_next[0] = mio_outsel_regwen_10_qs;
Tests: T9 T10 T11
37778 end
37779
37780 addr_hit[126]: begin
37781 1/1 reg_rdata_next[0] = mio_outsel_regwen_11_qs;
Tests: T10 T11 T80
37782 end
37783
37784 addr_hit[127]: begin
37785 1/1 reg_rdata_next[0] = mio_outsel_regwen_12_qs;
Tests: T9 T10 T11
37786 end
37787
37788 addr_hit[128]: begin
37789 1/1 reg_rdata_next[0] = mio_outsel_regwen_13_qs;
Tests: T1 T2 T3
37790 end
37791
37792 addr_hit[129]: begin
37793 1/1 reg_rdata_next[0] = mio_outsel_regwen_14_qs;
Tests: T1 T2 T3
37794 end
37795
37796 addr_hit[130]: begin
37797 1/1 reg_rdata_next[0] = mio_outsel_regwen_15_qs;
Tests: T9 T27 T80
37798 end
37799
37800 addr_hit[131]: begin
37801 1/1 reg_rdata_next[0] = mio_outsel_regwen_16_qs;
Tests: T27 T13 T15
37802 end
37803
37804 addr_hit[132]: begin
37805 1/1 reg_rdata_next[0] = mio_outsel_regwen_17_qs;
Tests: T27 T80 T104
37806 end
37807
37808 addr_hit[133]: begin
37809 1/1 reg_rdata_next[0] = mio_outsel_regwen_18_qs;
Tests: T5 T27 T64
37810 end
37811
37812 addr_hit[134]: begin
37813 1/1 reg_rdata_next[0] = mio_outsel_regwen_19_qs;
Tests: T5 T27 T64
37814 end
37815
37816 addr_hit[135]: begin
37817 1/1 reg_rdata_next[0] = mio_outsel_regwen_20_qs;
Tests: T5 T27 T66
37818 end
37819
37820 addr_hit[136]: begin
37821 1/1 reg_rdata_next[0] = mio_outsel_regwen_21_qs;
Tests: T5 T27 T66
37822 end
37823
37824 addr_hit[137]: begin
37825 1/1 reg_rdata_next[0] = mio_outsel_regwen_22_qs;
Tests: T80 T104 T265
37826 end
37827
37828 addr_hit[138]: begin
37829 1/1 reg_rdata_next[0] = mio_outsel_regwen_23_qs;
Tests: T80 T104 T265
37830 end
37831
37832 addr_hit[139]: begin
37833 1/1 reg_rdata_next[0] = mio_outsel_regwen_24_qs;
Tests: T80 T104 T265
37834 end
37835
37836 addr_hit[140]: begin
37837 1/1 reg_rdata_next[0] = mio_outsel_regwen_25_qs;
Tests: T1 T2 T3
37838 end
37839
37840 addr_hit[141]: begin
37841 1/1 reg_rdata_next[0] = mio_outsel_regwen_26_qs;
Tests: T1 T2 T3
37842 end
37843
37844 addr_hit[142]: begin
37845 1/1 reg_rdata_next[0] = mio_outsel_regwen_27_qs;
Tests: T80 T104 T265
37846 end
37847
37848 addr_hit[143]: begin
37849 1/1 reg_rdata_next[0] = mio_outsel_regwen_28_qs;
Tests: T80 T104 T265
37850 end
37851
37852 addr_hit[144]: begin
37853 1/1 reg_rdata_next[0] = mio_outsel_regwen_29_qs;
Tests: T1 T2 T3
37854 end
37855
37856 addr_hit[145]: begin
37857 1/1 reg_rdata_next[0] = mio_outsel_regwen_30_qs;
Tests: T80 T104 T265
37858 end
37859
37860 addr_hit[146]: begin
37861 1/1 reg_rdata_next[0] = mio_outsel_regwen_31_qs;
Tests: T27 T13 T80
37862 end
37863
37864 addr_hit[147]: begin
37865 1/1 reg_rdata_next[0] = mio_outsel_regwen_32_qs;
Tests: T27 T198 T80
37866 end
37867
37868 addr_hit[148]: begin
37869 1/1 reg_rdata_next[0] = mio_outsel_regwen_33_qs;
Tests: T27 T80 T35
37870 end
37871
37872 addr_hit[149]: begin
37873 1/1 reg_rdata_next[0] = mio_outsel_regwen_34_qs;
Tests: T27 T80 T35
37874 end
37875
37876 addr_hit[150]: begin
37877 1/1 reg_rdata_next[0] = mio_outsel_regwen_35_qs;
Tests: T27 T80 T104
37878 end
37879
37880 addr_hit[151]: begin
37881 1/1 reg_rdata_next[0] = mio_outsel_regwen_36_qs;
Tests: T27 T80 T104
37882 end
37883
37884 addr_hit[152]: begin
37885 1/1 reg_rdata_next[0] = mio_outsel_regwen_37_qs;
Tests: T27 T80 T104
37886 end
37887
37888 addr_hit[153]: begin
37889 1/1 reg_rdata_next[0] = mio_outsel_regwen_38_qs;
Tests: T27 T80 T104
37890 end
37891
37892 addr_hit[154]: begin
37893 1/1 reg_rdata_next[0] = mio_outsel_regwen_39_qs;
Tests: T27 T80 T104
37894 end
37895
37896 addr_hit[155]: begin
37897 1/1 reg_rdata_next[0] = mio_outsel_regwen_40_qs;
Tests: T27 T13 T80
37898 end
37899
37900 addr_hit[156]: begin
37901 1/1 reg_rdata_next[0] = mio_outsel_regwen_41_qs;
Tests: T27 T13 T80
37902 end
37903
37904 addr_hit[157]: begin
37905 1/1 reg_rdata_next[0] = mio_outsel_regwen_42_qs;
Tests: T27 T80 T104
37906 end
37907
37908 addr_hit[158]: begin
37909 1/1 reg_rdata_next[0] = mio_outsel_regwen_43_qs;
Tests: T27 T80 T264
37910 end
37911
37912 addr_hit[159]: begin
37913 1/1 reg_rdata_next[0] = mio_outsel_regwen_44_qs;
Tests: T27 T80 T104
37914 end
37915
37916 addr_hit[160]: begin
37917 1/1 reg_rdata_next[0] = mio_outsel_regwen_45_qs;
Tests: T45 T27 T80
37918 end
37919
37920 addr_hit[161]: begin
37921 1/1 reg_rdata_next[0] = mio_outsel_regwen_46_qs;
Tests: T27 T80 T104
37922 end
37923
37924 addr_hit[162]: begin
37925 1/1 reg_rdata_next[6:0] = mio_outsel_0_qs;
Tests: T25 T27 T80
37926 end
37927
37928 addr_hit[163]: begin
37929 1/1 reg_rdata_next[6:0] = mio_outsel_1_qs;
Tests: T25 T26 T27
37930 end
37931
37932 addr_hit[164]: begin
37933 1/1 reg_rdata_next[6:0] = mio_outsel_2_qs;
Tests: T25 T27 T80
37934 end
37935
37936 addr_hit[165]: begin
37937 1/1 reg_rdata_next[6:0] = mio_outsel_3_qs;
Tests: T25 T27 T80
37938 end
37939
37940 addr_hit[166]: begin
37941 1/1 reg_rdata_next[6:0] = mio_outsel_4_qs;
Tests: T25 T27 T80
37942 end
37943
37944 addr_hit[167]: begin
37945 1/1 reg_rdata_next[6:0] = mio_outsel_5_qs;
Tests: T4 T25 T27
37946 end
37947
37948 addr_hit[168]: begin
37949 1/1 reg_rdata_next[6:0] = mio_outsel_6_qs;
Tests: T25 T27 T80
37950 end
37951
37952 addr_hit[169]: begin
37953 1/1 reg_rdata_next[6:0] = mio_outsel_7_qs;
Tests: T25 T27 T62
37954 end
37955
37956 addr_hit[170]: begin
37957 1/1 reg_rdata_next[6:0] = mio_outsel_8_qs;
Tests: T27 T62 T80
37958 end
37959
37960 addr_hit[171]: begin
37961 1/1 reg_rdata_next[6:0] = mio_outsel_9_qs;
Tests: T9 T10 T11
37962 end
37963
37964 addr_hit[172]: begin
37965 1/1 reg_rdata_next[6:0] = mio_outsel_10_qs;
Tests: T9 T10 T11
37966 end
37967
37968 addr_hit[173]: begin
37969 1/1 reg_rdata_next[6:0] = mio_outsel_11_qs;
Tests: T10 T11 T80
37970 end
37971
37972 addr_hit[174]: begin
37973 1/1 reg_rdata_next[6:0] = mio_outsel_12_qs;
Tests: T9 T10 T11
37974 end
37975
37976 addr_hit[175]: begin
37977 1/1 reg_rdata_next[6:0] = mio_outsel_13_qs;
Tests: T1 T2 T3
37978 end
37979
37980 addr_hit[176]: begin
37981 1/1 reg_rdata_next[6:0] = mio_outsel_14_qs;
Tests: T1 T2 T3
37982 end
37983
37984 addr_hit[177]: begin
37985 1/1 reg_rdata_next[6:0] = mio_outsel_15_qs;
Tests: T9 T27 T80
37986 end
37987
37988 addr_hit[178]: begin
37989 1/1 reg_rdata_next[6:0] = mio_outsel_16_qs;
Tests: T27 T13 T15
37990 end
37991
37992 addr_hit[179]: begin
37993 1/1 reg_rdata_next[6:0] = mio_outsel_17_qs;
Tests: T27 T80 T104
37994 end
37995
37996 addr_hit[180]: begin
37997 1/1 reg_rdata_next[6:0] = mio_outsel_18_qs;
Tests: T5 T27 T64
37998 end
37999
38000 addr_hit[181]: begin
38001 1/1 reg_rdata_next[6:0] = mio_outsel_19_qs;
Tests: T5 T27 T64
38002 end
38003
38004 addr_hit[182]: begin
38005 1/1 reg_rdata_next[6:0] = mio_outsel_20_qs;
Tests: T5 T27 T66
38006 end
38007
38008 addr_hit[183]: begin
38009 1/1 reg_rdata_next[6:0] = mio_outsel_21_qs;
Tests: T5 T27 T66
38010 end
38011
38012 addr_hit[184]: begin
38013 1/1 reg_rdata_next[6:0] = mio_outsel_22_qs;
Tests: T80 T104 T265
38014 end
38015
38016 addr_hit[185]: begin
38017 1/1 reg_rdata_next[6:0] = mio_outsel_23_qs;
Tests: T80 T104 T265
38018 end
38019
38020 addr_hit[186]: begin
38021 1/1 reg_rdata_next[6:0] = mio_outsel_24_qs;
Tests: T80 T104 T265
38022 end
38023
38024 addr_hit[187]: begin
38025 1/1 reg_rdata_next[6:0] = mio_outsel_25_qs;
Tests: T1 T2 T3
38026 end
38027
38028 addr_hit[188]: begin
38029 1/1 reg_rdata_next[6:0] = mio_outsel_26_qs;
Tests: T1 T2 T3
38030 end
38031
38032 addr_hit[189]: begin
38033 1/1 reg_rdata_next[6:0] = mio_outsel_27_qs;
Tests: T80 T104 T265
38034 end
38035
38036 addr_hit[190]: begin
38037 1/1 reg_rdata_next[6:0] = mio_outsel_28_qs;
Tests: T80 T104 T265
38038 end
38039
38040 addr_hit[191]: begin
38041 1/1 reg_rdata_next[6:0] = mio_outsel_29_qs;
Tests: T1 T2 T3
38042 end
38043
38044 addr_hit[192]: begin
38045 1/1 reg_rdata_next[6:0] = mio_outsel_30_qs;
Tests: T80 T104 T265
38046 end
38047
38048 addr_hit[193]: begin
38049 1/1 reg_rdata_next[6:0] = mio_outsel_31_qs;
Tests: T27 T13 T80
38050 end
38051
38052 addr_hit[194]: begin
38053 1/1 reg_rdata_next[6:0] = mio_outsel_32_qs;
Tests: T27 T86 T80
38054 end
38055
38056 addr_hit[195]: begin
38057 1/1 reg_rdata_next[6:0] = mio_outsel_33_qs;
Tests: T27 T80 T35
38058 end
38059
38060 addr_hit[196]: begin
38061 1/1 reg_rdata_next[6:0] = mio_outsel_34_qs;
Tests: T27 T80 T35
38062 end
38063
38064 addr_hit[197]: begin
38065 1/1 reg_rdata_next[6:0] = mio_outsel_35_qs;
Tests: T27 T80 T104
38066 end
38067
38068 addr_hit[198]: begin
38069 1/1 reg_rdata_next[6:0] = mio_outsel_36_qs;
Tests: T27 T80 T104
38070 end
38071
38072 addr_hit[199]: begin
38073 1/1 reg_rdata_next[6:0] = mio_outsel_37_qs;
Tests: T27 T87 T80
38074 end
38075
38076 addr_hit[200]: begin
38077 1/1 reg_rdata_next[6:0] = mio_outsel_38_qs;
Tests: T27 T80 T104
38078 end
38079
38080 addr_hit[201]: begin
38081 1/1 reg_rdata_next[6:0] = mio_outsel_39_qs;
Tests: T27 T80 T265
38082 end
38083
38084 addr_hit[202]: begin
38085 1/1 reg_rdata_next[6:0] = mio_outsel_40_qs;
Tests: T27 T13 T80
38086 end
38087
38088 addr_hit[203]: begin
38089 1/1 reg_rdata_next[6:0] = mio_outsel_41_qs;
Tests: T27 T13 T80
38090 end
38091
38092 addr_hit[204]: begin
38093 1/1 reg_rdata_next[6:0] = mio_outsel_42_qs;
Tests: T27 T80 T265
38094 end
38095
38096 addr_hit[205]: begin
38097 1/1 reg_rdata_next[6:0] = mio_outsel_43_qs;
Tests: T27 T80 T265
38098 end
38099
38100 addr_hit[206]: begin
38101 1/1 reg_rdata_next[6:0] = mio_outsel_44_qs;
Tests: T27 T80 T265
38102 end
38103
38104 addr_hit[207]: begin
38105 1/1 reg_rdata_next[6:0] = mio_outsel_45_qs;
Tests: T27 T80 T265
38106 end
38107
38108 addr_hit[208]: begin
38109 1/1 reg_rdata_next[6:0] = mio_outsel_46_qs;
Tests: T27 T80 T265
38110 end
38111
38112 addr_hit[209]: begin
38113 1/1 reg_rdata_next[0] = mio_pad_attr_regwen_0_qs;
Tests: T80 T265 T266
38114 end
38115
38116 addr_hit[210]: begin
38117 1/1 reg_rdata_next[0] = mio_pad_attr_regwen_1_qs;
Tests: T80 T265 T266
38118 end
38119
38120 addr_hit[211]: begin
38121 1/1 reg_rdata_next[0] = mio_pad_attr_regwen_2_qs;
Tests: T9 T80 T265
38122 end
38123
38124 addr_hit[212]: begin
38125 1/1 reg_rdata_next[0] = mio_pad_attr_regwen_3_qs;
Tests: T198 T80 T265
38126 end
38127
38128 addr_hit[213]: begin
38129 1/1 reg_rdata_next[0] = mio_pad_attr_regwen_4_qs;
Tests: T80 T265 T266
38130 end
38131
38132 addr_hit[214]: begin
38133 1/1 reg_rdata_next[0] = mio_pad_attr_regwen_5_qs;
Tests: T80 T265 T266
38134 end
38135
38136 addr_hit[215]: begin
38137 1/1 reg_rdata_next[0] = mio_pad_attr_regwen_6_qs;
Tests: T80 T265 T266
38138 end
38139
38140 addr_hit[216]: begin
38141 1/1 reg_rdata_next[0] = mio_pad_attr_regwen_7_qs;
Tests: T12 T80 T265
38142 end
38143
38144 addr_hit[217]: begin
38145 1/1 reg_rdata_next[0] = mio_pad_attr_regwen_8_qs;
Tests: T80 T265 T266
38146 end
38147
38148 addr_hit[218]: begin
38149 1/1 reg_rdata_next[0] = mio_pad_attr_regwen_9_qs;
Tests: T9 T80 T265
38150 end
38151
38152 addr_hit[219]: begin
38153 1/1 reg_rdata_next[0] = mio_pad_attr_regwen_10_qs;
Tests: T9 T10 T11
38154 end
38155
38156 addr_hit[220]: begin
38157 1/1 reg_rdata_next[0] = mio_pad_attr_regwen_11_qs;
Tests: T80 T265 T266
38158 end
38159
38160 addr_hit[221]: begin
38161 1/1 reg_rdata_next[0] = mio_pad_attr_regwen_12_qs;
Tests: T9 T10 T11
38162 end
38163
38164 addr_hit[222]: begin
38165 1/1 reg_rdata_next[0] = mio_pad_attr_regwen_13_qs;
Tests: T9 T80 T265
38166 end
38167
38168 addr_hit[223]: begin
38169 1/1 reg_rdata_next[0] = mio_pad_attr_regwen_14_qs;
Tests: T9 T80 T264
38170 end
38171
38172 addr_hit[224]: begin
38173 1/1 reg_rdata_next[0] = mio_pad_attr_regwen_15_qs;
Tests: T9 T80 T265
38174 end
38175
38176 addr_hit[225]: begin
38177 1/1 reg_rdata_next[0] = mio_pad_attr_regwen_16_qs;
Tests: T45 T80 T265
38178 end
38179
38180 addr_hit[226]: begin
38181 1/1 reg_rdata_next[0] = mio_pad_attr_regwen_17_qs;
Tests: T80 T265 T266
38182 end
38183
38184 addr_hit[227]: begin
38185 1/1 reg_rdata_next[0] = mio_pad_attr_regwen_18_qs;
Tests: T80 T265 T266
38186 end
38187
38188 addr_hit[228]: begin
38189 1/1 reg_rdata_next[0] = mio_pad_attr_regwen_19_qs;
Tests: T80 T265 T266
38190 end
38191
38192 addr_hit[229]: begin
38193 1/1 reg_rdata_next[0] = mio_pad_attr_regwen_20_qs;
Tests: T80 T265 T266
38194 end
38195
38196 addr_hit[230]: begin
38197 1/1 reg_rdata_next[0] = mio_pad_attr_regwen_21_qs;
Tests: T80 T265 T266
38198 end
38199
38200 addr_hit[231]: begin
38201 1/1 reg_rdata_next[0] = mio_pad_attr_regwen_22_qs;
Tests: T80 T265 T266
38202 end
38203
38204 addr_hit[232]: begin
38205 1/1 reg_rdata_next[0] = mio_pad_attr_regwen_23_qs;
Tests: T80 T265 T266
38206 end
38207
38208 addr_hit[233]: begin
38209 1/1 reg_rdata_next[0] = mio_pad_attr_regwen_24_qs;
Tests: T80 T265 T266
38210 end
38211
38212 addr_hit[234]: begin
38213 1/1 reg_rdata_next[0] = mio_pad_attr_regwen_25_qs;
Tests: T1 T2 T3
38214 end
38215
38216 addr_hit[235]: begin
38217 1/1 reg_rdata_next[0] = mio_pad_attr_regwen_26_qs;
Tests: T80 T265 T266
38218 end
38219
38220 addr_hit[236]: begin
38221 1/1 reg_rdata_next[0] = mio_pad_attr_regwen_27_qs;
Tests: T80 T265 T266
38222 end
38223
38224 addr_hit[237]: begin
38225 1/1 reg_rdata_next[0] = mio_pad_attr_regwen_28_qs;
Tests: T80 T265 T266
38226 end
38227
38228 addr_hit[238]: begin
38229 1/1 reg_rdata_next[0] = mio_pad_attr_regwen_29_qs;
Tests: T80 T265 T266
38230 end
38231
38232 addr_hit[239]: begin
38233 1/1 reg_rdata_next[0] = mio_pad_attr_regwen_30_qs;
Tests: T80 T265 T266
38234 end
38235
38236 addr_hit[240]: begin
38237 1/1 reg_rdata_next[0] = mio_pad_attr_regwen_31_qs;
Tests: T80 T265 T266
38238 end
38239
38240 addr_hit[241]: begin
38241 1/1 reg_rdata_next[0] = mio_pad_attr_regwen_32_qs;
Tests: T265 T266 T105
38242 end
38243
38244 addr_hit[242]: begin
38245 1/1 reg_rdata_next[0] = mio_pad_attr_regwen_33_qs;
Tests: T80 T265 T266
38246 end
38247
38248 addr_hit[243]: begin
38249 1/1 reg_rdata_next[0] = mio_pad_attr_regwen_34_qs;
Tests: T80 T265 T266
38250 end
38251
38252 addr_hit[244]: begin
38253 1/1 reg_rdata_next[0] = mio_pad_attr_regwen_35_qs;
Tests: T80 T265 T266
38254 end
38255
38256 addr_hit[245]: begin
38257 1/1 reg_rdata_next[0] = mio_pad_attr_regwen_36_qs;
Tests: T80 T265 T266
38258 end
38259
38260 addr_hit[246]: begin
38261 1/1 reg_rdata_next[0] = mio_pad_attr_regwen_37_qs;
Tests: T80 T265 T266
38262 end
38263
38264 addr_hit[247]: begin
38265 1/1 reg_rdata_next[0] = mio_pad_attr_regwen_38_qs;
Tests: T80 T265 T266
38266 end
38267
38268 addr_hit[248]: begin
38269 1/1 reg_rdata_next[0] = mio_pad_attr_regwen_39_qs;
Tests: T80 T265 T266
38270 end
38271
38272 addr_hit[249]: begin
38273 1/1 reg_rdata_next[0] = mio_pad_attr_regwen_40_qs;
Tests: T80 T265 T266
38274 end
38275
38276 addr_hit[250]: begin
38277 1/1 reg_rdata_next[0] = mio_pad_attr_regwen_41_qs;
Tests: T80 T265 T266
38278 end
38279
38280 addr_hit[251]: begin
38281 1/1 reg_rdata_next[0] = mio_pad_attr_regwen_42_qs;
Tests: T80 T265 T266
38282 end
38283
38284 addr_hit[252]: begin
38285 1/1 reg_rdata_next[0] = mio_pad_attr_regwen_43_qs;
Tests: T80 T265 T266
38286 end
38287
38288 addr_hit[253]: begin
38289 1/1 reg_rdata_next[0] = mio_pad_attr_regwen_44_qs;
Tests: T80 T265 T266
38290 end
38291
38292 addr_hit[254]: begin
38293 1/1 reg_rdata_next[0] = mio_pad_attr_regwen_45_qs;
Tests: T80 T265 T266
38294 end
38295
38296 addr_hit[255]: begin
38297 1/1 reg_rdata_next[0] = mio_pad_attr_regwen_46_qs;
Tests: T80 T265 T266
38298 end
38299
38300 addr_hit[256]: begin
38301 1/1 reg_rdata_next[0] = mio_pad_attr_0_invert_0_qs;
Tests: T80 T265 T266
38302 1/1 reg_rdata_next[1] = mio_pad_attr_0_virtual_od_en_0_qs;
Tests: T80 T265 T266
38303 1/1 reg_rdata_next[2] = mio_pad_attr_0_pull_en_0_qs;
Tests: T80 T265 T266
38304 1/1 reg_rdata_next[3] = mio_pad_attr_0_pull_select_0_qs;
Tests: T80 T265 T266
38305 1/1 reg_rdata_next[4] = mio_pad_attr_0_keeper_en_0_qs;
Tests: T80 T265 T266
38306 1/1 reg_rdata_next[5] = mio_pad_attr_0_schmitt_en_0_qs;
Tests: T80 T265 T266
38307 1/1 reg_rdata_next[6] = mio_pad_attr_0_od_en_0_qs;
Tests: T80 T265 T266
38308 1/1 reg_rdata_next[7] = mio_pad_attr_0_input_disable_0_qs;
Tests: T80 T265 T266
38309 1/1 reg_rdata_next[17:16] = mio_pad_attr_0_slew_rate_0_qs;
Tests: T80 T265 T266
38310 1/1 reg_rdata_next[23:20] = mio_pad_attr_0_drive_strength_0_qs;
Tests: T80 T265 T266
38311 end
38312
38313 addr_hit[257]: begin
38314 1/1 reg_rdata_next[0] = mio_pad_attr_1_invert_1_qs;
Tests: T80 T265 T266
38315 1/1 reg_rdata_next[1] = mio_pad_attr_1_virtual_od_en_1_qs;
Tests: T80 T265 T266
38316 1/1 reg_rdata_next[2] = mio_pad_attr_1_pull_en_1_qs;
Tests: T80 T265 T266
38317 1/1 reg_rdata_next[3] = mio_pad_attr_1_pull_select_1_qs;
Tests: T80 T265 T266
38318 1/1 reg_rdata_next[4] = mio_pad_attr_1_keeper_en_1_qs;
Tests: T80 T265 T266
38319 1/1 reg_rdata_next[5] = mio_pad_attr_1_schmitt_en_1_qs;
Tests: T80 T265 T266
38320 1/1 reg_rdata_next[6] = mio_pad_attr_1_od_en_1_qs;
Tests: T80 T265 T266
38321 1/1 reg_rdata_next[7] = mio_pad_attr_1_input_disable_1_qs;
Tests: T80 T265 T266
38322 1/1 reg_rdata_next[17:16] = mio_pad_attr_1_slew_rate_1_qs;
Tests: T80 T265 T266
38323 1/1 reg_rdata_next[23:20] = mio_pad_attr_1_drive_strength_1_qs;
Tests: T80 T265 T266
38324 end
38325
38326 addr_hit[258]: begin
38327 1/1 reg_rdata_next[0] = mio_pad_attr_2_invert_2_qs;
Tests: T9 T80 T265
38328 1/1 reg_rdata_next[1] = mio_pad_attr_2_virtual_od_en_2_qs;
Tests: T9 T80 T265
38329 1/1 reg_rdata_next[2] = mio_pad_attr_2_pull_en_2_qs;
Tests: T9 T80 T265
38330 1/1 reg_rdata_next[3] = mio_pad_attr_2_pull_select_2_qs;
Tests: T9 T80 T265
38331 1/1 reg_rdata_next[4] = mio_pad_attr_2_keeper_en_2_qs;
Tests: T9 T80 T265
38332 1/1 reg_rdata_next[5] = mio_pad_attr_2_schmitt_en_2_qs;
Tests: T9 T80 T265
38333 1/1 reg_rdata_next[6] = mio_pad_attr_2_od_en_2_qs;
Tests: T9 T80 T265
38334 1/1 reg_rdata_next[7] = mio_pad_attr_2_input_disable_2_qs;
Tests: T9 T80 T265
38335 1/1 reg_rdata_next[17:16] = mio_pad_attr_2_slew_rate_2_qs;
Tests: T9 T80 T265
38336 1/1 reg_rdata_next[23:20] = mio_pad_attr_2_drive_strength_2_qs;
Tests: T9 T80 T265
38337 end
38338
38339 addr_hit[259]: begin
38340 1/1 reg_rdata_next[0] = mio_pad_attr_3_invert_3_qs;
Tests: T86 T80 T265
38341 1/1 reg_rdata_next[1] = mio_pad_attr_3_virtual_od_en_3_qs;
Tests: T86 T80 T265
38342 1/1 reg_rdata_next[2] = mio_pad_attr_3_pull_en_3_qs;
Tests: T86 T80 T265
38343 1/1 reg_rdata_next[3] = mio_pad_attr_3_pull_select_3_qs;
Tests: T86 T80 T265
38344 1/1 reg_rdata_next[4] = mio_pad_attr_3_keeper_en_3_qs;
Tests: T86 T80 T265
38345 1/1 reg_rdata_next[5] = mio_pad_attr_3_schmitt_en_3_qs;
Tests: T86 T80 T265
38346 1/1 reg_rdata_next[6] = mio_pad_attr_3_od_en_3_qs;
Tests: T86 T80 T265
38347 1/1 reg_rdata_next[7] = mio_pad_attr_3_input_disable_3_qs;
Tests: T86 T80 T265
38348 1/1 reg_rdata_next[17:16] = mio_pad_attr_3_slew_rate_3_qs;
Tests: T86 T80 T265
38349 1/1 reg_rdata_next[23:20] = mio_pad_attr_3_drive_strength_3_qs;
Tests: T86 T80 T265
38350 end
38351
38352 addr_hit[260]: begin
38353 1/1 reg_rdata_next[0] = mio_pad_attr_4_invert_4_qs;
Tests: T80 T265 T266
38354 1/1 reg_rdata_next[1] = mio_pad_attr_4_virtual_od_en_4_qs;
Tests: T80 T265 T266
38355 1/1 reg_rdata_next[2] = mio_pad_attr_4_pull_en_4_qs;
Tests: T80 T265 T266
38356 1/1 reg_rdata_next[3] = mio_pad_attr_4_pull_select_4_qs;
Tests: T80 T265 T266
38357 1/1 reg_rdata_next[4] = mio_pad_attr_4_keeper_en_4_qs;
Tests: T80 T265 T266
38358 1/1 reg_rdata_next[5] = mio_pad_attr_4_schmitt_en_4_qs;
Tests: T80 T265 T266
38359 1/1 reg_rdata_next[6] = mio_pad_attr_4_od_en_4_qs;
Tests: T80 T265 T266
38360 1/1 reg_rdata_next[7] = mio_pad_attr_4_input_disable_4_qs;
Tests: T80 T265 T266
38361 1/1 reg_rdata_next[17:16] = mio_pad_attr_4_slew_rate_4_qs;
Tests: T80 T265 T266
38362 1/1 reg_rdata_next[23:20] = mio_pad_attr_4_drive_strength_4_qs;
Tests: T80 T265 T266
38363 end
38364
38365 addr_hit[261]: begin
38366 1/1 reg_rdata_next[0] = mio_pad_attr_5_invert_5_qs;
Tests: T80 T265 T266
38367 1/1 reg_rdata_next[1] = mio_pad_attr_5_virtual_od_en_5_qs;
Tests: T80 T265 T266
38368 1/1 reg_rdata_next[2] = mio_pad_attr_5_pull_en_5_qs;
Tests: T80 T265 T266
38369 1/1 reg_rdata_next[3] = mio_pad_attr_5_pull_select_5_qs;
Tests: T80 T265 T266
38370 1/1 reg_rdata_next[4] = mio_pad_attr_5_keeper_en_5_qs;
Tests: T80 T265 T266
38371 1/1 reg_rdata_next[5] = mio_pad_attr_5_schmitt_en_5_qs;
Tests: T80 T265 T266
38372 1/1 reg_rdata_next[6] = mio_pad_attr_5_od_en_5_qs;
Tests: T80 T265 T266
38373 1/1 reg_rdata_next[7] = mio_pad_attr_5_input_disable_5_qs;
Tests: T80 T265 T266
38374 1/1 reg_rdata_next[17:16] = mio_pad_attr_5_slew_rate_5_qs;
Tests: T80 T265 T266
38375 1/1 reg_rdata_next[23:20] = mio_pad_attr_5_drive_strength_5_qs;
Tests: T80 T265 T266
38376 end
38377
38378 addr_hit[262]: begin
38379 1/1 reg_rdata_next[0] = mio_pad_attr_6_invert_6_qs;
Tests: T80 T265 T266
38380 1/1 reg_rdata_next[1] = mio_pad_attr_6_virtual_od_en_6_qs;
Tests: T80 T265 T266
38381 1/1 reg_rdata_next[2] = mio_pad_attr_6_pull_en_6_qs;
Tests: T80 T265 T266
38382 1/1 reg_rdata_next[3] = mio_pad_attr_6_pull_select_6_qs;
Tests: T80 T265 T266
38383 1/1 reg_rdata_next[4] = mio_pad_attr_6_keeper_en_6_qs;
Tests: T80 T265 T266
38384 1/1 reg_rdata_next[5] = mio_pad_attr_6_schmitt_en_6_qs;
Tests: T80 T265 T266
38385 1/1 reg_rdata_next[6] = mio_pad_attr_6_od_en_6_qs;
Tests: T80 T265 T266
38386 1/1 reg_rdata_next[7] = mio_pad_attr_6_input_disable_6_qs;
Tests: T80 T265 T266
38387 1/1 reg_rdata_next[17:16] = mio_pad_attr_6_slew_rate_6_qs;
Tests: T80 T265 T266
38388 1/1 reg_rdata_next[23:20] = mio_pad_attr_6_drive_strength_6_qs;
Tests: T80 T265 T266
38389 end
38390
38391 addr_hit[263]: begin
38392 1/1 reg_rdata_next[0] = mio_pad_attr_7_invert_7_qs;
Tests: T12 T80 T265
38393 1/1 reg_rdata_next[1] = mio_pad_attr_7_virtual_od_en_7_qs;
Tests: T12 T80 T265
38394 1/1 reg_rdata_next[2] = mio_pad_attr_7_pull_en_7_qs;
Tests: T12 T80 T265
38395 1/1 reg_rdata_next[3] = mio_pad_attr_7_pull_select_7_qs;
Tests: T12 T80 T265
38396 1/1 reg_rdata_next[4] = mio_pad_attr_7_keeper_en_7_qs;
Tests: T12 T80 T265
38397 1/1 reg_rdata_next[5] = mio_pad_attr_7_schmitt_en_7_qs;
Tests: T12 T80 T265
38398 1/1 reg_rdata_next[6] = mio_pad_attr_7_od_en_7_qs;
Tests: T12 T80 T265
38399 1/1 reg_rdata_next[7] = mio_pad_attr_7_input_disable_7_qs;
Tests: T12 T80 T265
38400 1/1 reg_rdata_next[17:16] = mio_pad_attr_7_slew_rate_7_qs;
Tests: T12 T80 T265
38401 1/1 reg_rdata_next[23:20] = mio_pad_attr_7_drive_strength_7_qs;
Tests: T12 T80 T265
38402 end
38403
38404 addr_hit[264]: begin
38405 1/1 reg_rdata_next[0] = mio_pad_attr_8_invert_8_qs;
Tests: T87 T80 T265
38406 1/1 reg_rdata_next[1] = mio_pad_attr_8_virtual_od_en_8_qs;
Tests: T87 T80 T265
38407 1/1 reg_rdata_next[2] = mio_pad_attr_8_pull_en_8_qs;
Tests: T87 T80 T265
38408 1/1 reg_rdata_next[3] = mio_pad_attr_8_pull_select_8_qs;
Tests: T87 T80 T265
38409 1/1 reg_rdata_next[4] = mio_pad_attr_8_keeper_en_8_qs;
Tests: T87 T80 T265
38410 1/1 reg_rdata_next[5] = mio_pad_attr_8_schmitt_en_8_qs;
Tests: T87 T80 T265
38411 1/1 reg_rdata_next[6] = mio_pad_attr_8_od_en_8_qs;
Tests: T87 T80 T265
38412 1/1 reg_rdata_next[7] = mio_pad_attr_8_input_disable_8_qs;
Tests: T87 T80 T265
38413 1/1 reg_rdata_next[17:16] = mio_pad_attr_8_slew_rate_8_qs;
Tests: T87 T80 T265
38414 1/1 reg_rdata_next[23:20] = mio_pad_attr_8_drive_strength_8_qs;
Tests: T87 T80 T265
38415 end
38416
38417 addr_hit[265]: begin
38418 1/1 reg_rdata_next[0] = mio_pad_attr_9_invert_9_qs;
Tests: T9 T80 T265
38419 1/1 reg_rdata_next[1] = mio_pad_attr_9_virtual_od_en_9_qs;
Tests: T9 T80 T265
38420 1/1 reg_rdata_next[2] = mio_pad_attr_9_pull_en_9_qs;
Tests: T9 T80 T265
38421 1/1 reg_rdata_next[3] = mio_pad_attr_9_pull_select_9_qs;
Tests: T9 T80 T265
38422 1/1 reg_rdata_next[4] = mio_pad_attr_9_keeper_en_9_qs;
Tests: T9 T80 T265
38423 1/1 reg_rdata_next[5] = mio_pad_attr_9_schmitt_en_9_qs;
Tests: T9 T80 T265
38424 1/1 reg_rdata_next[6] = mio_pad_attr_9_od_en_9_qs;
Tests: T9 T80 T265
38425 1/1 reg_rdata_next[7] = mio_pad_attr_9_input_disable_9_qs;
Tests: T9 T80 T265
38426 1/1 reg_rdata_next[17:16] = mio_pad_attr_9_slew_rate_9_qs;
Tests: T9 T80 T265
38427 1/1 reg_rdata_next[23:20] = mio_pad_attr_9_drive_strength_9_qs;
Tests: T9 T80 T265
38428 end
38429
38430 addr_hit[266]: begin
38431 1/1 reg_rdata_next[0] = mio_pad_attr_10_invert_10_qs;
Tests: T9 T10 T11
38432 1/1 reg_rdata_next[1] = mio_pad_attr_10_virtual_od_en_10_qs;
Tests: T9 T10 T11
38433 1/1 reg_rdata_next[2] = mio_pad_attr_10_pull_en_10_qs;
Tests: T9 T10 T11
38434 1/1 reg_rdata_next[3] = mio_pad_attr_10_pull_select_10_qs;
Tests: T9 T10 T11
38435 1/1 reg_rdata_next[4] = mio_pad_attr_10_keeper_en_10_qs;
Tests: T9 T10 T11
38436 1/1 reg_rdata_next[5] = mio_pad_attr_10_schmitt_en_10_qs;
Tests: T9 T10 T11
38437 1/1 reg_rdata_next[6] = mio_pad_attr_10_od_en_10_qs;
Tests: T9 T10 T11
38438 1/1 reg_rdata_next[7] = mio_pad_attr_10_input_disable_10_qs;
Tests: T9 T10 T11
38439 1/1 reg_rdata_next[17:16] = mio_pad_attr_10_slew_rate_10_qs;
Tests: T9 T10 T11
38440 1/1 reg_rdata_next[23:20] = mio_pad_attr_10_drive_strength_10_qs;
Tests: T9 T10 T11
38441 end
38442
38443 addr_hit[267]: begin
38444 1/1 reg_rdata_next[0] = mio_pad_attr_11_invert_11_qs;
Tests: T104 T265 T105
38445 1/1 reg_rdata_next[1] = mio_pad_attr_11_virtual_od_en_11_qs;
Tests: T104 T265 T105
38446 1/1 reg_rdata_next[2] = mio_pad_attr_11_pull_en_11_qs;
Tests: T104 T265 T105
38447 1/1 reg_rdata_next[3] = mio_pad_attr_11_pull_select_11_qs;
Tests: T104 T265 T105
38448 1/1 reg_rdata_next[4] = mio_pad_attr_11_keeper_en_11_qs;
Tests: T104 T265 T105
38449 1/1 reg_rdata_next[5] = mio_pad_attr_11_schmitt_en_11_qs;
Tests: T104 T265 T105
38450 1/1 reg_rdata_next[6] = mio_pad_attr_11_od_en_11_qs;
Tests: T104 T265 T105
38451 1/1 reg_rdata_next[7] = mio_pad_attr_11_input_disable_11_qs;
Tests: T104 T265 T105
38452 1/1 reg_rdata_next[17:16] = mio_pad_attr_11_slew_rate_11_qs;
Tests: T104 T265 T105
38453 1/1 reg_rdata_next[23:20] = mio_pad_attr_11_drive_strength_11_qs;
Tests: T104 T265 T105
38454 end
38455
38456 addr_hit[268]: begin
38457 1/1 reg_rdata_next[0] = mio_pad_attr_12_invert_12_qs;
Tests: T9 T10 T11
38458 1/1 reg_rdata_next[1] = mio_pad_attr_12_virtual_od_en_12_qs;
Tests: T9 T10 T11
38459 1/1 reg_rdata_next[2] = mio_pad_attr_12_pull_en_12_qs;
Tests: T9 T10 T11
38460 1/1 reg_rdata_next[3] = mio_pad_attr_12_pull_select_12_qs;
Tests: T9 T10 T11
38461 1/1 reg_rdata_next[4] = mio_pad_attr_12_keeper_en_12_qs;
Tests: T9 T10 T11
38462 1/1 reg_rdata_next[5] = mio_pad_attr_12_schmitt_en_12_qs;
Tests: T9 T10 T11
38463 1/1 reg_rdata_next[6] = mio_pad_attr_12_od_en_12_qs;
Tests: T9 T10 T11
38464 1/1 reg_rdata_next[7] = mio_pad_attr_12_input_disable_12_qs;
Tests: T9 T10 T11
38465 1/1 reg_rdata_next[17:16] = mio_pad_attr_12_slew_rate_12_qs;
Tests: T9 T10 T11
38466 1/1 reg_rdata_next[23:20] = mio_pad_attr_12_drive_strength_12_qs;
Tests: T9 T10 T11
38467 end
38468
38469 addr_hit[269]: begin
38470 1/1 reg_rdata_next[0] = mio_pad_attr_13_invert_13_qs;
Tests: T9 T104 T265
38471 1/1 reg_rdata_next[1] = mio_pad_attr_13_virtual_od_en_13_qs;
Tests: T9 T104 T265
38472 1/1 reg_rdata_next[2] = mio_pad_attr_13_pull_en_13_qs;
Tests: T9 T104 T265
38473 1/1 reg_rdata_next[3] = mio_pad_attr_13_pull_select_13_qs;
Tests: T9 T104 T265
38474 1/1 reg_rdata_next[4] = mio_pad_attr_13_keeper_en_13_qs;
Tests: T9 T104 T265
38475 1/1 reg_rdata_next[5] = mio_pad_attr_13_schmitt_en_13_qs;
Tests: T9 T104 T265
38476 1/1 reg_rdata_next[6] = mio_pad_attr_13_od_en_13_qs;
Tests: T9 T104 T265
38477 1/1 reg_rdata_next[7] = mio_pad_attr_13_input_disable_13_qs;
Tests: T9 T104 T265
38478 1/1 reg_rdata_next[17:16] = mio_pad_attr_13_slew_rate_13_qs;
Tests: T9 T104 T265
38479 1/1 reg_rdata_next[23:20] = mio_pad_attr_13_drive_strength_13_qs;
Tests: T9 T104 T265
38480 end
38481
38482 addr_hit[270]: begin
38483 1/1 reg_rdata_next[0] = mio_pad_attr_14_invert_14_qs;
Tests: T9 T104 T265
38484 1/1 reg_rdata_next[1] = mio_pad_attr_14_virtual_od_en_14_qs;
Tests: T9 T104 T265
38485 1/1 reg_rdata_next[2] = mio_pad_attr_14_pull_en_14_qs;
Tests: T9 T104 T265
38486 1/1 reg_rdata_next[3] = mio_pad_attr_14_pull_select_14_qs;
Tests: T9 T104 T265
38487 1/1 reg_rdata_next[4] = mio_pad_attr_14_keeper_en_14_qs;
Tests: T9 T104 T265
38488 1/1 reg_rdata_next[5] = mio_pad_attr_14_schmitt_en_14_qs;
Tests: T9 T104 T265
38489 1/1 reg_rdata_next[6] = mio_pad_attr_14_od_en_14_qs;
Tests: T9 T104 T265
38490 1/1 reg_rdata_next[7] = mio_pad_attr_14_input_disable_14_qs;
Tests: T9 T104 T265
38491 1/1 reg_rdata_next[17:16] = mio_pad_attr_14_slew_rate_14_qs;
Tests: T9 T104 T265
38492 1/1 reg_rdata_next[23:20] = mio_pad_attr_14_drive_strength_14_qs;
Tests: T9 T104 T265
38493 end
38494
38495 addr_hit[271]: begin
38496 1/1 reg_rdata_next[0] = mio_pad_attr_15_invert_15_qs;
Tests: T9 T104 T265
38497 1/1 reg_rdata_next[1] = mio_pad_attr_15_virtual_od_en_15_qs;
Tests: T9 T104 T265
38498 1/1 reg_rdata_next[2] = mio_pad_attr_15_pull_en_15_qs;
Tests: T9 T104 T265
38499 1/1 reg_rdata_next[3] = mio_pad_attr_15_pull_select_15_qs;
Tests: T9 T104 T265
38500 1/1 reg_rdata_next[4] = mio_pad_attr_15_keeper_en_15_qs;
Tests: T9 T104 T265
38501 1/1 reg_rdata_next[5] = mio_pad_attr_15_schmitt_en_15_qs;
Tests: T9 T104 T265
38502 1/1 reg_rdata_next[6] = mio_pad_attr_15_od_en_15_qs;
Tests: T9 T104 T265
38503 1/1 reg_rdata_next[7] = mio_pad_attr_15_input_disable_15_qs;
Tests: T9 T104 T265
38504 1/1 reg_rdata_next[17:16] = mio_pad_attr_15_slew_rate_15_qs;
Tests: T9 T104 T265
38505 1/1 reg_rdata_next[23:20] = mio_pad_attr_15_drive_strength_15_qs;
Tests: T9 T104 T265
38506 end
38507
38508 addr_hit[272]: begin
38509 1/1 reg_rdata_next[0] = mio_pad_attr_16_invert_16_qs;
Tests: T104 T265 T105
38510 1/1 reg_rdata_next[1] = mio_pad_attr_16_virtual_od_en_16_qs;
Tests: T104 T265 T105
38511 1/1 reg_rdata_next[2] = mio_pad_attr_16_pull_en_16_qs;
Tests: T104 T265 T105
38512 1/1 reg_rdata_next[3] = mio_pad_attr_16_pull_select_16_qs;
Tests: T104 T265 T105
38513 1/1 reg_rdata_next[4] = mio_pad_attr_16_keeper_en_16_qs;
Tests: T104 T265 T105
38514 1/1 reg_rdata_next[5] = mio_pad_attr_16_schmitt_en_16_qs;
Tests: T104 T265 T105
38515 1/1 reg_rdata_next[6] = mio_pad_attr_16_od_en_16_qs;
Tests: T104 T265 T105
38516 1/1 reg_rdata_next[7] = mio_pad_attr_16_input_disable_16_qs;
Tests: T104 T265 T105
38517 1/1 reg_rdata_next[17:16] = mio_pad_attr_16_slew_rate_16_qs;
Tests: T104 T265 T105
38518 1/1 reg_rdata_next[23:20] = mio_pad_attr_16_drive_strength_16_qs;
Tests: T104 T265 T105
38519 end
38520
38521 addr_hit[273]: begin
38522 1/1 reg_rdata_next[0] = mio_pad_attr_17_invert_17_qs;
Tests: T104 T265 T266
38523 1/1 reg_rdata_next[1] = mio_pad_attr_17_virtual_od_en_17_qs;
Tests: T104 T265 T266
38524 1/1 reg_rdata_next[2] = mio_pad_attr_17_pull_en_17_qs;
Tests: T104 T265 T266
38525 1/1 reg_rdata_next[3] = mio_pad_attr_17_pull_select_17_qs;
Tests: T104 T265 T266
38526 1/1 reg_rdata_next[4] = mio_pad_attr_17_keeper_en_17_qs;
Tests: T104 T265 T266
38527 1/1 reg_rdata_next[5] = mio_pad_attr_17_schmitt_en_17_qs;
Tests: T104 T265 T266
38528 1/1 reg_rdata_next[6] = mio_pad_attr_17_od_en_17_qs;
Tests: T104 T265 T266
38529 1/1 reg_rdata_next[7] = mio_pad_attr_17_input_disable_17_qs;
Tests: T104 T265 T266
38530 1/1 reg_rdata_next[17:16] = mio_pad_attr_17_slew_rate_17_qs;
Tests: T104 T265 T266
38531 1/1 reg_rdata_next[23:20] = mio_pad_attr_17_drive_strength_17_qs;
Tests: T104 T265 T266
38532 end
38533
38534 addr_hit[274]: begin
38535 1/1 reg_rdata_next[0] = mio_pad_attr_18_invert_18_qs;
Tests: T104 T265 T105
38536 1/1 reg_rdata_next[1] = mio_pad_attr_18_virtual_od_en_18_qs;
Tests: T104 T265 T105
38537 1/1 reg_rdata_next[2] = mio_pad_attr_18_pull_en_18_qs;
Tests: T104 T265 T105
38538 1/1 reg_rdata_next[3] = mio_pad_attr_18_pull_select_18_qs;
Tests: T104 T265 T105
38539 1/1 reg_rdata_next[4] = mio_pad_attr_18_keeper_en_18_qs;
Tests: T104 T265 T105
38540 1/1 reg_rdata_next[5] = mio_pad_attr_18_schmitt_en_18_qs;
Tests: T104 T265 T105
38541 1/1 reg_rdata_next[6] = mio_pad_attr_18_od_en_18_qs;
Tests: T104 T265 T105
38542 1/1 reg_rdata_next[7] = mio_pad_attr_18_input_disable_18_qs;
Tests: T104 T265 T105
38543 1/1 reg_rdata_next[17:16] = mio_pad_attr_18_slew_rate_18_qs;
Tests: T104 T265 T105
38544 1/1 reg_rdata_next[23:20] = mio_pad_attr_18_drive_strength_18_qs;
Tests: T104 T265 T105
38545 end
38546
38547 addr_hit[275]: begin
38548 1/1 reg_rdata_next[0] = mio_pad_attr_19_invert_19_qs;
Tests: T104 T265 T105
38549 1/1 reg_rdata_next[1] = mio_pad_attr_19_virtual_od_en_19_qs;
Tests: T104 T265 T105
38550 1/1 reg_rdata_next[2] = mio_pad_attr_19_pull_en_19_qs;
Tests: T104 T265 T105
38551 1/1 reg_rdata_next[3] = mio_pad_attr_19_pull_select_19_qs;
Tests: T104 T265 T105
38552 1/1 reg_rdata_next[4] = mio_pad_attr_19_keeper_en_19_qs;
Tests: T104 T265 T105
38553 1/1 reg_rdata_next[5] = mio_pad_attr_19_schmitt_en_19_qs;
Tests: T104 T265 T105
38554 1/1 reg_rdata_next[6] = mio_pad_attr_19_od_en_19_qs;
Tests: T104 T265 T105
38555 1/1 reg_rdata_next[7] = mio_pad_attr_19_input_disable_19_qs;
Tests: T104 T265 T105
38556 1/1 reg_rdata_next[17:16] = mio_pad_attr_19_slew_rate_19_qs;
Tests: T104 T265 T105
38557 1/1 reg_rdata_next[23:20] = mio_pad_attr_19_drive_strength_19_qs;
Tests: T104 T265 T105
38558 end
38559
38560 addr_hit[276]: begin
38561 1/1 reg_rdata_next[0] = mio_pad_attr_20_invert_20_qs;
Tests: T104 T265 T105
38562 1/1 reg_rdata_next[1] = mio_pad_attr_20_virtual_od_en_20_qs;
Tests: T104 T265 T105
38563 1/1 reg_rdata_next[2] = mio_pad_attr_20_pull_en_20_qs;
Tests: T104 T265 T105
38564 1/1 reg_rdata_next[3] = mio_pad_attr_20_pull_select_20_qs;
Tests: T104 T265 T105
38565 1/1 reg_rdata_next[4] = mio_pad_attr_20_keeper_en_20_qs;
Tests: T104 T265 T105
38566 1/1 reg_rdata_next[5] = mio_pad_attr_20_schmitt_en_20_qs;
Tests: T104 T265 T105
38567 1/1 reg_rdata_next[6] = mio_pad_attr_20_od_en_20_qs;
Tests: T104 T265 T105
38568 1/1 reg_rdata_next[7] = mio_pad_attr_20_input_disable_20_qs;
Tests: T104 T265 T105
38569 1/1 reg_rdata_next[17:16] = mio_pad_attr_20_slew_rate_20_qs;
Tests: T104 T265 T105
38570 1/1 reg_rdata_next[23:20] = mio_pad_attr_20_drive_strength_20_qs;
Tests: T104 T265 T105
38571 end
38572
38573 addr_hit[277]: begin
38574 1/1 reg_rdata_next[0] = mio_pad_attr_21_invert_21_qs;
Tests: T104 T265 T105
38575 1/1 reg_rdata_next[1] = mio_pad_attr_21_virtual_od_en_21_qs;
Tests: T104 T265 T105
38576 1/1 reg_rdata_next[2] = mio_pad_attr_21_pull_en_21_qs;
Tests: T104 T265 T105
38577 1/1 reg_rdata_next[3] = mio_pad_attr_21_pull_select_21_qs;
Tests: T104 T265 T105
38578 1/1 reg_rdata_next[4] = mio_pad_attr_21_keeper_en_21_qs;
Tests: T104 T265 T105
38579 1/1 reg_rdata_next[5] = mio_pad_attr_21_schmitt_en_21_qs;
Tests: T104 T265 T105
38580 1/1 reg_rdata_next[6] = mio_pad_attr_21_od_en_21_qs;
Tests: T104 T265 T105
38581 1/1 reg_rdata_next[7] = mio_pad_attr_21_input_disable_21_qs;
Tests: T104 T265 T105
38582 1/1 reg_rdata_next[17:16] = mio_pad_attr_21_slew_rate_21_qs;
Tests: T104 T265 T105
38583 1/1 reg_rdata_next[23:20] = mio_pad_attr_21_drive_strength_21_qs;
Tests: T104 T265 T105
38584 end
38585
38586 addr_hit[278]: begin
38587 1/1 reg_rdata_next[0] = mio_pad_attr_22_invert_22_qs;
Tests: T104 T265 T105
38588 1/1 reg_rdata_next[1] = mio_pad_attr_22_virtual_od_en_22_qs;
Tests: T104 T265 T105
38589 1/1 reg_rdata_next[2] = mio_pad_attr_22_pull_en_22_qs;
Tests: T104 T265 T105
38590 1/1 reg_rdata_next[3] = mio_pad_attr_22_pull_select_22_qs;
Tests: T104 T265 T105
38591 1/1 reg_rdata_next[4] = mio_pad_attr_22_keeper_en_22_qs;
Tests: T104 T265 T105
38592 1/1 reg_rdata_next[5] = mio_pad_attr_22_schmitt_en_22_qs;
Tests: T104 T265 T105
38593 1/1 reg_rdata_next[6] = mio_pad_attr_22_od_en_22_qs;
Tests: T104 T265 T105
38594 1/1 reg_rdata_next[7] = mio_pad_attr_22_input_disable_22_qs;
Tests: T104 T265 T105
38595 1/1 reg_rdata_next[17:16] = mio_pad_attr_22_slew_rate_22_qs;
Tests: T104 T265 T105
38596 1/1 reg_rdata_next[23:20] = mio_pad_attr_22_drive_strength_22_qs;
Tests: T104 T265 T105
38597 end
38598
38599 addr_hit[279]: begin
38600 1/1 reg_rdata_next[0] = mio_pad_attr_23_invert_23_qs;
Tests: T104 T265 T105
38601 1/1 reg_rdata_next[1] = mio_pad_attr_23_virtual_od_en_23_qs;
Tests: T104 T265 T105
38602 1/1 reg_rdata_next[2] = mio_pad_attr_23_pull_en_23_qs;
Tests: T104 T265 T105
38603 1/1 reg_rdata_next[3] = mio_pad_attr_23_pull_select_23_qs;
Tests: T104 T265 T105
38604 1/1 reg_rdata_next[4] = mio_pad_attr_23_keeper_en_23_qs;
Tests: T104 T265 T105
38605 1/1 reg_rdata_next[5] = mio_pad_attr_23_schmitt_en_23_qs;
Tests: T104 T265 T105
38606 1/1 reg_rdata_next[6] = mio_pad_attr_23_od_en_23_qs;
Tests: T104 T265 T105
38607 1/1 reg_rdata_next[7] = mio_pad_attr_23_input_disable_23_qs;
Tests: T104 T265 T105
38608 1/1 reg_rdata_next[17:16] = mio_pad_attr_23_slew_rate_23_qs;
Tests: T104 T265 T105
38609 1/1 reg_rdata_next[23:20] = mio_pad_attr_23_drive_strength_23_qs;
Tests: T104 T265 T105
38610 end
38611
38612 addr_hit[280]: begin
38613 1/1 reg_rdata_next[0] = mio_pad_attr_24_invert_24_qs;
Tests: T104 T265 T266
38614 1/1 reg_rdata_next[1] = mio_pad_attr_24_virtual_od_en_24_qs;
Tests: T104 T265 T266
38615 1/1 reg_rdata_next[2] = mio_pad_attr_24_pull_en_24_qs;
Tests: T104 T265 T266
38616 1/1 reg_rdata_next[3] = mio_pad_attr_24_pull_select_24_qs;
Tests: T104 T265 T266
38617 1/1 reg_rdata_next[4] = mio_pad_attr_24_keeper_en_24_qs;
Tests: T104 T265 T266
38618 1/1 reg_rdata_next[5] = mio_pad_attr_24_schmitt_en_24_qs;
Tests: T104 T265 T266
38619 1/1 reg_rdata_next[6] = mio_pad_attr_24_od_en_24_qs;
Tests: T104 T265 T266
38620 1/1 reg_rdata_next[7] = mio_pad_attr_24_input_disable_24_qs;
Tests: T104 T265 T266
38621 1/1 reg_rdata_next[17:16] = mio_pad_attr_24_slew_rate_24_qs;
Tests: T104 T265 T266
38622 1/1 reg_rdata_next[23:20] = mio_pad_attr_24_drive_strength_24_qs;
Tests: T104 T265 T266
38623 end
38624
38625 addr_hit[281]: begin
38626 1/1 reg_rdata_next[0] = mio_pad_attr_25_invert_25_qs;
Tests: T1 T2 T3
38627 1/1 reg_rdata_next[1] = mio_pad_attr_25_virtual_od_en_25_qs;
Tests: T1 T2 T3
38628 1/1 reg_rdata_next[2] = mio_pad_attr_25_pull_en_25_qs;
Tests: T1 T2 T3
38629 1/1 reg_rdata_next[3] = mio_pad_attr_25_pull_select_25_qs;
Tests: T1 T2 T3
38630 1/1 reg_rdata_next[4] = mio_pad_attr_25_keeper_en_25_qs;
Tests: T1 T2 T3
38631 1/1 reg_rdata_next[5] = mio_pad_attr_25_schmitt_en_25_qs;
Tests: T1 T2 T3
38632 1/1 reg_rdata_next[6] = mio_pad_attr_25_od_en_25_qs;
Tests: T1 T2 T3
38633 1/1 reg_rdata_next[7] = mio_pad_attr_25_input_disable_25_qs;
Tests: T1 T2 T3
38634 1/1 reg_rdata_next[17:16] = mio_pad_attr_25_slew_rate_25_qs;
Tests: T1 T2 T3
38635 1/1 reg_rdata_next[23:20] = mio_pad_attr_25_drive_strength_25_qs;
Tests: T1 T2 T3
38636 end
38637
38638 addr_hit[282]: begin
38639 1/1 reg_rdata_next[0] = mio_pad_attr_26_invert_26_qs;
Tests: T104 T265 T105
38640 1/1 reg_rdata_next[1] = mio_pad_attr_26_virtual_od_en_26_qs;
Tests: T104 T265 T105
38641 1/1 reg_rdata_next[2] = mio_pad_attr_26_pull_en_26_qs;
Tests: T104 T265 T105
38642 1/1 reg_rdata_next[3] = mio_pad_attr_26_pull_select_26_qs;
Tests: T104 T265 T105
38643 1/1 reg_rdata_next[4] = mio_pad_attr_26_keeper_en_26_qs;
Tests: T104 T265 T105
38644 1/1 reg_rdata_next[5] = mio_pad_attr_26_schmitt_en_26_qs;
Tests: T104 T265 T105
38645 1/1 reg_rdata_next[6] = mio_pad_attr_26_od_en_26_qs;
Tests: T104 T265 T105
38646 1/1 reg_rdata_next[7] = mio_pad_attr_26_input_disable_26_qs;
Tests: T104 T265 T105
38647 1/1 reg_rdata_next[17:16] = mio_pad_attr_26_slew_rate_26_qs;
Tests: T104 T265 T105
38648 1/1 reg_rdata_next[23:20] = mio_pad_attr_26_drive_strength_26_qs;
Tests: T104 T265 T105
38649 end
38650
38651 addr_hit[283]: begin
38652 1/1 reg_rdata_next[0] = mio_pad_attr_27_invert_27_qs;
Tests: T104 T265 T105
38653 1/1 reg_rdata_next[1] = mio_pad_attr_27_virtual_od_en_27_qs;
Tests: T104 T265 T105
38654 1/1 reg_rdata_next[2] = mio_pad_attr_27_pull_en_27_qs;
Tests: T104 T265 T105
38655 1/1 reg_rdata_next[3] = mio_pad_attr_27_pull_select_27_qs;
Tests: T104 T265 T105
38656 1/1 reg_rdata_next[4] = mio_pad_attr_27_keeper_en_27_qs;
Tests: T104 T265 T105
38657 1/1 reg_rdata_next[5] = mio_pad_attr_27_schmitt_en_27_qs;
Tests: T104 T265 T105
38658 1/1 reg_rdata_next[6] = mio_pad_attr_27_od_en_27_qs;
Tests: T104 T265 T105
38659 1/1 reg_rdata_next[7] = mio_pad_attr_27_input_disable_27_qs;
Tests: T104 T265 T105
38660 1/1 reg_rdata_next[17:16] = mio_pad_attr_27_slew_rate_27_qs;
Tests: T104 T265 T105
38661 1/1 reg_rdata_next[23:20] = mio_pad_attr_27_drive_strength_27_qs;
Tests: T104 T265 T105
38662 end
38663
38664 addr_hit[284]: begin
38665 1/1 reg_rdata_next[0] = mio_pad_attr_28_invert_28_qs;
Tests: T104 T265 T105
38666 1/1 reg_rdata_next[1] = mio_pad_attr_28_virtual_od_en_28_qs;
Tests: T104 T265 T105
38667 1/1 reg_rdata_next[2] = mio_pad_attr_28_pull_en_28_qs;
Tests: T104 T265 T105
38668 1/1 reg_rdata_next[3] = mio_pad_attr_28_pull_select_28_qs;
Tests: T104 T265 T105
38669 1/1 reg_rdata_next[4] = mio_pad_attr_28_keeper_en_28_qs;
Tests: T104 T265 T105
38670 1/1 reg_rdata_next[5] = mio_pad_attr_28_schmitt_en_28_qs;
Tests: T104 T265 T105
38671 1/1 reg_rdata_next[6] = mio_pad_attr_28_od_en_28_qs;
Tests: T104 T265 T105
38672 1/1 reg_rdata_next[7] = mio_pad_attr_28_input_disable_28_qs;
Tests: T104 T265 T105
38673 1/1 reg_rdata_next[17:16] = mio_pad_attr_28_slew_rate_28_qs;
Tests: T104 T265 T105
38674 1/1 reg_rdata_next[23:20] = mio_pad_attr_28_drive_strength_28_qs;
Tests: T104 T265 T105
38675 end
38676
38677 addr_hit[285]: begin
38678 1/1 reg_rdata_next[0] = mio_pad_attr_29_invert_29_qs;
Tests: T104 T265 T105
38679 1/1 reg_rdata_next[1] = mio_pad_attr_29_virtual_od_en_29_qs;
Tests: T104 T265 T105
38680 1/1 reg_rdata_next[2] = mio_pad_attr_29_pull_en_29_qs;
Tests: T104 T265 T105
38681 1/1 reg_rdata_next[3] = mio_pad_attr_29_pull_select_29_qs;
Tests: T104 T265 T105
38682 1/1 reg_rdata_next[4] = mio_pad_attr_29_keeper_en_29_qs;
Tests: T104 T265 T105
38683 1/1 reg_rdata_next[5] = mio_pad_attr_29_schmitt_en_29_qs;
Tests: T104 T265 T105
38684 1/1 reg_rdata_next[6] = mio_pad_attr_29_od_en_29_qs;
Tests: T104 T265 T105
38685 1/1 reg_rdata_next[7] = mio_pad_attr_29_input_disable_29_qs;
Tests: T104 T265 T105
38686 1/1 reg_rdata_next[17:16] = mio_pad_attr_29_slew_rate_29_qs;
Tests: T104 T265 T105
38687 1/1 reg_rdata_next[23:20] = mio_pad_attr_29_drive_strength_29_qs;
Tests: T104 T265 T105
38688 end
38689
38690 addr_hit[286]: begin
38691 1/1 reg_rdata_next[0] = mio_pad_attr_30_invert_30_qs;
Tests: T104 T265 T105
38692 1/1 reg_rdata_next[1] = mio_pad_attr_30_virtual_od_en_30_qs;
Tests: T104 T265 T105
38693 1/1 reg_rdata_next[2] = mio_pad_attr_30_pull_en_30_qs;
Tests: T104 T265 T105
38694 1/1 reg_rdata_next[3] = mio_pad_attr_30_pull_select_30_qs;
Tests: T104 T265 T105
38695 1/1 reg_rdata_next[4] = mio_pad_attr_30_keeper_en_30_qs;
Tests: T104 T265 T105
38696 1/1 reg_rdata_next[5] = mio_pad_attr_30_schmitt_en_30_qs;
Tests: T104 T265 T105
38697 1/1 reg_rdata_next[6] = mio_pad_attr_30_od_en_30_qs;
Tests: T104 T265 T105
38698 1/1 reg_rdata_next[7] = mio_pad_attr_30_input_disable_30_qs;
Tests: T104 T265 T105
38699 1/1 reg_rdata_next[17:16] = mio_pad_attr_30_slew_rate_30_qs;
Tests: T104 T265 T105
38700 1/1 reg_rdata_next[23:20] = mio_pad_attr_30_drive_strength_30_qs;
Tests: T104 T265 T105
38701 end
38702
38703 addr_hit[287]: begin
38704 1/1 reg_rdata_next[0] = mio_pad_attr_31_invert_31_qs;
Tests: T265 T266 T105
38705 1/1 reg_rdata_next[1] = mio_pad_attr_31_virtual_od_en_31_qs;
Tests: T265 T266 T105
38706 1/1 reg_rdata_next[2] = mio_pad_attr_31_pull_en_31_qs;
Tests: T265 T266 T105
38707 1/1 reg_rdata_next[3] = mio_pad_attr_31_pull_select_31_qs;
Tests: T265 T266 T105
38708 1/1 reg_rdata_next[4] = mio_pad_attr_31_keeper_en_31_qs;
Tests: T265 T266 T105
38709 1/1 reg_rdata_next[5] = mio_pad_attr_31_schmitt_en_31_qs;
Tests: T265 T266 T105
38710 1/1 reg_rdata_next[6] = mio_pad_attr_31_od_en_31_qs;
Tests: T265 T266 T105
38711 1/1 reg_rdata_next[7] = mio_pad_attr_31_input_disable_31_qs;
Tests: T265 T266 T105
38712 1/1 reg_rdata_next[17:16] = mio_pad_attr_31_slew_rate_31_qs;
Tests: T265 T266 T105
38713 1/1 reg_rdata_next[23:20] = mio_pad_attr_31_drive_strength_31_qs;
Tests: T265 T266 T105
38714 end
38715
38716 addr_hit[288]: begin
38717 1/1 reg_rdata_next[0] = mio_pad_attr_32_invert_32_qs;
Tests: T265 T105 T460
38718 1/1 reg_rdata_next[1] = mio_pad_attr_32_virtual_od_en_32_qs;
Tests: T265 T105 T460
38719 1/1 reg_rdata_next[2] = mio_pad_attr_32_pull_en_32_qs;
Tests: T265 T105 T460
38720 1/1 reg_rdata_next[3] = mio_pad_attr_32_pull_select_32_qs;
Tests: T265 T105 T460
38721 1/1 reg_rdata_next[4] = mio_pad_attr_32_keeper_en_32_qs;
Tests: T265 T105 T460
38722 1/1 reg_rdata_next[5] = mio_pad_attr_32_schmitt_en_32_qs;
Tests: T265 T105 T460
38723 1/1 reg_rdata_next[6] = mio_pad_attr_32_od_en_32_qs;
Tests: T265 T105 T460
38724 1/1 reg_rdata_next[7] = mio_pad_attr_32_input_disable_32_qs;
Tests: T265 T105 T460
38725 1/1 reg_rdata_next[17:16] = mio_pad_attr_32_slew_rate_32_qs;
Tests: T265 T105 T460
38726 1/1 reg_rdata_next[23:20] = mio_pad_attr_32_drive_strength_32_qs;
Tests: T265 T105 T460
38727 end
38728
38729 addr_hit[289]: begin
38730 1/1 reg_rdata_next[0] = mio_pad_attr_33_invert_33_qs;
Tests: T265 T105 T460
38731 1/1 reg_rdata_next[1] = mio_pad_attr_33_virtual_od_en_33_qs;
Tests: T265 T105 T460
38732 1/1 reg_rdata_next[2] = mio_pad_attr_33_pull_en_33_qs;
Tests: T265 T105 T460
38733 1/1 reg_rdata_next[3] = mio_pad_attr_33_pull_select_33_qs;
Tests: T265 T105 T460
38734 1/1 reg_rdata_next[4] = mio_pad_attr_33_keeper_en_33_qs;
Tests: T265 T105 T460
38735 1/1 reg_rdata_next[5] = mio_pad_attr_33_schmitt_en_33_qs;
Tests: T265 T105 T460
38736 1/1 reg_rdata_next[6] = mio_pad_attr_33_od_en_33_qs;
Tests: T265 T105 T460
38737 1/1 reg_rdata_next[7] = mio_pad_attr_33_input_disable_33_qs;
Tests: T265 T105 T460
38738 1/1 reg_rdata_next[17:16] = mio_pad_attr_33_slew_rate_33_qs;
Tests: T265 T105 T460
38739 1/1 reg_rdata_next[23:20] = mio_pad_attr_33_drive_strength_33_qs;
Tests: T265 T105 T460
38740 end
38741
38742 addr_hit[290]: begin
38743 1/1 reg_rdata_next[0] = mio_pad_attr_34_invert_34_qs;
Tests: T265 T105 T460
38744 1/1 reg_rdata_next[1] = mio_pad_attr_34_virtual_od_en_34_qs;
Tests: T265 T105 T460
38745 1/1 reg_rdata_next[2] = mio_pad_attr_34_pull_en_34_qs;
Tests: T265 T105 T460
38746 1/1 reg_rdata_next[3] = mio_pad_attr_34_pull_select_34_qs;
Tests: T265 T105 T460
38747 1/1 reg_rdata_next[4] = mio_pad_attr_34_keeper_en_34_qs;
Tests: T265 T105 T460
38748 1/1 reg_rdata_next[5] = mio_pad_attr_34_schmitt_en_34_qs;
Tests: T265 T105 T460
38749 1/1 reg_rdata_next[6] = mio_pad_attr_34_od_en_34_qs;
Tests: T265 T105 T460
38750 1/1 reg_rdata_next[7] = mio_pad_attr_34_input_disable_34_qs;
Tests: T265 T105 T460
38751 1/1 reg_rdata_next[17:16] = mio_pad_attr_34_slew_rate_34_qs;
Tests: T265 T105 T460
38752 1/1 reg_rdata_next[23:20] = mio_pad_attr_34_drive_strength_34_qs;
Tests: T265 T105 T460
38753 end
38754
38755 addr_hit[291]: begin
38756 1/1 reg_rdata_next[0] = mio_pad_attr_35_invert_35_qs;
Tests: T265 T105 T460
38757 1/1 reg_rdata_next[1] = mio_pad_attr_35_virtual_od_en_35_qs;
Tests: T265 T105 T460
38758 1/1 reg_rdata_next[2] = mio_pad_attr_35_pull_en_35_qs;
Tests: T265 T105 T460
38759 1/1 reg_rdata_next[3] = mio_pad_attr_35_pull_select_35_qs;
Tests: T265 T105 T460
38760 1/1 reg_rdata_next[4] = mio_pad_attr_35_keeper_en_35_qs;
Tests: T265 T105 T460
38761 1/1 reg_rdata_next[5] = mio_pad_attr_35_schmitt_en_35_qs;
Tests: T265 T105 T460
38762 1/1 reg_rdata_next[6] = mio_pad_attr_35_od_en_35_qs;
Tests: T265 T105 T460
38763 1/1 reg_rdata_next[7] = mio_pad_attr_35_input_disable_35_qs;
Tests: T265 T105 T460
38764 1/1 reg_rdata_next[17:16] = mio_pad_attr_35_slew_rate_35_qs;
Tests: T265 T105 T460
38765 1/1 reg_rdata_next[23:20] = mio_pad_attr_35_drive_strength_35_qs;
Tests: T265 T105 T460
38766 end
38767
38768 addr_hit[292]: begin
38769 1/1 reg_rdata_next[0] = mio_pad_attr_36_invert_36_qs;
Tests: T265 T105 T460
38770 1/1 reg_rdata_next[1] = mio_pad_attr_36_virtual_od_en_36_qs;
Tests: T265 T105 T460
38771 1/1 reg_rdata_next[2] = mio_pad_attr_36_pull_en_36_qs;
Tests: T265 T105 T460
38772 1/1 reg_rdata_next[3] = mio_pad_attr_36_pull_select_36_qs;
Tests: T265 T105 T460
38773 1/1 reg_rdata_next[4] = mio_pad_attr_36_keeper_en_36_qs;
Tests: T265 T105 T460
38774 1/1 reg_rdata_next[5] = mio_pad_attr_36_schmitt_en_36_qs;
Tests: T265 T105 T460
38775 1/1 reg_rdata_next[6] = mio_pad_attr_36_od_en_36_qs;
Tests: T265 T105 T460
38776 1/1 reg_rdata_next[7] = mio_pad_attr_36_input_disable_36_qs;
Tests: T265 T105 T460
38777 1/1 reg_rdata_next[17:16] = mio_pad_attr_36_slew_rate_36_qs;
Tests: T265 T105 T460
38778 1/1 reg_rdata_next[23:20] = mio_pad_attr_36_drive_strength_36_qs;
Tests: T265 T105 T460
38779 end
38780
38781 addr_hit[293]: begin
38782 1/1 reg_rdata_next[0] = mio_pad_attr_37_invert_37_qs;
Tests: T265 T105 T460
38783 1/1 reg_rdata_next[1] = mio_pad_attr_37_virtual_od_en_37_qs;
Tests: T265 T105 T460
38784 1/1 reg_rdata_next[2] = mio_pad_attr_37_pull_en_37_qs;
Tests: T265 T105 T460
38785 1/1 reg_rdata_next[3] = mio_pad_attr_37_pull_select_37_qs;
Tests: T265 T105 T460
38786 1/1 reg_rdata_next[4] = mio_pad_attr_37_keeper_en_37_qs;
Tests: T265 T105 T460
38787 1/1 reg_rdata_next[5] = mio_pad_attr_37_schmitt_en_37_qs;
Tests: T265 T105 T460
38788 1/1 reg_rdata_next[6] = mio_pad_attr_37_od_en_37_qs;
Tests: T265 T105 T460
38789 1/1 reg_rdata_next[7] = mio_pad_attr_37_input_disable_37_qs;
Tests: T265 T105 T460
38790 1/1 reg_rdata_next[17:16] = mio_pad_attr_37_slew_rate_37_qs;
Tests: T265 T105 T460
38791 1/1 reg_rdata_next[23:20] = mio_pad_attr_37_drive_strength_37_qs;
Tests: T265 T105 T460
38792 end
38793
38794 addr_hit[294]: begin
38795 1/1 reg_rdata_next[0] = mio_pad_attr_38_invert_38_qs;
Tests: T198 T80 T264
38796 1/1 reg_rdata_next[1] = mio_pad_attr_38_virtual_od_en_38_qs;
Tests: T198 T80 T264
38797 1/1 reg_rdata_next[2] = mio_pad_attr_38_pull_en_38_qs;
Tests: T198 T80 T264
38798 1/1 reg_rdata_next[3] = mio_pad_attr_38_pull_select_38_qs;
Tests: T198 T80 T264
38799 1/1 reg_rdata_next[4] = mio_pad_attr_38_keeper_en_38_qs;
Tests: T198 T80 T264
38800 1/1 reg_rdata_next[5] = mio_pad_attr_38_schmitt_en_38_qs;
Tests: T198 T80 T264
38801 1/1 reg_rdata_next[6] = mio_pad_attr_38_od_en_38_qs;
Tests: T198 T80 T264
38802 1/1 reg_rdata_next[7] = mio_pad_attr_38_input_disable_38_qs;
Tests: T198 T80 T264
38803 1/1 reg_rdata_next[17:16] = mio_pad_attr_38_slew_rate_38_qs;
Tests: T198 T80 T264
38804 1/1 reg_rdata_next[23:20] = mio_pad_attr_38_drive_strength_38_qs;
Tests: T198 T80 T264
38805 end
38806
38807 addr_hit[295]: begin
38808 1/1 reg_rdata_next[0] = mio_pad_attr_39_invert_39_qs;
Tests: T198 T80 T264
38809 1/1 reg_rdata_next[1] = mio_pad_attr_39_virtual_od_en_39_qs;
Tests: T198 T80 T264
38810 1/1 reg_rdata_next[2] = mio_pad_attr_39_pull_en_39_qs;
Tests: T198 T80 T264
38811 1/1 reg_rdata_next[3] = mio_pad_attr_39_pull_select_39_qs;
Tests: T198 T80 T264
38812 1/1 reg_rdata_next[4] = mio_pad_attr_39_keeper_en_39_qs;
Tests: T198 T80 T264
38813 1/1 reg_rdata_next[5] = mio_pad_attr_39_schmitt_en_39_qs;
Tests: T198 T80 T264
38814 1/1 reg_rdata_next[6] = mio_pad_attr_39_od_en_39_qs;
Tests: T198 T80 T264
38815 1/1 reg_rdata_next[7] = mio_pad_attr_39_input_disable_39_qs;
Tests: T198 T80 T264
38816 1/1 reg_rdata_next[17:16] = mio_pad_attr_39_slew_rate_39_qs;
Tests: T198 T80 T264
38817 1/1 reg_rdata_next[23:20] = mio_pad_attr_39_drive_strength_39_qs;
Tests: T198 T80 T264
38818 end
38819
38820 addr_hit[296]: begin
38821 1/1 reg_rdata_next[0] = mio_pad_attr_40_invert_40_qs;
Tests: T461 T462 T101
38822 1/1 reg_rdata_next[1] = mio_pad_attr_40_virtual_od_en_40_qs;
Tests: T461 T462 T101
38823 1/1 reg_rdata_next[2] = mio_pad_attr_40_pull_en_40_qs;
Tests: T461 T462 T101
38824 1/1 reg_rdata_next[3] = mio_pad_attr_40_pull_select_40_qs;
Tests: T461 T462 T101
38825 1/1 reg_rdata_next[4] = mio_pad_attr_40_keeper_en_40_qs;
Tests: T461 T462 T101
38826 1/1 reg_rdata_next[5] = mio_pad_attr_40_schmitt_en_40_qs;
Tests: T461 T462 T101
38827 1/1 reg_rdata_next[6] = mio_pad_attr_40_od_en_40_qs;
Tests: T461 T462 T101
38828 1/1 reg_rdata_next[7] = mio_pad_attr_40_input_disable_40_qs;
Tests: T461 T462 T101
38829 1/1 reg_rdata_next[17:16] = mio_pad_attr_40_slew_rate_40_qs;
Tests: T461 T462 T101
38830 1/1 reg_rdata_next[23:20] = mio_pad_attr_40_drive_strength_40_qs;
Tests: T461 T462 T101
38831 end
38832
38833 addr_hit[297]: begin
38834 1/1 reg_rdata_next[0] = mio_pad_attr_41_invert_41_qs;
Tests: T461 T246 T463
38835 1/1 reg_rdata_next[1] = mio_pad_attr_41_virtual_od_en_41_qs;
Tests: T461 T246 T463
38836 1/1 reg_rdata_next[2] = mio_pad_attr_41_pull_en_41_qs;
Tests: T461 T246 T463
38837 1/1 reg_rdata_next[3] = mio_pad_attr_41_pull_select_41_qs;
Tests: T461 T246 T463
38838 1/1 reg_rdata_next[4] = mio_pad_attr_41_keeper_en_41_qs;
Tests: T461 T246 T463
38839 1/1 reg_rdata_next[5] = mio_pad_attr_41_schmitt_en_41_qs;
Tests: T461 T246 T463
38840 1/1 reg_rdata_next[6] = mio_pad_attr_41_od_en_41_qs;
Tests: T461 T246 T463
38841 1/1 reg_rdata_next[7] = mio_pad_attr_41_input_disable_41_qs;
Tests: T461 T246 T463
38842 1/1 reg_rdata_next[17:16] = mio_pad_attr_41_slew_rate_41_qs;
Tests: T461 T246 T463
38843 1/1 reg_rdata_next[23:20] = mio_pad_attr_41_drive_strength_41_qs;
Tests: T461 T246 T463
38844 end
38845
38846 addr_hit[298]: begin
38847 1/1 reg_rdata_next[0] = mio_pad_attr_42_invert_42_qs;
Tests: T101 T276 T464
38848 1/1 reg_rdata_next[1] = mio_pad_attr_42_virtual_od_en_42_qs;
Tests: T101 T276 T464
38849 1/1 reg_rdata_next[2] = mio_pad_attr_42_pull_en_42_qs;
Tests: T101 T276 T464
38850 1/1 reg_rdata_next[3] = mio_pad_attr_42_pull_select_42_qs;
Tests: T101 T276 T464
38851 1/1 reg_rdata_next[4] = mio_pad_attr_42_keeper_en_42_qs;
Tests: T101 T276 T464
38852 1/1 reg_rdata_next[5] = mio_pad_attr_42_schmitt_en_42_qs;
Tests: T101 T276 T464
38853 1/1 reg_rdata_next[6] = mio_pad_attr_42_od_en_42_qs;
Tests: T101 T276 T464
38854 1/1 reg_rdata_next[7] = mio_pad_attr_42_input_disable_42_qs;
Tests: T101 T276 T464
38855 1/1 reg_rdata_next[17:16] = mio_pad_attr_42_slew_rate_42_qs;
Tests: T101 T276 T464
38856 1/1 reg_rdata_next[23:20] = mio_pad_attr_42_drive_strength_42_qs;
Tests: T101 T276 T464
38857 end
38858
38859 addr_hit[299]: begin
38860 1/1 reg_rdata_next[0] = mio_pad_attr_43_invert_43_qs;
Tests: T198 T80 T264
38861 1/1 reg_rdata_next[1] = mio_pad_attr_43_virtual_od_en_43_qs;
Tests: T198 T80 T264
38862 1/1 reg_rdata_next[2] = mio_pad_attr_43_pull_en_43_qs;
Tests: T198 T80 T264
38863 1/1 reg_rdata_next[3] = mio_pad_attr_43_pull_select_43_qs;
Tests: T198 T80 T264
38864 1/1 reg_rdata_next[4] = mio_pad_attr_43_keeper_en_43_qs;
Tests: T198 T80 T264
38865 1/1 reg_rdata_next[5] = mio_pad_attr_43_schmitt_en_43_qs;
Tests: T198 T80 T264
38866 1/1 reg_rdata_next[6] = mio_pad_attr_43_od_en_43_qs;
Tests: T198 T80 T264
38867 1/1 reg_rdata_next[7] = mio_pad_attr_43_input_disable_43_qs;
Tests: T198 T80 T264
38868 1/1 reg_rdata_next[17:16] = mio_pad_attr_43_slew_rate_43_qs;
Tests: T198 T80 T264
38869 1/1 reg_rdata_next[23:20] = mio_pad_attr_43_drive_strength_43_qs;
Tests: T198 T80 T264
38870 end
38871
38872 addr_hit[300]: begin
38873 1/1 reg_rdata_next[0] = mio_pad_attr_44_invert_44_qs;
Tests: T198 T80 T264
38874 1/1 reg_rdata_next[1] = mio_pad_attr_44_virtual_od_en_44_qs;
Tests: T198 T80 T264
38875 1/1 reg_rdata_next[2] = mio_pad_attr_44_pull_en_44_qs;
Tests: T198 T80 T264
38876 1/1 reg_rdata_next[3] = mio_pad_attr_44_pull_select_44_qs;
Tests: T198 T80 T264
38877 1/1 reg_rdata_next[4] = mio_pad_attr_44_keeper_en_44_qs;
Tests: T198 T80 T264
38878 1/1 reg_rdata_next[5] = mio_pad_attr_44_schmitt_en_44_qs;
Tests: T198 T80 T264
38879 1/1 reg_rdata_next[6] = mio_pad_attr_44_od_en_44_qs;
Tests: T198 T80 T264
38880 1/1 reg_rdata_next[7] = mio_pad_attr_44_input_disable_44_qs;
Tests: T198 T80 T264
38881 1/1 reg_rdata_next[17:16] = mio_pad_attr_44_slew_rate_44_qs;
Tests: T198 T80 T264
38882 1/1 reg_rdata_next[23:20] = mio_pad_attr_44_drive_strength_44_qs;
Tests: T198 T80 T264
38883 end
38884
38885 addr_hit[301]: begin
38886 1/1 reg_rdata_next[0] = mio_pad_attr_45_invert_45_qs;
Tests: T198 T80 T264
38887 1/1 reg_rdata_next[1] = mio_pad_attr_45_virtual_od_en_45_qs;
Tests: T198 T80 T264
38888 1/1 reg_rdata_next[2] = mio_pad_attr_45_pull_en_45_qs;
Tests: T198 T80 T264
38889 1/1 reg_rdata_next[3] = mio_pad_attr_45_pull_select_45_qs;
Tests: T198 T80 T264
38890 1/1 reg_rdata_next[4] = mio_pad_attr_45_keeper_en_45_qs;
Tests: T198 T80 T264
38891 1/1 reg_rdata_next[5] = mio_pad_attr_45_schmitt_en_45_qs;
Tests: T198 T80 T264
38892 1/1 reg_rdata_next[6] = mio_pad_attr_45_od_en_45_qs;
Tests: T198 T80 T264
38893 1/1 reg_rdata_next[7] = mio_pad_attr_45_input_disable_45_qs;
Tests: T198 T80 T264
38894 1/1 reg_rdata_next[17:16] = mio_pad_attr_45_slew_rate_45_qs;
Tests: T198 T80 T264
38895 1/1 reg_rdata_next[23:20] = mio_pad_attr_45_drive_strength_45_qs;
Tests: T198 T80 T264
38896 end
38897
38898 addr_hit[302]: begin
38899 1/1 reg_rdata_next[0] = mio_pad_attr_46_invert_46_qs;
Tests: T198 T80 T264
38900 1/1 reg_rdata_next[1] = mio_pad_attr_46_virtual_od_en_46_qs;
Tests: T198 T80 T264
38901 1/1 reg_rdata_next[2] = mio_pad_attr_46_pull_en_46_qs;
Tests: T198 T80 T264
38902 1/1 reg_rdata_next[3] = mio_pad_attr_46_pull_select_46_qs;
Tests: T198 T80 T264
38903 1/1 reg_rdata_next[4] = mio_pad_attr_46_keeper_en_46_qs;
Tests: T198 T80 T264
38904 1/1 reg_rdata_next[5] = mio_pad_attr_46_schmitt_en_46_qs;
Tests: T198 T80 T264
38905 1/1 reg_rdata_next[6] = mio_pad_attr_46_od_en_46_qs;
Tests: T198 T80 T264
38906 1/1 reg_rdata_next[7] = mio_pad_attr_46_input_disable_46_qs;
Tests: T198 T80 T264
38907 1/1 reg_rdata_next[17:16] = mio_pad_attr_46_slew_rate_46_qs;
Tests: T198 T80 T264
38908 1/1 reg_rdata_next[23:20] = mio_pad_attr_46_drive_strength_46_qs;
Tests: T198 T80 T264
38909 end
38910
38911 addr_hit[303]: begin
38912 1/1 reg_rdata_next[0] = dio_pad_attr_regwen_0_qs;
Tests: T1 T2 T3
38913 end
38914
38915 addr_hit[304]: begin
38916 1/1 reg_rdata_next[0] = dio_pad_attr_regwen_1_qs;
Tests: T1 T2 T3
38917 end
38918
38919 addr_hit[305]: begin
38920 1/1 reg_rdata_next[0] = dio_pad_attr_regwen_2_qs;
Tests: T9 T10 T11
38921 end
38922
38923 addr_hit[306]: begin
38924 1/1 reg_rdata_next[0] = dio_pad_attr_regwen_3_qs;
Tests: T9 T10 T11
38925 end
38926
38927 addr_hit[307]: begin
38928 1/1 reg_rdata_next[0] = dio_pad_attr_regwen_4_qs;
Tests: T9 T10 T11
38929 end
38930
38931 addr_hit[308]: begin
38932 1/1 reg_rdata_next[0] = dio_pad_attr_regwen_5_qs;
Tests: T9 T10 T86
38933 end
38934
38935 addr_hit[309]: begin
38936 1/1 reg_rdata_next[0] = dio_pad_attr_regwen_6_qs;
Tests: T86 T87 T80
38937 end
38938
38939 addr_hit[310]: begin
38940 1/1 reg_rdata_next[0] = dio_pad_attr_regwen_7_qs;
Tests: T101 T71 T98
38941 end
38942
38943 addr_hit[311]: begin
38944 1/1 reg_rdata_next[0] = dio_pad_attr_regwen_8_qs;
Tests: T101 T71 T465
38945 end
38946
38947 addr_hit[312]: begin
38948 1/1 reg_rdata_next[0] = dio_pad_attr_regwen_9_qs;
Tests: T101 T71 T103
38949 end
38950
38951 addr_hit[313]: begin
38952 1/1 reg_rdata_next[0] = dio_pad_attr_regwen_10_qs;
Tests: T86 T87 T15
38953 end
38954
38955 addr_hit[314]: begin
38956 1/1 reg_rdata_next[0] = dio_pad_attr_regwen_11_qs;
Tests: T86 T87 T15
38957 end
38958
38959 addr_hit[315]: begin
38960 1/1 reg_rdata_next[0] = dio_pad_attr_regwen_12_qs;
Tests: T86 T87 T80
38961 end
38962
38963 addr_hit[316]: begin
38964 1/1 reg_rdata_next[0] = dio_pad_attr_regwen_13_qs;
Tests: T86 T87 T80
38965 end
38966
38967 addr_hit[317]: begin
38968 1/1 reg_rdata_next[0] = dio_pad_attr_regwen_14_qs;
Tests: T9 T86 T87
38969 end
38970
38971 addr_hit[318]: begin
38972 1/1 reg_rdata_next[0] = dio_pad_attr_regwen_15_qs;
Tests: T9 T86 T87
38973 end
38974
38975 addr_hit[319]: begin
38976 1/1 reg_rdata_next[0] = dio_pad_attr_0_invert_0_qs;
Tests: T1 T2 T3
38977 1/1 reg_rdata_next[1] = dio_pad_attr_0_virtual_od_en_0_qs;
Tests: T1 T2 T3
38978 1/1 reg_rdata_next[2] = dio_pad_attr_0_pull_en_0_qs;
Tests: T1 T2 T3
38979 1/1 reg_rdata_next[3] = dio_pad_attr_0_pull_select_0_qs;
Tests: T1 T2 T3
38980 1/1 reg_rdata_next[4] = dio_pad_attr_0_keeper_en_0_qs;
Tests: T1 T2 T3
38981 1/1 reg_rdata_next[5] = dio_pad_attr_0_schmitt_en_0_qs;
Tests: T1 T2 T3
38982 1/1 reg_rdata_next[6] = dio_pad_attr_0_od_en_0_qs;
Tests: T1 T2 T3
38983 1/1 reg_rdata_next[7] = dio_pad_attr_0_input_disable_0_qs;
Tests: T1 T2 T3
38984 1/1 reg_rdata_next[17:16] = dio_pad_attr_0_slew_rate_0_qs;
Tests: T1 T2 T3
38985 1/1 reg_rdata_next[23:20] = dio_pad_attr_0_drive_strength_0_qs;
Tests: T1 T2 T3
38986 end
38987
38988 addr_hit[320]: begin
38989 1/1 reg_rdata_next[0] = dio_pad_attr_1_invert_1_qs;
Tests: T1 T2 T3
38990 1/1 reg_rdata_next[1] = dio_pad_attr_1_virtual_od_en_1_qs;
Tests: T1 T2 T3
38991 1/1 reg_rdata_next[2] = dio_pad_attr_1_pull_en_1_qs;
Tests: T1 T2 T3
38992 1/1 reg_rdata_next[3] = dio_pad_attr_1_pull_select_1_qs;
Tests: T1 T2 T3
38993 1/1 reg_rdata_next[4] = dio_pad_attr_1_keeper_en_1_qs;
Tests: T1 T2 T3
38994 1/1 reg_rdata_next[5] = dio_pad_attr_1_schmitt_en_1_qs;
Tests: T1 T2 T3
38995 1/1 reg_rdata_next[6] = dio_pad_attr_1_od_en_1_qs;
Tests: T1 T2 T3
38996 1/1 reg_rdata_next[7] = dio_pad_attr_1_input_disable_1_qs;
Tests: T1 T2 T3
38997 1/1 reg_rdata_next[17:16] = dio_pad_attr_1_slew_rate_1_qs;
Tests: T1 T2 T3
38998 1/1 reg_rdata_next[23:20] = dio_pad_attr_1_drive_strength_1_qs;
Tests: T1 T2 T3
38999 end
39000
39001 addr_hit[321]: begin
39002 1/1 reg_rdata_next[0] = dio_pad_attr_2_invert_2_qs;
Tests: T9 T10 T86
39003 1/1 reg_rdata_next[1] = dio_pad_attr_2_virtual_od_en_2_qs;
Tests: T9 T10 T86
39004 1/1 reg_rdata_next[2] = dio_pad_attr_2_pull_en_2_qs;
Tests: T9 T10 T86
39005 1/1 reg_rdata_next[3] = dio_pad_attr_2_pull_select_2_qs;
Tests: T9 T10 T86
39006 1/1 reg_rdata_next[4] = dio_pad_attr_2_keeper_en_2_qs;
Tests: T9 T10 T86
39007 1/1 reg_rdata_next[5] = dio_pad_attr_2_schmitt_en_2_qs;
Tests: T9 T10 T86
39008 1/1 reg_rdata_next[6] = dio_pad_attr_2_od_en_2_qs;
Tests: T9 T10 T86
39009 1/1 reg_rdata_next[7] = dio_pad_attr_2_input_disable_2_qs;
Tests: T9 T10 T86
39010 1/1 reg_rdata_next[17:16] = dio_pad_attr_2_slew_rate_2_qs;
Tests: T9 T10 T86
39011 1/1 reg_rdata_next[23:20] = dio_pad_attr_2_drive_strength_2_qs;
Tests: T9 T10 T86
39012 end
39013
39014 addr_hit[322]: begin
39015 1/1 reg_rdata_next[0] = dio_pad_attr_3_invert_3_qs;
Tests: T9 T10 T11
39016 1/1 reg_rdata_next[1] = dio_pad_attr_3_virtual_od_en_3_qs;
Tests: T9 T10 T11
39017 1/1 reg_rdata_next[2] = dio_pad_attr_3_pull_en_3_qs;
Tests: T9 T10 T11
39018 1/1 reg_rdata_next[3] = dio_pad_attr_3_pull_select_3_qs;
Tests: T9 T10 T11
39019 1/1 reg_rdata_next[4] = dio_pad_attr_3_keeper_en_3_qs;
Tests: T9 T10 T11
39020 1/1 reg_rdata_next[5] = dio_pad_attr_3_schmitt_en_3_qs;
Tests: T9 T10 T11
39021 1/1 reg_rdata_next[6] = dio_pad_attr_3_od_en_3_qs;
Tests: T9 T10 T11
39022 1/1 reg_rdata_next[7] = dio_pad_attr_3_input_disable_3_qs;
Tests: T9 T10 T11
39023 1/1 reg_rdata_next[17:16] = dio_pad_attr_3_slew_rate_3_qs;
Tests: T9 T10 T11
39024 1/1 reg_rdata_next[23:20] = dio_pad_attr_3_drive_strength_3_qs;
Tests: T9 T10 T11
39025 end
39026
39027 addr_hit[323]: begin
39028 1/1 reg_rdata_next[0] = dio_pad_attr_4_invert_4_qs;
Tests: T9 T10 T11
39029 1/1 reg_rdata_next[1] = dio_pad_attr_4_virtual_od_en_4_qs;
Tests: T9 T10 T11
39030 1/1 reg_rdata_next[2] = dio_pad_attr_4_pull_en_4_qs;
Tests: T9 T10 T11
39031 1/1 reg_rdata_next[3] = dio_pad_attr_4_pull_select_4_qs;
Tests: T9 T10 T11
39032 1/1 reg_rdata_next[4] = dio_pad_attr_4_keeper_en_4_qs;
Tests: T9 T10 T11
39033 1/1 reg_rdata_next[5] = dio_pad_attr_4_schmitt_en_4_qs;
Tests: T9 T10 T11
39034 1/1 reg_rdata_next[6] = dio_pad_attr_4_od_en_4_qs;
Tests: T9 T10 T11
39035 1/1 reg_rdata_next[7] = dio_pad_attr_4_input_disable_4_qs;
Tests: T9 T10 T11
39036 1/1 reg_rdata_next[17:16] = dio_pad_attr_4_slew_rate_4_qs;
Tests: T9 T10 T11
39037 1/1 reg_rdata_next[23:20] = dio_pad_attr_4_drive_strength_4_qs;
Tests: T9 T10 T11
39038 end
39039
39040 addr_hit[324]: begin
39041 1/1 reg_rdata_next[0] = dio_pad_attr_5_invert_5_qs;
Tests: T9 T10 T11
39042 1/1 reg_rdata_next[1] = dio_pad_attr_5_virtual_od_en_5_qs;
Tests: T9 T10 T11
39043 1/1 reg_rdata_next[2] = dio_pad_attr_5_pull_en_5_qs;
Tests: T9 T10 T11
39044 1/1 reg_rdata_next[3] = dio_pad_attr_5_pull_select_5_qs;
Tests: T9 T10 T11
39045 1/1 reg_rdata_next[4] = dio_pad_attr_5_keeper_en_5_qs;
Tests: T9 T10 T11
39046 1/1 reg_rdata_next[5] = dio_pad_attr_5_schmitt_en_5_qs;
Tests: T9 T10 T11
39047 1/1 reg_rdata_next[6] = dio_pad_attr_5_od_en_5_qs;
Tests: T9 T10 T11
39048 1/1 reg_rdata_next[7] = dio_pad_attr_5_input_disable_5_qs;
Tests: T9 T10 T11
39049 1/1 reg_rdata_next[17:16] = dio_pad_attr_5_slew_rate_5_qs;
Tests: T9 T10 T11
39050 1/1 reg_rdata_next[23:20] = dio_pad_attr_5_drive_strength_5_qs;
Tests: T9 T10 T11
39051 end
39052
39053 addr_hit[325]: begin
39054 1/1 reg_rdata_next[0] = dio_pad_attr_6_invert_6_qs;
Tests: T101 T98 T465
39055 1/1 reg_rdata_next[1] = dio_pad_attr_6_virtual_od_en_6_qs;
Tests: T101 T98 T465
39056 1/1 reg_rdata_next[2] = dio_pad_attr_6_pull_en_6_qs;
Tests: T101 T98 T465
39057 1/1 reg_rdata_next[3] = dio_pad_attr_6_pull_select_6_qs;
Tests: T101 T98 T465
39058 1/1 reg_rdata_next[4] = dio_pad_attr_6_keeper_en_6_qs;
Tests: T101 T98 T465
39059 1/1 reg_rdata_next[5] = dio_pad_attr_6_schmitt_en_6_qs;
Tests: T101 T98 T465
39060 1/1 reg_rdata_next[6] = dio_pad_attr_6_od_en_6_qs;
Tests: T101 T98 T465
39061 1/1 reg_rdata_next[7] = dio_pad_attr_6_input_disable_6_qs;
Tests: T101 T98 T465
39062 1/1 reg_rdata_next[17:16] = dio_pad_attr_6_slew_rate_6_qs;
Tests: T101 T98 T465
39063 1/1 reg_rdata_next[23:20] = dio_pad_attr_6_drive_strength_6_qs;
Tests: T101 T98 T465
39064 end
39065
39066 addr_hit[326]: begin
39067 1/1 reg_rdata_next[0] = dio_pad_attr_7_invert_7_qs;
Tests: T101 T96 T276
39068 1/1 reg_rdata_next[1] = dio_pad_attr_7_virtual_od_en_7_qs;
Tests: T101 T96 T276
39069 1/1 reg_rdata_next[2] = dio_pad_attr_7_pull_en_7_qs;
Tests: T101 T96 T276
39070 1/1 reg_rdata_next[3] = dio_pad_attr_7_pull_select_7_qs;
Tests: T101 T96 T276
39071 1/1 reg_rdata_next[4] = dio_pad_attr_7_keeper_en_7_qs;
Tests: T101 T96 T276
39072 1/1 reg_rdata_next[5] = dio_pad_attr_7_schmitt_en_7_qs;
Tests: T101 T96 T276
39073 1/1 reg_rdata_next[6] = dio_pad_attr_7_od_en_7_qs;
Tests: T101 T96 T276
39074 1/1 reg_rdata_next[7] = dio_pad_attr_7_input_disable_7_qs;
Tests: T101 T96 T276
39075 1/1 reg_rdata_next[17:16] = dio_pad_attr_7_slew_rate_7_qs;
Tests: T101 T96 T276
39076 1/1 reg_rdata_next[23:20] = dio_pad_attr_7_drive_strength_7_qs;
Tests: T101 T96 T276
39077 end
39078
39079 addr_hit[327]: begin
39080 1/1 reg_rdata_next[0] = dio_pad_attr_8_invert_8_qs;
Tests: T199 T58 T59
39081 1/1 reg_rdata_next[1] = dio_pad_attr_8_virtual_od_en_8_qs;
Tests: T199 T58 T59
39082 1/1 reg_rdata_next[2] = dio_pad_attr_8_pull_en_8_qs;
Tests: T199 T58 T59
39083 1/1 reg_rdata_next[3] = dio_pad_attr_8_pull_select_8_qs;
Tests: T199 T58 T59
39084 1/1 reg_rdata_next[4] = dio_pad_attr_8_keeper_en_8_qs;
Tests: T199 T58 T59
39085 1/1 reg_rdata_next[5] = dio_pad_attr_8_schmitt_en_8_qs;
Tests: T199 T58 T59
39086 1/1 reg_rdata_next[6] = dio_pad_attr_8_od_en_8_qs;
Tests: T199 T58 T59
39087 1/1 reg_rdata_next[7] = dio_pad_attr_8_input_disable_8_qs;
Tests: T199 T58 T59
39088 1/1 reg_rdata_next[17:16] = dio_pad_attr_8_slew_rate_8_qs;
Tests: T199 T58 T59
39089 1/1 reg_rdata_next[23:20] = dio_pad_attr_8_drive_strength_8_qs;
Tests: T199 T58 T59
39090 end
39091
39092 addr_hit[328]: begin
39093 1/1 reg_rdata_next[0] = dio_pad_attr_9_invert_9_qs;
Tests: T199 T58 T59
39094 1/1 reg_rdata_next[1] = dio_pad_attr_9_virtual_od_en_9_qs;
Tests: T199 T58 T59
39095 1/1 reg_rdata_next[2] = dio_pad_attr_9_pull_en_9_qs;
Tests: T199 T58 T59
39096 1/1 reg_rdata_next[3] = dio_pad_attr_9_pull_select_9_qs;
Tests: T199 T58 T59
39097 1/1 reg_rdata_next[4] = dio_pad_attr_9_keeper_en_9_qs;
Tests: T199 T58 T59
39098 1/1 reg_rdata_next[5] = dio_pad_attr_9_schmitt_en_9_qs;
Tests: T199 T58 T59
39099 1/1 reg_rdata_next[6] = dio_pad_attr_9_od_en_9_qs;
Tests: T199 T58 T59
39100 1/1 reg_rdata_next[7] = dio_pad_attr_9_input_disable_9_qs;
Tests: T199 T58 T59
39101 1/1 reg_rdata_next[17:16] = dio_pad_attr_9_slew_rate_9_qs;
Tests: T199 T58 T59
39102 1/1 reg_rdata_next[23:20] = dio_pad_attr_9_drive_strength_9_qs;
Tests: T199 T58 T59
39103 end
39104
39105 addr_hit[329]: begin
39106 1/1 reg_rdata_next[0] = dio_pad_attr_10_invert_10_qs;
Tests: T15 T199 T267
39107 1/1 reg_rdata_next[1] = dio_pad_attr_10_virtual_od_en_10_qs;
Tests: T15 T199 T267
39108 1/1 reg_rdata_next[2] = dio_pad_attr_10_pull_en_10_qs;
Tests: T15 T199 T267
39109 1/1 reg_rdata_next[3] = dio_pad_attr_10_pull_select_10_qs;
Tests: T15 T199 T267
39110 1/1 reg_rdata_next[4] = dio_pad_attr_10_keeper_en_10_qs;
Tests: T15 T199 T267
39111 1/1 reg_rdata_next[5] = dio_pad_attr_10_schmitt_en_10_qs;
Tests: T15 T199 T267
39112 1/1 reg_rdata_next[6] = dio_pad_attr_10_od_en_10_qs;
Tests: T15 T199 T267
39113 1/1 reg_rdata_next[7] = dio_pad_attr_10_input_disable_10_qs;
Tests: T15 T199 T267
39114 1/1 reg_rdata_next[17:16] = dio_pad_attr_10_slew_rate_10_qs;
Tests: T15 T199 T267
39115 1/1 reg_rdata_next[23:20] = dio_pad_attr_10_drive_strength_10_qs;
Tests: T15 T199 T267
39116 end
39117
39118 addr_hit[330]: begin
39119 1/1 reg_rdata_next[0] = dio_pad_attr_11_invert_11_qs;
Tests: T15 T199 T58
39120 1/1 reg_rdata_next[1] = dio_pad_attr_11_virtual_od_en_11_qs;
Tests: T15 T199 T58
39121 1/1 reg_rdata_next[2] = dio_pad_attr_11_pull_en_11_qs;
Tests: T15 T199 T58
39122 1/1 reg_rdata_next[3] = dio_pad_attr_11_pull_select_11_qs;
Tests: T15 T199 T58
39123 1/1 reg_rdata_next[4] = dio_pad_attr_11_keeper_en_11_qs;
Tests: T15 T199 T58
39124 1/1 reg_rdata_next[5] = dio_pad_attr_11_schmitt_en_11_qs;
Tests: T15 T199 T58
39125 1/1 reg_rdata_next[6] = dio_pad_attr_11_od_en_11_qs;
Tests: T15 T199 T58
39126 1/1 reg_rdata_next[7] = dio_pad_attr_11_input_disable_11_qs;
Tests: T15 T199 T58
39127 1/1 reg_rdata_next[17:16] = dio_pad_attr_11_slew_rate_11_qs;
Tests: T15 T199 T58
39128 1/1 reg_rdata_next[23:20] = dio_pad_attr_11_drive_strength_11_qs;
Tests: T15 T199 T58
39129 end
39130
39131 addr_hit[331]: begin
39132 1/1 reg_rdata_next[0] = dio_pad_attr_12_invert_12_qs;
Tests: T199 T58 T59
39133 1/1 reg_rdata_next[1] = dio_pad_attr_12_virtual_od_en_12_qs;
Tests: T199 T58 T59
39134 1/1 reg_rdata_next[2] = dio_pad_attr_12_pull_en_12_qs;
Tests: T199 T58 T59
39135 1/1 reg_rdata_next[3] = dio_pad_attr_12_pull_select_12_qs;
Tests: T199 T58 T59
39136 1/1 reg_rdata_next[4] = dio_pad_attr_12_keeper_en_12_qs;
Tests: T199 T58 T59
39137 1/1 reg_rdata_next[5] = dio_pad_attr_12_schmitt_en_12_qs;
Tests: T199 T58 T59
39138 1/1 reg_rdata_next[6] = dio_pad_attr_12_od_en_12_qs;
Tests: T199 T58 T59
39139 1/1 reg_rdata_next[7] = dio_pad_attr_12_input_disable_12_qs;
Tests: T199 T58 T59
39140 1/1 reg_rdata_next[17:16] = dio_pad_attr_12_slew_rate_12_qs;
Tests: T199 T58 T59
39141 1/1 reg_rdata_next[23:20] = dio_pad_attr_12_drive_strength_12_qs;
Tests: T199 T58 T59
39142 end
39143
39144 addr_hit[332]: begin
39145 1/1 reg_rdata_next[0] = dio_pad_attr_13_invert_13_qs;
Tests: T58 T59 T57
39146 1/1 reg_rdata_next[1] = dio_pad_attr_13_virtual_od_en_13_qs;
Tests: T58 T59 T57
39147 1/1 reg_rdata_next[2] = dio_pad_attr_13_pull_en_13_qs;
Tests: T58 T59 T57
39148 1/1 reg_rdata_next[3] = dio_pad_attr_13_pull_select_13_qs;
Tests: T58 T59 T57
39149 1/1 reg_rdata_next[4] = dio_pad_attr_13_keeper_en_13_qs;
Tests: T58 T59 T57
39150 1/1 reg_rdata_next[5] = dio_pad_attr_13_schmitt_en_13_qs;
Tests: T58 T59 T57
39151 1/1 reg_rdata_next[6] = dio_pad_attr_13_od_en_13_qs;
Tests: T58 T59 T57
39152 1/1 reg_rdata_next[7] = dio_pad_attr_13_input_disable_13_qs;
Tests: T58 T59 T57
39153 1/1 reg_rdata_next[17:16] = dio_pad_attr_13_slew_rate_13_qs;
Tests: T58 T59 T57
39154 1/1 reg_rdata_next[23:20] = dio_pad_attr_13_drive_strength_13_qs;
Tests: T58 T59 T57
39155 end
39156
39157 addr_hit[333]: begin
39158 1/1 reg_rdata_next[0] = dio_pad_attr_14_invert_14_qs;
Tests: T9 T58 T59
39159 1/1 reg_rdata_next[1] = dio_pad_attr_14_virtual_od_en_14_qs;
Tests: T9 T58 T59
39160 1/1 reg_rdata_next[2] = dio_pad_attr_14_pull_en_14_qs;
Tests: T9 T58 T59
39161 1/1 reg_rdata_next[3] = dio_pad_attr_14_pull_select_14_qs;
Tests: T9 T58 T59
39162 1/1 reg_rdata_next[4] = dio_pad_attr_14_keeper_en_14_qs;
Tests: T9 T58 T59
39163 1/1 reg_rdata_next[5] = dio_pad_attr_14_schmitt_en_14_qs;
Tests: T9 T58 T59
39164 1/1 reg_rdata_next[6] = dio_pad_attr_14_od_en_14_qs;
Tests: T9 T58 T59
39165 1/1 reg_rdata_next[7] = dio_pad_attr_14_input_disable_14_qs;
Tests: T9 T58 T59
39166 1/1 reg_rdata_next[17:16] = dio_pad_attr_14_slew_rate_14_qs;
Tests: T9 T58 T59
39167 1/1 reg_rdata_next[23:20] = dio_pad_attr_14_drive_strength_14_qs;
Tests: T9 T58 T59
39168 end
39169
39170 addr_hit[334]: begin
39171 1/1 reg_rdata_next[0] = dio_pad_attr_15_invert_15_qs;
Tests: T9 T47 T101
39172 1/1 reg_rdata_next[1] = dio_pad_attr_15_virtual_od_en_15_qs;
Tests: T9 T47 T101
39173 1/1 reg_rdata_next[2] = dio_pad_attr_15_pull_en_15_qs;
Tests: T9 T47 T101
39174 1/1 reg_rdata_next[3] = dio_pad_attr_15_pull_select_15_qs;
Tests: T9 T47 T101
39175 1/1 reg_rdata_next[4] = dio_pad_attr_15_keeper_en_15_qs;
Tests: T9 T47 T101
39176 1/1 reg_rdata_next[5] = dio_pad_attr_15_schmitt_en_15_qs;
Tests: T9 T47 T101
39177 1/1 reg_rdata_next[6] = dio_pad_attr_15_od_en_15_qs;
Tests: T9 T47 T101
39178 1/1 reg_rdata_next[7] = dio_pad_attr_15_input_disable_15_qs;
Tests: T9 T47 T101
39179 1/1 reg_rdata_next[17:16] = dio_pad_attr_15_slew_rate_15_qs;
Tests: T9 T47 T101
39180 1/1 reg_rdata_next[23:20] = dio_pad_attr_15_drive_strength_15_qs;
Tests: T9 T47 T101
39181 end
39182
39183 addr_hit[335]: begin
39184 1/1 reg_rdata_next[0] = mio_pad_sleep_status_0_en_0_qs;
Tests: T6 T25 T76
39185 1/1 reg_rdata_next[1] = mio_pad_sleep_status_0_en_1_qs;
Tests: T6 T25 T76
39186 1/1 reg_rdata_next[2] = mio_pad_sleep_status_0_en_2_qs;
Tests: T6 T25 T76
39187 1/1 reg_rdata_next[3] = mio_pad_sleep_status_0_en_3_qs;
Tests: T6 T25 T76
39188 1/1 reg_rdata_next[4] = mio_pad_sleep_status_0_en_4_qs;
Tests: T6 T25 T76
39189 1/1 reg_rdata_next[5] = mio_pad_sleep_status_0_en_5_qs;
Tests: T6 T25 T76
39190 1/1 reg_rdata_next[6] = mio_pad_sleep_status_0_en_6_qs;
Tests: T6 T25 T76
39191 1/1 reg_rdata_next[7] = mio_pad_sleep_status_0_en_7_qs;
Tests: T6 T25 T76
39192 1/1 reg_rdata_next[8] = mio_pad_sleep_status_0_en_8_qs;
Tests: T6 T25 T76
39193 1/1 reg_rdata_next[9] = mio_pad_sleep_status_0_en_9_qs;
Tests: T6 T25 T76
39194 1/1 reg_rdata_next[10] = mio_pad_sleep_status_0_en_10_qs;
Tests: T6 T25 T76
39195 1/1 reg_rdata_next[11] = mio_pad_sleep_status_0_en_11_qs;
Tests: T6 T25 T76
39196 1/1 reg_rdata_next[12] = mio_pad_sleep_status_0_en_12_qs;
Tests: T6 T25 T76
39197 1/1 reg_rdata_next[13] = mio_pad_sleep_status_0_en_13_qs;
Tests: T6 T25 T76
39198 1/1 reg_rdata_next[14] = mio_pad_sleep_status_0_en_14_qs;
Tests: T6 T25 T76
39199 1/1 reg_rdata_next[15] = mio_pad_sleep_status_0_en_15_qs;
Tests: T6 T25 T76
39200 1/1 reg_rdata_next[16] = mio_pad_sleep_status_0_en_16_qs;
Tests: T6 T25 T76
39201 1/1 reg_rdata_next[17] = mio_pad_sleep_status_0_en_17_qs;
Tests: T6 T25 T76
39202 1/1 reg_rdata_next[18] = mio_pad_sleep_status_0_en_18_qs;
Tests: T6 T25 T76
39203 1/1 reg_rdata_next[19] = mio_pad_sleep_status_0_en_19_qs;
Tests: T6 T25 T76
39204 1/1 reg_rdata_next[20] = mio_pad_sleep_status_0_en_20_qs;
Tests: T6 T25 T76
39205 1/1 reg_rdata_next[21] = mio_pad_sleep_status_0_en_21_qs;
Tests: T6 T25 T76
39206 1/1 reg_rdata_next[22] = mio_pad_sleep_status_0_en_22_qs;
Tests: T6 T25 T76
39207 1/1 reg_rdata_next[23] = mio_pad_sleep_status_0_en_23_qs;
Tests: T6 T25 T76
39208 1/1 reg_rdata_next[24] = mio_pad_sleep_status_0_en_24_qs;
Tests: T6 T25 T76
39209 1/1 reg_rdata_next[25] = mio_pad_sleep_status_0_en_25_qs;
Tests: T6 T25 T76
39210 1/1 reg_rdata_next[26] = mio_pad_sleep_status_0_en_26_qs;
Tests: T6 T25 T76
39211 1/1 reg_rdata_next[27] = mio_pad_sleep_status_0_en_27_qs;
Tests: T6 T25 T76
39212 1/1 reg_rdata_next[28] = mio_pad_sleep_status_0_en_28_qs;
Tests: T6 T25 T76
39213 1/1 reg_rdata_next[29] = mio_pad_sleep_status_0_en_29_qs;
Tests: T6 T25 T76
39214 1/1 reg_rdata_next[30] = mio_pad_sleep_status_0_en_30_qs;
Tests: T6 T25 T76
39215 1/1 reg_rdata_next[31] = mio_pad_sleep_status_0_en_31_qs;
Tests: T6 T25 T76
39216 end
39217
39218 addr_hit[336]: begin
39219 1/1 reg_rdata_next[0] = mio_pad_sleep_status_1_en_32_qs;
Tests: T45 T199 T58
39220 1/1 reg_rdata_next[1] = mio_pad_sleep_status_1_en_33_qs;
Tests: T45 T199 T58
39221 1/1 reg_rdata_next[2] = mio_pad_sleep_status_1_en_34_qs;
Tests: T45 T199 T58
39222 1/1 reg_rdata_next[3] = mio_pad_sleep_status_1_en_35_qs;
Tests: T45 T199 T58
39223 1/1 reg_rdata_next[4] = mio_pad_sleep_status_1_en_36_qs;
Tests: T45 T199 T58
39224 1/1 reg_rdata_next[5] = mio_pad_sleep_status_1_en_37_qs;
Tests: T45 T199 T58
39225 1/1 reg_rdata_next[6] = mio_pad_sleep_status_1_en_38_qs;
Tests: T45 T199 T58
39226 1/1 reg_rdata_next[7] = mio_pad_sleep_status_1_en_39_qs;
Tests: T45 T199 T58
39227 1/1 reg_rdata_next[8] = mio_pad_sleep_status_1_en_40_qs;
Tests: T45 T199 T58
39228 1/1 reg_rdata_next[9] = mio_pad_sleep_status_1_en_41_qs;
Tests: T45 T199 T58
39229 1/1 reg_rdata_next[10] = mio_pad_sleep_status_1_en_42_qs;
Tests: T45 T199 T58
39230 1/1 reg_rdata_next[11] = mio_pad_sleep_status_1_en_43_qs;
Tests: T45 T199 T58
39231 1/1 reg_rdata_next[12] = mio_pad_sleep_status_1_en_44_qs;
Tests: T45 T199 T58
39232 1/1 reg_rdata_next[13] = mio_pad_sleep_status_1_en_45_qs;
Tests: T45 T199 T58
39233 1/1 reg_rdata_next[14] = mio_pad_sleep_status_1_en_46_qs;
Tests: T45 T199 T58
39234 end
39235
39236 addr_hit[337]: begin
39237 1/1 reg_rdata_next[0] = mio_pad_sleep_regwen_0_qs;
Tests: T2 T25 T45
39238 end
39239
39240 addr_hit[338]: begin
39241 1/1 reg_rdata_next[0] = mio_pad_sleep_regwen_1_qs;
Tests: T2 T25 T19
39242 end
39243
39244 addr_hit[339]: begin
39245 1/1 reg_rdata_next[0] = mio_pad_sleep_regwen_2_qs;
Tests: T2 T25 T19
39246 end
39247
39248 addr_hit[340]: begin
39249 1/1 reg_rdata_next[0] = mio_pad_sleep_regwen_3_qs;
Tests: T2 T25 T19
39250 end
39251
39252 addr_hit[341]: begin
39253 1/1 reg_rdata_next[0] = mio_pad_sleep_regwen_4_qs;
Tests: T2 T25 T45
39254 end
39255
39256 addr_hit[342]: begin
39257 1/1 reg_rdata_next[0] = mio_pad_sleep_regwen_5_qs;
Tests: T2 T25 T45
39258 end
39259
39260 addr_hit[343]: begin
39261 1/1 reg_rdata_next[0] = mio_pad_sleep_regwen_6_qs;
Tests: T2 T25 T45
39262 end
39263
39264 addr_hit[344]: begin
39265 1/1 reg_rdata_next[0] = mio_pad_sleep_regwen_7_qs;
Tests: T2 T6 T25
39266 end
39267
39268 addr_hit[345]: begin
39269 1/1 reg_rdata_next[0] = mio_pad_sleep_regwen_8_qs;
Tests: T2 T45 T199
39270 end
39271
39272 addr_hit[346]: begin
39273 1/1 reg_rdata_next[0] = mio_pad_sleep_regwen_9_qs;
Tests: T2 T45 T199
39274 end
39275
39276 addr_hit[347]: begin
39277 1/1 reg_rdata_next[0] = mio_pad_sleep_regwen_10_qs;
Tests: T2 T45 T58
39278 end
39279
39280 addr_hit[348]: begin
39281 1/1 reg_rdata_next[0] = mio_pad_sleep_regwen_11_qs;
Tests: T2 T19 T40
39282 end
39283
39284 addr_hit[349]: begin
39285 1/1 reg_rdata_next[0] = mio_pad_sleep_regwen_12_qs;
Tests: T2 T45 T19
39286 end
39287
39288 addr_hit[350]: begin
39289 1/1 reg_rdata_next[0] = mio_pad_sleep_regwen_13_qs;
Tests: T2 T19 T40
39290 end
39291
39292 addr_hit[351]: begin
39293 1/1 reg_rdata_next[0] = mio_pad_sleep_regwen_14_qs;
Tests: T2 T19 T40
39294 end
39295
39296 addr_hit[352]: begin
39297 1/1 reg_rdata_next[0] = mio_pad_sleep_regwen_15_qs;
Tests: T2 T19 T40
39298 end
39299
39300 addr_hit[353]: begin
39301 1/1 reg_rdata_next[0] = mio_pad_sleep_regwen_16_qs;
Tests: T2 T19 T40
39302 end
39303
39304 addr_hit[354]: begin
39305 1/1 reg_rdata_next[0] = mio_pad_sleep_regwen_17_qs;
Tests: T2 T19 T40
39306 end
39307
39308 addr_hit[355]: begin
39309 1/1 reg_rdata_next[0] = mio_pad_sleep_regwen_18_qs;
Tests: T2 T19 T40
39310 end
39311
39312 addr_hit[356]: begin
39313 1/1 reg_rdata_next[0] = mio_pad_sleep_regwen_19_qs;
Tests: T2 T19 T40
39314 end
39315
39316 addr_hit[357]: begin
39317 1/1 reg_rdata_next[0] = mio_pad_sleep_regwen_20_qs;
Tests: T2 T19 T40
39318 end
39319
39320 addr_hit[358]: begin
39321 1/1 reg_rdata_next[0] = mio_pad_sleep_regwen_21_qs;
Tests: T2 T19 T40
39322 end
39323
39324 addr_hit[359]: begin
39325 1/1 reg_rdata_next[0] = mio_pad_sleep_regwen_22_qs;
Tests: T2 T19 T40
39326 end
39327
39328 addr_hit[360]: begin
39329 1/1 reg_rdata_next[0] = mio_pad_sleep_regwen_23_qs;
Tests: T2 T19 T40
39330 end
39331
39332 addr_hit[361]: begin
39333 1/1 reg_rdata_next[0] = mio_pad_sleep_regwen_24_qs;
Tests: T2 T19 T40
39334 end
39335
39336 addr_hit[362]: begin
39337 1/1 reg_rdata_next[0] = mio_pad_sleep_regwen_25_qs;
Tests: T2 T19 T40
39338 end
39339
39340 addr_hit[363]: begin
39341 1/1 reg_rdata_next[0] = mio_pad_sleep_regwen_26_qs;
Tests: T2 T19 T40
39342 end
39343
39344 addr_hit[364]: begin
39345 1/1 reg_rdata_next[0] = mio_pad_sleep_regwen_27_qs;
Tests: T2 T19 T40
39346 end
39347
39348 addr_hit[365]: begin
39349 1/1 reg_rdata_next[0] = mio_pad_sleep_regwen_28_qs;
Tests: T2 T19 T40
39350 end
39351
39352 addr_hit[366]: begin
39353 1/1 reg_rdata_next[0] = mio_pad_sleep_regwen_29_qs;
Tests: T2 T19 T40
39354 end
39355
39356 addr_hit[367]: begin
39357 1/1 reg_rdata_next[0] = mio_pad_sleep_regwen_30_qs;
Tests: T2 T19 T40
39358 end
39359
39360 addr_hit[368]: begin
39361 1/1 reg_rdata_next[0] = mio_pad_sleep_regwen_31_qs;
Tests: T2 T19 T40
39362 end
39363
39364 addr_hit[369]: begin
39365 1/1 reg_rdata_next[0] = mio_pad_sleep_regwen_32_qs;
Tests: T2 T19 T40
39366 end
39367
39368 addr_hit[370]: begin
39369 1/1 reg_rdata_next[0] = mio_pad_sleep_regwen_33_qs;
Tests: T2 T19 T40
39370 end
39371
39372 addr_hit[371]: begin
39373 1/1 reg_rdata_next[0] = mio_pad_sleep_regwen_34_qs;
Tests: T2 T19 T40
39374 end
39375
39376 addr_hit[372]: begin
39377 1/1 reg_rdata_next[0] = mio_pad_sleep_regwen_35_qs;
Tests: T2 T19 T40
39378 end
39379
39380 addr_hit[373]: begin
39381 1/1 reg_rdata_next[0] = mio_pad_sleep_regwen_36_qs;
Tests: T2 T19 T40
39382 end
39383
39384 addr_hit[374]: begin
39385 1/1 reg_rdata_next[0] = mio_pad_sleep_regwen_37_qs;
Tests: T2 T19 T40
39386 end
39387
39388 addr_hit[375]: begin
39389 1/1 reg_rdata_next[0] = mio_pad_sleep_regwen_38_qs;
Tests: T2 T19 T40
39390 end
39391
39392 addr_hit[376]: begin
39393 1/1 reg_rdata_next[0] = mio_pad_sleep_regwen_39_qs;
Tests: T2 T19 T40
39394 end
39395
39396 addr_hit[377]: begin
39397 1/1 reg_rdata_next[0] = mio_pad_sleep_regwen_40_qs;
Tests: T2 T19 T40
39398 end
39399
39400 addr_hit[378]: begin
39401 1/1 reg_rdata_next[0] = mio_pad_sleep_regwen_41_qs;
Tests: T2 T19 T40
39402 end
39403
39404 addr_hit[379]: begin
39405 1/1 reg_rdata_next[0] = mio_pad_sleep_regwen_42_qs;
Tests: T2 T19 T40
39406 end
39407
39408 addr_hit[380]: begin
39409 1/1 reg_rdata_next[0] = mio_pad_sleep_regwen_43_qs;
Tests: T2 T19 T40
39410 end
39411
39412 addr_hit[381]: begin
39413 1/1 reg_rdata_next[0] = mio_pad_sleep_regwen_44_qs;
Tests: T2 T19 T40
39414 end
39415
39416 addr_hit[382]: begin
39417 1/1 reg_rdata_next[0] = mio_pad_sleep_regwen_45_qs;
Tests: T2 T19 T40
39418 end
39419
39420 addr_hit[383]: begin
39421 1/1 reg_rdata_next[0] = mio_pad_sleep_regwen_46_qs;
Tests: T2 T19 T40
39422 end
39423
39424 addr_hit[384]: begin
39425 1/1 reg_rdata_next[0] = mio_pad_sleep_en_0_qs;
Tests: T2 T25 T19
39426 end
39427
39428 addr_hit[385]: begin
39429 1/1 reg_rdata_next[0] = mio_pad_sleep_en_1_qs;
Tests: T2 T25 T19
39430 end
39431
39432 addr_hit[386]: begin
39433 1/1 reg_rdata_next[0] = mio_pad_sleep_en_2_qs;
Tests: T2 T25 T19
39434 end
39435
39436 addr_hit[387]: begin
39437 1/1 reg_rdata_next[0] = mio_pad_sleep_en_3_qs;
Tests: T2 T25 T19
39438 end
39439
39440 addr_hit[388]: begin
39441 1/1 reg_rdata_next[0] = mio_pad_sleep_en_4_qs;
Tests: T2 T25 T19
39442 end
39443
39444 addr_hit[389]: begin
39445 1/1 reg_rdata_next[0] = mio_pad_sleep_en_5_qs;
Tests: T2 T25 T19
39446 end
39447
39448 addr_hit[390]: begin
39449 1/1 reg_rdata_next[0] = mio_pad_sleep_en_6_qs;
Tests: T2 T25 T19
39450 end
39451
39452 addr_hit[391]: begin
39453 1/1 reg_rdata_next[0] = mio_pad_sleep_en_7_qs;
Tests: T2 T6 T25
39454 end
39455
39456 addr_hit[392]: begin
39457 1/1 reg_rdata_next[0] = mio_pad_sleep_en_8_qs;
Tests: T2 T19 T40
39458 end
39459
39460 addr_hit[393]: begin
39461 1/1 reg_rdata_next[0] = mio_pad_sleep_en_9_qs;
Tests: T2 T19 T40
39462 end
39463
39464 addr_hit[394]: begin
39465 1/1 reg_rdata_next[0] = mio_pad_sleep_en_10_qs;
Tests: T2 T19 T40
39466 end
39467
39468 addr_hit[395]: begin
39469 1/1 reg_rdata_next[0] = mio_pad_sleep_en_11_qs;
Tests: T2 T19 T40
39470 end
39471
39472 addr_hit[396]: begin
39473 1/1 reg_rdata_next[0] = mio_pad_sleep_en_12_qs;
Tests: T2 T19 T40
39474 end
39475
39476 addr_hit[397]: begin
39477 1/1 reg_rdata_next[0] = mio_pad_sleep_en_13_qs;
Tests: T2 T19 T40
39478 end
39479
39480 addr_hit[398]: begin
39481 1/1 reg_rdata_next[0] = mio_pad_sleep_en_14_qs;
Tests: T2 T19 T40
39482 end
39483
39484 addr_hit[399]: begin
39485 1/1 reg_rdata_next[0] = mio_pad_sleep_en_15_qs;
Tests: T2 T19 T40
39486 end
39487
39488 addr_hit[400]: begin
39489 1/1 reg_rdata_next[0] = mio_pad_sleep_en_16_qs;
Tests: T2 T19 T40
39490 end
39491
39492 addr_hit[401]: begin
39493 1/1 reg_rdata_next[0] = mio_pad_sleep_en_17_qs;
Tests: T2 T19 T40
39494 end
39495
39496 addr_hit[402]: begin
39497 1/1 reg_rdata_next[0] = mio_pad_sleep_en_18_qs;
Tests: T2 T19 T40
39498 end
39499
39500 addr_hit[403]: begin
39501 1/1 reg_rdata_next[0] = mio_pad_sleep_en_19_qs;
Tests: T2 T19 T40
39502 end
39503
39504 addr_hit[404]: begin
39505 1/1 reg_rdata_next[0] = mio_pad_sleep_en_20_qs;
Tests: T2 T19 T40
39506 end
39507
39508 addr_hit[405]: begin
39509 1/1 reg_rdata_next[0] = mio_pad_sleep_en_21_qs;
Tests: T2 T19 T40
39510 end
39511
39512 addr_hit[406]: begin
39513 1/1 reg_rdata_next[0] = mio_pad_sleep_en_22_qs;
Tests: T2 T19 T40
39514 end
39515
39516 addr_hit[407]: begin
39517 1/1 reg_rdata_next[0] = mio_pad_sleep_en_23_qs;
Tests: T2 T19 T40
39518 end
39519
39520 addr_hit[408]: begin
39521 1/1 reg_rdata_next[0] = mio_pad_sleep_en_24_qs;
Tests: T2 T19 T40
39522 end
39523
39524 addr_hit[409]: begin
39525 1/1 reg_rdata_next[0] = mio_pad_sleep_en_25_qs;
Tests: T2 T19 T40
39526 end
39527
39528 addr_hit[410]: begin
39529 1/1 reg_rdata_next[0] = mio_pad_sleep_en_26_qs;
Tests: T2 T19 T40
39530 end
39531
39532 addr_hit[411]: begin
39533 1/1 reg_rdata_next[0] = mio_pad_sleep_en_27_qs;
Tests: T2 T19 T40
39534 end
39535
39536 addr_hit[412]: begin
39537 1/1 reg_rdata_next[0] = mio_pad_sleep_en_28_qs;
Tests: T2 T19 T40
39538 end
39539
39540 addr_hit[413]: begin
39541 1/1 reg_rdata_next[0] = mio_pad_sleep_en_29_qs;
Tests: T2 T19 T40
39542 end
39543
39544 addr_hit[414]: begin
39545 1/1 reg_rdata_next[0] = mio_pad_sleep_en_30_qs;
Tests: T2 T19 T40
39546 end
39547
39548 addr_hit[415]: begin
39549 1/1 reg_rdata_next[0] = mio_pad_sleep_en_31_qs;
Tests: T2 T19 T40
39550 end
39551
39552 addr_hit[416]: begin
39553 1/1 reg_rdata_next[0] = mio_pad_sleep_en_32_qs;
Tests: T2 T19 T40
39554 end
39555
39556 addr_hit[417]: begin
39557 1/1 reg_rdata_next[0] = mio_pad_sleep_en_33_qs;
Tests: T2 T19 T40
39558 end
39559
39560 addr_hit[418]: begin
39561 1/1 reg_rdata_next[0] = mio_pad_sleep_en_34_qs;
Tests: T2 T19 T40
39562 end
39563
39564 addr_hit[419]: begin
39565 1/1 reg_rdata_next[0] = mio_pad_sleep_en_35_qs;
Tests: T2 T19 T40
39566 end
39567
39568 addr_hit[420]: begin
39569 1/1 reg_rdata_next[0] = mio_pad_sleep_en_36_qs;
Tests: T2 T19 T40
39570 end
39571
39572 addr_hit[421]: begin
39573 1/1 reg_rdata_next[0] = mio_pad_sleep_en_37_qs;
Tests: T2 T19 T40
39574 end
39575
39576 addr_hit[422]: begin
39577 1/1 reg_rdata_next[0] = mio_pad_sleep_en_38_qs;
Tests: T2 T19 T40
39578 end
39579
39580 addr_hit[423]: begin
39581 1/1 reg_rdata_next[0] = mio_pad_sleep_en_39_qs;
Tests: T2 T19 T40
39582 end
39583
39584 addr_hit[424]: begin
39585 1/1 reg_rdata_next[0] = mio_pad_sleep_en_40_qs;
Tests: T2 T19 T40
39586 end
39587
39588 addr_hit[425]: begin
39589 1/1 reg_rdata_next[0] = mio_pad_sleep_en_41_qs;
Tests: T2 T19 T40
39590 end
39591
39592 addr_hit[426]: begin
39593 1/1 reg_rdata_next[0] = mio_pad_sleep_en_42_qs;
Tests: T2 T19 T40
39594 end
39595
39596 addr_hit[427]: begin
39597 1/1 reg_rdata_next[0] = mio_pad_sleep_en_43_qs;
Tests: T2 T19 T40
39598 end
39599
39600 addr_hit[428]: begin
39601 1/1 reg_rdata_next[0] = mio_pad_sleep_en_44_qs;
Tests: T2 T19 T40
39602 end
39603
39604 addr_hit[429]: begin
39605 1/1 reg_rdata_next[0] = mio_pad_sleep_en_45_qs;
Tests: T2 T19 T40
39606 end
39607
39608 addr_hit[430]: begin
39609 1/1 reg_rdata_next[0] = mio_pad_sleep_en_46_qs;
Tests: T2 T19 T40
39610 end
39611
39612 addr_hit[431]: begin
39613 1/1 reg_rdata_next[1:0] = mio_pad_sleep_mode_0_qs;
Tests: T2 T25 T19
39614 end
39615
39616 addr_hit[432]: begin
39617 1/1 reg_rdata_next[1:0] = mio_pad_sleep_mode_1_qs;
Tests: T2 T25 T19
39618 end
39619
39620 addr_hit[433]: begin
39621 1/1 reg_rdata_next[1:0] = mio_pad_sleep_mode_2_qs;
Tests: T2 T25 T19
39622 end
39623
39624 addr_hit[434]: begin
39625 1/1 reg_rdata_next[1:0] = mio_pad_sleep_mode_3_qs;
Tests: T2 T25 T19
39626 end
39627
39628 addr_hit[435]: begin
39629 1/1 reg_rdata_next[1:0] = mio_pad_sleep_mode_4_qs;
Tests: T2 T25 T19
39630 end
39631
39632 addr_hit[436]: begin
39633 1/1 reg_rdata_next[1:0] = mio_pad_sleep_mode_5_qs;
Tests: T2 T25 T19
39634 end
39635
39636 addr_hit[437]: begin
39637 1/1 reg_rdata_next[1:0] = mio_pad_sleep_mode_6_qs;
Tests: T2 T25 T19
39638 end
39639
39640 addr_hit[438]: begin
39641 1/1 reg_rdata_next[1:0] = mio_pad_sleep_mode_7_qs;
Tests: T2 T6 T25
39642 end
39643
39644 addr_hit[439]: begin
39645 1/1 reg_rdata_next[1:0] = mio_pad_sleep_mode_8_qs;
Tests: T2 T19 T40
39646 end
39647
39648 addr_hit[440]: begin
39649 1/1 reg_rdata_next[1:0] = mio_pad_sleep_mode_9_qs;
Tests: T2 T19 T40
39650 end
39651
39652 addr_hit[441]: begin
39653 1/1 reg_rdata_next[1:0] = mio_pad_sleep_mode_10_qs;
Tests: T2 T19 T40
39654 end
39655
39656 addr_hit[442]: begin
39657 1/1 reg_rdata_next[1:0] = mio_pad_sleep_mode_11_qs;
Tests: T2 T19 T40
39658 end
39659
39660 addr_hit[443]: begin
39661 1/1 reg_rdata_next[1:0] = mio_pad_sleep_mode_12_qs;
Tests: T2 T19 T40
39662 end
39663
39664 addr_hit[444]: begin
39665 1/1 reg_rdata_next[1:0] = mio_pad_sleep_mode_13_qs;
Tests: T2 T19 T40
39666 end
39667
39668 addr_hit[445]: begin
39669 1/1 reg_rdata_next[1:0] = mio_pad_sleep_mode_14_qs;
Tests: T2 T19 T40
39670 end
39671
39672 addr_hit[446]: begin
39673 1/1 reg_rdata_next[1:0] = mio_pad_sleep_mode_15_qs;
Tests: T2 T19 T40
39674 end
39675
39676 addr_hit[447]: begin
39677 1/1 reg_rdata_next[1:0] = mio_pad_sleep_mode_16_qs;
Tests: T2 T19 T40
39678 end
39679
39680 addr_hit[448]: begin
39681 1/1 reg_rdata_next[1:0] = mio_pad_sleep_mode_17_qs;
Tests: T2 T19 T40
39682 end
39683
39684 addr_hit[449]: begin
39685 1/1 reg_rdata_next[1:0] = mio_pad_sleep_mode_18_qs;
Tests: T2 T19 T40
39686 end
39687
39688 addr_hit[450]: begin
39689 1/1 reg_rdata_next[1:0] = mio_pad_sleep_mode_19_qs;
Tests: T2 T19 T40
39690 end
39691
39692 addr_hit[451]: begin
39693 1/1 reg_rdata_next[1:0] = mio_pad_sleep_mode_20_qs;
Tests: T2 T19 T40
39694 end
39695
39696 addr_hit[452]: begin
39697 1/1 reg_rdata_next[1:0] = mio_pad_sleep_mode_21_qs;
Tests: T2 T19 T40
39698 end
39699
39700 addr_hit[453]: begin
39701 1/1 reg_rdata_next[1:0] = mio_pad_sleep_mode_22_qs;
Tests: T2 T19 T40
39702 end
39703
39704 addr_hit[454]: begin
39705 1/1 reg_rdata_next[1:0] = mio_pad_sleep_mode_23_qs;
Tests: T2 T19 T40
39706 end
39707
39708 addr_hit[455]: begin
39709 1/1 reg_rdata_next[1:0] = mio_pad_sleep_mode_24_qs;
Tests: T2 T19 T40
39710 end
39711
39712 addr_hit[456]: begin
39713 1/1 reg_rdata_next[1:0] = mio_pad_sleep_mode_25_qs;
Tests: T2 T19 T40
39714 end
39715
39716 addr_hit[457]: begin
39717 1/1 reg_rdata_next[1:0] = mio_pad_sleep_mode_26_qs;
Tests: T2 T19 T40
39718 end
39719
39720 addr_hit[458]: begin
39721 1/1 reg_rdata_next[1:0] = mio_pad_sleep_mode_27_qs;
Tests: T2 T19 T40
39722 end
39723
39724 addr_hit[459]: begin
39725 1/1 reg_rdata_next[1:0] = mio_pad_sleep_mode_28_qs;
Tests: T2 T19 T40
39726 end
39727
39728 addr_hit[460]: begin
39729 1/1 reg_rdata_next[1:0] = mio_pad_sleep_mode_29_qs;
Tests: T2 T19 T40
39730 end
39731
39732 addr_hit[461]: begin
39733 1/1 reg_rdata_next[1:0] = mio_pad_sleep_mode_30_qs;
Tests: T2 T19 T40
39734 end
39735
39736 addr_hit[462]: begin
39737 1/1 reg_rdata_next[1:0] = mio_pad_sleep_mode_31_qs;
Tests: T2 T19 T40
39738 end
39739
39740 addr_hit[463]: begin
39741 1/1 reg_rdata_next[1:0] = mio_pad_sleep_mode_32_qs;
Tests: T2 T19 T40
39742 end
39743
39744 addr_hit[464]: begin
39745 1/1 reg_rdata_next[1:0] = mio_pad_sleep_mode_33_qs;
Tests: T2 T19 T40
39746 end
39747
39748 addr_hit[465]: begin
39749 1/1 reg_rdata_next[1:0] = mio_pad_sleep_mode_34_qs;
Tests: T2 T19 T40
39750 end
39751
39752 addr_hit[466]: begin
39753 1/1 reg_rdata_next[1:0] = mio_pad_sleep_mode_35_qs;
Tests: T2 T19 T40
39754 end
39755
39756 addr_hit[467]: begin
39757 1/1 reg_rdata_next[1:0] = mio_pad_sleep_mode_36_qs;
Tests: T2 T19 T40
39758 end
39759
39760 addr_hit[468]: begin
39761 1/1 reg_rdata_next[1:0] = mio_pad_sleep_mode_37_qs;
Tests: T2 T19 T40
39762 end
39763
39764 addr_hit[469]: begin
39765 1/1 reg_rdata_next[1:0] = mio_pad_sleep_mode_38_qs;
Tests: T2 T19 T40
39766 end
39767
39768 addr_hit[470]: begin
39769 1/1 reg_rdata_next[1:0] = mio_pad_sleep_mode_39_qs;
Tests: T2 T19 T40
39770 end
39771
39772 addr_hit[471]: begin
39773 1/1 reg_rdata_next[1:0] = mio_pad_sleep_mode_40_qs;
Tests: T2 T19 T40
39774 end
39775
39776 addr_hit[472]: begin
39777 1/1 reg_rdata_next[1:0] = mio_pad_sleep_mode_41_qs;
Tests: T2 T19 T40
39778 end
39779
39780 addr_hit[473]: begin
39781 1/1 reg_rdata_next[1:0] = mio_pad_sleep_mode_42_qs;
Tests: T2 T19 T40
39782 end
39783
39784 addr_hit[474]: begin
39785 1/1 reg_rdata_next[1:0] = mio_pad_sleep_mode_43_qs;
Tests: T2 T19 T40
39786 end
39787
39788 addr_hit[475]: begin
39789 1/1 reg_rdata_next[1:0] = mio_pad_sleep_mode_44_qs;
Tests: T2 T19 T40
39790 end
39791
39792 addr_hit[476]: begin
39793 1/1 reg_rdata_next[1:0] = mio_pad_sleep_mode_45_qs;
Tests: T2 T19 T40
39794 end
39795
39796 addr_hit[477]: begin
39797 1/1 reg_rdata_next[1:0] = mio_pad_sleep_mode_46_qs;
Tests: T2 T19 T40
39798 end
39799
39800 addr_hit[478]: begin
39801 1/1 reg_rdata_next[0] = dio_pad_sleep_status_en_0_qs;
Tests: T2 T3 T4
39802 1/1 reg_rdata_next[1] = dio_pad_sleep_status_en_1_qs;
Tests: T2 T3 T4
39803 1/1 reg_rdata_next[2] = dio_pad_sleep_status_en_2_qs;
Tests: T2 T3 T4
39804 1/1 reg_rdata_next[3] = dio_pad_sleep_status_en_3_qs;
Tests: T2 T3 T4
39805 1/1 reg_rdata_next[4] = dio_pad_sleep_status_en_4_qs;
Tests: T2 T3 T4
39806 1/1 reg_rdata_next[5] = dio_pad_sleep_status_en_5_qs;
Tests: T2 T3 T4
39807 1/1 reg_rdata_next[6] = dio_pad_sleep_status_en_6_qs;
Tests: T2 T3 T4
39808 1/1 reg_rdata_next[7] = dio_pad_sleep_status_en_7_qs;
Tests: T2 T3 T4
39809 1/1 reg_rdata_next[8] = dio_pad_sleep_status_en_8_qs;
Tests: T2 T3 T4
39810 1/1 reg_rdata_next[9] = dio_pad_sleep_status_en_9_qs;
Tests: T2 T3 T4
39811 1/1 reg_rdata_next[10] = dio_pad_sleep_status_en_10_qs;
Tests: T2 T3 T4
39812 1/1 reg_rdata_next[11] = dio_pad_sleep_status_en_11_qs;
Tests: T2 T3 T4
39813 1/1 reg_rdata_next[12] = dio_pad_sleep_status_en_12_qs;
Tests: T2 T3 T4
39814 1/1 reg_rdata_next[13] = dio_pad_sleep_status_en_13_qs;
Tests: T2 T3 T4
39815 1/1 reg_rdata_next[14] = dio_pad_sleep_status_en_14_qs;
Tests: T2 T3 T4
39816 1/1 reg_rdata_next[15] = dio_pad_sleep_status_en_15_qs;
Tests: T2 T3 T4
39817 end
39818
39819 addr_hit[479]: begin
39820 1/1 reg_rdata_next[0] = dio_pad_sleep_regwen_0_qs;
Tests: T2 T58 T55
39821 end
39822
39823 addr_hit[480]: begin
39824 1/1 reg_rdata_next[0] = dio_pad_sleep_regwen_1_qs;
Tests: T2 T58 T55
39825 end
39826
39827 addr_hit[481]: begin
39828 1/1 reg_rdata_next[0] = dio_pad_sleep_regwen_2_qs;
Tests: T2 T58 T55
39829 end
39830
39831 addr_hit[482]: begin
39832 1/1 reg_rdata_next[0] = dio_pad_sleep_regwen_3_qs;
Tests: T2 T58 T55
39833 end
39834
39835 addr_hit[483]: begin
39836 1/1 reg_rdata_next[0] = dio_pad_sleep_regwen_4_qs;
Tests: T2 T58 T55
39837 end
39838
39839 addr_hit[484]: begin
39840 1/1 reg_rdata_next[0] = dio_pad_sleep_regwen_5_qs;
Tests: T2 T58 T55
39841 end
39842
39843 addr_hit[485]: begin
39844 1/1 reg_rdata_next[0] = dio_pad_sleep_regwen_6_qs;
Tests: T2 T6 T58
39845 end
39846
39847 addr_hit[486]: begin
39848 1/1 reg_rdata_next[0] = dio_pad_sleep_regwen_7_qs;
Tests: T2 T6 T58
39849 end
39850
39851 addr_hit[487]: begin
39852 1/1 reg_rdata_next[0] = dio_pad_sleep_regwen_8_qs;
Tests: T2 T6 T58
39853 end
39854
39855 addr_hit[488]: begin
39856 1/1 reg_rdata_next[0] = dio_pad_sleep_regwen_9_qs;
Tests: T2 T6 T58
39857 end
39858
39859 addr_hit[489]: begin
39860 1/1 reg_rdata_next[0] = dio_pad_sleep_regwen_10_qs;
Tests: T2 T58 T55
39861 end
39862
39863 addr_hit[490]: begin
39864 1/1 reg_rdata_next[0] = dio_pad_sleep_regwen_11_qs;
Tests: T2 T58 T55
39865 end
39866
39867 addr_hit[491]: begin
39868 1/1 reg_rdata_next[0] = dio_pad_sleep_regwen_12_qs;
Tests: T2 T58 T55
39869 end
39870
39871 addr_hit[492]: begin
39872 1/1 reg_rdata_next[0] = dio_pad_sleep_regwen_13_qs;
Tests: T2 T58 T55
39873 end
39874
39875 addr_hit[493]: begin
39876 1/1 reg_rdata_next[0] = dio_pad_sleep_regwen_14_qs;
Tests: T2 T58 T55
39877 end
39878
39879 addr_hit[494]: begin
39880 1/1 reg_rdata_next[0] = dio_pad_sleep_regwen_15_qs;
Tests: T2 T58 T55
39881 end
39882
39883 addr_hit[495]: begin
39884 1/1 reg_rdata_next[0] = dio_pad_sleep_en_0_qs;
Tests: T2 T58 T55
39885 end
39886
39887 addr_hit[496]: begin
39888 1/1 reg_rdata_next[0] = dio_pad_sleep_en_1_qs;
Tests: T2 T58 T55
39889 end
39890
39891 addr_hit[497]: begin
39892 1/1 reg_rdata_next[0] = dio_pad_sleep_en_2_qs;
Tests: T2 T58 T55
39893 end
39894
39895 addr_hit[498]: begin
39896 1/1 reg_rdata_next[0] = dio_pad_sleep_en_3_qs;
Tests: T2 T58 T55
39897 end
39898
39899 addr_hit[499]: begin
39900 1/1 reg_rdata_next[0] = dio_pad_sleep_en_4_qs;
Tests: T2 T58 T55
39901 end
39902
39903 addr_hit[500]: begin
39904 1/1 reg_rdata_next[0] = dio_pad_sleep_en_5_qs;
Tests: T2 T58 T55
39905 end
39906
39907 addr_hit[501]: begin
39908 1/1 reg_rdata_next[0] = dio_pad_sleep_en_6_qs;
Tests: T2 T6 T58
39909 end
39910
39911 addr_hit[502]: begin
39912 1/1 reg_rdata_next[0] = dio_pad_sleep_en_7_qs;
Tests: T2 T6 T58
39913 end
39914
39915 addr_hit[503]: begin
39916 1/1 reg_rdata_next[0] = dio_pad_sleep_en_8_qs;
Tests: T2 T6 T58
39917 end
39918
39919 addr_hit[504]: begin
39920 1/1 reg_rdata_next[0] = dio_pad_sleep_en_9_qs;
Tests: T2 T6 T58
39921 end
39922
39923 addr_hit[505]: begin
39924 1/1 reg_rdata_next[0] = dio_pad_sleep_en_10_qs;
Tests: T2 T58 T55
39925 end
39926
39927 addr_hit[506]: begin
39928 1/1 reg_rdata_next[0] = dio_pad_sleep_en_11_qs;
Tests: T2 T58 T55
39929 end
39930
39931 addr_hit[507]: begin
39932 1/1 reg_rdata_next[0] = dio_pad_sleep_en_12_qs;
Tests: T2 T58 T55
39933 end
39934
39935 addr_hit[508]: begin
39936 1/1 reg_rdata_next[0] = dio_pad_sleep_en_13_qs;
Tests: T2 T58 T55
39937 end
39938
39939 addr_hit[509]: begin
39940 1/1 reg_rdata_next[0] = dio_pad_sleep_en_14_qs;
Tests: T2 T58 T55
39941 end
39942
39943 addr_hit[510]: begin
39944 1/1 reg_rdata_next[0] = dio_pad_sleep_en_15_qs;
Tests: T2 T58 T55
39945 end
39946
39947 addr_hit[511]: begin
39948 1/1 reg_rdata_next[1:0] = dio_pad_sleep_mode_0_qs;
Tests: T2 T58 T55
39949 end
39950
39951 addr_hit[512]: begin
39952 1/1 reg_rdata_next[1:0] = dio_pad_sleep_mode_1_qs;
Tests: T2 T45 T86
39953 end
39954
39955 addr_hit[513]: begin
39956 1/1 reg_rdata_next[1:0] = dio_pad_sleep_mode_2_qs;
Tests: T2 T12 T45
39957 end
39958
39959 addr_hit[514]: begin
39960 1/1 reg_rdata_next[1:0] = dio_pad_sleep_mode_3_qs;
Tests: T2 T12 T45
39961 end
39962
39963 addr_hit[515]: begin
39964 1/1 reg_rdata_next[1:0] = dio_pad_sleep_mode_4_qs;
Tests: T2 T87 T156
39965 end
39966
39967 addr_hit[516]: begin
39968 1/1 reg_rdata_next[1:0] = dio_pad_sleep_mode_5_qs;
Tests: T2 T45 T86
39969 end
39970
39971 addr_hit[517]: begin
39972 1/1 reg_rdata_next[1:0] = dio_pad_sleep_mode_6_qs;
Tests: T2 T6 T45
39973 end
39974
39975 addr_hit[518]: begin
39976 1/1 reg_rdata_next[1:0] = dio_pad_sleep_mode_7_qs;
Tests: T2 T6 T45
39977 end
39978
39979 addr_hit[519]: begin
39980 1/1 reg_rdata_next[1:0] = dio_pad_sleep_mode_8_qs;
Tests: T2 T6 T156
39981 end
39982
39983 addr_hit[520]: begin
39984 1/1 reg_rdata_next[1:0] = dio_pad_sleep_mode_9_qs;
Tests: T2 T6 T156
39985 end
39986
39987 addr_hit[521]: begin
39988 1/1 reg_rdata_next[1:0] = dio_pad_sleep_mode_10_qs;
Tests: T2 T156 T217
39989 end
39990
39991 addr_hit[522]: begin
39992 1/1 reg_rdata_next[1:0] = dio_pad_sleep_mode_11_qs;
Tests: T2 T156 T217
39993 end
39994
39995 addr_hit[523]: begin
39996 1/1 reg_rdata_next[1:0] = dio_pad_sleep_mode_12_qs;
Tests: T2 T156 T217
39997 end
39998
39999 addr_hit[524]: begin
40000 1/1 reg_rdata_next[1:0] = dio_pad_sleep_mode_13_qs;
Tests: T2 T12 T156
40001 end
40002
40003 addr_hit[525]: begin
40004 1/1 reg_rdata_next[1:0] = dio_pad_sleep_mode_14_qs;
Tests: T2 T12 T156
40005 end
40006
40007 addr_hit[526]: begin
40008 1/1 reg_rdata_next[1:0] = dio_pad_sleep_mode_15_qs;
Tests: T2 T156 T217
40009 end
40010
40011 addr_hit[527]: begin
40012 1/1 reg_rdata_next[0] = wkup_detector_regwen_0_qs;
Tests: T6 T25 T156
40013 end
40014
40015 addr_hit[528]: begin
40016 1/1 reg_rdata_next[0] = wkup_detector_regwen_1_qs;
Tests: T1 T2 T3
40017 end
40018
40019 addr_hit[529]: begin
40020 1/1 reg_rdata_next[0] = wkup_detector_regwen_2_qs;
Tests: T1 T2 T3
40021 end
40022
40023 addr_hit[530]: begin
40024 1/1 reg_rdata_next[0] = wkup_detector_regwen_3_qs;
Tests: T1 T2 T3
40025 end
40026
40027 addr_hit[531]: begin
40028 1/1 reg_rdata_next[0] = wkup_detector_regwen_4_qs;
Tests: T1 T2 T3
40029 end
40030
40031 addr_hit[532]: begin
40032 1/1 reg_rdata_next[0] = wkup_detector_regwen_5_qs;
Tests: T1 T2 T3
40033 end
40034
40035 addr_hit[533]: begin
40036 1/1 reg_rdata_next[0] = wkup_detector_regwen_6_qs;
Tests: T1 T2 T3
40037 end
40038
40039 addr_hit[534]: begin
40040 1/1 reg_rdata_next[0] = wkup_detector_regwen_7_qs;
Tests: T1 T2 T3
40041 end
40042
40043 addr_hit[535]: begin
40044 1/1 reg_rdata_next = DW'(wkup_detector_en_0_qs);
Tests: T1 T2 T3
40045 end
40046 addr_hit[536]: begin
40047 1/1 reg_rdata_next = DW'(wkup_detector_en_1_qs);
Tests: T1 T2 T3
40048 end
40049 addr_hit[537]: begin
40050 1/1 reg_rdata_next = DW'(wkup_detector_en_2_qs);
Tests: T1 T2 T3
40051 end
40052 addr_hit[538]: begin
40053 1/1 reg_rdata_next = DW'(wkup_detector_en_3_qs);
Tests: T1 T2 T3
40054 end
40055 addr_hit[539]: begin
40056 1/1 reg_rdata_next = DW'(wkup_detector_en_4_qs);
Tests: T1 T2 T3
40057 end
40058 addr_hit[540]: begin
40059 1/1 reg_rdata_next = DW'(wkup_detector_en_5_qs);
Tests: T1 T2 T3
40060 end
40061 addr_hit[541]: begin
40062 1/1 reg_rdata_next = DW'(wkup_detector_en_6_qs);
Tests: T1 T2 T3
40063 end
40064 addr_hit[542]: begin
40065 1/1 reg_rdata_next = DW'(wkup_detector_en_7_qs);
Tests: T1 T2 T3
40066 end
40067 addr_hit[543]: begin
40068 1/1 reg_rdata_next = DW'(wkup_detector_0_qs);
Tests: T1 T2 T3
40069 end
40070 addr_hit[544]: begin
40071 1/1 reg_rdata_next = DW'(wkup_detector_1_qs);
Tests: T1 T2 T3
40072 end
40073 addr_hit[545]: begin
40074 1/1 reg_rdata_next = DW'(wkup_detector_2_qs);
Tests: T1 T2 T3
40075 end
40076 addr_hit[546]: begin
40077 1/1 reg_rdata_next = DW'(wkup_detector_3_qs);
Tests: T1 T2 T3
40078 end
40079 addr_hit[547]: begin
40080 1/1 reg_rdata_next = DW'(wkup_detector_4_qs);
Tests: T1 T2 T3
40081 end
40082 addr_hit[548]: begin
40083 1/1 reg_rdata_next = DW'(wkup_detector_5_qs);
Tests: T1 T2 T3
40084 end
40085 addr_hit[549]: begin
40086 1/1 reg_rdata_next = DW'(wkup_detector_6_qs);
Tests: T1 T2 T3
40087 end
40088 addr_hit[550]: begin
40089 1/1 reg_rdata_next = DW'(wkup_detector_7_qs);
Tests: T1 T2 T3
40090 end
40091 addr_hit[551]: begin
40092 1/1 reg_rdata_next = DW'(wkup_detector_cnt_th_0_qs);
Tests: T1 T2 T3
40093 end
40094 addr_hit[552]: begin
40095 1/1 reg_rdata_next = DW'(wkup_detector_cnt_th_1_qs);
Tests: T1 T2 T3
40096 end
40097 addr_hit[553]: begin
40098 1/1 reg_rdata_next = DW'(wkup_detector_cnt_th_2_qs);
Tests: T1 T2 T3
40099 end
40100 addr_hit[554]: begin
40101 1/1 reg_rdata_next = DW'(wkup_detector_cnt_th_3_qs);
Tests: T1 T2 T3
40102 end
40103 addr_hit[555]: begin
40104 1/1 reg_rdata_next = DW'(wkup_detector_cnt_th_4_qs);
Tests: T1 T2 T3
40105 end
40106 addr_hit[556]: begin
40107 1/1 reg_rdata_next = DW'(wkup_detector_cnt_th_5_qs);
Tests: T1 T2 T3
40108 end
40109 addr_hit[557]: begin
40110 1/1 reg_rdata_next = DW'(wkup_detector_cnt_th_6_qs);
Tests: T1 T2 T3
40111 end
40112 addr_hit[558]: begin
40113 1/1 reg_rdata_next = DW'(wkup_detector_cnt_th_7_qs);
Tests: T1 T2 T3
40114 end
40115 addr_hit[559]: begin
40116 1/1 reg_rdata_next[5:0] = wkup_detector_padsel_0_qs;
Tests: T1 T2 T3
40117 end
40118
40119 addr_hit[560]: begin
40120 1/1 reg_rdata_next[5:0] = wkup_detector_padsel_1_qs;
Tests: T1 T2 T3
40121 end
40122
40123 addr_hit[561]: begin
40124 1/1 reg_rdata_next[5:0] = wkup_detector_padsel_2_qs;
Tests: T1 T2 T3
40125 end
40126
40127 addr_hit[562]: begin
40128 1/1 reg_rdata_next[5:0] = wkup_detector_padsel_3_qs;
Tests: T1 T2 T3
40129 end
40130
40131 addr_hit[563]: begin
40132 1/1 reg_rdata_next[5:0] = wkup_detector_padsel_4_qs;
Tests: T1 T2 T3
40133 end
40134
40135 addr_hit[564]: begin
40136 1/1 reg_rdata_next[5:0] = wkup_detector_padsel_5_qs;
Tests: T1 T2 T3
40137 end
40138
40139 addr_hit[565]: begin
40140 1/1 reg_rdata_next[5:0] = wkup_detector_padsel_6_qs;
Tests: T1 T2 T3
40141 end
40142
40143 addr_hit[566]: begin
40144 1/1 reg_rdata_next[5:0] = wkup_detector_padsel_7_qs;
Tests: T1 T2 T3
40145 end
40146
40147 addr_hit[567]: begin
40148 1/1 reg_rdata_next = DW'(wkup_cause_qs);
Tests: T1 T2 T3
40149 end
40150 default: begin
40151 reg_rdata_next = '1;
40152 end
40153 endcase
40154 end
40155
40156 // shadow busy
40157 logic shadow_busy;
40158 assign shadow_busy = 1'b0;
40159
40160 // register busy
40161 logic reg_busy_sel;
40162 1/1 assign reg_busy = reg_busy_sel | shadow_busy;
Tests: T4 T6 T25
40163 always_comb begin
40164 1/1 reg_busy_sel = '0;
Tests: T1 T2 T3
40165 1/1 unique case (1'b1)
Tests: T1 T2 T3
40166 addr_hit[535]: begin
40167 1/1 reg_busy_sel = wkup_detector_en_0_busy;
Tests: T1 T2 T3
40168 end
40169 addr_hit[536]: begin
40170 1/1 reg_busy_sel = wkup_detector_en_1_busy;
Tests: T1 T2 T3
40171 end
40172 addr_hit[537]: begin
40173 1/1 reg_busy_sel = wkup_detector_en_2_busy;
Tests: T1 T2 T3
40174 end
40175 addr_hit[538]: begin
40176 1/1 reg_busy_sel = wkup_detector_en_3_busy;
Tests: T1 T2 T3
40177 end
40178 addr_hit[539]: begin
40179 1/1 reg_busy_sel = wkup_detector_en_4_busy;
Tests: T1 T2 T3
40180 end
40181 addr_hit[540]: begin
40182 1/1 reg_busy_sel = wkup_detector_en_5_busy;
Tests: T1 T2 T3
40183 end
40184 addr_hit[541]: begin
40185 1/1 reg_busy_sel = wkup_detector_en_6_busy;
Tests: T1 T2 T3
40186 end
40187 addr_hit[542]: begin
40188 1/1 reg_busy_sel = wkup_detector_en_7_busy;
Tests: T1 T2 T3
40189 end
40190 addr_hit[543]: begin
40191 1/1 reg_busy_sel = wkup_detector_0_busy;
Tests: T1 T2 T3
40192 end
40193 addr_hit[544]: begin
40194 1/1 reg_busy_sel = wkup_detector_1_busy;
Tests: T1 T2 T3
40195 end
40196 addr_hit[545]: begin
40197 1/1 reg_busy_sel = wkup_detector_2_busy;
Tests: T1 T2 T3
40198 end
40199 addr_hit[546]: begin
40200 1/1 reg_busy_sel = wkup_detector_3_busy;
Tests: T1 T2 T3
40201 end
40202 addr_hit[547]: begin
40203 1/1 reg_busy_sel = wkup_detector_4_busy;
Tests: T1 T2 T3
40204 end
40205 addr_hit[548]: begin
40206 1/1 reg_busy_sel = wkup_detector_5_busy;
Tests: T1 T2 T3
40207 end
40208 addr_hit[549]: begin
40209 1/1 reg_busy_sel = wkup_detector_6_busy;
Tests: T1 T2 T3
40210 end
40211 addr_hit[550]: begin
40212 1/1 reg_busy_sel = wkup_detector_7_busy;
Tests: T1 T2 T3
40213 end
40214 addr_hit[551]: begin
40215 1/1 reg_busy_sel = wkup_detector_cnt_th_0_busy;
Tests: T1 T2 T3
40216 end
40217 addr_hit[552]: begin
40218 1/1 reg_busy_sel = wkup_detector_cnt_th_1_busy;
Tests: T1 T2 T3
40219 end
40220 addr_hit[553]: begin
40221 1/1 reg_busy_sel = wkup_detector_cnt_th_2_busy;
Tests: T1 T2 T3
40222 end
40223 addr_hit[554]: begin
40224 1/1 reg_busy_sel = wkup_detector_cnt_th_3_busy;
Tests: T1 T2 T3
40225 end
40226 addr_hit[555]: begin
40227 1/1 reg_busy_sel = wkup_detector_cnt_th_4_busy;
Tests: T1 T2 T3
40228 end
40229 addr_hit[556]: begin
40230 1/1 reg_busy_sel = wkup_detector_cnt_th_5_busy;
Tests: T1 T2 T3
40231 end
40232 addr_hit[557]: begin
40233 1/1 reg_busy_sel = wkup_detector_cnt_th_6_busy;
Tests: T1 T2 T3
40234 end
40235 addr_hit[558]: begin
40236 1/1 reg_busy_sel = wkup_detector_cnt_th_7_busy;
Tests: T1 T2 T3
40237 end
40238 addr_hit[567]: begin
40239 1/1 reg_busy_sel = wkup_cause_busy;
Tests: T1 T2 T3
40240 end
40241 default: begin
40242 reg_busy_sel = '0;
40243 end
40244 endcase
40245 end
40246
40247
40248 // Unused signal tieoff
40249
40250 // wdata / byte enable are not always fully used
40251 // add a blanket unused statement to handle lint waivers
40252 logic unused_wdata;
40253 logic unused_be;
40254 1/1 assign unused_wdata = ^reg_wdata;
Tests: T1 T2 T3
40255 1/1 assign unused_be = ^reg_be;
Tests: T1 T2 T3