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 LINE       1298
 EXPRESSION (addr_hit[19] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T75,T227,T391
1	0	1	Covered	T43,T81,T229
1	1	0	Covered	T543,T475,T592
1	1	1	Covered	T43,T81,T83

 LINE       1303
 EXPRESSION (addr_hit[20] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T43,T81,T83
1	0	1	Covered	T43,T81,T229
1	1	0	Covered	T543,T557,T498
1	1	1	Covered	T391,T70,T130

 LINE       1308
 EXPRESSION (addr_hit[21] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T43,T81,T83
1	0	1	Covered	T229,T291,T292
1	1	0	Covered	T540,T475,T641
1	1	1	Covered	T445,T543,T178

 LINE       1317
 EXPRESSION (addr_hit[22] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Covered	T248,T449,T540
1	1	0	Covered	T642,T643,T644
1	1	1	Covered	T2,T3,T5

 LINE       1318
 EXPRESSION (addr_hit[23] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Covered	T248,T448,T449
1	1	0	Covered	T645
1	1	1	Covered	T2,T3,T5

 LINE       1319
 EXPRESSION (addr_hit[24] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T5
1	0	1	Covered	T445,T452,T448
1	1	0	Covered	T646
1	1	1	Covered	T2,T3,T4