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 LINE       63
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T99,T100,T161
1	1	Covered	T53,T88,T89

 LINE       75
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T278,T279,T280
1	0	Not Covered

 LINE       82
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T278,T279,T280
0	1	0	Covered	T281,T282,T477
1	0	0	Covered	T278,T279,T280

 LINE       130
 EXPRESSION ((tl_i.a_address[(AW - 1):0] inside {[128:159]}) ? 1'b0 : 1'b1)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       168
 EXPRESSION (addrmiss | wr_err | intg_err)
             ----1---   ---2--   ----3---

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T281,T282,T477
0	1	0	Covered	T100,T161,T185
1	0	0	Covered	T98,T99,T100

 LINE       447
 EXPRESSION (ibus_addr_en_0_we & ibus_regwen_0_qs)
             --------1--------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T169,T173,T179
1	1	Covered	T206,T208,T272

 LINE       479
 EXPRESSION (ibus_addr_en_1_we & ibus_regwen_1_qs)
             --------1--------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T422,T556,T176
1	1	Covered	T206,T208,T272

 LINE       511
 EXPRESSION (ibus_addr_matching_0_we & ibus_regwen_0_qs)
             -----------1-----------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T169,T179,T422
1	1	Covered	T206,T208,T272

 LINE       543
 EXPRESSION (ibus_addr_matching_1_we & ibus_regwen_1_qs)
             -----------1-----------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T422,T556,T432
1	1	Covered	T206,T208,T272

 LINE       575
 EXPRESSION (ibus_remap_addr_0_we & ibus_regwen_0_qs)
             ----------1---------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T173,T179,T422
1	1	Covered	T206,T208,T272

 LINE       607
 EXPRESSION (ibus_remap_addr_1_we & ibus_regwen_1_qs)
             ----------1---------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T422,T556,T176
1	1	Covered	T206,T208,T272

 LINE       697
 EXPRESSION (dbus_addr_en_0_we & dbus_regwen_0_qs)
             --------1--------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T169,T174,T444
1	1	Covered	T206,T208,T272

 LINE       729
 EXPRESSION (dbus_addr_en_1_we & dbus_regwen_1_qs)
             --------1--------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T179,T422,T556
1	1	Covered	T206,T208,T272

 LINE       761
 EXPRESSION (dbus_addr_matching_0_we & dbus_regwen_0_qs)
             -----------1-----------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T169,T443,T444
1	1	Covered	T206,T208,T272

 LINE       793
 EXPRESSION (dbus_addr_matching_1_we & dbus_regwen_1_qs)
             -----------1-----------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T179,T422,T432
1	1	Covered	T206,T208,T272

 LINE       825
 EXPRESSION (dbus_remap_addr_0_we & dbus_regwen_0_qs)
             ----------1---------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T169,T174,T444
1	1	Covered	T206,T208,T272

 LINE       857
 EXPRESSION (dbus_remap_addr_1_we & dbus_regwen_1_qs)
             ----------1---------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T179,T422,T432
1	1	Covered	T206,T208,T272

 LINE       1175
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_ALERT_TEST_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1176
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_SW_RECOV_ERR_OFFSET)
            ----------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T100,T185,T281

 LINE       1177
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_SW_FATAL_ERR_OFFSET)
            ----------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T273,T100,T185

 LINE       1178
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_IBUS_REGWEN_0_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T206,T208,T272

 LINE       1179
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_IBUS_REGWEN_1_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T206,T208,T272

 LINE       1180
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_IBUS_ADDR_EN_0_OFFSET)
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T206,T208,T272

 LINE       1181
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_IBUS_ADDR_EN_1_OFFSET)
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T206,T208,T272

 LINE       1182
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_IBUS_ADDR_MATCHING_0_OFFSET)
            --------------------------------------1-------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T206,T208,T272

 LINE       1183
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_IBUS_ADDR_MATCHING_1_OFFSET)
            --------------------------------------1-------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T206,T208,T272

 LINE       1184
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_IBUS_REMAP_ADDR_0_OFFSET)
            ------------------------------------1------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T206,T208,T272

 LINE       1185
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_IBUS_REMAP_ADDR_1_OFFSET)
            ------------------------------------1------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T206,T208,T272

 LINE       1186
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_DBUS_REGWEN_0_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T206,T208,T272

 LINE       1187
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_DBUS_REGWEN_1_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T206,T208,T272

 LINE       1188
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_DBUS_ADDR_EN_0_OFFSET)
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T206,T208,T272

 LINE       1189
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_DBUS_ADDR_EN_1_OFFSET)
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T206,T208,T272

 LINE       1190
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_DBUS_ADDR_MATCHING_0_OFFSET)
            --------------------------------------1-------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T206,T208,T272

 LINE       1191
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_DBUS_ADDR_MATCHING_1_OFFSET)
            --------------------------------------1-------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T206,T208,T272

 LINE       1192
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_DBUS_REMAP_ADDR_0_OFFSET)
            ------------------------------------1------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T206,T208,T272

 LINE       1193
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_DBUS_REMAP_ADDR_1_OFFSET)
            ------------------------------------1------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T206,T208,T272

 LINE       1194
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_NMI_ENABLE_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T53,T88,T89

 LINE       1195
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_NMI_STATE_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T53,T88,T89

 LINE       1196
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_ERR_STATUS_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T88,T301,T314

 LINE       1197
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_RND_DATA_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T6

 LINE       1198
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_RND_STATUS_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T6

 LINE       1199
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_FPGA_INFO_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       1202
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       1202
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T53,T88,T89
1	0	Covered	T2,T3,T4

 LINE       1206
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | (addr_hit[5] & ((|(4'b1 & (~reg_be))))) | (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | (addr_hit[7] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[8] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[9] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[10] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[11] & ((|(4'b1 & (~reg_be))))) | (addr_hit[12] & ((|(4'b1 & (~reg_be))))) | (addr_hit[13] & ((|(4'b1 & (~reg_be))))) | (addr_hit[14] & ((|(4'b1 & (~reg_be))))) | (addr_hit[15] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[16] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[17] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[18] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[19] & ((|(4'b1 & (~reg_be))))) | (addr_hit[20] & ((|(4'b1 & (~reg_be))))) | (addr_hit[21] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[22] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[23] & ((|(4'b1 & (~reg_be))))) | (addr_hit[24] & ((|(4'b1111 & (~reg_be)))))))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T53,T88,T89
1	1	Covered	T100,T161,T185

 LINE       1206
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b1 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b1 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | 
      8  (addr_hit[7] & ((|(4'b1111 & (~reg_be))))) | 
      9  (addr_hit[8] & ((|(4'b1111 & (~reg_be))))) | 
     10  (addr_hit[9] & ((|(4'b1111 & (~reg_be))))) | 
     11  (addr_hit[10] & ((|(4'b1111 & (~reg_be))))) | 
     12  (addr_hit[11] & ((|(4'b1 & (~reg_be))))) | 
     13  (addr_hit[12] & ((|(4'b1 & (~reg_be))))) | 
     14  (addr_hit[13] & ((|(4'b1 & (~reg_be))))) | 
     15  (addr_hit[14] & ((|(4'b1 & (~reg_be))))) | 
     16  (addr_hit[15] & ((|(4'b1111 & (~reg_be))))) | 
     17  (addr_hit[16] & ((|(4'b1111 & (~reg_be))))) | 
     18  (addr_hit[17] & ((|(4'b1111 & (~reg_be))))) | 
     19  (addr_hit[18] & ((|(4'b1111 & (~reg_be))))) | 
     20  (addr_hit[19] & ((|(4'b1 & (~reg_be))))) | 
     21  (addr_hit[20] & ((|(4'b1 & (~reg_be))))) | 
     22  (addr_hit[21] & ((|(4'b0011 & (~reg_be))))) | 
     23  (addr_hit[22] & ((|(4'b1111 & (~reg_be))))) | 
     24  (addr_hit[23] & ((|(4'b1 & (~reg_be))))) | 
     25  (addr_hit[24] & ((|(4'b1111 & (~reg_be))))))

Sensitive Expression == 1	Status	Tests
ALL ZEROS	Covered	T1,T2,T3
25 (addr_hit[24] & ((\|(4'...	Covered	T98,T185,T236
24 (addr_hit[23] & ((\|(4'...	Covered	T236,T477,T428
23 (addr_hit[22] & ((\|(4'...	Covered	T100,T185,T281
22 (addr_hit[21] & ((\|(4'...	Covered	T462,T477,T448
21 (addr_hit[20] & ((\|(4'...	Covered	T100,T462,T458
20 (addr_hit[19] & ((\|(4'...	Covered	T185,T462,T458
19 (addr_hit[18] & ((\|(4'...	Covered	T100,T185,T281
18 (addr_hit[17] & ((\|(4'...	Covered	T100,T185,T458
17 (addr_hit[16] & ((\|(4'...	Covered	T458,T477,T428
16 (addr_hit[15] & ((\|(4'...	Covered	T100,T185,T462
15 (addr_hit[14] & ((\|(4'...	Covered	T458,T477,T566
14 (addr_hit[13] & ((\|(4'...	Covered	T100,T185,T462
13 (addr_hit[12] & ((\|(4'...	Covered	T185,T428,T448
12 (addr_hit[11] & ((\|(4'...	Covered	T100,T185,T281
11 (addr_hit[10] & ((\|(4'...	Covered	T98,T100,T185
10 (addr_hit[9] & ((\|(4'b...	Covered	T161,T478,T477
9 (addr_hit[8] & ((\|(4'b...	Covered	T100,T281,T462
8 (addr_hit[7] & ((\|(4'b...	Covered	T100,T161,T185
7 (addr_hit[6] & ((\|(4'b...	Covered	T100,T185,T477
6 (addr_hit[5] & ((\|(4'b...	Covered	T100,T458,T477
5 (addr_hit[4] & ((\|(4'b...	Covered	T100,T462,T478
4 (addr_hit[3] & ((\|(4'b...	Covered	T185,T282,T477
3 (addr_hit[2] & ((\|(4'b...	Covered	T100,T281,T458
2 (addr_hit[1] & ((\|(4'b...	Covered	T100,T185,T281
1 (addr_hit[0] & ((\|(4'b...	Covered	T1,T2,T3

 LINE       1206
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T98,T99,T100
1	0	Covered	T83,T223,T189
1	1	Covered	T1,T2,T3

 LINE       1206
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T458,T477,T461
1	1	Covered	T100,T185,T281

 LINE       1206
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T273,T100,T185
1	1	Covered	T100,T281,T458

 LINE       1206
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T206,T208,T272
1	1	Covered	T185,T282,T477

 LINE       1206
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T206,T208,T272
1	1	Covered	T100,T462,T478

 LINE       1206
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T206,T208,T272
1	1	Covered	T100,T458,T477

 LINE       1206
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T206,T208,T272
1	1	Covered	T100,T185,T477

 LINE       1206
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T206,T208,T272
1	1	Covered	T100,T161,T185

 LINE       1206
 SUB-EXPRESSION (addr_hit[8] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T206,T208,T272
1	1	Covered	T100,T281,T462

 LINE       1206
 SUB-EXPRESSION (addr_hit[9] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T206,T208,T272
1	1	Covered	T161,T478,T477

 LINE       1206
 SUB-EXPRESSION (addr_hit[10] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T206,T208,T272
1	1	Covered	T98,T100,T185

 LINE       1206
 SUB-EXPRESSION (addr_hit[11] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T206,T208,T272
1	1	Covered	T100,T185,T281

 LINE       1206
 SUB-EXPRESSION (addr_hit[12] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T206,T208,T272
1	1	Covered	T185,T428,T448

 LINE       1206
 SUB-EXPRESSION (addr_hit[13] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T206,T208,T272
1	1	Covered	T100,T185,T462

 LINE       1206
 SUB-EXPRESSION (addr_hit[14] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T206,T208,T272
1	1	Covered	T458,T477,T566

 LINE       1206
 SUB-EXPRESSION (addr_hit[15] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T206,T208,T272
1	1	Covered	T100,T185,T462

 LINE       1206
 SUB-EXPRESSION (addr_hit[16] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T206,T208,T272
1	1	Covered	T458,T477,T428

 LINE       1206
 SUB-EXPRESSION (addr_hit[17] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T206,T208,T272
1	1	Covered	T100,T185,T458

 LINE       1206
 SUB-EXPRESSION (addr_hit[18] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T206,T208,T272
1	1	Covered	T100,T185,T281

 LINE       1206
 SUB-EXPRESSION (addr_hit[19] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T53,T88,T89
1	1	Covered	T185,T462,T458

 LINE       1206
 SUB-EXPRESSION (addr_hit[20] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T53,T88,T89
1	1	Covered	T100,T462,T458

 LINE       1206
 SUB-EXPRESSION (addr_hit[21] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T88,T301,T314
1	1	Covered	T462,T477,T448

 LINE       1206
 SUB-EXPRESSION (addr_hit[22] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T6
1	1	Covered	T100,T185,T281

 LINE       1206
 SUB-EXPRESSION (addr_hit[23] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T6
1	1	Covered	T236,T477,T428

 LINE       1206
 SUB-EXPRESSION (addr_hit[24] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T98,T185,T236

 LINE       1235
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T53,T88,T89
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T428,T581,T459
1	1	1	Covered	T83,T223,T189

 LINE       1244
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T53,T88,T89
1	0	1	Covered	T100,T185,T462
1	1	0	Covered	T557,T459,T485
1	1	1	Covered	T458,T461,T524

 LINE       1247
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T53,T88,T89
1	0	1	Covered	T100,T458,T428
1	1	0	Covered	T459,T497,T541
1	1	1	Covered	T273,T100,T185

 LINE       1250
 EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T53,T88,T89
1	0	1	Covered	T206,T208,T272
1	1	0	Covered	T185,T564,T524
1	1	1	Covered	T169,T421,T459

 LINE       1253
 EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T53,T88,T89
1	0	1	Covered	T206,T208,T272
1	1	0	Covered	T100,T428,T429
1	1	1	Covered	T99,T610,T169

 LINE       1256
 EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T53,T88,T89
1	0	1	Covered	T100,T458,T428
1	1	0	Covered	T459,T485,T571
1	1	1	Covered	T206,T208,T272

 LINE       1259
 EXPRESSION (addr_hit[6] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T53,T88,T89
1	0	1	Covered	T185,T448,T429
1	1	0	Covered	T100,T448,T459
1	1	1	Covered	T206,T208,T272

 LINE       1262
 EXPRESSION (addr_hit[7] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T53,T88,T89
1	0	1	Covered	T161,T185,T564
1	1	0	Covered	T100,T428,T448
1	1	1	Covered	T206,T208,T272

 LINE       1265
 EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T53,T88,T89
1	0	1	Covered	T100,T462,T458
1	1	0	Covered	T428,T461,T524
1	1	1	Covered	T206,T208,T272

 LINE       1268
 EXPRESSION (addr_hit[9] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T53,T88,T89
1	0	1	Covered	T161,T428,T461
1	1	0	Covered	T161,T478,T448
1	1	1	Covered	T206,T208,T272

 LINE       1271
 EXPRESSION (addr_hit[10] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T53,T88,T89
1	0	1	Covered	T98,T100,T462
1	1	0	Covered	T185,T458,T460
1	1	1	Covered	T206,T208,T272

 LINE       1274
 EXPRESSION (addr_hit[11] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T53,T88,T89
1	0	1	Covered	T206,T208,T272
1	1	0	Covered	T462,T428,T448
1	1	1	Covered	T458,T461,T448

 LINE       1277
 EXPRESSION (addr_hit[12] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T53,T88,T89
1	0	1	Covered	T206,T208,T272
1	1	0	Covered	T185,T448,T522
1	1	1	Covered	T169,T421,T459

 LINE       1280
 EXPRESSION (addr_hit[13] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T53,T88,T89
1	0	1	Covered	T100,T185,T462
1	1	0	Covered	T462,T448,T459
1	1	1	Covered	T206,T208,T272

 LINE       1283
 EXPRESSION (addr_hit[14] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T53,T88,T89
1	0	1	Covered	T458,T566,T428
1	1	0	Covered	T485,T622,T571
1	1	1	Covered	T206,T208,T272

 LINE       1286
 EXPRESSION (addr_hit[15] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T53,T88,T89
1	0	1	Covered	T100,T462,T458
1	1	0	Covered	T185,T448,T559
1	1	1	Covered	T206,T208,T272

 LINE       1289
 EXPRESSION (addr_hit[16] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T53,T88,T89
1	0	1	Covered	T458,T428,T448
1	1	0	Covered	T557,T538,T496
1	1	1	Covered	T206,T208,T272

 LINE       1292
 EXPRESSION (addr_hit[17] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T53,T88,T89
1	0	1	Covered	T100,T185,T458
1	1	0	Covered	T100,T448,T559
1	1	1	Covered	T206,T208,T272

 LINE       1295
 EXPRESSION (addr_hit[18] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T53,T88,T89
1	0	1	Covered	T100,T185,T458
1	1	0	Covered	T524,T429,T459
1	1	1	Covered	T206,T208,T272

 LINE       1298
 EXPRESSION (addr_hit[19] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T83,T223,T475
1	0	1	Covered	T53,T88,T89
1	1	0	Covered	T459,T485,T568
1	1	1	Covered	T53,T88,T89

 LINE       1303
 EXPRESSION (addr_hit[20] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T53,T88,T89
1	0	1	Covered	T53,T88,T89
1	1	0	Covered	T462,T485,T568
1	1	1	Covered	T475,T77,T136

 LINE       1308
 EXPRESSION (addr_hit[21] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T53,T88,T89
1	0	1	Covered	T88,T301,T314
1	1	0	Covered	T462,T448,T485
1	1	1	Covered	T462,T448,T557

 LINE       1317
 EXPRESSION (addr_hit[22] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Covered	T100,T185,T462
1	1	0	Not Covered
1	1	1	Covered	T2,T5,T6