LINE 1318 EXPRESSION (addr_hit[23] & reg_re & ((!reg_error))) ------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
---|---|---|---|---|
0 | 1 | 1 | Covered | T2,T3,T4 |
1 | 0 | 1 | Covered | T428,T461,T448 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T2,T5,T6 |
LINE 1319 EXPRESSION (addr_hit[24] & reg_re & ((!reg_error))) ------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
---|---|---|---|---|
0 | 1 | 1 | Covered | T2,T5,T6 |
1 | 0 | 1 | Covered | T98,T185,T236 |
1 | 1 | 0 | Covered | T661,T662,T608 |
1 | 1 | 1 | Covered | T2,T3,T4 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |