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 LINE       1298
 EXPRESSION (addr_hit[19] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T80,T279,T461
1	0	1	Covered	T45,T86,T87
1	1	0	Covered	T409,T541,T515
1	1	1	Covered	T45,T86,T87

 LINE       1303
 EXPRESSION (addr_hit[20] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T45,T86,T87
1	0	1	Covered	T45,T86,T87
1	1	0	Covered	T410,T560,T447
1	1	1	Covered	T461,T75,T462

 LINE       1308
 EXPRESSION (addr_hit[21] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T45,T86,T87
1	0	1	Covered	T87,T267,T336
1	1	0	Covered	T98,T445,T432
1	1	1	Covered	T169,T465,T542

 LINE       1317
 EXPRESSION (addr_hit[22] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Covered	T465,T542,T445
1	1	0	Covered	T466,T651,T652
1	1	1	Covered	T2,T4,T5

 LINE       1318
 EXPRESSION (addr_hit[23] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Covered	T98,T103,T309
1	1	0	Covered	T653,T654
1	1	1	Covered	T2,T4,T5

 LINE       1319
 EXPRESSION (addr_hit[24] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T4,T5
1	0	1	Covered	T542,T446,T409
1	1	0	Covered	T655,T656
1	1	1	Covered	T2,T3,T4