| T299 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_unmapped_addr.4090887560 |
|
|
Feb 08 08:59:10 AM UTC 25 |
Feb 08 08:59:36 AM UTC 25 |
472022787 ps |
| T383 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_random.659337000 |
|
|
Feb 08 08:58:59 AM UTC 25 |
Feb 08 08:59:36 AM UTC 25 |
2404687420 ps |
| T384 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_smoke_slow_rsp.3063424400 |
|
|
Feb 08 08:58:23 AM UTC 25 |
Feb 08 08:59:37 AM UTC 25 |
24181645899 ps |
| T385 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_error_random.3391419110 |
|
|
Feb 08 08:59:08 AM UTC 25 |
Feb 08 08:59:40 AM UTC 25 |
330539770 ps |
| T321 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_stress_all_with_error.1180200535 |
|
|
Feb 08 08:58:52 AM UTC 25 |
Feb 08 08:59:41 AM UTC 25 |
2761467436 ps |
| T314 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_stress_all_with_error.2107319466 |
|
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Feb 08 08:56:58 AM UTC 25 |
Feb 08 08:59:42 AM UTC 25 |
1434590557 ps |
| T386 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_access_same_device.4065012431 |
|
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Feb 08 08:59:37 AM UTC 25 |
Feb 08 08:59:45 AM UTC 25 |
126252650 ps |
| T387 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_random_zero_delays.2502451818 |
|
|
Feb 08 08:59:33 AM UTC 25 |
Feb 08 08:59:46 AM UTC 25 |
133637463 ps |
| T296 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_stress_all_with_rand_reset.2519808872 |
|
|
Feb 08 08:57:16 AM UTC 25 |
Feb 08 08:59:47 AM UTC 25 |
1604448531 ps |
| T388 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_unmapped_addr.152370750 |
|
|
Feb 08 08:59:43 AM UTC 25 |
Feb 08 08:59:55 AM UTC 25 |
304178235 ps |
| T389 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_error_and_unmapped_addr.435643081 |
|
|
Feb 08 08:59:46 AM UTC 25 |
Feb 08 08:59:56 AM UTC 25 |
182509985 ps |
| T206 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_random.3267641044 |
|
|
Feb 08 08:59:33 AM UTC 25 |
Feb 08 09:00:01 AM UTC 25 |
534505789 ps |
| T105 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_stress_all.2778839845 |
|
|
Feb 08 08:55:02 AM UTC 25 |
Feb 08 09:00:02 AM UTC 25 |
19112488663 ps |
| T59 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_smoke_slow_rsp.3978133867 |
|
|
Feb 08 08:59:31 AM UTC 25 |
Feb 08 09:00:05 AM UTC 25 |
3900269064 ps |
| T307 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_access_same_device.3244703209 |
|
|
Feb 08 08:59:02 AM UTC 25 |
Feb 08 09:00:06 AM UTC 25 |
2833479881 ps |
| T33 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_stress_all_with_reset_error.2539020064 |
|
|
Feb 08 08:57:00 AM UTC 25 |
Feb 08 09:00:08 AM UTC 25 |
5693404557 ps |
| T390 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_error_random.594936259 |
|
|
Feb 08 08:59:43 AM UTC 25 |
Feb 08 09:00:09 AM UTC 25 |
4170056598 ps |
| T315 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_access_same_device_slow_rsp.2710228404 |
|
|
Feb 08 08:55:23 AM UTC 25 |
Feb 08 09:00:10 AM UTC 25 |
31081630292 ps |
| T272 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_stress_all_with_rand_reset.4019350467 |
|
|
Feb 08 08:54:40 AM UTC 25 |
Feb 08 09:00:12 AM UTC 25 |
894418476 ps |
| T327 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_stress_all_with_reset_error.1783864846 |
|
|
Feb 08 08:58:16 AM UTC 25 |
Feb 08 09:00:14 AM UTC 25 |
174600331 ps |
| T391 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_random_large_delays.766549737 |
|
|
Feb 08 08:58:59 AM UTC 25 |
Feb 08 09:00:14 AM UTC 25 |
13430583374 ps |
| T392 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_same_source.4204754587 |
|
|
Feb 08 08:59:41 AM UTC 25 |
Feb 08 09:00:19 AM UTC 25 |
3921224903 ps |
| T207 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_random_slow_rsp.1883635953 |
|
|
Feb 08 08:57:33 AM UTC 25 |
Feb 08 09:00:19 AM UTC 25 |
21070243589 ps |
| T268 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_access_same_device_slow_rsp.781127596 |
|
|
Feb 08 08:53:46 AM UTC 25 |
Feb 08 09:00:21 AM UTC 25 |
41926793745 ps |
| T393 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_smoke_large_delays.3108346798 |
|
|
Feb 08 08:58:59 AM UTC 25 |
Feb 08 09:00:22 AM UTC 25 |
36353195762 ps |
| T326 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_stress_all_with_reset_error.2121980467 |
|
|
Feb 08 08:56:36 AM UTC 25 |
Feb 08 09:00:22 AM UTC 25 |
1234216628 ps |
| T394 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_smoke_large_delays.2702954192 |
|
|
Feb 08 08:59:31 AM UTC 25 |
Feb 08 09:00:25 AM UTC 25 |
8815021998 ps |
| T204 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_access_same_device_slow_rsp.1007207720 |
|
|
Feb 08 08:58:31 AM UTC 25 |
Feb 08 09:00:30 AM UTC 25 |
12725891648 ps |
| T34 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_stress_all_with_reset_error.2275061062 |
|
|
Feb 08 08:56:12 AM UTC 25 |
Feb 08 09:00:31 AM UTC 25 |
1867490315 ps |
| T124 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_random_large_delays.3365878149 |
|
|
Feb 08 08:56:46 AM UTC 25 |
Feb 08 09:00:36 AM UTC 25 |
57338677760 ps |
| T274 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_smoke_zero_delays.1162872763 |
|
|
Feb 08 09:00:23 AM UTC 25 |
Feb 08 09:00:39 AM UTC 25 |
41373479 ps |
| T275 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_access_same_device_slow_rsp.4219189508 |
|
|
Feb 08 08:59:39 AM UTC 25 |
Feb 08 09:00:41 AM UTC 25 |
9704766648 ps |
| T276 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_smoke.2936801357 |
|
|
Feb 08 09:00:02 AM UTC 25 |
Feb 08 09:00:41 AM UTC 25 |
132678760 ps |
| T277 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_stress_all_with_error.180591719 |
|
|
Feb 08 08:59:18 AM UTC 25 |
Feb 08 09:00:42 AM UTC 25 |
2275581254 ps |
| T278 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_stress_all_with_error.3615033255 |
|
|
Feb 08 08:57:50 AM UTC 25 |
Feb 08 09:00:43 AM UTC 25 |
21079871301 ps |
| T279 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_error_and_unmapped_addr.3824748369 |
|
|
Feb 08 09:00:32 AM UTC 25 |
Feb 08 09:00:44 AM UTC 25 |
70960338 ps |
| T280 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_smoke_zero_delays.3466394786 |
|
|
Feb 08 09:00:41 AM UTC 25 |
Feb 08 09:00:45 AM UTC 25 |
42106302 ps |
| T304 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_smoke.2832047134 |
|
|
Feb 08 09:00:37 AM UTC 25 |
Feb 08 09:00:46 AM UTC 25 |
555549515 ps |
| T35 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_stress_all_with_rand_reset.538629359 |
|
|
Feb 08 08:56:08 AM UTC 25 |
Feb 08 09:00:48 AM UTC 25 |
2858317341 ps |
| T193 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_random_zero_delays.2451717298 |
|
|
Feb 08 09:00:30 AM UTC 25 |
Feb 08 09:00:49 AM UTC 25 |
101803560 ps |
| T154 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_random_large_delays.1679789696 |
|
|
Feb 08 08:57:32 AM UTC 25 |
Feb 08 09:00:49 AM UTC 25 |
31034191808 ps |
| T395 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_random.2989574626 |
|
|
Feb 08 09:00:30 AM UTC 25 |
Feb 08 09:00:51 AM UTC 25 |
144717835 ps |
| T151 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_access_same_device.3516648082 |
|
|
Feb 08 09:00:32 AM UTC 25 |
Feb 08 09:00:51 AM UTC 25 |
964953598 ps |
| T396 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_random_zero_delays.716157777 |
|
|
Feb 08 09:00:45 AM UTC 25 |
Feb 08 09:00:52 AM UTC 25 |
42038152 ps |
| T320 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_access_same_device_slow_rsp.3207575875 |
|
|
Feb 08 08:56:23 AM UTC 25 |
Feb 08 09:00:57 AM UTC 25 |
44959327170 ps |
| T397 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_error_random.1201553609 |
|
|
Feb 08 09:00:32 AM UTC 25 |
Feb 08 09:00:58 AM UTC 25 |
229224622 ps |
| T398 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_same_source.1095255841 |
|
|
Feb 08 09:00:32 AM UTC 25 |
Feb 08 09:01:00 AM UTC 25 |
240022326 ps |
| T399 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_stress_all.736849506 |
|
|
Feb 08 08:58:10 AM UTC 25 |
Feb 08 09:01:00 AM UTC 25 |
4005658423 ps |
| T400 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_unmapped_addr.4059589610 |
|
|
Feb 08 09:00:32 AM UTC 25 |
Feb 08 09:01:00 AM UTC 25 |
386480518 ps |
| T401 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_random.3803348230 |
|
|
Feb 08 09:00:43 AM UTC 25 |
Feb 08 09:01:01 AM UTC 25 |
1241131182 ps |
| T402 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_stress_all_with_error.1743118705 |
|
|
Feb 08 09:00:35 AM UTC 25 |
Feb 08 09:01:01 AM UTC 25 |
565375932 ps |
| T403 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_stress_all_with_reset_error.2742763236 |
|
|
Feb 08 08:59:20 AM UTC 25 |
Feb 08 09:01:04 AM UTC 25 |
4130354194 ps |
| T404 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_smoke.1871675043 |
|
|
Feb 08 09:01:01 AM UTC 25 |
Feb 08 09:01:06 AM UTC 25 |
32611092 ps |
| T405 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_smoke_zero_delays.635640135 |
|
|
Feb 08 09:01:01 AM UTC 25 |
Feb 08 09:01:06 AM UTC 25 |
48997380 ps |
| T406 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_random.3932831846 |
|
|
Feb 08 09:01:03 AM UTC 25 |
Feb 08 09:01:07 AM UTC 25 |
57533793 ps |
| T329 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_stress_all_with_reset_error.606248849 |
|
|
Feb 08 08:58:54 AM UTC 25 |
Feb 08 09:01:08 AM UTC 25 |
2400230614 ps |
| T407 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_stress_all.790026261 |
|
|
Feb 08 09:00:52 AM UTC 25 |
Feb 08 09:01:10 AM UTC 25 |
317894639 ps |
| T408 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_error_random.1885312437 |
|
|
Feb 08 09:00:50 AM UTC 25 |
Feb 08 09:01:11 AM UTC 25 |
147550606 ps |
| T409 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_random_zero_delays.3573741247 |
|
|
Feb 08 09:01:04 AM UTC 25 |
Feb 08 09:01:11 AM UTC 25 |
32882986 ps |
| T410 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_stress_all_with_error.1294454941 |
|
|
Feb 08 08:58:16 AM UTC 25 |
Feb 08 09:01:11 AM UTC 25 |
12295725071 ps |
| T411 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_smoke_large_delays.1596299088 |
|
|
Feb 08 09:00:27 AM UTC 25 |
Feb 08 09:01:17 AM UTC 25 |
9530389288 ps |
| T46 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_same_source.3412879192 |
|
|
Feb 08 09:00:50 AM UTC 25 |
Feb 08 09:01:18 AM UTC 25 |
841863240 ps |
| T412 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_smoke_large_delays.1629189189 |
|
|
Feb 08 09:00:43 AM UTC 25 |
Feb 08 09:01:19 AM UTC 25 |
4748017541 ps |
| T270 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_stress_all.167012319 |
|
|
Feb 08 09:00:32 AM UTC 25 |
Feb 08 09:01:21 AM UTC 25 |
1657471834 ps |
| T413 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_same_source.2908887741 |
|
|
Feb 08 09:01:12 AM UTC 25 |
Feb 08 09:01:25 AM UTC 25 |
468259245 ps |
| T414 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_error_and_unmapped_addr.1970965440 |
|
|
Feb 08 09:00:52 AM UTC 25 |
Feb 08 09:01:25 AM UTC 25 |
2091277644 ps |
| T125 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_stress_all.3936799658 |
|
|
Feb 08 08:59:16 AM UTC 25 |
Feb 08 09:01:26 AM UTC 25 |
3511344048 ps |
| T60 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_smoke_slow_rsp.2135688572 |
|
|
Feb 08 09:01:02 AM UTC 25 |
Feb 08 09:01:26 AM UTC 25 |
3713301490 ps |
| T242 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_unmapped_addr.3368088985 |
|
|
Feb 08 09:00:52 AM UTC 25 |
Feb 08 09:01:27 AM UTC 25 |
1406751347 ps |
| T415 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_smoke_slow_rsp.3265192561 |
|
|
Feb 08 09:00:43 AM UTC 25 |
Feb 08 09:01:27 AM UTC 25 |
10566910805 ps |
| T312 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_access_same_device_slow_rsp.1042038547 |
|
|
Feb 08 08:54:52 AM UTC 25 |
Feb 08 09:01:29 AM UTC 25 |
47738526814 ps |
| T416 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_smoke_zero_delays.2545012826 |
|
|
Feb 08 09:01:26 AM UTC 25 |
Feb 08 09:01:30 AM UTC 25 |
57092335 ps |
| T61 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_smoke.4216135375 |
|
|
Feb 08 09:01:25 AM UTC 25 |
Feb 08 09:01:31 AM UTC 25 |
162741220 ps |
| T417 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_random_large_delays.2770495171 |
|
|
Feb 08 09:00:45 AM UTC 25 |
Feb 08 09:01:33 AM UTC 25 |
5851035981 ps |
| T418 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_random_slow_rsp.3813840374 |
|
|
Feb 08 08:58:05 AM UTC 25 |
Feb 08 09:01:34 AM UTC 25 |
43031714523 ps |
| T243 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_unmapped_addr.3246667335 |
|
|
Feb 08 09:01:12 AM UTC 25 |
Feb 08 09:01:36 AM UTC 25 |
895717464 ps |
| T126 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_access_same_device.2759428137 |
|
|
Feb 08 09:00:48 AM UTC 25 |
Feb 08 09:01:36 AM UTC 25 |
3098439761 ps |
| T419 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_error_and_unmapped_addr.173623272 |
|
|
Feb 08 09:01:13 AM UTC 25 |
Feb 08 09:01:36 AM UTC 25 |
736985695 ps |
| T420 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_stress_all_with_error.2515838938 |
|
|
Feb 08 09:01:20 AM UTC 25 |
Feb 08 09:01:38 AM UTC 25 |
636508300 ps |
| T421 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_error_random.1845595223 |
|
|
Feb 08 09:01:12 AM UTC 25 |
Feb 08 09:01:39 AM UTC 25 |
869739030 ps |
| T422 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_random.3067959451 |
|
|
Feb 08 09:01:28 AM UTC 25 |
Feb 08 09:01:43 AM UTC 25 |
137675944 ps |
| T423 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_same_source.1840482612 |
|
|
Feb 08 09:01:34 AM UTC 25 |
Feb 08 09:01:43 AM UTC 25 |
74737205 ps |
| T424 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_random_large_delays.1083234129 |
|
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Feb 08 08:58:24 AM UTC 25 |
Feb 08 09:01:45 AM UTC 25 |
24945090026 ps |
| T425 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_unmapped_addr.3592420749 |
|
|
Feb 08 09:01:38 AM UTC 25 |
Feb 08 09:01:46 AM UTC 25 |
149148328 ps |
| T426 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_smoke_large_delays.597635423 |
|
|
Feb 08 09:01:02 AM UTC 25 |
Feb 08 09:01:47 AM UTC 25 |
7940396049 ps |
| T427 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_error_random.2569202681 |
|
|
Feb 08 09:01:36 AM UTC 25 |
Feb 08 09:01:50 AM UTC 25 |
78156738 ps |
| T127 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_access_same_device.4207242763 |
|
|
Feb 08 09:01:08 AM UTC 25 |
Feb 08 09:01:52 AM UTC 25 |
1917901088 ps |
| T330 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_stress_all_with_rand_reset.2427620026 |
|
|
Feb 08 08:54:13 AM UTC 25 |
Feb 08 09:01:52 AM UTC 25 |
3480812182 ps |
| T428 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_smoke_zero_delays.4080559074 |
|
|
Feb 08 09:01:47 AM UTC 25 |
Feb 08 09:01:52 AM UTC 25 |
54891779 ps |
| T205 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_stress_all_with_rand_reset.3801302448 |
|
|
Feb 08 08:53:51 AM UTC 25 |
Feb 08 09:01:52 AM UTC 25 |
3141413245 ps |
| T429 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_error_and_unmapped_addr.2429350955 |
|
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Feb 08 09:01:38 AM UTC 25 |
Feb 08 09:01:52 AM UTC 25 |
387064875 ps |
| T62 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_smoke.1664646519 |
|
|
Feb 08 09:01:46 AM UTC 25 |
Feb 08 09:01:53 AM UTC 25 |
212864459 ps |
| T430 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_smoke_slow_rsp.281820044 |
|
|
Feb 08 09:00:27 AM UTC 25 |
Feb 08 09:01:56 AM UTC 25 |
13061040678 ps |
| T128 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_stress_all.1561812462 |
|
|
Feb 08 08:58:47 AM UTC 25 |
Feb 08 09:01:56 AM UTC 25 |
8269167676 ps |
| T210 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_stress_all_with_reset_error.3110443817 |
|
|
Feb 08 09:00:58 AM UTC 25 |
Feb 08 09:01:56 AM UTC 25 |
131880506 ps |
| T211 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_random_zero_delays.1300720755 |
|
|
Feb 08 09:01:53 AM UTC 25 |
Feb 08 09:01:58 AM UTC 25 |
32657364 ps |
| T212 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_stress_all_with_rand_reset.2511939735 |
|
|
Feb 08 08:59:48 AM UTC 25 |
Feb 08 09:01:59 AM UTC 25 |
314462915 ps |
| T213 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_random_zero_delays.4102226296 |
|
|
Feb 08 09:01:28 AM UTC 25 |
Feb 08 09:01:59 AM UTC 25 |
453758060 ps |
| T214 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_random.2770442783 |
|
|
Feb 08 09:01:53 AM UTC 25 |
Feb 08 09:02:01 AM UTC 25 |
130474163 ps |
| T215 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_random_slow_rsp.3992476576 |
|
|
Feb 08 08:59:00 AM UTC 25 |
Feb 08 09:02:07 AM UTC 25 |
16735319147 ps |
| T216 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_error_and_unmapped_addr.4245020196 |
|
|
Feb 08 09:01:58 AM UTC 25 |
Feb 08 09:02:09 AM UTC 25 |
67759832 ps |
| T129 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_stress_all.3038665356 |
|
|
Feb 08 08:59:48 AM UTC 25 |
Feb 08 09:02:10 AM UTC 25 |
3822358975 ps |
| T217 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_access_same_device.3805990208 |
|
|
Feb 08 09:01:55 AM UTC 25 |
Feb 08 09:02:12 AM UTC 25 |
1542039433 ps |
| T431 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_stress_all_with_error.1163002694 |
|
|
Feb 08 08:59:56 AM UTC 25 |
Feb 08 09:02:13 AM UTC 25 |
6842748343 ps |
| T432 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_smoke_slow_rsp.1147242596 |
|
|
Feb 08 09:01:27 AM UTC 25 |
Feb 08 09:02:13 AM UTC 25 |
6300566740 ps |
| T433 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_smoke_large_delays.3719457280 |
|
|
Feb 08 09:01:27 AM UTC 25 |
Feb 08 09:02:14 AM UTC 25 |
7346701349 ps |
| T434 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_smoke.3072459187 |
|
|
Feb 08 09:02:11 AM UTC 25 |
Feb 08 09:02:15 AM UTC 25 |
33742311 ps |
| T435 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_smoke_zero_delays.1821200424 |
|
|
Feb 08 09:02:11 AM UTC 25 |
Feb 08 09:02:16 AM UTC 25 |
50908942 ps |
| T130 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_access_same_device.1545804562 |
|
|
Feb 08 09:01:32 AM UTC 25 |
Feb 08 09:02:17 AM UTC 25 |
869082863 ps |
| T436 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_unmapped_addr.3762213870 |
|
|
Feb 08 09:01:57 AM UTC 25 |
Feb 08 09:02:23 AM UTC 25 |
748435588 ps |
| T437 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_error_random.3450478775 |
|
|
Feb 08 09:01:57 AM UTC 25 |
Feb 08 09:02:24 AM UTC 25 |
763709664 ps |
| T438 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_same_source.4163503938 |
|
|
Feb 08 09:01:57 AM UTC 25 |
Feb 08 09:02:25 AM UTC 25 |
341921164 ps |
| T332 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_stress_all_with_rand_reset.485764535 |
|
|
Feb 08 08:55:06 AM UTC 25 |
Feb 08 09:02:26 AM UTC 25 |
1398812979 ps |
| T439 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_random_large_delays.2890198974 |
|
|
Feb 08 08:59:35 AM UTC 25 |
Feb 08 09:02:30 AM UTC 25 |
32553647250 ps |
| T440 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_random.1706505709 |
|
|
Feb 08 09:02:14 AM UTC 25 |
Feb 08 09:02:30 AM UTC 25 |
386871415 ps |
| T441 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_same_source.2327267736 |
|
|
Feb 08 09:02:24 AM UTC 25 |
Feb 08 09:02:31 AM UTC 25 |
208497018 ps |
| T442 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_smoke_slow_rsp.435836032 |
|
|
Feb 08 09:01:51 AM UTC 25 |
Feb 08 09:02:35 AM UTC 25 |
12320309776 ps |
| T443 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_stress_all_with_error.952252689 |
|
|
Feb 08 09:00:57 AM UTC 25 |
Feb 08 09:02:37 AM UTC 25 |
2902086633 ps |
| T444 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_error_and_unmapped_addr.1367468185 |
|
|
Feb 08 09:02:31 AM UTC 25 |
Feb 08 09:02:40 AM UTC 25 |
48977035 ps |
| T316 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_access_same_device.2400923884 |
|
|
Feb 08 09:02:18 AM UTC 25 |
Feb 08 09:02:40 AM UTC 25 |
497849892 ps |
| T445 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_smoke_large_delays.2529032677 |
|
|
Feb 08 09:01:48 AM UTC 25 |
Feb 08 09:02:40 AM UTC 25 |
17254442536 ps |
| T446 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_random_slow_rsp.1149795594 |
|
|
Feb 08 08:56:22 AM UTC 25 |
Feb 08 09:02:41 AM UTC 25 |
173026332579 ps |
| T325 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_access_same_device_slow_rsp.4139344094 |
|
|
Feb 08 09:01:55 AM UTC 25 |
Feb 08 09:02:41 AM UTC 25 |
4642910523 ps |
| T447 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_unmapped_addr.1593747279 |
|
|
Feb 08 09:02:27 AM UTC 25 |
Feb 08 09:02:42 AM UTC 25 |
269370205 ps |
| T317 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_stress_all_with_rand_reset.4057965121 |
|
|
Feb 08 08:59:18 AM UTC 25 |
Feb 08 09:02:44 AM UTC 25 |
3255206292 ps |
| T448 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_smoke_zero_delays.383230820 |
|
|
Feb 08 09:02:41 AM UTC 25 |
Feb 08 09:02:46 AM UTC 25 |
83556079 ps |
| T449 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_smoke.2274830621 |
|
|
Feb 08 09:02:41 AM UTC 25 |
Feb 08 09:02:47 AM UTC 25 |
117507255 ps |
| T450 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_random_zero_delays.1260463115 |
|
|
Feb 08 09:02:15 AM UTC 25 |
Feb 08 09:02:50 AM UTC 25 |
374022809 ps |
| T451 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_random_zero_delays.1793272316 |
|
|
Feb 08 09:02:43 AM UTC 25 |
Feb 08 09:02:52 AM UTC 25 |
80667526 ps |
| T331 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_stress_all_with_reset_error.3385823347 |
|
|
Feb 08 08:57:50 AM UTC 25 |
Feb 08 09:02:53 AM UTC 25 |
700772034 ps |
| T452 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_smoke_slow_rsp.335778127 |
|
|
Feb 08 09:02:14 AM UTC 25 |
Feb 08 09:02:56 AM UTC 25 |
3032620068 ps |
| T453 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_error_random.2308988366 |
|
|
Feb 08 09:02:26 AM UTC 25 |
Feb 08 09:02:58 AM UTC 25 |
688623070 ps |
| T454 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_unmapped_addr.1199323932 |
|
|
Feb 08 09:02:56 AM UTC 25 |
Feb 08 09:03:02 AM UTC 25 |
21174088 ps |
| T455 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_access_same_device.2744257567 |
|
|
Feb 08 09:02:48 AM UTC 25 |
Feb 08 09:03:03 AM UTC 25 |
223710120 ps |
| T456 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_random_large_delays.2766164597 |
|
|
Feb 08 09:01:06 AM UTC 25 |
Feb 08 09:03:04 AM UTC 25 |
21675233918 ps |
| T208 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_access_same_device_slow_rsp.111856822 |
|
|
Feb 08 08:52:48 AM UTC 25 |
Feb 08 09:03:04 AM UTC 25 |
170052875761 ps |
| T457 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_smoke_large_delays.3126506610 |
|
|
Feb 08 09:02:13 AM UTC 25 |
Feb 08 09:03:08 AM UTC 25 |
7232017127 ps |
| T458 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_stress_all_with_reset_error.199938021 |
|
|
Feb 08 09:01:44 AM UTC 25 |
Feb 08 09:03:08 AM UTC 25 |
309947816 ps |
| T459 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_error_and_unmapped_addr.4193717869 |
|
|
Feb 08 09:02:59 AM UTC 25 |
Feb 08 09:03:08 AM UTC 25 |
45757356 ps |
| T460 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_smoke_slow_rsp.1446796809 |
|
|
Feb 08 09:02:42 AM UTC 25 |
Feb 08 09:03:09 AM UTC 25 |
4168867154 ps |
| T194 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_stress_all_with_rand_reset.2433464614 |
|
|
Feb 08 08:57:49 AM UTC 25 |
Feb 08 09:03:09 AM UTC 25 |
3122709384 ps |
| T461 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_error_random.3209748043 |
|
|
Feb 08 09:02:55 AM UTC 25 |
Feb 08 09:03:13 AM UTC 25 |
116949185 ps |
| T462 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_smoke_zero_delays.930137027 |
|
|
Feb 08 09:03:09 AM UTC 25 |
Feb 08 09:03:14 AM UTC 25 |
51646019 ps |
| T463 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_stress_all_with_error.744012128 |
|
|
Feb 08 09:01:44 AM UTC 25 |
Feb 08 09:03:14 AM UTC 25 |
5923229745 ps |
| T464 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_smoke.2068927251 |
|
|
Feb 08 09:03:09 AM UTC 25 |
Feb 08 09:03:16 AM UTC 25 |
162128420 ps |
| T465 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_stress_all_with_error.2395034505 |
|
|
Feb 08 09:02:01 AM UTC 25 |
Feb 08 09:03:17 AM UTC 25 |
570664266 ps |
| T466 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_stress_all_with_reset_error.520863870 |
|
|
Feb 08 08:55:10 AM UTC 25 |
Feb 08 09:03:22 AM UTC 25 |
9721858263 ps |
| T467 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_random_slow_rsp.3190161862 |
|
|
Feb 08 08:58:24 AM UTC 25 |
Feb 08 09:03:22 AM UTC 25 |
46535863337 ps |
| T468 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_same_source.1853232038 |
|
|
Feb 08 09:02:54 AM UTC 25 |
Feb 08 09:03:24 AM UTC 25 |
1004480516 ps |
| T469 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_access_same_device.2105806021 |
|
|
Feb 08 09:03:17 AM UTC 25 |
Feb 08 09:03:26 AM UTC 25 |
105152438 ps |
| T209 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_random.879083655 |
|
|
Feb 08 09:02:42 AM UTC 25 |
Feb 08 09:03:27 AM UTC 25 |
2960116572 ps |
| T470 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_random.284038164 |
|
|
Feb 08 09:03:10 AM UTC 25 |
Feb 08 09:03:28 AM UTC 25 |
375410558 ps |
| T131 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_random_large_delays.1271440980 |
|
|
Feb 08 09:01:53 AM UTC 25 |
Feb 08 09:03:31 AM UTC 25 |
33121961281 ps |
| T471 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_same_source.2136488861 |
|
|
Feb 08 09:03:23 AM UTC 25 |
Feb 08 09:03:33 AM UTC 25 |
321104395 ps |
| T237 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_smoke_large_delays.1354094750 |
|
|
Feb 08 09:03:09 AM UTC 25 |
Feb 08 09:03:44 AM UTC 25 |
7378363749 ps |
| T472 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_stress_all_with_reset_error.1742461779 |
|
|
Feb 08 09:02:38 AM UTC 25 |
Feb 08 09:03:44 AM UTC 25 |
345877461 ps |
| T473 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_smoke_large_delays.3663136403 |
|
|
Feb 08 09:02:41 AM UTC 25 |
Feb 08 09:03:44 AM UTC 25 |
6838329874 ps |
| T63 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_smoke_slow_rsp.3920257605 |
|
|
Feb 08 09:03:10 AM UTC 25 |
Feb 08 09:03:46 AM UTC 25 |
3866408486 ps |
| T303 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_stress_all_with_rand_reset.4290466099 |
|
|
Feb 08 08:58:49 AM UTC 25 |
Feb 08 09:03:47 AM UTC 25 |
2792538334 ps |
| T474 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_error_and_unmapped_addr.2314838931 |
|
|
Feb 08 09:03:27 AM UTC 25 |
Feb 08 09:03:47 AM UTC 25 |
542745935 ps |
| T475 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_stress_all_with_rand_reset.1756029057 |
|
|
Feb 08 09:03:29 AM UTC 25 |
Feb 08 09:03:47 AM UTC 25 |
11955721 ps |
| T238 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_random_zero_delays.746022355 |
|
|
Feb 08 09:03:13 AM UTC 25 |
Feb 08 09:03:48 AM UTC 25 |
341751532 ps |
| T476 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_error_random.1382251538 |
|
|
Feb 08 09:03:23 AM UTC 25 |
Feb 08 09:03:48 AM UTC 25 |
3209562969 ps |
| T477 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_unmapped_addr.1326081528 |
|
|
Feb 08 09:05:31 AM UTC 25 |
Feb 08 09:05:41 AM UTC 25 |
262869988 ps |
| T478 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_smoke_zero_delays.3252897859 |
|
|
Feb 08 09:03:45 AM UTC 25 |
Feb 08 09:03:50 AM UTC 25 |
39387179 ps |
| T479 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_stress_all_with_reset_error.1081409411 |
|
|
Feb 08 08:59:58 AM UTC 25 |
Feb 08 09:03:50 AM UTC 25 |
6813251208 ps |
| T64 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_random_slow_rsp.1510750100 |
|
|
Feb 08 09:02:46 AM UTC 25 |
Feb 08 09:03:51 AM UTC 25 |
15987611637 ps |
| T65 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_smoke.1791413141 |
|
|
Feb 08 09:03:45 AM UTC 25 |
Feb 08 09:03:52 AM UTC 25 |
272259704 ps |
| T480 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_random.78905677 |
|
|
Feb 08 09:03:48 AM UTC 25 |
Feb 08 09:03:53 AM UTC 25 |
54814542 ps |
| T481 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_access_same_device.629742455 |
|
|
Feb 08 09:03:49 AM UTC 25 |
Feb 08 09:03:59 AM UTC 25 |
204545325 ps |
| T482 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_stress_all.3311315710 |
|
|
Feb 08 09:01:18 AM UTC 25 |
Feb 08 09:04:00 AM UTC 25 |
5041149868 ps |
| T483 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_error_random.1885397098 |
|
|
Feb 08 09:03:52 AM UTC 25 |
Feb 08 09:04:02 AM UTC 25 |
191860807 ps |
| T484 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_random_slow_rsp.3625623279 |
|
|
Feb 08 09:01:31 AM UTC 25 |
Feb 08 09:04:03 AM UTC 25 |
17885618879 ps |
| T132 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_stress_all.2176214094 |
|
|
Feb 08 09:01:39 AM UTC 25 |
Feb 08 09:04:04 AM UTC 25 |
5680995477 ps |
| T485 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_unmapped_addr.2906079183 |
|
|
Feb 08 09:03:24 AM UTC 25 |
Feb 08 09:04:04 AM UTC 25 |
869728577 ps |
| T486 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_random_slow_rsp.528597430 |
|
|
Feb 08 09:03:49 AM UTC 25 |
Feb 08 09:04:06 AM UTC 25 |
2152312360 ps |
| T487 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_random_zero_delays.3883240143 |
|
|
Feb 08 09:03:49 AM UTC 25 |
Feb 08 09:04:06 AM UTC 25 |
214897740 ps |
| T488 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_smoke_zero_delays.3956305279 |
|
|
Feb 08 09:04:05 AM UTC 25 |
Feb 08 09:04:11 AM UTC 25 |
24426307 ps |
| T489 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_smoke.1599316478 |
|
|
Feb 08 09:04:05 AM UTC 25 |
Feb 08 09:04:13 AM UTC 25 |
1061719909 ps |
| T490 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_random_slow_rsp.1659618245 |
|
|
Feb 08 09:01:07 AM UTC 25 |
Feb 08 09:04:17 AM UTC 25 |
18199598312 ps |
| T491 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_stress_all_with_reset_error.3713204037 |
|
|
Feb 08 09:04:04 AM UTC 25 |
Feb 08 09:04:19 AM UTC 25 |
84158465 ps |
| T492 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_same_source.2422102670 |
|
|
Feb 08 09:03:51 AM UTC 25 |
Feb 08 09:04:24 AM UTC 25 |
4390032344 ps |
| T66 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_smoke_slow_rsp.4289772973 |
|
|
Feb 08 09:03:48 AM UTC 25 |
Feb 08 09:04:24 AM UTC 25 |
3841529098 ps |
| T493 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_unmapped_addr.4238807282 |
|
|
Feb 08 09:03:52 AM UTC 25 |
Feb 08 09:04:25 AM UTC 25 |
1707326584 ps |
| T494 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_random_zero_delays.1994032144 |
|
|
Feb 08 09:04:14 AM UTC 25 |
Feb 08 09:04:27 AM UTC 25 |
95325314 ps |
| T495 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_error_and_unmapped_addr.1493300363 |
|
|
Feb 08 09:03:55 AM UTC 25 |
Feb 08 09:04:29 AM UTC 25 |
1296891892 ps |
| T496 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_stress_all_with_error.1818340922 |
|
|
Feb 08 09:02:35 AM UTC 25 |
Feb 08 09:04:31 AM UTC 25 |
5833369922 ps |
| T133 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_access_same_device_slow_rsp.2354042424 |
|
|
Feb 08 08:54:08 AM UTC 25 |
Feb 08 09:04:33 AM UTC 25 |
75555332301 ps |
| T497 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_stress_all_with_rand_reset.3650374958 |
|
|
Feb 08 08:56:33 AM UTC 25 |
Feb 08 09:04:36 AM UTC 25 |
8132824639 ps |
| T498 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_stress_all_with_rand_reset.206929558 |
|
|
Feb 08 08:52:32 AM UTC 25 |
Feb 08 09:04:44 AM UTC 25 |
15394775750 ps |
| T298 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_access_same_device.3012815889 |
|
|
Feb 08 09:04:25 AM UTC 25 |
Feb 08 09:04:45 AM UTC 25 |
460522753 ps |
| T499 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_smoke_large_delays.2893159572 |
|
|
Feb 08 09:04:07 AM UTC 25 |
Feb 08 09:04:48 AM UTC 25 |
6312248106 ps |
| T500 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_smoke_slow_rsp.3984162848 |
|
|
Feb 08 09:04:07 AM UTC 25 |
Feb 08 09:04:52 AM UTC 25 |
9410123607 ps |
| T501 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_smoke_large_delays.2124542254 |
|
|
Feb 08 09:03:45 AM UTC 25 |
Feb 08 09:04:53 AM UTC 25 |
5398776516 ps |
| T502 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_smoke.3864762723 |
|
|
Feb 08 09:04:49 AM UTC 25 |
Feb 08 09:04:53 AM UTC 25 |
44451279 ps |
| T503 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_stress_all_with_reset_error.252943860 |
|
|
Feb 08 09:03:34 AM UTC 25 |
Feb 08 09:04:54 AM UTC 25 |
573183111 ps |
| T504 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_same_source.1348877489 |
|
|
Feb 08 09:04:26 AM UTC 25 |
Feb 08 09:04:55 AM UTC 25 |
3097017071 ps |
| T505 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_unmapped_addr.246524750 |
|
|
Feb 08 09:04:30 AM UTC 25 |
Feb 08 09:04:55 AM UTC 25 |
470514501 ps |
| T506 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_stress_all_with_error.1830656266 |
|
|
Feb 08 09:03:32 AM UTC 25 |
Feb 08 09:04:55 AM UTC 25 |
2701218421 ps |
| T195 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_random.4184068413 |
|
|
Feb 08 09:04:11 AM UTC 25 |
Feb 08 09:04:55 AM UTC 25 |
739221792 ps |
| T507 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_stress_all_with_reset_error.67595271 |
|
|
Feb 08 09:00:35 AM UTC 25 |
Feb 08 09:04:56 AM UTC 25 |
5008004118 ps |
| T508 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_error_random.665796715 |
|
|
Feb 08 09:04:28 AM UTC 25 |
Feb 08 09:04:57 AM UTC 25 |
565320386 ps |
| T509 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_smoke_zero_delays.1754688886 |
|
|
Feb 08 09:04:53 AM UTC 25 |
Feb 08 09:04:57 AM UTC 25 |
103961059 ps |
| T510 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_stress_all_with_rand_reset.3207845490 |
|
|
Feb 08 09:02:00 AM UTC 25 |
Feb 08 09:05:00 AM UTC 25 |
343743507 ps |
| T511 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_error_and_unmapped_addr.4249609061 |
|
|
Feb 08 09:04:32 AM UTC 25 |
Feb 08 09:05:04 AM UTC 25 |
821335083 ps |
| T512 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_stress_all_with_rand_reset.601930032 |
|
|
Feb 08 09:01:19 AM UTC 25 |
Feb 08 09:05:06 AM UTC 25 |
2788203082 ps |
| T196 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_stress_all.4277087468 |
|
|
Feb 08 09:01:59 AM UTC 25 |
Feb 08 09:05:07 AM UTC 25 |
1571698190 ps |
| T513 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_random_slow_rsp.4246773648 |
|
|
Feb 08 09:01:54 AM UTC 25 |
Feb 08 09:05:10 AM UTC 25 |
23402694633 ps |
| T514 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_same_source.3326684391 |
|
|
Feb 08 09:04:58 AM UTC 25 |
Feb 08 09:05:11 AM UTC 25 |
1776475409 ps |
| T515 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_random.2999470056 |
|
|
Feb 08 09:04:56 AM UTC 25 |
Feb 08 09:05:13 AM UTC 25 |
156987339 ps |
| T516 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_unmapped_addr.2213982054 |
|
|
Feb 08 09:05:01 AM UTC 25 |
Feb 08 09:05:15 AM UTC 25 |
314077658 ps |
| T517 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_error_random.3990499303 |
|
|
Feb 08 09:04:58 AM UTC 25 |
Feb 08 09:05:16 AM UTC 25 |
663114899 ps |
| T518 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_stress_all_with_error.3222421922 |
|
|
Feb 08 09:04:45 AM UTC 25 |
Feb 08 09:05:20 AM UTC 25 |
620635552 ps |
| T519 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_smoke.4463706 |
|
|
Feb 08 09:05:14 AM UTC 25 |
Feb 08 09:05:20 AM UTC 25 |
121036689 ps |
| T520 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_smoke_zero_delays.2869968479 |
|
|
Feb 08 09:05:16 AM UTC 25 |
Feb 08 09:05:21 AM UTC 25 |
72139847 ps |
| T185 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_random_slow_rsp.2067070277 |
|
|
Feb 08 08:59:37 AM UTC 25 |
Feb 08 09:05:25 AM UTC 25 |
178739342576 ps |
| T521 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_stress_all.869926495 |
|
|
Feb 08 09:03:27 AM UTC 25 |
Feb 08 09:05:25 AM UTC 25 |
7644062889 ps |
| T522 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_error_and_unmapped_addr.2793146464 |
|
|
Feb 08 09:05:05 AM UTC 25 |
Feb 08 09:05:26 AM UTC 25 |
172830492 ps |
| T523 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_smoke_slow_rsp.4146679020 |
|
|
Feb 08 09:04:54 AM UTC 25 |
Feb 08 09:05:28 AM UTC 25 |
3645890189 ps |
| T524 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_random_large_delays.4080407313 |
|
|
Feb 08 09:00:32 AM UTC 25 |
Feb 08 09:05:30 AM UTC 25 |
37166677859 ps |
| T525 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_random_large_delays.3692420560 |
|
|
Feb 08 09:01:30 AM UTC 25 |
Feb 08 09:05:30 AM UTC 25 |
40006163050 ps |
| T526 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_random_zero_delays.3375957773 |
|
|
Feb 08 09:04:56 AM UTC 25 |
Feb 08 09:05:31 AM UTC 25 |
1336683488 ps |
| T527 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_random.2968304850 |
|
|
Feb 08 09:05:22 AM UTC 25 |
Feb 08 09:05:33 AM UTC 25 |
90907003 ps |
| T528 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_smoke_large_delays.4100235460 |
|
|
Feb 08 09:04:54 AM UTC 25 |
Feb 08 09:05:36 AM UTC 25 |
5281822080 ps |
| T187 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_random_slow_rsp.3083101234 |
|
|
Feb 08 09:00:48 AM UTC 25 |
Feb 08 09:05:36 AM UTC 25 |
28109765735 ps |
| T529 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_same_source.3945067340 |
|
|
Feb 08 09:05:31 AM UTC 25 |
Feb 08 09:05:38 AM UTC 25 |
99525796 ps |
| T530 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_random_large_delays.3862121253 |
|
|
Feb 08 09:02:45 AM UTC 25 |
Feb 08 09:05:40 AM UTC 25 |
39741066699 ps |
| T531 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_smoke.1732142394 |
|
|
Feb 08 09:05:41 AM UTC 25 |
Feb 08 09:05:46 AM UTC 25 |
136502468 ps |
| T532 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_access_same_device.1724779208 |
|
|
Feb 08 09:04:57 AM UTC 25 |
Feb 08 09:05:40 AM UTC 25 |
940424760 ps |
| T533 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_stress_all_with_reset_error.592050147 |
|
|
Feb 08 09:02:08 AM UTC 25 |
Feb 08 09:05:41 AM UTC 25 |
10111512407 ps |
| T534 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_access_same_device_slow_rsp.993332024 |
|
|
Feb 08 09:00:32 AM UTC 25 |
Feb 08 09:05:45 AM UTC 25 |
31775193147 ps |
| T535 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_random_zero_delays.504790234 |
|
|
Feb 08 09:05:22 AM UTC 25 |
Feb 08 09:05:47 AM UTC 25 |
376493754 ps |
| T536 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_smoke_zero_delays.2054174502 |
|
|
Feb 08 09:05:43 AM UTC 25 |
Feb 08 09:05:48 AM UTC 25 |
32594759 ps |
| T537 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_stress_all_with_rand_reset.2783603498 |
|
|
Feb 08 09:04:37 AM UTC 25 |
Feb 08 09:05:51 AM UTC 25 |
332562174 ps |
| T538 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_stress_all_with_rand_reset.2554383380 |
|
|
Feb 08 09:05:37 AM UTC 25 |
Feb 08 09:05:53 AM UTC 25 |
53432247 ps |
| T157 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_smoke_slow_rsp.580311620 |
|
|
Feb 08 09:05:22 AM UTC 25 |
Feb 08 09:05:59 AM UTC 25 |
3856413403 ps |
| T539 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_random_zero_delays.1375562020 |
|
|
Feb 08 09:05:49 AM UTC 25 |
Feb 08 09:05:59 AM UTC 25 |
36392091 ps |
| T134 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_access_same_device_slow_rsp.2556324114 |
|
|
Feb 08 08:56:52 AM UTC 25 |
Feb 08 09:06:01 AM UTC 25 |
82534928580 ps |
| T540 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_error_and_unmapped_addr.1013088330 |
|
|
Feb 08 09:05:35 AM UTC 25 |
Feb 08 09:06:01 AM UTC 25 |
216709634 ps |
| T541 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_same_source.1697121365 |
|
|
Feb 08 09:06:00 AM UTC 25 |
Feb 08 09:06:04 AM UTC 25 |
19653091 ps |
| T542 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_smoke_large_delays.3195085660 |
|
|
Feb 08 09:05:18 AM UTC 25 |
Feb 08 09:06:05 AM UTC 25 |
17722670854 ps |
| T543 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_random_slow_rsp.3507302659 |
|
|
Feb 08 09:00:32 AM UTC 25 |
Feb 08 09:06:06 AM UTC 25 |
100953605778 ps |
| T544 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_error_random.3371652947 |
|
|
Feb 08 09:05:31 AM UTC 25 |
Feb 08 09:06:06 AM UTC 25 |
5564221500 ps |
| T67 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_random_large_delays.243668413 |
|
|
Feb 08 09:05:26 AM UTC 25 |
Feb 08 09:06:06 AM UTC 25 |
12719272105 ps |
| T545 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_access_same_device.3449720201 |
|
|
Feb 08 09:05:27 AM UTC 25 |
Feb 08 09:06:08 AM UTC 25 |
1469646273 ps |
| T546 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_stress_all_with_rand_reset.310513971 |
|
|
Feb 08 08:56:57 AM UTC 25 |
Feb 08 09:06:13 AM UTC 25 |
2234288757 ps |
| T547 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_smoke.3313866490 |
|
|
Feb 08 09:06:09 AM UTC 25 |
Feb 08 09:06:14 AM UTC 25 |
457225519 ps |
| T548 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_stress_all_with_reset_error.363526845 |
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|
Feb 08 09:05:12 AM UTC 25 |
Feb 08 09:06:15 AM UTC 25 |
590386580 ps |
| T549 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_random.1232126360 |
|
|
Feb 08 09:05:47 AM UTC 25 |
Feb 08 09:06:16 AM UTC 25 |
684553477 ps |
| T550 |
/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_smoke_slow_rsp.1249731935 |
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|
Feb 08 09:05:46 AM UTC 25 |
Feb 08 09:06:17 AM UTC 25 |
3266951469 ps |