Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.02	99.26	88.89	98.80		95.88	99.26	100.00

Total test records in report: 900

T772	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_access_same_device.2332556958	Feb 08 09:10:47 AM UTC 25	Feb 08 09:12:19 AM UTC 25	2138060570 ps
T235	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_stress_all_with_rand_reset.1043113458	Feb 08 09:07:19 AM UTC 25	Feb 08 09:12:20 AM UTC 25	622998284 ps
T773	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_unmapped_addr.22525651	Feb 08 09:11:49 AM UTC 25	Feb 08 09:12:23 AM UTC 25	812559235 ps
T774	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke.2702092899	Feb 08 09:12:19 AM UTC 25	Feb 08 09:12:23 AM UTC 25	101695606 ps
T775	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_zero_delays.4023383290	Feb 08 09:12:20 AM UTC 25	Feb 08 09:12:25 AM UTC 25	104396172 ps
T776	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_random_large_delays.168645869	Feb 08 09:07:50 AM UTC 25	Feb 08 09:12:26 AM UTC 25	92264011108 ps
T777	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_access_same_device.93084837	Feb 08 09:12:07 AM UTC 25	Feb 08 09:12:27 AM UTC 25	193488206 ps
T778	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_slow_rsp.297300241	Feb 08 09:12:00 AM UTC 25	Feb 08 09:12:28 AM UTC 25	2978642295 ps
T779	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_random_zero_delays.3950858522	Feb 08 09:12:03 AM UTC 25	Feb 08 09:12:28 AM UTC 25	179743171 ps
T41	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_stress_all_with_rand_reset.204732809	Feb 08 09:06:40 AM UTC 25	Feb 08 09:12:30 AM UTC 25	16090867877 ps
T780	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_error_and_unmapped_addr.625193035	Feb 08 09:12:11 AM UTC 25	Feb 08 09:12:31 AM UTC 25	879409504 ps
T781	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_unmapped_addr.2637868284	Feb 08 09:12:11 AM UTC 25	Feb 08 09:12:32 AM UTC 25	522787643 ps
T782	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_same_source.1965872142	Feb 08 09:12:09 AM UTC 25	Feb 08 09:12:34 AM UTC 25	374155966 ps
T783	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all_with_rand_reset.2069670330	Feb 08 09:09:36 AM UTC 25	Feb 08 09:12:34 AM UTC 25	453961228 ps
T784	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_random_zero_delays.517724766	Feb 08 09:12:24 AM UTC 25	Feb 08 09:12:37 AM UTC 25	86878154 ps
T785	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all_with_rand_reset.414292906	Feb 08 09:09:06 AM UTC 25	Feb 08 09:12:38 AM UTC 25	514631046 ps
T786	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_unmapped_addr.2058036013	Feb 08 09:12:33 AM UTC 25	Feb 08 09:12:40 AM UTC 25	114030108 ps
T141	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_random_large_delays.813155675	Feb 08 09:08:11 AM UTC 25	Feb 08 09:12:42 AM UTC 25	46955799296 ps
T787	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_error_and_unmapped_addr.1409622571	Feb 08 09:12:33 AM UTC 25	Feb 08 09:12:44 AM UTC 25	103465939 ps
T788	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_large_delays.1952294436	Feb 08 09:12:00 AM UTC 25	Feb 08 09:12:44 AM UTC 25	7259822621 ps
T789	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_random.1052142803	Feb 08 09:12:24 AM UTC 25	Feb 08 09:12:46 AM UTC 25	430445923 ps
T790	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.2273940213	Feb 08 09:12:43 AM UTC 25	Feb 08 09:12:48 AM UTC 25	146515298 ps
T791	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke.1325028541	Feb 08 09:12:42 AM UTC 25	Feb 08 09:12:48 AM UTC 25	303949002 ps
T792	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_same_source.1166182193	Feb 08 09:12:29 AM UTC 25	Feb 08 09:12:51 AM UTC 25	671796565 ps
T793	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all.37786351	Feb 08 09:10:29 AM UTC 25	Feb 08 09:12:51 AM UTC 25	2038453613 ps
T794	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_random.2778177026	Feb 08 09:12:47 AM UTC 25	Feb 08 09:12:51 AM UTC 25	25310354 ps
T795	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_access_same_device_slow_rsp.705259185	Feb 08 09:09:49 AM UTC 25	Feb 08 09:12:52 AM UTC 25	40970542339 ps
T153	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_access_same_device_slow_rsp.1850534693	Feb 08 09:02:52 AM UTC 25	Feb 08 09:12:53 AM UTC 25	75234196070 ps
T796	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_large_delays.2416877572	Feb 08 09:12:22 AM UTC 25	Feb 08 09:12:53 AM UTC 25	6910320728 ps
T797	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_reset_error.3852063424	Feb 08 09:10:32 AM UTC 25	Feb 08 09:12:58 AM UTC 25	565887470 ps
T798	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_access_same_device.1280631324	Feb 08 09:12:27 AM UTC 25	Feb 08 09:13:00 AM UTC 25	495299431 ps
T799	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_random_zero_delays.3728647493	Feb 08 09:12:48 AM UTC 25	Feb 08 09:13:04 AM UTC 25	114514857 ps
T800	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all.1332941383	Feb 08 09:12:12 AM UTC 25	Feb 08 09:13:04 AM UTC 25	424044948 ps
T801	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.777955694	Feb 08 09:12:59 AM UTC 25	Feb 08 09:13:04 AM UTC 25	19823078 ps
T802	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_random_slow_rsp.207394518	Feb 08 09:11:44 AM UTC 25	Feb 08 09:13:06 AM UTC 25	20081060302 ps
T803	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_slow_rsp.3933873475	Feb 08 09:12:22 AM UTC 25	Feb 08 09:13:13 AM UTC 25	3480428733 ps
T804	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all.3313219880	Feb 08 09:12:36 AM UTC 25	Feb 08 09:13:13 AM UTC 25	1480965445 ps
T805	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.104162256	Feb 08 09:12:46 AM UTC 25	Feb 08 09:13:16 AM UTC 25	4650361262 ps
T806	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.1417486770	Feb 08 09:13:14 AM UTC 25	Feb 08 09:13:19 AM UTC 25	41954605 ps
T807	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_random_slow_rsp.2359381068	Feb 08 09:11:13 AM UTC 25	Feb 08 09:13:19 AM UTC 25	22780910269 ps
T808	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_error_random.4129247355	Feb 08 09:12:54 AM UTC 25	Feb 08 09:13:20 AM UTC 25	1499448253 ps
T809	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_error.875556	Feb 08 09:12:14 AM UTC 25	Feb 08 09:13:22 AM UTC 25	3354370192 ps
T810	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_access_same_device.3232416197	Feb 08 09:12:52 AM UTC 25	Feb 08 09:13:25 AM UTC 25	1556427755 ps
T811	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_unmapped_addr.816805837	Feb 08 09:12:55 AM UTC 25	Feb 08 09:13:26 AM UTC 25	171988144 ps
T269	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_access_same_device.3722977293	Feb 08 09:13:21 AM UTC 25	Feb 08 09:13:28 AM UTC 25	452830164 ps
T812	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_same_source.2956046139	Feb 08 09:12:54 AM UTC 25	Feb 08 09:13:29 AM UTC 25	1081635861 ps
T142	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_access_same_device_slow_rsp.3827522946	Feb 08 09:00:50 AM UTC 25	Feb 08 09:13:29 AM UTC 25	228458359004 ps
T813	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_random_large_delays.3517989712	Feb 08 09:08:51 AM UTC 25	Feb 08 09:13:36 AM UTC 25	162175843531 ps
T814	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.2731510297	Feb 08 09:12:29 AM UTC 25	Feb 08 09:13:36 AM UTC 25	9526986841 ps
T815	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_large_delays.4263399026	Feb 08 09:12:46 AM UTC 25	Feb 08 09:13:40 AM UTC 25	29015825120 ps
T816	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_error.3942467821	Feb 08 09:12:38 AM UTC 25	Feb 08 09:13:40 AM UTC 25	1150475140 ps
T817	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_unmapped_addr.2346054541	Feb 08 09:13:29 AM UTC 25	Feb 08 09:13:41 AM UTC 25	308600274 ps
T818	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.3908530992	Feb 08 09:13:30 AM UTC 25	Feb 08 09:13:42 AM UTC 25	200084464 ps
T819	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_random.3890170766	Feb 08 09:13:17 AM UTC 25	Feb 08 09:13:42 AM UTC 25	966942322 ps
T820	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all_with_rand_reset.1513913946	Feb 08 09:08:30 AM UTC 25	Feb 08 09:13:43 AM UTC 25	1520991647 ps
T143	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_access_same_device_slow_rsp.3683383550	Feb 08 09:02:23 AM UTC 25	Feb 08 09:13:44 AM UTC 25	89814248355 ps
T821	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_random_slow_rsp.54288969	Feb 08 09:10:44 AM UTC 25	Feb 08 09:13:45 AM UTC 25	27622613643 ps
T822	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_random_zero_delays.977381003	Feb 08 09:13:18 AM UTC 25	Feb 08 09:13:46 AM UTC 25	172005818 ps
T823	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_zero_delays.3581339363	Feb 08 09:13:42 AM UTC 25	Feb 08 09:13:47 AM UTC 25	65003351 ps
T824	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_random_slow_rsp.391205915	Feb 08 09:08:51 AM UTC 25	Feb 08 09:13:48 AM UTC 25	71477615387 ps
T825	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke.1418951292	Feb 08 09:13:41 AM UTC 25	Feb 08 09:13:49 AM UTC 25	950993369 ps
T826	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_error_random.1850446597	Feb 08 09:13:27 AM UTC 25	Feb 08 09:13:54 AM UTC 25	1551178806 ps
T827	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_large_delays.3916957721	Feb 08 09:13:15 AM UTC 25	Feb 08 09:13:56 AM UTC 25	16847216609 ps
T828	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_slow_rsp.3061554961	Feb 08 09:13:17 AM UTC 25	Feb 08 09:13:57 AM UTC 25	6546389406 ps
T236	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all_with_rand_reset.2569548606	Feb 08 09:07:59 AM UTC 25	Feb 08 09:13:57 AM UTC 25	1760404786 ps
T829	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_random_zero_delays.1903143391	Feb 08 09:13:46 AM UTC 25	Feb 08 09:13:59 AM UTC 25	51733966 ps
T830	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_reset_error.2405805014	Feb 08 09:12:40 AM UTC 25	Feb 08 09:14:00 AM UTC 25	214937141 ps
T831	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_random_slow_rsp.4019222997	Feb 08 09:13:48 AM UTC 25	Feb 08 09:14:03 AM UTC 25	1687729527 ps
T832	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_same_source.531037718	Feb 08 09:13:26 AM UTC 25	Feb 08 09:14:04 AM UTC 25	1607068570 ps
T833	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.3613541094	Feb 08 09:11:52 AM UTC 25	Feb 08 09:14:04 AM UTC 25	251197120 ps
T834	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_error.1549736166	Feb 08 09:14:02 AM UTC 25	Feb 08 09:14:06 AM UTC 25	65423719 ps
T835	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_same_source.2768454453	Feb 08 09:13:50 AM UTC 25	Feb 08 09:14:09 AM UTC 25	701077721 ps
T836	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_random.326851690	Feb 08 09:13:45 AM UTC 25	Feb 08 09:14:09 AM UTC 25	141456090 ps
T837	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke.776853380	Feb 08 09:14:05 AM UTC 25	Feb 08 09:14:11 AM UTC 25	116766088 ps
T838	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.1912967366	Feb 08 09:14:07 AM UTC 25	Feb 08 09:14:11 AM UTC 25	33961745 ps
T839	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_error_random.4039190208	Feb 08 09:13:56 AM UTC 25	Feb 08 09:14:11 AM UTC 25	1210034755 ps
T68	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_unmapped_addr.50063432	Feb 08 09:14:00 AM UTC 25	Feb 08 09:14:16 AM UTC 25	598917103 ps
T840	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.3888234820	Feb 08 09:14:05 AM UTC 25	Feb 08 09:14:18 AM UTC 25	75740185 ps
T841	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_random_large_delays.585780063	Feb 08 09:10:41 AM UTC 25	Feb 08 09:14:18 AM UTC 25	26701627082 ps
T842	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_random_large_delays.3152585051	Feb 08 09:11:41 AM UTC 25	Feb 08 09:14:18 AM UTC 25	38098645625 ps
T843	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_slow_rsp.2718716573	Feb 08 09:13:45 AM UTC 25	Feb 08 09:14:19 AM UTC 25	3746897921 ps
T844	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.1915483245	Feb 08 09:14:00 AM UTC 25	Feb 08 09:14:20 AM UTC 25	238998686 ps
T845	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_random_zero_delays.2016255121	Feb 08 09:14:13 AM UTC 25	Feb 08 09:14:20 AM UTC 25	40085114 ps
T155	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all_with_rand_reset.1708971348	Feb 08 09:10:02 AM UTC 25	Feb 08 09:14:21 AM UTC 25	3552423651 ps
T846	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_large_delays.1567543955	Feb 08 09:13:42 AM UTC 25	Feb 08 09:14:21 AM UTC 25	6403687494 ps
T847	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all.1552251991	Feb 08 09:14:00 AM UTC 25	Feb 08 09:14:22 AM UTC 25	170792121 ps
T301	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_access_same_device_slow_rsp.2694289933	Feb 08 09:13:24 AM UTC 25	Feb 08 09:14:24 AM UTC 25	5763824340 ps
T848	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_random.2773861064	Feb 08 09:14:11 AM UTC 25	Feb 08 09:14:25 AM UTC 25	190321757 ps
T849	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_error_random.1199947980	Feb 08 09:14:20 AM UTC 25	Feb 08 09:14:27 AM UTC 25	40184390 ps
T850	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_random_large_delays.739949636	Feb 08 09:13:46 AM UTC 25	Feb 08 09:14:27 AM UTC 25	7403933689 ps
T851	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_unmapped_addr.889679455	Feb 08 09:14:23 AM UTC 25	Feb 08 09:14:31 AM UTC 25	532072212 ps
T156	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all.328951867	Feb 08 09:13:30 AM UTC 25	Feb 08 09:14:38 AM UTC 25	2391705012 ps
T852	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_access_same_device.1827705367	Feb 08 09:13:48 AM UTC 25	Feb 08 09:14:39 AM UTC 25	669826158 ps
T853	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_rand_reset.3214225715	Feb 08 09:11:00 AM UTC 25	Feb 08 09:14:39 AM UTC 25	573796696 ps
T854	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_large_delays.2047905459	Feb 08 09:14:07 AM UTC 25	Feb 08 09:14:42 AM UTC 25	5008639785 ps
T855	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all.2453610603	Feb 08 09:13:01 AM UTC 25	Feb 08 09:14:42 AM UTC 25	3116127916 ps
T856	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_random_large_delays.1724560001	Feb 08 09:09:46 AM UTC 25	Feb 08 09:14:47 AM UTC 25	43533523989 ps
T857	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_same_source.3840710947	Feb 08 09:14:20 AM UTC 25	Feb 08 09:14:47 AM UTC 25	1269727994 ps
T858	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.1805468058	Feb 08 09:14:23 AM UTC 25	Feb 08 09:14:48 AM UTC 25	789588800 ps
T859	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.2040742671	Feb 08 09:14:11 AM UTC 25	Feb 08 09:14:51 AM UTC 25	6526195204 ps
T860	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_error.916120669	Feb 08 09:11:31 AM UTC 25	Feb 08 09:14:53 AM UTC 25	7980519493 ps
T861	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_random_slow_rsp.4030066787	Feb 08 09:12:52 AM UTC 25	Feb 08 09:14:56 AM UTC 25	12131027471 ps
T862	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.3091390584	Feb 08 09:14:02 AM UTC 25	Feb 08 09:14:56 AM UTC 25	49337448 ps
T863	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all.3514450736	Feb 08 09:10:58 AM UTC 25	Feb 08 09:14:59 AM UTC 25	9873535404 ps
T864	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_reset_error.1480043873	Feb 08 09:13:41 AM UTC 25	Feb 08 09:15:00 AM UTC 25	143949143 ps
T865	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.4275633705	Feb 08 09:14:23 AM UTC 25	Feb 08 09:15:02 AM UTC 25	108741507 ps
T866	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_error.1800876335	Feb 08 09:13:06 AM UTC 25	Feb 08 09:15:05 AM UTC 25	5504071918 ps
T867	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all_with_reset_error.3515646833	Feb 08 09:10:04 AM UTC 25	Feb 08 09:15:08 AM UTC 25	3335511192 ps
T868	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_access_same_device.127568508	Feb 08 09:14:17 AM UTC 25	Feb 08 09:15:22 AM UTC 25	2395782156 ps
T869	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_random_slow_rsp.500772909	Feb 08 09:14:13 AM UTC 25	Feb 08 09:15:29 AM UTC 25	9501632427 ps
T870	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_random_large_delays.4210773314	Feb 08 09:10:14 AM UTC 25	Feb 08 09:15:34 AM UTC 25	91821691230 ps
T231	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_random_large_delays.3604701926	Feb 08 09:12:26 AM UTC 25	Feb 08 09:15:34 AM UTC 25	29339713049 ps
T871	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_reset_error.1161807144	Feb 08 09:13:06 AM UTC 25	Feb 08 09:15:43 AM UTC 25	2020618616 ps
T872	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all.536886553	Feb 08 09:11:26 AM UTC 25	Feb 08 09:15:46 AM UTC 25	13401100355 ps
T164	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.946234669	Feb 08 09:11:46 AM UTC 25	Feb 08 09:15:57 AM UTC 25	22737633303 ps
T873	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_reset_error.77710066	Feb 08 09:14:26 AM UTC 25	Feb 08 09:15:59 AM UTC 25	2431698469 ps
T874	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_random_large_delays.1154410482	Feb 08 09:12:04 AM UTC 25	Feb 08 09:16:00 AM UTC 25	30418072034 ps
T165	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_random_slow_rsp.3265549978	Feb 08 09:13:20 AM UTC 25	Feb 08 09:16:02 AM UTC 25	31005405906 ps
T875	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_random_slow_rsp.1564255050	Feb 08 09:12:04 AM UTC 25	Feb 08 09:16:05 AM UTC 25	33588899561 ps
T69	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all.3426223756	Feb 08 09:14:23 AM UTC 25	Feb 08 09:16:05 AM UTC 25	2491530441 ps
T876	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_random_slow_rsp.3575282089	Feb 08 09:12:27 AM UTC 25	Feb 08 09:16:07 AM UTC 25	22470389788 ps
T877	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_random_large_delays.3350197067	Feb 08 09:11:12 AM UTC 25	Feb 08 09:16:10 AM UTC 25	153365573559 ps
T878	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_access_same_device_slow_rsp.4084691054	Feb 08 09:10:49 AM UTC 25	Feb 08 09:16:12 AM UTC 25	30870865892 ps
T879	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_error.3137653591	Feb 08 09:13:37 AM UTC 25	Feb 08 09:16:17 AM UTC 25	5592077322 ps
T880	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_random_large_delays.858027999	Feb 08 09:13:20 AM UTC 25	Feb 08 09:16:23 AM UTC 25	96659182961 ps
T881	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_access_same_device_slow_rsp.3781556574	Feb 08 09:07:14 AM UTC 25	Feb 08 09:16:27 AM UTC 25	64724390493 ps
T882	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_error.43672094	Feb 08 09:14:26 AM UTC 25	Feb 08 09:16:50 AM UTC 25	11516405735 ps
T883	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_access_same_device_slow_rsp.1382108647	Feb 08 09:08:15 AM UTC 25	Feb 08 09:16:51 AM UTC 25	157923113157 ps
T884	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_random_large_delays.1496814146	Feb 08 09:14:13 AM UTC 25	Feb 08 09:16:53 AM UTC 25	17711284156 ps
T885	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.2289103810	Feb 08 09:11:56 AM UTC 25	Feb 08 09:16:53 AM UTC 25	3166293143 ps
T886	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_random_large_delays.1923662464	Feb 08 09:12:50 AM UTC 25	Feb 08 09:16:53 AM UTC 25	126762423768 ps
T42	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.186186559	Feb 08 09:12:36 AM UTC 25	Feb 08 09:17:14 AM UTC 25	799666376 ps
T166	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_access_same_device_slow_rsp.2171516204	Feb 08 09:07:31 AM UTC 25	Feb 08 09:17:39 AM UTC 25	178033894734 ps
T887	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_reset_error.2569421123	Feb 08 09:11:02 AM UTC 25	Feb 08 09:17:42 AM UTC 25	9926707105 ps
T888	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_access_same_device_slow_rsp.2039596304	Feb 08 09:04:58 AM UTC 25	Feb 08 09:18:17 AM UTC 25	134785432872 ps
T167	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.4155341270	Feb 08 09:12:54 AM UTC 25	Feb 08 09:18:30 AM UTC 25	33087027012 ps
T252	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all.451317557	Feb 08 09:11:52 AM UTC 25	Feb 08 09:18:42 AM UTC 25	74165696302 ps
T889	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_rand_reset.3118037719	Feb 08 09:13:06 AM UTC 25	Feb 08 09:18:47 AM UTC 25	1081318569 ps
T890	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_rand_reset.3059440153	Feb 08 09:12:14 AM UTC 25	Feb 08 09:19:27 AM UTC 25	5687903847 ps
T891	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.2960833782	Feb 08 09:12:17 AM UTC 25	Feb 08 09:19:37 AM UTC 25	8274774462 ps
T292	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.2750573517	Feb 08 09:11:19 AM UTC 25	Feb 08 09:19:53 AM UTC 25	70553471411 ps
T892	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_access_same_device_slow_rsp.4210683418	Feb 08 09:05:29 AM UTC 25	Feb 08 09:20:11 AM UTC 25	155722159895 ps
T893	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_access_same_device_slow_rsp.3651682008	Feb 08 09:08:55 AM UTC 25	Feb 08 09:20:56 AM UTC 25	90720894287 ps
T894	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.4089031287	Feb 08 09:13:37 AM UTC 25	Feb 08 09:20:59 AM UTC 25	6294307332 ps
T895	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.4011571375	Feb 08 09:13:48 AM UTC 25	Feb 08 09:21:13 AM UTC 25	59067938494 ps
T896	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.3531731291	Feb 08 09:14:20 AM UTC 25	Feb 08 09:21:44 AM UTC 25	44116739156 ps
T897	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_reset_error.1388184185	Feb 08 09:11:33 AM UTC 25	Feb 08 09:22:19 AM UTC 25	13473430617 ps
T898	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.200500400	Feb 08 09:12:09 AM UTC 25	Feb 08 09:22:51 AM UTC 25	70032710579 ps
T899	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_access_same_device_slow_rsp.797872557	Feb 08 09:10:17 AM UTC 25	Feb 08 09:23:18 AM UTC 25	88890423890 ps
T900	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.3257334621	Feb 08 09:09:28 AM UTC 25	Feb 08 09:25:16 AM UTC 25	74020600687 ps

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_random.4033536255
Short name	T11
Test name
Test status
Simulation time	2114970480 ps
CPU time	13.99 seconds
Started	Feb 08 08:52:27 AM UTC 25
Finished	Feb 08 08:52:44 AM UTC 25
Peak memory	216748 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4033536255 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_buil d_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random.4033536255
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/0.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_access_same_device_slow_rsp.3399113528
Short name	T309
Test name
Test status
Simulation time	54716499868 ps
CPU time	415.52 seconds
Started	Feb 08 08:52:30 AM UTC 25
Finished	Feb 08 08:59:31 AM UTC 25
Peak memory	220852 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3399113528 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/ coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device_slow_rsp.3399113528
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/0.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_access_same_device_slow_rsp.781127596
Short name	T268
Test name
Test status
Simulation time	41926793745 ps
CPU time	389.56 seconds
Started	Feb 08 08:53:46 AM UTC 25
Finished	Feb 08 09:00:21 AM UTC 25
Peak memory	219312 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=781127596 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST _SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/c overage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device_slow_rsp.781127596
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/4.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_access_same_device.426819259
Short name	T76
Test name
Test status
Simulation time	1190127098 ps
CPU time	42.75 seconds
Started	Feb 08 08:53:26 AM UTC 25
Finished	Feb 08 08:54:10 AM UTC 25
Peak memory	218872 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=426819259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverag e/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device.426819259
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/3.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_access_same_device_slow_rsp.2354042424
Short name	T133
Test name
Test status
Simulation time	75555332301 ps
CPU time	617.69 seconds
Started	Feb 08 08:54:08 AM UTC 25
Finished	Feb 08 09:04:33 AM UTC 25
Peak memory	222924 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2354042424 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/ coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device_slow_rsp.2354042424
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/5.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_stress_all_with_error.893166922
Short name	T22
Test name
Test status
Simulation time	2753405958 ps
CPU time	47.89 seconds
Started	Feb 08 08:52:33 AM UTC 25
Finished	Feb 08 08:53:24 AM UTC 25
Peak memory	218928 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=893166922 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ= xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.893166922
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/0.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_access_same_device.1533884214
Short name	T84
Test name
Test status
Simulation time	1732780141 ps
CPU time	60.38 seconds
Started	Feb 08 08:55:53 AM UTC 25
Finished	Feb 08 08:56:56 AM UTC 25
Peak memory	216804 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1533884214 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/covera ge/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device.1533884214
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/9.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_access_same_device.3595923058
Short name	T73
Test name
Test status
Simulation time	5333430169 ps
CPU time	46.19 seconds
Started	Feb 08 08:52:48 AM UTC 25
Finished	Feb 08 08:53:36 AM UTC 25
Peak memory	218892 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3595923058 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/covera ge/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device.3595923058
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/1.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_access_same_device.918172368
Short name	T99
Test name
Test status
Simulation time	2390154016 ps
CPU time	63.1 seconds
Started	Feb 08 08:57:10 AM UTC 25
Finished	Feb 08 08:58:15 AM UTC 25
Peak memory	219244 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=918172368 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverag e/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device.918172368
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/12.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_error_and_unmapped_addr.969619111
Short name	T27
Test name
Test status
Simulation time	75115127 ps
CPU time	7.66 seconds
Started	Feb 08 08:52:58 AM UTC 25
Finished	Feb 08 08:53:07 AM UTC 25
Peak memory	217068 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=969619111 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ= xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xb ar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr.969619111
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/1.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_access_same_device_slow_rsp.2710228404
Short name	T315
Test name
Test status
Simulation time	31081630292 ps
CPU time	282.43 seconds
Started	Feb 08 08:55:23 AM UTC 25
Finished	Feb 08 09:00:10 AM UTC 25
Peak memory	218868 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2710228404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/ coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device_slow_rsp.2710228404
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/8.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_smoke_large_delays.3827385167
Short name	T29
Test name
Test status
Simulation time	14291658735 ps
CPU time	42.51 seconds
Started	Feb 08 08:52:25 AM UTC 25
Finished	Feb 08 08:53:10 AM UTC 25
Peak memory	216860 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3827385167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/ xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.3827385167
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/0.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_stress_all_with_rand_reset.2974892585
Short name	T36
Test name
Test status
Simulation time	171863407 ps
CPU time	64.35 seconds
Started	Feb 08 08:52:59 AM UTC 25
Finished	Feb 08 08:54:06 AM UTC 25
Peak memory	218856 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2974892585 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_rand_reset.2974892585
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/1.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_access_same_device.3013983452
Short name	T75
Test name
Test status
Simulation time	2374991941 ps
CPU time	49.94 seconds
Started	Feb 08 08:53:09 AM UTC 25
Finished	Feb 08 08:54:01 AM UTC 25
Peak memory	219176 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3013983452 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/covera ge/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device.3013983452
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/2.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_stress_all_with_reset_error.3385823347
Short name	T331
Test name
Test status
Simulation time	700772034 ps
CPU time	298.38 seconds
Started	Feb 08 08:57:50 AM UTC 25
Finished	Feb 08 09:02:53 AM UTC 25
Peak memory	233560 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3385823347 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_reset_error.3385823347
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/13.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_error_and_unmapped_addr.419967536
Short name	T14
Test name
Test status
Simulation time	995346747 ps
CPU time	29.71 seconds
Started	Feb 08 08:52:30 AM UTC 25
Finished	Feb 08 08:53:02 AM UTC 25
Peak memory	216800 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=419967536 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ= xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xb ar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr.419967536
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/0.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_stress_all_with_reset_error.606248849
Short name	T329
Test name
Test status
Simulation time	2400230614 ps
CPU time	131.88 seconds
Started	Feb 08 08:58:54 AM UTC 25
Finished	Feb 08 09:01:08 AM UTC 25
Peak memory	220968 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=606248849 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ= xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_reset_error.606248849
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/15.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_stress_all.1561812462
Short name	T128
Test name
Test status
Simulation time	8269167676 ps
CPU time	185.55 seconds
Started	Feb 08 08:58:47 AM UTC 25
Finished	Feb 08 09:01:56 AM UTC 25
Peak memory	223020 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1561812462 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.1561812462
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/15.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_stress_all_with_reset_error.2397393825
Short name	T39
Test name
Test status
Simulation time	576180441 ps
CPU time	221.52 seconds
Started	Feb 08 08:52:33 AM UTC 25
Finished	Feb 08 08:56:19 AM UTC 25
Peak memory	233824 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2397393825 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_reset_error.2397393825
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/0.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_random_slow_rsp.3337134037
Short name	T97
Test name
Test status
Simulation time	11978738115 ps
CPU time	112.31 seconds
Started	Feb 08 08:52:44 AM UTC 25
Finished	Feb 08 08:54:39 AM UTC 25
Peak memory	217136 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3337134037 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xba r_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.3337134037
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/1.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_stress_all_with_rand_reset.204732809
Short name	T41
Test name
Test status
Simulation time	16090867877 ps
CPU time	345.04 seconds
Started	Feb 08 09:06:40 AM UTC 25
Finished	Feb 08 09:12:30 AM UTC 25
Peak memory	223016 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=204732809 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs /coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_rand_reset.204732809
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/31.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_stress_all_with_rand_reset.538629359
Short name	T35
Test name
Test status
Simulation time	2858317341 ps
CPU time	275.69 seconds
Started	Feb 08 08:56:08 AM UTC 25
Finished	Feb 08 09:00:48 AM UTC 25
Peak memory	223024 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=538629359 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs /coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_rand_reset.538629359
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/9.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_stress_all_with_rand_reset.206929558
Short name	T498
Test name
Test status
Simulation time	15394775750 ps
CPU time	722.51 seconds
Started	Feb 08 08:52:32 AM UTC 25
Finished	Feb 08 09:04:44 AM UTC 25
Peak memory	237240 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=206929558 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs /coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_rand_reset.206929558
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/0.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_stress_all_with_reset_error.2813613884
Short name	T43
Test name
Test status
Simulation time	2628042001 ps
CPU time	245.33 seconds
Started	Feb 08 09:07:21 AM UTC 25
Finished	Feb 08 09:11:30 AM UTC 25
Peak memory	223516 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2813613884 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_reset_error.2813613884
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/33.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_stress_all_with_reset_error.361662092
Short name	T40
Test name
Test status
Simulation time	1013775127 ps
CPU time	303.3 seconds
Started	Feb 08 08:53:02 AM UTC 25
Finished	Feb 08 08:58:10 AM UTC 25
Peak memory	233536 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=361662092 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ= xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_reset_error.361662092
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/1.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_random.2532956174
Short name	T4
Test name
Test status
Simulation time	798804531 ps
CPU time	31.19 seconds
Started	Feb 08 08:53:06 AM UTC 25
Finished	Feb 08 08:53:39 AM UTC 25
Peak memory	217004 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2532956174 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_buil d_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random.2532956174
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/2.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_stress_all.3038665356
Short name	T129
Test name
Test status
Simulation time	3822358975 ps
CPU time	139.04 seconds
Started	Feb 08 08:59:48 AM UTC 25
Finished	Feb 08 09:02:10 AM UTC 25
Peak memory	218924 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3038665356 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.3038665356
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/17.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_access_same_device.635661562
Short name	T8
Test name
Test status
Simulation time	80504729 ps
CPU time	8.97 seconds
Started	Feb 08 08:52:27 AM UTC 25
Finished	Feb 08 08:52:39 AM UTC 25
Peak memory	217056 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=635661562 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverag e/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device.635661562
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/0.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_error_random.230156793
Short name	T3
Test name
Test status
Simulation time	88123268 ps
CPU time	3.07 seconds
Started	Feb 08 08:52:30 AM UTC 25
Finished	Feb 08 08:52:34 AM UTC 25
Peak memory	215928 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=230156793 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ= xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_buil d_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.230156793
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/0.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_random_large_delays.786090905
Short name	T258
Test name
Test status
Simulation time	30567854635 ps
CPU time	115.76 seconds
Started	Feb 08 08:52:27 AM UTC 25
Finished	Feb 08 08:54:27 AM UTC 25
Peak memory	216852 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=786090905 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/ xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.786090905
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/0.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_random_slow_rsp.2809691274
Short name	T50
Test name
Test status
Simulation time	7499573908 ps
CPU time	64.93 seconds
Started	Feb 08 08:52:27 AM UTC 25
Finished	Feb 08 08:53:35 AM UTC 25
Peak memory	216880 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2809691274 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xba r_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.2809691274
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/0.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_random_zero_delays.1402306000
Short name	T12
Test name
Test status
Simulation time	210505547 ps
CPU time	23.38 seconds
Started	Feb 08 08:52:27 AM UTC 25
Finished	Feb 08 08:52:53 AM UTC 25
Peak memory	216680 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1402306000 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/cov erage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_delays.1402306000
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/0.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_same_source.2631984746
Short name	T17
Test name
Test status
Simulation time	2214750206 ps
CPU time	35.4 seconds
Started	Feb 08 08:52:30 AM UTC 25
Finished	Feb 08 08:53:07 AM UTC 25
Peak memory	216876 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2631984746 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.2631984746
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/0.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_smoke.3887718867
Short name	T2
Test name
Test status
Simulation time	153468552 ps
CPU time	4.59 seconds
Started	Feb 08 08:52:25 AM UTC 25
Finished	Feb 08 08:52:31 AM UTC 25
Peak memory	216792 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3887718867 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build _mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.3887718867
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/0.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_smoke_slow_rsp.2712425660
Short name	T72
Test name
Test status
Simulation time	24483805656 ps
CPU time	59.57 seconds
Started	Feb 08 08:52:27 AM UTC 25
Finished	Feb 08 08:53:30 AM UTC 25
Peak memory	216792 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2712425660 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.2712425660
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/0.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_smoke_zero_delays.3177253037
Short name	T1
Test name
Test status
Simulation time	35699982 ps
CPU time	2.3 seconds
Started	Feb 08 08:52:25 AM UTC 25
Finished	Feb 08 08:52:29 AM UTC 25
Peak memory	216852 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3177253037 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/cove rage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays.3177253037
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/0.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_stress_all.98571406
Short name	T7
Test name
Test status
Simulation time	190999701 ps
CPU time	5.84 seconds
Started	Feb 08 08:52:32 AM UTC 25
Finished	Feb 08 08:52:39 AM UTC 25
Peak memory	216788 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=98571406 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xb ar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_bu ild_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.98571406
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/0.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_unmapped_addr.186539294
Short name	T16
Test name
Test status
Simulation time	768881537 ps
CPU time	35.2 seconds
Started	Feb 08 08:52:30 AM UTC 25
Finished	Feb 08 08:53:07 AM UTC 25
Peak memory	215908 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=186539294 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xba r_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.186539294
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/0.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_access_same_device_slow_rsp.111856822
Short name	T208
Test name
Test status
Simulation time	170052875761 ps
CPU time	608.79 seconds
Started	Feb 08 08:52:48 AM UTC 25
Finished	Feb 08 09:03:04 AM UTC 25
Peak memory	222516 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=111856822 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST _SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/c overage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device_slow_rsp.111856822
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/1.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_error_random.2202937288
Short name	T13
Test name
Test status
Simulation time	51841007 ps
CPU time	3.12 seconds
Started	Feb 08 08:52:54 AM UTC 25
Finished	Feb 08 08:52:58 AM UTC 25
Peak memory	217068 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2202937288 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_bui ld_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.2202937288
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/1.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_random.1331491665
Short name	T21
Test name
Test status
Simulation time	1298350506 ps
CPU time	38.95 seconds
Started	Feb 08 08:52:40 AM UTC 25
Finished	Feb 08 08:53:21 AM UTC 25
Peak memory	216784 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1331491665 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_buil d_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random.1331491665
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/1.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_random_large_delays.3465686591
Short name	T115
Test name
Test status
Simulation time	44991221701 ps
CPU time	251.28 seconds
Started	Feb 08 08:52:41 AM UTC 25
Finished	Feb 08 08:56:57 AM UTC 25
Peak memory	218928 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3465686591 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage /xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.3465686591
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/1.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_random_zero_delays.512484689
Short name	T15
Test name
Test status
Simulation time	159366433 ps
CPU time	22.26 seconds
Started	Feb 08 08:52:41 AM UTC 25
Finished	Feb 08 08:53:06 AM UTC 25
Peak memory	217064 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=512484689 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/cove rage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_delays.512484689
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/1.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_same_source.3116920515
Short name	T18
Test name
Test status
Simulation time	382013743 ps
CPU time	19.08 seconds
Started	Feb 08 08:52:51 AM UTC 25
Finished	Feb 08 08:53:11 AM UTC 25
Peak memory	216816 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3116920515 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.3116920515
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/1.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_smoke.2841910198
Short name	T10
Test name
Test status
Simulation time	141161175 ps
CPU time	3.23 seconds
Started	Feb 08 08:52:35 AM UTC 25
Finished	Feb 08 08:52:41 AM UTC 25
Peak memory	216852 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2841910198 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build _mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.2841910198
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/1.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_smoke_large_delays.3772016562
Short name	T31
Test name
Test status
Simulation time	5196400430 ps
CPU time	37.01 seconds
Started	Feb 08 08:52:37 AM UTC 25
Finished	Feb 08 08:53:16 AM UTC 25
Peak memory	216796 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3772016562 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/ xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.3772016562
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/1.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_smoke_slow_rsp.660501283
Short name	T25
Test name
Test status
Simulation time	2335256031 ps
CPU time	22.26 seconds
Started	Feb 08 08:52:40 AM UTC 25
Finished	Feb 08 08:53:04 AM UTC 25
Peak memory	217084 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=660501283 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST _SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.660501283
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/1.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_smoke_zero_delays.1912296452
Short name	T9
Test name
Test status
Simulation time	35822287 ps
CPU time	3.07 seconds
Started	Feb 08 08:52:36 AM UTC 25
Finished	Feb 08 08:52:40 AM UTC 25
Peak memory	216788 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1912296452 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/cove rage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays.1912296452
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/1.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_stress_all.2014896422
Short name	T232
Test name
Test status
Simulation time	1150141317 ps
CPU time	171.58 seconds
Started	Feb 08 08:52:59 AM UTC 25
Finished	Feb 08 08:55:54 AM UTC 25
Peak memory	222956 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2014896422 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.2014896422
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/1.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_stress_all_with_error.1642359955
Short name	T311
Test name
Test status
Simulation time	18511054194 ps
CPU time	267.94 seconds
Started	Feb 08 08:53:02 AM UTC 25
Finished	Feb 08 08:57:34 AM UTC 25
Peak memory	221004 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1642359955 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.1642359955
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/1.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_unmapped_addr.4117639305
Short name	T30
Test name
Test status
Simulation time	419111429 ps
CPU time	16.15 seconds
Started	Feb 08 08:52:55 AM UTC 25
Finished	Feb 08 08:53:13 AM UTC 25
Peak memory	216816 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4117639305 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xb ar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.4117639305
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/1.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_access_same_device.3243542017
Short name	T289
Test name
Test status
Simulation time	863650516 ps
CPU time	20.34 seconds
Started	Feb 08 08:56:22 AM UTC 25
Finished	Feb 08 08:56:44 AM UTC 25
Peak memory	216708 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3243542017 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/covera ge/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device.3243542017
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/10.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_access_same_device_slow_rsp.3207575875
Short name	T320
Test name
Test status
Simulation time	44959327170 ps
CPU time	269.35 seconds
Started	Feb 08 08:56:23 AM UTC 25
Finished	Feb 08 09:00:57 AM UTC 25
Peak memory	218868 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3207575875 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/ coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device_slow_rsp.3207575875
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/10.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_error_and_unmapped_addr.3284057990
Short name	T355
Test name
Test status
Simulation time	48582597 ps
CPU time	2.68 seconds
Started	Feb 08 08:56:31 AM UTC 25
Finished	Feb 08 08:56:35 AM UTC 25
Peak memory	217064 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3284057990 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/x bar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_addr.3284057990
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/10.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_error_random.3088161720
Short name	T352
Test name
Test status
Simulation time	55812214 ps
CPU time	6.11 seconds
Started	Feb 08 08:56:24 AM UTC 25
Finished	Feb 08 08:56:32 AM UTC 25
Peak memory	217056 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3088161720 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_bui ld_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.3088161720
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/10.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_random.442117961
Short name	T83
Test name
Test status
Simulation time	1682145353 ps
CPU time	38.22 seconds
Started	Feb 08 08:56:14 AM UTC 25
Finished	Feb 08 08:56:54 AM UTC 25
Peak memory	216744 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=442117961 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build _mode.vdb -cm_log /dev/null -cm_name 10.xbar_random.442117961
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/10.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_random_large_delays.3985061408
Short name	T54
Test name
Test status
Simulation time	12262973665 ps
CPU time	86.13 seconds
Started	Feb 08 08:56:19 AM UTC 25
Finished	Feb 08 08:57:48 AM UTC 25
Peak memory	216876 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3985061408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage /xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.3985061408
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/10.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_random_slow_rsp.1149795594
Short name	T446
Test name
Test status
Simulation time	173026332579 ps
CPU time	373.58 seconds
Started	Feb 08 08:56:22 AM UTC 25
Finished	Feb 08 09:02:41 AM UTC 25
Peak memory	218916 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1149795594 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xba r_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.1149795594
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/10.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_random_zero_delays.4122073544
Short name	T353
Test name
Test status
Simulation time	187998115 ps
CPU time	12.23 seconds
Started	Feb 08 08:56:18 AM UTC 25
Finished	Feb 08 08:56:32 AM UTC 25
Peak memory	216744 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4122073544 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/cov erage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_delays.4122073544
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/10.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_same_source.2341439158
Short name	T283
Test name
Test status
Simulation time	2865600411 ps
CPU time	25.67 seconds
Started	Feb 08 08:56:24 AM UTC 25
Finished	Feb 08 08:56:52 AM UTC 25
Peak memory	217132 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2341439158 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.2341439158
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/10.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_smoke.196242777
Short name	T6
Test name
Test status
Simulation time	169565200 ps
CPU time	5.4 seconds
Started	Feb 08 08:56:12 AM UTC 25
Finished	Feb 08 08:56:19 AM UTC 25
Peak memory	217048 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=196242777 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_ mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.196242777
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/10.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_smoke_large_delays.3111767143
Short name	T120
Test name
Test status
Simulation time	6981188805 ps
CPU time	47.24 seconds
Started	Feb 08 08:56:13 AM UTC 25
Finished	Feb 08 08:57:02 AM UTC 25
Peak memory	216864 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3111767143 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/ xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.3111767143
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/10.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_smoke_slow_rsp.1064507879
Short name	T284
Test name
Test status
Simulation time	6111208623 ps
CPU time	38.36 seconds
Started	Feb 08 08:56:13 AM UTC 25
Finished	Feb 08 08:56:53 AM UTC 25
Peak memory	216856 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1064507879 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.1064507879
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/10.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_smoke_zero_delays.3983399725
Short name	T182
Test name
Test status
Simulation time	47070184 ps
CPU time	2.76 seconds
Started	Feb 08 08:56:13 AM UTC 25
Finished	Feb 08 08:56:17 AM UTC 25
Peak memory	216788 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3983399725 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/cove rage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delays.3983399725
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/10.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_stress_all.2463180250
Short name	T47
Test name
Test status
Simulation time	5357006631 ps
CPU time	51.41 seconds
Started	Feb 08 08:56:33 AM UTC 25
Finished	Feb 08 08:57:26 AM UTC 25
Peak memory	219244 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2463180250 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.2463180250
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/10.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_stress_all_with_error.2054134457
Short name	T306
Test name
Test status
Simulation time	3788059124 ps
CPU time	73.84 seconds
Started	Feb 08 08:56:33 AM UTC 25
Finished	Feb 08 08:57:49 AM UTC 25
Peak memory	218920 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2054134457 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.2054134457
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/10.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_stress_all_with_rand_reset.3650374958
Short name	T497
Test name
Test status
Simulation time	8132824639 ps
CPU time	476.53 seconds
Started	Feb 08 08:56:33 AM UTC 25
Finished	Feb 08 09:04:36 AM UTC 25
Peak memory	233568 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3650374958 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_rand_reset.3650374958
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/10.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_stress_all_with_reset_error.2121980467
Short name	T326
Test name
Test status
Simulation time	1234216628 ps
CPU time	222.78 seconds
Started	Feb 08 08:56:36 AM UTC 25
Finished	Feb 08 09:00:22 AM UTC 25
Peak memory	223580 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2121980467 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_reset_error.2121980467
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/10.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_unmapped_addr.3489475492
Short name	T82
Test name
Test status
Simulation time	903397190 ps
CPU time	20.33 seconds
Started	Feb 08 08:56:29 AM UTC 25
Finished	Feb 08 08:56:51 AM UTC 25
Peak memory	216808 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3489475492 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xb ar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.3489475492
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/10.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_access_same_device.306403379
Short name	T257
Test name
Test status
Simulation time	2272097745 ps
CPU time	15.87 seconds
Started	Feb 08 08:56:50 AM UTC 25
Finished	Feb 08 08:57:08 AM UTC 25
Peak memory	216804 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=306403379 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverag e/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device.306403379
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/11.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_access_same_device_slow_rsp.2556324114
Short name	T134
Test name
Test status
Simulation time	82534928580 ps
CPU time	542.62 seconds
Started	Feb 08 08:56:52 AM UTC 25
Finished	Feb 08 09:06:01 AM UTC 25
Peak memory	220552 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2556324114 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/ coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device_slow_rsp.2556324114
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/11.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_error_and_unmapped_addr.2868300139
Short name	T122
Test name
Test status
Simulation time	142353771 ps
CPU time	8.87 seconds
Started	Feb 08 08:56:55 AM UTC 25
Finished	Feb 08 08:57:05 AM UTC 25
Peak memory	216744 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2868300139 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/x bar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_addr.2868300139
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/11.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_error_random.840454175
Short name	T118
Test name
Test status
Simulation time	48228652 ps
CPU time	4.52 seconds
Started	Feb 08 08:56:55 AM UTC 25
Finished	Feb 08 08:57:01 AM UTC 25
Peak memory	216804 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=840454175 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ= xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_buil d_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.840454175
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/11.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_random.3096698007
Short name	T225
Test name
Test status
Simulation time	278608902 ps
CPU time	29.28 seconds
Started	Feb 08 08:56:44 AM UTC 25
Finished	Feb 08 08:57:15 AM UTC 25
Peak memory	217076 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3096698007 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_buil d_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random.3096698007
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/11.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_random_large_delays.3365878149
Short name	T124
Test name
Test status
Simulation time	57338677760 ps
CPU time	226.39 seconds
Started	Feb 08 08:56:46 AM UTC 25
Finished	Feb 08 09:00:36 AM UTC 25
Peak memory	216880 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3365878149 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage /xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.3365878149
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/11.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_random_slow_rsp.1726506914
Short name	T240
Test name
Test status
Simulation time	29802129546 ps
CPU time	119.62 seconds
Started	Feb 08 08:56:50 AM UTC 25
Finished	Feb 08 08:58:53 AM UTC 25
Peak memory	216880 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1726506914 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xba r_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.1726506914
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/11.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_random_zero_delays.2316918721
Short name	T117
Test name
Test status
Simulation time	287392958 ps
CPU time	13.83 seconds
Started	Feb 08 08:56:45 AM UTC 25
Finished	Feb 08 08:57:01 AM UTC 25
Peak memory	216808 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2316918721 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/cov erage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_delays.2316918721
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/11.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_same_source.3640565004
Short name	T119
Test name
Test status
Simulation time	472778380 ps
CPU time	7.74 seconds
Started	Feb 08 08:56:53 AM UTC 25
Finished	Feb 08 08:57:02 AM UTC 25
Peak memory	216748 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3640565004 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.3640565004
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/11.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_smoke.1689913138
Short name	T287
Test name
Test status
Simulation time	41136926 ps
CPU time	3.33 seconds
Started	Feb 08 08:56:37 AM UTC 25
Finished	Feb 08 08:56:42 AM UTC 25
Peak memory	216728 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1689913138 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build _mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.1689913138
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/11.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_smoke_large_delays.2891181848
Short name	T360
Test name
Test status
Simulation time	6070376989 ps
CPU time	53.56 seconds
Started	Feb 08 08:56:41 AM UTC 25
Finished	Feb 08 08:57:36 AM UTC 25
Peak memory	216860 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2891181848 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/ xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.2891181848
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/11.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_smoke_slow_rsp.440862283
Short name	T358
Test name
Test status
Simulation time	7110642541 ps
CPU time	29.2 seconds
Started	Feb 08 08:56:42 AM UTC 25
Finished	Feb 08 08:57:13 AM UTC 25
Peak memory	216860 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=440862283 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST _SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.440862283
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/11.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_smoke_zero_delays.571356196
Short name	T288
Test name
Test status
Simulation time	70459454 ps
CPU time	3.65 seconds
Started	Feb 08 08:56:38 AM UTC 25
Finished	Feb 08 08:56:43 AM UTC 25
Peak memory	216724 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=571356196 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/cover age/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delays.571356196
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/11.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_stress_all.4040479281
Short name	T86
Test name
Test status
Simulation time	1262174532 ps
CPU time	51.33 seconds
Started	Feb 08 08:56:56 AM UTC 25
Finished	Feb 08 08:57:49 AM UTC 25
Peak memory	216812 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4040479281 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.4040479281
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/11.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_stress_all_with_error.2107319466
Short name	T314
Test name
Test status
Simulation time	1434590557 ps
CPU time	160.68 seconds
Started	Feb 08 08:56:58 AM UTC 25
Finished	Feb 08 08:59:42 AM UTC 25
Peak memory	220840 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2107319466 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.2107319466
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/11.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_stress_all_with_rand_reset.310513971
Short name	T546
Test name
Test status
Simulation time	2234288757 ps
CPU time	549.03 seconds
Started	Feb 08 08:56:57 AM UTC 25
Finished	Feb 08 09:06:13 AM UTC 25
Peak memory	238360 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=310513971 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs /coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_rand_reset.310513971
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/11.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_stress_all_with_reset_error.2539020064
Short name	T33
Test name
Test status
Simulation time	5693404557 ps
CPU time	184.42 seconds
Started	Feb 08 08:57:00 AM UTC 25
Finished	Feb 08 09:00:08 AM UTC 25
Peak memory	220908 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2539020064 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_reset_error.2539020064
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/11.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_unmapped_addr.3752153109
Short name	T121
Test name
Test status
Simulation time	590429242 ps
CPU time	8.06 seconds
Started	Feb 08 08:56:55 AM UTC 25
Finished	Feb 08 08:57:04 AM UTC 25
Peak memory	217072 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3752153109 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xb ar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.3752153109
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/11.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_access_same_device_slow_rsp.1473070667
Short name	T760
Test name
Test status
Simulation time	250035735845 ps
CPU time	884.59 seconds
Started	Feb 08 08:57:11 AM UTC 25
Finished	Feb 08 09:12:06 AM UTC 25
Peak memory	222600 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1473070667 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/ coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device_slow_rsp.1473070667
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/12.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_error_and_unmapped_addr.2337412716
Short name	T229
Test name
Test status
Simulation time	66735419 ps
CPU time	12.54 seconds
Started	Feb 08 08:57:15 AM UTC 25
Finished	Feb 08 08:57:29 AM UTC 25
Peak memory	217068 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2337412716 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/x bar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_addr.2337412716
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/12.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_error_random.2396450423
Short name	T222
Test name
Test status
Simulation time	4746383947 ps
CPU time	53.7 seconds
Started	Feb 08 08:57:12 AM UTC 25
Finished	Feb 08 08:58:08 AM UTC 25
Peak memory	216864 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2396450423 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_bui ld_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.2396450423
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/12.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_random.3312587560
Short name	T357
Test name
Test status
Simulation time	74120482 ps
CPU time	2.71 seconds
Started	Feb 08 08:57:06 AM UTC 25
Finished	Feb 08 08:57:10 AM UTC 25
Peak memory	216748 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3312587560 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_buil d_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random.3312587560
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/12.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_random_large_delays.222203235
Short name	T228
Test name
Test status
Simulation time	3401320415 ps
CPU time	16.77 seconds
Started	Feb 08 08:57:07 AM UTC 25
Finished	Feb 08 08:57:25 AM UTC 25
Peak memory	216876 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=222203235 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/ xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.222203235
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/12.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_random_slow_rsp.2008629440
Short name	T367
Test name
Test status
Simulation time	10447940192 ps
CPU time	91.85 seconds
Started	Feb 08 08:57:09 AM UTC 25
Finished	Feb 08 08:58:43 AM UTC 25
Peak memory	217204 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2008629440 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xba r_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.2008629440
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/12.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_random_zero_delays.413247638
Short name	T226
Test name
Test status
Simulation time	49029256 ps
CPU time	9.39 seconds
Started	Feb 08 08:57:06 AM UTC 25
Finished	Feb 08 08:57:17 AM UTC 25
Peak memory	216808 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=413247638 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/cove rage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_delays.413247638
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/12.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_same_source.3909092153
Short name	T227
Test name
Test status
Simulation time	140099804 ps
CPU time	10.01 seconds
Started	Feb 08 08:57:11 AM UTC 25
Finished	Feb 08 08:57:23 AM UTC 25
Peak memory	216812 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3909092153 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.3909092153
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/12.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_smoke.3246083020
Short name	T53
Test name
Test status
Simulation time	453443297 ps
CPU time	5.51 seconds
Started	Feb 08 08:57:01 AM UTC 25
Finished	Feb 08 08:57:09 AM UTC 25
Peak memory	216896 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3246083020 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build _mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.3246083020
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/12.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_smoke_large_delays.3055572237
Short name	T56
Test name
Test status
Simulation time	6177365379 ps
CPU time	43.75 seconds
Started	Feb 08 08:57:03 AM UTC 25
Finished	Feb 08 08:57:48 AM UTC 25
Peak memory	216796 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3055572237 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/ xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.3055572237
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/12.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_smoke_slow_rsp.1484627643
Short name	T363
Test name
Test status
Simulation time	12285197070 ps
CPU time	51.38 seconds
Started	Feb 08 08:57:04 AM UTC 25
Finished	Feb 08 08:57:57 AM UTC 25
Peak memory	217180 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1484627643 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.1484627643
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/12.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_smoke_zero_delays.4282355444
Short name	T123
Test name
Test status
Simulation time	21611116 ps
CPU time	2.97 seconds
Started	Feb 08 08:57:01 AM UTC 25
Finished	Feb 08 08:57:06 AM UTC 25
Peak memory	217044 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4282355444 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/cove rage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delays.4282355444
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/12.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_stress_all.3936453847
Short name	T104
Test name
Test status
Simulation time	7238817250 ps
CPU time	130.82 seconds
Started	Feb 08 08:57:15 AM UTC 25
Finished	Feb 08 08:59:28 AM UTC 25
Peak memory	220972 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3936453847 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.3936453847
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/12.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_stress_all_with_error.2335757597
Short name	T145
Test name
Test status
Simulation time	2501288246 ps
CPU time	58.43 seconds
Started	Feb 08 08:57:16 AM UTC 25
Finished	Feb 08 08:58:16 AM UTC 25
Peak memory	219176 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2335757597 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.2335757597
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/12.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_stress_all_with_rand_reset.2519808872
Short name	T296
Test name
Test status
Simulation time	1604448531 ps
CPU time	148 seconds
Started	Feb 08 08:57:16 AM UTC 25
Finished	Feb 08 08:59:47 AM UTC 25
Peak memory	220844 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2519808872 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_rand_reset.2519808872
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/12.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_stress_all_with_reset_error.3857847243
Short name	T369
Test name
Test status
Simulation time	179841229 ps
CPU time	92.97 seconds
Started	Feb 08 08:57:18 AM UTC 25
Finished	Feb 08 08:58:53 AM UTC 25
Peak memory	221224 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3857847243 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_reset_error.3857847243
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/12.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_unmapped_addr.140608372
Short name	T361
Test name
Test status
Simulation time	157037555 ps
CPU time	23.12 seconds
Started	Feb 08 08:57:13 AM UTC 25
Finished	Feb 08 08:57:39 AM UTC 25
Peak memory	216816 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=140608372 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xba r_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.140608372
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/12.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_access_same_device.2187258423
Short name	T100
Test name
Test status
Simulation time	1306979917 ps
CPU time	44.21 seconds
Started	Feb 08 08:57:35 AM UTC 25
Finished	Feb 08 08:58:21 AM UTC 25
Peak memory	218856 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2187258423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/covera ge/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device.2187258423
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/13.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_access_same_device_slow_rsp.4031669286
Short name	T137
Test name
Test status
Simulation time	74759007384 ps
CPU time	803.55 seconds
Started	Feb 08 08:57:37 AM UTC 25
Finished	Feb 08 09:11:10 AM UTC 25
Peak memory	220552 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4031669286 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/ coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device_slow_rsp.4031669286
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/13.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_error_and_unmapped_addr.2676480041
Short name	T147
Test name
Test status
Simulation time	1770899819 ps
CPU time	31.49 seconds
Started	Feb 08 08:57:49 AM UTC 25
Finished	Feb 08 08:58:23 AM UTC 25
Peak memory	216748 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2676480041 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/x bar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_addr.2676480041
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/13.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_error_random.3273020085
Short name	T219
Test name
Test status
Simulation time	645143922 ps
CPU time	19.13 seconds
Started	Feb 08 08:57:45 AM UTC 25
Finished	Feb 08 08:58:07 AM UTC 25
Peak memory	216744 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3273020085 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_bui ld_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.3273020085
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/13.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_random.3989431059
Short name	T87
Test name
Test status
Simulation time	397641578 ps
CPU time	20.52 seconds
Started	Feb 08 08:57:30 AM UTC 25
Finished	Feb 08 08:57:52 AM UTC 25
Peak memory	216496 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3989431059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_buil d_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random.3989431059
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/13.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_random_large_delays.1679789696
Short name	T154
Test name
Test status
Simulation time	31034191808 ps
CPU time	194.21 seconds
Started	Feb 08 08:57:32 AM UTC 25
Finished	Feb 08 09:00:49 AM UTC 25
Peak memory	216868 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1679789696 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage /xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.1679789696
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/13.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_random_slow_rsp.1883635953
Short name	T207
Test name
Test status
Simulation time	21070243589 ps
CPU time	163.19 seconds
Started	Feb 08 08:57:33 AM UTC 25
Finished	Feb 08 09:00:19 AM UTC 25
Peak memory	216816 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1883635953 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xba r_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.1883635953
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/13.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_random_zero_delays.4235430196
Short name	T362
Test name
Test status
Simulation time	476957017 ps
CPU time	23.29 seconds
Started	Feb 08 08:57:30 AM UTC 25
Finished	Feb 08 08:57:55 AM UTC 25
Peak memory	216744 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4235430196 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/cov erage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_delays.4235430196
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/13.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_same_source.1342316924
Short name	T144
Test name
Test status
Simulation time	1360778723 ps
CPU time	33.93 seconds
Started	Feb 08 08:57:40 AM UTC 25
Finished	Feb 08 08:58:16 AM UTC 25
Peak memory	217004 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1342316924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.1342316924
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/13.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_smoke.1904480366
Short name	T267
Test name
Test status
Simulation time	732481009 ps
CPU time	6.05 seconds
Started	Feb 08 08:57:24 AM UTC 25
Finished	Feb 08 08:57:32 AM UTC 25
Peak memory	216796 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1904480366 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build _mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.1904480366
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/13.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_smoke_large_delays.1368125392
Short name	T220
Test name
Test status
Simulation time	5742279670 ps
CPU time	38.65 seconds
Started	Feb 08 08:57:26 AM UTC 25
Finished	Feb 08 08:58:07 AM UTC 25
Peak memory	216860 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1368125392 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/ xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.1368125392
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/13.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_smoke_slow_rsp.1423316800
Short name	T223
Test name
Test status
Simulation time	3135207522 ps
CPU time	39.32 seconds
Started	Feb 08 08:57:27 AM UTC 25
Finished	Feb 08 08:58:09 AM UTC 25
Peak memory	216856 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1423316800 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.1423316800
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/13.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_smoke_zero_delays.253428477
Short name	T230
Test name
Test status
Simulation time	55446319 ps
CPU time	3.35 seconds
Started	Feb 08 08:57:26 AM UTC 25
Finished	Feb 08 08:57:31 AM UTC 25
Peak memory	216784 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=253428477 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/cover age/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delays.253428477
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/13.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_stress_all.743457392
Short name	T224
Test name
Test status
Simulation time	307783575 ps
CPU time	23.87 seconds
Started	Feb 08 08:57:49 AM UTC 25
Finished	Feb 08 08:58:15 AM UTC 25
Peak memory	218796 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=743457392 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_b uild_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.743457392
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/13.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_stress_all_with_error.3615033255
Short name	T278
Test name
Test status
Simulation time	21079871301 ps
CPU time	169.51 seconds
Started	Feb 08 08:57:50 AM UTC 25
Finished	Feb 08 09:00:43 AM UTC 25
Peak memory	222944 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3615033255 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.3615033255
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/13.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_stress_all_with_rand_reset.2433464614
Short name	T194
Test name
Test status
Simulation time	3122709384 ps
CPU time	315.31 seconds
Started	Feb 08 08:57:49 AM UTC 25
Finished	Feb 08 09:03:09 AM UTC 25
Peak memory	223388 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2433464614 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_rand_reset.2433464614
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/13.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_unmapped_addr.3300699724
Short name	T365
Test name
Test status
Simulation time	83877174 ps
CPU time	6.39 seconds
Started	Feb 08 08:57:49 AM UTC 25
Finished	Feb 08 08:57:57 AM UTC 25
Peak memory	216804 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3300699724 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xb ar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.3300699724
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/13.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_access_same_device.2520336851
Short name	T101
Test name
Test status
Simulation time	820711756 ps
CPU time	12.93 seconds
Started	Feb 08 08:58:07 AM UTC 25
Finished	Feb 08 08:58:22 AM UTC 25
Peak memory	216744 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2520336851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/covera ge/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device.2520336851
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/14.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_access_same_device_slow_rsp.447608042
Short name	T319
Test name
Test status
Simulation time	90233013645 ps
CPU time	534.83 seconds
Started	Feb 08 08:58:08 AM UTC 25
Finished	Feb 08 09:07:09 AM UTC 25
Peak memory	220972 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=447608042 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST _SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/c overage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device_slow_rsp.447608042
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/14.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_error_and_unmapped_addr.248412170
Short name	T294
Test name
Test status
Simulation time	2885868963 ps
CPU time	28.05 seconds
Started	Feb 08 08:58:09 AM UTC 25
Finished	Feb 08 08:58:39 AM UTC 25
Peak memory	216792 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=248412170 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ= xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xb ar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_addr.248412170
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/14.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_error_random.2596402765
Short name	T48
Test name
Test status
Simulation time	2575592024 ps
CPU time	18.75 seconds
Started	Feb 08 08:58:09 AM UTC 25
Finished	Feb 08 08:58:30 AM UTC 25
Peak memory	217124 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2596402765 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_bui ld_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.2596402765
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/14.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_random.579402446
Short name	T218
Test name
Test status
Simulation time	68284723 ps
CPU time	5.07 seconds
Started	Feb 08 08:57:58 AM UTC 25
Finished	Feb 08 08:58:06 AM UTC 25
Peak memory	217132 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=579402446 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build _mode.vdb -cm_log /dev/null -cm_name 14.xbar_random.579402446
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/14.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_random_large_delays.1338031351
Short name	T57
Test name
Test status
Simulation time	29693437607 ps
CPU time	65.58 seconds
Started	Feb 08 08:58:01 AM UTC 25
Finished	Feb 08 08:59:09 AM UTC 25
Peak memory	216868 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1338031351 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage /xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.1338031351
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/14.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_random_slow_rsp.3813840374
Short name	T418
Test name
Test status
Simulation time	43031714523 ps
CPU time	205.6 seconds
Started	Feb 08 08:58:05 AM UTC 25
Finished	Feb 08 09:01:34 AM UTC 25
Peak memory	218924 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3813840374 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xba r_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.3813840374
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/14.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_random_zero_delays.4050082942
Short name	T150
Test name
Test status
Simulation time	176838771 ps
CPU time	27.44 seconds
Started	Feb 08 08:57:59 AM UTC 25
Finished	Feb 08 08:58:29 AM UTC 25
Peak memory	216744 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4050082942 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/cov erage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_delays.4050082942
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/14.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_same_source.570739506
Short name	T149
Test name
Test status
Simulation time	725060790 ps
CPU time	13.56 seconds
Started	Feb 08 08:58:08 AM UTC 25
Finished	Feb 08 08:58:23 AM UTC 25
Peak memory	216812 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=570739506 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.570739506
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/14.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_smoke.582937327
Short name	T364
Test name
Test status
Simulation time	49678603 ps
CPU time	2.43 seconds
Started	Feb 08 08:57:53 AM UTC 25
Finished	Feb 08 08:57:57 AM UTC 25
Peak memory	216788 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=582937327 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_ mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.582937327
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/14.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_smoke_large_delays.2721784057
Short name	T281
Test name
Test status
Simulation time	14910533806 ps
CPU time	55.15 seconds
Started	Feb 08 08:57:58 AM UTC 25
Finished	Feb 08 08:58:56 AM UTC 25
Peak memory	217124 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2721784057 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/ xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.2721784057
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/14.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_smoke_slow_rsp.1592203170
Short name	T368
Test name
Test status
Simulation time	5127434665 ps
CPU time	51.96 seconds
Started	Feb 08 08:57:58 AM UTC 25
Finished	Feb 08 08:58:53 AM UTC 25
Peak memory	217180 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1592203170 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.1592203170
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/14.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_smoke_zero_delays.449292862
Short name	T366
Test name
Test status
Simulation time	23852866 ps
CPU time	2.85 seconds
Started	Feb 08 08:57:55 AM UTC 25
Finished	Feb 08 08:58:00 AM UTC 25
Peak memory	216980 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=449292862 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/cover age/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delays.449292862
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/14.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_stress_all.736849506
Short name	T399
Test name
Test status
Simulation time	4005658423 ps
CPU time	165.8 seconds
Started	Feb 08 08:58:10 AM UTC 25
Finished	Feb 08 09:01:00 AM UTC 25
Peak memory	219184 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=736849506 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_b uild_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.736849506
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/14.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_stress_all_with_error.1294454941
Short name	T410
Test name
Test status
Simulation time	12295725071 ps
CPU time	172.45 seconds
Started	Feb 08 08:58:16 AM UTC 25
Finished	Feb 08 09:01:11 AM UTC 25
Peak memory	220904 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1294454941 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.1294454941
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/14.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_stress_all_with_rand_reset.1645604105
Short name	T577
Test name
Test status
Simulation time	7307438926 ps
CPU time	521.02 seconds
Started	Feb 08 08:58:12 AM UTC 25
Finished	Feb 08 09:07:00 AM UTC 25
Peak memory	221296 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1645604105 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_rand_reset.1645604105
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/14.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_stress_all_with_reset_error.1783864846
Short name	T327
Test name
Test status
Simulation time	174600331 ps
CPU time	115.9 seconds
Started	Feb 08 08:58:16 AM UTC 25
Finished	Feb 08 09:00:14 AM UTC 25
Peak memory	222956 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1783864846 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_reset_error.1783864846
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/14.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_unmapped_addr.2015166318
Short name	T293
Test name
Test status
Simulation time	93155444 ps
CPU time	18.85 seconds
Started	Feb 08 08:58:09 AM UTC 25
Finished	Feb 08 08:58:30 AM UTC 25
Peak memory	218864 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2015166318 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xb ar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.2015166318
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/14.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_access_same_device.3145517638
Short name	T377
Test name
Test status
Simulation time	655910565 ps
CPU time	34.26 seconds
Started	Feb 08 08:58:31 AM UTC 25
Finished	Feb 08 08:59:07 AM UTC 25
Peak memory	216812 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3145517638 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/covera ge/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device.3145517638
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/15.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_access_same_device_slow_rsp.1007207720
Short name	T204
Test name
Test status
Simulation time	12725891648 ps
CPU time	116.11 seconds
Started	Feb 08 08:58:31 AM UTC 25
Finished	Feb 08 09:00:30 AM UTC 25
Peak memory	219180 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1007207720 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/ coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device_slow_rsp.1007207720
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/15.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_error_and_unmapped_addr.3064098303
Short name	T376
Test name
Test status
Simulation time	478116543 ps
CPU time	20.31 seconds
Started	Feb 08 08:58:44 AM UTC 25
Finished	Feb 08 08:59:06 AM UTC 25
Peak memory	217068 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3064098303 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/x bar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_addr.3064098303
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/15.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_error_random.1942015683
Short name	T372
Test name
Test status
Simulation time	122421951 ps
CPU time	20.01 seconds
Started	Feb 08 08:58:36 AM UTC 25
Finished	Feb 08 08:58:57 AM UTC 25
Peak memory	216740 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1942015683 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_bui ld_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.1942015683
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/15.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_random.3670520092
Short name	T186
Test name
Test status
Simulation time	866128026 ps
CPU time	21.34 seconds
Started	Feb 08 08:58:23 AM UTC 25
Finished	Feb 08 08:58:46 AM UTC 25
Peak memory	216816 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3670520092 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_buil d_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random.3670520092
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/15.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_random_large_delays.1083234129
Short name	T424
Test name
Test status
Simulation time	24945090026 ps
CPU time	197.64 seconds
Started	Feb 08 08:58:24 AM UTC 25
Finished	Feb 08 09:01:45 AM UTC 25
Peak memory	216600 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1083234129 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage /xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.1083234129
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/15.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_random_slow_rsp.3190161862
Short name	T467
Test name
Test status
Simulation time	46535863337 ps
CPU time	293.68 seconds
Started	Feb 08 08:58:24 AM UTC 25
Finished	Feb 08 09:03:22 AM UTC 25
Peak memory	216632 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3190161862 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xba r_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.3190161862
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/15.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_random_zero_delays.1021550381
Short name	T371
Test name
Test status
Simulation time	261192339 ps
CPU time	31.54 seconds
Started	Feb 08 08:58:23 AM UTC 25
Finished	Feb 08 08:58:57 AM UTC 25
Peak memory	216804 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1021550381 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/cov erage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_delays.1021550381
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/15.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_same_source.180743710
Short name	T370
Test name
Test status
Simulation time	1103398621 ps
CPU time	23.41 seconds
Started	Feb 08 08:58:31 AM UTC 25
Finished	Feb 08 08:58:56 AM UTC 25
Peak memory	216748 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=180743710 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.180743710
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/15.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_smoke.2195174143
Short name	T146
Test name
Test status
Simulation time	60265845 ps
CPU time	3.69 seconds
Started	Feb 08 08:58:17 AM UTC 25
Finished	Feb 08 08:58:22 AM UTC 25
Peak memory	216728 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2195174143 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build _mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.2195174143
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/15.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_smoke_large_delays.3512382034
Short name	T374
Test name
Test status
Simulation time	8333637407 ps
CPU time	35.26 seconds
Started	Feb 08 08:58:22 AM UTC 25
Finished	Feb 08 08:58:59 AM UTC 25
Peak memory	216864 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3512382034 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/ xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.3512382034
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/15.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_smoke_slow_rsp.3063424400
Short name	T384
Test name
Test status
Simulation time	24181645899 ps
CPU time	71.05 seconds
Started	Feb 08 08:58:23 AM UTC 25
Finished	Feb 08 08:59:37 AM UTC 25
Peak memory	216856 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3063424400 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.3063424400
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/15.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_smoke_zero_delays.1077984775
Short name	T148
Test name
Test status
Simulation time	38202286 ps
CPU time	3.61 seconds
Started	Feb 08 08:58:18 AM UTC 25
Finished	Feb 08 08:58:23 AM UTC 25
Peak memory	216784 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1077984775 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/cove rage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delays.1077984775
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/15.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_stress_all_with_error.1180200535
Short name	T321
Test name
Test status
Simulation time	2761467436 ps
CPU time	46.57 seconds
Started	Feb 08 08:58:52 AM UTC 25
Finished	Feb 08 08:59:41 AM UTC 25
Peak memory	218924 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1180200535 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.1180200535
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/15.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_stress_all_with_rand_reset.4290466099
Short name	T303
Test name
Test status
Simulation time	2792538334 ps
CPU time	293.02 seconds
Started	Feb 08 08:58:49 AM UTC 25
Finished	Feb 08 09:03:47 AM UTC 25
Peak memory	223484 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4290466099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_rand_reset.4290466099
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/15.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_unmapped_addr.1517297290
Short name	T102
Test name
Test status
Simulation time	798731451 ps
CPU time	29.39 seconds
Started	Feb 08 08:58:40 AM UTC 25
Finished	Feb 08 08:59:11 AM UTC 25
Peak memory	218856 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1517297290 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xb ar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.1517297290
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/15.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_access_same_device.3244703209
Short name	T307
Test name
Test status
Simulation time	2833479881 ps
CPU time	61.98 seconds
Started	Feb 08 08:59:02 AM UTC 25
Finished	Feb 08 09:00:06 AM UTC 25
Peak memory	219180 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3244703209 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/covera ge/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device.3244703209
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/16.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_access_same_device_slow_rsp.3561543807
Short name	T587
Test name
Test status
Simulation time	71787856077 ps
CPU time	485.07 seconds
Started	Feb 08 08:59:02 AM UTC 25
Finished	Feb 08 09:07:13 AM UTC 25
Peak memory	218928 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3561543807 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/ coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device_slow_rsp.3561543807
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/16.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_error_and_unmapped_addr.487477089
Short name	T379
Test name
Test status
Simulation time	79606024 ps
CPU time	4.73 seconds
Started	Feb 08 08:59:12 AM UTC 25
Finished	Feb 08 08:59:18 AM UTC 25
Peak memory	216788 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=487477089 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ= xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xb ar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_addr.487477089
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/16.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_error_random.3391419110
Short name	T385
Test name
Test status
Simulation time	330539770 ps
CPU time	30.7 seconds
Started	Feb 08 08:59:08 AM UTC 25
Finished	Feb 08 08:59:40 AM UTC 25
Peak memory	217060 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3391419110 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_bui ld_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.3391419110
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/16.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_random.659337000
Short name	T383
Test name
Test status
Simulation time	2404687420 ps
CPU time	35.16 seconds
Started	Feb 08 08:58:59 AM UTC 25
Finished	Feb 08 08:59:36 AM UTC 25
Peak memory	218920 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=659337000 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build _mode.vdb -cm_log /dev/null -cm_name 16.xbar_random.659337000
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/16.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_random_large_delays.766549737
Short name	T391
Test name
Test status
Simulation time	13430583374 ps
CPU time	72.59 seconds
Started	Feb 08 08:58:59 AM UTC 25
Finished	Feb 08 09:00:14 AM UTC 25
Peak memory	216880 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=766549737 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/ xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.766549737
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/16.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_random_slow_rsp.3992476576
Short name	T215
Test name
Test status
Simulation time	16735319147 ps
CPU time	184.02 seconds
Started	Feb 08 08:59:00 AM UTC 25
Finished	Feb 08 09:02:07 AM UTC 25
Peak memory	216880 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3992476576 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xba r_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.3992476576
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/16.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_random_zero_delays.635892382
Short name	T192
Test name
Test status
Simulation time	339189392 ps
CPU time	31.33 seconds
Started	Feb 08 08:58:59 AM UTC 25
Finished	Feb 08 08:59:33 AM UTC 25
Peak memory	217000 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=635892382 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/cove rage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_delays.635892382
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/16.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_same_source.4081399557
Short name	T300
Test name
Test status
Simulation time	571446537 ps
CPU time	8.82 seconds
Started	Feb 08 08:59:08 AM UTC 25
Finished	Feb 08 08:59:18 AM UTC 25
Peak memory	216808 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4081399557 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.4081399557
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/16.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_smoke.1632661638
Short name	T373
Test name
Test status
Simulation time	220611979 ps
CPU time	3.63 seconds
Started	Feb 08 08:58:54 AM UTC 25
Finished	Feb 08 08:58:59 AM UTC 25
Peak memory	216792 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1632661638 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build _mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.1632661638
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/16.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_smoke_large_delays.3108346798
Short name	T393
Test name
Test status
Simulation time	36353195762 ps
CPU time	80.25 seconds
Started	Feb 08 08:58:59 AM UTC 25
Finished	Feb 08 09:00:22 AM UTC 25
Peak memory	217120 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3108346798 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/ xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.3108346798
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/16.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_smoke_slow_rsp.1959766610
Short name	T381
Test name
Test status
Simulation time	7499002017 ps
CPU time	27.36 seconds
Started	Feb 08 08:58:59 AM UTC 25
Finished	Feb 08 08:59:28 AM UTC 25
Peak memory	216844 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1959766610 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.1959766610
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/16.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_smoke_zero_delays.2692021720
Short name	T375
Test name
Test status
Simulation time	22027598 ps
CPU time	2.91 seconds
Started	Feb 08 08:58:55 AM UTC 25
Finished	Feb 08 08:58:59 AM UTC 25
Peak memory	216720 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2692021720 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/cove rage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delays.2692021720
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/16.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_stress_all.3936799658
Short name	T125
Test name
Test status
Simulation time	3511344048 ps
CPU time	126.69 seconds
Started	Feb 08 08:59:16 AM UTC 25
Finished	Feb 08 09:01:26 AM UTC 25
Peak memory	219248 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3936799658 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.3936799658
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/16.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_stress_all_with_error.180591719
Short name	T277
Test name
Test status
Simulation time	2275581254 ps
CPU time	80.88 seconds
Started	Feb 08 08:59:18 AM UTC 25
Finished	Feb 08 09:00:42 AM UTC 25
Peak memory	218924 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=180591719 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ= xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.180591719
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/16.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_stress_all_with_rand_reset.4057965121
Short name	T317
Test name
Test status
Simulation time	3255206292 ps
CPU time	202.47 seconds
Started	Feb 08 08:59:18 AM UTC 25
Finished	Feb 08 09:02:44 AM UTC 25
Peak memory	222956 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4057965121 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_rand_reset.4057965121
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/16.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_stress_all_with_reset_error.2742763236
Short name	T403
Test name
Test status
Simulation time	4130354194 ps
CPU time	100.76 seconds
Started	Feb 08 08:59:20 AM UTC 25
Finished	Feb 08 09:01:04 AM UTC 25
Peak memory	219208 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2742763236 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_reset_error.2742763236
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/16.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_unmapped_addr.4090887560
Short name	T299
Test name
Test status
Simulation time	472022787 ps
CPU time	23.76 seconds
Started	Feb 08 08:59:10 AM UTC 25
Finished	Feb 08 08:59:36 AM UTC 25
Peak memory	218792 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4090887560 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xb ar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.4090887560
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/16.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_access_same_device.4065012431
Short name	T386
Test name
Test status
Simulation time	126252650 ps
CPU time	6.48 seconds
Started	Feb 08 08:59:37 AM UTC 25
Finished	Feb 08 08:59:45 AM UTC 25
Peak memory	216804 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4065012431 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/covera ge/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device.4065012431
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/17.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_access_same_device_slow_rsp.4219189508
Short name	T275
Test name
Test status
Simulation time	9704766648 ps
CPU time	59.8 seconds
Started	Feb 08 08:59:39 AM UTC 25
Finished	Feb 08 09:00:41 AM UTC 25
Peak memory	216880 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4219189508 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/ coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device_slow_rsp.4219189508
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/17.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_error_and_unmapped_addr.435643081
Short name	T389
Test name
Test status
Simulation time	182509985 ps
CPU time	9.05 seconds
Started	Feb 08 08:59:46 AM UTC 25
Finished	Feb 08 08:59:56 AM UTC 25
Peak memory	217056 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=435643081 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ= xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xb ar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_addr.435643081
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/17.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_error_random.594936259
Short name	T390
Test name
Test status
Simulation time	4170056598 ps
CPU time	23.37 seconds
Started	Feb 08 08:59:43 AM UTC 25
Finished	Feb 08 09:00:09 AM UTC 25
Peak memory	216804 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=594936259 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ= xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_buil d_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.594936259
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/17.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_random.3267641044
Short name	T206
Test name
Test status
Simulation time	534505789 ps
CPU time	26.81 seconds
Started	Feb 08 08:59:33 AM UTC 25
Finished	Feb 08 09:00:01 AM UTC 25
Peak memory	216708 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3267641044 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_buil d_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random.3267641044
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/17.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_random_large_delays.2890198974
Short name	T439
Test name
Test status
Simulation time	32553647250 ps
CPU time	171.82 seconds
Started	Feb 08 08:59:35 AM UTC 25
Finished	Feb 08 09:02:30 AM UTC 25
Peak memory	219180 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2890198974 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage /xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.2890198974
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/17.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_random_slow_rsp.2067070277
Short name	T185
Test name
Test status
Simulation time	178739342576 ps
CPU time	343.51 seconds
Started	Feb 08 08:59:37 AM UTC 25
Finished	Feb 08 09:05:25 AM UTC 25
Peak memory	218864 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2067070277 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xba r_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.2067070277
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/17.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_random_zero_delays.2502451818
Short name	T387
Test name
Test status
Simulation time	133637463 ps
CPU time	12.04 seconds
Started	Feb 08 08:59:33 AM UTC 25
Finished	Feb 08 08:59:46 AM UTC 25
Peak memory	216956 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2502451818 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/cov erage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_delays.2502451818
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/17.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_same_source.4204754587
Short name	T392
Test name
Test status
Simulation time	3921224903 ps
CPU time	35.89 seconds
Started	Feb 08 08:59:41 AM UTC 25
Finished	Feb 08 09:00:19 AM UTC 25
Peak memory	216812 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4204754587 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.4204754587
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/17.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_smoke.439833051
Short name	T380
Test name
Test status
Simulation time	211795650 ps
CPU time	4.32 seconds
Started	Feb 08 08:59:20 AM UTC 25
Finished	Feb 08 08:59:26 AM UTC 25
Peak memory	216788 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=439833051 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_ mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.439833051
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/17.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_smoke_large_delays.2702954192
Short name	T394
Test name
Test status
Simulation time	8815021998 ps
CPU time	52.06 seconds
Started	Feb 08 08:59:31 AM UTC 25
Finished	Feb 08 09:00:25 AM UTC 25
Peak memory	216924 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2702954192 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/ xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.2702954192
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/17.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_smoke_slow_rsp.3978133867
Short name	T59
Test name
Test status
Simulation time	3900269064 ps
CPU time	33.1 seconds
Started	Feb 08 08:59:31 AM UTC 25
Finished	Feb 08 09:00:05 AM UTC 25
Peak memory	217120 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3978133867 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.3978133867
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/17.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_smoke_zero_delays.2018957228
Short name	T382
Test name
Test status
Simulation time	57107093 ps
CPU time	3.47 seconds
Started	Feb 08 08:59:26 AM UTC 25
Finished	Feb 08 08:59:32 AM UTC 25
Peak memory	217044 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2018957228 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/cove rage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delays.2018957228
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/17.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_stress_all_with_error.1163002694
Short name	T431
Test name
Test status
Simulation time	6842748343 ps
CPU time	134.76 seconds
Started	Feb 08 08:59:56 AM UTC 25
Finished	Feb 08 09:02:13 AM UTC 25
Peak memory	222952 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1163002694 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.1163002694
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/17.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_stress_all_with_rand_reset.2511939735
Short name	T212
Test name
Test status
Simulation time	314462915 ps
CPU time	127.78 seconds
Started	Feb 08 08:59:48 AM UTC 25
Finished	Feb 08 09:01:59 AM UTC 25
Peak memory	221168 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2511939735 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_rand_reset.2511939735
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/17.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_stress_all_with_reset_error.1081409411
Short name	T479
Test name
Test status
Simulation time	6813251208 ps
CPU time	228.68 seconds
Started	Feb 08 08:59:58 AM UTC 25
Finished	Feb 08 09:03:50 AM UTC 25
Peak memory	233884 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1081409411 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_reset_error.1081409411
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/17.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_unmapped_addr.152370750
Short name	T388
Test name
Test status
Simulation time	304178235 ps
CPU time	9.42 seconds
Started	Feb 08 08:59:43 AM UTC 25
Finished	Feb 08 08:59:55 AM UTC 25
Peak memory	216748 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=152370750 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xba r_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.152370750
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/17.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_access_same_device.3516648082
Short name	T151
Test name
Test status
Simulation time	964953598 ps
CPU time	14.25 seconds
Started	Feb 08 09:00:32 AM UTC 25
Finished	Feb 08 09:00:51 AM UTC 25
Peak memory	217068 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3516648082 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/covera ge/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device.3516648082
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/18.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_access_same_device_slow_rsp.993332024
Short name	T534
Test name
Test status
Simulation time	31775193147 ps
CPU time	305.39 seconds
Started	Feb 08 09:00:32 AM UTC 25
Finished	Feb 08 09:05:45 AM UTC 25
Peak memory	218860 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=993332024 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST _SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/c overage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device_slow_rsp.993332024
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/18.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_error_and_unmapped_addr.3824748369
Short name	T279
Test name
Test status
Simulation time	70960338 ps
CPU time	6.53 seconds
Started	Feb 08 09:00:32 AM UTC 25
Finished	Feb 08 09:00:44 AM UTC 25
Peak memory	217068 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3824748369 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/x bar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_addr.3824748369
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/18.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_error_random.1201553609
Short name	T397
Test name
Test status
Simulation time	229224622 ps
CPU time	20.19 seconds
Started	Feb 08 09:00:32 AM UTC 25
Finished	Feb 08 09:00:58 AM UTC 25
Peak memory	216800 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1201553609 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_bui ld_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.1201553609
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/18.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_random.2989574626
Short name	T395
Test name
Test status
Simulation time	144717835 ps
CPU time	13.84 seconds
Started	Feb 08 09:00:30 AM UTC 25
Finished	Feb 08 09:00:51 AM UTC 25
Peak memory	216816 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2989574626 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_buil d_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random.2989574626
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/18.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_random_large_delays.4080407313
Short name	T524
Test name
Test status
Simulation time	37166677859 ps
CPU time	289.8 seconds
Started	Feb 08 09:00:32 AM UTC 25
Finished	Feb 08 09:05:30 AM UTC 25
Peak memory	218992 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4080407313 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage /xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.4080407313
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/18.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_random_slow_rsp.3507302659
Short name	T543
Test name
Test status
Simulation time	100953605778 ps
CPU time	325.35 seconds
Started	Feb 08 09:00:32 AM UTC 25
Finished	Feb 08 09:06:06 AM UTC 25
Peak memory	219184 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3507302659 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xba r_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.3507302659
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/18.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_random_zero_delays.2451717298
Short name	T193
Test name
Test status
Simulation time	101803560 ps
CPU time	10.95 seconds
Started	Feb 08 09:00:30 AM UTC 25
Finished	Feb 08 09:00:49 AM UTC 25
Peak memory	216808 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2451717298 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/cov erage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_delays.2451717298
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/18.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_same_source.1095255841
Short name	T398
Test name
Test status
Simulation time	240022326 ps
CPU time	22.26 seconds
Started	Feb 08 09:00:32 AM UTC 25
Finished	Feb 08 09:01:00 AM UTC 25
Peak memory	216748 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1095255841 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.1095255841
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/18.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_smoke.2936801357
Short name	T276
Test name
Test status
Simulation time	132678760 ps
CPU time	4.39 seconds
Started	Feb 08 09:00:02 AM UTC 25
Finished	Feb 08 09:00:41 AM UTC 25
Peak memory	217048 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2936801357 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build _mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.2936801357
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/18.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_smoke_large_delays.1596299088
Short name	T411
Test name
Test status
Simulation time	9530389288 ps
CPU time	40.11 seconds
Started	Feb 08 09:00:27 AM UTC 25
Finished	Feb 08 09:01:17 AM UTC 25
Peak memory	217120 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1596299088 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/ xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.1596299088
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/18.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_smoke_slow_rsp.281820044
Short name	T430
Test name
Test status
Simulation time	13061040678 ps
CPU time	78.23 seconds
Started	Feb 08 09:00:27 AM UTC 25
Finished	Feb 08 09:01:56 AM UTC 25
Peak memory	216712 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=281820044 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST _SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.281820044
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/18.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_smoke_zero_delays.1162872763
Short name	T274
Test name
Test status
Simulation time	41373479 ps
CPU time	2.7 seconds
Started	Feb 08 09:00:23 AM UTC 25
Finished	Feb 08 09:00:39 AM UTC 25
Peak memory	216804 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1162872763 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/cove rage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delays.1162872763
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/18.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_stress_all.167012319
Short name	T270
Test name
Test status
Simulation time	1657471834 ps
CPU time	43.68 seconds
Started	Feb 08 09:00:32 AM UTC 25
Finished	Feb 08 09:01:21 AM UTC 25
Peak memory	219056 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=167012319 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_b uild_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.167012319
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/18.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_stress_all_with_error.1743118705
Short name	T402
Test name
Test status
Simulation time	565375932 ps
CPU time	22.3 seconds
Started	Feb 08 09:00:35 AM UTC 25
Finished	Feb 08 09:01:01 AM UTC 25
Peak memory	217060 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1743118705 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.1743118705
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/18.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_stress_all_with_rand_reset.617804506
Short name	T297
Test name
Test status
Simulation time	7295925898 ps
CPU time	519.9 seconds
Started	Feb 08 09:00:33 AM UTC 25
Finished	Feb 08 09:09:22 AM UTC 25
Peak memory	222532 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=617804506 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs /coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_rand_reset.617804506
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/18.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_stress_all_with_reset_error.67595271
Short name	T507
Test name
Test status
Simulation time	5008004118 ps
CPU time	254.55 seconds
Started	Feb 08 09:00:35 AM UTC 25
Finished	Feb 08 09:04:56 AM UTC 25
Peak memory	223020 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=67595271 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=x bar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs /coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_reset_error.67595271
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/18.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_unmapped_addr.4059589610
Short name	T400
Test name
Test status
Simulation time	386480518 ps
CPU time	23.08 seconds
Started	Feb 08 09:00:32 AM UTC 25
Finished	Feb 08 09:01:00 AM UTC 25
Peak memory	217136 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4059589610 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xb ar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.4059589610
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/18.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_access_same_device.2759428137
Short name	T126
Test name
Test status
Simulation time	3098439761 ps
CPU time	46.76 seconds
Started	Feb 08 09:00:48 AM UTC 25
Finished	Feb 08 09:01:36 AM UTC 25
Peak memory	218892 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2759428137 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/covera ge/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device.2759428137
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/19.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_access_same_device_slow_rsp.3827522946
Short name	T142
Test name
Test status
Simulation time	228458359004 ps
CPU time	750.9 seconds
Started	Feb 08 09:00:50 AM UTC 25
Finished	Feb 08 09:13:29 AM UTC 25
Peak memory	222536 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3827522946 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/ coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device_slow_rsp.3827522946
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/19.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_error_and_unmapped_addr.1970965440
Short name	T414
Test name
Test status
Simulation time	2091277644 ps
CPU time	30.55 seconds
Started	Feb 08 09:00:52 AM UTC 25
Finished	Feb 08 09:01:25 AM UTC 25
Peak memory	217068 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1970965440 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/x bar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_addr.1970965440
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/19.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_error_random.1885312437
Short name	T408
Test name
Test status
Simulation time	147550606 ps
CPU time	18.92 seconds
Started	Feb 08 09:00:50 AM UTC 25
Finished	Feb 08 09:01:11 AM UTC 25
Peak memory	216808 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1885312437 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_bui ld_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.1885312437
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/19.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_random.3803348230
Short name	T401
Test name
Test status
Simulation time	1241131182 ps
CPU time	16.15 seconds
Started	Feb 08 09:00:43 AM UTC 25
Finished	Feb 08 09:01:01 AM UTC 25
Peak memory	217076 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3803348230 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_buil d_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random.3803348230
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/19.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_random_large_delays.2770495171
Short name	T417
Test name
Test status
Simulation time	5851035981 ps
CPU time	45.81 seconds
Started	Feb 08 09:00:45 AM UTC 25
Finished	Feb 08 09:01:33 AM UTC 25
Peak memory	216752 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2770495171 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage /xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.2770495171
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/19.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_random_slow_rsp.3083101234
Short name	T187
Test name
Test status
Simulation time	28109765735 ps
CPU time	283.61 seconds
Started	Feb 08 09:00:48 AM UTC 25
Finished	Feb 08 09:05:36 AM UTC 25
Peak memory	218924 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3083101234 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xba r_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.3083101234
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/19.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_random_zero_delays.716157777
Short name	T396
Test name
Test status
Simulation time	42038152 ps
CPU time	4.75 seconds
Started	Feb 08 09:00:45 AM UTC 25
Finished	Feb 08 09:00:52 AM UTC 25
Peak memory	216568 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=716157777 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/cove rage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_delays.716157777
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/19.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_same_source.3412879192
Short name	T46
Test name
Test status
Simulation time	841863240 ps
CPU time	26.23 seconds
Started	Feb 08 09:00:50 AM UTC 25
Finished	Feb 08 09:01:18 AM UTC 25
Peak memory	216812 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3412879192 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.3412879192
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/19.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_smoke.2832047134
Short name	T304
Test name
Test status
Simulation time	555549515 ps
CPU time	5.86 seconds
Started	Feb 08 09:00:37 AM UTC 25
Finished	Feb 08 09:00:46 AM UTC 25
Peak memory	216920 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2832047134 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build _mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.2832047134
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/19.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_smoke_large_delays.1629189189
Short name	T412
Test name
Test status
Simulation time	4748017541 ps
CPU time	33.81 seconds
Started	Feb 08 09:00:43 AM UTC 25
Finished	Feb 08 09:01:19 AM UTC 25
Peak memory	217120 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1629189189 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/ xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.1629189189
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/19.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_smoke_slow_rsp.3265192561
Short name	T415
Test name
Test status
Simulation time	10566910805 ps
CPU time	41.96 seconds
Started	Feb 08 09:00:43 AM UTC 25
Finished	Feb 08 09:01:27 AM UTC 25
Peak memory	217116 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3265192561 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.3265192561
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/19.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_smoke_zero_delays.3466394786
Short name	T280
Test name
Test status
Simulation time	42106302 ps
CPU time	2.65 seconds
Started	Feb 08 09:00:41 AM UTC 25
Finished	Feb 08 09:00:45 AM UTC 25
Peak memory	216784 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3466394786 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/cove rage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delays.3466394786
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/19.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_stress_all.790026261
Short name	T407
Test name
Test status
Simulation time	317894639 ps
CPU time	16.5 seconds
Started	Feb 08 09:00:52 AM UTC 25
Finished	Feb 08 09:01:10 AM UTC 25
Peak memory	219120 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=790026261 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_b uild_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.790026261
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/19.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_stress_all_with_error.952252689
Short name	T443
Test name
Test status
Simulation time	2902086633 ps
CPU time	96.98 seconds
Started	Feb 08 09:00:57 AM UTC 25
Finished	Feb 08 09:02:37 AM UTC 25
Peak memory	218860 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=952252689 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ= xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.952252689
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/19.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_stress_all_with_rand_reset.4148170178
Short name	T612
Test name
Test status
Simulation time	1257839391 ps
CPU time	401.94 seconds
Started	Feb 08 09:00:57 AM UTC 25
Finished	Feb 08 09:07:45 AM UTC 25
Peak memory	223152 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4148170178 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_rand_reset.4148170178
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/19.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_stress_all_with_reset_error.3110443817
Short name	T210
Test name
Test status
Simulation time	131880506 ps
CPU time	55.63 seconds
Started	Feb 08 09:00:58 AM UTC 25
Finished	Feb 08 09:01:56 AM UTC 25
Peak memory	221040 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3110443817 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_reset_error.3110443817
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/19.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_unmapped_addr.3368088985
Short name	T242
Test name
Test status
Simulation time	1406751347 ps
CPU time	32.57 seconds
Started	Feb 08 09:00:52 AM UTC 25
Finished	Feb 08 09:01:27 AM UTC 25
Peak memory	216816 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3368088985 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xb ar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.3368088985
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/19.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_access_same_device_slow_rsp.241150779
Short name	T96
Test name
Test status
Simulation time	5723684442 ps
CPU time	48.71 seconds
Started	Feb 08 08:53:10 AM UTC 25
Finished	Feb 08 08:54:00 AM UTC 25
Peak memory	216884 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=241150779 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST _SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/c overage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device_slow_rsp.241150779
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/2.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_error_and_unmapped_addr.3237395826
Short name	T19
Test name
Test status
Simulation time	293250463 ps
CPU time	5.16 seconds
Started	Feb 08 08:53:11 AM UTC 25
Finished	Feb 08 08:53:18 AM UTC 25
Peak memory	216796 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3237395826 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/x bar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr.3237395826
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/2.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_error_random.3229074670
Short name	T20
Test name
Test status
Simulation time	70379879 ps
CPU time	8.04 seconds
Started	Feb 08 08:53:10 AM UTC 25
Finished	Feb 08 08:53:19 AM UTC 25
Peak memory	216740 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3229074670 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_bui ld_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.3229074670
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/2.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_random_large_delays.2196416126
Short name	T177
Test name
Test status
Simulation time	97712300679 ps
CPU time	241.21 seconds
Started	Feb 08 08:53:09 AM UTC 25
Finished	Feb 08 08:57:14 AM UTC 25
Peak memory	219248 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2196416126 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage /xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.2196416126
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/2.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_random_slow_rsp.617420267
Short name	T189
Test name
Test status
Simulation time	12877182544 ps
CPU time	115.65 seconds
Started	Feb 08 08:53:09 AM UTC 25
Finished	Feb 08 08:55:08 AM UTC 25
Peak memory	216872 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=617420267 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST _SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.617420267
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/2.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_random_zero_delays.2436237454
Short name	T24
Test name
Test status
Simulation time	1057983254 ps
CPU time	22.59 seconds
Started	Feb 08 08:53:07 AM UTC 25
Finished	Feb 08 08:53:32 AM UTC 25
Peak memory	216812 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2436237454 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/cov erage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_delays.2436237454
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/2.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_same_source.983053386
Short name	T113
Test name
Test status
Simulation time	1907524521 ps
CPU time	36.55 seconds
Started	Feb 08 08:53:10 AM UTC 25
Finished	Feb 08 08:53:48 AM UTC 25
Peak memory	217044 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=983053386 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.983053386
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/2.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_smoke.2491552523
Short name	T28
Test name
Test status
Simulation time	193123134 ps
CPU time	4.13 seconds
Started	Feb 08 08:53:02 AM UTC 25
Finished	Feb 08 08:53:08 AM UTC 25
Peak memory	216792 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2491552523 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build _mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.2491552523
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/2.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_smoke_large_delays.3665623725
Short name	T114
Test name
Test status
Simulation time	6490859843 ps
CPU time	44.43 seconds
Started	Feb 08 08:53:02 AM UTC 25
Finished	Feb 08 08:53:48 AM UTC 25
Peak memory	217120 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3665623725 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/ xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.3665623725
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/2.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_smoke_slow_rsp.2371862358
Short name	T74
Test name
Test status
Simulation time	15521125744 ps
CPU time	30.41 seconds
Started	Feb 08 08:53:05 AM UTC 25
Finished	Feb 08 08:53:37 AM UTC 25
Peak memory	216860 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2371862358 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.2371862358
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/2.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_smoke_zero_delays.221265439
Short name	T26
Test name
Test status
Simulation time	33984496 ps
CPU time	3.16 seconds
Started	Feb 08 08:53:02 AM UTC 25
Finished	Feb 08 08:53:07 AM UTC 25
Peak memory	216980 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=221265439 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/cover age/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays.221265439
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/2.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_stress_all.287166678
Short name	T171
Test name
Test status
Simulation time	906386547 ps
CPU time	90.43 seconds
Started	Feb 08 08:53:12 AM UTC 25
Finished	Feb 08 08:54:45 AM UTC 25
Peak memory	221164 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=287166678 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_b uild_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.287166678
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/2.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_stress_all_with_error.664928793
Short name	T305
Test name
Test status
Simulation time	49918660398 ps
CPU time	262.52 seconds
Started	Feb 08 08:53:17 AM UTC 25
Finished	Feb 08 08:57:44 AM UTC 25
Peak memory	223396 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=664928793 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ= xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.664928793
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/2.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_stress_all_with_rand_reset.530563866
Short name	T49
Test name
Test status
Simulation time	102784985 ps
CPU time	36.3 seconds
Started	Feb 08 08:53:14 AM UTC 25
Finished	Feb 08 08:53:52 AM UTC 25
Peak memory	218804 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=530563866 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs /coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_rand_reset.530563866
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/2.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_stress_all_with_reset_error.2108653740
Short name	T261
Test name
Test status
Simulation time	417953598 ps
CPU time	139.89 seconds
Started	Feb 08 08:53:17 AM UTC 25
Finished	Feb 08 08:55:40 AM UTC 25
Peak memory	222960 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2108653740 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_reset_error.2108653740
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/2.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_unmapped_addr.501216451
Short name	T23
Test name
Test status
Simulation time	460447752 ps
CPU time	13.04 seconds
Started	Feb 08 08:53:11 AM UTC 25
Finished	Feb 08 08:53:26 AM UTC 25
Peak memory	216944 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=501216451 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xba r_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.501216451
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/2.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_access_same_device.4207242763
Short name	T127
Test name
Test status
Simulation time	1917901088 ps
CPU time	41.48 seconds
Started	Feb 08 09:01:08 AM UTC 25
Finished	Feb 08 09:01:52 AM UTC 25
Peak memory	218860 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4207242763 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/covera ge/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device.4207242763
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/20.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_access_same_device_slow_rsp.3250480121
Short name	T751
Test name
Test status
Simulation time	117928946554 ps
CPU time	637.72 seconds
Started	Feb 08 09:01:10 AM UTC 25
Finished	Feb 08 09:11:55 AM UTC 25
Peak memory	220552 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3250480121 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/ coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device_slow_rsp.3250480121
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/20.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_error_and_unmapped_addr.173623272
Short name	T419
Test name
Test status
Simulation time	736985695 ps
CPU time	21.81 seconds
Started	Feb 08 09:01:13 AM UTC 25
Finished	Feb 08 09:01:36 AM UTC 25
Peak memory	216728 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=173623272 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ= xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xb ar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_addr.173623272
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/20.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_error_random.1845595223
Short name	T421
Test name
Test status
Simulation time	869739030 ps
CPU time	25.49 seconds
Started	Feb 08 09:01:12 AM UTC 25
Finished	Feb 08 09:01:39 AM UTC 25
Peak memory	216580 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1845595223 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_bui ld_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.1845595223
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/20.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_random.3932831846
Short name	T406
Test name
Test status
Simulation time	57533793 ps
CPU time	2.64 seconds
Started	Feb 08 09:01:03 AM UTC 25
Finished	Feb 08 09:01:07 AM UTC 25
Peak memory	216812 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3932831846 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_buil d_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random.3932831846
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/20.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_random_large_delays.2766164597
Short name	T456
Test name
Test status
Simulation time	21675233918 ps
CPU time	114.89 seconds
Started	Feb 08 09:01:06 AM UTC 25
Finished	Feb 08 09:03:04 AM UTC 25
Peak memory	217132 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2766164597 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage /xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.2766164597
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/20.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_random_slow_rsp.1659618245
Short name	T490
Test name
Test status
Simulation time	18199598312 ps
CPU time	186.47 seconds
Started	Feb 08 09:01:07 AM UTC 25
Finished	Feb 08 09:04:17 AM UTC 25
Peak memory	218924 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1659618245 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xba r_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.1659618245
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/20.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_random_zero_delays.3573741247
Short name	T409
Test name
Test status
Simulation time	32882986 ps
CPU time	5.11 seconds
Started	Feb 08 09:01:04 AM UTC 25
Finished	Feb 08 09:01:11 AM UTC 25
Peak memory	216744 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3573741247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/cov erage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_delays.3573741247
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/20.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_same_source.2908887741
Short name	T413
Test name
Test status
Simulation time	468259245 ps
CPU time	11.37 seconds
Started	Feb 08 09:01:12 AM UTC 25
Finished	Feb 08 09:01:25 AM UTC 25
Peak memory	216748 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2908887741 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.2908887741
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/20.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_smoke.1871675043
Short name	T404
Test name
Test status
Simulation time	32611092 ps
CPU time	3.44 seconds
Started	Feb 08 09:01:01 AM UTC 25
Finished	Feb 08 09:01:06 AM UTC 25
Peak memory	216728 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1871675043 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build _mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.1871675043
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/20.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_smoke_large_delays.597635423
Short name	T426
Test name
Test status
Simulation time	7940396049 ps
CPU time	43.48 seconds
Started	Feb 08 09:01:02 AM UTC 25
Finished	Feb 08 09:01:47 AM UTC 25
Peak memory	216860 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=597635423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/x bar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.597635423
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/20.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_smoke_slow_rsp.2135688572
Short name	T60
Test name
Test status
Simulation time	3713301490 ps
CPU time	22.77 seconds
Started	Feb 08 09:01:02 AM UTC 25
Finished	Feb 08 09:01:26 AM UTC 25
Peak memory	216864 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2135688572 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.2135688572
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/20.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_smoke_zero_delays.635640135
Short name	T405
Test name
Test status
Simulation time	48997380 ps
CPU time	3.68 seconds
Started	Feb 08 09:01:01 AM UTC 25
Finished	Feb 08 09:01:06 AM UTC 25
Peak memory	216788 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=635640135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/cover age/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delays.635640135
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/20.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_stress_all.3311315710
Short name	T482
Test name
Test status
Simulation time	5041149868 ps
CPU time	158.69 seconds
Started	Feb 08 09:01:18 AM UTC 25
Finished	Feb 08 09:04:00 AM UTC 25
Peak memory	220972 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3311315710 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.3311315710
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/20.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_stress_all_with_error.2515838938
Short name	T420
Test name
Test status
Simulation time	636508300 ps
CPU time	15.72 seconds
Started	Feb 08 09:01:20 AM UTC 25
Finished	Feb 08 09:01:38 AM UTC 25
Peak memory	216800 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2515838938 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.2515838938
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/20.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_stress_all_with_rand_reset.601930032
Short name	T512
Test name
Test status
Simulation time	2788203082 ps
CPU time	222.57 seconds
Started	Feb 08 09:01:19 AM UTC 25
Finished	Feb 08 09:05:06 AM UTC 25
Peak memory	220972 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=601930032 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs /coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_rand_reset.601930032
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/20.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_stress_all_with_reset_error.3384019279
Short name	T552
Test name
Test status
Simulation time	10042429846 ps
CPU time	300.99 seconds
Started	Feb 08 09:01:22 AM UTC 25
Finished	Feb 08 09:06:28 AM UTC 25
Peak memory	233884 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3384019279 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_reset_error.3384019279
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/20.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_unmapped_addr.3246667335
Short name	T243
Test name
Test status
Simulation time	895717464 ps
CPU time	22.41 seconds
Started	Feb 08 09:01:12 AM UTC 25
Finished	Feb 08 09:01:36 AM UTC 25
Peak memory	218708 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3246667335 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xb ar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.3246667335
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/20.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_access_same_device.1545804562
Short name	T130
Test name
Test status
Simulation time	869082863 ps
CPU time	43.29 seconds
Started	Feb 08 09:01:32 AM UTC 25
Finished	Feb 08 09:02:17 AM UTC 25
Peak memory	217068 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1545804562 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/covera ge/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device.1545804562
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/21.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_access_same_device_slow_rsp.3049049175
Short name	T138
Test name
Test status
Simulation time	240407366087 ps
CPU time	482.21 seconds
Started	Feb 08 09:01:34 AM UTC 25
Finished	Feb 08 09:09:43 AM UTC 25
Peak memory	218928 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3049049175 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/ coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device_slow_rsp.3049049175
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/21.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_error_and_unmapped_addr.2429350955
Short name	T429
Test name
Test status
Simulation time	387064875 ps
CPU time	13.01 seconds
Started	Feb 08 09:01:38 AM UTC 25
Finished	Feb 08 09:01:52 AM UTC 25
Peak memory	216808 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2429350955 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/x bar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_addr.2429350955
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/21.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_error_random.2569202681
Short name	T427
Test name
Test status
Simulation time	78156738 ps
CPU time	12.06 seconds
Started	Feb 08 09:01:36 AM UTC 25
Finished	Feb 08 09:01:50 AM UTC 25
Peak memory	216736 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2569202681 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_bui ld_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.2569202681
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/21.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_random.3067959451
Short name	T422
Test name
Test status
Simulation time	137675944 ps
CPU time	12.94 seconds
Started	Feb 08 09:01:28 AM UTC 25
Finished	Feb 08 09:01:43 AM UTC 25
Peak memory	216816 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3067959451 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_buil d_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random.3067959451
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/21.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_random_large_delays.3692420560
Short name	T525
Test name
Test status
Simulation time	40006163050 ps
CPU time	236.06 seconds
Started	Feb 08 09:01:30 AM UTC 25
Finished	Feb 08 09:05:30 AM UTC 25
Peak memory	216876 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3692420560 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage /xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.3692420560
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/21.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_random_slow_rsp.3625623279
Short name	T484
Test name
Test status
Simulation time	17885618879 ps
CPU time	148.56 seconds
Started	Feb 08 09:01:31 AM UTC 25
Finished	Feb 08 09:04:03 AM UTC 25
Peak memory	217072 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3625623279 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xba r_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.3625623279
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/21.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_random_zero_delays.4102226296
Short name	T213
Test name
Test status
Simulation time	453758060 ps
CPU time	29.37 seconds
Started	Feb 08 09:01:28 AM UTC 25
Finished	Feb 08 09:01:59 AM UTC 25
Peak memory	216744 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4102226296 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/cov erage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_delays.4102226296
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/21.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_same_source.1840482612
Short name	T423
Test name
Test status
Simulation time	74737205 ps
CPU time	7.17 seconds
Started	Feb 08 09:01:34 AM UTC 25
Finished	Feb 08 09:01:43 AM UTC 25
Peak memory	216748 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1840482612 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.1840482612
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/21.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_smoke.4216135375
Short name	T61
Test name
Test status
Simulation time	162741220 ps
CPU time	4.55 seconds
Started	Feb 08 09:01:25 AM UTC 25
Finished	Feb 08 09:01:31 AM UTC 25
Peak memory	216584 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4216135375 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build _mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.4216135375
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/21.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_smoke_large_delays.3719457280
Short name	T433
Test name
Test status
Simulation time	7346701349 ps
CPU time	44.82 seconds
Started	Feb 08 09:01:27 AM UTC 25
Finished	Feb 08 09:02:14 AM UTC 25
Peak memory	217124 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3719457280 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/ xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.3719457280
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/21.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_smoke_slow_rsp.1147242596
Short name	T432
Test name
Test status
Simulation time	6300566740 ps
CPU time	44.69 seconds
Started	Feb 08 09:01:27 AM UTC 25
Finished	Feb 08 09:02:13 AM UTC 25
Peak memory	216856 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1147242596 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.1147242596
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/21.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_smoke_zero_delays.2545012826
Short name	T416
Test name
Test status
Simulation time	57092335 ps
CPU time	3.08 seconds
Started	Feb 08 09:01:26 AM UTC 25
Finished	Feb 08 09:01:30 AM UTC 25
Peak memory	216560 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2545012826 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/cove rage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delays.2545012826
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/21.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_stress_all.2176214094
Short name	T132
Test name
Test status
Simulation time	5680995477 ps
CPU time	141.64 seconds
Started	Feb 08 09:01:39 AM UTC 25
Finished	Feb 08 09:04:04 AM UTC 25
Peak memory	220972 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2176214094 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.2176214094
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/21.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_stress_all_with_error.744012128
Short name	T463
Test name
Test status
Simulation time	5923229745 ps
CPU time	86.45 seconds
Started	Feb 08 09:01:44 AM UTC 25
Finished	Feb 08 09:03:14 AM UTC 25
Peak memory	218864 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=744012128 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ= xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.744012128
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/21.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_stress_all_with_rand_reset.513694654
Short name	T661
Test name
Test status
Simulation time	1774240508 ps
CPU time	460.17 seconds
Started	Feb 08 09:01:40 AM UTC 25
Finished	Feb 08 09:09:26 AM UTC 25
Peak memory	222952 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=513694654 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs /coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_rand_reset.513694654
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/21.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_stress_all_with_reset_error.199938021
Short name	T458
Test name
Test status
Simulation time	309947816 ps
CPU time	80.53 seconds
Started	Feb 08 09:01:44 AM UTC 25
Finished	Feb 08 09:03:08 AM UTC 25
Peak memory	220908 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=199938021 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ= xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_reset_error.199938021
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/21.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_unmapped_addr.3592420749
Short name	T425
Test name
Test status
Simulation time	149148328 ps
CPU time	6.61 seconds
Started	Feb 08 09:01:38 AM UTC 25
Finished	Feb 08 09:01:46 AM UTC 25
Peak memory	216740 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3592420749 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xb ar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.3592420749
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/21.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_access_same_device.3805990208
Short name	T217
Test name
Test status
Simulation time	1542039433 ps
CPU time	16.08 seconds
Started	Feb 08 09:01:55 AM UTC 25
Finished	Feb 08 09:02:12 AM UTC 25
Peak memory	216748 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3805990208 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/covera ge/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device.3805990208
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/22.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_access_same_device_slow_rsp.4139344094
Short name	T325
Test name
Test status
Simulation time	4642910523 ps
CPU time	44.56 seconds
Started	Feb 08 09:01:55 AM UTC 25
Finished	Feb 08 09:02:41 AM UTC 25
Peak memory	216816 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4139344094 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/ coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device_slow_rsp.4139344094
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/22.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_error_and_unmapped_addr.4245020196
Short name	T216
Test name
Test status
Simulation time	67759832 ps
CPU time	9.78 seconds
Started	Feb 08 09:01:58 AM UTC 25
Finished	Feb 08 09:02:09 AM UTC 25
Peak memory	217132 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4245020196 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/x bar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_addr.4245020196
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/22.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_error_random.3450478775
Short name	T437
Test name
Test status
Simulation time	763709664 ps
CPU time	25.37 seconds
Started	Feb 08 09:01:57 AM UTC 25
Finished	Feb 08 09:02:24 AM UTC 25
Peak memory	216740 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3450478775 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_bui ld_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.3450478775
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/22.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_random.2770442783
Short name	T214
Test name
Test status
Simulation time	130474163 ps
CPU time	6.01 seconds
Started	Feb 08 09:01:53 AM UTC 25
Finished	Feb 08 09:02:01 AM UTC 25
Peak memory	216888 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2770442783 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_buil d_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random.2770442783
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/22.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_random_large_delays.1271440980
Short name	T131
Test name
Test status
Simulation time	33121961281 ps
CPU time	95.11 seconds
Started	Feb 08 09:01:53 AM UTC 25
Finished	Feb 08 09:03:31 AM UTC 25
Peak memory	216872 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1271440980 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage /xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.1271440980
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/22.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_random_slow_rsp.4246773648
Short name	T513
Test name
Test status
Simulation time	23402694633 ps
CPU time	192.39 seconds
Started	Feb 08 09:01:54 AM UTC 25
Finished	Feb 08 09:05:10 AM UTC 25
Peak memory	219120 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4246773648 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xba r_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.4246773648
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/22.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_random_zero_delays.1300720755
Short name	T211
Test name
Test status
Simulation time	32657364 ps
CPU time	2.97 seconds
Started	Feb 08 09:01:53 AM UTC 25
Finished	Feb 08 09:01:58 AM UTC 25
Peak memory	217060 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1300720755 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/cov erage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_delays.1300720755
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/22.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_same_source.4163503938
Short name	T438
Test name
Test status
Simulation time	341921164 ps
CPU time	26.54 seconds
Started	Feb 08 09:01:57 AM UTC 25
Finished	Feb 08 09:02:25 AM UTC 25
Peak memory	217132 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4163503938 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.4163503938
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/22.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_smoke.1664646519
Short name	T62
Test name
Test status
Simulation time	212864459 ps
CPU time	5.23 seconds
Started	Feb 08 09:01:46 AM UTC 25
Finished	Feb 08 09:01:53 AM UTC 25
Peak memory	216792 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1664646519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build _mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.1664646519
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/22.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_smoke_large_delays.2529032677
Short name	T445
Test name
Test status
Simulation time	17254442536 ps
CPU time	49.64 seconds
Started	Feb 08 09:01:48 AM UTC 25
Finished	Feb 08 09:02:40 AM UTC 25
Peak memory	216864 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2529032677 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/ xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.2529032677
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/22.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_smoke_slow_rsp.435836032
Short name	T442
Test name
Test status
Simulation time	12320309776 ps
CPU time	41.35 seconds
Started	Feb 08 09:01:51 AM UTC 25
Finished	Feb 08 09:02:35 AM UTC 25
Peak memory	216796 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=435836032 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST _SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.435836032
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/22.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_smoke_zero_delays.4080559074
Short name	T428
Test name
Test status
Simulation time	54891779 ps
CPU time	2.94 seconds
Started	Feb 08 09:01:47 AM UTC 25
Finished	Feb 08 09:01:52 AM UTC 25
Peak memory	216720 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4080559074 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/cove rage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delays.4080559074
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/22.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_stress_all.4277087468
Short name	T196
Test name
Test status
Simulation time	1571698190 ps
CPU time	184.17 seconds
Started	Feb 08 09:01:59 AM UTC 25
Finished	Feb 08 09:05:07 AM UTC 25
Peak memory	219116 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4277087468 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.4277087468
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/22.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_stress_all_with_error.2395034505
Short name	T465
Test name
Test status
Simulation time	570664266 ps
CPU time	73.6 seconds
Started	Feb 08 09:02:01 AM UTC 25
Finished	Feb 08 09:03:17 AM UTC 25
Peak memory	218856 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2395034505 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.2395034505
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/22.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_stress_all_with_rand_reset.3207845490
Short name	T510
Test name
Test status
Simulation time	343743507 ps
CPU time	176.58 seconds
Started	Feb 08 09:02:00 AM UTC 25
Finished	Feb 08 09:05:00 AM UTC 25
Peak memory	220912 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3207845490 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_rand_reset.3207845490
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/22.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_stress_all_with_reset_error.592050147
Short name	T533
Test name
Test status
Simulation time	10111512407 ps
CPU time	209.65 seconds
Started	Feb 08 09:02:08 AM UTC 25
Finished	Feb 08 09:05:41 AM UTC 25
Peak memory	223708 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=592050147 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ= xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_reset_error.592050147
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/22.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_unmapped_addr.3762213870
Short name	T436
Test name
Test status
Simulation time	748435588 ps
CPU time	23.89 seconds
Started	Feb 08 09:01:57 AM UTC 25
Finished	Feb 08 09:02:23 AM UTC 25
Peak memory	216744 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3762213870 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xb ar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.3762213870
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/22.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_access_same_device.2400923884
Short name	T316
Test name
Test status
Simulation time	497849892 ps
CPU time	20.18 seconds
Started	Feb 08 09:02:18 AM UTC 25
Finished	Feb 08 09:02:40 AM UTC 25
Peak memory	219116 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2400923884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/covera ge/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device.2400923884
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/23.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_access_same_device_slow_rsp.3683383550
Short name	T143
Test name
Test status
Simulation time	89814248355 ps
CPU time	672.11 seconds
Started	Feb 08 09:02:23 AM UTC 25
Finished	Feb 08 09:13:44 AM UTC 25
Peak memory	222596 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3683383550 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/ coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device_slow_rsp.3683383550
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/23.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_error_and_unmapped_addr.1367468185
Short name	T444
Test name
Test status
Simulation time	48977035 ps
CPU time	6.86 seconds
Started	Feb 08 09:02:31 AM UTC 25
Finished	Feb 08 09:02:40 AM UTC 25
Peak memory	217068 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1367468185 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/x bar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_addr.1367468185
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/23.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_error_random.2308988366
Short name	T453
Test name
Test status
Simulation time	688623070 ps
CPU time	30.42 seconds
Started	Feb 08 09:02:26 AM UTC 25
Finished	Feb 08 09:02:58 AM UTC 25
Peak memory	216804 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2308988366 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_bui ld_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.2308988366
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/23.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_random.1706505709
Short name	T440
Test name
Test status
Simulation time	386871415 ps
CPU time	13.61 seconds
Started	Feb 08 09:02:14 AM UTC 25
Finished	Feb 08 09:02:30 AM UTC 25
Peak memory	216748 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1706505709 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_buil d_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random.1706505709
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/23.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_random_large_delays.523054471
Short name	T588
Test name
Test status
Simulation time	44307057661 ps
CPU time	292.37 seconds
Started	Feb 08 09:02:16 AM UTC 25
Finished	Feb 08 09:07:13 AM UTC 25
Peak memory	218932 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=523054471 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/ xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.523054471
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/23.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_random_slow_rsp.1207418083
Short name	T622
Test name
Test status
Simulation time	39562527112 ps
CPU time	329.57 seconds
Started	Feb 08 09:02:16 AM UTC 25
Finished	Feb 08 09:07:51 AM UTC 25
Peak memory	218932 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1207418083 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xba r_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.1207418083
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/23.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_random_zero_delays.1260463115
Short name	T450
Test name
Test status
Simulation time	374022809 ps
CPU time	32.59 seconds
Started	Feb 08 09:02:15 AM UTC 25
Finished	Feb 08 09:02:50 AM UTC 25
Peak memory	217068 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1260463115 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/cov erage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_delays.1260463115
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/23.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_same_source.2327267736
Short name	T441
Test name
Test status
Simulation time	208497018 ps
CPU time	4.85 seconds
Started	Feb 08 09:02:24 AM UTC 25
Finished	Feb 08 09:02:31 AM UTC 25
Peak memory	216808 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2327267736 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.2327267736
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/23.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_smoke.3072459187
Short name	T434
Test name
Test status
Simulation time	33742311 ps
CPU time	2.88 seconds
Started	Feb 08 09:02:11 AM UTC 25
Finished	Feb 08 09:02:15 AM UTC 25
Peak memory	216604 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3072459187 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build _mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.3072459187
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/23.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_smoke_large_delays.3126506610
Short name	T457
Test name
Test status
Simulation time	7232017127 ps
CPU time	52.23 seconds
Started	Feb 08 09:02:13 AM UTC 25
Finished	Feb 08 09:03:08 AM UTC 25
Peak memory	217120 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3126506610 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/ xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.3126506610
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/23.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_smoke_slow_rsp.335778127
Short name	T452
Test name
Test status
Simulation time	3032620068 ps
CPU time	38.97 seconds
Started	Feb 08 09:02:14 AM UTC 25
Finished	Feb 08 09:02:56 AM UTC 25
Peak memory	216716 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=335778127 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST _SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.335778127
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/23.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_smoke_zero_delays.1821200424
Short name	T435
Test name
Test status
Simulation time	50908942 ps
CPU time	3.31 seconds
Started	Feb 08 09:02:11 AM UTC 25
Finished	Feb 08 09:02:16 AM UTC 25
Peak memory	216544 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1821200424 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/cove rage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delays.1821200424
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/23.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_stress_all.2350981483
Short name	T598
Test name
Test status
Simulation time	10157637133 ps
CPU time	290.71 seconds
Started	Feb 08 09:02:31 AM UTC 25
Finished	Feb 08 09:07:27 AM UTC 25
Peak memory	223576 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2350981483 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.2350981483
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/23.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_stress_all_with_error.1818340922
Short name	T496
Test name
Test status
Simulation time	5833369922 ps
CPU time	111.85 seconds
Started	Feb 08 09:02:35 AM UTC 25
Finished	Feb 08 09:04:31 AM UTC 25
Peak memory	218920 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1818340922 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.1818340922
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/23.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_stress_all_with_rand_reset.18549529
Short name	T568
Test name
Test status
Simulation time	1270715752 ps
CPU time	249.02 seconds
Started	Feb 08 09:02:32 AM UTC 25
Finished	Feb 08 09:06:46 AM UTC 25
Peak memory	223256 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18549529 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xb ar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/ coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_rand_reset.18549529
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/23.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_stress_all_with_reset_error.1742461779
Short name	T472
Test name
Test status
Simulation time	345877461 ps
CPU time	64.53 seconds
Started	Feb 08 09:02:38 AM UTC 25
Finished	Feb 08 09:03:44 AM UTC 25
Peak memory	219112 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1742461779 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_reset_error.1742461779
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/23.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_unmapped_addr.1593747279
Short name	T447
Test name
Test status
Simulation time	269370205 ps
CPU time	13.23 seconds
Started	Feb 08 09:02:27 AM UTC 25
Finished	Feb 08 09:02:42 AM UTC 25
Peak memory	217132 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1593747279 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xb ar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.1593747279
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/23.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_access_same_device.2744257567
Short name	T455
Test name
Test status
Simulation time	223710120 ps
CPU time	12.52 seconds
Started	Feb 08 09:02:48 AM UTC 25
Finished	Feb 08 09:03:03 AM UTC 25
Peak memory	217132 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2744257567 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/covera ge/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device.2744257567
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/24.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_access_same_device_slow_rsp.1850534693
Short name	T153
Test name
Test status
Simulation time	75234196070 ps
CPU time	593.93 seconds
Started	Feb 08 09:02:52 AM UTC 25
Finished	Feb 08 09:12:53 AM UTC 25
Peak memory	222920 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1850534693 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/ coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device_slow_rsp.1850534693
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/24.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_error_and_unmapped_addr.4193717869
Short name	T459
Test name
Test status
Simulation time	45757356 ps
CPU time	7.05 seconds
Started	Feb 08 09:02:59 AM UTC 25
Finished	Feb 08 09:03:08 AM UTC 25
Peak memory	216812 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4193717869 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/x bar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_addr.4193717869
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/24.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_error_random.3209748043
Short name	T461
Test name
Test status
Simulation time	116949185 ps
CPU time	15.99 seconds
Started	Feb 08 09:02:55 AM UTC 25
Finished	Feb 08 09:03:13 AM UTC 25
Peak memory	217060 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3209748043 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_bui ld_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.3209748043
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/24.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_random.879083655
Short name	T209
Test name
Test status
Simulation time	2960116572 ps
CPU time	42.87 seconds
Started	Feb 08 09:02:42 AM UTC 25
Finished	Feb 08 09:03:27 AM UTC 25
Peak memory	216880 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=879083655 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build _mode.vdb -cm_log /dev/null -cm_name 24.xbar_random.879083655
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/24.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_random_large_delays.3862121253
Short name	T530
Test name
Test status
Simulation time	39741066699 ps
CPU time	170.93 seconds
Started	Feb 08 09:02:45 AM UTC 25
Finished	Feb 08 09:05:40 AM UTC 25
Peak memory	216876 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3862121253 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage /xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.3862121253
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/24.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_random_slow_rsp.1510750100
Short name	T64
Test name
Test status
Simulation time	15987611637 ps
CPU time	62.38 seconds
Started	Feb 08 09:02:46 AM UTC 25
Finished	Feb 08 09:03:51 AM UTC 25
Peak memory	216876 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1510750100 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xba r_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.1510750100
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/24.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_random_zero_delays.1793272316
Short name	T451
Test name
Test status
Simulation time	80667526 ps
CPU time	7.75 seconds
Started	Feb 08 09:02:43 AM UTC 25
Finished	Feb 08 09:02:52 AM UTC 25
Peak memory	216744 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1793272316 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/cov erage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_delays.1793272316
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/24.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_same_source.1853232038
Short name	T468
Test name
Test status
Simulation time	1004480516 ps
CPU time	27.95 seconds
Started	Feb 08 09:02:54 AM UTC 25
Finished	Feb 08 09:03:24 AM UTC 25
Peak memory	216812 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1853232038 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.1853232038
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/24.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_smoke.2274830621
Short name	T449
Test name
Test status
Simulation time	117507255 ps
CPU time	5.01 seconds
Started	Feb 08 09:02:41 AM UTC 25
Finished	Feb 08 09:02:47 AM UTC 25
Peak memory	216728 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2274830621 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build _mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.2274830621
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/24.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_smoke_large_delays.3663136403
Short name	T473
Test name
Test status
Simulation time	6838329874 ps
CPU time	61.59 seconds
Started	Feb 08 09:02:41 AM UTC 25
Finished	Feb 08 09:03:44 AM UTC 25
Peak memory	216864 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3663136403 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/ xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.3663136403
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/24.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_smoke_slow_rsp.1446796809
Short name	T460
Test name
Test status
Simulation time	4168867154 ps
CPU time	25.04 seconds
Started	Feb 08 09:02:42 AM UTC 25
Finished	Feb 08 09:03:09 AM UTC 25
Peak memory	217180 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1446796809 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.1446796809
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/24.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_smoke_zero_delays.383230820
Short name	T448
Test name
Test status
Simulation time	83556079 ps
CPU time	3.32 seconds
Started	Feb 08 09:02:41 AM UTC 25
Finished	Feb 08 09:02:46 AM UTC 25
Peak memory	216788 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=383230820 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/cover age/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delays.383230820
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/24.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_stress_all.2226784841
Short name	T569
Test name
Test status
Simulation time	9371901753 ps
CPU time	219.41 seconds
Started	Feb 08 09:03:02 AM UTC 25
Finished	Feb 08 09:06:46 AM UTC 25
Peak memory	222956 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2226784841 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.2226784841
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/24.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_stress_all_with_error.2483855804
Short name	T318
Test name
Test status
Simulation time	39879460641 ps
CPU time	239.1 seconds
Started	Feb 08 09:03:05 AM UTC 25
Finished	Feb 08 09:07:08 AM UTC 25
Peak memory	219244 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2483855804 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.2483855804
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/24.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_stress_all_with_rand_reset.1569242850
Short name	T696
Test name
Test status
Simulation time	12490811665 ps
CPU time	433.12 seconds
Started	Feb 08 09:03:04 AM UTC 25
Finished	Feb 08 09:10:23 AM UTC 25
Peak memory	233892 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1569242850 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_rand_reset.1569242850
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/24.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_stress_all_with_reset_error.575645087
Short name	T250
Test name
Test status
Simulation time	2646099408 ps
CPU time	303.28 seconds
Started	Feb 08 09:03:06 AM UTC 25
Finished	Feb 08 09:08:14 AM UTC 25
Peak memory	223272 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=575645087 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ= xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_reset_error.575645087
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/24.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_unmapped_addr.1199323932
Short name	T454
Test name
Test status
Simulation time	21174088 ps
CPU time	3.87 seconds
Started	Feb 08 09:02:56 AM UTC 25
Finished	Feb 08 09:03:02 AM UTC 25
Peak memory	216728 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1199323932 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xb ar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.1199323932
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/24.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_access_same_device.2105806021
Short name	T469
Test name
Test status
Simulation time	105152438 ps
CPU time	7.85 seconds
Started	Feb 08 09:03:17 AM UTC 25
Finished	Feb 08 09:03:26 AM UTC 25
Peak memory	216744 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2105806021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/covera ge/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device.2105806021
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/25.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_access_same_device_slow_rsp.2550042591
Short name	T711
Test name
Test status
Simulation time	79844188443 ps
CPU time	447.22 seconds
Started	Feb 08 09:03:18 AM UTC 25
Finished	Feb 08 09:10:51 AM UTC 25
Peak memory	219248 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2550042591 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/ coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device_slow_rsp.2550042591
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/25.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_error_and_unmapped_addr.2314838931
Short name	T474
Test name
Test status
Simulation time	542745935 ps
CPU time	17.78 seconds
Started	Feb 08 09:03:27 AM UTC 25
Finished	Feb 08 09:03:47 AM UTC 25
Peak memory	216808 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2314838931 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/x bar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_addr.2314838931
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/25.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_error_random.1382251538
Short name	T476
Test name
Test status
Simulation time	3209562969 ps
CPU time	23.3 seconds
Started	Feb 08 09:03:23 AM UTC 25
Finished	Feb 08 09:03:48 AM UTC 25
Peak memory	216808 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1382251538 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_bui ld_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.1382251538
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/25.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_random.284038164
Short name	T470
Test name
Test status
Simulation time	375410558 ps
CPU time	15.66 seconds
Started	Feb 08 09:03:10 AM UTC 25
Finished	Feb 08 09:03:28 AM UTC 25
Peak memory	216812 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=284038164 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build _mode.vdb -cm_log /dev/null -cm_name 25.xbar_random.284038164
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/25.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_random_large_delays.3060916028
Short name	T584
Test name
Test status
Simulation time	32936388914 ps
CPU time	232.04 seconds
Started	Feb 08 09:03:15 AM UTC 25
Finished	Feb 08 09:07:10 AM UTC 25
Peak memory	216880 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3060916028 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage /xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.3060916028
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/25.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_random_slow_rsp.3447026227
Short name	T566
Test name
Test status
Simulation time	15039694209 ps
CPU time	205.72 seconds
Started	Feb 08 09:03:15 AM UTC 25
Finished	Feb 08 09:06:44 AM UTC 25
Peak memory	216816 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3447026227 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xba r_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.3447026227
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/25.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_random_zero_delays.746022355
Short name	T238
Test name
Test status
Simulation time	341751532 ps
CPU time	32.67 seconds
Started	Feb 08 09:03:13 AM UTC 25
Finished	Feb 08 09:03:48 AM UTC 25
Peak memory	217000 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=746022355 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/cove rage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_delays.746022355
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/25.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_same_source.2136488861
Short name	T471
Test name
Test status
Simulation time	321104395 ps
CPU time	8.47 seconds
Started	Feb 08 09:03:23 AM UTC 25
Finished	Feb 08 09:03:33 AM UTC 25
Peak memory	216744 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2136488861 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.2136488861
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/25.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_smoke.2068927251
Short name	T464
Test name
Test status
Simulation time	162128420 ps
CPU time	5.11 seconds
Started	Feb 08 09:03:09 AM UTC 25
Finished	Feb 08 09:03:16 AM UTC 25
Peak memory	216792 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2068927251 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build _mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.2068927251
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/25.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_smoke_large_delays.1354094750
Short name	T237
Test name
Test status
Simulation time	7378363749 ps
CPU time	32.68 seconds
Started	Feb 08 09:03:09 AM UTC 25
Finished	Feb 08 09:03:44 AM UTC 25
Peak memory	216860 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1354094750 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/ xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.1354094750
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/25.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_smoke_slow_rsp.3920257605
Short name	T63
Test name
Test status
Simulation time	3866408486 ps
CPU time	34.01 seconds
Started	Feb 08 09:03:10 AM UTC 25
Finished	Feb 08 09:03:46 AM UTC 25
Peak memory	216792 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3920257605 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.3920257605
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/25.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_smoke_zero_delays.930137027
Short name	T462
Test name
Test status
Simulation time	51646019 ps
CPU time	2.95 seconds
Started	Feb 08 09:03:09 AM UTC 25
Finished	Feb 08 09:03:14 AM UTC 25
Peak memory	217108 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=930137027 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/cover age/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delays.930137027
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/25.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_stress_all.869926495
Short name	T521
Test name
Test status
Simulation time	7644062889 ps
CPU time	115.21 seconds
Started	Feb 08 09:03:27 AM UTC 25
Finished	Feb 08 09:05:25 AM UTC 25
Peak memory	218924 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=869926495 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_b uild_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.869926495
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/25.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_stress_all_with_error.1830656266
Short name	T506
Test name
Test status
Simulation time	2701218421 ps
CPU time	80.68 seconds
Started	Feb 08 09:03:32 AM UTC 25
Finished	Feb 08 09:04:55 AM UTC 25
Peak memory	219180 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1830656266 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.1830656266
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/25.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_stress_all_with_rand_reset.1756029057
Short name	T475
Test name
Test status
Simulation time	11955721 ps
CPU time	16.92 seconds
Started	Feb 08 09:03:29 AM UTC 25
Finished	Feb 08 09:03:47 AM UTC 25
Peak memory	216796 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1756029057 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_rand_reset.1756029057
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/25.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_stress_all_with_reset_error.252943860
Short name	T503
Test name
Test status
Simulation time	573183111 ps
CPU time	77.8 seconds
Started	Feb 08 09:03:34 AM UTC 25
Finished	Feb 08 09:04:54 AM UTC 25
Peak memory	220904 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=252943860 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ= xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_reset_error.252943860
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/25.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_unmapped_addr.2906079183
Short name	T485
Test name
Test status
Simulation time	869728577 ps
CPU time	37.81 seconds
Started	Feb 08 09:03:24 AM UTC 25
Finished	Feb 08 09:04:04 AM UTC 25
Peak memory	218792 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2906079183 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xb ar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.2906079183
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/25.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_access_same_device.629742455
Short name	T481
Test name
Test status
Simulation time	204545325 ps
CPU time	8.59 seconds
Started	Feb 08 09:03:49 AM UTC 25
Finished	Feb 08 09:03:59 AM UTC 25
Peak memory	216876 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=629742455 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverag e/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device.629742455
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/26.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_access_same_device_slow_rsp.3394119690
Short name	T657
Test name
Test status
Simulation time	53784916316 ps
CPU time	320.34 seconds
Started	Feb 08 09:03:51 AM UTC 25
Finished	Feb 08 09:09:16 AM UTC 25
Peak memory	219188 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3394119690 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/ coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device_slow_rsp.3394119690
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/26.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_error_and_unmapped_addr.1493300363
Short name	T495
Test name
Test status
Simulation time	1296891892 ps
CPU time	32.62 seconds
Started	Feb 08 09:03:55 AM UTC 25
Finished	Feb 08 09:04:29 AM UTC 25
Peak memory	216812 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1493300363 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/x bar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_addr.1493300363
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/26.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_error_random.1885397098
Short name	T483
Test name
Test status
Simulation time	191860807 ps
CPU time	7.86 seconds
Started	Feb 08 09:03:52 AM UTC 25
Finished	Feb 08 09:04:02 AM UTC 25
Peak memory	216792 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1885397098 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_bui ld_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.1885397098
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/26.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_random.78905677
Short name	T480
Test name
Test status
Simulation time	54814542 ps
CPU time	3.98 seconds
Started	Feb 08 09:03:48 AM UTC 25
Finished	Feb 08 09:03:53 AM UTC 25
Peak memory	216580 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=78905677 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xb ar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_ mode.vdb -cm_log /dev/null -cm_name 26.xbar_random.78905677
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/26.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_random_large_delays.2774067264
Short name	T570
Test name
Test status
Simulation time	27969951039 ps
CPU time	174.05 seconds
Started	Feb 08 09:03:49 AM UTC 25
Finished	Feb 08 09:06:46 AM UTC 25
Peak memory	218852 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2774067264 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage /xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.2774067264
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/26.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_random_slow_rsp.528597430
Short name	T486
Test name
Test status
Simulation time	2152312360 ps
CPU time	14.87 seconds
Started	Feb 08 09:03:49 AM UTC 25
Finished	Feb 08 09:04:06 AM UTC 25
Peak memory	216872 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=528597430 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST _SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.528597430
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/26.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_random_zero_delays.3883240143
Short name	T487
Test name
Test status
Simulation time	214897740 ps
CPU time	15.14 seconds
Started	Feb 08 09:03:49 AM UTC 25
Finished	Feb 08 09:04:06 AM UTC 25
Peak memory	216804 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3883240143 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/cov erage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_delays.3883240143
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/26.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_same_source.2422102670
Short name	T492
Test name
Test status
Simulation time	4390032344 ps
CPU time	30.41 seconds
Started	Feb 08 09:03:51 AM UTC 25
Finished	Feb 08 09:04:24 AM UTC 25
Peak memory	217132 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2422102670 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.2422102670
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/26.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_smoke.1791413141
Short name	T65
Test name
Test status
Simulation time	272259704 ps
CPU time	5.19 seconds
Started	Feb 08 09:03:45 AM UTC 25
Finished	Feb 08 09:03:52 AM UTC 25
Peak memory	216772 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1791413141 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build _mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.1791413141
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/26.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_smoke_large_delays.2124542254
Short name	T501
Test name
Test status
Simulation time	5398776516 ps
CPU time	65.1 seconds
Started	Feb 08 09:03:45 AM UTC 25
Finished	Feb 08 09:04:53 AM UTC 25
Peak memory	216864 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2124542254 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/ xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.2124542254
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/26.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_smoke_slow_rsp.4289772973
Short name	T66
Test name
Test status
Simulation time	3841529098 ps
CPU time	35.01 seconds
Started	Feb 08 09:03:48 AM UTC 25
Finished	Feb 08 09:04:24 AM UTC 25
Peak memory	216628 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4289772973 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.4289772973
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/26.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_smoke_zero_delays.3252897859
Short name	T478
Test name
Test status
Simulation time	39387179 ps
CPU time	3.31 seconds
Started	Feb 08 09:03:45 AM UTC 25
Finished	Feb 08 09:03:50 AM UTC 25
Peak memory	217044 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3252897859 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/cove rage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delays.3252897859
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/26.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_stress_all.2522703302
Short name	T583
Test name
Test status
Simulation time	18049296769 ps
CPU time	185.02 seconds
Started	Feb 08 09:04:01 AM UTC 25
Finished	Feb 08 09:07:09 AM UTC 25
Peak memory	221292 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2522703302 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.2522703302
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/26.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_stress_all_with_error.645945518
Short name	T559
Test name
Test status
Simulation time	2850872263 ps
CPU time	151.52 seconds
Started	Feb 08 09:04:03 AM UTC 25
Finished	Feb 08 09:06:38 AM UTC 25
Peak memory	220972 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=645945518 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ= xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.645945518
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/26.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_stress_all_with_rand_reset.91416430
Short name	T667
Test name
Test status
Simulation time	5669178245 ps
CPU time	329.27 seconds
Started	Feb 08 09:04:01 AM UTC 25
Finished	Feb 08 09:09:35 AM UTC 25
Peak memory	223020 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=91416430 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xb ar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/ coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_rand_reset.91416430
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/26.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_stress_all_with_reset_error.3713204037
Short name	T491
Test name
Test status
Simulation time	84158465 ps
CPU time	13.24 seconds
Started	Feb 08 09:04:04 AM UTC 25
Finished	Feb 08 09:04:19 AM UTC 25
Peak memory	216744 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3713204037 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_reset_error.3713204037
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/26.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_unmapped_addr.4238807282
Short name	T493
Test name
Test status
Simulation time	1707326584 ps
CPU time	30.41 seconds
Started	Feb 08 09:03:52 AM UTC 25
Finished	Feb 08 09:04:25 AM UTC 25
Peak memory	216788 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4238807282 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xb ar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.4238807282
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/26.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_access_same_device.3012815889
Short name	T298
Test name
Test status
Simulation time	460522753 ps
CPU time	18.01 seconds
Started	Feb 08 09:04:25 AM UTC 25
Finished	Feb 08 09:04:45 AM UTC 25
Peak memory	216812 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3012815889 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/covera ge/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device.3012815889
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/27.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_access_same_device_slow_rsp.2647020332
Short name	T253
Test name
Test status
Simulation time	37305967156 ps
CPU time	382.14 seconds
Started	Feb 08 09:04:26 AM UTC 25
Finished	Feb 08 09:10:54 AM UTC 25
Peak memory	218864 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2647020332 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/ coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device_slow_rsp.2647020332
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/27.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_error_and_unmapped_addr.4249609061
Short name	T511
Test name
Test status
Simulation time	821335083 ps
CPU time	29.06 seconds
Started	Feb 08 09:04:32 AM UTC 25
Finished	Feb 08 09:05:04 AM UTC 25
Peak memory	216748 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4249609061 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/x bar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_addr.4249609061
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/27.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_error_random.665796715
Short name	T508
Test name
Test status
Simulation time	565320386 ps
CPU time	26.54 seconds
Started	Feb 08 09:04:28 AM UTC 25
Finished	Feb 08 09:04:57 AM UTC 25
Peak memory	216808 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=665796715 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ= xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_buil d_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.665796715
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/27.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_random.4184068413
Short name	T195
Test name
Test status
Simulation time	739221792 ps
CPU time	42.16 seconds
Started	Feb 08 09:04:11 AM UTC 25
Finished	Feb 08 09:04:55 AM UTC 25
Peak memory	216752 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4184068413 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_buil d_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random.4184068413
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/27.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_random_large_delays.224727842
Short name	T558
Test name
Test status
Simulation time	36557881907 ps
CPU time	135.61 seconds
Started	Feb 08 09:04:19 AM UTC 25
Finished	Feb 08 09:06:37 AM UTC 25
Peak memory	216880 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=224727842 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/ xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.224727842
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/27.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_random_slow_rsp.3136558178
Short name	T580
Test name
Test status
Simulation time	26930483014 ps
CPU time	162.67 seconds
Started	Feb 08 09:04:20 AM UTC 25
Finished	Feb 08 09:07:05 AM UTC 25
Peak memory	217136 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3136558178 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xba r_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.3136558178
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/27.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_random_zero_delays.1994032144
Short name	T494
Test name
Test status
Simulation time	95325314 ps
CPU time	11.23 seconds
Started	Feb 08 09:04:14 AM UTC 25
Finished	Feb 08 09:04:27 AM UTC 25
Peak memory	216744 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1994032144 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/cov erage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_delays.1994032144
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/27.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_same_source.1348877489
Short name	T504
Test name
Test status
Simulation time	3097017071 ps
CPU time	26.78 seconds
Started	Feb 08 09:04:26 AM UTC 25
Finished	Feb 08 09:04:55 AM UTC 25
Peak memory	216876 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1348877489 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.1348877489
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/27.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_smoke.1599316478
Short name	T489
Test name
Test status
Simulation time	1061719909 ps
CPU time	6.25 seconds
Started	Feb 08 09:04:05 AM UTC 25
Finished	Feb 08 09:04:13 AM UTC 25
Peak memory	217052 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1599316478 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build _mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.1599316478
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/27.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_smoke_large_delays.2893159572
Short name	T499
Test name
Test status
Simulation time	6312248106 ps
CPU time	38.49 seconds
Started	Feb 08 09:04:07 AM UTC 25
Finished	Feb 08 09:04:48 AM UTC 25
Peak memory	217056 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2893159572 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/ xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.2893159572
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/27.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_smoke_slow_rsp.3984162848
Short name	T500
Test name
Test status
Simulation time	9410123607 ps
CPU time	42.49 seconds
Started	Feb 08 09:04:07 AM UTC 25
Finished	Feb 08 09:04:52 AM UTC 25
Peak memory	216856 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3984162848 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.3984162848
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/27.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_smoke_zero_delays.3956305279
Short name	T488
Test name
Test status
Simulation time	24426307 ps
CPU time	3.37 seconds
Started	Feb 08 09:04:05 AM UTC 25
Finished	Feb 08 09:04:11 AM UTC 25
Peak memory	216784 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3956305279 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/cove rage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delays.3956305279
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/27.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_stress_all.2496751961
Short name	T562
Test name
Test status
Simulation time	7380732112 ps
CPU time	124.47 seconds
Started	Feb 08 09:04:34 AM UTC 25
Finished	Feb 08 09:06:42 AM UTC 25
Peak memory	223020 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2496751961 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.2496751961
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/27.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_stress_all_with_error.3222421922
Short name	T518
Test name
Test status
Simulation time	620635552 ps
CPU time	33.03 seconds
Started	Feb 08 09:04:45 AM UTC 25
Finished	Feb 08 09:05:20 AM UTC 25
Peak memory	216744 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3222421922 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.3222421922
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/27.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_stress_all_with_rand_reset.2783603498
Short name	T537
Test name
Test status
Simulation time	332562174 ps
CPU time	72.03 seconds
Started	Feb 08 09:04:37 AM UTC 25
Finished	Feb 08 09:05:51 AM UTC 25
Peak memory	220904 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2783603498 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_rand_reset.2783603498
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/27.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_stress_all_with_reset_error.3067129017
Short name	T762
Test name
Test status
Simulation time	8221968814 ps
CPU time	433.83 seconds
Started	Feb 08 09:04:46 AM UTC 25
Finished	Feb 08 09:12:06 AM UTC 25
Peak memory	233564 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3067129017 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_reset_error.3067129017
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/27.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_unmapped_addr.246524750
Short name	T505
Test name
Test status
Simulation time	470514501 ps
CPU time	22.23 seconds
Started	Feb 08 09:04:30 AM UTC 25
Finished	Feb 08 09:04:55 AM UTC 25
Peak memory	216748 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=246524750 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xba r_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.246524750
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/27.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_access_same_device.1724779208
Short name	T532
Test name
Test status
Simulation time	940424760 ps
CPU time	40.73 seconds
Started	Feb 08 09:04:57 AM UTC 25
Finished	Feb 08 09:05:40 AM UTC 25
Peak memory	218856 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1724779208 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/covera ge/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device.1724779208
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/28.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_access_same_device_slow_rsp.2039596304
Short name	T888
Test name
Test status
Simulation time	134785432872 ps
CPU time	789.56 seconds
Started	Feb 08 09:04:58 AM UTC 25
Finished	Feb 08 09:18:17 AM UTC 25
Peak memory	222856 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2039596304 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/ coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device_slow_rsp.2039596304
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/28.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_error_and_unmapped_addr.2793146464
Short name	T522
Test name
Test status
Simulation time	172830492 ps
CPU time	19.14 seconds
Started	Feb 08 09:05:05 AM UTC 25
Finished	Feb 08 09:05:26 AM UTC 25
Peak memory	216744 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2793146464 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/x bar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_addr.2793146464
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/28.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_error_random.3990499303
Short name	T517
Test name
Test status
Simulation time	663114899 ps
CPU time	16.54 seconds
Started	Feb 08 09:04:58 AM UTC 25
Finished	Feb 08 09:05:16 AM UTC 25
Peak memory	216808 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3990499303 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_bui ld_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.3990499303
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/28.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_random.2999470056
Short name	T515
Test name
Test status
Simulation time	156987339 ps
CPU time	14.54 seconds
Started	Feb 08 09:04:56 AM UTC 25
Finished	Feb 08 09:05:13 AM UTC 25
Peak memory	216816 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2999470056 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_buil d_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random.2999470056
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/28.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_random_large_delays.2956441691
Short name	T136
Test name
Test status
Simulation time	53040969164 ps
CPU time	300.08 seconds
Started	Feb 08 09:04:56 AM UTC 25
Finished	Feb 08 09:10:01 AM UTC 25
Peak memory	218916 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2956441691 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage /xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.2956441691
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/28.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_random_slow_rsp.4032976583
Short name	T619
Test name
Test status
Simulation time	20328971185 ps
CPU time	169.54 seconds
Started	Feb 08 09:04:57 AM UTC 25
Finished	Feb 08 09:07:49 AM UTC 25
Peak memory	217140 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4032976583 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xba r_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.4032976583
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/28.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_random_zero_delays.3375957773
Short name	T526
Test name
Test status
Simulation time	1336683488 ps
CPU time	32.52 seconds
Started	Feb 08 09:04:56 AM UTC 25
Finished	Feb 08 09:05:31 AM UTC 25
Peak memory	216808 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3375957773 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/cov erage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_delays.3375957773
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/28.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_same_source.3326684391
Short name	T514
Test name
Test status
Simulation time	1776475409 ps
CPU time	10.89 seconds
Started	Feb 08 09:04:58 AM UTC 25
Finished	Feb 08 09:05:11 AM UTC 25
Peak memory	216860 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3326684391 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.3326684391
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/28.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_smoke.3864762723
Short name	T502
Test name
Test status
Simulation time	44451279 ps
CPU time	3.09 seconds
Started	Feb 08 09:04:49 AM UTC 25
Finished	Feb 08 09:04:53 AM UTC 25
Peak memory	216792 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3864762723 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build _mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.3864762723
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/28.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_smoke_large_delays.4100235460
Short name	T528
Test name
Test status
Simulation time	5281822080 ps
CPU time	39.56 seconds
Started	Feb 08 09:04:54 AM UTC 25
Finished	Feb 08 09:05:36 AM UTC 25
Peak memory	216796 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4100235460 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/ xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.4100235460
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/28.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_smoke_slow_rsp.4146679020
Short name	T523
Test name
Test status
Simulation time	3645890189 ps
CPU time	31.35 seconds
Started	Feb 08 09:04:54 AM UTC 25
Finished	Feb 08 09:05:28 AM UTC 25
Peak memory	216856 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4146679020 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.4146679020
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/28.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_smoke_zero_delays.1754688886
Short name	T509
Test name
Test status
Simulation time	103961059 ps
CPU time	2.84 seconds
Started	Feb 08 09:04:53 AM UTC 25
Finished	Feb 08 09:04:57 AM UTC 25
Peak memory	216780 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1754688886 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/cove rage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delays.1754688886
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/28.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_stress_all.1861968463
Short name	T597
Test name
Test status
Simulation time	28996263387 ps
CPU time	135.94 seconds
Started	Feb 08 09:05:07 AM UTC 25
Finished	Feb 08 09:07:26 AM UTC 25
Peak memory	220972 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1861968463 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.1861968463
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/28.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_stress_all_with_error.1523477249
Short name	T563
Test name
Test status
Simulation time	1409940960 ps
CPU time	87.93 seconds
Started	Feb 08 09:05:12 AM UTC 25
Finished	Feb 08 09:06:42 AM UTC 25
Peak memory	218648 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1523477249 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.1523477249
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/28.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_stress_all_with_rand_reset.1193995386
Short name	T756
Test name
Test status
Simulation time	3144527990 ps
CPU time	403.6 seconds
Started	Feb 08 09:05:08 AM UTC 25
Finished	Feb 08 09:11:58 AM UTC 25
Peak memory	223024 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1193995386 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_rand_reset.1193995386
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/28.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_stress_all_with_reset_error.363526845
Short name	T548
Test name
Test status
Simulation time	590386580 ps
CPU time	61.07 seconds
Started	Feb 08 09:05:12 AM UTC 25
Finished	Feb 08 09:06:15 AM UTC 25
Peak memory	218696 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=363526845 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ= xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_reset_error.363526845
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/28.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_unmapped_addr.2213982054
Short name	T516
Test name
Test status
Simulation time	314077658 ps
CPU time	11.69 seconds
Started	Feb 08 09:05:01 AM UTC 25
Finished	Feb 08 09:05:15 AM UTC 25
Peak memory	217076 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2213982054 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xb ar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.2213982054
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/28.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_access_same_device.3449720201
Short name	T545
Test name
Test status
Simulation time	1469646273 ps
CPU time	39.25 seconds
Started	Feb 08 09:05:27 AM UTC 25
Finished	Feb 08 09:06:08 AM UTC 25
Peak memory	218792 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3449720201 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/covera ge/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device.3449720201
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/29.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_access_same_device_slow_rsp.4210683418
Short name	T892
Test name
Test status
Simulation time	155722159895 ps
CPU time	872.43 seconds
Started	Feb 08 09:05:29 AM UTC 25
Finished	Feb 08 09:20:11 AM UTC 25
Peak memory	222472 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4210683418 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/ coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device_slow_rsp.4210683418
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/29.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_error_and_unmapped_addr.1013088330
Short name	T540
Test name
Test status
Simulation time	216709634 ps
CPU time	24.39 seconds
Started	Feb 08 09:05:35 AM UTC 25
Finished	Feb 08 09:06:01 AM UTC 25
Peak memory	216812 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1013088330 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/x bar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_addr.1013088330
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/29.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_error_random.3371652947
Short name	T544
Test name
Test status
Simulation time	5564221500 ps
CPU time	32.56 seconds
Started	Feb 08 09:05:31 AM UTC 25
Finished	Feb 08 09:06:06 AM UTC 25
Peak memory	216808 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3371652947 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_bui ld_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.3371652947
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/29.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_random.2968304850
Short name	T527
Test name
Test status
Simulation time	90907003 ps
CPU time	9.67 seconds
Started	Feb 08 09:05:22 AM UTC 25
Finished	Feb 08 09:05:33 AM UTC 25
Peak memory	216524 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2968304850 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_buil d_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random.2968304850
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/29.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_random_large_delays.243668413
Short name	T67
Test name
Test status
Simulation time	12719272105 ps
CPU time	37.65 seconds
Started	Feb 08 09:05:26 AM UTC 25
Finished	Feb 08 09:06:06 AM UTC 25
Peak memory	216876 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=243668413 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/ xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.243668413
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/29.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_random_slow_rsp.1181879489
Short name	T676
Test name
Test status
Simulation time	30592078121 ps
CPU time	256.45 seconds
Started	Feb 08 09:05:26 AM UTC 25
Finished	Feb 08 09:09:47 AM UTC 25
Peak memory	216880 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1181879489 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xba r_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.1181879489
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/29.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_random_zero_delays.504790234
Short name	T535
Test name
Test status
Simulation time	376493754 ps
CPU time	23.03 seconds
Started	Feb 08 09:05:22 AM UTC 25
Finished	Feb 08 09:05:47 AM UTC 25
Peak memory	217064 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=504790234 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/cove rage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_delays.504790234
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/29.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_same_source.3945067340
Short name	T529
Test name
Test status
Simulation time	99525796 ps
CPU time	5.09 seconds
Started	Feb 08 09:05:31 AM UTC 25
Finished	Feb 08 09:05:38 AM UTC 25
Peak memory	216812 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3945067340 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.3945067340
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/29.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_smoke.4463706
Short name	T519
Test name
Test status
Simulation time	121036689 ps
CPU time	4.94 seconds
Started	Feb 08 09:05:14 AM UTC 25
Finished	Feb 08 09:05:20 AM UTC 25
Peak memory	216796 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4463706 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xba r_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mo de.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.4463706
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/29.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_smoke_large_delays.3195085660
Short name	T542
Test name
Test status
Simulation time	17722670854 ps
CPU time	45.73 seconds
Started	Feb 08 09:05:18 AM UTC 25
Finished	Feb 08 09:06:05 AM UTC 25
Peak memory	216860 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3195085660 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/ xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.3195085660
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/29.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_smoke_slow_rsp.580311620
Short name	T157
Test name
Test status
Simulation time	3856413403 ps
CPU time	34.73 seconds
Started	Feb 08 09:05:22 AM UTC 25
Finished	Feb 08 09:05:59 AM UTC 25
Peak memory	216732 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=580311620 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST _SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.580311620
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/29.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_smoke_zero_delays.2869968479
Short name	T520
Test name
Test status
Simulation time	72139847 ps
CPU time	3.25 seconds
Started	Feb 08 09:05:16 AM UTC 25
Finished	Feb 08 09:05:21 AM UTC 25
Peak memory	216780 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2869968479 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/cove rage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delays.2869968479
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/29.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_stress_all.3934897409
Short name	T600
Test name
Test status
Simulation time	4251348813 ps
CPU time	107.73 seconds
Started	Feb 08 09:05:37 AM UTC 25
Finished	Feb 08 09:07:28 AM UTC 25
Peak memory	220972 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3934897409 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.3934897409
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/29.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_stress_all_with_error.1278463345
Short name	T564
Test name
Test status
Simulation time	827350492 ps
CPU time	60.39 seconds
Started	Feb 08 09:05:40 AM UTC 25
Finished	Feb 08 09:06:42 AM UTC 25
Peak memory	219120 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1278463345 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.1278463345
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/29.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_stress_all_with_rand_reset.2554383380
Short name	T538
Test name
Test status
Simulation time	53432247 ps
CPU time	14.44 seconds
Started	Feb 08 09:05:37 AM UTC 25
Finished	Feb 08 09:05:53 AM UTC 25
Peak memory	217072 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2554383380 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_rand_reset.2554383380
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/29.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_stress_all_with_reset_error.3879558848
Short name	T632
Test name
Test status
Simulation time	9297017467 ps
CPU time	162.71 seconds
Started	Feb 08 09:05:41 AM UTC 25
Finished	Feb 08 09:08:27 AM UTC 25
Peak memory	223040 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3879558848 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_reset_error.3879558848
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/29.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_unmapped_addr.1326081528
Short name	T477
Test name
Test status
Simulation time	262869988 ps
CPU time	7.4 seconds
Started	Feb 08 09:05:31 AM UTC 25
Finished	Feb 08 09:05:41 AM UTC 25
Peak memory	216808 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1326081528 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xb ar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.1326081528
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/29.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_access_same_device_slow_rsp.3773529191
Short name	T256
Test name
Test status
Simulation time	54774779014 ps
CPU time	189.7 seconds
Started	Feb 08 08:53:27 AM UTC 25
Finished	Feb 08 08:56:41 AM UTC 25
Peak memory	218960 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3773529191 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/ coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device_slow_rsp.3773529191
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/3.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_error_and_unmapped_addr.147030727
Short name	T108
Test name
Test status
Simulation time	117237279 ps
CPU time	8.18 seconds
Started	Feb 08 08:53:31 AM UTC 25
Finished	Feb 08 08:53:41 AM UTC 25
Peak memory	216800 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=147030727 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ= xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xb ar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr.147030727
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/3.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_error_random.2336593335
Short name	T111
Test name
Test status
Simulation time	522020187 ps
CPU time	17.02 seconds
Started	Feb 08 08:53:27 AM UTC 25
Finished	Feb 08 08:53:46 AM UTC 25
Peak memory	217132 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2336593335 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_bui ld_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.2336593335
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/3.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_random.93040112
Short name	T106
Test name
Test status
Simulation time	1355614269 ps
CPU time	18.62 seconds
Started	Feb 08 08:53:20 AM UTC 25
Finished	Feb 08 08:53:40 AM UTC 25
Peak memory	216748 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=93040112 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xb ar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_ mode.vdb -cm_log /dev/null -cm_name 3.xbar_random.93040112
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/3.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_random_large_delays.1479556843
Short name	T302
Test name
Test status
Simulation time	19559501452 ps
CPU time	126.07 seconds
Started	Feb 08 08:53:23 AM UTC 25
Finished	Feb 08 08:55:32 AM UTC 25
Peak memory	216876 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1479556843 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage /xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.1479556843
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/3.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_random_slow_rsp.1941386685
Short name	T359
Test name
Test status
Simulation time	108205206330 ps
CPU time	225.62 seconds
Started	Feb 08 08:53:24 AM UTC 25
Finished	Feb 08 08:57:13 AM UTC 25
Peak memory	218860 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1941386685 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xba r_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.1941386685
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/3.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_random_zero_delays.646747152
Short name	T107
Test name
Test status
Simulation time	303966109 ps
CPU time	16.55 seconds
Started	Feb 08 08:53:22 AM UTC 25
Finished	Feb 08 08:53:40 AM UTC 25
Peak memory	216808 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=646747152 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/cove rage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_delays.646747152
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/3.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_same_source.2814597921
Short name	T37
Test name
Test status
Simulation time	5856961473 ps
CPU time	44.81 seconds
Started	Feb 08 08:53:27 AM UTC 25
Finished	Feb 08 08:54:14 AM UTC 25
Peak memory	216876 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2814597921 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.2814597921
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/3.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_smoke.1636955405
Short name	T71
Test name
Test status
Simulation time	163451979 ps
CPU time	5.68 seconds
Started	Feb 08 08:53:17 AM UTC 25
Finished	Feb 08 08:53:25 AM UTC 25
Peak memory	217112 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1636955405 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build _mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.1636955405
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/3.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_smoke_large_delays.1299649541
Short name	T333
Test name
Test status
Simulation time	7384497124 ps
CPU time	38.44 seconds
Started	Feb 08 08:53:18 AM UTC 25
Finished	Feb 08 08:53:58 AM UTC 25
Peak memory	216860 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1299649541 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/ xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.1299649541
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/3.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_smoke_slow_rsp.1432403033
Short name	T310
Test name
Test status
Simulation time	3487298580 ps
CPU time	35.13 seconds
Started	Feb 08 08:53:19 AM UTC 25
Finished	Feb 08 08:53:56 AM UTC 25
Peak memory	216860 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1432403033 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.1432403033
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/3.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_smoke_zero_delays.2613699261
Short name	T70
Test name
Test status
Simulation time	79314238 ps
CPU time	2.74 seconds
Started	Feb 08 08:53:18 AM UTC 25
Finished	Feb 08 08:53:22 AM UTC 25
Peak memory	217112 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2613699261 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/cove rage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays.2613699261
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/3.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_stress_all.818763024
Short name	T85
Test name
Test status
Simulation time	44611821160 ps
CPU time	216.04 seconds
Started	Feb 08 08:53:32 AM UTC 25
Finished	Feb 08 08:57:12 AM UTC 25
Peak memory	222952 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=818763024 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_b uild_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.818763024
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/3.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_stress_all_with_error.3060024085
Short name	T308
Test name
Test status
Simulation time	8525270488 ps
CPU time	170.4 seconds
Started	Feb 08 08:53:37 AM UTC 25
Finished	Feb 08 08:56:30 AM UTC 25
Peak memory	221232 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3060024085 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.3060024085
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/3.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_stress_all_with_rand_reset.1653112147
Short name	T32
Test name
Test status
Simulation time	1821058980 ps
CPU time	307.18 seconds
Started	Feb 08 08:53:37 AM UTC 25
Finished	Feb 08 08:58:48 AM UTC 25
Peak memory	222952 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1653112147 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_rand_reset.1653112147
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/3.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_stress_all_with_reset_error.3175230369
Short name	T313
Test name
Test status
Simulation time	1077508983 ps
CPU time	211.56 seconds
Started	Feb 08 08:53:38 AM UTC 25
Finished	Feb 08 08:57:14 AM UTC 25
Peak memory	233560 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3175230369 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_reset_error.3175230369
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/3.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_unmapped_addr.3282642205
Short name	T112
Test name
Test status
Simulation time	81136076 ps
CPU time	16.54 seconds
Started	Feb 08 08:53:29 AM UTC 25
Finished	Feb 08 08:53:47 AM UTC 25
Peak memory	218864 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3282642205 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xb ar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.3282642205
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/3.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_access_same_device.10579754
Short name	T560
Test name
Test status
Simulation time	1932290470 ps
CPU time	42.88 seconds
Started	Feb 08 09:05:54 AM UTC 25
Finished	Feb 08 09:06:39 AM UTC 25
Peak memory	218864 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10579754 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xb ar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage /xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device.10579754
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/30.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_access_same_device_slow_rsp.3974558829
Short name	T742
Test name
Test status
Simulation time	123515226030 ps
CPU time	340.69 seconds
Started	Feb 08 09:06:00 AM UTC 25
Finished	Feb 08 09:11:45 AM UTC 25
Peak memory	219248 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3974558829 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/ coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device_slow_rsp.3974558829
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/30.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_error_and_unmapped_addr.3866015892
Short name	T554
Test name
Test status
Simulation time	939995695 ps
CPU time	27.44 seconds
Started	Feb 08 09:06:04 AM UTC 25
Finished	Feb 08 09:06:34 AM UTC 25
Peak memory	216744 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3866015892 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/x bar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_addr.3866015892
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/30.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_error_random.1095292394
Short name	T567
Test name
Test status
Simulation time	1569354067 ps
CPU time	40.23 seconds
Started	Feb 08 09:06:02 AM UTC 25
Finished	Feb 08 09:06:44 AM UTC 25
Peak memory	217056 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1095292394 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_bui ld_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.1095292394
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/30.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_random.1232126360
Short name	T549
Test name
Test status
Simulation time	684553477 ps
CPU time	26.54 seconds
Started	Feb 08 09:05:47 AM UTC 25
Finished	Feb 08 09:06:16 AM UTC 25
Peak memory	216816 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1232126360 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_buil d_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random.1232126360
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/30.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_random_large_delays.3783874678
Short name	T561
Test name
Test status
Simulation time	12745301201 ps
CPU time	48.71 seconds
Started	Feb 08 09:05:49 AM UTC 25
Finished	Feb 08 09:06:40 AM UTC 25
Peak memory	217196 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3783874678 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage /xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.3783874678
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/30.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_random_slow_rsp.1755718463
Short name	T162
Test name
Test status
Simulation time	31990141482 ps
CPU time	228 seconds
Started	Feb 08 09:05:52 AM UTC 25
Finished	Feb 08 09:09:44 AM UTC 25
Peak memory	218928 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1755718463 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xba r_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.1755718463
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/30.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_random_zero_delays.1375562020
Short name	T539
Test name
Test status
Simulation time	36392091 ps
CPU time	8.23 seconds
Started	Feb 08 09:05:49 AM UTC 25
Finished	Feb 08 09:05:59 AM UTC 25
Peak memory	216936 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1375562020 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/cov erage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_delays.1375562020
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/30.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_same_source.1697121365
Short name	T541
Test name
Test status
Simulation time	19653091 ps
CPU time	2.58 seconds
Started	Feb 08 09:06:00 AM UTC 25
Finished	Feb 08 09:06:04 AM UTC 25
Peak memory	216808 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1697121365 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.1697121365
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/30.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_smoke.1732142394
Short name	T531
Test name
Test status
Simulation time	136502468 ps
CPU time	3.31 seconds
Started	Feb 08 09:05:41 AM UTC 25
Finished	Feb 08 09:05:46 AM UTC 25
Peak memory	216792 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1732142394 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build _mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.1732142394
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/30.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_smoke_large_delays.3249953899
Short name	T553
Test name
Test status
Simulation time	4300338201 ps
CPU time	48.37 seconds
Started	Feb 08 09:05:43 AM UTC 25
Finished	Feb 08 09:06:33 AM UTC 25
Peak memory	216796 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3249953899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/ xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.3249953899
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/30.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_smoke_slow_rsp.1249731935
Short name	T550
Test name
Test status
Simulation time	3266951469 ps
CPU time	28.85 seconds
Started	Feb 08 09:05:46 AM UTC 25
Finished	Feb 08 09:06:17 AM UTC 25
Peak memory	216856 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1249731935 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.1249731935
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/30.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_smoke_zero_delays.2054174502
Short name	T536
Test name
Test status
Simulation time	32594759 ps
CPU time	3.55 seconds
Started	Feb 08 09:05:43 AM UTC 25
Finished	Feb 08 09:05:48 AM UTC 25
Peak memory	216784 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2054174502 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/cove rage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delays.2054174502
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/30.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_stress_all.80750275
Short name	T135
Test name
Test status
Simulation time	17170855022 ps
CPU time	177.99 seconds
Started	Feb 08 09:06:07 AM UTC 25
Finished	Feb 08 09:09:08 AM UTC 25
Peak memory	220976 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=80750275 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xb ar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_bu ild_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.80750275
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/30.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_stress_all_with_error.1896543558
Short name	T555
Test name
Test status
Simulation time	1285808668 ps
CPU time	25.96 seconds
Started	Feb 08 09:06:07 AM UTC 25
Finished	Feb 08 09:06:35 AM UTC 25
Peak memory	217072 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1896543558 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.1896543558
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/30.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_stress_all_with_rand_reset.2533529812
Short name	T140
Test name
Test status
Simulation time	1739325915 ps
CPU time	310.3 seconds
Started	Feb 08 09:06:07 AM UTC 25
Finished	Feb 08 09:11:22 AM UTC 25
Peak memory	222956 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2533529812 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_rand_reset.2533529812
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/30.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_stress_all_with_reset_error.1532301453
Short name	T684
Test name
Test status
Simulation time	7454642440 ps
CPU time	232.57 seconds
Started	Feb 08 09:06:07 AM UTC 25
Finished	Feb 08 09:10:04 AM UTC 25
Peak memory	233884 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1532301453 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_reset_error.1532301453
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/30.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_unmapped_addr.2951391999
Short name	T557
Test name
Test status
Simulation time	604507810 ps
CPU time	32.43 seconds
Started	Feb 08 09:06:02 AM UTC 25
Finished	Feb 08 09:06:37 AM UTC 25
Peak memory	216808 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2951391999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xb ar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.2951391999
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/30.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_access_same_device.3585306407
Short name	T188
Test name
Test status
Simulation time	1690010160 ps
CPU time	56.88 seconds
Started	Feb 08 09:06:34 AM UTC 25
Finished	Feb 08 09:07:33 AM UTC 25
Peak memory	218856 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3585306407 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/covera ge/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device.3585306407
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/31.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_access_same_device_slow_rsp.1512431634
Short name	T613
Test name
Test status
Simulation time	7750334669 ps
CPU time	68.05 seconds
Started	Feb 08 09:06:36 AM UTC 25
Finished	Feb 08 09:07:46 AM UTC 25
Peak memory	217004 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1512431634 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/ coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device_slow_rsp.1512431634
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/31.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_error_and_unmapped_addr.795214977
Short name	T576
Test name
Test status
Simulation time	485938007 ps
CPU time	17.7 seconds
Started	Feb 08 09:06:39 AM UTC 25
Finished	Feb 08 09:06:58 AM UTC 25
Peak memory	216796 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=795214977 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ= xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xb ar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_addr.795214977
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/31.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_error_random.1648198169
Short name	T574
Test name
Test status
Simulation time	1636210654 ps
CPU time	14.71 seconds
Started	Feb 08 09:06:36 AM UTC 25
Finished	Feb 08 09:06:52 AM UTC 25
Peak memory	217124 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1648198169 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_bui ld_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.1648198169
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/31.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_random.918761979
Short name	T556
Test name
Test status
Simulation time	369487006 ps
CPU time	17.14 seconds
Started	Feb 08 09:06:16 AM UTC 25
Finished	Feb 08 09:06:35 AM UTC 25
Peak memory	217068 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=918761979 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build _mode.vdb -cm_log /dev/null -cm_name 31.xbar_random.918761979
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/31.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_random_large_delays.2622228270
Short name	T158
Test name
Test status
Simulation time	10410779362 ps
CPU time	52.49 seconds
Started	Feb 08 09:06:21 AM UTC 25
Finished	Feb 08 09:07:15 AM UTC 25
Peak memory	217196 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2622228270 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage /xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.2622228270
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/31.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_random_slow_rsp.1857546677
Short name	T704
Test name
Test status
Simulation time	27693351081 ps
CPU time	243.76 seconds
Started	Feb 08 09:06:29 AM UTC 25
Finished	Feb 08 09:10:37 AM UTC 25
Peak memory	219252 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1857546677 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xba r_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.1857546677
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/31.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_random_zero_delays.2449955640
Short name	T565
Test name
Test status
Simulation time	175371176 ps
CPU time	23.65 seconds
Started	Feb 08 09:06:17 AM UTC 25
Finished	Feb 08 09:06:43 AM UTC 25
Peak memory	216808 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2449955640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/cov erage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_delays.2449955640
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/31.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_same_source.231819963
Short name	T579
Test name
Test status
Simulation time	270236772 ps
CPU time	26.5 seconds
Started	Feb 08 09:06:36 AM UTC 25
Finished	Feb 08 09:07:04 AM UTC 25
Peak memory	216744 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=231819963 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.231819963
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/31.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_smoke.3313866490
Short name	T547
Test name
Test status
Simulation time	457225519 ps
CPU time	3.63 seconds
Started	Feb 08 09:06:09 AM UTC 25
Finished	Feb 08 09:06:14 AM UTC 25
Peak memory	216788 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3313866490 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build _mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.3313866490
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/31.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_smoke_large_delays.220787349
Short name	T585
Test name
Test status
Simulation time	14232187314 ps
CPU time	52.99 seconds
Started	Feb 08 09:06:16 AM UTC 25
Finished	Feb 08 09:07:11 AM UTC 25
Peak memory	216860 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=220787349 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/x bar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.220787349
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/31.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_smoke_slow_rsp.2539061704
Short name	T575
Test name
Test status
Simulation time	5606516831 ps
CPU time	35.87 seconds
Started	Feb 08 09:06:16 AM UTC 25
Finished	Feb 08 09:06:54 AM UTC 25
Peak memory	216860 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2539061704 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.2539061704
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/31.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_smoke_zero_delays.3344132012
Short name	T551
Test name
Test status
Simulation time	29005615 ps
CPU time	3.36 seconds
Started	Feb 08 09:06:15 AM UTC 25
Finished	Feb 08 09:06:19 AM UTC 25
Peak memory	216784 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3344132012 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/cove rage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delays.3344132012
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/31.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_stress_all.363857607
Short name	T605
Test name
Test status
Simulation time	1707307106 ps
CPU time	54.11 seconds
Started	Feb 08 09:06:39 AM UTC 25
Finished	Feb 08 09:07:35 AM UTC 25
Peak memory	218796 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=363857607 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_b uild_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.363857607
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/31.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_stress_all_with_error.4151085797
Short name	T673
Test name
Test status
Simulation time	4903627566 ps
CPU time	175.79 seconds
Started	Feb 08 09:06:41 AM UTC 25
Finished	Feb 08 09:09:41 AM UTC 25
Peak memory	221228 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4151085797 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.4151085797
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/31.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_stress_all_with_reset_error.159862568
Short name	T594
Test name
Test status
Simulation time	162283200 ps
CPU time	34.62 seconds
Started	Feb 08 09:06:43 AM UTC 25
Finished	Feb 08 09:07:20 AM UTC 25
Peak memory	216744 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=159862568 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ= xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_reset_error.159862568
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/31.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_unmapped_addr.3878800535
Short name	T234
Test name
Test status
Simulation time	774957410 ps
CPU time	31.13 seconds
Started	Feb 08 09:06:37 AM UTC 25
Finished	Feb 08 09:07:10 AM UTC 25
Peak memory	216816 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3878800535 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xb ar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.3878800535
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/31.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_access_same_device.563362515
Short name	T595
Test name
Test status
Simulation time	1032523167 ps
CPU time	27.82 seconds
Started	Feb 08 09:06:50 AM UTC 25
Finished	Feb 08 09:07:20 AM UTC 25
Peak memory	216740 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=563362515 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverag e/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device.563362515
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/32.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_access_same_device_slow_rsp.3047935300
Short name	T733
Test name
Test status
Simulation time	23350919279 ps
CPU time	278.22 seconds
Started	Feb 08 09:06:50 AM UTC 25
Finished	Feb 08 09:11:33 AM UTC 25
Peak memory	218928 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3047935300 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/ coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device_slow_rsp.3047935300
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/32.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_error_and_unmapped_addr.3792249239
Short name	T593
Test name
Test status
Simulation time	260719961 ps
CPU time	13.77 seconds
Started	Feb 08 09:07:02 AM UTC 25
Finished	Feb 08 09:07:17 AM UTC 25
Peak memory	216812 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3792249239 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/x bar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_addr.3792249239
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/32.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_error_random.1182418193
Short name	T586
Test name
Test status
Simulation time	922998761 ps
CPU time	15.18 seconds
Started	Feb 08 09:06:54 AM UTC 25
Finished	Feb 08 09:07:11 AM UTC 25
Peak memory	216740 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1182418193 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_bui ld_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.1182418193
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/32.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_random.127922223
Short name	T592
Test name
Test status
Simulation time	716976052 ps
CPU time	27.65 seconds
Started	Feb 08 09:06:46 AM UTC 25
Finished	Feb 08 09:07:16 AM UTC 25
Peak memory	216412 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=127922223 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build _mode.vdb -cm_log /dev/null -cm_name 32.xbar_random.127922223
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/32.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_random_large_delays.1587436944
Short name	T596
Test name
Test status
Simulation time	7273917414 ps
CPU time	32.09 seconds
Started	Feb 08 09:06:47 AM UTC 25
Finished	Feb 08 09:07:21 AM UTC 25
Peak memory	217132 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1587436944 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage /xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.1587436944
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/32.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_random_slow_rsp.1298385940
Short name	T668
Test name
Test status
Simulation time	50398865349 ps
CPU time	166.65 seconds
Started	Feb 08 09:06:47 AM UTC 25
Finished	Feb 08 09:09:37 AM UTC 25
Peak memory	216880 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1298385940 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xba r_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.1298385940
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/32.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_random_zero_delays.641926852
Short name	T589
Test name
Test status
Simulation time	141433819 ps
CPU time	24.62 seconds
Started	Feb 08 09:06:47 AM UTC 25
Finished	Feb 08 09:07:14 AM UTC 25
Peak memory	216808 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=641926852 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/cove rage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_delays.641926852
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/32.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_same_source.4218870883
Short name	T582
Test name
Test status
Simulation time	131849088 ps
CPU time	13.24 seconds
Started	Feb 08 09:06:53 AM UTC 25
Finished	Feb 08 09:07:08 AM UTC 25
Peak memory	216812 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4218870883 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.4218870883
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/32.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_smoke.2453769237
Short name	T571
Test name
Test status
Simulation time	29451167 ps
CPU time	3.39 seconds
Started	Feb 08 09:06:43 AM UTC 25
Finished	Feb 08 09:06:48 AM UTC 25
Peak memory	217048 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2453769237 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build _mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.2453769237
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/32.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_smoke_large_delays.2960347555
Short name	T271
Test name
Test status
Simulation time	7942317092 ps
CPU time	34.85 seconds
Started	Feb 08 09:06:44 AM UTC 25
Finished	Feb 08 09:07:21 AM UTC 25
Peak memory	216860 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2960347555 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/ xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.2960347555
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/32.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_smoke_slow_rsp.3723531845
Short name	T617
Test name
Test status
Simulation time	14998346308 ps
CPU time	60.4 seconds
Started	Feb 08 09:06:46 AM UTC 25
Finished	Feb 08 09:07:49 AM UTC 25
Peak memory	216384 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3723531845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.3723531845
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/32.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_smoke_zero_delays.1863842065
Short name	T572
Test name
Test status
Simulation time	27073864 ps
CPU time	2.73 seconds
Started	Feb 08 09:06:44 AM UTC 25
Finished	Feb 08 09:06:49 AM UTC 25
Peak memory	216720 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1863842065 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/cove rage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delays.1863842065
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/32.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_stress_all.335049792
Short name	T152
Test name
Test status
Simulation time	3897294945 ps
CPU time	59.3 seconds
Started	Feb 08 09:07:02 AM UTC 25
Finished	Feb 08 09:08:03 AM UTC 25
Peak memory	218860 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=335049792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_b uild_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.335049792
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/32.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_stress_all_with_error.4079240181
Short name	T660
Test name
Test status
Simulation time	3732399297 ps
CPU time	135.75 seconds
Started	Feb 08 09:07:06 AM UTC 25
Finished	Feb 08 09:09:25 AM UTC 25
Peak memory	220968 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4079240181 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.4079240181
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/32.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_stress_all_with_rand_reset.3165088052
Short name	T659
Test name
Test status
Simulation time	298327334 ps
CPU time	136.98 seconds
Started	Feb 08 09:07:05 AM UTC 25
Finished	Feb 08 09:09:25 AM UTC 25
Peak memory	220908 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3165088052 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_rand_reset.3165088052
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/32.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_stress_all_with_reset_error.741810353
Short name	T616
Test name
Test status
Simulation time	64253364 ps
CPU time	38.75 seconds
Started	Feb 08 09:07:08 AM UTC 25
Finished	Feb 08 09:07:48 AM UTC 25
Peak memory	221224 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=741810353 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ= xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_reset_error.741810353
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/32.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_unmapped_addr.966838682
Short name	T581
Test name
Test status
Simulation time	267089932 ps
CPU time	6.77 seconds
Started	Feb 08 09:06:59 AM UTC 25
Finished	Feb 08 09:07:07 AM UTC 25
Peak memory	216808 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=966838682 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xba r_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.966838682
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/32.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_access_same_device.3503403047
Short name	T603
Test name
Test status
Simulation time	332409356 ps
CPU time	12.93 seconds
Started	Feb 08 09:07:14 AM UTC 25
Finished	Feb 08 09:07:29 AM UTC 25
Peak memory	217068 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3503403047 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/covera ge/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device.3503403047
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/33.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_access_same_device_slow_rsp.3781556574
Short name	T881
Test name
Test status
Simulation time	64724390493 ps
CPU time	546.2 seconds
Started	Feb 08 09:07:14 AM UTC 25
Finished	Feb 08 09:16:27 AM UTC 25
Peak memory	220488 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3781556574 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/ coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device_slow_rsp.3781556574
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/33.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_error_and_unmapped_addr.936868351
Short name	T620
Test name
Test status
Simulation time	4796258507 ps
CPU time	30.43 seconds
Started	Feb 08 09:07:17 AM UTC 25
Finished	Feb 08 09:07:50 AM UTC 25
Peak memory	217120 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=936868351 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ= xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xb ar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_addr.936868351
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/33.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_error_random.2361779991
Short name	T601
Test name
Test status
Simulation time	84225210 ps
CPU time	10.62 seconds
Started	Feb 08 09:07:16 AM UTC 25
Finished	Feb 08 09:07:28 AM UTC 25
Peak memory	216624 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2361779991 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_bui ld_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.2361779991
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/33.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_random.3826294715
Short name	T604
Test name
Test status
Simulation time	183497404 ps
CPU time	18.47 seconds
Started	Feb 08 09:07:12 AM UTC 25
Finished	Feb 08 09:07:33 AM UTC 25
Peak memory	217140 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3826294715 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_buil d_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random.3826294715
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/33.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_random_large_delays.2423118839
Short name	T646
Test name
Test status
Simulation time	25720343015 ps
CPU time	99.32 seconds
Started	Feb 08 09:07:13 AM UTC 25
Finished	Feb 08 09:08:54 AM UTC 25
Peak memory	217136 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2423118839 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage /xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.2423118839
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/33.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_random_slow_rsp.3178830240
Short name	T615
Test name
Test status
Simulation time	3936859495 ps
CPU time	33.78 seconds
Started	Feb 08 09:07:13 AM UTC 25
Finished	Feb 08 09:07:48 AM UTC 25
Peak memory	216876 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3178830240 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xba r_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.3178830240
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/33.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_random_zero_delays.507358158
Short name	T606
Test name
Test status
Simulation time	212831477 ps
CPU time	21.12 seconds
Started	Feb 08 09:07:12 AM UTC 25
Finished	Feb 08 09:07:35 AM UTC 25
Peak memory	216936 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=507358158 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/cove rage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_delays.507358158
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/33.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_same_source.1729788984
Short name	T602
Test name
Test status
Simulation time	181029833 ps
CPU time	10.71 seconds
Started	Feb 08 09:07:16 AM UTC 25
Finished	Feb 08 09:07:28 AM UTC 25
Peak memory	216436 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1729788984 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.1729788984
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/33.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_smoke.2870554100
Short name	T591
Test name
Test status
Simulation time	124541313 ps
CPU time	3.49 seconds
Started	Feb 08 09:07:09 AM UTC 25
Finished	Feb 08 09:07:15 AM UTC 25
Peak memory	217048 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2870554100 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build _mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.2870554100
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/33.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_smoke_large_delays.1116022033
Short name	T618
Test name
Test status
Simulation time	7757027419 ps
CPU time	36.26 seconds
Started	Feb 08 09:07:11 AM UTC 25
Finished	Feb 08 09:07:49 AM UTC 25
Peak memory	216860 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1116022033 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/ xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.1116022033
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/33.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_smoke_slow_rsp.549588120
Short name	T609
Test name
Test status
Simulation time	4112657651 ps
CPU time	28.81 seconds
Started	Feb 08 09:07:11 AM UTC 25
Finished	Feb 08 09:07:41 AM UTC 25
Peak memory	216860 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=549588120 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST _SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.549588120
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/33.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_smoke_zero_delays.2874933390
Short name	T590
Test name
Test status
Simulation time	26596275 ps
CPU time	2.91 seconds
Started	Feb 08 09:07:09 AM UTC 25
Finished	Feb 08 09:07:14 AM UTC 25
Peak memory	217044 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2874933390 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/cove rage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delays.2874933390
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/33.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_stress_all.1826541398
Short name	T628
Test name
Test status
Simulation time	1090586219 ps
CPU time	40.63 seconds
Started	Feb 08 09:07:17 AM UTC 25
Finished	Feb 08 09:08:00 AM UTC 25
Peak memory	218860 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1826541398 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.1826541398
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/33.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_stress_all_with_error.3467315723
Short name	T625
Test name
Test status
Simulation time	4230288412 ps
CPU time	35.03 seconds
Started	Feb 08 09:07:21 AM UTC 25
Finished	Feb 08 09:07:58 AM UTC 25
Peak memory	217192 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3467315723 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.3467315723
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/33.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_stress_all_with_rand_reset.1043113458
Short name	T235
Test name
Test status
Simulation time	622998284 ps
CPU time	296.47 seconds
Started	Feb 08 09:07:19 AM UTC 25
Finished	Feb 08 09:12:20 AM UTC 25
Peak memory	222956 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1043113458 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_rand_reset.1043113458
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/33.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_unmapped_addr.3785374476
Short name	T610
Test name
Test status
Simulation time	3329603829 ps
CPU time	24.15 seconds
Started	Feb 08 09:07:16 AM UTC 25
Finished	Feb 08 09:07:42 AM UTC 25
Peak memory	217204 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3785374476 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xb ar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.3785374476
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/33.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_access_same_device.843076468
Short name	T607
Test name
Test status
Simulation time	17289184 ps
CPU time	3.79 seconds
Started	Feb 08 09:07:31 AM UTC 25
Finished	Feb 08 09:07:36 AM UTC 25
Peak memory	216740 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=843076468 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverag e/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device.843076468
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/34.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_access_same_device_slow_rsp.2171516204
Short name	T166
Test name
Test status
Simulation time	178033894734 ps
CPU time	601.07 seconds
Started	Feb 08 09:07:31 AM UTC 25
Finished	Feb 08 09:17:39 AM UTC 25
Peak memory	220488 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2171516204 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/ coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device_slow_rsp.2171516204
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/34.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_error_and_unmapped_addr.3447863827
Short name	T614
Test name
Test status
Simulation time	224446045 ps
CPU time	9.47 seconds
Started	Feb 08 09:07:37 AM UTC 25
Finished	Feb 08 09:07:48 AM UTC 25
Peak memory	216808 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3447863827 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/x bar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_addr.3447863827
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/34.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_error_random.2674026089
Short name	T621
Test name
Test status
Simulation time	129040524 ps
CPU time	14.49 seconds
Started	Feb 08 09:07:34 AM UTC 25
Finished	Feb 08 09:07:50 AM UTC 25
Peak memory	216720 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2674026089 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_bui ld_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.2674026089
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/34.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_random.4204702594
Short name	T624
Test name
Test status
Simulation time	167085911 ps
CPU time	22.57 seconds
Started	Feb 08 09:07:29 AM UTC 25
Finished	Feb 08 09:07:53 AM UTC 25
Peak memory	216752 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4204702594 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_buil d_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random.4204702594
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/34.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_random_large_delays.104788803
Short name	T638
Test name
Test status
Simulation time	9133859414 ps
CPU time	62.55 seconds
Started	Feb 08 09:07:29 AM UTC 25
Finished	Feb 08 09:08:34 AM UTC 25
Peak memory	216876 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=104788803 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/ xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.104788803
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/34.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_random_slow_rsp.860479570
Short name	T636
Test name
Test status
Simulation time	5963156365 ps
CPU time	59.45 seconds
Started	Feb 08 09:07:31 AM UTC 25
Finished	Feb 08 09:08:32 AM UTC 25
Peak memory	217132 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=860479570 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST _SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.860479570
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/34.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_random_zero_delays.3645259753
Short name	T611
Test name
Test status
Simulation time	87853756 ps
CPU time	13.13 seconds
Started	Feb 08 09:07:29 AM UTC 25
Finished	Feb 08 09:07:44 AM UTC 25
Peak memory	216808 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3645259753 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/cov erage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_delays.3645259753
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/34.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_same_source.584085253
Short name	T608
Test name
Test status
Simulation time	119317683 ps
CPU time	3.95 seconds
Started	Feb 08 09:07:34 AM UTC 25
Finished	Feb 08 09:07:40 AM UTC 25
Peak memory	216692 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=584085253 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.584085253
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/34.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_smoke.3298467707
Short name	T573
Test name
Test status
Simulation time	106559464 ps
CPU time	3.31 seconds
Started	Feb 08 09:07:23 AM UTC 25
Finished	Feb 08 09:07:28 AM UTC 25
Peak memory	216792 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3298467707 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build _mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.3298467707
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/34.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_smoke_large_delays.793937134
Short name	T645
Test name
Test status
Simulation time	23560740277 ps
CPU time	84.03 seconds
Started	Feb 08 09:07:27 AM UTC 25
Finished	Feb 08 09:08:54 AM UTC 25
Peak memory	216924 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=793937134 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/x bar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.793937134
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/34.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_smoke_slow_rsp.1908531445
Short name	T249
Test name
Test status
Simulation time	13626272841 ps
CPU time	39.67 seconds
Started	Feb 08 09:07:29 AM UTC 25
Finished	Feb 08 09:08:10 AM UTC 25
Peak memory	216860 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1908531445 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.1908531445
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/34.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_smoke_zero_delays.1779183957
Short name	T599
Test name
Test status
Simulation time	53608029 ps
CPU time	3.33 seconds
Started	Feb 08 09:07:23 AM UTC 25
Finished	Feb 08 09:07:28 AM UTC 25
Peak memory	217044 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1779183957 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/cove rage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delays.1779183957
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/34.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_stress_all.1750980159
Short name	T647
Test name
Test status
Simulation time	552492481 ps
CPU time	78.68 seconds
Started	Feb 08 09:07:37 AM UTC 25
Finished	Feb 08 09:08:58 AM UTC 25
Peak memory	220844 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1750980159 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.1750980159
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/34.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_stress_all_with_error.3271816190
Short name	T643
Test name
Test status
Simulation time	595451231 ps
CPU time	63.67 seconds
Started	Feb 08 09:07:43 AM UTC 25
Finished	Feb 08 09:08:49 AM UTC 25
Peak memory	218792 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3271816190 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.3271816190
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/34.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_stress_all_with_rand_reset.3463130385
Short name	T666
Test name
Test status
Simulation time	255850742 ps
CPU time	109.04 seconds
Started	Feb 08 09:07:41 AM UTC 25
Finished	Feb 08 09:09:33 AM UTC 25
Peak memory	220908 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3463130385 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_rand_reset.3463130385
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/34.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_stress_all_with_reset_error.4257856020
Short name	T731
Test name
Test status
Simulation time	2320473078 ps
CPU time	222.72 seconds
Started	Feb 08 09:07:43 AM UTC 25
Finished	Feb 08 09:11:29 AM UTC 25
Peak memory	233628 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4257856020 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_reset_error.4257856020
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/34.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_unmapped_addr.1299817807
Short name	T246
Test name
Test status
Simulation time	639895067 ps
CPU time	31.14 seconds
Started	Feb 08 09:07:35 AM UTC 25
Finished	Feb 08 09:08:09 AM UTC 25
Peak memory	216744 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1299817807 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xb ar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.1299817807
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/34.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_access_same_device.499919509
Short name	T244
Test name
Test status
Simulation time	65561402 ps
CPU time	12.92 seconds
Started	Feb 08 09:07:50 AM UTC 25
Finished	Feb 08 09:08:05 AM UTC 25
Peak memory	216804 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=499919509 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverag e/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device.499919509
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/35.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_access_same_device_slow_rsp.1346647609
Short name	T713
Test name
Test status
Simulation time	24516978826 ps
CPU time	179.95 seconds
Started	Feb 08 09:07:52 AM UTC 25
Finished	Feb 08 09:10:55 AM UTC 25
Peak memory	218868 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1346647609 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/ coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device_slow_rsp.1346647609
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/35.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_error_and_unmapped_addr.2968261545
Short name	T248
Test name
Test status
Simulation time	307803250 ps
CPU time	15.23 seconds
Started	Feb 08 09:07:52 AM UTC 25
Finished	Feb 08 09:08:09 AM UTC 25
Peak memory	216808 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2968261545 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/x bar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_addr.2968261545
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/35.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_error_random.3298094485
Short name	T627
Test name
Test status
Simulation time	308816768 ps
CPU time	5.83 seconds
Started	Feb 08 09:07:52 AM UTC 25
Finished	Feb 08 09:08:00 AM UTC 25
Peak memory	216804 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3298094485 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_bui ld_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.3298094485
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/35.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_random.487770595
Short name	T160
Test name
Test status
Simulation time	289178847 ps
CPU time	12.74 seconds
Started	Feb 08 09:07:50 AM UTC 25
Finished	Feb 08 09:08:05 AM UTC 25
Peak memory	216808 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=487770595 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build _mode.vdb -cm_log /dev/null -cm_name 35.xbar_random.487770595
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/35.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_random_large_delays.168645869
Short name	T776
Test name
Test status
Simulation time	92264011108 ps
CPU time	271.52 seconds
Started	Feb 08 09:07:50 AM UTC 25
Finished	Feb 08 09:12:26 AM UTC 25
Peak memory	216888 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=168645869 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/ xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.168645869
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/35.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_random_slow_rsp.3965879208
Short name	T161
Test name
Test status
Simulation time	13304321858 ps
CPU time	112.2 seconds
Started	Feb 08 09:07:50 AM UTC 25
Finished	Feb 08 09:09:45 AM UTC 25
Peak memory	216876 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3965879208 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xba r_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.3965879208
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/35.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_random_zero_delays.1430385470
Short name	T630
Test name
Test status
Simulation time	255886032 ps
CPU time	27.62 seconds
Started	Feb 08 09:07:50 AM UTC 25
Finished	Feb 08 09:08:20 AM UTC 25
Peak memory	216808 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1430385470 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/cov erage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_delays.1430385470
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/35.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_same_source.3758503145
Short name	T251
Test name
Test status
Simulation time	804259642 ps
CPU time	22.48 seconds
Started	Feb 08 09:07:52 AM UTC 25
Finished	Feb 08 09:08:16 AM UTC 25
Peak memory	216748 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3758503145 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.3758503145
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/35.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_smoke.2764590566
Short name	T159
Test name
Test status
Simulation time	245123750 ps
CPU time	4.56 seconds
Started	Feb 08 09:07:45 AM UTC 25
Finished	Feb 08 09:07:51 AM UTC 25
Peak memory	217048 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2764590566 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build _mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.2764590566
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/35.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_smoke_large_delays.3582967520
Short name	T635
Test name
Test status
Simulation time	7241447322 ps
CPU time	42.51 seconds
Started	Feb 08 09:07:47 AM UTC 25
Finished	Feb 08 09:08:31 AM UTC 25
Peak memory	216864 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3582967520 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/ xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.3582967520
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/35.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_smoke_slow_rsp.3135857586
Short name	T641
Test name
Test status
Simulation time	14399828469 ps
CPU time	47.76 seconds
Started	Feb 08 09:07:50 AM UTC 25
Finished	Feb 08 09:08:40 AM UTC 25
Peak memory	217180 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3135857586 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.3135857586
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/35.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_smoke_zero_delays.1938306619
Short name	T623
Test name
Test status
Simulation time	150885731 ps
CPU time	3.13 seconds
Started	Feb 08 09:07:47 AM UTC 25
Finished	Feb 08 09:07:52 AM UTC 25
Peak memory	216780 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1938306619 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/cove rage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delays.1938306619
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/35.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all.1213142573
Short name	T139
Test name
Test status
Simulation time	24096527334 ps
CPU time	195.25 seconds
Started	Feb 08 09:07:54 AM UTC 25
Finished	Feb 08 09:11:12 AM UTC 25
Peak memory	221228 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1213142573 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.1213142573
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/35.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all_with_error.3103623980
Short name	T652
Test name
Test status
Simulation time	936934710 ps
CPU time	62.27 seconds
Started	Feb 08 09:08:01 AM UTC 25
Finished	Feb 08 09:09:05 AM UTC 25
Peak memory	219096 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3103623980 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.3103623980
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/35.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all_with_rand_reset.2569548606
Short name	T236
Test name
Test status
Simulation time	1760404786 ps
CPU time	353.21 seconds
Started	Feb 08 09:07:59 AM UTC 25
Finished	Feb 08 09:13:57 AM UTC 25
Peak memory	223328 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2569548606 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_rand_reset.2569548606
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/35.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all_with_reset_error.1553806205
Short name	T683
Test name
Test status
Simulation time	294321345 ps
CPU time	118.2 seconds
Started	Feb 08 09:08:01 AM UTC 25
Finished	Feb 08 09:10:02 AM UTC 25
Peak memory	223184 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1553806205 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_reset_error.1553806205
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/35.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_unmapped_addr.2599053934
Short name	T626
Test name
Test status
Simulation time	20285448 ps
CPU time	4.9 seconds
Started	Feb 08 09:07:52 AM UTC 25
Finished	Feb 08 09:07:59 AM UTC 25
Peak memory	217068 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2599053934 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xb ar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.2599053934
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/35.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_access_same_device.4272402747
Short name	T631
Test name
Test status
Simulation time	244874282 ps
CPU time	7.69 seconds
Started	Feb 08 09:08:12 AM UTC 25
Finished	Feb 08 09:08:22 AM UTC 25
Peak memory	217068 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4272402747 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/covera ge/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device.4272402747
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/36.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_access_same_device_slow_rsp.1382108647
Short name	T883
Test name
Test status
Simulation time	157923113157 ps
CPU time	508.76 seconds
Started	Feb 08 09:08:15 AM UTC 25
Finished	Feb 08 09:16:51 AM UTC 25
Peak memory	219312 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1382108647 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/ coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device_slow_rsp.1382108647
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/36.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_error_and_unmapped_addr.2752479605
Short name	T633
Test name
Test status
Simulation time	89812504 ps
CPU time	3.68 seconds
Started	Feb 08 09:08:23 AM UTC 25
Finished	Feb 08 09:08:28 AM UTC 25
Peak memory	216736 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2752479605 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/x bar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_addr.2752479605
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/36.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_error_random.1953828949
Short name	T651
Test name
Test status
Simulation time	1738030146 ps
CPU time	41.19 seconds
Started	Feb 08 09:08:20 AM UTC 25
Finished	Feb 08 09:09:04 AM UTC 25
Peak memory	216744 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1953828949 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_bui ld_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.1953828949
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/36.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_random.1347680976
Short name	T637
Test name
Test status
Simulation time	150674846 ps
CPU time	21.73 seconds
Started	Feb 08 09:08:09 AM UTC 25
Finished	Feb 08 09:08:33 AM UTC 25
Peak memory	216752 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1347680976 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_buil d_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random.1347680976
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/36.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_random_large_delays.813155675
Short name	T141
Test name
Test status
Simulation time	46955799296 ps
CPU time	266.24 seconds
Started	Feb 08 09:08:11 AM UTC 25
Finished	Feb 08 09:12:42 AM UTC 25
Peak memory	216880 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=813155675 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/ xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.813155675
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/36.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_random_slow_rsp.2734911956
Short name	T649
Test name
Test status
Simulation time	7196937941 ps
CPU time	49 seconds
Started	Feb 08 09:08:11 AM UTC 25
Finished	Feb 08 09:09:02 AM UTC 25
Peak memory	216880 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2734911956 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xba r_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.2734911956
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/36.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_random_zero_delays.3603867769
Short name	T629
Test name
Test status
Simulation time	166064497 ps
CPU time	6.52 seconds
Started	Feb 08 09:08:11 AM UTC 25
Finished	Feb 08 09:08:19 AM UTC 25
Peak memory	216808 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3603867769 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/cov erage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_delays.3603867769
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/36.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_same_source.4273854074
Short name	T644
Test name
Test status
Simulation time	2367327108 ps
CPU time	34.49 seconds
Started	Feb 08 09:08:17 AM UTC 25
Finished	Feb 08 09:08:54 AM UTC 25
Peak memory	216876 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4273854074 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.4273854074
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/36.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_smoke.4021925714
Short name	T247
Test name
Test status
Simulation time	141438217 ps
CPU time	5.43 seconds
Started	Feb 08 09:08:02 AM UTC 25
Finished	Feb 08 09:08:09 AM UTC 25
Peak memory	216792 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4021925714 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build _mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.4021925714
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/36.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_smoke_large_delays.2544455052
Short name	T648
Test name
Test status
Simulation time	15567711041 ps
CPU time	52.72 seconds
Started	Feb 08 09:08:06 AM UTC 25
Finished	Feb 08 09:09:01 AM UTC 25
Peak memory	216864 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2544455052 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/ xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.2544455052
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/36.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_smoke_slow_rsp.3102894029
Short name	T642
Test name
Test status
Simulation time	4740356444 ps
CPU time	40.13 seconds
Started	Feb 08 09:08:06 AM UTC 25
Finished	Feb 08 09:08:48 AM UTC 25
Peak memory	216988 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3102894029 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.3102894029
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/36.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_smoke_zero_delays.3875744327
Short name	T245
Test name
Test status
Simulation time	27827282 ps
CPU time	3.24 seconds
Started	Feb 08 09:08:04 AM UTC 25
Finished	Feb 08 09:08:08 AM UTC 25
Peak memory	217108 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3875744327 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/cove rage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delays.3875744327
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/36.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all.1901286608
Short name	T692
Test name
Test status
Simulation time	3521463042 ps
CPU time	104.12 seconds
Started	Feb 08 09:08:28 AM UTC 25
Finished	Feb 08 09:10:15 AM UTC 25
Peak memory	219244 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1901286608 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.1901286608
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/36.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all_with_error.3853221768
Short name	T718
Test name
Test status
Simulation time	4303440985 ps
CPU time	149.13 seconds
Started	Feb 08 09:08:31 AM UTC 25
Finished	Feb 08 09:11:03 AM UTC 25
Peak memory	221228 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3853221768 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.3853221768
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/36.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all_with_rand_reset.1513913946
Short name	T820
Test name
Test status
Simulation time	1520991647 ps
CPU time	308.58 seconds
Started	Feb 08 09:08:30 AM UTC 25
Finished	Feb 08 09:13:43 AM UTC 25
Peak memory	222892 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1513913946 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_rand_reset.1513913946
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/36.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all_with_reset_error.3263176056
Short name	T738
Test name
Test status
Simulation time	5403719595 ps
CPU time	180.29 seconds
Started	Feb 08 09:08:32 AM UTC 25
Finished	Feb 08 09:11:36 AM UTC 25
Peak memory	223276 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3263176056 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_reset_error.3263176056
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/36.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_unmapped_addr.3020667581
Short name	T634
Test name
Test status
Simulation time	36210608 ps
CPU time	6.54 seconds
Started	Feb 08 09:08:22 AM UTC 25
Finished	Feb 08 09:08:30 AM UTC 25
Peak memory	216744 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3020667581 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xb ar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.3020667581
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/36.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_access_same_device.1182652435
Short name	T665
Test name
Test status
Simulation time	4064257638 ps
CPU time	33.16 seconds
Started	Feb 08 09:08:55 AM UTC 25
Finished	Feb 08 09:09:31 AM UTC 25
Peak memory	217196 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1182652435 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/covera ge/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device.1182652435
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/37.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_access_same_device_slow_rsp.3651682008
Short name	T893
Test name
Test status
Simulation time	90720894287 ps
CPU time	711.41 seconds
Started	Feb 08 09:08:55 AM UTC 25
Finished	Feb 08 09:20:56 AM UTC 25
Peak memory	220552 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3651682008 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/ coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device_slow_rsp.3651682008
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/37.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_error_and_unmapped_addr.1434718466
Short name	T654
Test name
Test status
Simulation time	89327617 ps
CPU time	3.1 seconds
Started	Feb 08 09:09:03 AM UTC 25
Finished	Feb 08 09:09:08 AM UTC 25
Peak memory	217064 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1434718466 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/x bar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_addr.1434718466
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/37.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_error_random.474697786
Short name	T663
Test name
Test status
Simulation time	800426980 ps
CPU time	26.94 seconds
Started	Feb 08 09:09:00 AM UTC 25
Finished	Feb 08 09:09:29 AM UTC 25
Peak memory	217008 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=474697786 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ= xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_buil d_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.474697786
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/37.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_random.1837705887
Short name	T671
Test name
Test status
Simulation time	6711998982 ps
CPU time	56.66 seconds
Started	Feb 08 09:08:40 AM UTC 25
Finished	Feb 08 09:09:39 AM UTC 25
Peak memory	218420 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1837705887 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_buil d_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random.1837705887
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/37.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_random_large_delays.3517989712
Short name	T813
Test name
Test status
Simulation time	162175843531 ps
CPU time	280.78 seconds
Started	Feb 08 09:08:51 AM UTC 25
Finished	Feb 08 09:13:36 AM UTC 25
Peak memory	217192 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3517989712 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage /xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.3517989712
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/37.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_random_slow_rsp.391205915
Short name	T824
Test name
Test status
Simulation time	71477615387 ps
CPU time	292.65 seconds
Started	Feb 08 09:08:51 AM UTC 25
Finished	Feb 08 09:13:48 AM UTC 25
Peak memory	219184 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=391205915 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST _SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.391205915
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/37.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_random_zero_delays.312974983
Short name	T653
Test name
Test status
Simulation time	394893241 ps
CPU time	22.91 seconds
Started	Feb 08 09:08:42 AM UTC 25
Finished	Feb 08 09:09:07 AM UTC 25
Peak memory	216740 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=312974983 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/cove rage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_delays.312974983
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/37.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_same_source.25027496
Short name	T650
Test name
Test status
Simulation time	228917877 ps
CPU time	4.05 seconds
Started	Feb 08 09:08:56 AM UTC 25
Finished	Feb 08 09:09:03 AM UTC 25
Peak memory	217064 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25027496 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xb ar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_b uild_mode.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.25027496
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/37.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_smoke.156084666
Short name	T639
Test name
Test status
Simulation time	32019643 ps
CPU time	3.61 seconds
Started	Feb 08 09:08:33 AM UTC 25
Finished	Feb 08 09:08:39 AM UTC 25
Peak memory	216788 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=156084666 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_ mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.156084666
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/37.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_smoke_large_delays.3421702489
Short name	T662
Test name
Test status
Simulation time	4765682149 ps
CPU time	51.04 seconds
Started	Feb 08 09:08:35 AM UTC 25
Finished	Feb 08 09:09:28 AM UTC 25
Peak memory	216516 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3421702489 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/ xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.3421702489
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/37.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_smoke_slow_rsp.3309084776
Short name	T658
Test name
Test status
Simulation time	3596131195 ps
CPU time	42.12 seconds
Started	Feb 08 09:08:40 AM UTC 25
Finished	Feb 08 09:09:25 AM UTC 25
Peak memory	216708 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3309084776 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.3309084776
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/37.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_smoke_zero_delays.2102236643
Short name	T640
Test name
Test status
Simulation time	38350142 ps
CPU time	3.24 seconds
Started	Feb 08 09:08:35 AM UTC 25
Finished	Feb 08 09:08:40 AM UTC 25
Peak memory	216552 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2102236643 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/cove rage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delays.2102236643
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/37.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all.2238731699
Short name	T698
Test name
Test status
Simulation time	2382826461 ps
CPU time	81.54 seconds
Started	Feb 08 09:09:03 AM UTC 25
Finished	Feb 08 09:10:27 AM UTC 25
Peak memory	218924 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2238731699 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.2238731699
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/37.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all_with_error.1902327974
Short name	T682
Test name
Test status
Simulation time	1520873982 ps
CPU time	52.17 seconds
Started	Feb 08 09:09:07 AM UTC 25
Finished	Feb 08 09:10:01 AM UTC 25
Peak memory	217064 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1902327974 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.1902327974
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/37.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all_with_rand_reset.414292906
Short name	T785
Test name
Test status
Simulation time	514631046 ps
CPU time	208.79 seconds
Started	Feb 08 09:09:06 AM UTC 25
Finished	Feb 08 09:12:38 AM UTC 25
Peak memory	220840 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=414292906 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs /coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_rand_reset.414292906
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/37.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all_with_reset_error.157951832
Short name	T685
Test name
Test status
Simulation time	227421470 ps
CPU time	55.86 seconds
Started	Feb 08 09:09:08 AM UTC 25
Finished	Feb 08 09:10:06 AM UTC 25
Peak memory	220904 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=157951832 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ= xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_reset_error.157951832
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/37.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_unmapped_addr.1690590410
Short name	T664
Test name
Test status
Simulation time	872259768 ps
CPU time	26.29 seconds
Started	Feb 08 09:09:02 AM UTC 25
Finished	Feb 08 09:09:30 AM UTC 25
Peak memory	219116 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1690590410 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xb ar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.1690590410
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/37.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_access_same_device.2294627393
Short name	T163
Test name
Test status
Simulation time	4515134417 ps
CPU time	76.78 seconds
Started	Feb 08 09:09:26 AM UTC 25
Finished	Feb 08 09:10:45 AM UTC 25
Peak memory	218920 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2294627393 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/covera ge/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device.2294627393
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/38.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.3257334621
Short name	T900
Test name
Test status
Simulation time	74020600687 ps
CPU time	936.8 seconds
Started	Feb 08 09:09:28 AM UTC 25
Finished	Feb 08 09:25:16 AM UTC 25
Peak memory	222856 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3257334621 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/ coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device_slow_rsp.3257334621
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/38.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_error_and_unmapped_addr.2762278539
Short name	T681
Test name
Test status
Simulation time	1132209665 ps
CPU time	26.89 seconds
Started	Feb 08 09:09:32 AM UTC 25
Finished	Feb 08 09:10:01 AM UTC 25
Peak memory	216812 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2762278539 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/x bar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_addr.2762278539
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/38.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_error_random.3811984532
Short name	T670
Test name
Test status
Simulation time	216153854 ps
CPU time	6.92 seconds
Started	Feb 08 09:09:31 AM UTC 25
Finished	Feb 08 09:09:39 AM UTC 25
Peak memory	216612 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3811984532 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_bui ld_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.3811984532
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/38.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_random.2852515827
Short name	T680
Test name
Test status
Simulation time	1012622459 ps
CPU time	37.22 seconds
Started	Feb 08 09:09:18 AM UTC 25
Finished	Feb 08 09:09:57 AM UTC 25
Peak memory	216820 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2852515827 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_buil d_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random.2852515827
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/38.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_random_large_delays.829063006
Short name	T703
Test name
Test status
Simulation time	10546695221 ps
CPU time	64.9 seconds
Started	Feb 08 09:09:26 AM UTC 25
Finished	Feb 08 09:10:33 AM UTC 25
Peak memory	216560 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=829063006 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/ xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.829063006
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/38.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_random_slow_rsp.3924922437
Short name	T714
Test name
Test status
Simulation time	13421819424 ps
CPU time	88.61 seconds
Started	Feb 08 09:09:26 AM UTC 25
Finished	Feb 08 09:10:57 AM UTC 25
Peak memory	216876 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3924922437 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xba r_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.3924922437
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/38.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_random_zero_delays.1180541219
Short name	T669
Test name
Test status
Simulation time	126111861 ps
CPU time	12.82 seconds
Started	Feb 08 09:09:23 AM UTC 25
Finished	Feb 08 09:09:38 AM UTC 25
Peak memory	216744 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1180541219 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/cov erage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_delays.1180541219
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/38.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_same_source.3840372791
Short name	T678
Test name
Test status
Simulation time	152775068 ps
CPU time	17.49 seconds
Started	Feb 08 09:09:29 AM UTC 25
Finished	Feb 08 09:09:48 AM UTC 25
Peak memory	217068 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3840372791 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.3840372791
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/38.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_smoke.1461534227
Short name	T656
Test name
Test status
Simulation time	153758878 ps
CPU time	4.69 seconds
Started	Feb 08 09:09:10 AM UTC 25
Finished	Feb 08 09:09:16 AM UTC 25
Peak memory	216792 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1461534227 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build _mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.1461534227
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/38.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_smoke_large_delays.4187002376
Short name	T677
Test name
Test status
Simulation time	4718195989 ps
CPU time	30.3 seconds
Started	Feb 08 09:09:15 AM UTC 25
Finished	Feb 08 09:09:47 AM UTC 25
Peak memory	216860 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4187002376 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/ xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.4187002376
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/38.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_smoke_slow_rsp.1965656827
Short name	T679
Test name
Test status
Simulation time	2587384092 ps
CPU time	33.06 seconds
Started	Feb 08 09:09:18 AM UTC 25
Finished	Feb 08 09:09:53 AM UTC 25
Peak memory	216856 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1965656827 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.1965656827
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/38.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_smoke_zero_delays.1200343297
Short name	T655
Test name
Test status
Simulation time	42266104 ps
CPU time	2.89 seconds
Started	Feb 08 09:09:10 AM UTC 25
Finished	Feb 08 09:09:14 AM UTC 25
Peak memory	216720 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1200343297 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/cove rage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delays.1200343297
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/38.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all.1924100496
Short name	T725
Test name
Test status
Simulation time	1112239789 ps
CPU time	100.61 seconds
Started	Feb 08 09:09:34 AM UTC 25
Finished	Feb 08 09:11:17 AM UTC 25
Peak memory	218860 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1924100496 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.1924100496
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/38.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all_with_error.3172879284
Short name	T744
Test name
Test status
Simulation time	21178264519 ps
CPU time	125.14 seconds
Started	Feb 08 09:09:38 AM UTC 25
Finished	Feb 08 09:11:46 AM UTC 25
Peak memory	218920 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3172879284 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.3172879284
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/38.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all_with_rand_reset.2069670330
Short name	T783
Test name
Test status
Simulation time	453961228 ps
CPU time	174.99 seconds
Started	Feb 08 09:09:36 AM UTC 25
Finished	Feb 08 09:12:34 AM UTC 25
Peak memory	220908 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2069670330 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_rand_reset.2069670330
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/38.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all_with_reset_error.2440078164
Short name	T736
Test name
Test status
Simulation time	356821241 ps
CPU time	114.17 seconds
Started	Feb 08 09:09:39 AM UTC 25
Finished	Feb 08 09:11:36 AM UTC 25
Peak memory	223208 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2440078164 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_reset_error.2440078164
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/38.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_unmapped_addr.3737616018
Short name	T672
Test name
Test status
Simulation time	108150832 ps
CPU time	7.58 seconds
Started	Feb 08 09:09:31 AM UTC 25
Finished	Feb 08 09:09:40 AM UTC 25
Peak memory	216596 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3737616018 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xb ar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.3737616018
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/38.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_access_same_device.2828325255
Short name	T688
Test name
Test status
Simulation time	106807157 ps
CPU time	20.81 seconds
Started	Feb 08 09:09:47 AM UTC 25
Finished	Feb 08 09:10:10 AM UTC 25
Peak memory	218844 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2828325255 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/covera ge/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device.2828325255
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/39.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_access_same_device_slow_rsp.705259185
Short name	T795
Test name
Test status
Simulation time	40970542339 ps
CPU time	179.6 seconds
Started	Feb 08 09:09:49 AM UTC 25
Finished	Feb 08 09:12:52 AM UTC 25
Peak memory	219248 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=705259185 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST _SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/c overage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device_slow_rsp.705259185
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/39.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_error_and_unmapped_addr.984577421
Short name	T697
Test name
Test status
Simulation time	1407181349 ps
CPU time	23.24 seconds
Started	Feb 08 09:09:58 AM UTC 25
Finished	Feb 08 09:10:23 AM UTC 25
Peak memory	217056 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=984577421 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ= xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xb ar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_addr.984577421
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/39.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_error_random.402171944
Short name	T699
Test name
Test status
Simulation time	1048475899 ps
CPU time	36.16 seconds
Started	Feb 08 09:09:49 AM UTC 25
Finished	Feb 08 09:10:27 AM UTC 25
Peak memory	217072 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=402171944 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ= xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_buil d_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.402171944
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/39.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_random.2821456634
Short name	T700
Test name
Test status
Simulation time	2228836651 ps
CPU time	41.51 seconds
Started	Feb 08 09:09:45 AM UTC 25
Finished	Feb 08 09:10:28 AM UTC 25
Peak memory	216816 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2821456634 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_buil d_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random.2821456634
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/39.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_random_large_delays.1724560001
Short name	T856
Test name
Test status
Simulation time	43533523989 ps
CPU time	296.39 seconds
Started	Feb 08 09:09:46 AM UTC 25
Finished	Feb 08 09:14:47 AM UTC 25
Peak memory	218916 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1724560001 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage /xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.1724560001
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/39.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_random_slow_rsp.4089192992
Short name	T750
Test name
Test status
Simulation time	8899966738 ps
CPU time	123.3 seconds
Started	Feb 08 09:09:47 AM UTC 25
Finished	Feb 08 09:11:54 AM UTC 25
Peak memory	218924 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4089192992 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xba r_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.4089192992
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/39.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_random_zero_delays.632740318
Short name	T687
Test name
Test status
Simulation time	142513221 ps
CPU time	22.28 seconds
Started	Feb 08 09:09:45 AM UTC 25
Finished	Feb 08 09:10:09 AM UTC 25
Peak memory	216804 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=632740318 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/cove rage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_delays.632740318
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/39.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_same_source.216198009
Short name	T690
Test name
Test status
Simulation time	790739152 ps
CPU time	21.72 seconds
Started	Feb 08 09:09:49 AM UTC 25
Finished	Feb 08 09:10:13 AM UTC 25
Peak memory	216812 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=216198009 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.216198009
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/39.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_smoke.2819085754
Short name	T675
Test name
Test status
Simulation time	118553462 ps
CPU time	3.75 seconds
Started	Feb 08 09:09:41 AM UTC 25
Finished	Feb 08 09:09:46 AM UTC 25
Peak memory	216760 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2819085754 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build _mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.2819085754
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/39.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_smoke_large_delays.221784803
Short name	T694
Test name
Test status
Simulation time	14543513812 ps
CPU time	35.77 seconds
Started	Feb 08 09:09:41 AM UTC 25
Finished	Feb 08 09:10:18 AM UTC 25
Peak memory	216860 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=221784803 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/x bar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.221784803
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/39.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_smoke_slow_rsp.2388337326
Short name	T686
Test name
Test status
Simulation time	2820288423 ps
CPU time	23.1 seconds
Started	Feb 08 09:09:42 AM UTC 25
Finished	Feb 08 09:10:07 AM UTC 25
Peak memory	216856 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2388337326 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.2388337326
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/39.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_smoke_zero_delays.3250904011
Short name	T674
Test name
Test status
Simulation time	94375550 ps
CPU time	2.51 seconds
Started	Feb 08 09:09:41 AM UTC 25
Finished	Feb 08 09:09:45 AM UTC 25
Peak memory	216704 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3250904011 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/cove rage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delays.3250904011
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/39.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all.772377276
Short name	T754
Test name
Test status
Simulation time	1022500581 ps
CPU time	112.37 seconds
Started	Feb 08 09:10:02 AM UTC 25
Finished	Feb 08 09:11:57 AM UTC 25
Peak memory	221168 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=772377276 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_b uild_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.772377276
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/39.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all_with_error.416939238
Short name	T720
Test name
Test status
Simulation time	735360866 ps
CPU time	62.57 seconds
Started	Feb 08 09:10:02 AM UTC 25
Finished	Feb 08 09:11:07 AM UTC 25
Peak memory	216812 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=416939238 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ= xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.416939238
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/39.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all_with_rand_reset.1708971348
Short name	T155
Test name
Test status
Simulation time	3552423651 ps
CPU time	254.35 seconds
Started	Feb 08 09:10:02 AM UTC 25
Finished	Feb 08 09:14:21 AM UTC 25
Peak memory	223024 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1708971348 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_rand_reset.1708971348
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/39.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all_with_reset_error.3515646833
Short name	T867
Test name
Test status
Simulation time	3335511192 ps
CPU time	299.01 seconds
Started	Feb 08 09:10:04 AM UTC 25
Finished	Feb 08 09:15:08 AM UTC 25
Peak memory	233564 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3515646833 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_reset_error.3515646833
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/39.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_unmapped_addr.3062473039
Short name	T693
Test name
Test status
Simulation time	652069597 ps
CPU time	21.42 seconds
Started	Feb 08 09:09:53 AM UTC 25
Finished	Feb 08 09:10:16 AM UTC 25
Peak memory	216808 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3062473039 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xb ar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.3062473039
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/39.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_access_same_device.1208234152
Short name	T77
Test name
Test status
Simulation time	1556245535 ps
CPU time	30.06 seconds
Started	Feb 08 08:53:45 AM UTC 25
Finished	Feb 08 08:54:17 AM UTC 25
Peak memory	216808 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1208234152 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/covera ge/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device.1208234152
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/4.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_error_and_unmapped_addr.588784607
Short name	T201
Test name
Test status
Simulation time	162119838 ps
CPU time	18.36 seconds
Started	Feb 08 08:53:49 AM UTC 25
Finished	Feb 08 08:54:09 AM UTC 25
Peak memory	216804 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=588784607 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ= xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xb ar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr.588784607
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/4.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_error_random.2851863756
Short name	T202
Test name
Test status
Simulation time	254719502 ps
CPU time	19.47 seconds
Started	Feb 08 08:53:48 AM UTC 25
Finished	Feb 08 08:54:09 AM UTC 25
Peak memory	216744 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2851863756 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_bui ld_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.2851863756
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/4.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_random.880178581
Short name	T175
Test name
Test status
Simulation time	194442497 ps
CPU time	8.12 seconds
Started	Feb 08 08:53:41 AM UTC 25
Finished	Feb 08 08:53:50 AM UTC 25
Peak memory	216432 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=880178581 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build _mode.vdb -cm_log /dev/null -cm_name 4.xbar_random.880178581
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/4.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_random_large_delays.3986217180
Short name	T291
Test name
Test status
Simulation time	36295379099 ps
CPU time	183.5 seconds
Started	Feb 08 08:53:43 AM UTC 25
Finished	Feb 08 08:56:49 AM UTC 25
Peak memory	217140 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3986217180 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage /xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.3986217180
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/4.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_random_slow_rsp.938764131
Short name	T290
Test name
Test status
Simulation time	77123558075 ps
CPU time	179.05 seconds
Started	Feb 08 08:53:43 AM UTC 25
Finished	Feb 08 08:56:45 AM UTC 25
Peak memory	216812 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=938764131 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST _SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.938764131
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/4.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_random_zero_delays.2620254469
Short name	T91
Test name
Test status
Simulation time	176036447 ps
CPU time	28.86 seconds
Started	Feb 08 08:53:43 AM UTC 25
Finished	Feb 08 08:54:13 AM UTC 25
Peak memory	216744 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2620254469 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/cov erage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_delays.2620254469
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/4.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_same_source.4201613457
Short name	T44
Test name
Test status
Simulation time	1361031829 ps
CPU time	14.24 seconds
Started	Feb 08 08:53:46 AM UTC 25
Finished	Feb 08 08:54:01 AM UTC 25
Peak memory	216732 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4201613457 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.4201613457
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/4.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_smoke.3853290872
Short name	T110
Test name
Test status
Simulation time	137781060 ps
CPU time	4.3 seconds
Started	Feb 08 08:53:39 AM UTC 25
Finished	Feb 08 08:53:44 AM UTC 25
Peak memory	216792 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3853290872 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build _mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.3853290872
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/4.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_smoke_large_delays.1300280916
Short name	T173
Test name
Test status
Simulation time	7716624331 ps
CPU time	62.92 seconds
Started	Feb 08 08:53:41 AM UTC 25
Finished	Feb 08 08:54:46 AM UTC 25
Peak memory	216860 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1300280916 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/ xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.1300280916
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/4.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_smoke_slow_rsp.79089766
Short name	T200
Test name
Test status
Simulation time	5080449618 ps
CPU time	25.59 seconds
Started	Feb 08 08:53:41 AM UTC 25
Finished	Feb 08 08:54:08 AM UTC 25
Peak memory	216568 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=79089766 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_ SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_b uild_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.79089766
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/4.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_smoke_zero_delays.3220972808
Short name	T109
Test name
Test status
Simulation time	149859105 ps
CPU time	3.81 seconds
Started	Feb 08 08:53:39 AM UTC 25
Finished	Feb 08 08:53:44 AM UTC 25
Peak memory	217048 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3220972808 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/cove rage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays.3220972808
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/4.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_stress_all.1743483226
Short name	T324
Test name
Test status
Simulation time	1919818545 ps
CPU time	93.71 seconds
Started	Feb 08 08:53:50 AM UTC 25
Finished	Feb 08 08:55:26 AM UTC 25
Peak memory	220844 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1743483226 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.1743483226
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/4.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_stress_all_with_error.4110423417
Short name	T180
Test name
Test status
Simulation time	5485678540 ps
CPU time	136.73 seconds
Started	Feb 08 08:53:53 AM UTC 25
Finished	Feb 08 08:56:13 AM UTC 25
Peak memory	219188 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4110423417 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.4110423417
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/4.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_stress_all_with_rand_reset.3801302448
Short name	T205
Test name
Test status
Simulation time	3141413245 ps
CPU time	474.87 seconds
Started	Feb 08 08:53:51 AM UTC 25
Finished	Feb 08 09:01:52 AM UTC 25
Peak memory	237556 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3801302448 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_rand_reset.3801302448
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/4.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_stress_all_with_reset_error.900762301
Short name	T90
Test name
Test status
Simulation time	87725331 ps
CPU time	15.83 seconds
Started	Feb 08 08:53:55 AM UTC 25
Finished	Feb 08 08:54:12 AM UTC 25
Peak memory	216792 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=900762301 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ= xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_reset_error.900762301
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/4.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_unmapped_addr.1140154110
Short name	T199
Test name
Test status
Simulation time	143260688 ps
CPU time	17.13 seconds
Started	Feb 08 08:53:48 AM UTC 25
Finished	Feb 08 08:54:07 AM UTC 25
Peak memory	216816 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1140154110 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xb ar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.1140154110
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/4.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_access_same_device.1310903535
Short name	T706
Test name
Test status
Simulation time	574431360 ps
CPU time	18.42 seconds
Started	Feb 08 09:10:17 AM UTC 25
Finished	Feb 08 09:10:37 AM UTC 25
Peak memory	219116 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1310903535 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/covera ge/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device.1310903535
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/40.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_access_same_device_slow_rsp.797872557
Short name	T899
Test name
Test status
Simulation time	88890423890 ps
CPU time	771.73 seconds
Started	Feb 08 09:10:17 AM UTC 25
Finished	Feb 08 09:23:18 AM UTC 25
Peak memory	222920 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=797872557 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST _SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/c overage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device_slow_rsp.797872557
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/40.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_error_and_unmapped_addr.773708303
Short name	T701
Test name
Test status
Simulation time	56906481 ps
CPU time	5.58 seconds
Started	Feb 08 09:10:24 AM UTC 25
Finished	Feb 08 09:10:32 AM UTC 25
Peak memory	216728 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=773708303 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ= xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xb ar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_addr.773708303
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/40.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_error_random.1610837486
Short name	T712
Test name
Test status
Simulation time	1058702073 ps
CPU time	30.46 seconds
Started	Feb 08 09:10:21 AM UTC 25
Finished	Feb 08 09:10:53 AM UTC 25
Peak memory	216864 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1610837486 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_bui ld_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.1610837486
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/40.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_random.3322042239
Short name	T702
Test name
Test status
Simulation time	170028208 ps
CPU time	19.01 seconds
Started	Feb 08 09:10:12 AM UTC 25
Finished	Feb 08 09:10:33 AM UTC 25
Peak memory	216816 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3322042239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_buil d_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random.3322042239
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/40.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_random_large_delays.4210773314
Short name	T870
Test name
Test status
Simulation time	91821691230 ps
CPU time	315.24 seconds
Started	Feb 08 09:10:14 AM UTC 25
Finished	Feb 08 09:15:34 AM UTC 25
Peak memory	216872 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4210773314 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage /xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.4210773314
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/40.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_random_slow_rsp.109615673
Short name	T766
Test name
Test status
Simulation time	19165414179 ps
CPU time	113.26 seconds
Started	Feb 08 09:10:15 AM UTC 25
Finished	Feb 08 09:12:10 AM UTC 25
Peak memory	216872 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=109615673 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST _SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.109615673
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/40.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_random_zero_delays.330370636
Short name	T695
Test name
Test status
Simulation time	36458917 ps
CPU time	6.18 seconds
Started	Feb 08 09:10:12 AM UTC 25
Finished	Feb 08 09:10:20 AM UTC 25
Peak memory	216804 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=330370636 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/cove rage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_delays.330370636
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/40.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_same_source.2396981707
Short name	T705
Test name
Test status
Simulation time	1462440003 ps
CPU time	16.27 seconds
Started	Feb 08 09:10:19 AM UTC 25
Finished	Feb 08 09:10:37 AM UTC 25
Peak memory	216812 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2396981707 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.2396981707
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/40.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_smoke.1466400609
Short name	T689
Test name
Test status
Simulation time	58257227 ps
CPU time	3.6 seconds
Started	Feb 08 09:10:05 AM UTC 25
Finished	Feb 08 09:10:10 AM UTC 25
Peak memory	217048 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1466400609 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build _mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.1466400609
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/40.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_smoke_large_delays.1004385827
Short name	T715
Test name
Test status
Simulation time	12482608142 ps
CPU time	48.16 seconds
Started	Feb 08 09:10:08 AM UTC 25
Finished	Feb 08 09:10:58 AM UTC 25
Peak memory	216860 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1004385827 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/ xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.1004385827
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/40.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_smoke_slow_rsp.2840752400
Short name	T710
Test name
Test status
Simulation time	4343955374 ps
CPU time	36.53 seconds
Started	Feb 08 09:10:09 AM UTC 25
Finished	Feb 08 09:10:48 AM UTC 25
Peak memory	217116 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2840752400 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.2840752400
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/40.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_smoke_zero_delays.2862487038
Short name	T691
Test name
Test status
Simulation time	36540153 ps
CPU time	3.25 seconds
Started	Feb 08 09:10:08 AM UTC 25
Finished	Feb 08 09:10:13 AM UTC 25
Peak memory	217044 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2862487038 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/cove rage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delays.2862487038
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/40.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all.37786351
Short name	T793
Test name
Test status
Simulation time	2038453613 ps
CPU time	138.58 seconds
Started	Feb 08 09:10:29 AM UTC 25
Finished	Feb 08 09:12:51 AM UTC 25
Peak memory	222956 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37786351 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xb ar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_bu ild_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.37786351
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/40.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_error.2213988871
Short name	T734
Test name
Test status
Simulation time	2483304038 ps
CPU time	62.39 seconds
Started	Feb 08 09:10:29 AM UTC 25
Finished	Feb 08 09:11:34 AM UTC 25
Peak memory	218852 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2213988871 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.2213988871
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/40.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_rand_reset.80967268
Short name	T735
Test name
Test status
Simulation time	1000193838 ps
CPU time	62.43 seconds
Started	Feb 08 09:10:29 AM UTC 25
Finished	Feb 08 09:11:34 AM UTC 25
Peak memory	218856 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=80967268 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xb ar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/ coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_rand_reset.80967268
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/40.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_reset_error.3852063424
Short name	T797
Test name
Test status
Simulation time	565887470 ps
CPU time	141.82 seconds
Started	Feb 08 09:10:32 AM UTC 25
Finished	Feb 08 09:12:58 AM UTC 25
Peak memory	222952 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3852063424 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_reset_error.3852063424
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/40.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_unmapped_addr.3605527145
Short name	T709
Test name
Test status
Simulation time	137724706 ps
CPU time	17.15 seconds
Started	Feb 08 09:10:24 AM UTC 25
Finished	Feb 08 09:10:43 AM UTC 25
Peak memory	216820 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3605527145 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xb ar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.3605527145
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/40.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_access_same_device.2332556958
Short name	T772
Test name
Test status
Simulation time	2138060570 ps
CPU time	90.31 seconds
Started	Feb 08 09:10:47 AM UTC 25
Finished	Feb 08 09:12:19 AM UTC 25
Peak memory	218856 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2332556958 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/covera ge/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device.2332556958
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/41.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_access_same_device_slow_rsp.4084691054
Short name	T878
Test name
Test status
Simulation time	30870865892 ps
CPU time	318.03 seconds
Started	Feb 08 09:10:49 AM UTC 25
Finished	Feb 08 09:16:12 AM UTC 25
Peak memory	218928 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4084691054 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/ coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device_slow_rsp.4084691054
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/41.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_error_and_unmapped_addr.4152336906
Short name	T717
Test name
Test status
Simulation time	32785823 ps
CPU time	3.29 seconds
Started	Feb 08 09:10:56 AM UTC 25
Finished	Feb 08 09:11:01 AM UTC 25
Peak memory	216740 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4152336906 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/x bar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_addr.4152336906
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/41.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_error_random.3902411853
Short name	T748
Test name
Test status
Simulation time	5887614068 ps
CPU time	54.34 seconds
Started	Feb 08 09:10:54 AM UTC 25
Finished	Feb 08 09:11:50 AM UTC 25
Peak memory	217120 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3902411853 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_bui ld_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.3902411853
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/41.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_random.452857112
Short name	T721
Test name
Test status
Simulation time	720402991 ps
CPU time	26.9 seconds
Started	Feb 08 09:10:39 AM UTC 25
Finished	Feb 08 09:11:07 AM UTC 25
Peak memory	216808 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=452857112 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build _mode.vdb -cm_log /dev/null -cm_name 41.xbar_random.452857112
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/41.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_random_large_delays.585780063
Short name	T841
Test name
Test status
Simulation time	26701627082 ps
CPU time	213.36 seconds
Started	Feb 08 09:10:41 AM UTC 25
Finished	Feb 08 09:14:18 AM UTC 25
Peak memory	216880 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=585780063 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/ xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.585780063
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/41.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_random_slow_rsp.54288969
Short name	T821
Test name
Test status
Simulation time	27622613643 ps
CPU time	177.67 seconds
Started	Feb 08 09:10:44 AM UTC 25
Finished	Feb 08 09:13:45 AM UTC 25
Peak memory	216816 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=54288969 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_ SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.54288969
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/41.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_random_zero_delays.1876100309
Short name	T716
Test name
Test status
Simulation time	113823498 ps
CPU time	15.63 seconds
Started	Feb 08 09:10:41 AM UTC 25
Finished	Feb 08 09:10:59 AM UTC 25
Peak memory	217064 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1876100309 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/cov erage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_delays.1876100309
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/41.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_same_source.115770243
Short name	T719
Test name
Test status
Simulation time	156099386 ps
CPU time	9.08 seconds
Started	Feb 08 09:10:52 AM UTC 25
Finished	Feb 08 09:11:03 AM UTC 25
Peak memory	216876 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=115770243 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.115770243
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/41.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_smoke.2033684134
Short name	T707
Test name
Test status
Simulation time	298370365 ps
CPU time	4.5 seconds
Started	Feb 08 09:10:34 AM UTC 25
Finished	Feb 08 09:10:40 AM UTC 25
Peak memory	216792 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2033684134 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build _mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.2033684134
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/41.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_smoke_large_delays.3050745098
Short name	T747
Test name
Test status
Simulation time	20233786907 ps
CPU time	67.39 seconds
Started	Feb 08 09:10:39 AM UTC 25
Finished	Feb 08 09:11:48 AM UTC 25
Peak memory	217120 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3050745098 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/ xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.3050745098
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/41.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_smoke_slow_rsp.1742070640
Short name	T728
Test name
Test status
Simulation time	2710223939 ps
CPU time	41.63 seconds
Started	Feb 08 09:10:39 AM UTC 25
Finished	Feb 08 09:11:22 AM UTC 25
Peak memory	217052 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1742070640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.1742070640
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/41.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_smoke_zero_delays.2030373195
Short name	T708
Test name
Test status
Simulation time	54726575 ps
CPU time	3.58 seconds
Started	Feb 08 09:10:35 AM UTC 25
Finished	Feb 08 09:10:40 AM UTC 25
Peak memory	216784 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2030373195 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/cove rage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delays.2030373195
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/41.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all.3514450736
Short name	T863
Test name
Test status
Simulation time	9873535404 ps
CPU time	236.69 seconds
Started	Feb 08 09:10:58 AM UTC 25
Finished	Feb 08 09:14:59 AM UTC 25
Peak memory	223020 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3514450736 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.3514450736
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/41.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_error.2793572113
Short name	T767
Test name
Test status
Simulation time	6704538578 ps
CPU time	70.79 seconds
Started	Feb 08 09:11:00 AM UTC 25
Finished	Feb 08 09:12:13 AM UTC 25
Peak memory	216872 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2793572113 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.2793572113
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/41.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_rand_reset.3214225715
Short name	T853
Test name
Test status
Simulation time	573796696 ps
CPU time	215.69 seconds
Started	Feb 08 09:11:00 AM UTC 25
Finished	Feb 08 09:14:39 AM UTC 25
Peak memory	220912 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3214225715 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_rand_reset.3214225715
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/41.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_reset_error.2569421123
Short name	T887
Test name
Test status
Simulation time	9926707105 ps
CPU time	393.88 seconds
Started	Feb 08 09:11:02 AM UTC 25
Finished	Feb 08 09:17:42 AM UTC 25
Peak memory	233884 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2569421123 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_reset_error.2569421123
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/41.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_unmapped_addr.1522307382
Short name	T724
Test name
Test status
Simulation time	100449063 ps
CPU time	16.34 seconds
Started	Feb 08 09:10:55 AM UTC 25
Finished	Feb 08 09:11:13 AM UTC 25
Peak memory	216808 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1522307382 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xb ar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.1522307382
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/41.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_access_same_device.3723831908
Short name	T727
Test name
Test status
Simulation time	38529778 ps
CPU time	3.58 seconds
Started	Feb 08 09:11:14 AM UTC 25
Finished	Feb 08 09:11:19 AM UTC 25
Peak memory	216812 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3723831908 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/covera ge/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device.3723831908
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/42.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.2750573517
Short name	T292
Test name
Test status
Simulation time	70553471411 ps
CPU time	507.34 seconds
Started	Feb 08 09:11:19 AM UTC 25
Finished	Feb 08 09:19:53 AM UTC 25
Peak memory	219244 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2750573517 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/ coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device_slow_rsp.2750573517
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/42.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_error_and_unmapped_addr.2523289985
Short name	T745
Test name
Test status
Simulation time	181081843 ps
CPU time	20.17 seconds
Started	Feb 08 09:11:24 AM UTC 25
Finished	Feb 08 09:11:46 AM UTC 25
Peak memory	216812 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2523289985 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/x bar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_addr.2523289985
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/42.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_error_random.4156413383
Short name	T729
Test name
Test status
Simulation time	86753565 ps
CPU time	3.65 seconds
Started	Feb 08 09:11:20 AM UTC 25
Finished	Feb 08 09:11:25 AM UTC 25
Peak memory	217056 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4156413383 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_bui ld_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.4156413383
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/42.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_random.2097348044
Short name	T746
Test name
Test status
Simulation time	239567094 ps
CPU time	35.6 seconds
Started	Feb 08 09:11:11 AM UTC 25
Finished	Feb 08 09:11:48 AM UTC 25
Peak memory	218864 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2097348044 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_buil d_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random.2097348044
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/42.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_random_large_delays.3350197067
Short name	T877
Test name
Test status
Simulation time	153365573559 ps
CPU time	294.27 seconds
Started	Feb 08 09:11:12 AM UTC 25
Finished	Feb 08 09:16:10 AM UTC 25
Peak memory	217136 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3350197067 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage /xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.3350197067
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/42.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_random_slow_rsp.2359381068
Short name	T807
Test name
Test status
Simulation time	22780910269 ps
CPU time	122.96 seconds
Started	Feb 08 09:11:13 AM UTC 25
Finished	Feb 08 09:13:19 AM UTC 25
Peak memory	216816 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2359381068 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xba r_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.2359381068
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/42.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_random_zero_delays.3176065933
Short name	T726
Test name
Test status
Simulation time	37058102 ps
CPU time	5.75 seconds
Started	Feb 08 09:11:11 AM UTC 25
Finished	Feb 08 09:11:18 AM UTC 25
Peak memory	216808 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3176065933 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/cov erage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_delays.3176065933
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/42.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_same_source.3375465874
Short name	T730
Test name
Test status
Simulation time	201666531 ps
CPU time	7.61 seconds
Started	Feb 08 09:11:19 AM UTC 25
Finished	Feb 08 09:11:28 AM UTC 25
Peak memory	216812 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3375465874 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.3375465874
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/42.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_smoke.3595568521
Short name	T723
Test name
Test status
Simulation time	160614572 ps
CPU time	5.12 seconds
Started	Feb 08 09:11:05 AM UTC 25
Finished	Feb 08 09:11:11 AM UTC 25
Peak memory	216712 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3595568521 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build _mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.3595568521
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/42.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_smoke_large_delays.2840303223
Short name	T749
Test name
Test status
Simulation time	6571552205 ps
CPU time	40.38 seconds
Started	Feb 08 09:11:08 AM UTC 25
Finished	Feb 08 09:11:51 AM UTC 25
Peak memory	217120 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2840303223 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/ xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.2840303223
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/42.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_smoke_slow_rsp.146125003
Short name	T743
Test name
Test status
Simulation time	3336346238 ps
CPU time	34.81 seconds
Started	Feb 08 09:11:08 AM UTC 25
Finished	Feb 08 09:11:45 AM UTC 25
Peak memory	216796 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=146125003 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST _SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.146125003
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/42.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_smoke_zero_delays.3973695681
Short name	T722
Test name
Test status
Simulation time	28618177 ps
CPU time	3.26 seconds
Started	Feb 08 09:11:05 AM UTC 25
Finished	Feb 08 09:11:09 AM UTC 25
Peak memory	216696 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3973695681 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/cove rage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delays.3973695681
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/42.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all.536886553
Short name	T872
Test name
Test status
Simulation time	13401100355 ps
CPU time	255.16 seconds
Started	Feb 08 09:11:26 AM UTC 25
Finished	Feb 08 09:15:46 AM UTC 25
Peak memory	223280 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=536886553 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_b uild_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.536886553
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/42.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_error.916120669
Short name	T860
Test name
Test status
Simulation time	7980519493 ps
CPU time	198.21 seconds
Started	Feb 08 09:11:31 AM UTC 25
Finished	Feb 08 09:14:53 AM UTC 25
Peak memory	222956 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=916120669 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ= xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.916120669
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/42.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.455004581
Short name	T752
Test name
Test status
Simulation time	107822583 ps
CPU time	23.9 seconds
Started	Feb 08 09:11:30 AM UTC 25
Finished	Feb 08 09:11:55 AM UTC 25
Peak memory	218792 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=455004581 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs /coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_rand_reset.455004581
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/42.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_reset_error.1388184185
Short name	T897
Test name
Test status
Simulation time	13473430617 ps
CPU time	638.08 seconds
Started	Feb 08 09:11:33 AM UTC 25
Finished	Feb 08 09:22:19 AM UTC 25
Peak memory	235252 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1388184185 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_reset_error.1388184185
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/42.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_unmapped_addr.3769466359
Short name	T753
Test name
Test status
Simulation time	768457171 ps
CPU time	30.32 seconds
Started	Feb 08 09:11:24 AM UTC 25
Finished	Feb 08 09:11:56 AM UTC 25
Peak memory	216808 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3769466359 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xb ar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.3769466359
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/42.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_access_same_device.1262780741
Short name	T765
Test name
Test status
Simulation time	217344678 ps
CPU time	22.27 seconds
Started	Feb 08 09:11:46 AM UTC 25
Finished	Feb 08 09:12:10 AM UTC 25
Peak memory	216808 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1262780741 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/covera ge/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device.1262780741
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/43.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.946234669
Short name	T164
Test name
Test status
Simulation time	22737633303 ps
CPU time	246.63 seconds
Started	Feb 08 09:11:46 AM UTC 25
Finished	Feb 08 09:15:57 AM UTC 25
Peak memory	218928 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=946234669 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST _SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/c overage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device_slow_rsp.946234669
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/43.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_error_and_unmapped_addr.769309314
Short name	T768
Test name
Test status
Simulation time	155223646 ps
CPU time	22.08 seconds
Started	Feb 08 09:11:49 AM UTC 25
Finished	Feb 08 09:12:13 AM UTC 25
Peak memory	215640 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=769309314 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ= xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xb ar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_addr.769309314
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/43.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_error_random.31104993
Short name	T755
Test name
Test status
Simulation time	89346100 ps
CPU time	7.84 seconds
Started	Feb 08 09:11:48 AM UTC 25
Finished	Feb 08 09:11:57 AM UTC 25
Peak memory	216956 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31104993 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=x bar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build _mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.31104993
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/43.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_random.3307360333
Short name	T741
Test name
Test status
Simulation time	407534211 ps
CPU time	4.32 seconds
Started	Feb 08 09:11:37 AM UTC 25
Finished	Feb 08 09:11:43 AM UTC 25
Peak memory	216816 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3307360333 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_buil d_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random.3307360333
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/43.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_random_large_delays.3152585051
Short name	T842
Test name
Test status
Simulation time	38098645625 ps
CPU time	154.8 seconds
Started	Feb 08 09:11:41 AM UTC 25
Finished	Feb 08 09:14:18 AM UTC 25
Peak memory	216876 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3152585051 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage /xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.3152585051
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/43.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_random_slow_rsp.207394518
Short name	T802
Test name
Test status
Simulation time	20081060302 ps
CPU time	80.19 seconds
Started	Feb 08 09:11:44 AM UTC 25
Finished	Feb 08 09:13:06 AM UTC 25
Peak memory	216880 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=207394518 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST _SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.207394518
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/43.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_random_zero_delays.1302527683
Short name	T758
Test name
Test status
Simulation time	426822620 ps
CPU time	21.87 seconds
Started	Feb 08 09:11:39 AM UTC 25
Finished	Feb 08 09:12:03 AM UTC 25
Peak memory	216808 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1302527683 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/cov erage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_delays.1302527683
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/43.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_same_source.977895307
Short name	T763
Test name
Test status
Simulation time	191403072 ps
CPU time	16.86 seconds
Started	Feb 08 09:11:48 AM UTC 25
Finished	Feb 08 09:12:07 AM UTC 25
Peak memory	216592 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=977895307 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.977895307
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/43.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke.2070110053
Short name	T739
Test name
Test status
Simulation time	30225926 ps
CPU time	3.35 seconds
Started	Feb 08 09:11:34 AM UTC 25
Finished	Feb 08 09:11:39 AM UTC 25
Peak memory	217048 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2070110053 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build _mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.2070110053
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/43.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke_large_delays.2624015676
Short name	T769
Test name
Test status
Simulation time	11705777576 ps
CPU time	38.36 seconds
Started	Feb 08 09:11:35 AM UTC 25
Finished	Feb 08 09:12:16 AM UTC 25
Peak memory	216928 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2624015676 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/ xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.2624015676
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/43.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke_slow_rsp.843061328
Short name	T764
Test name
Test status
Simulation time	4285108229 ps
CPU time	30.11 seconds
Started	Feb 08 09:11:37 AM UTC 25
Finished	Feb 08 09:12:09 AM UTC 25
Peak memory	216860 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=843061328 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST _SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.843061328
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/43.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke_zero_delays.2653753247
Short name	T740
Test name
Test status
Simulation time	31076156 ps
CPU time	2.92 seconds
Started	Feb 08 09:11:35 AM UTC 25
Finished	Feb 08 09:11:40 AM UTC 25
Peak memory	216784 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2653753247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/cove rage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delays.2653753247
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/43.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all.451317557
Short name	T252
Test name
Test status
Simulation time	74165696302 ps
CPU time	404.76 seconds
Started	Feb 08 09:11:52 AM UTC 25
Finished	Feb 08 09:18:42 AM UTC 25
Peak memory	223392 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=451317557 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_b uild_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.451317557
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/43.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_error.505284048
Short name	T761
Test name
Test status
Simulation time	165463805 ps
CPU time	9.73 seconds
Started	Feb 08 09:11:55 AM UTC 25
Finished	Feb 08 09:12:06 AM UTC 25
Peak memory	216812 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=505284048 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ= xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.505284048
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/43.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.3613541094
Short name	T833
Test name
Test status
Simulation time	251197120 ps
CPU time	129.49 seconds
Started	Feb 08 09:11:52 AM UTC 25
Finished	Feb 08 09:14:04 AM UTC 25
Peak memory	222956 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3613541094 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_rand_reset.3613541094
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/43.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.2289103810
Short name	T885
Test name
Test status
Simulation time	3166293143 ps
CPU time	292.13 seconds
Started	Feb 08 09:11:56 AM UTC 25
Finished	Feb 08 09:16:53 AM UTC 25
Peak memory	235932 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2289103810 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_reset_error.2289103810
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/43.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_unmapped_addr.22525651
Short name	T773
Test name
Test status
Simulation time	812559235 ps
CPU time	31.38 seconds
Started	Feb 08 09:11:49 AM UTC 25
Finished	Feb 08 09:12:23 AM UTC 25
Peak memory	216084 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22525651 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xb ar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.22525651
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/43.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_access_same_device.93084837
Short name	T777
Test name
Test status
Simulation time	193488206 ps
CPU time	18.22 seconds
Started	Feb 08 09:12:07 AM UTC 25
Finished	Feb 08 09:12:27 AM UTC 25
Peak memory	216812 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=93084837 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xb ar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage /xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device.93084837
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/44.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.200500400
Short name	T898
Test name
Test status
Simulation time	70032710579 ps
CPU time	634.48 seconds
Started	Feb 08 09:12:09 AM UTC 25
Finished	Feb 08 09:22:51 AM UTC 25
Peak memory	220552 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=200500400 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST _SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/c overage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device_slow_rsp.200500400
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/44.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_error_and_unmapped_addr.625193035
Short name	T780
Test name
Test status
Simulation time	879409504 ps
CPU time	18.2 seconds
Started	Feb 08 09:12:11 AM UTC 25
Finished	Feb 08 09:12:31 AM UTC 25
Peak memory	217056 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=625193035 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ= xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xb ar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_addr.625193035
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/44.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_error_random.3249717660
Short name	T770
Test name
Test status
Simulation time	135699302 ps
CPU time	6.03 seconds
Started	Feb 08 09:12:09 AM UTC 25
Finished	Feb 08 09:12:17 AM UTC 25
Peak memory	216800 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3249717660 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_bui ld_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.3249717660
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/44.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_random.2811660482
Short name	T771
Test name
Test status
Simulation time	1260199400 ps
CPU time	16.92 seconds
Started	Feb 08 09:12:00 AM UTC 25
Finished	Feb 08 09:12:19 AM UTC 25
Peak memory	216816 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2811660482 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_buil d_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random.2811660482
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/44.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_random_large_delays.1154410482
Short name	T874
Test name
Test status
Simulation time	30418072034 ps
CPU time	231.8 seconds
Started	Feb 08 09:12:04 AM UTC 25
Finished	Feb 08 09:16:00 AM UTC 25
Peak memory	217136 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1154410482 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage /xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.1154410482
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/44.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_random_slow_rsp.1564255050
Short name	T875
Test name
Test status
Simulation time	33588899561 ps
CPU time	235.71 seconds
Started	Feb 08 09:12:04 AM UTC 25
Finished	Feb 08 09:16:05 AM UTC 25
Peak memory	217204 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1564255050 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xba r_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.1564255050
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/44.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_random_zero_delays.3950858522
Short name	T779
Test name
Test status
Simulation time	179743171 ps
CPU time	23.43 seconds
Started	Feb 08 09:12:03 AM UTC 25
Finished	Feb 08 09:12:28 AM UTC 25
Peak memory	216744 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3950858522 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/cov erage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_delays.3950858522
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/44.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_same_source.1965872142
Short name	T782
Test name
Test status
Simulation time	374155966 ps
CPU time	22.97 seconds
Started	Feb 08 09:12:09 AM UTC 25
Finished	Feb 08 09:12:34 AM UTC 25
Peak memory	216804 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1965872142 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.1965872142
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/44.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke.858233095
Short name	T757
Test name
Test status
Simulation time	35239064 ps
CPU time	3.4 seconds
Started	Feb 08 09:11:56 AM UTC 25
Finished	Feb 08 09:12:02 AM UTC 25
Peak memory	216792 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=858233095 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_ mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.858233095
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/44.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_large_delays.1952294436
Short name	T788
Test name
Test status
Simulation time	7259822621 ps
CPU time	42.67 seconds
Started	Feb 08 09:12:00 AM UTC 25
Finished	Feb 08 09:12:44 AM UTC 25
Peak memory	216864 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1952294436 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/ xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.1952294436
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/44.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_slow_rsp.297300241
Short name	T778
Test name
Test status
Simulation time	2978642295 ps
CPU time	25.98 seconds
Started	Feb 08 09:12:00 AM UTC 25
Finished	Feb 08 09:12:28 AM UTC 25
Peak memory	216860 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=297300241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST _SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.297300241
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/44.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_zero_delays.559628298
Short name	T759
Test name
Test status
Simulation time	33167497 ps
CPU time	3.38 seconds
Started	Feb 08 09:11:58 AM UTC 25
Finished	Feb 08 09:12:03 AM UTC 25
Peak memory	216724 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=559628298 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/cover age/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delays.559628298
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/44.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all.1332941383
Short name	T800
Test name
Test status
Simulation time	424044948 ps
CPU time	49.53 seconds
Started	Feb 08 09:12:12 AM UTC 25
Finished	Feb 08 09:13:04 AM UTC 25
Peak memory	218860 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1332941383 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.1332941383
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/44.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_error.875556
Short name	T809
Test name
Test status
Simulation time	3354370192 ps
CPU time	65.76 seconds
Started	Feb 08 09:12:14 AM UTC 25
Finished	Feb 08 09:13:22 AM UTC 25
Peak memory	218856 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=875556 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xba r_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_bui ld_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.875556
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/44.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_rand_reset.3059440153
Short name	T890
Test name
Test status
Simulation time	5687903847 ps
CPU time	427.56 seconds
Started	Feb 08 09:12:14 AM UTC 25
Finished	Feb 08 09:19:27 AM UTC 25
Peak memory	223320 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3059440153 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_rand_reset.3059440153
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/44.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.2960833782
Short name	T891
Test name
Test status
Simulation time	8274774462 ps
CPU time	433.17 seconds
Started	Feb 08 09:12:17 AM UTC 25
Finished	Feb 08 09:19:37 AM UTC 25
Peak memory	233564 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2960833782 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_reset_error.2960833782
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/44.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_unmapped_addr.2637868284
Short name	T781
Test name
Test status
Simulation time	522787643 ps
CPU time	19.37 seconds
Started	Feb 08 09:12:11 AM UTC 25
Finished	Feb 08 09:12:32 AM UTC 25
Peak memory	217068 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2637868284 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xb ar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.2637868284
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/44.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_access_same_device.1280631324
Short name	T798
Test name
Test status
Simulation time	495299431 ps
CPU time	30.26 seconds
Started	Feb 08 09:12:27 AM UTC 25
Finished	Feb 08 09:13:00 AM UTC 25
Peak memory	218860 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1280631324 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/covera ge/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device.1280631324
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/45.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.2731510297
Short name	T814
Test name
Test status
Simulation time	9526986841 ps
CPU time	63.92 seconds
Started	Feb 08 09:12:29 AM UTC 25
Finished	Feb 08 09:13:36 AM UTC 25
Peak memory	216876 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2731510297 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/ coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device_slow_rsp.2731510297
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/45.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_error_and_unmapped_addr.1409622571
Short name	T787
Test name
Test status
Simulation time	103465939 ps
CPU time	8.37 seconds
Started	Feb 08 09:12:33 AM UTC 25
Finished	Feb 08 09:12:44 AM UTC 25
Peak memory	216876 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1409622571 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/x bar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_addr.1409622571
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/45.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_error_random.3940032195
Short name	T732
Test name
Test status
Simulation time	796355882 ps
CPU time	40.83 seconds
Started	Feb 08 09:12:32 AM UTC 25
Finished	Feb 08 09:13:15 AM UTC 25
Peak memory	216872 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3940032195 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_bui ld_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.3940032195
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/45.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_random.1052142803
Short name	T789
Test name
Test status
Simulation time	430445923 ps
CPU time	19.51 seconds
Started	Feb 08 09:12:24 AM UTC 25
Finished	Feb 08 09:12:46 AM UTC 25
Peak memory	216816 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1052142803 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_buil d_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random.1052142803
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/45.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_random_large_delays.3604701926
Short name	T231
Test name
Test status
Simulation time	29339713049 ps
CPU time	185.22 seconds
Started	Feb 08 09:12:26 AM UTC 25
Finished	Feb 08 09:15:34 AM UTC 25
Peak memory	216808 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3604701926 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage /xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.3604701926
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/45.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_random_slow_rsp.3575282089
Short name	T876
Test name
Test status
Simulation time	22470389788 ps
CPU time	215.88 seconds
Started	Feb 08 09:12:27 AM UTC 25
Finished	Feb 08 09:16:07 AM UTC 25
Peak memory	216812 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3575282089 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xba r_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.3575282089
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/45.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_random_zero_delays.517724766
Short name	T784
Test name
Test status
Simulation time	86878154 ps
CPU time	11.1 seconds
Started	Feb 08 09:12:24 AM UTC 25
Finished	Feb 08 09:12:37 AM UTC 25
Peak memory	217064 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=517724766 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/cove rage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_delays.517724766
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/45.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_same_source.1166182193
Short name	T792
Test name
Test status
Simulation time	671796565 ps
CPU time	18.8 seconds
Started	Feb 08 09:12:29 AM UTC 25
Finished	Feb 08 09:12:51 AM UTC 25
Peak memory	217132 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1166182193 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.1166182193
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/45.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke.2702092899
Short name	T774
Test name
Test status
Simulation time	101695606 ps
CPU time	2.73 seconds
Started	Feb 08 09:12:19 AM UTC 25
Finished	Feb 08 09:12:23 AM UTC 25
Peak memory	216792 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2702092899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build _mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.2702092899
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/45.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_large_delays.2416877572
Short name	T796
Test name
Test status
Simulation time	6910320728 ps
CPU time	28.46 seconds
Started	Feb 08 09:12:22 AM UTC 25
Finished	Feb 08 09:12:53 AM UTC 25
Peak memory	216864 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2416877572 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/ xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.2416877572
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/45.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_slow_rsp.3933873475
Short name	T803
Test name
Test status
Simulation time	3480428733 ps
CPU time	47.99 seconds
Started	Feb 08 09:12:22 AM UTC 25
Finished	Feb 08 09:13:13 AM UTC 25
Peak memory	217180 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3933873475 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.3933873475
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/45.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_zero_delays.4023383290
Short name	T775
Test name
Test status
Simulation time	104396172 ps
CPU time	2.77 seconds
Started	Feb 08 09:12:20 AM UTC 25
Finished	Feb 08 09:12:25 AM UTC 25
Peak memory	216784 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4023383290 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/cove rage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delays.4023383290
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/45.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all.3313219880
Short name	T804
Test name
Test status
Simulation time	1480965445 ps
CPU time	34.42 seconds
Started	Feb 08 09:12:36 AM UTC 25
Finished	Feb 08 09:13:13 AM UTC 25
Peak memory	219180 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3313219880 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.3313219880
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/45.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_error.3942467821
Short name	T816
Test name
Test status
Simulation time	1150475140 ps
CPU time	59.32 seconds
Started	Feb 08 09:12:38 AM UTC 25
Finished	Feb 08 09:13:40 AM UTC 25
Peak memory	221164 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3942467821 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.3942467821
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/45.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.186186559
Short name	T42
Test name
Test status
Simulation time	799666376 ps
CPU time	272.37 seconds
Started	Feb 08 09:12:36 AM UTC 25
Finished	Feb 08 09:17:14 AM UTC 25
Peak memory	223212 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=186186559 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs /coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_rand_reset.186186559
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/45.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_reset_error.2405805014
Short name	T830
Test name
Test status
Simulation time	214937141 ps
CPU time	77.37 seconds
Started	Feb 08 09:12:40 AM UTC 25
Finished	Feb 08 09:14:00 AM UTC 25
Peak memory	220904 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2405805014 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_reset_error.2405805014
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/45.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_unmapped_addr.2058036013
Short name	T786
Test name
Test status
Simulation time	114030108 ps
CPU time	4.62 seconds
Started	Feb 08 09:12:33 AM UTC 25
Finished	Feb 08 09:12:40 AM UTC 25
Peak memory	216708 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2058036013 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xb ar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.2058036013
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/45.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_access_same_device.3232416197
Short name	T810
Test name
Test status
Simulation time	1556427755 ps
CPU time	30.84 seconds
Started	Feb 08 09:12:52 AM UTC 25
Finished	Feb 08 09:13:25 AM UTC 25
Peak memory	216744 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3232416197 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/covera ge/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device.3232416197
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/46.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.4155341270
Short name	T167
Test name
Test status
Simulation time	33087027012 ps
CPU time	331.58 seconds
Started	Feb 08 09:12:54 AM UTC 25
Finished	Feb 08 09:18:30 AM UTC 25
Peak memory	218864 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4155341270 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/ coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device_slow_rsp.4155341270
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/46.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.777955694
Short name	T801
Test name
Test status
Simulation time	19823078 ps
CPU time	3.49 seconds
Started	Feb 08 09:12:59 AM UTC 25
Finished	Feb 08 09:13:04 AM UTC 25
Peak memory	216788 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=777955694 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ= xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xb ar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_addr.777955694
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/46.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_error_random.4129247355
Short name	T808
Test name
Test status
Simulation time	1499448253 ps
CPU time	24.9 seconds
Started	Feb 08 09:12:54 AM UTC 25
Finished	Feb 08 09:13:20 AM UTC 25
Peak memory	216804 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4129247355 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_bui ld_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.4129247355
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/46.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_random.2778177026
Short name	T794
Test name
Test status
Simulation time	25310354 ps
CPU time	2.84 seconds
Started	Feb 08 09:12:47 AM UTC 25
Finished	Feb 08 09:12:51 AM UTC 25
Peak memory	217072 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2778177026 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_buil d_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random.2778177026
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/46.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_random_large_delays.1923662464
Short name	T886
Test name
Test status
Simulation time	126762423768 ps
CPU time	239.98 seconds
Started	Feb 08 09:12:50 AM UTC 25
Finished	Feb 08 09:16:53 AM UTC 25
Peak memory	217136 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1923662464 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage /xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.1923662464
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/46.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_random_slow_rsp.4030066787
Short name	T861
Test name
Test status
Simulation time	12131027471 ps
CPU time	121.39 seconds
Started	Feb 08 09:12:52 AM UTC 25
Finished	Feb 08 09:14:56 AM UTC 25
Peak memory	216880 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4030066787 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xba r_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.4030066787
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/46.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_random_zero_delays.3728647493
Short name	T799
Test name
Test status
Simulation time	114514857 ps
CPU time	13.63 seconds
Started	Feb 08 09:12:48 AM UTC 25
Finished	Feb 08 09:13:04 AM UTC 25
Peak memory	216808 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3728647493 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/cov erage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_delays.3728647493
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/46.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_same_source.2956046139
Short name	T812
Test name
Test status
Simulation time	1081635861 ps
CPU time	33.64 seconds
Started	Feb 08 09:12:54 AM UTC 25
Finished	Feb 08 09:13:29 AM UTC 25
Peak memory	216748 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2956046139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.2956046139
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/46.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke.1325028541
Short name	T791
Test name
Test status
Simulation time	303949002 ps
CPU time	4.75 seconds
Started	Feb 08 09:12:42 AM UTC 25
Finished	Feb 08 09:12:48 AM UTC 25
Peak memory	216728 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1325028541 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build _mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.1325028541
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/46.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_large_delays.4263399026
Short name	T815
Test name
Test status
Simulation time	29015825120 ps
CPU time	51.8 seconds
Started	Feb 08 09:12:46 AM UTC 25
Finished	Feb 08 09:13:40 AM UTC 25
Peak memory	217112 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4263399026 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/ xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.4263399026
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/46.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.104162256
Short name	T805
Test name
Test status
Simulation time	4650361262 ps
CPU time	28.79 seconds
Started	Feb 08 09:12:46 AM UTC 25
Finished	Feb 08 09:13:16 AM UTC 25
Peak memory	216860 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=104162256 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST _SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.104162256
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/46.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.2273940213
Short name	T790
Test name
Test status
Simulation time	146515298 ps
CPU time	3.21 seconds
Started	Feb 08 09:12:43 AM UTC 25
Finished	Feb 08 09:12:48 AM UTC 25
Peak memory	216788 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2273940213 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/cove rage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delays.2273940213
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/46.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all.2453610603
Short name	T855
Test name
Test status
Simulation time	3116127916 ps
CPU time	98 seconds
Started	Feb 08 09:13:01 AM UTC 25
Finished	Feb 08 09:14:42 AM UTC 25
Peak memory	219052 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2453610603 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.2453610603
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/46.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_error.1800876335
Short name	T866
Test name
Test status
Simulation time	5504071918 ps
CPU time	116.37 seconds
Started	Feb 08 09:13:06 AM UTC 25
Finished	Feb 08 09:15:05 AM UTC 25
Peak memory	218856 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1800876335 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.1800876335
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/46.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_rand_reset.3118037719
Short name	T889
Test name
Test status
Simulation time	1081318569 ps
CPU time	336.51 seconds
Started	Feb 08 09:13:06 AM UTC 25
Finished	Feb 08 09:18:47 AM UTC 25
Peak memory	221224 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3118037719 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_rand_reset.3118037719
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/46.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_reset_error.1161807144
Short name	T871
Test name
Test status
Simulation time	2020618616 ps
CPU time	154.51 seconds
Started	Feb 08 09:13:06 AM UTC 25
Finished	Feb 08 09:15:43 AM UTC 25
Peak memory	223176 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1161807144 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_reset_error.1161807144
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/46.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_unmapped_addr.816805837
Short name	T811
Test name
Test status
Simulation time	171988144 ps
CPU time	28.58 seconds
Started	Feb 08 09:12:55 AM UTC 25
Finished	Feb 08 09:13:26 AM UTC 25
Peak memory	216816 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=816805837 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xba r_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.816805837
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/46.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_access_same_device.3722977293
Short name	T269
Test name
Test status
Simulation time	452830164 ps
CPU time	5.32 seconds
Started	Feb 08 09:13:21 AM UTC 25
Finished	Feb 08 09:13:28 AM UTC 25
Peak memory	216808 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3722977293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/covera ge/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device.3722977293
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/47.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_access_same_device_slow_rsp.2694289933
Short name	T301
Test name
Test status
Simulation time	5763824340 ps
CPU time	57.89 seconds
Started	Feb 08 09:13:24 AM UTC 25
Finished	Feb 08 09:14:24 AM UTC 25
Peak memory	217132 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2694289933 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/ coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device_slow_rsp.2694289933
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/47.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.3908530992
Short name	T818
Test name
Test status
Simulation time	200084464 ps
CPU time	9.67 seconds
Started	Feb 08 09:13:30 AM UTC 25
Finished	Feb 08 09:13:42 AM UTC 25
Peak memory	216808 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3908530992 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/x bar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_addr.3908530992
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/47.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_error_random.1850446597
Short name	T826
Test name
Test status
Simulation time	1551178806 ps
CPU time	24.18 seconds
Started	Feb 08 09:13:27 AM UTC 25
Finished	Feb 08 09:13:54 AM UTC 25
Peak memory	216804 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1850446597 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_bui ld_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.1850446597
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/47.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_random.3890170766
Short name	T819
Test name
Test status
Simulation time	966942322 ps
CPU time	23.32 seconds
Started	Feb 08 09:13:17 AM UTC 25
Finished	Feb 08 09:13:42 AM UTC 25
Peak memory	217076 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3890170766 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_buil d_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random.3890170766
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/47.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_random_large_delays.858027999
Short name	T880
Test name
Test status
Simulation time	96659182961 ps
CPU time	179.64 seconds
Started	Feb 08 09:13:20 AM UTC 25
Finished	Feb 08 09:16:23 AM UTC 25
Peak memory	219216 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=858027999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/ xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.858027999
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/47.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_random_slow_rsp.3265549978
Short name	T165
Test name
Test status
Simulation time	31005405906 ps
CPU time	158.89 seconds
Started	Feb 08 09:13:20 AM UTC 25
Finished	Feb 08 09:16:02 AM UTC 25
Peak memory	219168 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3265549978 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xba r_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.3265549978
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/47.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_random_zero_delays.977381003
Short name	T822
Test name
Test status
Simulation time	172005818 ps
CPU time	25.26 seconds
Started	Feb 08 09:13:18 AM UTC 25
Finished	Feb 08 09:13:46 AM UTC 25
Peak memory	217064 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=977381003 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/cove rage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_delays.977381003
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/47.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_same_source.531037718
Short name	T832
Test name
Test status
Simulation time	1607068570 ps
CPU time	35.97 seconds
Started	Feb 08 09:13:26 AM UTC 25
Finished	Feb 08 09:14:04 AM UTC 25
Peak memory	217068 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=531037718 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.531037718
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/47.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke.1596708863
Short name	T737
Test name
Test status
Simulation time	537387646 ps
CPU time	5.93 seconds
Started	Feb 08 09:13:07 AM UTC 25
Finished	Feb 08 09:13:15 AM UTC 25
Peak memory	216792 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1596708863 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build _mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.1596708863
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/47.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_large_delays.3916957721
Short name	T827
Test name
Test status
Simulation time	16847216609 ps
CPU time	39.25 seconds
Started	Feb 08 09:13:15 AM UTC 25
Finished	Feb 08 09:13:56 AM UTC 25
Peak memory	216860 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3916957721 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/ xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.3916957721
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/47.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_slow_rsp.3061554961
Short name	T828
Test name
Test status
Simulation time	6546389406 ps
CPU time	37.56 seconds
Started	Feb 08 09:13:17 AM UTC 25
Finished	Feb 08 09:13:57 AM UTC 25
Peak memory	217116 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3061554961 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.3061554961
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/47.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.1417486770
Short name	T806
Test name
Test status
Simulation time	41954605 ps
CPU time	3.14 seconds
Started	Feb 08 09:13:14 AM UTC 25
Finished	Feb 08 09:13:19 AM UTC 25
Peak memory	216784 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1417486770 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/cove rage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delays.1417486770
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/47.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all.328951867
Short name	T156
Test name
Test status
Simulation time	2391705012 ps
CPU time	64.96 seconds
Started	Feb 08 09:13:30 AM UTC 25
Finished	Feb 08 09:14:38 AM UTC 25
Peak memory	219184 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=328951867 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_b uild_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.328951867
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/47.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_error.3137653591
Short name	T879
Test name
Test status
Simulation time	5592077322 ps
CPU time	157.01 seconds
Started	Feb 08 09:13:37 AM UTC 25
Finished	Feb 08 09:16:17 AM UTC 25
Peak memory	218924 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3137653591 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.3137653591
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/47.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.4089031287
Short name	T894
Test name
Test status
Simulation time	6294307332 ps
CPU time	435.95 seconds
Started	Feb 08 09:13:37 AM UTC 25
Finished	Feb 08 09:20:59 AM UTC 25
Peak memory	223324 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4089031287 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_rand_reset.4089031287
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/47.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_reset_error.1480043873
Short name	T864
Test name
Test status
Simulation time	143949143 ps
CPU time	76.56 seconds
Started	Feb 08 09:13:41 AM UTC 25
Finished	Feb 08 09:15:00 AM UTC 25
Peak memory	220840 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1480043873 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_reset_error.1480043873
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/47.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_unmapped_addr.2346054541
Short name	T817
Test name
Test status
Simulation time	308600274 ps
CPU time	11.06 seconds
Started	Feb 08 09:13:29 AM UTC 25
Finished	Feb 08 09:13:41 AM UTC 25
Peak memory	216744 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2346054541 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xb ar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.2346054541
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/47.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_access_same_device.1827705367
Short name	T852
Test name
Test status
Simulation time	669826158 ps
CPU time	48.66 seconds
Started	Feb 08 09:13:48 AM UTC 25
Finished	Feb 08 09:14:39 AM UTC 25
Peak memory	216720 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1827705367 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/covera ge/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device.1827705367
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/48.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.4011571375
Short name	T895
Test name
Test status
Simulation time	59067938494 ps
CPU time	439.24 seconds
Started	Feb 08 09:13:48 AM UTC 25
Finished	Feb 08 09:21:13 AM UTC 25
Peak memory	218864 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4011571375 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/ coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device_slow_rsp.4011571375
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/48.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.1915483245
Short name	T844
Test name
Test status
Simulation time	238998686 ps
CPU time	18.22 seconds
Started	Feb 08 09:14:00 AM UTC 25
Finished	Feb 08 09:14:20 AM UTC 25
Peak memory	217004 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1915483245 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/x bar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_addr.1915483245
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/48.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_error_random.4039190208
Short name	T839
Test name
Test status
Simulation time	1210034755 ps
CPU time	13.66 seconds
Started	Feb 08 09:13:56 AM UTC 25
Finished	Feb 08 09:14:11 AM UTC 25
Peak memory	216736 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4039190208 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_bui ld_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.4039190208
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/48.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_random.326851690
Short name	T836
Test name
Test status
Simulation time	141456090 ps
CPU time	22.91 seconds
Started	Feb 08 09:13:45 AM UTC 25
Finished	Feb 08 09:14:09 AM UTC 25
Peak memory	216940 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=326851690 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build _mode.vdb -cm_log /dev/null -cm_name 48.xbar_random.326851690
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/48.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_random_large_delays.739949636
Short name	T850
Test name
Test status
Simulation time	7403933689 ps
CPU time	38.89 seconds
Started	Feb 08 09:13:46 AM UTC 25
Finished	Feb 08 09:14:27 AM UTC 25
Peak memory	216884 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=739949636 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/ xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.739949636
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/48.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_random_slow_rsp.4019222997
Short name	T831
Test name
Test status
Simulation time	1687729527 ps
CPU time	12.69 seconds
Started	Feb 08 09:13:48 AM UTC 25
Finished	Feb 08 09:14:03 AM UTC 25
Peak memory	216796 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4019222997 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xba r_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.4019222997
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/48.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_random_zero_delays.1903143391
Short name	T829
Test name
Test status
Simulation time	51733966 ps
CPU time	10.94 seconds
Started	Feb 08 09:13:46 AM UTC 25
Finished	Feb 08 09:13:59 AM UTC 25
Peak memory	217064 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1903143391 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/cov erage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_delays.1903143391
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/48.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_same_source.2768454453
Short name	T835
Test name
Test status
Simulation time	701077721 ps
CPU time	17.36 seconds
Started	Feb 08 09:13:50 AM UTC 25
Finished	Feb 08 09:14:09 AM UTC 25
Peak memory	216812 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2768454453 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.2768454453
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/48.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke.1418951292
Short name	T825
Test name
Test status
Simulation time	950993369 ps
CPU time	6.25 seconds
Started	Feb 08 09:13:41 AM UTC 25
Finished	Feb 08 09:13:49 AM UTC 25
Peak memory	216728 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1418951292 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build _mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.1418951292
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/48.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_large_delays.1567543955
Short name	T846
Test name
Test status
Simulation time	6403687494 ps
CPU time	36.84 seconds
Started	Feb 08 09:13:42 AM UTC 25
Finished	Feb 08 09:14:21 AM UTC 25
Peak memory	217120 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1567543955 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/ xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.1567543955
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/48.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_slow_rsp.2718716573
Short name	T843
Test name
Test status
Simulation time	3746897921 ps
CPU time	32.91 seconds
Started	Feb 08 09:13:45 AM UTC 25
Finished	Feb 08 09:14:19 AM UTC 25
Peak memory	217120 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2718716573 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.2718716573
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/48.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_zero_delays.3581339363
Short name	T823
Test name
Test status
Simulation time	65003351 ps
CPU time	3.41 seconds
Started	Feb 08 09:13:42 AM UTC 25
Finished	Feb 08 09:13:47 AM UTC 25
Peak memory	216784 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3581339363 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/cove rage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delays.3581339363
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/48.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all.1552251991
Short name	T847
Test name
Test status
Simulation time	170792121 ps
CPU time	20.54 seconds
Started	Feb 08 09:14:00 AM UTC 25
Finished	Feb 08 09:14:22 AM UTC 25
Peak memory	219052 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1552251991 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.1552251991
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/48.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_error.1549736166
Short name	T834
Test name
Test status
Simulation time	65423719 ps
CPU time	2.06 seconds
Started	Feb 08 09:14:02 AM UTC 25
Finished	Feb 08 09:14:06 AM UTC 25
Peak memory	216792 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1549736166 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.1549736166
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/48.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.3091390584
Short name	T862
Test name
Test status
Simulation time	49337448 ps
CPU time	52.1 seconds
Started	Feb 08 09:14:02 AM UTC 25
Finished	Feb 08 09:14:56 AM UTC 25
Peak memory	218796 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3091390584 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_rand_reset.3091390584
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/48.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.3888234820
Short name	T840
Test name
Test status
Simulation time	75740185 ps
CPU time	11.27 seconds
Started	Feb 08 09:14:05 AM UTC 25
Finished	Feb 08 09:14:18 AM UTC 25
Peak memory	216808 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3888234820 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_reset_error.3888234820
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/48.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_unmapped_addr.50063432
Short name	T68
Test name
Test status
Simulation time	598917103 ps
CPU time	14.6 seconds
Started	Feb 08 09:14:00 AM UTC 25
Finished	Feb 08 09:14:16 AM UTC 25
Peak memory	216748 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=50063432 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xb ar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.50063432
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/48.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_access_same_device.127568508
Short name	T868
Test name
Test status
Simulation time	2395782156 ps
CPU time	63.14 seconds
Started	Feb 08 09:14:17 AM UTC 25
Finished	Feb 08 09:15:22 AM UTC 25
Peak memory	216876 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=127568508 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverag e/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device.127568508
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/49.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.3531731291
Short name	T896
Test name
Test status
Simulation time	44116739156 ps
CPU time	438.14 seconds
Started	Feb 08 09:14:20 AM UTC 25
Finished	Feb 08 09:21:44 AM UTC 25
Peak memory	219164 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3531731291 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/ coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device_slow_rsp.3531731291
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/49.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.1805468058
Short name	T858
Test name
Test status
Simulation time	789588800 ps
CPU time	22.47 seconds
Started	Feb 08 09:14:23 AM UTC 25
Finished	Feb 08 09:14:48 AM UTC 25
Peak memory	216544 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1805468058 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/x bar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_addr.1805468058
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/49.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_error_random.1199947980
Short name	T849
Test name
Test status
Simulation time	40184390 ps
CPU time	5.12 seconds
Started	Feb 08 09:14:20 AM UTC 25
Finished	Feb 08 09:14:27 AM UTC 25
Peak memory	216800 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1199947980 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_bui ld_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.1199947980
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/49.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_random.2773861064
Short name	T848
Test name
Test status
Simulation time	190321757 ps
CPU time	12.13 seconds
Started	Feb 08 09:14:11 AM UTC 25
Finished	Feb 08 09:14:25 AM UTC 25
Peak memory	216816 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2773861064 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_buil d_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random.2773861064
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/49.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_random_large_delays.1496814146
Short name	T884
Test name
Test status
Simulation time	17711284156 ps
CPU time	156.27 seconds
Started	Feb 08 09:14:13 AM UTC 25
Finished	Feb 08 09:16:53 AM UTC 25
Peak memory	217092 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1496814146 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage /xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.1496814146
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/49.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_random_slow_rsp.500772909
Short name	T869
Test name
Test status
Simulation time	9501632427 ps
CPU time	72.77 seconds
Started	Feb 08 09:14:13 AM UTC 25
Finished	Feb 08 09:15:29 AM UTC 25
Peak memory	217196 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=500772909 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST _SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.500772909
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/49.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_random_zero_delays.2016255121
Short name	T845
Test name
Test status
Simulation time	40085114 ps
CPU time	5.68 seconds
Started	Feb 08 09:14:13 AM UTC 25
Finished	Feb 08 09:14:20 AM UTC 25
Peak memory	217032 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2016255121 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/cov erage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_delays.2016255121
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/49.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_same_source.3840710947
Short name	T857
Test name
Test status
Simulation time	1269727994 ps
CPU time	25.02 seconds
Started	Feb 08 09:14:20 AM UTC 25
Finished	Feb 08 09:14:47 AM UTC 25
Peak memory	217044 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3840710947 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.3840710947
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/49.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke.776853380
Short name	T837
Test name
Test status
Simulation time	116766088 ps
CPU time	4.41 seconds
Started	Feb 08 09:14:05 AM UTC 25
Finished	Feb 08 09:14:11 AM UTC 25
Peak memory	216788 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=776853380 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_ mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.776853380
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/49.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_large_delays.2047905459
Short name	T854
Test name
Test status
Simulation time	5008639785 ps
CPU time	33.31 seconds
Started	Feb 08 09:14:07 AM UTC 25
Finished	Feb 08 09:14:42 AM UTC 25
Peak memory	216860 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2047905459 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/ xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.2047905459
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/49.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.2040742671
Short name	T859
Test name
Test status
Simulation time	6526195204 ps
CPU time	38.24 seconds
Started	Feb 08 09:14:11 AM UTC 25
Finished	Feb 08 09:14:51 AM UTC 25
Peak memory	216792 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2040742671 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.2040742671
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/49.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.1912967366
Short name	T838
Test name
Test status
Simulation time	33961745 ps
CPU time	2.59 seconds
Started	Feb 08 09:14:07 AM UTC 25
Finished	Feb 08 09:14:11 AM UTC 25
Peak memory	216780 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1912967366 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/cove rage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delays.1912967366
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/49.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all.3426223756
Short name	T69
Test name
Test status
Simulation time	2491530441 ps
CPU time	99.22 seconds
Started	Feb 08 09:14:23 AM UTC 25
Finished	Feb 08 09:16:05 AM UTC 25
Peak memory	220972 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3426223756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.3426223756
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/49.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_error.43672094
Short name	T882
Test name
Test status
Simulation time	11516405735 ps
CPU time	141.54 seconds
Started	Feb 08 09:14:26 AM UTC 25
Finished	Feb 08 09:16:50 AM UTC 25
Peak memory	220760 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=43672094 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=x bar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_b uild_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.43672094
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/49.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.4275633705
Short name	T865
Test name
Test status
Simulation time	108741507 ps
CPU time	36.64 seconds
Started	Feb 08 09:14:23 AM UTC 25
Finished	Feb 08 09:15:02 AM UTC 25
Peak memory	218860 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4275633705 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_rand_reset.4275633705
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/49.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_reset_error.77710066
Short name	T873
Test name
Test status
Simulation time	2431698469 ps
CPU time	90.22 seconds
Started	Feb 08 09:14:26 AM UTC 25
Finished	Feb 08 09:15:59 AM UTC 25
Peak memory	218604 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=77710066 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=x bar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs /coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_reset_error.77710066
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/49.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_unmapped_addr.889679455
Short name	T851
Test name
Test status
Simulation time	532072212 ps
CPU time	5.75 seconds
Started	Feb 08 09:14:23 AM UTC 25
Finished	Feb 08 09:14:31 AM UTC 25
Peak memory	216560 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=889679455 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xba r_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.889679455
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/49.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_access_same_device.3199253123
Short name	T79
Test name
Test status
Simulation time	4730832336 ps
CPU time	33.01 seconds
Started	Feb 08 08:54:08 AM UTC 25
Finished	Feb 08 08:54:43 AM UTC 25
Peak memory	219240 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3199253123 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/covera ge/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device.3199253123
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/5.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_error_and_unmapped_addr.1937959897
Short name	T92
Test name
Test status
Simulation time	187750784 ps
CPU time	7.34 seconds
Started	Feb 08 08:54:10 AM UTC 25
Finished	Feb 08 08:54:18 AM UTC 25
Peak memory	216800 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1937959897 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/x bar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr.1937959897
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/5.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_error_random.1885859847
Short name	T259
Test name
Test status
Simulation time	513988474 ps
CPU time	16.96 seconds
Started	Feb 08 08:54:09 AM UTC 25
Finished	Feb 08 08:54:28 AM UTC 25
Peak memory	216316 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1885859847 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_bui ld_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.1885859847
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/5.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_random.596472537
Short name	T93
Test name
Test status
Simulation time	360940097 ps
CPU time	15.09 seconds
Started	Feb 08 08:54:02 AM UTC 25
Finished	Feb 08 08:54:19 AM UTC 25
Peak memory	217068 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=596472537 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build _mode.vdb -cm_log /dev/null -cm_name 5.xbar_random.596472537
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/5.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_random_large_delays.1323160400
Short name	T191
Test name
Test status
Simulation time	87702278856 ps
CPU time	197.54 seconds
Started	Feb 08 08:54:04 AM UTC 25
Finished	Feb 08 08:57:25 AM UTC 25
Peak memory	216884 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1323160400 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage /xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.1323160400
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/5.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_random_slow_rsp.4139989098
Short name	T221
Test name
Test status
Simulation time	66395760542 ps
CPU time	237.56 seconds
Started	Feb 08 08:54:07 AM UTC 25
Finished	Feb 08 08:58:08 AM UTC 25
Peak memory	219184 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4139989098 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xba r_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.4139989098
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/5.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_random_zero_delays.4091046984
Short name	T334
Test name
Test status
Simulation time	463792299 ps
CPU time	31.24 seconds
Started	Feb 08 08:54:04 AM UTC 25
Finished	Feb 08 08:54:37 AM UTC 25
Peak memory	216744 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4091046984 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/cov erage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_delays.4091046984
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/5.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_same_source.824975259
Short name	T95
Test name
Test status
Simulation time	1813457092 ps
CPU time	16.03 seconds
Started	Feb 08 08:54:08 AM UTC 25
Finished	Feb 08 08:54:26 AM UTC 25
Peak memory	217072 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=824975259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.824975259
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/5.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_smoke.80553965
Short name	T197
Test name
Test status
Simulation time	103707911 ps
CPU time	4.8 seconds
Started	Feb 08 08:53:57 AM UTC 25
Finished	Feb 08 08:54:03 AM UTC 25
Peak memory	216984 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=80553965 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xb ar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_m ode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.80553965
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/5.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_smoke_large_delays.4156678228
Short name	T254
Test name
Test status
Simulation time	18218465783 ps
CPU time	56.02 seconds
Started	Feb 08 08:54:01 AM UTC 25
Finished	Feb 08 08:54:59 AM UTC 25
Peak memory	216864 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4156678228 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/ xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.4156678228
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/5.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_smoke_slow_rsp.1899573460
Short name	T170
Test name
Test status
Simulation time	5879139460 ps
CPU time	40.17 seconds
Started	Feb 08 08:54:02 AM UTC 25
Finished	Feb 08 08:54:44 AM UTC 25
Peak memory	216792 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1899573460 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.1899573460
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/5.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_smoke_zero_delays.2308353719
Short name	T198
Test name
Test status
Simulation time	31416007 ps
CPU time	3.28 seconds
Started	Feb 08 08:53:59 AM UTC 25
Finished	Feb 08 08:54:03 AM UTC 25
Peak memory	216724 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2308353719 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/cove rage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays.2308353719
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/5.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_stress_all.1886050587
Short name	T190
Test name
Test status
Simulation time	113345460 ps
CPU time	25.37 seconds
Started	Feb 08 08:54:12 AM UTC 25
Finished	Feb 08 08:54:39 AM UTC 25
Peak memory	216812 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1886050587 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.1886050587
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/5.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_stress_all_with_error.195660341
Short name	T116
Test name
Test status
Simulation time	1743006031 ps
CPU time	161.59 seconds
Started	Feb 08 08:54:15 AM UTC 25
Finished	Feb 08 08:57:00 AM UTC 25
Peak memory	223284 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=195660341 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ= xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.195660341
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/5.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_stress_all_with_rand_reset.2427620026
Short name	T330
Test name
Test status
Simulation time	3480812182 ps
CPU time	453.12 seconds
Started	Feb 08 08:54:13 AM UTC 25
Finished	Feb 08 09:01:52 AM UTC 25
Peak memory	223020 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2427620026 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_rand_reset.2427620026
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/5.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_stress_all_with_reset_error.2743918537
Short name	T328
Test name
Test status
Simulation time	5235535161 ps
CPU time	208.62 seconds
Started	Feb 08 08:54:15 AM UTC 25
Finished	Feb 08 08:57:47 AM UTC 25
Peak memory	222956 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2743918537 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_reset_error.2743918537
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/5.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_unmapped_addr.2898195164
Short name	T78
Test name
Test status
Simulation time	687632097 ps
CPU time	28.77 seconds
Started	Feb 08 08:54:10 AM UTC 25
Finished	Feb 08 08:54:40 AM UTC 25
Peak memory	216228 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2898195164 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xb ar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.2898195164
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/5.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_access_same_device.322058797
Short name	T174
Test name
Test status
Simulation time	479638003 ps
CPU time	18.65 seconds
Started	Feb 08 08:54:27 AM UTC 25
Finished	Feb 08 08:54:48 AM UTC 25
Peak memory	217076 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=322058797 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverag e/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device.322058797
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/6.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_access_same_device_slow_rsp.113406841
Short name	T273
Test name
Test status
Simulation time	35350880420 ps
CPU time	262.7 seconds
Started	Feb 08 08:54:29 AM UTC 25
Finished	Feb 08 08:58:56 AM UTC 25
Peak memory	218932 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=113406841 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST _SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/c overage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device_slow_rsp.113406841
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/6.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_error_and_unmapped_addr.1819894501
Short name	T339
Test name
Test status
Simulation time	1588614407 ps
CPU time	27.74 seconds
Started	Feb 08 08:54:39 AM UTC 25
Finished	Feb 08 08:55:09 AM UTC 25
Peak memory	216808 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1819894501 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/x bar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr.1819894501
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/6.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_error_random.2133155775
Short name	T172
Test name
Test status
Simulation time	94565073 ps
CPU time	5.6 seconds
Started	Feb 08 08:54:38 AM UTC 25
Finished	Feb 08 08:54:45 AM UTC 25
Peak memory	216568 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2133155775 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_bui ld_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.2133155775
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/6.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_random.2039545834
Short name	T168
Test name
Test status
Simulation time	197330957 ps
CPU time	15.6 seconds
Started	Feb 08 08:54:25 AM UTC 25
Finished	Feb 08 08:54:43 AM UTC 25
Peak memory	216772 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2039545834 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_buil d_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random.2039545834
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/6.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_random_large_delays.3795018872
Short name	T282
Test name
Test status
Simulation time	54841019482 ps
CPU time	140.11 seconds
Started	Feb 08 08:54:26 AM UTC 25
Finished	Feb 08 08:56:49 AM UTC 25
Peak memory	216876 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3795018872 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage /xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.3795018872
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/6.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_random_slow_rsp.3522014597
Short name	T203
Test name
Test status
Simulation time	55586038496 ps
CPU time	219.76 seconds
Started	Feb 08 08:54:27 AM UTC 25
Finished	Feb 08 08:58:11 AM UTC 25
Peak memory	217136 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3522014597 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xba r_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.3522014597
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/6.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_random_zero_delays.711408240
Short name	T260
Test name
Test status
Simulation time	22630705 ps
CPU time	2.4 seconds
Started	Feb 08 08:54:25 AM UTC 25
Finished	Feb 08 08:54:30 AM UTC 25
Peak memory	216804 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=711408240 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/cove rage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_delays.711408240
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/6.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_same_source.4053799048
Short name	T169
Test name
Test status
Simulation time	351068789 ps
CPU time	11.05 seconds
Started	Feb 08 08:54:31 AM UTC 25
Finished	Feb 08 08:54:43 AM UTC 25
Peak memory	216812 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4053799048 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.4053799048
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/6.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_smoke.176250371
Short name	T5
Test name
Test status
Simulation time	159798038 ps
CPU time	5.23 seconds
Started	Feb 08 08:54:18 AM UTC 25
Finished	Feb 08 08:54:25 AM UTC 25
Peak memory	217052 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=176250371 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_ mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.176250371
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/6.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_smoke_large_delays.2857532661
Short name	T342
Test name
Test status
Simulation time	18377466710 ps
CPU time	54.15 seconds
Started	Feb 08 08:54:19 AM UTC 25
Finished	Feb 08 08:55:15 AM UTC 25
Peak memory	217120 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2857532661 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/ xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.2857532661
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/6.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_smoke_slow_rsp.2090018512
Short name	T340
Test name
Test status
Simulation time	8328829915 ps
CPU time	43.65 seconds
Started	Feb 08 08:54:25 AM UTC 25
Finished	Feb 08 08:55:11 AM UTC 25
Peak memory	217104 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2090018512 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.2090018512
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/6.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_smoke_zero_delays.899200313
Short name	T94
Test name
Test status
Simulation time	34609511 ps
CPU time	3.18 seconds
Started	Feb 08 08:54:19 AM UTC 25
Finished	Feb 08 08:54:24 AM UTC 25
Peak memory	216784 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=899200313 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/cover age/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays.899200313
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/6.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_stress_all.3005602870
Short name	T335
Test name
Test status
Simulation time	467464326 ps
CPU time	26.27 seconds
Started	Feb 08 08:54:40 AM UTC 25
Finished	Feb 08 08:55:09 AM UTC 25
Peak memory	218796 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3005602870 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.3005602870
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/6.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_stress_all_with_error.4004996528
Short name	T266
Test name
Test status
Simulation time	2564283911 ps
CPU time	62.56 seconds
Started	Feb 08 08:54:42 AM UTC 25
Finished	Feb 08 08:55:47 AM UTC 25
Peak memory	217132 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4004996528 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.4004996528
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/6.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_stress_all_with_rand_reset.4019350467
Short name	T272
Test name
Test status
Simulation time	894418476 ps
CPU time	326.72 seconds
Started	Feb 08 08:54:40 AM UTC 25
Finished	Feb 08 09:00:12 AM UTC 25
Peak memory	221164 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4019350467 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_rand_reset.4019350467
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/6.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_stress_all_with_reset_error.2537489128
Short name	T322
Test name
Test status
Simulation time	472310612 ps
CPU time	143.62 seconds
Started	Feb 08 08:54:43 AM UTC 25
Finished	Feb 08 08:57:10 AM UTC 25
Peak memory	223216 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2537489128 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_reset_error.2537489128
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/6.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_unmapped_addr.3436615408
Short name	T80
Test name
Test status
Simulation time	668320335 ps
CPU time	29.74 seconds
Started	Feb 08 08:54:38 AM UTC 25
Finished	Feb 08 08:55:10 AM UTC 25
Peak memory	218832 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3436615408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xb ar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.3436615408
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/6.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_access_same_device.3471849498
Short name	T323
Test name
Test status
Simulation time	35027960 ps
CPU time	7.08 seconds
Started	Feb 08 08:54:51 AM UTC 25
Finished	Feb 08 08:55:00 AM UTC 25
Peak memory	216728 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3471849498 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/covera ge/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device.3471849498
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/7.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_access_same_device_slow_rsp.1042038547
Short name	T312
Test name
Test status
Simulation time	47738526814 ps
CPU time	392.08 seconds
Started	Feb 08 08:54:52 AM UTC 25
Finished	Feb 08 09:01:29 AM UTC 25
Peak memory	218928 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1042038547 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/ coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device_slow_rsp.1042038547
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/7.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_error_and_unmapped_addr.221329029
Short name	T345
Test name
Test status
Simulation time	157675190 ps
CPU time	17.75 seconds
Started	Feb 08 08:55:01 AM UTC 25
Finished	Feb 08 08:55:21 AM UTC 25
Peak memory	217064 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=221329029 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ= xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xb ar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr.221329029
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/7.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_error_random.2695393104
Short name	T338
Test name
Test status
Simulation time	231611060 ps
CPU time	7.14 seconds
Started	Feb 08 08:54:56 AM UTC 25
Finished	Feb 08 08:55:05 AM UTC 25
Peak memory	216808 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2695393104 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_bui ld_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.2695393104
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/7.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_random.500948607
Short name	T344
Test name
Test status
Simulation time	663889545 ps
CPU time	28.46 seconds
Started	Feb 08 08:54:46 AM UTC 25
Finished	Feb 08 08:55:17 AM UTC 25
Peak memory	216812 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=500948607 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build _mode.vdb -cm_log /dev/null -cm_name 7.xbar_random.500948607
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/7.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_random_large_delays.3511470972
Short name	T378
Test name
Test status
Simulation time	30066090031 ps
CPU time	261.31 seconds
Started	Feb 08 08:54:49 AM UTC 25
Finished	Feb 08 08:59:15 AM UTC 25
Peak memory	219252 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3511470972 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage /xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.3511470972
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/7.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_random_slow_rsp.418055524
Short name	T241
Test name
Test status
Simulation time	93761537078 ps
CPU time	221.47 seconds
Started	Feb 08 08:54:50 AM UTC 25
Finished	Feb 08 08:58:35 AM UTC 25
Peak memory	216816 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=418055524 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST _SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.418055524
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/7.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_random_zero_delays.1798732282
Short name	T337
Test name
Test status
Simulation time	34088509 ps
CPU time	6.95 seconds
Started	Feb 08 08:54:47 AM UTC 25
Finished	Feb 08 08:54:56 AM UTC 25
Peak memory	216744 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1798732282 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/cov erage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_delays.1798732282
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/7.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_same_source.3209973754
Short name	T263
Test name
Test status
Simulation time	5388054176 ps
CPU time	49.65 seconds
Started	Feb 08 08:54:54 AM UTC 25
Finished	Feb 08 08:55:46 AM UTC 25
Peak memory	216812 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3209973754 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.3209973754
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/7.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_smoke.102722864
Short name	T51
Test name
Test status
Simulation time	39393240 ps
CPU time	2.53 seconds
Started	Feb 08 08:54:44 AM UTC 25
Finished	Feb 08 08:54:49 AM UTC 25
Peak memory	216108 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=102722864 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_ mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.102722864
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/7.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_smoke_large_delays.890369518
Short name	T98
Test name
Test status
Simulation time	6233554817 ps
CPU time	36.93 seconds
Started	Feb 08 08:54:44 AM UTC 25
Finished	Feb 08 08:55:24 AM UTC 25
Peak memory	217180 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=890369518 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/x bar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.890369518
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/7.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_smoke_slow_rsp.1141208008
Short name	T255
Test name
Test status
Simulation time	11603646259 ps
CPU time	49.52 seconds
Started	Feb 08 08:54:46 AM UTC 25
Finished	Feb 08 08:55:38 AM UTC 25
Peak memory	216856 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1141208008 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.1141208008
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/7.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_smoke_zero_delays.2991034860
Short name	T336
Test name
Test status
Simulation time	44663241 ps
CPU time	3.13 seconds
Started	Feb 08 08:54:44 AM UTC 25
Finished	Feb 08 08:54:50 AM UTC 25
Peak memory	215932 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2991034860 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/cove rage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays.2991034860
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/7.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_stress_all.2778839845
Short name	T105
Test name
Test status
Simulation time	19112488663 ps
CPU time	294.87 seconds
Started	Feb 08 08:55:02 AM UTC 25
Finished	Feb 08 09:00:02 AM UTC 25
Peak memory	223020 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2778839845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.2778839845
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/7.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_stress_all_with_error.2062150355
Short name	T285
Test name
Test status
Simulation time	4280953257 ps
CPU time	102.48 seconds
Started	Feb 08 08:55:08 AM UTC 25
Finished	Feb 08 08:56:54 AM UTC 25
Peak memory	220908 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2062150355 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.2062150355
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/7.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_stress_all_with_rand_reset.485764535
Short name	T332
Test name
Test status
Simulation time	1398812979 ps
CPU time	433.48 seconds
Started	Feb 08 08:55:06 AM UTC 25
Finished	Feb 08 09:02:26 AM UTC 25
Peak memory	223216 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=485764535 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs /coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_rand_reset.485764535
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/7.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_stress_all_with_reset_error.520863870
Short name	T466
Test name
Test status
Simulation time	9721858263 ps
CPU time	485.69 seconds
Started	Feb 08 08:55:10 AM UTC 25
Finished	Feb 08 09:03:22 AM UTC 25
Peak memory	233944 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=520863870 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ= xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_reset_error.520863870
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/7.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_unmapped_addr.473860831
Short name	T341
Test name
Test status
Simulation time	624480867 ps
CPU time	10.15 seconds
Started	Feb 08 08:55:01 AM UTC 25
Finished	Feb 08 08:55:13 AM UTC 25
Peak memory	217072 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=473860831 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xba r_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.473860831
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/7.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_access_same_device.1136817856
Short name	T81
Test name
Test status
Simulation time	962459465 ps
CPU time	29.7 seconds
Started	Feb 08 08:55:21 AM UTC 25
Finished	Feb 08 08:55:53 AM UTC 25
Peak memory	219116 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1136817856 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/covera ge/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device.1136817856
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/8.xbar_access_same_device/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_error_and_unmapped_addr.4056958636
Short name	T264
Test name
Test status
Simulation time	234349011 ps
CPU time	14.09 seconds
Started	Feb 08 08:55:31 AM UTC 25
Finished	Feb 08 08:55:46 AM UTC 25
Peak memory	216736 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4056958636 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/x bar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr.4056958636
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/8.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_error_random.1671107620
Short name	T346
Test name
Test status
Simulation time	92306980 ps
CPU time	3.83 seconds
Started	Feb 08 08:55:24 AM UTC 25
Finished	Feb 08 08:55:30 AM UTC 25
Peak memory	217064 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1671107620 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_bui ld_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.1671107620
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/8.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_random.845243005
Short name	T176
Test name
Test status
Simulation time	4524115647 ps
CPU time	48.48 seconds
Started	Feb 08 08:55:16 AM UTC 25
Finished	Feb 08 08:56:06 AM UTC 25
Peak memory	218836 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=845243005 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build _mode.vdb -cm_log /dev/null -cm_name 8.xbar_random.845243005
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/8.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_random_large_delays.1685596718
Short name	T348
Test name
Test status
Simulation time	6206997713 ps
CPU time	16.13 seconds
Started	Feb 08 08:55:18 AM UTC 25
Finished	Feb 08 08:55:36 AM UTC 25
Peak memory	216872 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1685596718 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage /xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.1685596718
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/8.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_random_slow_rsp.3600961538
Short name	T58
Test name
Test status
Simulation time	29602583192 ps
CPU time	235.03 seconds
Started	Feb 08 08:55:18 AM UTC 25
Finished	Feb 08 08:59:17 AM UTC 25
Peak memory	216880 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3600961538 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xba r_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.3600961538
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/8.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_random_zero_delays.3382311296
Short name	T347
Test name
Test status
Simulation time	111366188 ps
CPU time	13.18 seconds
Started	Feb 08 08:55:16 AM UTC 25
Finished	Feb 08 08:55:31 AM UTC 25
Peak memory	216744 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3382311296 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/cov erage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_delays.3382311296
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/8.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_same_source.116474366
Short name	T233
Test name
Test status
Simulation time	86312330 ps
CPU time	8.44 seconds
Started	Feb 08 08:55:23 AM UTC 25
Finished	Feb 08 08:55:34 AM UTC 25
Peak memory	216812 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=116474366 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.116474366
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/8.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_smoke.3093095900
Short name	T295
Test name
Test status
Simulation time	403943319 ps
CPU time	4.84 seconds
Started	Feb 08 08:55:11 AM UTC 25
Finished	Feb 08 08:55:17 AM UTC 25
Peak memory	217112 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3093095900 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build _mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.3093095900
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/8.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_smoke_large_delays.2009507730
Short name	T183
Test name
Test status
Simulation time	37631153478 ps
CPU time	68.26 seconds
Started	Feb 08 08:55:12 AM UTC 25
Finished	Feb 08 08:56:22 AM UTC 25
Peak memory	216852 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2009507730 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/ xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.2009507730
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/8.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_smoke_slow_rsp.1663189974
Short name	T356
Test name
Test status
Simulation time	30665448555 ps
CPU time	80.11 seconds
Started	Feb 08 08:55:14 AM UTC 25
Finished	Feb 08 08:56:36 AM UTC 25
Peak memory	216856 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1663189974 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.1663189974
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/8.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_smoke_zero_delays.3669357089
Short name	T343
Test name
Test status
Simulation time	87541951 ps
CPU time	3.25 seconds
Started	Feb 08 08:55:11 AM UTC 25
Finished	Feb 08 08:55:15 AM UTC 25
Peak memory	216788 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3669357089 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/cove rage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays.3669357089
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/8.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_stress_all.2751316186
Short name	T88
Test name
Test status
Simulation time	7206162143 ps
CPU time	144.35 seconds
Started	Feb 08 08:55:32 AM UTC 25
Finished	Feb 08 08:57:59 AM UTC 25
Peak memory	218860 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2751316186 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.2751316186
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/8.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_stress_all_with_error.4147131710
Short name	T184
Test name
Test status
Simulation time	1576965891 ps
CPU time	46.62 seconds
Started	Feb 08 08:55:35 AM UTC 25
Finished	Feb 08 08:56:23 AM UTC 25
Peak memory	216812 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4147131710 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.4147131710
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/8.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_stress_all_with_rand_reset.3880859284
Short name	T45
Test name
Test status
Simulation time	513616866 ps
CPU time	195.2 seconds
Started	Feb 08 08:55:33 AM UTC 25
Finished	Feb 08 08:58:51 AM UTC 25
Peak memory	220904 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3880859284 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_rand_reset.3880859284
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/8.xbar_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_stress_all_with_reset_error.1421250606
Short name	T38
Test name
Test status
Simulation time	329698750 ps
CPU time	108.98 seconds
Started	Feb 08 08:55:37 AM UTC 25
Finished	Feb 08 08:57:28 AM UTC 25
Peak memory	222960 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1421250606 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_reset_error.1421250606
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/8.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_unmapped_addr.4027068778
Short name	T239
Test name
Test status
Simulation time	548526956 ps
CPU time	23.98 seconds
Started	Feb 08 08:55:27 AM UTC 25
Finished	Feb 08 08:55:53 AM UTC 25
Peak memory	218800 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4027068778 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xb ar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.4027068778
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/8.xbar_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_access_same_device_slow_rsp.3935304741
Short name	T578
Test name
Test status
Simulation time	141990500705 ps
CPU time	657.94 seconds
Started	Feb 08 08:55:54 AM UTC 25
Finished	Feb 08 09:07:00 AM UTC 25
Peak memory	222732 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3935304741 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/ coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device_slow_rsp.3935304741
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/9.xbar_access_same_device_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_error_and_unmapped_addr.2995995639
Short name	T350
Test name
Test status
Simulation time	1209072445 ps
CPU time	20.43 seconds
Started	Feb 08 08:56:02 AM UTC 25
Finished	Feb 08 08:56:24 AM UTC 25
Peak memory	216800 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2995995639 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/x bar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr.2995995639
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/9.xbar_error_and_unmapped_addr/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_error_random.2245595440
Short name	T351
Test name
Test status
Simulation time	1263711912 ps
CPU time	30.7 seconds
Started	Feb 08 08:55:56 AM UTC 25
Finished	Feb 08 08:56:28 AM UTC 25
Peak memory	216748 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2245595440 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_bui ld_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.2245595440
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/9.xbar_error_random/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_random.37537339
Short name	T179
Test name
Test status
Simulation time	420176831 ps
CPU time	22.2 seconds
Started	Feb 08 08:55:48 AM UTC 25
Finished	Feb 08 08:56:12 AM UTC 25
Peak memory	216944 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37537339 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xb ar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_ mode.vdb -cm_log /dev/null -cm_name 9.xbar_random.37537339
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/9.xbar_random/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_random_large_delays.2469916519
Short name	T103
Test name
Test status
Simulation time	37581465151 ps
CPU time	204.71 seconds
Started	Feb 08 08:55:48 AM UTC 25
Finished	Feb 08 08:59:16 AM UTC 25
Peak memory	216880 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2469916519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage /xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.2469916519
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/9.xbar_random_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_random_slow_rsp.588409061
Short name	T55
Test name
Test status
Simulation time	49825497808 ps
CPU time	115.75 seconds
Started	Feb 08 08:55:50 AM UTC 25
Finished	Feb 08 08:57:48 AM UTC 25
Peak memory	217136 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=588409061 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST _SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.588409061
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/9.xbar_random_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_random_zero_delays.2592463154
Short name	T181
Test name
Test status
Simulation time	276653108 ps
CPU time	23.69 seconds
Started	Feb 08 08:55:48 AM UTC 25
Finished	Feb 08 08:56:13 AM UTC 25
Peak memory	217068 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2592463154 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/cov erage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_delays.2592463154
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/9.xbar_random_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_same_source.2790011619
Short name	T349
Test name
Test status
Simulation time	63777113 ps
CPU time	3.56 seconds
Started	Feb 08 08:55:54 AM UTC 25
Finished	Feb 08 08:56:00 AM UTC 25
Peak memory	216748 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2790011619 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.2790011619
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/9.xbar_same_source/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_smoke.486476172
Short name	T262
Test name
Test status
Simulation time	134145722 ps
CPU time	3.56 seconds
Started	Feb 08 08:55:39 AM UTC 25
Finished	Feb 08 08:55:44 AM UTC 25
Peak memory	216728 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=486476172 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_ mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.486476172
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/9.xbar_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_smoke_large_delays.3723308253
Short name	T354
Test name
Test status
Simulation time	19520337904 ps
CPU time	48.92 seconds
Started	Feb 08 08:55:44 AM UTC 25
Finished	Feb 08 08:56:35 AM UTC 25
Peak memory	216860 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3723308253 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/ xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.3723308253
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/9.xbar_smoke_large_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_smoke_slow_rsp.1916975545
Short name	T52
Test name
Test status
Simulation time	20639900743 ps
CPU time	42.63 seconds
Started	Feb 08 08:55:46 AM UTC 25
Finished	Feb 08 08:56:31 AM UTC 25
Peak memory	217116 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1916975545 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.1916975545
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/9.xbar_smoke_slow_rsp/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_smoke_zero_delays.4143901257
Short name	T265
Test name
Test status
Simulation time	61680914 ps
CPU time	3.55 seconds
Started	Feb 08 08:55:41 AM UTC 25
Finished	Feb 08 08:55:46 AM UTC 25
Peak memory	216788 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4143901257 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/cove rage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays.4143901257
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/9.xbar_smoke_zero_delays/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_stress_all.1634114456
Short name	T89
Test name
Test status
Simulation time	12854136508 ps
CPU time	116.02 seconds
Started	Feb 08 08:56:04 AM UTC 25
Finished	Feb 08 08:58:03 AM UTC 25
Peak memory	218924 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1634114456 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.1634114456
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/9.xbar_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_stress_all_with_error.4287899709
Short name	T286
Test name
Test status
Simulation time	1276194634 ps
CPU time	45.39 seconds
Started	Feb 08 08:56:08 AM UTC 25
Finished	Feb 08 08:56:56 AM UTC 25
Peak memory	216808 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4287899709 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.4287899709
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/9.xbar_stress_all_with_error/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_stress_all_with_reset_error.2275061062
Short name	T34
Test name
Test status
Simulation time	1867490315 ps
CPU time	254.52 seconds
Started	Feb 08 08:56:12 AM UTC 25
Finished	Feb 08 09:00:31 AM UTC 25
Peak memory	223328 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2275061062 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_reset_error.2275061062
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/9.xbar_stress_all_with_reset_error/latest

Test location	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_unmapped_addr.2283820509
Short name	T178
Test name
Test status
Simulation time	1202793047 ps
CPU time	8.32 seconds
Started	Feb 08 08:56:01 AM UTC 25
Finished	Feb 08 08:56:10 AM UTC 25
Peak memory	216752 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2283820509 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/coverage/xb ar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.2283820509
Directory	/workspaces/repo/scratch/os_regression/xbar_main-sim-vcs/9.xbar_unmapped_addr/latest