| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 97.22 | 99.26 | 88.92 | 100.00 | 95.88 | 99.28 | 100.00 |
| T772 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_unmapped_addr.1049068161 | Oct 14 09:10:00 PM UTC 24 | Oct 14 09:10:24 PM UTC 24 | 558960610 ps | ||
| T773 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_zero_delays.1424807473 | Oct 14 09:10:21 PM UTC 24 | Oct 14 09:10:25 PM UTC 24 | 35671636 ps | ||
| T774 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all_with_reset_error.2536098097 | Oct 14 09:07:20 PM UTC 24 | Oct 14 09:10:26 PM UTC 24 | 1214844399 ps | ||
| T775 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all_with_reset_error.2672720183 | Oct 14 09:08:40 PM UTC 24 | Oct 14 09:10:27 PM UTC 24 | 341016502 ps | ||
| T776 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all_with_error.1601966159 | Oct 14 09:08:22 PM UTC 24 | Oct 14 09:10:28 PM UTC 24 | 3434956780 ps | ||
| T777 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_error_random.2752728353 | Oct 14 09:10:00 PM UTC 24 | Oct 14 09:10:29 PM UTC 24 | 1285254216 ps | ||
| T247 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all.3035443228 | Oct 14 09:08:18 PM UTC 24 | Oct 14 09:10:31 PM UTC 24 | 1361190679 ps | ||
| T778 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_random_zero_delays.770241133 | Oct 14 09:10:13 PM UTC 24 | Oct 14 09:10:32 PM UTC 24 | 98978901 ps | ||
| T779 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_random_zero_delays.2542481337 | Oct 14 09:10:26 PM UTC 24 | Oct 14 09:10:33 PM UTC 24 | 69009326 ps | ||
| T780 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke_large_delays.127622619 | Oct 14 09:09:50 PM UTC 24 | Oct 14 09:10:34 PM UTC 24 | 9560583294 ps | ||
| T158 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_access_same_device_slow_rsp.688522812 | Oct 14 09:06:59 PM UTC 24 | Oct 14 09:10:35 PM UTC 24 | 36106792684 ps | ||
| T781 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_reset_error.1382139209 | Oct 14 09:09:00 PM UTC 24 | Oct 14 09:10:35 PM UTC 24 | 507183807 ps | ||
| T782 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_slow_rsp.2300123591 | Oct 14 09:10:08 PM UTC 24 | Oct 14 09:10:38 PM UTC 24 | 4916376978 ps | ||
| T783 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_error_and_unmapped_addr.1543326462 | Oct 14 09:10:16 PM UTC 24 | Oct 14 09:10:39 PM UTC 24 | 188898922 ps | ||
| T42 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_stress_all_with_rand_reset.1245258303 | Oct 14 09:05:16 PM UTC 24 | Oct 14 09:10:39 PM UTC 24 | 786970740 ps | ||
| T784 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_error.3246604559 | Oct 14 09:09:44 PM UTC 24 | Oct 14 09:10:41 PM UTC 24 | 784548960 ps | ||
| T165 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_access_same_device_slow_rsp.2458252694 | Oct 14 09:06:12 PM UTC 24 | Oct 14 09:10:42 PM UTC 24 | 52210639656 ps | ||
| T785 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_same_source.2255837744 | Oct 14 09:10:13 PM UTC 24 | Oct 14 09:10:43 PM UTC 24 | 3641358372 ps | ||
| T786 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all.325912348 | Oct 14 09:09:00 PM UTC 24 | Oct 14 09:10:43 PM UTC 24 | 4995080600 ps | ||
| T787 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_random.2912834196 | Oct 14 09:10:08 PM UTC 24 | Oct 14 09:10:44 PM UTC 24 | 963202681 ps | ||
| T788 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_error_random.3413485277 | Oct 14 09:10:32 PM UTC 24 | Oct 14 09:10:44 PM UTC 24 | 410575830 ps | ||
| T789 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.2240731764 | Oct 14 09:10:41 PM UTC 24 | Oct 14 09:10:45 PM UTC 24 | 47870738 ps | ||
| T790 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke.521958786 | Oct 14 09:10:41 PM UTC 24 | Oct 14 09:10:46 PM UTC 24 | 359310910 ps | ||
| T791 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_unmapped_addr.1633307016 | Oct 14 09:10:16 PM UTC 24 | Oct 14 09:10:46 PM UTC 24 | 2473565343 ps | ||
| T792 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all.28530638 | Oct 14 09:10:36 PM UTC 24 | Oct 14 09:10:46 PM UTC 24 | 291525173 ps | ||
| T793 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.1397159731 | Oct 14 09:10:18 PM UTC 24 | Oct 14 09:10:47 PM UTC 24 | 170691681 ps | ||
| T794 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_error.3857373880 | Oct 14 09:10:05 PM UTC 24 | Oct 14 09:10:47 PM UTC 24 | 489354165 ps | ||
| T795 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_error_random.1637465345 | Oct 14 09:10:16 PM UTC 24 | Oct 14 09:10:48 PM UTC 24 | 1725998143 ps | ||
| T796 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_large_delays.164071484 | Oct 14 09:10:08 PM UTC 24 | Oct 14 09:10:49 PM UTC 24 | 20012153139 ps | ||
| T797 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_same_source.4063719723 | Oct 14 09:10:30 PM UTC 24 | Oct 14 09:10:50 PM UTC 24 | 324021084 ps | ||
| T798 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_error_and_unmapped_addr.4085071582 | Oct 14 09:10:34 PM UTC 24 | Oct 14 09:10:50 PM UTC 24 | 168566371 ps | ||
| T799 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all_with_rand_reset.447908647 | Oct 14 09:08:40 PM UTC 24 | Oct 14 09:10:51 PM UTC 24 | 239870328 ps | ||
| T800 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_random.3529279342 | Oct 14 09:10:45 PM UTC 24 | Oct 14 09:10:53 PM UTC 24 | 33287752 ps | ||
| T801 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_random.1851601931 | Oct 14 09:10:26 PM UTC 24 | Oct 14 09:10:54 PM UTC 24 | 884156777 ps | ||
| T802 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_unmapped_addr.1001006554 | Oct 14 09:10:34 PM UTC 24 | Oct 14 09:10:57 PM UTC 24 | 636342197 ps | ||
| T803 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.3493274643 | Oct 14 09:10:54 PM UTC 24 | Oct 14 09:10:58 PM UTC 24 | 36695717 ps | ||
| T804 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke.1918481603 | Oct 14 09:10:54 PM UTC 24 | Oct 14 09:11:00 PM UTC 24 | 120665849 ps | ||
| T805 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_random_zero_delays.1549370231 | Oct 14 09:10:45 PM UTC 24 | Oct 14 09:11:00 PM UTC 24 | 149255881 ps | ||
| T806 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_slow_rsp.1570434343 | Oct 14 09:10:26 PM UTC 24 | Oct 14 09:11:05 PM UTC 24 | 6137775404 ps | ||
| T807 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_access_same_device.3416584546 | Oct 14 09:10:46 PM UTC 24 | Oct 14 09:11:06 PM UTC 24 | 1017199394 ps | ||
| T808 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_large_delays.2909345880 | Oct 14 09:10:23 PM UTC 24 | Oct 14 09:11:07 PM UTC 24 | 10031650211 ps | ||
| T809 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all.26185525 | Oct 14 09:10:02 PM UTC 24 | Oct 14 09:11:07 PM UTC 24 | 1552888836 ps | ||
| T810 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_error.1326248720 | Oct 14 09:10:36 PM UTC 24 | Oct 14 09:11:08 PM UTC 24 | 390783017 ps | ||
| T811 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_access_same_device.3419686164 | Oct 14 09:11:08 PM UTC 24 | Oct 14 09:11:12 PM UTC 24 | 20214236 ps | ||
| T812 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_random_zero_delays.865669415 | Oct 14 09:11:01 PM UTC 24 | Oct 14 09:11:12 PM UTC 24 | 52910848 ps | ||
| T813 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_stress_all_with_rand_reset.3634550933 | Oct 14 09:07:03 PM UTC 24 | Oct 14 09:11:12 PM UTC 24 | 503569414 ps | ||
| T814 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.1932900594 | Oct 14 09:10:30 PM UTC 24 | Oct 14 09:11:12 PM UTC 24 | 4723241319 ps | ||
| T815 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.1595078495 | Oct 14 09:10:43 PM UTC 24 | Oct 14 09:11:13 PM UTC 24 | 4884315379 ps | ||
| T816 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_same_source.1654011879 | Oct 14 09:10:48 PM UTC 24 | Oct 14 09:11:13 PM UTC 24 | 595165574 ps | ||
| T68 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_random.3995735011 | Oct 14 09:10:59 PM UTC 24 | Oct 14 09:11:14 PM UTC 24 | 634732613 ps | ||
| T817 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.2872909989 | Oct 14 09:10:51 PM UTC 24 | Oct 14 09:11:14 PM UTC 24 | 1439524377 ps | ||
| T818 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all.1227537842 | Oct 14 09:10:51 PM UTC 24 | Oct 14 09:11:15 PM UTC 24 | 169623748 ps | ||
| T289 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_unmapped_addr.828266976 | Oct 14 09:10:49 PM UTC 24 | Oct 14 09:11:19 PM UTC 24 | 498131072 ps | ||
| T819 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_same_source.3031966097 | Oct 14 09:11:10 PM UTC 24 | Oct 14 09:11:19 PM UTC 24 | 320341455 ps | ||
| T820 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_access_same_device.1731077621 | Oct 14 09:10:28 PM UTC 24 | Oct 14 09:11:19 PM UTC 24 | 2788558854 ps | ||
| T821 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_error_random.1888178749 | Oct 14 09:10:49 PM UTC 24 | Oct 14 09:11:20 PM UTC 24 | 1430262401 ps | ||
| T822 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_zero_delays.557082934 | Oct 14 09:11:17 PM UTC 24 | Oct 14 09:11:21 PM UTC 24 | 29964874 ps | ||
| T823 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_large_delays.1900157971 | Oct 14 09:10:55 PM UTC 24 | Oct 14 09:11:23 PM UTC 24 | 6730880541 ps | ||
| T824 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke.3162442187 | Oct 14 09:11:17 PM UTC 24 | Oct 14 09:11:23 PM UTC 24 | 134496876 ps | ||
| T825 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_random_large_delays.2901916012 | Oct 14 09:09:34 PM UTC 24 | Oct 14 09:11:25 PM UTC 24 | 36566856525 ps | ||
| T826 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_large_delays.1477860717 | Oct 14 09:10:43 PM UTC 24 | Oct 14 09:11:25 PM UTC 24 | 10321869124 ps | ||
| T173 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.2239949019 | Oct 14 09:11:14 PM UTC 24 | Oct 14 09:11:31 PM UTC 24 | 95663421 ps | ||
| T827 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_random_large_delays.2201808862 | Oct 14 09:10:13 PM UTC 24 | Oct 14 09:11:31 PM UTC 24 | 12930029234 ps | ||
| T828 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_error_random.3004898982 | Oct 14 09:11:10 PM UTC 24 | Oct 14 09:11:33 PM UTC 24 | 3452363955 ps | ||
| T829 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.30880994 | Oct 14 09:11:14 PM UTC 24 | Oct 14 09:11:34 PM UTC 24 | 1745462883 ps | ||
| T830 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_random.3234554226 | Oct 14 09:11:21 PM UTC 24 | Oct 14 09:11:35 PM UTC 24 | 471360983 ps | ||
| T831 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all_with_reset_error.1945713378 | Oct 14 09:08:23 PM UTC 24 | Oct 14 09:11:41 PM UTC 24 | 4074489551 ps | ||
| T832 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_random_zero_delays.1861656081 | Oct 14 09:11:23 PM UTC 24 | Oct 14 09:11:42 PM UTC 24 | 158509136 ps | ||
| T833 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_random_slow_rsp.3278643109 | Oct 14 09:10:28 PM UTC 24 | Oct 14 09:11:43 PM UTC 24 | 6377196315 ps | ||
| T834 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_error.1804204645 | Oct 14 09:10:51 PM UTC 24 | Oct 14 09:11:44 PM UTC 24 | 1130362652 ps | ||
| T835 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_slow_rsp.160375360 | Oct 14 09:10:58 PM UTC 24 | Oct 14 09:11:46 PM UTC 24 | 9930745394 ps | ||
| T836 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_same_source.2387606145 | Oct 14 09:11:27 PM UTC 24 | Oct 14 09:11:48 PM UTC 24 | 530322718 ps | ||
| T837 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke.1443190350 | Oct 14 09:11:43 PM UTC 24 | Oct 14 09:11:48 PM UTC 24 | 37650839 ps | ||
| T838 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_stress_all_with_reset_error.2867610595 | Oct 14 09:04:25 PM UTC 24 | Oct 14 09:11:49 PM UTC 24 | 7353798442 ps | ||
| T839 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.1404224938 | Oct 14 09:11:45 PM UTC 24 | Oct 14 09:11:49 PM UTC 24 | 87632147 ps | ||
| T840 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_error_random.1508735249 | Oct 14 09:11:27 PM UTC 24 | Oct 14 09:11:51 PM UTC 24 | 732982012 ps | ||
| T841 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_unmapped_addr.557704531 | Oct 14 09:11:33 PM UTC 24 | Oct 14 09:11:52 PM UTC 24 | 435631850 ps | ||
| T842 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_random_slow_rsp.2888634985 | Oct 14 09:09:09 PM UTC 24 | Oct 14 09:11:53 PM UTC 24 | 61552316550 ps | ||
| T843 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_large_delays.154175136 | Oct 14 09:11:17 PM UTC 24 | Oct 14 09:11:54 PM UTC 24 | 11610937991 ps | ||
| T844 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_random_large_delays.3297591269 | Oct 14 09:10:45 PM UTC 24 | Oct 14 09:11:55 PM UTC 24 | 19266172333 ps | ||
| T845 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_unmapped_addr.1252761320 | Oct 14 09:11:14 PM UTC 24 | Oct 14 09:11:55 PM UTC 24 | 2159280075 ps | ||
| T846 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_random.3220773551 | Oct 14 09:11:51 PM UTC 24 | Oct 14 09:11:56 PM UTC 24 | 137552729 ps | ||
| T847 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_random_slow_rsp.1317365310 | Oct 14 09:10:46 PM UTC 24 | Oct 14 09:11:56 PM UTC 24 | 10778403595 ps | ||
| T848 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.2160016230 | Oct 14 09:11:33 PM UTC 24 | Oct 14 09:11:56 PM UTC 24 | 727583772 ps | ||
| T849 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_random_large_delays.1139870785 | Oct 14 09:09:56 PM UTC 24 | Oct 14 09:11:57 PM UTC 24 | 40939151574 ps | ||
| T850 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_slow_rsp.3088229870 | Oct 14 09:11:21 PM UTC 24 | Oct 14 09:11:57 PM UTC 24 | 11250200823 ps | ||
| T248 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_random_zero_delays.3814435915 | Oct 14 09:11:51 PM UTC 24 | Oct 14 09:11:58 PM UTC 24 | 83980873 ps | ||
| T218 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_access_same_device.4204890097 | Oct 14 09:11:25 PM UTC 24 | Oct 14 09:11:58 PM UTC 24 | 296705086 ps | ||
| T851 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.3621403623 | Oct 14 09:08:14 PM UTC 24 | Oct 14 09:12:00 PM UTC 24 | 31444268115 ps | ||
| T852 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.269246825 | Oct 14 09:11:43 PM UTC 24 | Oct 14 09:12:00 PM UTC 24 | 81237284 ps | ||
| T291 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_random_slow_rsp.970491945 | Oct 14 09:10:13 PM UTC 24 | Oct 14 09:12:00 PM UTC 24 | 17174429675 ps | ||
| T205 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_rand_reset.2239662300 | Oct 14 09:09:00 PM UTC 24 | Oct 14 09:12:01 PM UTC 24 | 6749765723 ps | ||
| T853 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all.3541836394 | Oct 14 09:11:14 PM UTC 24 | Oct 14 09:12:02 PM UTC 24 | 525109348 ps | ||
| T854 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_access_same_device.3858493770 | Oct 14 09:11:53 PM UTC 24 | Oct 14 09:12:03 PM UTC 24 | 735828794 ps | ||
| T855 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.2085140940 | Oct 14 09:11:57 PM UTC 24 | Oct 14 09:12:05 PM UTC 24 | 467410294 ps | ||
| T856 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_random_slow_rsp.3133339145 | Oct 14 09:09:56 PM UTC 24 | Oct 14 09:12:06 PM UTC 24 | 9528744409 ps | ||
| T857 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.2589054001 | Oct 14 09:09:42 PM UTC 24 | Oct 14 09:12:07 PM UTC 24 | 490817314 ps | ||
| T858 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_random_slow_rsp.874370204 | Oct 14 09:11:23 PM UTC 24 | Oct 14 09:12:09 PM UTC 24 | 16823818414 ps | ||
| T219 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_stress_all_with_rand_reset.2849572058 | Oct 14 09:04:52 PM UTC 24 | Oct 14 09:12:10 PM UTC 24 | 2467864634 ps | ||
| T859 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_unmapped_addr.2914973039 | Oct 14 09:11:57 PM UTC 24 | Oct 14 09:12:11 PM UTC 24 | 367262025 ps | ||
| T860 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_error_random.845905400 | Oct 14 09:11:57 PM UTC 24 | Oct 14 09:12:11 PM UTC 24 | 118210200 ps | ||
| T861 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_reset_error.3519843900 | Oct 14 09:09:21 PM UTC 24 | Oct 14 09:12:13 PM UTC 24 | 1679704094 ps | ||
| T331 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_random_large_delays.950045609 | Oct 14 09:11:03 PM UTC 24 | Oct 14 09:12:16 PM UTC 24 | 14226708835 ps | ||
| T862 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.657182623 | Oct 14 09:11:48 PM UTC 24 | Oct 14 09:12:22 PM UTC 24 | 4469858660 ps | ||
| T863 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_stress_all_with_reset_error.1587299809 | Oct 14 09:06:26 PM UTC 24 | Oct 14 09:12:24 PM UTC 24 | 10336658566 ps | ||
| T864 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_error.2472816617 | Oct 14 09:09:00 PM UTC 24 | Oct 14 09:12:24 PM UTC 24 | 9042996546 ps | ||
| T865 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_rand_reset.1673045752 | Oct 14 09:10:16 PM UTC 24 | Oct 14 09:12:25 PM UTC 24 | 335662760 ps | ||
| T866 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_same_source.290492856 | Oct 14 09:11:54 PM UTC 24 | Oct 14 09:12:27 PM UTC 24 | 1371324097 ps | ||
| T867 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all.978348222 | Oct 14 09:07:32 PM UTC 24 | Oct 14 09:12:28 PM UTC 24 | 8782380756 ps | ||
| T868 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all.3796139690 | Oct 14 09:11:34 PM UTC 24 | Oct 14 09:12:29 PM UTC 24 | 1612945474 ps | ||
| T869 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_large_delays.681293792 | Oct 14 09:11:45 PM UTC 24 | Oct 14 09:12:35 PM UTC 24 | 5700970306 ps | ||
| T870 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all.1919724234 | Oct 14 09:09:16 PM UTC 24 | Oct 14 09:12:39 PM UTC 24 | 2606333527 ps | ||
| T871 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_random_large_delays.2670494332 | Oct 14 09:11:51 PM UTC 24 | Oct 14 09:12:41 PM UTC 24 | 15364935788 ps | ||
| T872 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_error.3239802694 | Oct 14 09:12:00 PM UTC 24 | Oct 14 09:12:45 PM UTC 24 | 2861184919 ps | ||
| T873 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_error.3438761960 | Oct 14 09:11:36 PM UTC 24 | Oct 14 09:12:45 PM UTC 24 | 4855133101 ps | ||
| T874 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_random_large_delays.2368808138 | Oct 14 09:11:23 PM UTC 24 | Oct 14 09:12:53 PM UTC 24 | 13490846045 ps | ||
| T875 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_access_same_device_slow_rsp.2572883765 | Oct 14 09:08:50 PM UTC 24 | Oct 14 09:12:57 PM UTC 24 | 35927758438 ps | ||
| T876 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.1087187134 | Oct 14 09:10:13 PM UTC 24 | Oct 14 09:13:02 PM UTC 24 | 21043799231 ps | ||
| T877 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_error.534701717 | Oct 14 09:10:17 PM UTC 24 | Oct 14 09:13:02 PM UTC 24 | 6187384183 ps | ||
| T878 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_random_large_delays.1784763905 | Oct 14 09:10:26 PM UTC 24 | Oct 14 09:13:07 PM UTC 24 | 22872697849 ps | ||
| T879 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_error.1634611694 | Oct 14 09:11:14 PM UTC 24 | Oct 14 09:13:08 PM UTC 24 | 1045047753 ps | ||
| T880 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all.3731945023 | Oct 14 09:09:42 PM UTC 24 | Oct 14 09:13:10 PM UTC 24 | 1583132521 ps | ||
| T159 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_access_same_device_slow_rsp.2884562169 | Oct 14 09:09:12 PM UTC 24 | Oct 14 09:13:11 PM UTC 24 | 28412134068 ps | ||
| T43 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_stress_all_with_rand_reset.3997317953 | Oct 14 09:06:22 PM UTC 24 | Oct 14 09:13:16 PM UTC 24 | 753406335 ps | ||
| T881 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_reset_error.273740451 | Oct 14 09:10:51 PM UTC 24 | Oct 14 09:13:19 PM UTC 24 | 161346813 ps | ||
| T882 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.2231531225 | Oct 14 09:09:36 PM UTC 24 | Oct 14 09:13:20 PM UTC 24 | 109507099845 ps | ||
| T883 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all.1620082488 | Oct 14 09:10:16 PM UTC 24 | Oct 14 09:13:20 PM UTC 24 | 6520981603 ps | ||
| T884 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_random_slow_rsp.2345080883 | Oct 14 09:11:51 PM UTC 24 | Oct 14 09:13:32 PM UTC 24 | 31174315154 ps | ||
| T160 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_stress_all_with_rand_reset.883019539 | Oct 14 09:03:21 PM UTC 24 | Oct 14 09:13:34 PM UTC 24 | 13291154183 ps | ||
| T885 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_reset_error.1938987034 | Oct 14 09:10:39 PM UTC 24 | Oct 14 09:13:34 PM UTC 24 | 9762873920 ps | ||
| T886 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.3257082963 | Oct 14 09:11:53 PM UTC 24 | Oct 14 09:13:35 PM UTC 24 | 11539530212 ps | ||
| T887 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_random_slow_rsp.1918989067 | Oct 14 09:11:06 PM UTC 24 | Oct 14 09:13:40 PM UTC 24 | 33616539829 ps | ||
| T69 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_access_same_device_slow_rsp.3460424043 | Oct 14 09:07:46 PM UTC 24 | Oct 14 09:13:41 PM UTC 24 | 35211225132 ps | ||
| T161 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all_with_rand_reset.385709412 | Oct 14 09:07:34 PM UTC 24 | Oct 14 09:13:58 PM UTC 24 | 11252533790 ps | ||
| T888 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_reset_error.3408685112 | Oct 14 09:11:14 PM UTC 24 | Oct 14 09:14:09 PM UTC 24 | 537738703 ps | ||
| T889 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all_with_reset_error.3166403500 | Oct 14 09:07:37 PM UTC 24 | Oct 14 09:14:46 PM UTC 24 | 6440966048 ps | ||
| T890 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all.3338161755 | Oct 14 09:11:57 PM UTC 24 | Oct 14 09:14:46 PM UTC 24 | 11449155243 ps | ||
| T891 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.559213543 | Oct 14 09:10:05 PM UTC 24 | Oct 14 09:14:46 PM UTC 24 | 752297967 ps | ||
| T892 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_access_same_device_slow_rsp.1119110416 | Oct 14 09:08:31 PM UTC 24 | Oct 14 09:14:57 PM UTC 24 | 42768584373 ps | ||
| T893 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.1653930910 | Oct 14 09:09:57 PM UTC 24 | Oct 14 09:15:23 PM UTC 24 | 87733314500 ps | ||
| T894 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.1493949401 | Oct 14 09:10:48 PM UTC 24 | Oct 14 09:15:34 PM UTC 24 | 52584794767 ps | ||
| T166 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.2208216202 | Oct 14 09:11:25 PM UTC 24 | Oct 14 09:16:15 PM UTC 24 | 35373095038 ps | ||
| T895 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.3965864405 | Oct 14 09:10:05 PM UTC 24 | Oct 14 09:16:17 PM UTC 24 | 10914397351 ps | ||
| T896 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_access_same_device_slow_rsp.3866810230 | Oct 14 09:11:10 PM UTC 24 | Oct 14 09:16:36 PM UTC 24 | 69359995440 ps | ||
| T897 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_reset_error.2627928511 | Oct 14 09:12:00 PM UTC 24 | Oct 14 09:17:33 PM UTC 24 | 3919557712 ps | ||
| T898 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.2109276908 | Oct 14 09:10:36 PM UTC 24 | Oct 14 09:18:24 PM UTC 24 | 3188626457 ps | ||
| T319 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.340396983 | Oct 14 09:11:36 PM UTC 24 | Oct 14 09:18:27 PM UTC 24 | 12043075625 ps | ||
| T162 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.3446637027 | Oct 14 09:12:00 PM UTC 24 | Oct 14 09:18:41 PM UTC 24 | 12334081013 ps | ||
| T899 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_rand_reset.2531261741 | Oct 14 09:10:51 PM UTC 24 | Oct 14 09:18:43 PM UTC 24 | 2515582805 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_error_and_unmapped_addr.2634292263 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 265671041 ps |
| CPU time | 8.13 seconds |
| Started | Oct 14 08:56:20 PM UTC 24 |
| Finished | Oct 14 08:56:49 PM UTC 24 |
| Peak memory | 214632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2634292263 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr.2634292263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/1.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_stress_all.1391772622 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 6968990861 ps |
| CPU time | 161.27 seconds |
| Started | Oct 14 08:58:34 PM UTC 24 |
| Finished | Oct 14 09:01:18 PM UTC 24 |
| Peak memory | 221216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1391772622 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.1391772622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/10.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_access_same_device_slow_rsp.2696090029 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 42447361195 ps |
| CPU time | 306.25 seconds |
| Started | Oct 14 08:56:18 PM UTC 24 |
| Finished | Oct 14 09:01:46 PM UTC 24 |
| Peak memory | 218260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2696090029 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device_slow_rsp.2696090029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/0.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_access_same_device_slow_rsp.2031724166 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 53884441734 ps |
| CPU time | 230.93 seconds |
| Started | Oct 14 08:59:36 PM UTC 24 |
| Finished | Oct 14 09:03:30 PM UTC 24 |
| Peak memory | 216724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2031724166 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device_slow_rsp.2031724166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/13.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_stress_all_with_error.607350820 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 1916024189 ps |
| CPU time | 60.96 seconds |
| Started | Oct 14 08:57:05 PM UTC 24 |
| Finished | Oct 14 08:58:08 PM UTC 24 |
| Peak memory | 216684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=607350820 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.607350820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/4.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_access_same_device_slow_rsp.2095961027 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 22537914539 ps |
| CPU time | 227.02 seconds |
| Started | Oct 14 08:58:49 PM UTC 24 |
| Finished | Oct 14 09:02:40 PM UTC 24 |
| Peak memory | 216808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2095961027 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device_slow_rsp.2095961027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/11.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_random_zero_delays.2988728963 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 153852833 ps |
| CPU time | 4.74 seconds |
| Started | Oct 14 08:56:19 PM UTC 24 |
| Finished | Oct 14 08:56:46 PM UTC 24 |
| Peak memory | 214624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2988728963 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_delays.2988728963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/1.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_stress_all_with_error.100963121 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 4670770555 ps |
| CPU time | 168.54 seconds |
| Started | Oct 14 08:56:22 PM UTC 24 |
| Finished | Oct 14 08:59:27 PM UTC 24 |
| Peak memory | 220840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=100963121 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.100963121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/1.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_stress_all_with_rand_reset.1082219705 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 12577446536 ps |
| CPU time | 387.23 seconds |
| Started | Oct 14 08:56:41 PM UTC 24 |
| Finished | Oct 14 09:03:17 PM UTC 24 |
| Peak memory | 222356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1082219705 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_rand_reset.1082219705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/2.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_access_same_device.1385999188 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 1093608417 ps |
| CPU time | 33.17 seconds |
| Started | Oct 14 08:56:18 PM UTC 24 |
| Finished | Oct 14 08:57:10 PM UTC 24 |
| Peak memory | 216876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1385999188 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device.1385999188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/0.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_smoke_large_delays.2117985786 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 12001369055 ps |
| CPU time | 27.88 seconds |
| Started | Oct 14 08:56:19 PM UTC 24 |
| Finished | Oct 14 08:56:59 PM UTC 24 |
| Peak memory | 214676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2117985786 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.2117985786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/1.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_access_same_device.180357504 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 1220376255 ps |
| CPU time | 35.59 seconds |
| Started | Oct 14 08:56:46 PM UTC 24 |
| Finished | Oct 14 08:57:23 PM UTC 24 |
| Peak memory | 214628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=180357504 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xba r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device.180357504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/3.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_error_random.1378799076 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 3027956865 ps |
| CPU time | 26.43 seconds |
| Started | Oct 14 08:56:18 PM UTC 24 |
| Finished | Oct 14 08:57:03 PM UTC 24 |
| Peak memory | 214660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1378799076 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.1378799076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/0.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_same_source.2458638899 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 341485036 ps |
| CPU time | 17.46 seconds |
| Started | Oct 14 08:56:33 PM UTC 24 |
| Finished | Oct 14 08:56:53 PM UTC 24 |
| Peak memory | 214696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2458638899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.2458638899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/2.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_stress_all_with_rand_reset.3757887333 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 13389292902 ps |
| CPU time | 481.05 seconds |
| Started | Oct 14 09:00:02 PM UTC 24 |
| Finished | Oct 14 09:08:13 PM UTC 24 |
| Peak memory | 222364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3757887333 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_rand_reset.3757887333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/14.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_stress_all_with_reset_error.1201907087 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 795099179 ps |
| CPU time | 211.6 seconds |
| Started | Oct 14 08:56:42 PM UTC 24 |
| Finished | Oct 14 09:00:19 PM UTC 24 |
| Peak memory | 231332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1201907087 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_reset_error.1201907087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/2.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_access_same_device.369069281 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 333437331 ps |
| CPU time | 47.96 seconds |
| Started | Oct 14 08:58:26 PM UTC 24 |
| Finished | Oct 14 08:59:16 PM UTC 24 |
| Peak memory | 216680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=369069281 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xba r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device.369069281 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/10.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_stress_all.1012325578 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 4153890322 ps |
| CPU time | 90.17 seconds |
| Started | Oct 14 08:56:52 PM UTC 24 |
| Finished | Oct 14 08:58:25 PM UTC 24 |
| Peak memory | 216748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1012325578 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.1012325578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/3.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_random_slow_rsp.2723191702 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 10688308277 ps |
| CPU time | 45.11 seconds |
| Started | Oct 14 08:57:34 PM UTC 24 |
| Finished | Oct 14 08:58:21 PM UTC 24 |
| Peak memory | 214760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2723191702 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.2723191702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/7.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_access_same_device.3297702300 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 378319113 ps |
| CPU time | 15.28 seconds |
| Started | Oct 14 09:03:55 PM UTC 24 |
| Finished | Oct 14 09:04:12 PM UTC 24 |
| Peak memory | 214636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3297702300 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device.3297702300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/25.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_stress_all_with_rand_reset.2187500783 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 6116123227 ps |
| CPU time | 317.09 seconds |
| Started | Oct 14 08:57:12 PM UTC 24 |
| Finished | Oct 14 09:02:34 PM UTC 24 |
| Peak memory | 221092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2187500783 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_rand_reset.2187500783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/5.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_stress_all_with_reset_error.1438756242 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 1393709926 ps |
| CPU time | 265.19 seconds |
| Started | Oct 14 08:56:53 PM UTC 24 |
| Finished | Oct 14 09:01:29 PM UTC 24 |
| Peak memory | 221288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1438756242 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_reset_error.1438756242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/3.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_access_same_device_slow_rsp.2720731731 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 40360160411 ps |
| CPU time | 333.65 seconds |
| Started | Oct 14 08:56:20 PM UTC 24 |
| Finished | Oct 14 09:02:18 PM UTC 24 |
| Peak memory | 218260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2720731731 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device_slow_rsp.2720731731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/1.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_stress_all_with_rand_reset.3359718756 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 624017614 ps |
| CPU time | 279.81 seconds |
| Started | Oct 14 09:01:11 PM UTC 24 |
| Finished | Oct 14 09:05:55 PM UTC 24 |
| Peak memory | 218724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3359718756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_rand_reset.3359718756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/17.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_same_source.2387163651 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 3687808395 ps |
| CPU time | 13.66 seconds |
| Started | Oct 14 08:56:18 PM UTC 24 |
| Finished | Oct 14 08:56:50 PM UTC 24 |
| Peak memory | 214636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2387163651 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.2387163651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/0.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_random_slow_rsp.2695553434 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 5443125600 ps |
| CPU time | 34.11 seconds |
| Started | Oct 14 08:56:18 PM UTC 24 |
| Finished | Oct 14 08:57:11 PM UTC 24 |
| Peak memory | 214880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2695553434 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.2695553434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/0.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_stress_all_with_reset_error.2281152376 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 609045273 ps |
| CPU time | 233.38 seconds |
| Started | Oct 14 09:06:00 PM UTC 24 |
| Finished | Oct 14 09:09:57 PM UTC 24 |
| Peak memory | 221092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2281152376 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_reset_error.2281152376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/31.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_stress_all_with_rand_reset.3997317953 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 753406335 ps |
| CPU time | 408.74 seconds |
| Started | Oct 14 09:06:22 PM UTC 24 |
| Finished | Oct 14 09:13:16 PM UTC 24 |
| Peak memory | 222292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3997317953 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_rand_reset.3997317953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/32.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_random.3031575416 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 1307992009 ps |
| CPU time | 32.3 seconds |
| Started | Oct 14 08:59:50 PM UTC 24 |
| Finished | Oct 14 09:00:24 PM UTC 24 |
| Peak memory | 214628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3031575416 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random.3031575416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/14.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_access_same_device.2918435371 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 1290043643 ps |
| CPU time | 27.37 seconds |
| Started | Oct 14 08:59:17 PM UTC 24 |
| Finished | Oct 14 08:59:46 PM UTC 24 |
| Peak memory | 214632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2918435371 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device.2918435371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/12.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_error_and_unmapped_addr.159842842 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 467069093 ps |
| CPU time | 14.07 seconds |
| Started | Oct 14 08:56:18 PM UTC 24 |
| Finished | Oct 14 08:56:51 PM UTC 24 |
| Peak memory | 214628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=159842842 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr.159842842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/0.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_random.3459825032 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 881589742 ps |
| CPU time | 32.36 seconds |
| Started | Oct 14 08:56:17 PM UTC 24 |
| Finished | Oct 14 08:57:24 PM UTC 24 |
| Peak memory | 214628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3459825032 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random.3459825032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/0.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_random_large_delays.1760615703 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 5062415263 ps |
| CPU time | 22.85 seconds |
| Started | Oct 14 08:56:18 PM UTC 24 |
| Finished | Oct 14 08:56:59 PM UTC 24 |
| Peak memory | 214700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1760615703 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.1760615703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/0.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_random_zero_delays.327061468 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 140030877 ps |
| CPU time | 15.31 seconds |
| Started | Oct 14 08:56:18 PM UTC 24 |
| Finished | Oct 14 08:56:52 PM UTC 24 |
| Peak memory | 216672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=327061468 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_delays.327061468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/0.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_smoke_large_delays.3161486138 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 12572109549 ps |
| CPU time | 41.35 seconds |
| Started | Oct 14 08:56:17 PM UTC 24 |
| Finished | Oct 14 08:57:33 PM UTC 24 |
| Peak memory | 214588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3161486138 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.3161486138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/0.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_smoke_slow_rsp.1654967975 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 8311493894 ps |
| CPU time | 43.75 seconds |
| Started | Oct 14 08:56:17 PM UTC 24 |
| Finished | Oct 14 08:57:35 PM UTC 24 |
| Peak memory | 214788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1654967975 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.1654967975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/0.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_smoke_zero_delays.2053067358 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 35055927 ps |
| CPU time | 3.52 seconds |
| Started | Oct 14 08:56:17 PM UTC 24 |
| Finished | Oct 14 08:56:55 PM UTC 24 |
| Peak memory | 214604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2053067358 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays.2053067358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/0.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_stress_all.2495985605 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 521939525 ps |
| CPU time | 21.31 seconds |
| Started | Oct 14 08:56:18 PM UTC 24 |
| Finished | Oct 14 08:57:08 PM UTC 24 |
| Peak memory | 216676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2495985605 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.2495985605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/0.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_stress_all_with_error.2786009751 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 1856450503 ps |
| CPU time | 85.4 seconds |
| Started | Oct 14 08:56:18 PM UTC 24 |
| Finished | Oct 14 08:58:13 PM UTC 24 |
| Peak memory | 216688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2786009751 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.2786009751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/0.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_stress_all_with_rand_reset.1497683750 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 675449985 ps |
| CPU time | 173.8 seconds |
| Started | Oct 14 08:56:18 PM UTC 24 |
| Finished | Oct 14 08:59:42 PM UTC 24 |
| Peak memory | 220244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1497683750 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_rand_reset.1497683750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/0.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_stress_all_with_reset_error.309835682 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 190140172 ps |
| CPU time | 41.31 seconds |
| Started | Oct 14 08:56:18 PM UTC 24 |
| Finished | Oct 14 08:57:13 PM UTC 24 |
| Peak memory | 216692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=309835682 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_reset_error.309835682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/0.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/0.xbar_unmapped_addr.2549506173 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 133041565 ps |
| CPU time | 21.73 seconds |
| Started | Oct 14 08:56:18 PM UTC 24 |
| Finished | Oct 14 08:57:09 PM UTC 24 |
| Peak memory | 214628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2549506173 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.2549506173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/0.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_access_same_device.1950389005 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 665505869 ps |
| CPU time | 28.85 seconds |
| Started | Oct 14 08:56:20 PM UTC 24 |
| Finished | Oct 14 08:57:10 PM UTC 24 |
| Peak memory | 216684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1950389005 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device.1950389005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/1.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_error_random.973742824 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 287804461 ps |
| CPU time | 13.13 seconds |
| Started | Oct 14 08:56:20 PM UTC 24 |
| Finished | Oct 14 08:56:54 PM UTC 24 |
| Peak memory | 214628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=973742824 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.973742824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/1.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_random.61669367 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 266829244 ps |
| CPU time | 24.88 seconds |
| Started | Oct 14 08:56:19 PM UTC 24 |
| Finished | Oct 14 08:57:06 PM UTC 24 |
| Peak memory | 214628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=61669367 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random.61669367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/1.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_random_large_delays.2669133808 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 45321280593 ps |
| CPU time | 78.78 seconds |
| Started | Oct 14 08:56:20 PM UTC 24 |
| Finished | Oct 14 08:58:00 PM UTC 24 |
| Peak memory | 214700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2669133808 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.2669133808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/1.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_random_slow_rsp.1817772662 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 11192148230 ps |
| CPU time | 91.17 seconds |
| Started | Oct 14 08:56:20 PM UTC 24 |
| Finished | Oct 14 08:58:13 PM UTC 24 |
| Peak memory | 216936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1817772662 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.1817772662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/1.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_same_source.3812896877 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 2780285341 ps |
| CPU time | 26.87 seconds |
| Started | Oct 14 08:56:20 PM UTC 24 |
| Finished | Oct 14 08:57:08 PM UTC 24 |
| Peak memory | 214888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3812896877 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.3812896877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/1.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_smoke.2375814030 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 233906946 ps |
| CPU time | 2.24 seconds |
| Started | Oct 14 08:56:19 PM UTC 24 |
| Finished | Oct 14 08:56:33 PM UTC 24 |
| Peak memory | 214864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2375814030 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.2375814030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/1.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_smoke_slow_rsp.2835004635 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 6094045142 ps |
| CPU time | 31.43 seconds |
| Started | Oct 14 08:56:19 PM UTC 24 |
| Finished | Oct 14 08:57:02 PM UTC 24 |
| Peak memory | 214656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2835004635 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.2835004635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/1.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_smoke_zero_delays.199842286 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 26026209 ps |
| CPU time | 1.65 seconds |
| Started | Oct 14 08:56:19 PM UTC 24 |
| Finished | Oct 14 08:56:32 PM UTC 24 |
| Peak memory | 214000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=199842286 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/x bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays.199842286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/1.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_stress_all.2382143125 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 260369084 ps |
| CPU time | 34.23 seconds |
| Started | Oct 14 08:56:21 PM UTC 24 |
| Finished | Oct 14 08:57:10 PM UTC 24 |
| Peak memory | 216672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2382143125 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.2382143125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/1.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_stress_all_with_rand_reset.1115770582 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 1222886148 ps |
| CPU time | 305.73 seconds |
| Started | Oct 14 08:56:21 PM UTC 24 |
| Finished | Oct 14 09:02:01 PM UTC 24 |
| Peak memory | 220244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1115770582 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_rand_reset.1115770582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/1.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_stress_all_with_reset_error.4139466647 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 779073729 ps |
| CPU time | 209.29 seconds |
| Started | Oct 14 08:56:23 PM UTC 24 |
| Finished | Oct 14 09:00:23 PM UTC 24 |
| Peak memory | 231332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4139466647 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_reset_error.4139466647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/1.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/1.xbar_unmapped_addr.1390937349 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 1606182911 ps |
| CPU time | 29.21 seconds |
| Started | Oct 14 08:56:20 PM UTC 24 |
| Finished | Oct 14 08:57:11 PM UTC 24 |
| Peak memory | 216668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1390937349 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.1390937349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/1.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_access_same_device_slow_rsp.1315826344 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 33754190614 ps |
| CPU time | 282.02 seconds |
| Started | Oct 14 08:58:26 PM UTC 24 |
| Finished | Oct 14 09:03:12 PM UTC 24 |
| Peak memory | 216740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1315826344 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device_slow_rsp.1315826344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/10.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_error_and_unmapped_addr.3597900807 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 773385011 ps |
| CPU time | 11.97 seconds |
| Started | Oct 14 08:58:33 PM UTC 24 |
| Finished | Oct 14 08:58:46 PM UTC 24 |
| Peak memory | 214888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3597900807 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_addr.3597900807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/10.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_error_random.1008212392 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 1286931709 ps |
| CPU time | 24.09 seconds |
| Started | Oct 14 08:58:29 PM UTC 24 |
| Finished | Oct 14 08:58:54 PM UTC 24 |
| Peak memory | 214820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1008212392 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.1008212392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/10.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_random.3100123880 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 146853069 ps |
| CPU time | 23.27 seconds |
| Started | Oct 14 08:58:23 PM UTC 24 |
| Finished | Oct 14 08:58:48 PM UTC 24 |
| Peak memory | 214628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3100123880 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random.3100123880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/10.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_random_large_delays.3619856316 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 27330285920 ps |
| CPU time | 119 seconds |
| Started | Oct 14 08:58:25 PM UTC 24 |
| Finished | Oct 14 09:00:27 PM UTC 24 |
| Peak memory | 214696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3619856316 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.3619856316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/10.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_random_slow_rsp.3738550414 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 14797247199 ps |
| CPU time | 102.75 seconds |
| Started | Oct 14 08:58:26 PM UTC 24 |
| Finished | Oct 14 09:00:11 PM UTC 24 |
| Peak memory | 216748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3738550414 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.3738550414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/10.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_random_zero_delays.3445009779 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 872266334 ps |
| CPU time | 21.92 seconds |
| Started | Oct 14 08:58:25 PM UTC 24 |
| Finished | Oct 14 08:58:48 PM UTC 24 |
| Peak memory | 214812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3445009779 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_delays.3445009779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/10.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_same_source.3432661043 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 116857238 ps |
| CPU time | 6.43 seconds |
| Started | Oct 14 08:58:27 PM UTC 24 |
| Finished | Oct 14 08:58:35 PM UTC 24 |
| Peak memory | 214884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3432661043 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.3432661043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/10.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_smoke.716678289 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 1032964045 ps |
| CPU time | 5.96 seconds |
| Started | Oct 14 08:58:21 PM UTC 24 |
| Finished | Oct 14 08:58:28 PM UTC 24 |
| Peak memory | 214604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=716678289 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.716678289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/10.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_smoke_large_delays.469735352 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 6166782107 ps |
| CPU time | 28.97 seconds |
| Started | Oct 14 08:58:22 PM UTC 24 |
| Finished | Oct 14 08:58:52 PM UTC 24 |
| Peak memory | 214680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=469735352 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.469735352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/10.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_smoke_slow_rsp.1579481231 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 5215505465 ps |
| CPU time | 22.56 seconds |
| Started | Oct 14 08:58:22 PM UTC 24 |
| Finished | Oct 14 08:58:46 PM UTC 24 |
| Peak memory | 214848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1579481231 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.1579481231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/10.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_smoke_zero_delays.3783656299 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 31069537 ps |
| CPU time | 3.26 seconds |
| Started | Oct 14 08:58:21 PM UTC 24 |
| Finished | Oct 14 08:58:25 PM UTC 24 |
| Peak memory | 214600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3783656299 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delays.3783656299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/10.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_stress_all_with_error.1873617202 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 1307014492 ps |
| CPU time | 149.75 seconds |
| Started | Oct 14 08:58:36 PM UTC 24 |
| Finished | Oct 14 09:01:08 PM UTC 24 |
| Peak memory | 220976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1873617202 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.1873617202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/10.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_stress_all_with_rand_reset.3933932806 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 93343735 ps |
| CPU time | 17.82 seconds |
| Started | Oct 14 08:58:34 PM UTC 24 |
| Finished | Oct 14 08:58:53 PM UTC 24 |
| Peak memory | 216672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3933932806 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_rand_reset.3933932806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/10.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_stress_all_with_reset_error.2321808800 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 5774365495 ps |
| CPU time | 119.58 seconds |
| Started | Oct 14 08:58:36 PM UTC 24 |
| Finished | Oct 14 09:00:38 PM UTC 24 |
| Peak memory | 216752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2321808800 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_reset_error.2321808800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/10.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/10.xbar_unmapped_addr.836285175 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 64418426 ps |
| CPU time | 3.72 seconds |
| Started | Oct 14 08:58:32 PM UTC 24 |
| Finished | Oct 14 08:58:36 PM UTC 24 |
| Peak memory | 214600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=836285175 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.836285175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/10.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_access_same_device.2345261563 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 3198445232 ps |
| CPU time | 55.53 seconds |
| Started | Oct 14 08:58:49 PM UTC 24 |
| Finished | Oct 14 08:59:47 PM UTC 24 |
| Peak memory | 218792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2345261563 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device.2345261563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/11.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_error_and_unmapped_addr.3250744657 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 14312348 ps |
| CPU time | 3.38 seconds |
| Started | Oct 14 08:58:54 PM UTC 24 |
| Finished | Oct 14 08:58:58 PM UTC 24 |
| Peak memory | 214272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3250744657 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_addr.3250744657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/11.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_error_random.3974391918 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 856127484 ps |
| CPU time | 25.34 seconds |
| Started | Oct 14 08:58:49 PM UTC 24 |
| Finished | Oct 14 08:59:16 PM UTC 24 |
| Peak memory | 214628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3974391918 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.3974391918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/11.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_random.3977155692 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 857885054 ps |
| CPU time | 31.14 seconds |
| Started | Oct 14 08:58:47 PM UTC 24 |
| Finished | Oct 14 08:59:19 PM UTC 24 |
| Peak memory | 214628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3977155692 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random.3977155692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/11.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_random_large_delays.2656054965 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 9693258884 ps |
| CPU time | 64.7 seconds |
| Started | Oct 14 08:58:48 PM UTC 24 |
| Finished | Oct 14 08:59:54 PM UTC 24 |
| Peak memory | 214696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2656054965 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.2656054965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/11.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_random_slow_rsp.703169164 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 26819164488 ps |
| CPU time | 99.75 seconds |
| Started | Oct 14 08:58:49 PM UTC 24 |
| Finished | Oct 14 09:00:31 PM UTC 24 |
| Peak memory | 214700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=703169164 -assert nopostproc +UVM_TEST NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.703169164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/11.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_random_zero_delays.3534668932 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 19161070 ps |
| CPU time | 3.37 seconds |
| Started | Oct 14 08:58:47 PM UTC 24 |
| Finished | Oct 14 08:58:51 PM UTC 24 |
| Peak memory | 214620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3534668932 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_delays.3534668932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/11.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_same_source.2085280196 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 209005711 ps |
| CPU time | 13.84 seconds |
| Started | Oct 14 08:58:49 PM UTC 24 |
| Finished | Oct 14 08:59:05 PM UTC 24 |
| Peak memory | 214628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2085280196 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.2085280196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/11.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_smoke.3163606130 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 168772467 ps |
| CPU time | 5.61 seconds |
| Started | Oct 14 08:58:37 PM UTC 24 |
| Finished | Oct 14 08:58:44 PM UTC 24 |
| Peak memory | 214780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3163606130 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.3163606130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/11.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_smoke_large_delays.884801161 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 25354694209 ps |
| CPU time | 48.42 seconds |
| Started | Oct 14 08:58:44 PM UTC 24 |
| Finished | Oct 14 08:59:35 PM UTC 24 |
| Peak memory | 214684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=884801161 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.884801161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/11.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_smoke_slow_rsp.2695433063 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 4129412252 ps |
| CPU time | 33.32 seconds |
| Started | Oct 14 08:58:45 PM UTC 24 |
| Finished | Oct 14 08:59:20 PM UTC 24 |
| Peak memory | 214652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2695433063 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.2695433063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/11.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_smoke_zero_delays.1307158064 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 24454286 ps |
| CPU time | 3.03 seconds |
| Started | Oct 14 08:58:43 PM UTC 24 |
| Finished | Oct 14 08:58:48 PM UTC 24 |
| Peak memory | 214600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1307158064 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delays.1307158064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/11.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_stress_all.955341226 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 2451320687 ps |
| CPU time | 70.78 seconds |
| Started | Oct 14 08:58:54 PM UTC 24 |
| Finished | Oct 14 09:00:06 PM UTC 24 |
| Peak memory | 218456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=955341226 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.955341226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/11.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_stress_all_with_error.239982687 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 7116986968 ps |
| CPU time | 104.47 seconds |
| Started | Oct 14 08:58:55 PM UTC 24 |
| Finished | Oct 14 09:00:42 PM UTC 24 |
| Peak memory | 216744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=239982687 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.239982687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/11.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_stress_all_with_rand_reset.3948454790 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 2745691314 ps |
| CPU time | 149.03 seconds |
| Started | Oct 14 08:58:55 PM UTC 24 |
| Finished | Oct 14 09:01:27 PM UTC 24 |
| Peak memory | 218792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3948454790 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_rand_reset.3948454790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/11.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_stress_all_with_reset_error.3062220601 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 7713637 ps |
| CPU time | 31.95 seconds |
| Started | Oct 14 08:58:57 PM UTC 24 |
| Finished | Oct 14 08:59:30 PM UTC 24 |
| Peak memory | 214620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3062220601 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_reset_error.3062220601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/11.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/11.xbar_unmapped_addr.1180901987 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 3643470917 ps |
| CPU time | 35.35 seconds |
| Started | Oct 14 08:58:51 PM UTC 24 |
| Finished | Oct 14 08:59:29 PM UTC 24 |
| Peak memory | 216736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1180901987 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.1180901987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/11.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_access_same_device_slow_rsp.1342331991 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 7389454380 ps |
| CPU time | 55.66 seconds |
| Started | Oct 14 08:59:17 PM UTC 24 |
| Finished | Oct 14 09:00:14 PM UTC 24 |
| Peak memory | 214692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1342331991 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device_slow_rsp.1342331991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/12.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_error_and_unmapped_addr.3005051080 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 320811077 ps |
| CPU time | 2.95 seconds |
| Started | Oct 14 08:59:22 PM UTC 24 |
| Finished | Oct 14 08:59:26 PM UTC 24 |
| Peak memory | 214624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3005051080 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_addr.3005051080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/12.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_error_random.1733319153 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 242335251 ps |
| CPU time | 6.75 seconds |
| Started | Oct 14 08:59:21 PM UTC 24 |
| Finished | Oct 14 08:59:29 PM UTC 24 |
| Peak memory | 214600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1733319153 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.1733319153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/12.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_random.3462107924 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 307758383 ps |
| CPU time | 15.22 seconds |
| Started | Oct 14 08:59:05 PM UTC 24 |
| Finished | Oct 14 08:59:21 PM UTC 24 |
| Peak memory | 214628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3462107924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random.3462107924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/12.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_random_large_delays.3794461405 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 2491866801 ps |
| CPU time | 18.43 seconds |
| Started | Oct 14 08:59:07 PM UTC 24 |
| Finished | Oct 14 08:59:27 PM UTC 24 |
| Peak memory | 214692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3794461405 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.3794461405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/12.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_random_slow_rsp.2251105449 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 36240743255 ps |
| CPU time | 84.86 seconds |
| Started | Oct 14 08:59:07 PM UTC 24 |
| Finished | Oct 14 09:00:34 PM UTC 24 |
| Peak memory | 214692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2251105449 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.2251105449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/12.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_random_zero_delays.34339395 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 113233624 ps |
| CPU time | 19 seconds |
| Started | Oct 14 08:59:07 PM UTC 24 |
| Finished | Oct 14 08:59:27 PM UTC 24 |
| Peak memory | 214628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=34339395 -assert nopostproc +UVM_TESTNAME=xbar_ base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/x bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_delays.34339395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/12.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_same_source.184683254 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 9172083187 ps |
| CPU time | 35.84 seconds |
| Started | Oct 14 08:59:21 PM UTC 24 |
| Finished | Oct 14 08:59:59 PM UTC 24 |
| Peak memory | 214952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=184683254 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.184683254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/12.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_smoke.4129191402 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 30319297 ps |
| CPU time | 2.72 seconds |
| Started | Oct 14 08:58:58 PM UTC 24 |
| Finished | Oct 14 08:59:02 PM UTC 24 |
| Peak memory | 214588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4129191402 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.4129191402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/12.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_smoke_large_delays.3744384591 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 5313640811 ps |
| CPU time | 36.42 seconds |
| Started | Oct 14 08:59:01 PM UTC 24 |
| Finished | Oct 14 08:59:39 PM UTC 24 |
| Peak memory | 214676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3744384591 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.3744384591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/12.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_smoke_slow_rsp.3535732081 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 11562862921 ps |
| CPU time | 41.93 seconds |
| Started | Oct 14 08:59:03 PM UTC 24 |
| Finished | Oct 14 08:59:46 PM UTC 24 |
| Peak memory | 214652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3535732081 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.3535732081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/12.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_smoke_zero_delays.2319632530 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 36810350 ps |
| CPU time | 3.19 seconds |
| Started | Oct 14 08:58:59 PM UTC 24 |
| Finished | Oct 14 08:59:03 PM UTC 24 |
| Peak memory | 214600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2319632530 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delays.2319632530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/12.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_stress_all.849400963 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 6810512688 ps |
| CPU time | 159.05 seconds |
| Started | Oct 14 08:59:24 PM UTC 24 |
| Finished | Oct 14 09:02:05 PM UTC 24 |
| Peak memory | 221032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=849400963 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.849400963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/12.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_stress_all_with_error.2837116430 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 198314894 ps |
| CPU time | 10.93 seconds |
| Started | Oct 14 08:59:27 PM UTC 24 |
| Finished | Oct 14 08:59:39 PM UTC 24 |
| Peak memory | 214636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2837116430 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.2837116430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/12.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_stress_all_with_rand_reset.2033101306 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 594871234 ps |
| CPU time | 218.3 seconds |
| Started | Oct 14 08:59:26 PM UTC 24 |
| Finished | Oct 14 09:03:08 PM UTC 24 |
| Peak memory | 218728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2033101306 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_rand_reset.2033101306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/12.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_stress_all_with_reset_error.3387985294 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 3504351994 ps |
| CPU time | 420.4 seconds |
| Started | Oct 14 08:59:27 PM UTC 24 |
| Finished | Oct 14 09:06:33 PM UTC 24 |
| Peak memory | 232916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3387985294 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_reset_error.3387985294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/12.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/12.xbar_unmapped_addr.3455621634 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 1324377359 ps |
| CPU time | 19.97 seconds |
| Started | Oct 14 08:59:22 PM UTC 24 |
| Finished | Oct 14 08:59:43 PM UTC 24 |
| Peak memory | 216676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3455621634 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.3455621634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/12.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_access_same_device.4274133357 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 1991321721 ps |
| CPU time | 76.29 seconds |
| Started | Oct 14 08:59:36 PM UTC 24 |
| Finished | Oct 14 09:00:54 PM UTC 24 |
| Peak memory | 214632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4274133357 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device.4274133357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/13.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_error_and_unmapped_addr.2160556231 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 1517912469 ps |
| CPU time | 16.01 seconds |
| Started | Oct 14 08:59:40 PM UTC 24 |
| Finished | Oct 14 08:59:58 PM UTC 24 |
| Peak memory | 214628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2160556231 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_addr.2160556231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/13.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_error_random.2064623077 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 2171168311 ps |
| CPU time | 12.76 seconds |
| Started | Oct 14 08:59:40 PM UTC 24 |
| Finished | Oct 14 08:59:54 PM UTC 24 |
| Peak memory | 214924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2064623077 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.2064623077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/13.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_random.1714180645 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 189309274 ps |
| CPU time | 25.39 seconds |
| Started | Oct 14 08:59:32 PM UTC 24 |
| Finished | Oct 14 08:59:58 PM UTC 24 |
| Peak memory | 214632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1714180645 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random.1714180645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/13.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_random_large_delays.30381534 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 11252313856 ps |
| CPU time | 30.25 seconds |
| Started | Oct 14 08:59:34 PM UTC 24 |
| Finished | Oct 14 09:00:05 PM UTC 24 |
| Peak memory | 214696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30381534 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.30381534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/13.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_random_slow_rsp.506116424 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 9934829299 ps |
| CPU time | 103.75 seconds |
| Started | Oct 14 08:59:36 PM UTC 24 |
| Finished | Oct 14 09:01:22 PM UTC 24 |
| Peak memory | 214680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=506116424 -assert nopostproc +UVM_TEST NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.506116424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/13.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_random_zero_delays.3730131978 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 54496946 ps |
| CPU time | 5.35 seconds |
| Started | Oct 14 08:59:32 PM UTC 24 |
| Finished | Oct 14 08:59:38 PM UTC 24 |
| Peak memory | 214620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3730131978 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_delays.3730131978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/13.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_same_source.1404740103 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 28231231 ps |
| CPU time | 3.52 seconds |
| Started | Oct 14 08:59:36 PM UTC 24 |
| Finished | Oct 14 08:59:41 PM UTC 24 |
| Peak memory | 214792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1404740103 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.1404740103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/13.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_smoke.759343156 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 214791595 ps |
| CPU time | 3.39 seconds |
| Started | Oct 14 08:59:29 PM UTC 24 |
| Finished | Oct 14 08:59:34 PM UTC 24 |
| Peak memory | 214868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=759343156 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.759343156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/13.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_smoke_large_delays.736715764 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 36525994453 ps |
| CPU time | 64.06 seconds |
| Started | Oct 14 08:59:29 PM UTC 24 |
| Finished | Oct 14 09:00:35 PM UTC 24 |
| Peak memory | 214680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=736715764 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.736715764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/13.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_smoke_slow_rsp.1178640181 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 21940236103 ps |
| CPU time | 40.18 seconds |
| Started | Oct 14 08:59:32 PM UTC 24 |
| Finished | Oct 14 09:00:13 PM UTC 24 |
| Peak memory | 214652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1178640181 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.1178640181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/13.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_smoke_zero_delays.777778044 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 29915433 ps |
| CPU time | 3.77 seconds |
| Started | Oct 14 08:59:29 PM UTC 24 |
| Finished | Oct 14 08:59:34 PM UTC 24 |
| Peak memory | 214612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=777778044 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/x bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delays.777778044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/13.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_stress_all.1827920771 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 10558455621 ps |
| CPU time | 104.12 seconds |
| Started | Oct 14 08:59:43 PM UTC 24 |
| Finished | Oct 14 09:01:29 PM UTC 24 |
| Peak memory | 218788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1827920771 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.1827920771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/13.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_stress_all_with_error.2912984018 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 3908572101 ps |
| CPU time | 99.37 seconds |
| Started | Oct 14 08:59:44 PM UTC 24 |
| Finished | Oct 14 09:01:25 PM UTC 24 |
| Peak memory | 218992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2912984018 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.2912984018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/13.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_stress_all_with_rand_reset.1313156929 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 2582043249 ps |
| CPU time | 178.36 seconds |
| Started | Oct 14 08:59:43 PM UTC 24 |
| Finished | Oct 14 09:02:44 PM UTC 24 |
| Peak memory | 220836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1313156929 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_rand_reset.1313156929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/13.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_stress_all_with_reset_error.836471093 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 4269844923 ps |
| CPU time | 73.65 seconds |
| Started | Oct 14 08:59:44 PM UTC 24 |
| Finished | Oct 14 09:00:59 PM UTC 24 |
| Peak memory | 218792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=836471093 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_reset_error.836471093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/13.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/13.xbar_unmapped_addr.1663715961 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 48436552 ps |
| CPU time | 9.7 seconds |
| Started | Oct 14 08:59:40 PM UTC 24 |
| Finished | Oct 14 08:59:51 PM UTC 24 |
| Peak memory | 216672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1663715961 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.1663715961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/13.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_access_same_device.369063372 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 938455542 ps |
| CPU time | 36.46 seconds |
| Started | Oct 14 08:59:55 PM UTC 24 |
| Finished | Oct 14 09:00:33 PM UTC 24 |
| Peak memory | 214632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=369063372 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xba r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device.369063372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/14.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_access_same_device_slow_rsp.1562607649 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 10106168437 ps |
| CPU time | 82.46 seconds |
| Started | Oct 14 08:59:56 PM UTC 24 |
| Finished | Oct 14 09:01:20 PM UTC 24 |
| Peak memory | 214692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1562607649 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device_slow_rsp.1562607649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/14.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_error_and_unmapped_addr.3884050913 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 448835310 ps |
| CPU time | 8.76 seconds |
| Started | Oct 14 08:59:59 PM UTC 24 |
| Finished | Oct 14 09:00:09 PM UTC 24 |
| Peak memory | 214628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3884050913 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_addr.3884050913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/14.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_error_random.2260012082 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 387926403 ps |
| CPU time | 9.95 seconds |
| Started | Oct 14 08:59:58 PM UTC 24 |
| Finished | Oct 14 09:00:09 PM UTC 24 |
| Peak memory | 214860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2260012082 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.2260012082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/14.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_random_large_delays.3599288158 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 42717661701 ps |
| CPU time | 124.1 seconds |
| Started | Oct 14 08:59:53 PM UTC 24 |
| Finished | Oct 14 09:01:59 PM UTC 24 |
| Peak memory | 214700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3599288158 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.3599288158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/14.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_random_slow_rsp.3907102622 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 39453539052 ps |
| CPU time | 130.42 seconds |
| Started | Oct 14 08:59:53 PM UTC 24 |
| Finished | Oct 14 09:02:05 PM UTC 24 |
| Peak memory | 214696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3907102622 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.3907102622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/14.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_random_zero_delays.4287540373 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 441281976 ps |
| CPU time | 24.35 seconds |
| Started | Oct 14 08:59:51 PM UTC 24 |
| Finished | Oct 14 09:00:17 PM UTC 24 |
| Peak memory | 216664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4287540373 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_delays.4287540373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/14.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_same_source.232158223 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 1173454776 ps |
| CPU time | 24.33 seconds |
| Started | Oct 14 08:59:57 PM UTC 24 |
| Finished | Oct 14 09:00:23 PM UTC 24 |
| Peak memory | 214888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=232158223 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.232158223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/14.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_smoke.3541146304 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 241868314 ps |
| CPU time | 4.25 seconds |
| Started | Oct 14 08:59:44 PM UTC 24 |
| Finished | Oct 14 08:59:49 PM UTC 24 |
| Peak memory | 214584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3541146304 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.3541146304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/14.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_smoke_large_delays.3021775135 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 6107891294 ps |
| CPU time | 33.92 seconds |
| Started | Oct 14 08:59:47 PM UTC 24 |
| Finished | Oct 14 09:00:22 PM UTC 24 |
| Peak memory | 214680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3021775135 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.3021775135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/14.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_smoke_slow_rsp.2180341500 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 8914612016 ps |
| CPU time | 47.85 seconds |
| Started | Oct 14 08:59:48 PM UTC 24 |
| Finished | Oct 14 09:00:38 PM UTC 24 |
| Peak memory | 214656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2180341500 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.2180341500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/14.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_smoke_zero_delays.939600207 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 44514839 ps |
| CPU time | 3.37 seconds |
| Started | Oct 14 08:59:47 PM UTC 24 |
| Finished | Oct 14 08:59:51 PM UTC 24 |
| Peak memory | 214612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=939600207 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/x bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delays.939600207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/14.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_stress_all.721990899 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 19063525613 ps |
| CPU time | 193.42 seconds |
| Started | Oct 14 09:00:01 PM UTC 24 |
| Finished | Oct 14 09:03:22 PM UTC 24 |
| Peak memory | 218984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=721990899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.721990899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/14.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_stress_all_with_error.3236085093 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 5179044758 ps |
| CPU time | 74.55 seconds |
| Started | Oct 14 09:00:08 PM UTC 24 |
| Finished | Oct 14 09:01:25 PM UTC 24 |
| Peak memory | 218796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3236085093 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.3236085093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/14.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_stress_all_with_reset_error.1489444627 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 8199119128 ps |
| CPU time | 406.34 seconds |
| Started | Oct 14 09:00:08 PM UTC 24 |
| Finished | Oct 14 09:07:00 PM UTC 24 |
| Peak memory | 235752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1489444627 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_reset_error.1489444627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/14.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/14.xbar_unmapped_addr.1308500276 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 822958675 ps |
| CPU time | 37.33 seconds |
| Started | Oct 14 08:59:59 PM UTC 24 |
| Finished | Oct 14 09:00:38 PM UTC 24 |
| Peak memory | 216672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1308500276 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.1308500276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/14.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_access_same_device.2423622649 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 1699221414 ps |
| CPU time | 38.82 seconds |
| Started | Oct 14 09:00:18 PM UTC 24 |
| Finished | Oct 14 09:00:58 PM UTC 24 |
| Peak memory | 216684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2423622649 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device.2423622649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/15.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_access_same_device_slow_rsp.1420047594 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 3143737797 ps |
| CPU time | 37.79 seconds |
| Started | Oct 14 09:00:20 PM UTC 24 |
| Finished | Oct 14 09:01:00 PM UTC 24 |
| Peak memory | 214692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1420047594 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device_slow_rsp.1420047594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/15.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_error_and_unmapped_addr.3232990511 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 1146745175 ps |
| CPU time | 24.75 seconds |
| Started | Oct 14 09:00:25 PM UTC 24 |
| Finished | Oct 14 09:00:51 PM UTC 24 |
| Peak memory | 214632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3232990511 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_addr.3232990511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/15.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_error_random.2827604217 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 2173327882 ps |
| CPU time | 19.99 seconds |
| Started | Oct 14 09:00:24 PM UTC 24 |
| Finished | Oct 14 09:00:45 PM UTC 24 |
| Peak memory | 214372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2827604217 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.2827604217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/15.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_random.2075157458 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 407121730 ps |
| CPU time | 9.75 seconds |
| Started | Oct 14 09:00:14 PM UTC 24 |
| Finished | Oct 14 09:00:26 PM UTC 24 |
| Peak memory | 214628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2075157458 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random.2075157458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/15.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_random_large_delays.137644187 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 153052304628 ps |
| CPU time | 226.49 seconds |
| Started | Oct 14 09:00:16 PM UTC 24 |
| Finished | Oct 14 09:04:06 PM UTC 24 |
| Peak memory | 214692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=137644187 -assert nopostproc +UVM_ TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.137644187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/15.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_random_slow_rsp.1982934226 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 20943791241 ps |
| CPU time | 89.8 seconds |
| Started | Oct 14 09:00:16 PM UTC 24 |
| Finished | Oct 14 09:01:48 PM UTC 24 |
| Peak memory | 214696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1982934226 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.1982934226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/15.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_random_zero_delays.1043441079 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 84475548 ps |
| CPU time | 8.4 seconds |
| Started | Oct 14 09:00:16 PM UTC 24 |
| Finished | Oct 14 09:00:25 PM UTC 24 |
| Peak memory | 214588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1043441079 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_delays.1043441079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/15.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_same_source.3253478639 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 457267605 ps |
| CPU time | 16.91 seconds |
| Started | Oct 14 09:00:24 PM UTC 24 |
| Finished | Oct 14 09:00:42 PM UTC 24 |
| Peak memory | 214284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3253478639 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.3253478639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/15.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_smoke.1740759449 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 131507337 ps |
| CPU time | 5.3 seconds |
| Started | Oct 14 09:00:08 PM UTC 24 |
| Finished | Oct 14 09:00:15 PM UTC 24 |
| Peak memory | 214584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1740759449 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.1740759449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/15.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_smoke_large_delays.1462810777 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 8255967159 ps |
| CPU time | 58.17 seconds |
| Started | Oct 14 09:00:10 PM UTC 24 |
| Finished | Oct 14 09:01:10 PM UTC 24 |
| Peak memory | 214744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1462810777 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.1462810777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/15.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_smoke_slow_rsp.2561942559 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 9262985717 ps |
| CPU time | 43.98 seconds |
| Started | Oct 14 09:00:12 PM UTC 24 |
| Finished | Oct 14 09:00:59 PM UTC 24 |
| Peak memory | 214652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2561942559 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.2561942559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/15.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_smoke_zero_delays.558749132 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 35674556 ps |
| CPU time | 3.27 seconds |
| Started | Oct 14 09:00:10 PM UTC 24 |
| Finished | Oct 14 09:00:14 PM UTC 24 |
| Peak memory | 214608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=558749132 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/x bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delays.558749132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/15.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_stress_all.3905019605 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 5349235178 ps |
| CPU time | 189.35 seconds |
| Started | Oct 14 09:00:26 PM UTC 24 |
| Finished | Oct 14 09:03:39 PM UTC 24 |
| Peak memory | 220840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3905019605 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.3905019605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/15.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_stress_all_with_error.2058567161 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 6708516563 ps |
| CPU time | 133.79 seconds |
| Started | Oct 14 09:00:27 PM UTC 24 |
| Finished | Oct 14 09:02:44 PM UTC 24 |
| Peak memory | 216748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2058567161 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.2058567161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/15.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_stress_all_with_rand_reset.1535081573 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 1891057538 ps |
| CPU time | 299.67 seconds |
| Started | Oct 14 09:00:26 PM UTC 24 |
| Finished | Oct 14 09:05:30 PM UTC 24 |
| Peak memory | 220880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1535081573 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_rand_reset.1535081573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/15.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_stress_all_with_reset_error.3255967503 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 5237446542 ps |
| CPU time | 85.35 seconds |
| Started | Oct 14 09:00:32 PM UTC 24 |
| Finished | Oct 14 09:02:00 PM UTC 24 |
| Peak memory | 218796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3255967503 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_reset_error.3255967503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/15.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/15.xbar_unmapped_addr.2700450662 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 61335195 ps |
| CPU time | 6.81 seconds |
| Started | Oct 14 09:00:24 PM UTC 24 |
| Finished | Oct 14 09:00:32 PM UTC 24 |
| Peak memory | 214624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2700450662 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.2700450662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/15.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_access_same_device.2195700328 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 2463818769 ps |
| CPU time | 69.77 seconds |
| Started | Oct 14 09:00:39 PM UTC 24 |
| Finished | Oct 14 09:01:51 PM UTC 24 |
| Peak memory | 216744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2195700328 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device.2195700328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/16.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_access_same_device_slow_rsp.1800051673 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 25865771173 ps |
| CPU time | 200.44 seconds |
| Started | Oct 14 09:00:42 PM UTC 24 |
| Finished | Oct 14 09:04:06 PM UTC 24 |
| Peak memory | 216744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1800051673 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device_slow_rsp.1800051673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/16.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_error_and_unmapped_addr.1826366344 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 77716463 ps |
| CPU time | 10.69 seconds |
| Started | Oct 14 09:00:50 PM UTC 24 |
| Finished | Oct 14 09:01:02 PM UTC 24 |
| Peak memory | 214824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1826366344 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_addr.1826366344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/16.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_error_random.528199116 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 108835307 ps |
| CPU time | 13.21 seconds |
| Started | Oct 14 09:00:46 PM UTC 24 |
| Finished | Oct 14 09:01:00 PM UTC 24 |
| Peak memory | 214816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=528199116 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.528199116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/16.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_random.3466998179 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 883552303 ps |
| CPU time | 30.51 seconds |
| Started | Oct 14 09:00:38 PM UTC 24 |
| Finished | Oct 14 09:01:10 PM UTC 24 |
| Peak memory | 214628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3466998179 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random.3466998179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/16.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_random_large_delays.3738678866 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 4419586298 ps |
| CPU time | 35.08 seconds |
| Started | Oct 14 09:00:39 PM UTC 24 |
| Finished | Oct 14 09:01:16 PM UTC 24 |
| Peak memory | 214692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3738678866 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.3738678866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/16.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_random_slow_rsp.1067993267 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 5623389138 ps |
| CPU time | 35.22 seconds |
| Started | Oct 14 09:00:39 PM UTC 24 |
| Finished | Oct 14 09:01:16 PM UTC 24 |
| Peak memory | 214692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1067993267 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.1067993267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/16.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_random_zero_delays.1996065853 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 179320086 ps |
| CPU time | 19.58 seconds |
| Started | Oct 14 09:00:39 PM UTC 24 |
| Finished | Oct 14 09:01:00 PM UTC 24 |
| Peak memory | 214628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1996065853 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_delays.1996065853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/16.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_same_source.4223213223 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 2130850332 ps |
| CPU time | 8.52 seconds |
| Started | Oct 14 09:00:44 PM UTC 24 |
| Finished | Oct 14 09:00:53 PM UTC 24 |
| Peak memory | 214624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4223213223 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.4223213223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/16.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_smoke.3497164727 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 200622872 ps |
| CPU time | 3.12 seconds |
| Started | Oct 14 09:00:32 PM UTC 24 |
| Finished | Oct 14 09:00:37 PM UTC 24 |
| Peak memory | 214584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3497164727 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.3497164727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/16.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_smoke_large_delays.3885831784 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 8174333143 ps |
| CPU time | 43.93 seconds |
| Started | Oct 14 09:00:35 PM UTC 24 |
| Finished | Oct 14 09:01:20 PM UTC 24 |
| Peak memory | 214868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3885831784 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.3885831784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/16.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_smoke_slow_rsp.2741436914 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 3400642758 ps |
| CPU time | 25.28 seconds |
| Started | Oct 14 09:00:36 PM UTC 24 |
| Finished | Oct 14 09:01:02 PM UTC 24 |
| Peak memory | 214912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2741436914 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.2741436914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/16.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_smoke_zero_delays.3506483534 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 34673884 ps |
| CPU time | 3.06 seconds |
| Started | Oct 14 09:00:34 PM UTC 24 |
| Finished | Oct 14 09:00:38 PM UTC 24 |
| Peak memory | 214600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3506483534 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delays.3506483534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/16.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_stress_all.3772078059 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 790792891 ps |
| CPU time | 81.57 seconds |
| Started | Oct 14 09:00:50 PM UTC 24 |
| Finished | Oct 14 09:02:14 PM UTC 24 |
| Peak memory | 216676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3772078059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.3772078059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/16.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_stress_all_with_error.1180993624 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 1050393007 ps |
| CPU time | 40.59 seconds |
| Started | Oct 14 09:00:54 PM UTC 24 |
| Finished | Oct 14 09:01:36 PM UTC 24 |
| Peak memory | 214636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1180993624 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.1180993624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/16.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_stress_all_with_rand_reset.371281887 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 631189085 ps |
| CPU time | 217.46 seconds |
| Started | Oct 14 09:00:51 PM UTC 24 |
| Finished | Oct 14 09:04:32 PM UTC 24 |
| Peak memory | 218720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=371281887 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_rand_reset.371281887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/16.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_stress_all_with_reset_error.4115125444 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 1283872963 ps |
| CPU time | 155.88 seconds |
| Started | Oct 14 09:00:54 PM UTC 24 |
| Finished | Oct 14 09:03:33 PM UTC 24 |
| Peak memory | 220784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4115125444 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_reset_error.4115125444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/16.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/16.xbar_unmapped_addr.2043231895 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 161331170 ps |
| CPU time | 13.93 seconds |
| Started | Oct 14 09:00:48 PM UTC 24 |
| Finished | Oct 14 09:01:03 PM UTC 24 |
| Peak memory | 214624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2043231895 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.2043231895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/16.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_access_same_device.3973882334 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 211804652 ps |
| CPU time | 13.72 seconds |
| Started | Oct 14 09:01:01 PM UTC 24 |
| Finished | Oct 14 09:01:16 PM UTC 24 |
| Peak memory | 214632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3973882334 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device.3973882334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/17.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_access_same_device_slow_rsp.1082077719 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 10285413560 ps |
| CPU time | 81.91 seconds |
| Started | Oct 14 09:01:01 PM UTC 24 |
| Finished | Oct 14 09:02:25 PM UTC 24 |
| Peak memory | 216740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1082077719 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device_slow_rsp.1082077719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/17.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_error_and_unmapped_addr.3261645939 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 116164473 ps |
| CPU time | 14.1 seconds |
| Started | Oct 14 09:01:04 PM UTC 24 |
| Finished | Oct 14 09:01:20 PM UTC 24 |
| Peak memory | 214824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3261645939 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_addr.3261645939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/17.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_error_random.4099860468 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 1298100659 ps |
| CPU time | 16.97 seconds |
| Started | Oct 14 09:01:03 PM UTC 24 |
| Finished | Oct 14 09:01:21 PM UTC 24 |
| Peak memory | 214636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4099860468 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.4099860468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/17.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_random.1929729078 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 136362945 ps |
| CPU time | 22.79 seconds |
| Started | Oct 14 09:00:59 PM UTC 24 |
| Finished | Oct 14 09:01:24 PM UTC 24 |
| Peak memory | 214624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1929729078 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random.1929729078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/17.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_random_large_delays.3166824793 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 12596116100 ps |
| CPU time | 68.38 seconds |
| Started | Oct 14 09:01:01 PM UTC 24 |
| Finished | Oct 14 09:02:11 PM UTC 24 |
| Peak memory | 214692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3166824793 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.3166824793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/17.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_random_slow_rsp.768836329 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 98652671407 ps |
| CPU time | 210.79 seconds |
| Started | Oct 14 09:01:01 PM UTC 24 |
| Finished | Oct 14 09:04:35 PM UTC 24 |
| Peak memory | 214696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=768836329 -assert nopostproc +UVM_TEST NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.768836329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/17.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_random_zero_delays.404703067 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 125844550 ps |
| CPU time | 16.82 seconds |
| Started | Oct 14 09:00:59 PM UTC 24 |
| Finished | Oct 14 09:01:18 PM UTC 24 |
| Peak memory | 214620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=404703067 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_delays.404703067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/17.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_same_source.2556469073 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 163113047 ps |
| CPU time | 8.71 seconds |
| Started | Oct 14 09:01:01 PM UTC 24 |
| Finished | Oct 14 09:01:11 PM UTC 24 |
| Peak memory | 214624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2556469073 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.2556469073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/17.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_smoke.2917050624 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 136642242 ps |
| CPU time | 5.26 seconds |
| Started | Oct 14 09:00:54 PM UTC 24 |
| Finished | Oct 14 09:01:00 PM UTC 24 |
| Peak memory | 214588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2917050624 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.2917050624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/17.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_smoke_large_delays.2692001316 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 7230347687 ps |
| CPU time | 50.93 seconds |
| Started | Oct 14 09:00:58 PM UTC 24 |
| Finished | Oct 14 09:01:51 PM UTC 24 |
| Peak memory | 214680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2692001316 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.2692001316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/17.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_smoke_slow_rsp.4153525666 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 3039491100 ps |
| CPU time | 22.86 seconds |
| Started | Oct 14 09:00:59 PM UTC 24 |
| Finished | Oct 14 09:01:24 PM UTC 24 |
| Peak memory | 214652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4153525666 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.4153525666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/17.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_smoke_zero_delays.3116527765 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 23860318 ps |
| CPU time | 2.88 seconds |
| Started | Oct 14 09:00:55 PM UTC 24 |
| Finished | Oct 14 09:00:59 PM UTC 24 |
| Peak memory | 214792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3116527765 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delays.3116527765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/17.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_stress_all.273344640 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 20712934887 ps |
| CPU time | 200.96 seconds |
| Started | Oct 14 09:01:09 PM UTC 24 |
| Finished | Oct 14 09:04:33 PM UTC 24 |
| Peak memory | 220836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=273344640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.273344640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/17.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_stress_all_with_error.1135495197 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 2266609096 ps |
| CPU time | 42.69 seconds |
| Started | Oct 14 09:01:11 PM UTC 24 |
| Finished | Oct 14 09:01:55 PM UTC 24 |
| Peak memory | 214700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1135495197 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.1135495197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/17.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_stress_all_with_reset_error.234809506 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 9040258676 ps |
| CPU time | 343.65 seconds |
| Started | Oct 14 09:01:12 PM UTC 24 |
| Finished | Oct 14 09:07:00 PM UTC 24 |
| Peak memory | 231464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=234809506 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_reset_error.234809506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/17.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/17.xbar_unmapped_addr.2450078167 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 185169568 ps |
| CPU time | 24.96 seconds |
| Started | Oct 14 09:01:03 PM UTC 24 |
| Finished | Oct 14 09:01:29 PM UTC 24 |
| Peak memory | 216672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2450078167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.2450078167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/17.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_access_same_device.2288618975 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 1987219944 ps |
| CPU time | 63.03 seconds |
| Started | Oct 14 09:01:22 PM UTC 24 |
| Finished | Oct 14 09:02:26 PM UTC 24 |
| Peak memory | 216680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2288618975 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device.2288618975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/18.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_access_same_device_slow_rsp.1490177226 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 33471297109 ps |
| CPU time | 318.43 seconds |
| Started | Oct 14 09:01:22 PM UTC 24 |
| Finished | Oct 14 09:06:44 PM UTC 24 |
| Peak memory | 216740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1490177226 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device_slow_rsp.1490177226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/18.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_error_and_unmapped_addr.2871481893 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 1129962159 ps |
| CPU time | 22.97 seconds |
| Started | Oct 14 09:01:24 PM UTC 24 |
| Finished | Oct 14 09:01:48 PM UTC 24 |
| Peak memory | 214628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2871481893 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_addr.2871481893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/18.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_error_random.595622998 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 1753346429 ps |
| CPU time | 35.18 seconds |
| Started | Oct 14 09:01:22 PM UTC 24 |
| Finished | Oct 14 09:01:58 PM UTC 24 |
| Peak memory | 214596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=595622998 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.595622998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/18.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_random.3724984991 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 164105418 ps |
| CPU time | 5.66 seconds |
| Started | Oct 14 09:01:18 PM UTC 24 |
| Finished | Oct 14 09:01:25 PM UTC 24 |
| Peak memory | 214624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3724984991 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random.3724984991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/18.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_random_large_delays.175927867 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 26615302501 ps |
| CPU time | 72.34 seconds |
| Started | Oct 14 09:01:20 PM UTC 24 |
| Finished | Oct 14 09:02:35 PM UTC 24 |
| Peak memory | 214688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=175927867 -assert nopostproc +UVM_ TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.175927867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/18.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_random_slow_rsp.1330182929 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 23635470584 ps |
| CPU time | 88.74 seconds |
| Started | Oct 14 09:01:21 PM UTC 24 |
| Finished | Oct 14 09:02:51 PM UTC 24 |
| Peak memory | 214892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1330182929 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.1330182929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/18.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_random_zero_delays.3619148531 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 62917983 ps |
| CPU time | 7.03 seconds |
| Started | Oct 14 09:01:19 PM UTC 24 |
| Finished | Oct 14 09:01:27 PM UTC 24 |
| Peak memory | 214616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3619148531 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_delays.3619148531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/18.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_same_source.3532621125 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 1036916511 ps |
| CPU time | 18.49 seconds |
| Started | Oct 14 09:01:22 PM UTC 24 |
| Finished | Oct 14 09:01:42 PM UTC 24 |
| Peak memory | 214624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3532621125 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.3532621125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/18.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_smoke.375935576 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 50534347 ps |
| CPU time | 2.92 seconds |
| Started | Oct 14 09:01:17 PM UTC 24 |
| Finished | Oct 14 09:01:21 PM UTC 24 |
| Peak memory | 214608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=375935576 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.375935576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/18.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_smoke_large_delays.3791647870 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 7043664761 ps |
| CPU time | 72.61 seconds |
| Started | Oct 14 09:01:17 PM UTC 24 |
| Finished | Oct 14 09:02:31 PM UTC 24 |
| Peak memory | 214680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3791647870 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.3791647870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/18.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_smoke_slow_rsp.4001515550 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 3616359440 ps |
| CPU time | 26.21 seconds |
| Started | Oct 14 09:01:17 PM UTC 24 |
| Finished | Oct 14 09:01:44 PM UTC 24 |
| Peak memory | 214656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4001515550 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.4001515550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/18.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_smoke_zero_delays.184619023 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 29747530 ps |
| CPU time | 3.21 seconds |
| Started | Oct 14 09:01:17 PM UTC 24 |
| Finished | Oct 14 09:01:21 PM UTC 24 |
| Peak memory | 214612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=184619023 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/x bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delays.184619023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/18.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_stress_all.2265731771 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 499038155 ps |
| CPU time | 56.04 seconds |
| Started | Oct 14 09:01:24 PM UTC 24 |
| Finished | Oct 14 09:02:22 PM UTC 24 |
| Peak memory | 216680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2265731771 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.2265731771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/18.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_stress_all_with_error.4257106673 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 2196121379 ps |
| CPU time | 49.93 seconds |
| Started | Oct 14 09:01:26 PM UTC 24 |
| Finished | Oct 14 09:02:18 PM UTC 24 |
| Peak memory | 216748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4257106673 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.4257106673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/18.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_stress_all_with_rand_reset.592440192 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 3023824935 ps |
| CPU time | 486.04 seconds |
| Started | Oct 14 09:01:25 PM UTC 24 |
| Finished | Oct 14 09:09:37 PM UTC 24 |
| Peak memory | 237004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=592440192 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_rand_reset.592440192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/18.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_stress_all_with_reset_error.1698938016 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 3776134267 ps |
| CPU time | 179.11 seconds |
| Started | Oct 14 09:01:26 PM UTC 24 |
| Finished | Oct 14 09:04:29 PM UTC 24 |
| Peak memory | 231656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1698938016 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_reset_error.1698938016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/18.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/18.xbar_unmapped_addr.4186789271 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 1322419775 ps |
| CPU time | 26.75 seconds |
| Started | Oct 14 09:01:23 PM UTC 24 |
| Finished | Oct 14 09:01:51 PM UTC 24 |
| Peak memory | 216672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4186789271 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.4186789271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/18.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_access_same_device.3983351433 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 2725090424 ps |
| CPU time | 47.52 seconds |
| Started | Oct 14 09:01:43 PM UTC 24 |
| Finished | Oct 14 09:02:32 PM UTC 24 |
| Peak memory | 216748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3983351433 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device.3983351433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/19.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_access_same_device_slow_rsp.26018752 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 50196592610 ps |
| CPU time | 126.09 seconds |
| Started | Oct 14 09:01:46 PM UTC 24 |
| Finished | Oct 14 09:03:55 PM UTC 24 |
| Peak memory | 214888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26018752 -assert nopostproc +UVM_TESTN AME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device_slow_rsp.26018752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/19.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_error_and_unmapped_addr.4019326672 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 125539186 ps |
| CPU time | 12.89 seconds |
| Started | Oct 14 09:01:51 PM UTC 24 |
| Finished | Oct 14 09:02:06 PM UTC 24 |
| Peak memory | 214636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4019326672 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_addr.4019326672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/19.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_error_random.1536015992 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 470705081 ps |
| CPU time | 16.98 seconds |
| Started | Oct 14 09:01:49 PM UTC 24 |
| Finished | Oct 14 09:02:07 PM UTC 24 |
| Peak memory | 214600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1536015992 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.1536015992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/19.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_random.1308279014 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 1593983882 ps |
| CPU time | 39.88 seconds |
| Started | Oct 14 09:01:30 PM UTC 24 |
| Finished | Oct 14 09:02:12 PM UTC 24 |
| Peak memory | 214628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1308279014 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random.1308279014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/19.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_random_large_delays.3002674661 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 20283863346 ps |
| CPU time | 51.72 seconds |
| Started | Oct 14 09:01:34 PM UTC 24 |
| Finished | Oct 14 09:02:28 PM UTC 24 |
| Peak memory | 214692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3002674661 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.3002674661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/19.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_random_slow_rsp.2171350909 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 20923747172 ps |
| CPU time | 170.77 seconds |
| Started | Oct 14 09:01:37 PM UTC 24 |
| Finished | Oct 14 09:04:30 PM UTC 24 |
| Peak memory | 214952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2171350909 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.2171350909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/19.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_random_zero_delays.1970487281 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 108652141 ps |
| CPU time | 22.5 seconds |
| Started | Oct 14 09:01:33 PM UTC 24 |
| Finished | Oct 14 09:01:57 PM UTC 24 |
| Peak memory | 214620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1970487281 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_delays.1970487281 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/19.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_same_source.3664239650 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 57989877 ps |
| CPU time | 7.28 seconds |
| Started | Oct 14 09:01:47 PM UTC 24 |
| Finished | Oct 14 09:01:56 PM UTC 24 |
| Peak memory | 214628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3664239650 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.3664239650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/19.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_smoke.3099634001 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 35103030 ps |
| CPU time | 3.14 seconds |
| Started | Oct 14 09:01:28 PM UTC 24 |
| Finished | Oct 14 09:01:32 PM UTC 24 |
| Peak memory | 214588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3099634001 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.3099634001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/19.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_smoke_large_delays.2695237319 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 5537477619 ps |
| CPU time | 37.93 seconds |
| Started | Oct 14 09:01:30 PM UTC 24 |
| Finished | Oct 14 09:02:10 PM UTC 24 |
| Peak memory | 214872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2695237319 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.2695237319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/19.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_smoke_slow_rsp.137930675 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 3077886208 ps |
| CPU time | 30.07 seconds |
| Started | Oct 14 09:01:30 PM UTC 24 |
| Finished | Oct 14 09:02:02 PM UTC 24 |
| Peak memory | 214908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=137930675 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.137930675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/19.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_smoke_zero_delays.4203657081 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 33810271 ps |
| CPU time | 3.16 seconds |
| Started | Oct 14 09:01:29 PM UTC 24 |
| Finished | Oct 14 09:01:33 PM UTC 24 |
| Peak memory | 214600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4203657081 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delays.4203657081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/19.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_stress_all.1766627173 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 15194501049 ps |
| CPU time | 242.32 seconds |
| Started | Oct 14 09:01:52 PM UTC 24 |
| Finished | Oct 14 09:05:58 PM UTC 24 |
| Peak memory | 221096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1766627173 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.1766627173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/19.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_stress_all_with_error.1367131331 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 7048441105 ps |
| CPU time | 138.62 seconds |
| Started | Oct 14 09:01:56 PM UTC 24 |
| Finished | Oct 14 09:04:17 PM UTC 24 |
| Peak memory | 218796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1367131331 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.1367131331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/19.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_stress_all_with_rand_reset.3868648586 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 6828218205 ps |
| CPU time | 248.41 seconds |
| Started | Oct 14 09:01:52 PM UTC 24 |
| Finished | Oct 14 09:06:05 PM UTC 24 |
| Peak memory | 221224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3868648586 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_rand_reset.3868648586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/19.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_stress_all_with_reset_error.3621752193 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 231172437 ps |
| CPU time | 82.08 seconds |
| Started | Oct 14 09:01:57 PM UTC 24 |
| Finished | Oct 14 09:03:21 PM UTC 24 |
| Peak memory | 218736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3621752193 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_reset_error.3621752193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/19.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/19.xbar_unmapped_addr.2323116423 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 546798849 ps |
| CPU time | 5.08 seconds |
| Started | Oct 14 09:01:49 PM UTC 24 |
| Finished | Oct 14 09:01:55 PM UTC 24 |
| Peak memory | 214884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2323116423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.2323116423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/19.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_access_same_device.479173182 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 5830442819 ps |
| CPU time | 30.92 seconds |
| Started | Oct 14 08:56:32 PM UTC 24 |
| Finished | Oct 14 08:57:08 PM UTC 24 |
| Peak memory | 216740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=479173182 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xba r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device.479173182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/2.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_access_same_device_slow_rsp.1491110044 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 7026634881 ps |
| CPU time | 27.19 seconds |
| Started | Oct 14 08:56:32 PM UTC 24 |
| Finished | Oct 14 08:57:04 PM UTC 24 |
| Peak memory | 214696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1491110044 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device_slow_rsp.1491110044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/2.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_error_and_unmapped_addr.3801686887 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 527510582 ps |
| CPU time | 16.96 seconds |
| Started | Oct 14 08:56:39 PM UTC 24 |
| Finished | Oct 14 08:57:09 PM UTC 24 |
| Peak memory | 214824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3801686887 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr.3801686887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/2.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_error_random.3239164657 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 5658915271 ps |
| CPU time | 26.9 seconds |
| Started | Oct 14 08:56:34 PM UTC 24 |
| Finished | Oct 14 08:57:03 PM UTC 24 |
| Peak memory | 214688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3239164657 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.3239164657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/2.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_random.2728640056 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 19238379 ps |
| CPU time | 1.46 seconds |
| Started | Oct 14 08:56:32 PM UTC 24 |
| Finished | Oct 14 08:56:35 PM UTC 24 |
| Peak memory | 213416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2728640056 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random.2728640056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/2.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_random_large_delays.1690302 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 59252122051 ps |
| CPU time | 108.52 seconds |
| Started | Oct 14 08:56:32 PM UTC 24 |
| Finished | Oct 14 08:58:26 PM UTC 24 |
| Peak memory | 214692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1690302 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.1690302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/2.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_random_slow_rsp.1942708363 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 13400073346 ps |
| CPU time | 107.33 seconds |
| Started | Oct 14 08:56:32 PM UTC 24 |
| Finished | Oct 14 08:58:25 PM UTC 24 |
| Peak memory | 214696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1942708363 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.1942708363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/2.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_random_zero_delays.3331079832 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 174330128 ps |
| CPU time | 20.88 seconds |
| Started | Oct 14 08:56:32 PM UTC 24 |
| Finished | Oct 14 08:56:58 PM UTC 24 |
| Peak memory | 214624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3331079832 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_delays.3331079832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/2.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_smoke.2324391144 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 197561790 ps |
| CPU time | 3.53 seconds |
| Started | Oct 14 08:56:27 PM UTC 24 |
| Finished | Oct 14 08:56:55 PM UTC 24 |
| Peak memory | 214800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2324391144 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.2324391144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/2.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_smoke_large_delays.3061113603 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 28873928811 ps |
| CPU time | 39.37 seconds |
| Started | Oct 14 08:56:32 PM UTC 24 |
| Finished | Oct 14 08:57:16 PM UTC 24 |
| Peak memory | 214220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3061113603 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.3061113603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/2.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_smoke_slow_rsp.3135440216 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 4145111060 ps |
| CPU time | 24.27 seconds |
| Started | Oct 14 08:56:32 PM UTC 24 |
| Finished | Oct 14 08:57:01 PM UTC 24 |
| Peak memory | 214656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3135440216 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.3135440216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/2.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_smoke_zero_delays.2882571779 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 32228610 ps |
| CPU time | 2.2 seconds |
| Started | Oct 14 08:56:32 PM UTC 24 |
| Finished | Oct 14 08:56:39 PM UTC 24 |
| Peak memory | 214084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2882571779 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays.2882571779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/2.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_stress_all.3796141050 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 251719102 ps |
| CPU time | 17.03 seconds |
| Started | Oct 14 08:56:41 PM UTC 24 |
| Finished | Oct 14 08:57:03 PM UTC 24 |
| Peak memory | 216672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3796141050 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.3796141050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/2.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_stress_all_with_error.3649771691 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 2031486846 ps |
| CPU time | 131.69 seconds |
| Started | Oct 14 08:56:41 PM UTC 24 |
| Finished | Oct 14 08:58:59 PM UTC 24 |
| Peak memory | 218732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3649771691 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.3649771691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/2.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/2.xbar_unmapped_addr.613381249 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 34568768 ps |
| CPU time | 4.35 seconds |
| Started | Oct 14 08:56:36 PM UTC 24 |
| Finished | Oct 14 08:56:41 PM UTC 24 |
| Peak memory | 214624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=613381249 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.613381249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/2.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_access_same_device.150555709 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 711981716 ps |
| CPU time | 13.29 seconds |
| Started | Oct 14 09:02:04 PM UTC 24 |
| Finished | Oct 14 09:02:19 PM UTC 24 |
| Peak memory | 214632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=150555709 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xba r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device.150555709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/20.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_access_same_device_slow_rsp.3718415089 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 7976531964 ps |
| CPU time | 75.38 seconds |
| Started | Oct 14 09:02:05 PM UTC 24 |
| Finished | Oct 14 09:03:23 PM UTC 24 |
| Peak memory | 214696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3718415089 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device_slow_rsp.3718415089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/20.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_error_and_unmapped_addr.2398432429 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 672431839 ps |
| CPU time | 21.3 seconds |
| Started | Oct 14 09:02:08 PM UTC 24 |
| Finished | Oct 14 09:02:30 PM UTC 24 |
| Peak memory | 214628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2398432429 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_addr.2398432429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/20.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_error_random.2225371811 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 399391340 ps |
| CPU time | 19.05 seconds |
| Started | Oct 14 09:02:07 PM UTC 24 |
| Finished | Oct 14 09:02:27 PM UTC 24 |
| Peak memory | 214824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2225371811 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.2225371811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/20.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_random.2787843031 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 18485292 ps |
| CPU time | 2.73 seconds |
| Started | Oct 14 09:02:00 PM UTC 24 |
| Finished | Oct 14 09:02:05 PM UTC 24 |
| Peak memory | 214792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2787843031 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random.2787843031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/20.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_random_large_delays.2757608047 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 20342867137 ps |
| CPU time | 89.94 seconds |
| Started | Oct 14 09:02:03 PM UTC 24 |
| Finished | Oct 14 09:03:35 PM UTC 24 |
| Peak memory | 214692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2757608047 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.2757608047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/20.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_random_slow_rsp.2661012755 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 3855590558 ps |
| CPU time | 41.45 seconds |
| Started | Oct 14 09:02:03 PM UTC 24 |
| Finished | Oct 14 09:02:46 PM UTC 24 |
| Peak memory | 214692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2661012755 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.2661012755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/20.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_random_zero_delays.1645022417 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 147055823 ps |
| CPU time | 18.92 seconds |
| Started | Oct 14 09:02:02 PM UTC 24 |
| Finished | Oct 14 09:02:22 PM UTC 24 |
| Peak memory | 214616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1645022417 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_delays.1645022417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/20.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_same_source.2498498294 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 950924204 ps |
| CPU time | 26.26 seconds |
| Started | Oct 14 09:02:07 PM UTC 24 |
| Finished | Oct 14 09:02:34 PM UTC 24 |
| Peak memory | 214628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2498498294 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.2498498294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/20.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_smoke.349992594 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 131948755 ps |
| CPU time | 4.66 seconds |
| Started | Oct 14 09:01:57 PM UTC 24 |
| Finished | Oct 14 09:02:03 PM UTC 24 |
| Peak memory | 214608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=349992594 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.349992594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/20.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_smoke_large_delays.1339056488 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 6054799838 ps |
| CPU time | 45.51 seconds |
| Started | Oct 14 09:01:59 PM UTC 24 |
| Finished | Oct 14 09:02:46 PM UTC 24 |
| Peak memory | 214872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1339056488 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.1339056488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/20.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_smoke_slow_rsp.3797427782 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 4460227949 ps |
| CPU time | 34.46 seconds |
| Started | Oct 14 09:01:59 PM UTC 24 |
| Finished | Oct 14 09:02:35 PM UTC 24 |
| Peak memory | 214848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3797427782 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.3797427782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/20.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_smoke_zero_delays.16415213 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 22466269 ps |
| CPU time | 2.82 seconds |
| Started | Oct 14 09:01:58 PM UTC 24 |
| Finished | Oct 14 09:02:02 PM UTC 24 |
| Peak memory | 214580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16415213 -assert nopostproc +UVM_TESTNAME=xbar_ base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delays.16415213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/20.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_stress_all.2788934402 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 4142099052 ps |
| CPU time | 87.7 seconds |
| Started | Oct 14 09:02:11 PM UTC 24 |
| Finished | Oct 14 09:03:41 PM UTC 24 |
| Peak memory | 218540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2788934402 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.2788934402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/20.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_stress_all_with_error.358938157 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 21656390135 ps |
| CPU time | 132.11 seconds |
| Started | Oct 14 09:02:12 PM UTC 24 |
| Finished | Oct 14 09:04:26 PM UTC 24 |
| Peak memory | 221032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=358938157 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.358938157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/20.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_stress_all_with_rand_reset.2747571261 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 10217332747 ps |
| CPU time | 467.92 seconds |
| Started | Oct 14 09:02:11 PM UTC 24 |
| Finished | Oct 14 09:10:06 PM UTC 24 |
| Peak memory | 221908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2747571261 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_rand_reset.2747571261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/20.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_stress_all_with_reset_error.3909929402 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 442783214 ps |
| CPU time | 117.72 seconds |
| Started | Oct 14 09:02:13 PM UTC 24 |
| Finished | Oct 14 09:04:13 PM UTC 24 |
| Peak memory | 220976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3909929402 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_reset_error.3909929402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/20.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/20.xbar_unmapped_addr.3204588161 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 152859868 ps |
| CPU time | 20.6 seconds |
| Started | Oct 14 09:02:07 PM UTC 24 |
| Finished | Oct 14 09:02:29 PM UTC 24 |
| Peak memory | 216672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3204588161 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.3204588161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/20.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_access_same_device.1024617509 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 194506327 ps |
| CPU time | 15.58 seconds |
| Started | Oct 14 09:02:26 PM UTC 24 |
| Finished | Oct 14 09:02:43 PM UTC 24 |
| Peak memory | 214636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1024617509 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device.1024617509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/21.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_access_same_device_slow_rsp.3212550502 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 71781044700 ps |
| CPU time | 352.07 seconds |
| Started | Oct 14 09:02:27 PM UTC 24 |
| Finished | Oct 14 09:08:24 PM UTC 24 |
| Peak memory | 216740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3212550502 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device_slow_rsp.3212550502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/21.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_error_and_unmapped_addr.773657574 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 643146878 ps |
| CPU time | 16.29 seconds |
| Started | Oct 14 09:02:32 PM UTC 24 |
| Finished | Oct 14 09:02:49 PM UTC 24 |
| Peak memory | 214828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=773657574 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_addr.773657574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/21.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_error_random.1233441165 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 6161403115 ps |
| CPU time | 39.53 seconds |
| Started | Oct 14 09:02:28 PM UTC 24 |
| Finished | Oct 14 09:03:09 PM UTC 24 |
| Peak memory | 214660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1233441165 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.1233441165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/21.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_random.3159257432 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 1535369235 ps |
| CPU time | 15.44 seconds |
| Started | Oct 14 09:02:20 PM UTC 24 |
| Finished | Oct 14 09:02:37 PM UTC 24 |
| Peak memory | 214824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3159257432 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random.3159257432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/21.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_random_large_delays.1587674727 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 73979022698 ps |
| CPU time | 128.22 seconds |
| Started | Oct 14 09:02:24 PM UTC 24 |
| Finished | Oct 14 09:04:34 PM UTC 24 |
| Peak memory | 214892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1587674727 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.1587674727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/21.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_random_slow_rsp.1182295671 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 9417077975 ps |
| CPU time | 78.78 seconds |
| Started | Oct 14 09:02:24 PM UTC 24 |
| Finished | Oct 14 09:03:44 PM UTC 24 |
| Peak memory | 214692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1182295671 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.1182295671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/21.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_random_zero_delays.1008271870 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 176170408 ps |
| CPU time | 21.93 seconds |
| Started | Oct 14 09:02:22 PM UTC 24 |
| Finished | Oct 14 09:02:46 PM UTC 24 |
| Peak memory | 214880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1008271870 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_delays.1008271870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/21.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_same_source.2135276976 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 99902217 ps |
| CPU time | 11.73 seconds |
| Started | Oct 14 09:02:28 PM UTC 24 |
| Finished | Oct 14 09:02:41 PM UTC 24 |
| Peak memory | 214824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2135276976 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.2135276976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/21.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_smoke.251930610 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 26074207 ps |
| CPU time | 2.85 seconds |
| Started | Oct 14 09:02:15 PM UTC 24 |
| Finished | Oct 14 09:02:19 PM UTC 24 |
| Peak memory | 214612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=251930610 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.251930610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/21.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_smoke_large_delays.2035707686 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 8164049434 ps |
| CPU time | 51.13 seconds |
| Started | Oct 14 09:02:19 PM UTC 24 |
| Finished | Oct 14 09:03:12 PM UTC 24 |
| Peak memory | 214680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2035707686 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.2035707686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/21.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_smoke_slow_rsp.228271302 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 5597224058 ps |
| CPU time | 29.2 seconds |
| Started | Oct 14 09:02:20 PM UTC 24 |
| Finished | Oct 14 09:02:51 PM UTC 24 |
| Peak memory | 214648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=228271302 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.228271302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/21.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_smoke_zero_delays.3851303957 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 28869800 ps |
| CPU time | 3.22 seconds |
| Started | Oct 14 09:02:19 PM UTC 24 |
| Finished | Oct 14 09:02:23 PM UTC 24 |
| Peak memory | 214600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3851303957 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delays.3851303957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/21.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_stress_all.2547583394 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 12285761059 ps |
| CPU time | 145.32 seconds |
| Started | Oct 14 09:02:33 PM UTC 24 |
| Finished | Oct 14 09:05:01 PM UTC 24 |
| Peak memory | 218788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2547583394 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.2547583394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/21.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_stress_all_with_error.3905313876 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 2849261395 ps |
| CPU time | 43.18 seconds |
| Started | Oct 14 09:02:36 PM UTC 24 |
| Finished | Oct 14 09:03:20 PM UTC 24 |
| Peak memory | 214696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3905313876 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.3905313876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/21.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_stress_all_with_rand_reset.1293030938 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 1355293392 ps |
| CPU time | 339.18 seconds |
| Started | Oct 14 09:02:33 PM UTC 24 |
| Finished | Oct 14 09:08:17 PM UTC 24 |
| Peak memory | 220772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1293030938 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_rand_reset.1293030938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/21.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_stress_all_with_reset_error.458047631 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 4897244653 ps |
| CPU time | 119.63 seconds |
| Started | Oct 14 09:02:36 PM UTC 24 |
| Finished | Oct 14 09:04:37 PM UTC 24 |
| Peak memory | 220844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=458047631 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_reset_error.458047631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/21.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/21.xbar_unmapped_addr.271566773 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 1507361714 ps |
| CPU time | 22.98 seconds |
| Started | Oct 14 09:02:30 PM UTC 24 |
| Finished | Oct 14 09:02:54 PM UTC 24 |
| Peak memory | 214628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=271566773 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.271566773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/21.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_access_same_device.1237711277 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 453321023 ps |
| CPU time | 36.92 seconds |
| Started | Oct 14 09:02:45 PM UTC 24 |
| Finished | Oct 14 09:03:23 PM UTC 24 |
| Peak memory | 216876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1237711277 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device.1237711277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/22.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_access_same_device_slow_rsp.4202456892 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 24426999840 ps |
| CPU time | 210.31 seconds |
| Started | Oct 14 09:02:45 PM UTC 24 |
| Finished | Oct 14 09:06:18 PM UTC 24 |
| Peak memory | 216740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4202456892 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device_slow_rsp.4202456892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/22.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_error_and_unmapped_addr.2614586925 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 40553832 ps |
| CPU time | 2.24 seconds |
| Started | Oct 14 09:02:50 PM UTC 24 |
| Finished | Oct 14 09:02:53 PM UTC 24 |
| Peak memory | 214612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2614586925 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_addr.2614586925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/22.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_error_random.2480126534 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 149161926 ps |
| CPU time | 12.87 seconds |
| Started | Oct 14 09:02:47 PM UTC 24 |
| Finished | Oct 14 09:03:01 PM UTC 24 |
| Peak memory | 214600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2480126534 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.2480126534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/22.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_random.3835001307 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 654734078 ps |
| CPU time | 12.61 seconds |
| Started | Oct 14 09:02:41 PM UTC 24 |
| Finished | Oct 14 09:02:55 PM UTC 24 |
| Peak memory | 214624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3835001307 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random.3835001307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/22.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_random_large_delays.989298872 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 19839702560 ps |
| CPU time | 134.47 seconds |
| Started | Oct 14 09:02:43 PM UTC 24 |
| Finished | Oct 14 09:04:59 PM UTC 24 |
| Peak memory | 216736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=989298872 -assert nopostproc +UVM_ TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.989298872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/22.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_random_slow_rsp.2944281159 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 9188924446 ps |
| CPU time | 100.61 seconds |
| Started | Oct 14 09:02:44 PM UTC 24 |
| Finished | Oct 14 09:04:26 PM UTC 24 |
| Peak memory | 214952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2944281159 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.2944281159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/22.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_random_zero_delays.672998794 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 423221192 ps |
| CPU time | 34.62 seconds |
| Started | Oct 14 09:02:42 PM UTC 24 |
| Finished | Oct 14 09:03:19 PM UTC 24 |
| Peak memory | 214620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=672998794 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_delays.672998794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/22.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_same_source.3518343127 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 1921269991 ps |
| CPU time | 27.85 seconds |
| Started | Oct 14 09:02:46 PM UTC 24 |
| Finished | Oct 14 09:03:15 PM UTC 24 |
| Peak memory | 214820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3518343127 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.3518343127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/22.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_smoke.2662574551 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 108609514 ps |
| CPU time | 2.75 seconds |
| Started | Oct 14 09:02:36 PM UTC 24 |
| Finished | Oct 14 09:02:39 PM UTC 24 |
| Peak memory | 214588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2662574551 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.2662574551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/22.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_smoke_large_delays.1320306708 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 4566758149 ps |
| CPU time | 49.42 seconds |
| Started | Oct 14 09:02:38 PM UTC 24 |
| Finished | Oct 14 09:03:29 PM UTC 24 |
| Peak memory | 214680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1320306708 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.1320306708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/22.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_smoke_slow_rsp.3369291747 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 3058498165 ps |
| CPU time | 26.96 seconds |
| Started | Oct 14 09:02:40 PM UTC 24 |
| Finished | Oct 14 09:03:08 PM UTC 24 |
| Peak memory | 214652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3369291747 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.3369291747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/22.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_smoke_zero_delays.3511034434 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 34580572 ps |
| CPU time | 3.4 seconds |
| Started | Oct 14 09:02:37 PM UTC 24 |
| Finished | Oct 14 09:02:41 PM UTC 24 |
| Peak memory | 214792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3511034434 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delays.3511034434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/22.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_stress_all.2694000897 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 292775760 ps |
| CPU time | 26.75 seconds |
| Started | Oct 14 09:02:52 PM UTC 24 |
| Finished | Oct 14 09:03:20 PM UTC 24 |
| Peak memory | 216672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2694000897 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.2694000897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/22.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_stress_all_with_error.527624085 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 3991231328 ps |
| CPU time | 141.72 seconds |
| Started | Oct 14 09:02:54 PM UTC 24 |
| Finished | Oct 14 09:05:18 PM UTC 24 |
| Peak memory | 214700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=527624085 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.527624085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/22.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_stress_all_with_rand_reset.3111953871 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 1722457449 ps |
| CPU time | 296.18 seconds |
| Started | Oct 14 09:02:52 PM UTC 24 |
| Finished | Oct 14 09:07:52 PM UTC 24 |
| Peak memory | 220964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3111953871 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_rand_reset.3111953871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/22.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_stress_all_with_reset_error.2115845607 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 72804959 ps |
| CPU time | 31.34 seconds |
| Started | Oct 14 09:02:55 PM UTC 24 |
| Finished | Oct 14 09:03:28 PM UTC 24 |
| Peak memory | 216680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2115845607 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_reset_error.2115845607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/22.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/22.xbar_unmapped_addr.923515677 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 75964487 ps |
| CPU time | 15.93 seconds |
| Started | Oct 14 09:02:48 PM UTC 24 |
| Finished | Oct 14 09:03:05 PM UTC 24 |
| Peak memory | 216676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=923515677 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.923515677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/22.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_access_same_device.3356175830 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 851360369 ps |
| CPU time | 45.26 seconds |
| Started | Oct 14 09:03:11 PM UTC 24 |
| Finished | Oct 14 09:03:58 PM UTC 24 |
| Peak memory | 216876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3356175830 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device.3356175830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/23.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_access_same_device_slow_rsp.34699471 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 17710325094 ps |
| CPU time | 163.76 seconds |
| Started | Oct 14 09:03:13 PM UTC 24 |
| Finished | Oct 14 09:06:00 PM UTC 24 |
| Peak memory | 216740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=34699471 -assert nopostproc +UVM_TESTN AME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device_slow_rsp.34699471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/23.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_error_and_unmapped_addr.650407743 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 2414008482 ps |
| CPU time | 27.61 seconds |
| Started | Oct 14 09:03:18 PM UTC 24 |
| Finished | Oct 14 09:03:47 PM UTC 24 |
| Peak memory | 214700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=650407743 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_addr.650407743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/23.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_error_random.2664029049 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 1898975262 ps |
| CPU time | 39.82 seconds |
| Started | Oct 14 09:03:13 PM UTC 24 |
| Finished | Oct 14 09:03:55 PM UTC 24 |
| Peak memory | 214888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2664029049 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.2664029049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/23.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_random.2222307048 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 1183288032 ps |
| CPU time | 35.06 seconds |
| Started | Oct 14 09:03:04 PM UTC 24 |
| Finished | Oct 14 09:03:40 PM UTC 24 |
| Peak memory | 214632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2222307048 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random.2222307048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/23.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_random_large_delays.98550204 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 17687787310 ps |
| CPU time | 60.75 seconds |
| Started | Oct 14 09:03:08 PM UTC 24 |
| Finished | Oct 14 09:04:11 PM UTC 24 |
| Peak memory | 214936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=98550204 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.98550204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/23.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_random_slow_rsp.1688714387 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 20347066677 ps |
| CPU time | 115.33 seconds |
| Started | Oct 14 09:03:09 PM UTC 24 |
| Finished | Oct 14 09:05:07 PM UTC 24 |
| Peak memory | 214692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1688714387 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.1688714387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/23.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_random_zero_delays.2175307923 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 33212249 ps |
| CPU time | 6.13 seconds |
| Started | Oct 14 09:03:05 PM UTC 24 |
| Finished | Oct 14 09:03:12 PM UTC 24 |
| Peak memory | 214620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2175307923 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_delays.2175307923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/23.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_same_source.2137910202 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 1040416835 ps |
| CPU time | 11.11 seconds |
| Started | Oct 14 09:03:13 PM UTC 24 |
| Finished | Oct 14 09:03:25 PM UTC 24 |
| Peak memory | 214884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2137910202 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.2137910202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/23.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_smoke.413784943 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 31612524 ps |
| CPU time | 3.38 seconds |
| Started | Oct 14 09:02:56 PM UTC 24 |
| Finished | Oct 14 09:03:01 PM UTC 24 |
| Peak memory | 214804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=413784943 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.413784943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/23.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_smoke_large_delays.2256859142 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 5285886750 ps |
| CPU time | 53.29 seconds |
| Started | Oct 14 09:03:02 PM UTC 24 |
| Finished | Oct 14 09:03:57 PM UTC 24 |
| Peak memory | 214680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2256859142 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.2256859142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/23.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_smoke_slow_rsp.1206585118 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 3571220818 ps |
| CPU time | 37.91 seconds |
| Started | Oct 14 09:03:03 PM UTC 24 |
| Finished | Oct 14 09:03:42 PM UTC 24 |
| Peak memory | 214848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1206585118 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.1206585118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/23.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_smoke_zero_delays.4269240884 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 34063469 ps |
| CPU time | 3.31 seconds |
| Started | Oct 14 09:02:59 PM UTC 24 |
| Finished | Oct 14 09:03:03 PM UTC 24 |
| Peak memory | 214600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4269240884 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delays.4269240884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/23.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_stress_all.3660614928 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 2771250305 ps |
| CPU time | 109.31 seconds |
| Started | Oct 14 09:03:20 PM UTC 24 |
| Finished | Oct 14 09:05:11 PM UTC 24 |
| Peak memory | 216808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3660614928 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.3660614928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/23.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_stress_all_with_error.500507581 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 3559577758 ps |
| CPU time | 26.02 seconds |
| Started | Oct 14 09:03:21 PM UTC 24 |
| Finished | Oct 14 09:03:49 PM UTC 24 |
| Peak memory | 214892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=500507581 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.500507581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/23.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_stress_all_with_rand_reset.883019539 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 13291154183 ps |
| CPU time | 604.53 seconds |
| Started | Oct 14 09:03:21 PM UTC 24 |
| Finished | Oct 14 09:13:34 PM UTC 24 |
| Peak memory | 232844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=883019539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_rand_reset.883019539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/23.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_stress_all_with_reset_error.2838568118 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 7590172376 ps |
| CPU time | 178.32 seconds |
| Started | Oct 14 09:03:23 PM UTC 24 |
| Finished | Oct 14 09:06:24 PM UTC 24 |
| Peak memory | 218796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2838568118 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_reset_error.2838568118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/23.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/23.xbar_unmapped_addr.3883691380 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 1043610380 ps |
| CPU time | 19.84 seconds |
| Started | Oct 14 09:03:16 PM UTC 24 |
| Finished | Oct 14 09:03:37 PM UTC 24 |
| Peak memory | 216676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3883691380 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.3883691380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/23.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_access_same_device.97443195 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 1172280134 ps |
| CPU time | 58.54 seconds |
| Started | Oct 14 09:03:31 PM UTC 24 |
| Finished | Oct 14 09:04:32 PM UTC 24 |
| Peak memory | 216672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=97443195 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar _main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device.97443195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/24.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_access_same_device_slow_rsp.382233303 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 14862403037 ps |
| CPU time | 63.28 seconds |
| Started | Oct 14 09:03:33 PM UTC 24 |
| Finished | Oct 14 09:04:39 PM UTC 24 |
| Peak memory | 214696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=382233303 -assert nopostproc +UVM_TEST NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device_slow_rsp.382233303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/24.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_error_and_unmapped_addr.1188595637 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 40240331 ps |
| CPU time | 2.85 seconds |
| Started | Oct 14 09:03:41 PM UTC 24 |
| Finished | Oct 14 09:03:45 PM UTC 24 |
| Peak memory | 214628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1188595637 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_addr.1188595637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/24.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_error_random.3672112687 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 252319666 ps |
| CPU time | 18.26 seconds |
| Started | Oct 14 09:03:39 PM UTC 24 |
| Finished | Oct 14 09:03:58 PM UTC 24 |
| Peak memory | 214624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3672112687 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.3672112687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/24.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_random.1004952137 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 716394868 ps |
| CPU time | 17.82 seconds |
| Started | Oct 14 09:03:29 PM UTC 24 |
| Finished | Oct 14 09:03:48 PM UTC 24 |
| Peak memory | 214628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1004952137 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random.1004952137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/24.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_random_large_delays.1776188407 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 38341829782 ps |
| CPU time | 166.45 seconds |
| Started | Oct 14 09:03:30 PM UTC 24 |
| Finished | Oct 14 09:06:19 PM UTC 24 |
| Peak memory | 214696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1776188407 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.1776188407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/24.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_random_slow_rsp.3318493427 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 31395356603 ps |
| CPU time | 98.26 seconds |
| Started | Oct 14 09:03:30 PM UTC 24 |
| Finished | Oct 14 09:05:11 PM UTC 24 |
| Peak memory | 214696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3318493427 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.3318493427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/24.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_random_zero_delays.3191806162 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 143091419 ps |
| CPU time | 10.92 seconds |
| Started | Oct 14 09:03:29 PM UTC 24 |
| Finished | Oct 14 09:03:41 PM UTC 24 |
| Peak memory | 214812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3191806162 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_delays.3191806162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/24.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_same_source.1356453242 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 474042045 ps |
| CPU time | 23.12 seconds |
| Started | Oct 14 09:03:36 PM UTC 24 |
| Finished | Oct 14 09:04:00 PM UTC 24 |
| Peak memory | 214820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1356453242 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.1356453242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/24.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_smoke.21140803 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 37279069 ps |
| CPU time | 3.03 seconds |
| Started | Oct 14 09:03:24 PM UTC 24 |
| Finished | Oct 14 09:03:29 PM UTC 24 |
| Peak memory | 214608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21140803 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs /coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.21140803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/24.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_smoke_large_delays.3029855070 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 4874845061 ps |
| CPU time | 21.43 seconds |
| Started | Oct 14 09:03:24 PM UTC 24 |
| Finished | Oct 14 09:03:47 PM UTC 24 |
| Peak memory | 214668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3029855070 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.3029855070 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/24.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_smoke_slow_rsp.299808503 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 4266336158 ps |
| CPU time | 37.37 seconds |
| Started | Oct 14 09:03:26 PM UTC 24 |
| Finished | Oct 14 09:04:05 PM UTC 24 |
| Peak memory | 214652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=299808503 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.299808503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/24.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_smoke_zero_delays.3743866538 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 58075928 ps |
| CPU time | 2.68 seconds |
| Started | Oct 14 09:03:24 PM UTC 24 |
| Finished | Oct 14 09:03:28 PM UTC 24 |
| Peak memory | 214584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3743866538 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delays.3743866538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/24.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_stress_all.401777677 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 1827636977 ps |
| CPU time | 209.96 seconds |
| Started | Oct 14 09:03:42 PM UTC 24 |
| Finished | Oct 14 09:07:16 PM UTC 24 |
| Peak memory | 218724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=401777677 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.401777677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/24.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_stress_all_with_error.1992210772 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 444330532 ps |
| CPU time | 17.74 seconds |
| Started | Oct 14 09:03:44 PM UTC 24 |
| Finished | Oct 14 09:04:03 PM UTC 24 |
| Peak memory | 214632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1992210772 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.1992210772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/24.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_stress_all_with_rand_reset.1263295108 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 91186730 ps |
| CPU time | 39.97 seconds |
| Started | Oct 14 09:03:42 PM UTC 24 |
| Finished | Oct 14 09:04:24 PM UTC 24 |
| Peak memory | 218728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1263295108 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_rand_reset.1263295108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/24.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_stress_all_with_reset_error.3253068620 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 5559650241 ps |
| CPU time | 169.3 seconds |
| Started | Oct 14 09:03:45 PM UTC 24 |
| Finished | Oct 14 09:06:38 PM UTC 24 |
| Peak memory | 220848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3253068620 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_reset_error.3253068620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/24.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/24.xbar_unmapped_addr.727841568 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 474193516 ps |
| CPU time | 13.86 seconds |
| Started | Oct 14 09:03:40 PM UTC 24 |
| Finished | Oct 14 09:03:55 PM UTC 24 |
| Peak memory | 216676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=727841568 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.727841568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/24.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_access_same_device_slow_rsp.1403573828 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 61134295926 ps |
| CPU time | 320.29 seconds |
| Started | Oct 14 09:03:57 PM UTC 24 |
| Finished | Oct 14 09:09:21 PM UTC 24 |
| Peak memory | 216740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1403573828 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device_slow_rsp.1403573828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/25.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_error_and_unmapped_addr.4045248060 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 164215903 ps |
| CPU time | 4.31 seconds |
| Started | Oct 14 09:03:59 PM UTC 24 |
| Finished | Oct 14 09:04:05 PM UTC 24 |
| Peak memory | 214884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4045248060 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_addr.4045248060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/25.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_error_random.1415007184 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 636297076 ps |
| CPU time | 21.61 seconds |
| Started | Oct 14 09:03:59 PM UTC 24 |
| Finished | Oct 14 09:04:22 PM UTC 24 |
| Peak memory | 214892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1415007184 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.1415007184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/25.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_random.187754488 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 171668191 ps |
| CPU time | 23.29 seconds |
| Started | Oct 14 09:03:50 PM UTC 24 |
| Finished | Oct 14 09:04:14 PM UTC 24 |
| Peak memory | 214824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=187754488 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random.187754488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/25.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_random_large_delays.43712356 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 71454644115 ps |
| CPU time | 103.98 seconds |
| Started | Oct 14 09:03:54 PM UTC 24 |
| Finished | Oct 14 09:05:40 PM UTC 24 |
| Peak memory | 214692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=43712356 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.43712356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/25.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_random_slow_rsp.3328640257 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 29045434908 ps |
| CPU time | 163.32 seconds |
| Started | Oct 14 09:03:55 PM UTC 24 |
| Finished | Oct 14 09:06:41 PM UTC 24 |
| Peak memory | 214692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3328640257 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.3328640257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/25.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_random_zero_delays.1124345011 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 11893978 ps |
| CPU time | 2.68 seconds |
| Started | Oct 14 09:03:54 PM UTC 24 |
| Finished | Oct 14 09:03:58 PM UTC 24 |
| Peak memory | 214812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1124345011 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_delays.1124345011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/25.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_same_source.1715407558 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 2273394556 ps |
| CPU time | 30.69 seconds |
| Started | Oct 14 09:03:58 PM UTC 24 |
| Finished | Oct 14 09:04:30 PM UTC 24 |
| Peak memory | 214692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1715407558 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.1715407558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/25.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_smoke.935975464 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 473558147 ps |
| CPU time | 5.57 seconds |
| Started | Oct 14 09:03:46 PM UTC 24 |
| Finished | Oct 14 09:03:53 PM UTC 24 |
| Peak memory | 214804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=935975464 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.935975464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/25.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_smoke_large_delays.2649741012 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 7863765283 ps |
| CPU time | 34.64 seconds |
| Started | Oct 14 09:03:48 PM UTC 24 |
| Finished | Oct 14 09:04:25 PM UTC 24 |
| Peak memory | 214680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2649741012 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.2649741012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/25.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_smoke_slow_rsp.2837086056 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 6610361319 ps |
| CPU time | 41.13 seconds |
| Started | Oct 14 09:03:50 PM UTC 24 |
| Finished | Oct 14 09:04:32 PM UTC 24 |
| Peak memory | 214652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2837086056 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.2837086056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/25.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_smoke_zero_delays.1113283047 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 68885189 ps |
| CPU time | 2.88 seconds |
| Started | Oct 14 09:03:48 PM UTC 24 |
| Finished | Oct 14 09:03:53 PM UTC 24 |
| Peak memory | 214600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1113283047 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delays.1113283047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/25.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_stress_all.302452200 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 6007247 ps |
| CPU time | 1.21 seconds |
| Started | Oct 14 09:04:01 PM UTC 24 |
| Finished | Oct 14 09:04:03 PM UTC 24 |
| Peak memory | 202656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=302452200 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.302452200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/25.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_stress_all_with_error.779335779 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 6229752598 ps |
| CPU time | 76.54 seconds |
| Started | Oct 14 09:04:04 PM UTC 24 |
| Finished | Oct 14 09:05:22 PM UTC 24 |
| Peak memory | 216744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=779335779 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.779335779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/25.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_stress_all_with_rand_reset.3854887160 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 2257808173 ps |
| CPU time | 291.82 seconds |
| Started | Oct 14 09:04:02 PM UTC 24 |
| Finished | Oct 14 09:08:58 PM UTC 24 |
| Peak memory | 221100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3854887160 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_rand_reset.3854887160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/25.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_stress_all_with_reset_error.3310308086 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 245187540 ps |
| CPU time | 63.61 seconds |
| Started | Oct 14 09:04:04 PM UTC 24 |
| Finished | Oct 14 09:05:09 PM UTC 24 |
| Peak memory | 218732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3310308086 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_reset_error.3310308086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/25.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/25.xbar_unmapped_addr.83856000 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 460250624 ps |
| CPU time | 20.82 seconds |
| Started | Oct 14 09:03:59 PM UTC 24 |
| Finished | Oct 14 09:04:21 PM UTC 24 |
| Peak memory | 214624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=83856000 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.83856000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/25.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_access_same_device.293294131 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 1093597276 ps |
| CPU time | 22.76 seconds |
| Started | Oct 14 09:04:14 PM UTC 24 |
| Finished | Oct 14 09:04:38 PM UTC 24 |
| Peak memory | 216872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=293294131 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xba r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device.293294131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/26.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_access_same_device_slow_rsp.3900797073 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 44021009559 ps |
| CPU time | 359.34 seconds |
| Started | Oct 14 09:04:16 PM UTC 24 |
| Finished | Oct 14 09:10:20 PM UTC 24 |
| Peak memory | 216740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3900797073 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device_slow_rsp.3900797073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/26.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_error_and_unmapped_addr.1198371605 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 866790682 ps |
| CPU time | 12.52 seconds |
| Started | Oct 14 09:04:19 PM UTC 24 |
| Finished | Oct 14 09:04:32 PM UTC 24 |
| Peak memory | 214628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1198371605 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_addr.1198371605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/26.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_error_random.268640111 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 652009390 ps |
| CPU time | 14.39 seconds |
| Started | Oct 14 09:04:19 PM UTC 24 |
| Finished | Oct 14 09:04:34 PM UTC 24 |
| Peak memory | 214624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=268640111 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.268640111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/26.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_random.3403092483 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 153457775 ps |
| CPU time | 5.88 seconds |
| Started | Oct 14 09:04:11 PM UTC 24 |
| Finished | Oct 14 09:04:18 PM UTC 24 |
| Peak memory | 214628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3403092483 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random.3403092483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/26.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_random_large_delays.614102486 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 10609055581 ps |
| CPU time | 63.22 seconds |
| Started | Oct 14 09:04:12 PM UTC 24 |
| Finished | Oct 14 09:05:17 PM UTC 24 |
| Peak memory | 214688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=614102486 -assert nopostproc +UVM_ TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.614102486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/26.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_random_slow_rsp.527698265 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 20315348491 ps |
| CPU time | 82.04 seconds |
| Started | Oct 14 09:04:14 PM UTC 24 |
| Finished | Oct 14 09:05:37 PM UTC 24 |
| Peak memory | 216744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=527698265 -assert nopostproc +UVM_TEST NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.527698265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/26.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_random_zero_delays.436963706 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 59021394 ps |
| CPU time | 3.22 seconds |
| Started | Oct 14 09:04:12 PM UTC 24 |
| Finished | Oct 14 09:04:16 PM UTC 24 |
| Peak memory | 214620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=436963706 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_delays.436963706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/26.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_same_source.2739066613 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 170757582 ps |
| CPU time | 15.31 seconds |
| Started | Oct 14 09:04:17 PM UTC 24 |
| Finished | Oct 14 09:04:33 PM UTC 24 |
| Peak memory | 214624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2739066613 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.2739066613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/26.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_smoke.3270924705 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 58693381 ps |
| CPU time | 2.82 seconds |
| Started | Oct 14 09:04:06 PM UTC 24 |
| Finished | Oct 14 09:04:10 PM UTC 24 |
| Peak memory | 214564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3270924705 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.3270924705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/26.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_smoke_large_delays.2929175553 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 6289740510 ps |
| CPU time | 36.77 seconds |
| Started | Oct 14 09:04:08 PM UTC 24 |
| Finished | Oct 14 09:04:46 PM UTC 24 |
| Peak memory | 214872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2929175553 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.2929175553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/26.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_smoke_slow_rsp.3298578805 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 3310763598 ps |
| CPU time | 29.65 seconds |
| Started | Oct 14 09:04:08 PM UTC 24 |
| Finished | Oct 14 09:04:39 PM UTC 24 |
| Peak memory | 214652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3298578805 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.3298578805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/26.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_smoke_zero_delays.4187802104 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 31516290 ps |
| CPU time | 3.44 seconds |
| Started | Oct 14 09:04:06 PM UTC 24 |
| Finished | Oct 14 09:04:11 PM UTC 24 |
| Peak memory | 214408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4187802104 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delays.4187802104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/26.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_stress_all.817560799 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 4729946816 ps |
| CPU time | 144.02 seconds |
| Started | Oct 14 09:04:21 PM UTC 24 |
| Finished | Oct 14 09:06:47 PM UTC 24 |
| Peak memory | 218980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=817560799 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.817560799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/26.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_stress_all_with_error.347199146 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 6442893635 ps |
| CPU time | 95.18 seconds |
| Started | Oct 14 09:04:23 PM UTC 24 |
| Finished | Oct 14 09:06:00 PM UTC 24 |
| Peak memory | 218792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=347199146 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.347199146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/26.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_stress_all_with_rand_reset.3148460040 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 591450176 ps |
| CPU time | 174.02 seconds |
| Started | Oct 14 09:04:22 PM UTC 24 |
| Finished | Oct 14 09:07:19 PM UTC 24 |
| Peak memory | 220772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3148460040 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_rand_reset.3148460040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/26.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_stress_all_with_reset_error.2867610595 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 7353798442 ps |
| CPU time | 438.54 seconds |
| Started | Oct 14 09:04:25 PM UTC 24 |
| Finished | Oct 14 09:11:49 PM UTC 24 |
| Peak memory | 239060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2867610595 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_reset_error.2867610595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/26.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/26.xbar_unmapped_addr.1197646713 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 39017617 ps |
| CPU time | 8.06 seconds |
| Started | Oct 14 09:04:19 PM UTC 24 |
| Finished | Oct 14 09:04:28 PM UTC 24 |
| Peak memory | 214820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1197646713 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.1197646713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/26.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_access_same_device.634475118 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 315042256 ps |
| CPU time | 19.34 seconds |
| Started | Oct 14 09:04:32 PM UTC 24 |
| Finished | Oct 14 09:04:53 PM UTC 24 |
| Peak memory | 214628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=634475118 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xba r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device.634475118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/27.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_access_same_device_slow_rsp.539755438 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 37759026665 ps |
| CPU time | 220.89 seconds |
| Started | Oct 14 09:04:32 PM UTC 24 |
| Finished | Oct 14 09:08:16 PM UTC 24 |
| Peak memory | 216744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=539755438 -assert nopostproc +UVM_TEST NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device_slow_rsp.539755438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/27.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_error_and_unmapped_addr.1166111255 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 989867211 ps |
| CPU time | 15.23 seconds |
| Started | Oct 14 09:04:35 PM UTC 24 |
| Finished | Oct 14 09:04:51 PM UTC 24 |
| Peak memory | 214632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1166111255 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_addr.1166111255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/27.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_error_random.2511969997 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 295539781 ps |
| CPU time | 7.78 seconds |
| Started | Oct 14 09:04:35 PM UTC 24 |
| Finished | Oct 14 09:04:44 PM UTC 24 |
| Peak memory | 214600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2511969997 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.2511969997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/27.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_random.3699501253 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 56063229 ps |
| CPU time | 9.03 seconds |
| Started | Oct 14 09:04:29 PM UTC 24 |
| Finished | Oct 14 09:04:39 PM UTC 24 |
| Peak memory | 214692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3699501253 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random.3699501253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/27.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_random_large_delays.227835696 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 2409269124 ps |
| CPU time | 12.44 seconds |
| Started | Oct 14 09:04:32 PM UTC 24 |
| Finished | Oct 14 09:04:46 PM UTC 24 |
| Peak memory | 214684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=227835696 -assert nopostproc +UVM_ TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.227835696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/27.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_random_slow_rsp.3184768397 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 60611914274 ps |
| CPU time | 187.22 seconds |
| Started | Oct 14 09:04:32 PM UTC 24 |
| Finished | Oct 14 09:07:43 PM UTC 24 |
| Peak memory | 216744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3184768397 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.3184768397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/27.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_random_zero_delays.685606914 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 70650438 ps |
| CPU time | 4.04 seconds |
| Started | Oct 14 09:04:30 PM UTC 24 |
| Finished | Oct 14 09:04:35 PM UTC 24 |
| Peak memory | 214620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=685606914 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_delays.685606914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/27.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_same_source.1886632992 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 76738604 ps |
| CPU time | 4.76 seconds |
| Started | Oct 14 09:04:35 PM UTC 24 |
| Finished | Oct 14 09:04:41 PM UTC 24 |
| Peak memory | 214624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1886632992 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.1886632992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/27.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_smoke.2462818612 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 137258945 ps |
| CPU time | 4.39 seconds |
| Started | Oct 14 09:04:26 PM UTC 24 |
| Finished | Oct 14 09:04:32 PM UTC 24 |
| Peak memory | 214584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2462818612 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.2462818612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/27.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_smoke_large_delays.3454512206 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 9255644192 ps |
| CPU time | 52.66 seconds |
| Started | Oct 14 09:04:28 PM UTC 24 |
| Finished | Oct 14 09:05:22 PM UTC 24 |
| Peak memory | 214868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3454512206 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.3454512206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/27.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_smoke_slow_rsp.2948897651 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 4044298835 ps |
| CPU time | 41.07 seconds |
| Started | Oct 14 09:04:28 PM UTC 24 |
| Finished | Oct 14 09:05:10 PM UTC 24 |
| Peak memory | 214660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2948897651 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.2948897651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/27.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_smoke_zero_delays.488724408 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 39226635 ps |
| CPU time | 2.96 seconds |
| Started | Oct 14 09:04:26 PM UTC 24 |
| Finished | Oct 14 09:04:31 PM UTC 24 |
| Peak memory | 214868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=488724408 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/x bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delays.488724408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/27.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_stress_all.502481054 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 1056383088 ps |
| CPU time | 47.55 seconds |
| Started | Oct 14 09:04:35 PM UTC 24 |
| Finished | Oct 14 09:05:24 PM UTC 24 |
| Peak memory | 216676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=502481054 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.502481054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/27.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_stress_all_with_error.2448113825 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 2824360981 ps |
| CPU time | 141.87 seconds |
| Started | Oct 14 09:04:35 PM UTC 24 |
| Finished | Oct 14 09:06:59 PM UTC 24 |
| Peak memory | 220848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2448113825 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.2448113825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/27.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_stress_all_with_rand_reset.3374183662 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 118331545 ps |
| CPU time | 35.35 seconds |
| Started | Oct 14 09:04:35 PM UTC 24 |
| Finished | Oct 14 09:05:12 PM UTC 24 |
| Peak memory | 216672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3374183662 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_rand_reset.3374183662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/27.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_stress_all_with_reset_error.1609672984 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 326482603 ps |
| CPU time | 116.55 seconds |
| Started | Oct 14 09:04:37 PM UTC 24 |
| Finished | Oct 14 09:06:36 PM UTC 24 |
| Peak memory | 220780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1609672984 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_reset_error.1609672984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/27.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/27.xbar_unmapped_addr.569323372 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 665063504 ps |
| CPU time | 19.64 seconds |
| Started | Oct 14 09:04:35 PM UTC 24 |
| Finished | Oct 14 09:04:56 PM UTC 24 |
| Peak memory | 216868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=569323372 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.569323372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/27.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_access_same_device.1637994027 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 554027290 ps |
| CPU time | 14.89 seconds |
| Started | Oct 14 09:04:42 PM UTC 24 |
| Finished | Oct 14 09:04:58 PM UTC 24 |
| Peak memory | 214636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1637994027 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device.1637994027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/28.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_access_same_device_slow_rsp.641418054 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 13962168067 ps |
| CPU time | 175.07 seconds |
| Started | Oct 14 09:04:42 PM UTC 24 |
| Finished | Oct 14 09:07:40 PM UTC 24 |
| Peak memory | 214884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=641418054 -assert nopostproc +UVM_TEST NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device_slow_rsp.641418054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/28.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_error_and_unmapped_addr.1209048804 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 230760404 ps |
| CPU time | 14.33 seconds |
| Started | Oct 14 09:04:47 PM UTC 24 |
| Finished | Oct 14 09:05:02 PM UTC 24 |
| Peak memory | 214888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1209048804 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_addr.1209048804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/28.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_error_random.4167576527 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 600412558 ps |
| CPU time | 18.33 seconds |
| Started | Oct 14 09:04:44 PM UTC 24 |
| Finished | Oct 14 09:05:04 PM UTC 24 |
| Peak memory | 214624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4167576527 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.4167576527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/28.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_random.4026102695 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 426470230 ps |
| CPU time | 22.62 seconds |
| Started | Oct 14 09:04:39 PM UTC 24 |
| Finished | Oct 14 09:05:02 PM UTC 24 |
| Peak memory | 214624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4026102695 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random.4026102695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/28.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_random_large_delays.2031362664 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 43930467422 ps |
| CPU time | 88.25 seconds |
| Started | Oct 14 09:04:40 PM UTC 24 |
| Finished | Oct 14 09:06:11 PM UTC 24 |
| Peak memory | 214888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2031362664 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.2031362664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/28.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_random_slow_rsp.2668294461 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 10537851899 ps |
| CPU time | 96.28 seconds |
| Started | Oct 14 09:04:40 PM UTC 24 |
| Finished | Oct 14 09:06:19 PM UTC 24 |
| Peak memory | 214700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2668294461 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.2668294461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/28.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_random_zero_delays.2684420946 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 293615079 ps |
| CPU time | 35.33 seconds |
| Started | Oct 14 09:04:40 PM UTC 24 |
| Finished | Oct 14 09:05:17 PM UTC 24 |
| Peak memory | 216668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2684420946 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_delays.2684420946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/28.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_same_source.50918561 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 80676994 ps |
| CPU time | 5.09 seconds |
| Started | Oct 14 09:04:44 PM UTC 24 |
| Finished | Oct 14 09:04:50 PM UTC 24 |
| Peak memory | 214624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=50918561 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.50918561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/28.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_smoke.3357189574 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 218109116 ps |
| CPU time | 5.34 seconds |
| Started | Oct 14 09:04:37 PM UTC 24 |
| Finished | Oct 14 09:04:43 PM UTC 24 |
| Peak memory | 214592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3357189574 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.3357189574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/28.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_smoke_large_delays.2477782199 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 12296070853 ps |
| CPU time | 38.7 seconds |
| Started | Oct 14 09:04:37 PM UTC 24 |
| Finished | Oct 14 09:05:17 PM UTC 24 |
| Peak memory | 214680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2477782199 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.2477782199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/28.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_smoke_slow_rsp.3943131967 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 3388728849 ps |
| CPU time | 33.94 seconds |
| Started | Oct 14 09:04:39 PM UTC 24 |
| Finished | Oct 14 09:05:14 PM UTC 24 |
| Peak memory | 214656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3943131967 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.3943131967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/28.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_smoke_zero_delays.349907138 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 35559400 ps |
| CPU time | 3.2 seconds |
| Started | Oct 14 09:04:37 PM UTC 24 |
| Finished | Oct 14 09:04:41 PM UTC 24 |
| Peak memory | 214608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=349907138 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/x bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delays.349907138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/28.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_stress_all.4148129421 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 12910992664 ps |
| CPU time | 308.63 seconds |
| Started | Oct 14 09:04:51 PM UTC 24 |
| Finished | Oct 14 09:10:04 PM UTC 24 |
| Peak memory | 218788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4148129421 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.4148129421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/28.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_stress_all_with_error.3943443299 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 560078538 ps |
| CPU time | 53.8 seconds |
| Started | Oct 14 09:04:55 PM UTC 24 |
| Finished | Oct 14 09:05:50 PM UTC 24 |
| Peak memory | 216684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3943443299 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.3943443299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/28.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_stress_all_with_rand_reset.2849572058 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 2467864634 ps |
| CPU time | 432.23 seconds |
| Started | Oct 14 09:04:52 PM UTC 24 |
| Finished | Oct 14 09:12:10 PM UTC 24 |
| Peak memory | 233764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2849572058 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_rand_reset.2849572058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/28.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_stress_all_with_reset_error.1521574361 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 104850466 ps |
| CPU time | 16.63 seconds |
| Started | Oct 14 09:04:57 PM UTC 24 |
| Finished | Oct 14 09:05:15 PM UTC 24 |
| Peak memory | 216680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1521574361 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_reset_error.1521574361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/28.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/28.xbar_unmapped_addr.4099740413 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 3843927147 ps |
| CPU time | 34.88 seconds |
| Started | Oct 14 09:04:47 PM UTC 24 |
| Finished | Oct 14 09:05:23 PM UTC 24 |
| Peak memory | 216996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4099740413 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.4099740413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/28.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_access_same_device.1465525290 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 1571285506 ps |
| CPU time | 46.86 seconds |
| Started | Oct 14 09:05:08 PM UTC 24 |
| Finished | Oct 14 09:05:57 PM UTC 24 |
| Peak memory | 216876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1465525290 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device.1465525290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/29.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_access_same_device_slow_rsp.3562190373 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 50679645903 ps |
| CPU time | 277.75 seconds |
| Started | Oct 14 09:05:10 PM UTC 24 |
| Finished | Oct 14 09:09:52 PM UTC 24 |
| Peak memory | 216936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3562190373 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device_slow_rsp.3562190373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/29.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_error_and_unmapped_addr.4042723773 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 490504906 ps |
| CPU time | 22.52 seconds |
| Started | Oct 14 09:05:13 PM UTC 24 |
| Finished | Oct 14 09:05:36 PM UTC 24 |
| Peak memory | 214660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4042723773 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_addr.4042723773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/29.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_error_random.2767366339 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 137251046 ps |
| CPU time | 16.51 seconds |
| Started | Oct 14 09:05:11 PM UTC 24 |
| Finished | Oct 14 09:05:29 PM UTC 24 |
| Peak memory | 214884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2767366339 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.2767366339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/29.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_random.2775391708 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 1371147404 ps |
| CPU time | 16.48 seconds |
| Started | Oct 14 09:05:03 PM UTC 24 |
| Finished | Oct 14 09:05:21 PM UTC 24 |
| Peak memory | 214628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2775391708 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random.2775391708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/29.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_random_large_delays.609765081 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 9436858557 ps |
| CPU time | 60.18 seconds |
| Started | Oct 14 09:05:06 PM UTC 24 |
| Finished | Oct 14 09:06:08 PM UTC 24 |
| Peak memory | 214688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=609765081 -assert nopostproc +UVM_ TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.609765081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/29.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_random_slow_rsp.3989932171 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 13997312818 ps |
| CPU time | 45.16 seconds |
| Started | Oct 14 09:05:06 PM UTC 24 |
| Finished | Oct 14 09:05:53 PM UTC 24 |
| Peak memory | 214692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3989932171 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.3989932171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/29.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_random_zero_delays.2619478071 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 103395846 ps |
| CPU time | 10.89 seconds |
| Started | Oct 14 09:05:04 PM UTC 24 |
| Finished | Oct 14 09:05:17 PM UTC 24 |
| Peak memory | 214620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2619478071 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_delays.2619478071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/29.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_same_source.2666057073 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 254150981 ps |
| CPU time | 15.29 seconds |
| Started | Oct 14 09:05:11 PM UTC 24 |
| Finished | Oct 14 09:05:28 PM UTC 24 |
| Peak memory | 214624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2666057073 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.2666057073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/29.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_smoke.1989249887 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 154401088 ps |
| CPU time | 4.77 seconds |
| Started | Oct 14 09:04:59 PM UTC 24 |
| Finished | Oct 14 09:05:05 PM UTC 24 |
| Peak memory | 214844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1989249887 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.1989249887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/29.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_smoke_large_delays.2811865585 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 5166264228 ps |
| CPU time | 31.81 seconds |
| Started | Oct 14 09:05:02 PM UTC 24 |
| Finished | Oct 14 09:05:35 PM UTC 24 |
| Peak memory | 214680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2811865585 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.2811865585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/29.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_smoke_slow_rsp.1639363046 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 11738716186 ps |
| CPU time | 49.21 seconds |
| Started | Oct 14 09:05:03 PM UTC 24 |
| Finished | Oct 14 09:05:54 PM UTC 24 |
| Peak memory | 214652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1639363046 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.1639363046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/29.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_smoke_zero_delays.3356080869 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 43437702 ps |
| CPU time | 3.15 seconds |
| Started | Oct 14 09:05:00 PM UTC 24 |
| Finished | Oct 14 09:05:05 PM UTC 24 |
| Peak memory | 214600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3356080869 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delays.3356080869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/29.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_stress_all.2894742355 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 948445266 ps |
| CPU time | 79.42 seconds |
| Started | Oct 14 09:05:15 PM UTC 24 |
| Finished | Oct 14 09:06:36 PM UTC 24 |
| Peak memory | 218920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2894742355 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.2894742355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/29.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_stress_all_with_error.1960560748 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 6417367863 ps |
| CPU time | 147.6 seconds |
| Started | Oct 14 09:05:17 PM UTC 24 |
| Finished | Oct 14 09:07:48 PM UTC 24 |
| Peak memory | 218992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1960560748 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.1960560748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/29.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_stress_all_with_rand_reset.1245258303 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 786970740 ps |
| CPU time | 318.49 seconds |
| Started | Oct 14 09:05:16 PM UTC 24 |
| Finished | Oct 14 09:10:39 PM UTC 24 |
| Peak memory | 220968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1245258303 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_rand_reset.1245258303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/29.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_stress_all_with_reset_error.3218642970 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 917123989 ps |
| CPU time | 286.66 seconds |
| Started | Oct 14 09:05:20 PM UTC 24 |
| Finished | Oct 14 09:10:11 PM UTC 24 |
| Peak memory | 231316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3218642970 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_reset_error.3218642970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/29.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/29.xbar_unmapped_addr.3205613199 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 2840464335 ps |
| CPU time | 24.89 seconds |
| Started | Oct 14 09:05:13 PM UTC 24 |
| Finished | Oct 14 09:05:39 PM UTC 24 |
| Peak memory | 216792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3205613199 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.3205613199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/29.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_access_same_device_slow_rsp.1875064309 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 34743864199 ps |
| CPU time | 362.69 seconds |
| Started | Oct 14 08:56:50 PM UTC 24 |
| Finished | Oct 14 09:02:57 PM UTC 24 |
| Peak memory | 218260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1875064309 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device_slow_rsp.1875064309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/3.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_error_and_unmapped_addr.4115781563 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 1390049293 ps |
| CPU time | 21.8 seconds |
| Started | Oct 14 08:56:52 PM UTC 24 |
| Finished | Oct 14 08:57:15 PM UTC 24 |
| Peak memory | 214640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4115781563 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr.4115781563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/3.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_error_random.321976163 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 451290635 ps |
| CPU time | 8.59 seconds |
| Started | Oct 14 08:56:50 PM UTC 24 |
| Finished | Oct 14 08:57:00 PM UTC 24 |
| Peak memory | 214628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=321976163 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.321976163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/3.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_random.3099300243 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 204076438 ps |
| CPU time | 27.87 seconds |
| Started | Oct 14 08:56:44 PM UTC 24 |
| Finished | Oct 14 08:57:14 PM UTC 24 |
| Peak memory | 216680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3099300243 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random.3099300243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/3.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_random_large_delays.750807746 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 7266112129 ps |
| CPU time | 41.19 seconds |
| Started | Oct 14 08:56:44 PM UTC 24 |
| Finished | Oct 14 08:57:28 PM UTC 24 |
| Peak memory | 214692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=750807746 -assert nopostproc +UVM_ TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.750807746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/3.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_random_slow_rsp.3151229506 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 18317627405 ps |
| CPU time | 48.88 seconds |
| Started | Oct 14 08:56:44 PM UTC 24 |
| Finished | Oct 14 08:57:35 PM UTC 24 |
| Peak memory | 214892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3151229506 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.3151229506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/3.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_random_zero_delays.2848197193 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 68562951 ps |
| CPU time | 9.85 seconds |
| Started | Oct 14 08:56:44 PM UTC 24 |
| Finished | Oct 14 08:56:56 PM UTC 24 |
| Peak memory | 214812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2848197193 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_delays.2848197193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/3.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_same_source.632121343 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 217421626 ps |
| CPU time | 5.98 seconds |
| Started | Oct 14 08:56:50 PM UTC 24 |
| Finished | Oct 14 08:56:57 PM UTC 24 |
| Peak memory | 214628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=632121343 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.632121343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/3.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_smoke.145845777 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 61003943 ps |
| CPU time | 2.42 seconds |
| Started | Oct 14 08:56:42 PM UTC 24 |
| Finished | Oct 14 08:56:48 PM UTC 24 |
| Peak memory | 214800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=145845777 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.145845777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/3.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_smoke_large_delays.2253735886 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 7886690761 ps |
| CPU time | 34.09 seconds |
| Started | Oct 14 08:56:42 PM UTC 24 |
| Finished | Oct 14 08:57:20 PM UTC 24 |
| Peak memory | 214936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2253735886 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.2253735886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/3.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_smoke_slow_rsp.1034006331 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 5788913579 ps |
| CPU time | 27.44 seconds |
| Started | Oct 14 08:56:44 PM UTC 24 |
| Finished | Oct 14 08:57:13 PM UTC 24 |
| Peak memory | 214656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1034006331 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.1034006331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/3.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_smoke_zero_delays.3860312521 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 26953307 ps |
| CPU time | 2.32 seconds |
| Started | Oct 14 08:56:42 PM UTC 24 |
| Finished | Oct 14 08:56:48 PM UTC 24 |
| Peak memory | 214604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3860312521 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays.3860312521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/3.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_stress_all_with_error.3318865668 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 1117419849 ps |
| CPU time | 21.45 seconds |
| Started | Oct 14 08:56:53 PM UTC 24 |
| Finished | Oct 14 08:57:23 PM UTC 24 |
| Peak memory | 214632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3318865668 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.3318865668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/3.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_stress_all_with_rand_reset.2900310333 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 6064918669 ps |
| CPU time | 445.09 seconds |
| Started | Oct 14 08:56:52 PM UTC 24 |
| Finished | Oct 14 09:04:31 PM UTC 24 |
| Peak memory | 232844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2900310333 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_rand_reset.2900310333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/3.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/3.xbar_unmapped_addr.155210186 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 575953338 ps |
| CPU time | 14.62 seconds |
| Started | Oct 14 08:56:52 PM UTC 24 |
| Finished | Oct 14 08:57:08 PM UTC 24 |
| Peak memory | 216932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=155210186 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.155210186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/3.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_access_same_device.110481783 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 1285410483 ps |
| CPU time | 39.04 seconds |
| Started | Oct 14 09:05:24 PM UTC 24 |
| Finished | Oct 14 09:06:05 PM UTC 24 |
| Peak memory | 214888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=110481783 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xba r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device.110481783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/30.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_access_same_device_slow_rsp.4206325886 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 21010838236 ps |
| CPU time | 122.42 seconds |
| Started | Oct 14 09:05:26 PM UTC 24 |
| Finished | Oct 14 09:07:31 PM UTC 24 |
| Peak memory | 214884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4206325886 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device_slow_rsp.4206325886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/30.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_error_and_unmapped_addr.3235742585 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 640573406 ps |
| CPU time | 13.77 seconds |
| Started | Oct 14 09:05:31 PM UTC 24 |
| Finished | Oct 14 09:05:46 PM UTC 24 |
| Peak memory | 214632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3235742585 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_addr.3235742585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/30.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_error_random.2224300701 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 850246125 ps |
| CPU time | 27.41 seconds |
| Started | Oct 14 09:05:29 PM UTC 24 |
| Finished | Oct 14 09:05:57 PM UTC 24 |
| Peak memory | 214628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2224300701 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.2224300701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/30.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_random.2033686923 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 1110767240 ps |
| CPU time | 28.87 seconds |
| Started | Oct 14 09:05:21 PM UTC 24 |
| Finished | Oct 14 09:05:52 PM UTC 24 |
| Peak memory | 216936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2033686923 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random.2033686923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/30.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_random_large_delays.630511510 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 26595180402 ps |
| CPU time | 75.13 seconds |
| Started | Oct 14 09:05:23 PM UTC 24 |
| Finished | Oct 14 09:06:40 PM UTC 24 |
| Peak memory | 214688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=630511510 -assert nopostproc +UVM_ TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.630511510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/30.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_random_slow_rsp.1129378423 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 6845194221 ps |
| CPU time | 28.06 seconds |
| Started | Oct 14 09:05:24 PM UTC 24 |
| Finished | Oct 14 09:05:54 PM UTC 24 |
| Peak memory | 214692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1129378423 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.1129378423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/30.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_random_zero_delays.234468906 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 301839687 ps |
| CPU time | 18.51 seconds |
| Started | Oct 14 09:05:23 PM UTC 24 |
| Finished | Oct 14 09:05:43 PM UTC 24 |
| Peak memory | 214620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=234468906 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_delays.234468906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/30.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_same_source.858172273 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 2129227917 ps |
| CPU time | 27.61 seconds |
| Started | Oct 14 09:05:26 PM UTC 24 |
| Finished | Oct 14 09:05:55 PM UTC 24 |
| Peak memory | 214628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=858172273 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.858172273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/30.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_smoke.2672420265 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 33614091 ps |
| CPU time | 3.36 seconds |
| Started | Oct 14 09:05:20 PM UTC 24 |
| Finished | Oct 14 09:05:25 PM UTC 24 |
| Peak memory | 214844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2672420265 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.2672420265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/30.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_smoke_large_delays.2004175707 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 7745836276 ps |
| CPU time | 35.41 seconds |
| Started | Oct 14 09:05:20 PM UTC 24 |
| Finished | Oct 14 09:05:57 PM UTC 24 |
| Peak memory | 214664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2004175707 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.2004175707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/30.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_smoke_slow_rsp.962864832 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 5479062948 ps |
| CPU time | 31.32 seconds |
| Started | Oct 14 09:05:20 PM UTC 24 |
| Finished | Oct 14 09:05:53 PM UTC 24 |
| Peak memory | 214652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=962864832 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.962864832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/30.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_smoke_zero_delays.386867131 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 83799320 ps |
| CPU time | 2.14 seconds |
| Started | Oct 14 09:05:20 PM UTC 24 |
| Finished | Oct 14 09:05:23 PM UTC 24 |
| Peak memory | 214700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=386867131 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/x bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delays.386867131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/30.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_stress_all.3417613309 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 1567433124 ps |
| CPU time | 74.81 seconds |
| Started | Oct 14 09:05:36 PM UTC 24 |
| Finished | Oct 14 09:06:52 PM UTC 24 |
| Peak memory | 216676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3417613309 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.3417613309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/30.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_stress_all_with_error.3741954644 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 2375397880 ps |
| CPU time | 44.45 seconds |
| Started | Oct 14 09:05:38 PM UTC 24 |
| Finished | Oct 14 09:06:24 PM UTC 24 |
| Peak memory | 216748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3741954644 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.3741954644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/30.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_stress_all_with_rand_reset.3453266377 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 491572385 ps |
| CPU time | 136.14 seconds |
| Started | Oct 14 09:05:37 PM UTC 24 |
| Finished | Oct 14 09:07:56 PM UTC 24 |
| Peak memory | 218728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3453266377 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_rand_reset.3453266377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/30.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_stress_all_with_reset_error.40898115 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 1719763923 ps |
| CPU time | 159.34 seconds |
| Started | Oct 14 09:05:39 PM UTC 24 |
| Finished | Oct 14 09:08:22 PM UTC 24 |
| Peak memory | 220780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40898115 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_reset_error.40898115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/30.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/30.xbar_unmapped_addr.2297007705 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 150863192 ps |
| CPU time | 25.15 seconds |
| Started | Oct 14 09:05:30 PM UTC 24 |
| Finished | Oct 14 09:05:56 PM UTC 24 |
| Peak memory | 216672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2297007705 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.2297007705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/30.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_access_same_device.4153789424 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 429031649 ps |
| CPU time | 46.32 seconds |
| Started | Oct 14 09:05:55 PM UTC 24 |
| Finished | Oct 14 09:06:43 PM UTC 24 |
| Peak memory | 216680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4153789424 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device.4153789424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/31.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_access_same_device_slow_rsp.2521394546 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 26669501618 ps |
| CPU time | 221.58 seconds |
| Started | Oct 14 09:05:55 PM UTC 24 |
| Finished | Oct 14 09:09:40 PM UTC 24 |
| Peak memory | 216736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2521394546 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device_slow_rsp.2521394546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/31.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_error_and_unmapped_addr.2170512705 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 665366357 ps |
| CPU time | 31.11 seconds |
| Started | Oct 14 09:06:00 PM UTC 24 |
| Finished | Oct 14 09:06:32 PM UTC 24 |
| Peak memory | 214628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2170512705 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_addr.2170512705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/31.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_error_random.1760826042 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 1083629070 ps |
| CPU time | 27.51 seconds |
| Started | Oct 14 09:05:57 PM UTC 24 |
| Finished | Oct 14 09:06:26 PM UTC 24 |
| Peak memory | 214888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1760826042 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.1760826042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/31.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_random.3436190551 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 203046116 ps |
| CPU time | 5.8 seconds |
| Started | Oct 14 09:05:50 PM UTC 24 |
| Finished | Oct 14 09:05:57 PM UTC 24 |
| Peak memory | 214820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3436190551 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random.3436190551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/31.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_random_large_delays.1170448162 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 4397942135 ps |
| CPU time | 25.51 seconds |
| Started | Oct 14 09:05:52 PM UTC 24 |
| Finished | Oct 14 09:06:19 PM UTC 24 |
| Peak memory | 214696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1170448162 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.1170448162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/31.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_random_slow_rsp.2740913539 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 8667339502 ps |
| CPU time | 73.81 seconds |
| Started | Oct 14 09:05:55 PM UTC 24 |
| Finished | Oct 14 09:07:10 PM UTC 24 |
| Peak memory | 214696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2740913539 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.2740913539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/31.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_random_zero_delays.2278770001 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 66345475 ps |
| CPU time | 7.15 seconds |
| Started | Oct 14 09:05:51 PM UTC 24 |
| Finished | Oct 14 09:05:59 PM UTC 24 |
| Peak memory | 214620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2278770001 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_delays.2278770001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/31.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_same_source.1732289068 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 1015767054 ps |
| CPU time | 21.31 seconds |
| Started | Oct 14 09:05:57 PM UTC 24 |
| Finished | Oct 14 09:06:20 PM UTC 24 |
| Peak memory | 214632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1732289068 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.1732289068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/31.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_smoke.4178108359 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 27369613 ps |
| CPU time | 3.03 seconds |
| Started | Oct 14 09:05:41 PM UTC 24 |
| Finished | Oct 14 09:05:45 PM UTC 24 |
| Peak memory | 214844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4178108359 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.4178108359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/31.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_smoke_large_delays.891436543 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 14670283437 ps |
| CPU time | 37.76 seconds |
| Started | Oct 14 09:05:46 PM UTC 24 |
| Finished | Oct 14 09:06:25 PM UTC 24 |
| Peak memory | 214940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=891436543 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.891436543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/31.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_smoke_slow_rsp.3415670678 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 3611015955 ps |
| CPU time | 30.95 seconds |
| Started | Oct 14 09:05:48 PM UTC 24 |
| Finished | Oct 14 09:06:20 PM UTC 24 |
| Peak memory | 214652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3415670678 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.3415670678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/31.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_smoke_zero_delays.1744086146 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 35953135 ps |
| CPU time | 2.98 seconds |
| Started | Oct 14 09:05:44 PM UTC 24 |
| Finished | Oct 14 09:05:48 PM UTC 24 |
| Peak memory | 214600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1744086146 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delays.1744086146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/31.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_stress_all.971024910 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 3705758320 ps |
| CPU time | 68.44 seconds |
| Started | Oct 14 09:06:00 PM UTC 24 |
| Finished | Oct 14 09:07:10 PM UTC 24 |
| Peak memory | 216740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=971024910 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.971024910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/31.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_stress_all_with_error.2613647014 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 335345570 ps |
| CPU time | 28.16 seconds |
| Started | Oct 14 09:06:00 PM UTC 24 |
| Finished | Oct 14 09:06:29 PM UTC 24 |
| Peak memory | 216688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2613647014 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.2613647014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/31.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_stress_all_with_rand_reset.1146872000 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 356253426 ps |
| CPU time | 101.24 seconds |
| Started | Oct 14 09:06:00 PM UTC 24 |
| Finished | Oct 14 09:07:43 PM UTC 24 |
| Peak memory | 218916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1146872000 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_rand_reset.1146872000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/31.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/31.xbar_unmapped_addr.2525840061 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 112707918 ps |
| CPU time | 22.24 seconds |
| Started | Oct 14 09:05:57 PM UTC 24 |
| Finished | Oct 14 09:06:21 PM UTC 24 |
| Peak memory | 216932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2525840061 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.2525840061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/31.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_access_same_device.596109450 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 2987229749 ps |
| CPU time | 46.02 seconds |
| Started | Oct 14 09:06:11 PM UTC 24 |
| Finished | Oct 14 09:06:58 PM UTC 24 |
| Peak memory | 217004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=596109450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xba r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device.596109450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/32.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_access_same_device_slow_rsp.2458252694 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 52210639656 ps |
| CPU time | 266.04 seconds |
| Started | Oct 14 09:06:12 PM UTC 24 |
| Finished | Oct 14 09:10:42 PM UTC 24 |
| Peak memory | 216740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2458252694 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device_slow_rsp.2458252694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/32.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_error_and_unmapped_addr.433664625 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 1786527568 ps |
| CPU time | 31.28 seconds |
| Started | Oct 14 09:06:22 PM UTC 24 |
| Finished | Oct 14 09:06:55 PM UTC 24 |
| Peak memory | 214632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=433664625 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_addr.433664625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/32.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_error_random.4276222551 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 3344590255 ps |
| CPU time | 36.44 seconds |
| Started | Oct 14 09:06:20 PM UTC 24 |
| Finished | Oct 14 09:06:58 PM UTC 24 |
| Peak memory | 214688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4276222551 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.4276222551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/32.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_random.4124958886 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 4509890931 ps |
| CPU time | 31.93 seconds |
| Started | Oct 14 09:06:07 PM UTC 24 |
| Finished | Oct 14 09:06:40 PM UTC 24 |
| Peak memory | 216736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4124958886 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random.4124958886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/32.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_random_large_delays.1886909244 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 21609704196 ps |
| CPU time | 86.31 seconds |
| Started | Oct 14 09:06:07 PM UTC 24 |
| Finished | Oct 14 09:07:35 PM UTC 24 |
| Peak memory | 214700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1886909244 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.1886909244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/32.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_random_slow_rsp.2704823686 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 8944002414 ps |
| CPU time | 63.9 seconds |
| Started | Oct 14 09:06:09 PM UTC 24 |
| Finished | Oct 14 09:07:14 PM UTC 24 |
| Peak memory | 214692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2704823686 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.2704823686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/32.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_random_zero_delays.3735110276 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 386128225 ps |
| CPU time | 26.72 seconds |
| Started | Oct 14 09:06:07 PM UTC 24 |
| Finished | Oct 14 09:06:35 PM UTC 24 |
| Peak memory | 216668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3735110276 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_delays.3735110276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/32.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_same_source.2097254130 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 259744851 ps |
| CPU time | 20.48 seconds |
| Started | Oct 14 09:06:20 PM UTC 24 |
| Finished | Oct 14 09:06:41 PM UTC 24 |
| Peak memory | 214628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2097254130 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.2097254130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/32.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_smoke.3358874734 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 286589604 ps |
| CPU time | 5.68 seconds |
| Started | Oct 14 09:06:00 PM UTC 24 |
| Finished | Oct 14 09:06:07 PM UTC 24 |
| Peak memory | 214584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3358874734 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.3358874734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/32.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_smoke_large_delays.4136308789 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 8332411653 ps |
| CPU time | 32.87 seconds |
| Started | Oct 14 09:06:02 PM UTC 24 |
| Finished | Oct 14 09:06:36 PM UTC 24 |
| Peak memory | 214680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4136308789 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.4136308789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/32.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_smoke_slow_rsp.413921419 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 6287966174 ps |
| CPU time | 52.34 seconds |
| Started | Oct 14 09:06:02 PM UTC 24 |
| Finished | Oct 14 09:06:56 PM UTC 24 |
| Peak memory | 214648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=413921419 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.413921419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/32.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_smoke_zero_delays.2282036957 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 123165964 ps |
| CPU time | 2.36 seconds |
| Started | Oct 14 09:06:02 PM UTC 24 |
| Finished | Oct 14 09:06:05 PM UTC 24 |
| Peak memory | 214600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2282036957 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delays.2282036957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/32.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_stress_all.2329100662 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 780403712 ps |
| CPU time | 17.94 seconds |
| Started | Oct 14 09:06:22 PM UTC 24 |
| Finished | Oct 14 09:06:41 PM UTC 24 |
| Peak memory | 216672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2329100662 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.2329100662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/32.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_stress_all_with_error.3615270501 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 3408524820 ps |
| CPU time | 96.08 seconds |
| Started | Oct 14 09:06:22 PM UTC 24 |
| Finished | Oct 14 09:08:00 PM UTC 24 |
| Peak memory | 218800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3615270501 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.3615270501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/32.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_stress_all_with_reset_error.1587299809 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 10336658566 ps |
| CPU time | 352.99 seconds |
| Started | Oct 14 09:06:26 PM UTC 24 |
| Finished | Oct 14 09:12:24 PM UTC 24 |
| Peak memory | 231396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1587299809 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_reset_error.1587299809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/32.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/32.xbar_unmapped_addr.3442030263 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 722968154 ps |
| CPU time | 32.44 seconds |
| Started | Oct 14 09:06:22 PM UTC 24 |
| Finished | Oct 14 09:06:56 PM UTC 24 |
| Peak memory | 214632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3442030263 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.3442030263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/32.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_access_same_device.2548904884 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 362989786 ps |
| CPU time | 35.05 seconds |
| Started | Oct 14 09:06:36 PM UTC 24 |
| Finished | Oct 14 09:07:13 PM UTC 24 |
| Peak memory | 214632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2548904884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device.2548904884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/33.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_access_same_device_slow_rsp.3422546152 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 9107118210 ps |
| CPU time | 53.15 seconds |
| Started | Oct 14 09:06:38 PM UTC 24 |
| Finished | Oct 14 09:07:32 PM UTC 24 |
| Peak memory | 214884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3422546152 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device_slow_rsp.3422546152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/33.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_error_and_unmapped_addr.3585646010 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 833107598 ps |
| CPU time | 29.55 seconds |
| Started | Oct 14 09:06:40 PM UTC 24 |
| Finished | Oct 14 09:07:11 PM UTC 24 |
| Peak memory | 214628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3585646010 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_addr.3585646010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/33.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_error_random.14580798 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 167612543 ps |
| CPU time | 17.89 seconds |
| Started | Oct 14 09:06:38 PM UTC 24 |
| Finished | Oct 14 09:06:57 PM UTC 24 |
| Peak memory | 214628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=14580798 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.14580798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/33.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_random.4038104258 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 4287838061 ps |
| CPU time | 37.7 seconds |
| Started | Oct 14 09:06:31 PM UTC 24 |
| Finished | Oct 14 09:07:10 PM UTC 24 |
| Peak memory | 214888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4038104258 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random.4038104258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/33.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_random_large_delays.398787581 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 18590201386 ps |
| CPU time | 184.57 seconds |
| Started | Oct 14 09:06:34 PM UTC 24 |
| Finished | Oct 14 09:09:42 PM UTC 24 |
| Peak memory | 216928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=398787581 -assert nopostproc +UVM_ TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.398787581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/33.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_random_slow_rsp.1124031228 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 11288350211 ps |
| CPU time | 98.53 seconds |
| Started | Oct 14 09:06:34 PM UTC 24 |
| Finished | Oct 14 09:08:15 PM UTC 24 |
| Peak memory | 214692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1124031228 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.1124031228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/33.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_random_zero_delays.132904004 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 70004614 ps |
| CPU time | 5.06 seconds |
| Started | Oct 14 09:06:32 PM UTC 24 |
| Finished | Oct 14 09:06:38 PM UTC 24 |
| Peak memory | 214616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=132904004 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_delays.132904004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/33.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_same_source.963081024 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 4053169637 ps |
| CPU time | 30.19 seconds |
| Started | Oct 14 09:06:38 PM UTC 24 |
| Finished | Oct 14 09:07:09 PM UTC 24 |
| Peak memory | 214692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=963081024 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.963081024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/33.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_smoke.3261954784 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 49275659 ps |
| CPU time | 3.51 seconds |
| Started | Oct 14 09:06:26 PM UTC 24 |
| Finished | Oct 14 09:06:31 PM UTC 24 |
| Peak memory | 214584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3261954784 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.3261954784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/33.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_smoke_large_delays.3684995710 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 19427400334 ps |
| CPU time | 47.04 seconds |
| Started | Oct 14 09:06:28 PM UTC 24 |
| Finished | Oct 14 09:07:17 PM UTC 24 |
| Peak memory | 214936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3684995710 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.3684995710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/33.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_smoke_slow_rsp.2571330473 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 8871124289 ps |
| CPU time | 33.79 seconds |
| Started | Oct 14 09:06:31 PM UTC 24 |
| Finished | Oct 14 09:07:06 PM UTC 24 |
| Peak memory | 214652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2571330473 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.2571330473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/33.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_smoke_zero_delays.3511814504 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 26106423 ps |
| CPU time | 2.04 seconds |
| Started | Oct 14 09:06:26 PM UTC 24 |
| Finished | Oct 14 09:06:29 PM UTC 24 |
| Peak memory | 214600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3511814504 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delays.3511814504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/33.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_stress_all.136673919 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 1862351754 ps |
| CPU time | 62.03 seconds |
| Started | Oct 14 09:06:42 PM UTC 24 |
| Finished | Oct 14 09:07:47 PM UTC 24 |
| Peak memory | 216684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=136673919 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.136673919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/33.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_stress_all_with_error.1272077239 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 9565073234 ps |
| CPU time | 113.64 seconds |
| Started | Oct 14 09:06:42 PM UTC 24 |
| Finished | Oct 14 09:08:39 PM UTC 24 |
| Peak memory | 218800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1272077239 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.1272077239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/33.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_stress_all_with_rand_reset.4253675896 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 7155763 ps |
| CPU time | 10.55 seconds |
| Started | Oct 14 09:06:42 PM UTC 24 |
| Finished | Oct 14 09:06:55 PM UTC 24 |
| Peak memory | 214804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4253675896 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_rand_reset.4253675896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/33.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_stress_all_with_reset_error.555942017 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 1165871461 ps |
| CPU time | 196.09 seconds |
| Started | Oct 14 09:06:42 PM UTC 24 |
| Finished | Oct 14 09:10:02 PM UTC 24 |
| Peak memory | 221092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=555942017 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_reset_error.555942017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/33.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/33.xbar_unmapped_addr.2795813312 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 141105477 ps |
| CPU time | 14.52 seconds |
| Started | Oct 14 09:06:40 PM UTC 24 |
| Finished | Oct 14 09:06:56 PM UTC 24 |
| Peak memory | 214888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2795813312 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.2795813312 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/33.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_access_same_device.2796064010 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 118370372 ps |
| CPU time | 4.77 seconds |
| Started | Oct 14 09:06:56 PM UTC 24 |
| Finished | Oct 14 09:07:02 PM UTC 24 |
| Peak memory | 214632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2796064010 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device.2796064010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/34.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_access_same_device_slow_rsp.688522812 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 36106792684 ps |
| CPU time | 211.91 seconds |
| Started | Oct 14 09:06:59 PM UTC 24 |
| Finished | Oct 14 09:10:35 PM UTC 24 |
| Peak memory | 216744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=688522812 -assert nopostproc +UVM_TEST NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device_slow_rsp.688522812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/34.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_error_and_unmapped_addr.1537168703 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 195279750 ps |
| CPU time | 8.98 seconds |
| Started | Oct 14 09:06:59 PM UTC 24 |
| Finished | Oct 14 09:07:10 PM UTC 24 |
| Peak memory | 214628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1537168703 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_addr.1537168703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/34.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_error_random.1452723779 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 800981963 ps |
| CPU time | 26.09 seconds |
| Started | Oct 14 09:06:59 PM UTC 24 |
| Finished | Oct 14 09:07:27 PM UTC 24 |
| Peak memory | 214632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1452723779 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.1452723779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/34.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_random.246387067 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 1220356482 ps |
| CPU time | 31.32 seconds |
| Started | Oct 14 09:06:50 PM UTC 24 |
| Finished | Oct 14 09:07:23 PM UTC 24 |
| Peak memory | 214632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=246387067 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random.246387067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/34.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_random_large_delays.1854037965 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 22148527820 ps |
| CPU time | 85.35 seconds |
| Started | Oct 14 09:06:53 PM UTC 24 |
| Finished | Oct 14 09:08:20 PM UTC 24 |
| Peak memory | 214888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1854037965 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.1854037965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/34.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_random_slow_rsp.770741847 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 102221920285 ps |
| CPU time | 194.63 seconds |
| Started | Oct 14 09:06:56 PM UTC 24 |
| Finished | Oct 14 09:10:14 PM UTC 24 |
| Peak memory | 216744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=770741847 -assert nopostproc +UVM_TEST NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.770741847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/34.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_random_zero_delays.783440352 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 27290660 ps |
| CPU time | 4.47 seconds |
| Started | Oct 14 09:06:52 PM UTC 24 |
| Finished | Oct 14 09:06:58 PM UTC 24 |
| Peak memory | 214616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=783440352 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_delays.783440352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/34.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_same_source.3669025967 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 352354796 ps |
| CPU time | 11.81 seconds |
| Started | Oct 14 09:06:59 PM UTC 24 |
| Finished | Oct 14 09:07:12 PM UTC 24 |
| Peak memory | 214624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3669025967 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.3669025967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/34.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_smoke.978625704 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 310625232 ps |
| CPU time | 4.68 seconds |
| Started | Oct 14 09:06:44 PM UTC 24 |
| Finished | Oct 14 09:06:50 PM UTC 24 |
| Peak memory | 214608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=978625704 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.978625704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/34.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_smoke_large_delays.2725385090 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 6346775278 ps |
| CPU time | 39.24 seconds |
| Started | Oct 14 09:06:46 PM UTC 24 |
| Finished | Oct 14 09:07:26 PM UTC 24 |
| Peak memory | 214680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2725385090 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.2725385090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/34.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_smoke_slow_rsp.2487616158 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 5019091899 ps |
| CPU time | 40.58 seconds |
| Started | Oct 14 09:06:49 PM UTC 24 |
| Finished | Oct 14 09:07:31 PM UTC 24 |
| Peak memory | 214652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2487616158 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.2487616158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/34.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_smoke_zero_delays.3251596852 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 28016221 ps |
| CPU time | 3.01 seconds |
| Started | Oct 14 09:06:44 PM UTC 24 |
| Finished | Oct 14 09:06:48 PM UTC 24 |
| Peak memory | 214600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3251596852 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delays.3251596852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/34.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_stress_all.2070375424 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 3638791626 ps |
| CPU time | 111.37 seconds |
| Started | Oct 14 09:07:03 PM UTC 24 |
| Finished | Oct 14 09:08:56 PM UTC 24 |
| Peak memory | 218984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2070375424 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.2070375424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/34.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_stress_all_with_error.2833904126 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 1232382899 ps |
| CPU time | 107.85 seconds |
| Started | Oct 14 09:07:03 PM UTC 24 |
| Finished | Oct 14 09:08:53 PM UTC 24 |
| Peak memory | 216688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2833904126 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.2833904126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/34.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_stress_all_with_rand_reset.3634550933 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 503569414 ps |
| CPU time | 245.62 seconds |
| Started | Oct 14 09:07:03 PM UTC 24 |
| Finished | Oct 14 09:11:12 PM UTC 24 |
| Peak memory | 218724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3634550933 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_rand_reset.3634550933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/34.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_stress_all_with_reset_error.2457536705 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 523815686 ps |
| CPU time | 85.62 seconds |
| Started | Oct 14 09:07:03 PM UTC 24 |
| Finished | Oct 14 09:08:30 PM UTC 24 |
| Peak memory | 220776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2457536705 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_reset_error.2457536705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/34.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/34.xbar_unmapped_addr.2938738726 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 223232343 ps |
| CPU time | 6.52 seconds |
| Started | Oct 14 09:06:59 PM UTC 24 |
| Finished | Oct 14 09:07:07 PM UTC 24 |
| Peak memory | 214624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2938738726 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.2938738726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/34.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_access_same_device.1774327167 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 501614630 ps |
| CPU time | 15.31 seconds |
| Started | Oct 14 09:07:11 PM UTC 24 |
| Finished | Oct 14 09:07:28 PM UTC 24 |
| Peak memory | 214828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1774327167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device.1774327167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/35.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_access_same_device_slow_rsp.3885192591 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 24454109106 ps |
| CPU time | 158.81 seconds |
| Started | Oct 14 09:07:11 PM UTC 24 |
| Finished | Oct 14 09:09:53 PM UTC 24 |
| Peak memory | 216740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3885192591 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device_slow_rsp.3885192591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/35.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_error_and_unmapped_addr.1365824532 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 97018077 ps |
| CPU time | 15.85 seconds |
| Started | Oct 14 09:07:14 PM UTC 24 |
| Finished | Oct 14 09:07:32 PM UTC 24 |
| Peak memory | 214628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1365824532 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_addr.1365824532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/35.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_error_random.2559170049 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 560869407 ps |
| CPU time | 19.93 seconds |
| Started | Oct 14 09:07:13 PM UTC 24 |
| Finished | Oct 14 09:07:34 PM UTC 24 |
| Peak memory | 214600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2559170049 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.2559170049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/35.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_random.2053742472 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 192040446 ps |
| CPU time | 9.75 seconds |
| Started | Oct 14 09:07:09 PM UTC 24 |
| Finished | Oct 14 09:07:20 PM UTC 24 |
| Peak memory | 214628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2053742472 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random.2053742472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/35.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_random_large_delays.2848431600 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 33029051549 ps |
| CPU time | 70.36 seconds |
| Started | Oct 14 09:07:11 PM UTC 24 |
| Finished | Oct 14 09:08:23 PM UTC 24 |
| Peak memory | 214692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2848431600 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.2848431600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/35.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_random_slow_rsp.2867981681 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 4416831248 ps |
| CPU time | 14.42 seconds |
| Started | Oct 14 09:07:11 PM UTC 24 |
| Finished | Oct 14 09:07:27 PM UTC 24 |
| Peak memory | 214668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2867981681 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.2867981681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/35.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_random_zero_delays.4007028810 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 32025069 ps |
| CPU time | 7.63 seconds |
| Started | Oct 14 09:07:11 PM UTC 24 |
| Finished | Oct 14 09:07:20 PM UTC 24 |
| Peak memory | 214876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4007028810 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_delays.4007028810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/35.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_same_source.2928808505 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 252616995 ps |
| CPU time | 7.24 seconds |
| Started | Oct 14 09:07:13 PM UTC 24 |
| Finished | Oct 14 09:07:21 PM UTC 24 |
| Peak memory | 214616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2928808505 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.2928808505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/35.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_smoke.9251089 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 330389985 ps |
| CPU time | 5.8 seconds |
| Started | Oct 14 09:07:03 PM UTC 24 |
| Finished | Oct 14 09:07:10 PM UTC 24 |
| Peak memory | 214608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9251089 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_T EST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/ coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.9251089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/35.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_smoke_large_delays.108313584 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 6304536125 ps |
| CPU time | 66.06 seconds |
| Started | Oct 14 09:07:08 PM UTC 24 |
| Finished | Oct 14 09:08:16 PM UTC 24 |
| Peak memory | 214316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=108313584 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.108313584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/35.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_smoke_slow_rsp.2277504629 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 3430410182 ps |
| CPU time | 31.76 seconds |
| Started | Oct 14 09:07:08 PM UTC 24 |
| Finished | Oct 14 09:07:41 PM UTC 24 |
| Peak memory | 214504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2277504629 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.2277504629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/35.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_smoke_zero_delays.926526470 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 30415843 ps |
| CPU time | 2.37 seconds |
| Started | Oct 14 09:07:04 PM UTC 24 |
| Finished | Oct 14 09:07:08 PM UTC 24 |
| Peak memory | 214608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=926526470 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/x bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delays.926526470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/35.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all.3181812276 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 8902300449 ps |
| CPU time | 163.11 seconds |
| Started | Oct 14 09:07:16 PM UTC 24 |
| Finished | Oct 14 09:10:02 PM UTC 24 |
| Peak memory | 218788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3181812276 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.3181812276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/35.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all_with_error.730553706 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 40474559 ps |
| CPU time | 6.26 seconds |
| Started | Oct 14 09:07:19 PM UTC 24 |
| Finished | Oct 14 09:07:26 PM UTC 24 |
| Peak memory | 214632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=730553706 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.730553706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/35.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all_with_rand_reset.2964243987 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 53707566 ps |
| CPU time | 36.42 seconds |
| Started | Oct 14 09:07:17 PM UTC 24 |
| Finished | Oct 14 09:07:55 PM UTC 24 |
| Peak memory | 216676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2964243987 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_rand_reset.2964243987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/35.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all_with_reset_error.2536098097 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 1214844399 ps |
| CPU time | 182.18 seconds |
| Started | Oct 14 09:07:20 PM UTC 24 |
| Finished | Oct 14 09:10:26 PM UTC 24 |
| Peak memory | 231332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2536098097 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_reset_error.2536098097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/35.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/35.xbar_unmapped_addr.3668693863 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 405927874 ps |
| CPU time | 13.77 seconds |
| Started | Oct 14 09:07:13 PM UTC 24 |
| Finished | Oct 14 09:07:28 PM UTC 24 |
| Peak memory | 214628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3668693863 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.3668693863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/35.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_access_same_device.2768225486 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 5527905554 ps |
| CPU time | 69.47 seconds |
| Started | Oct 14 09:07:29 PM UTC 24 |
| Finished | Oct 14 09:08:40 PM UTC 24 |
| Peak memory | 216744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2768225486 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device.2768225486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/36.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_access_same_device_slow_rsp.3442910666 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 8828498704 ps |
| CPU time | 36.18 seconds |
| Started | Oct 14 09:07:29 PM UTC 24 |
| Finished | Oct 14 09:08:07 PM UTC 24 |
| Peak memory | 214692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3442910666 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device_slow_rsp.3442910666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/36.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_error_and_unmapped_addr.857152478 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 97798121 ps |
| CPU time | 3.32 seconds |
| Started | Oct 14 09:07:32 PM UTC 24 |
| Finished | Oct 14 09:07:37 PM UTC 24 |
| Peak memory | 214628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=857152478 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_addr.857152478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/36.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_error_random.698602871 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 520553403 ps |
| CPU time | 13.03 seconds |
| Started | Oct 14 09:07:29 PM UTC 24 |
| Finished | Oct 14 09:07:44 PM UTC 24 |
| Peak memory | 214628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=698602871 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.698602871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/36.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_random.3109009463 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 1889678433 ps |
| CPU time | 20 seconds |
| Started | Oct 14 09:07:27 PM UTC 24 |
| Finished | Oct 14 09:07:49 PM UTC 24 |
| Peak memory | 216936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3109009463 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random.3109009463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/36.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_random_large_delays.442146917 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 16878627594 ps |
| CPU time | 115.44 seconds |
| Started | Oct 14 09:07:29 PM UTC 24 |
| Finished | Oct 14 09:09:27 PM UTC 24 |
| Peak memory | 214616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=442146917 -assert nopostproc +UVM_ TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.442146917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/36.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_random_slow_rsp.1284484523 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 7455206941 ps |
| CPU time | 72.48 seconds |
| Started | Oct 14 09:07:29 PM UTC 24 |
| Finished | Oct 14 09:08:43 PM UTC 24 |
| Peak memory | 216740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1284484523 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.1284484523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/36.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_random_zero_delays.1666536110 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 64107547 ps |
| CPU time | 9.58 seconds |
| Started | Oct 14 09:07:27 PM UTC 24 |
| Finished | Oct 14 09:07:38 PM UTC 24 |
| Peak memory | 214616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1666536110 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_delays.1666536110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/36.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_same_source.3959203154 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 1402643766 ps |
| CPU time | 20.69 seconds |
| Started | Oct 14 09:07:29 PM UTC 24 |
| Finished | Oct 14 09:07:51 PM UTC 24 |
| Peak memory | 214628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3959203154 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.3959203154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/36.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_smoke.746047862 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 163475167 ps |
| CPU time | 4.01 seconds |
| Started | Oct 14 09:07:22 PM UTC 24 |
| Finished | Oct 14 09:07:27 PM UTC 24 |
| Peak memory | 214608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=746047862 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.746047862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/36.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_smoke_large_delays.690188578 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 5768426276 ps |
| CPU time | 34.71 seconds |
| Started | Oct 14 09:07:22 PM UTC 24 |
| Finished | Oct 14 09:07:58 PM UTC 24 |
| Peak memory | 214680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=690188578 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.690188578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/36.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_smoke_slow_rsp.866365817 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 4638275558 ps |
| CPU time | 24.58 seconds |
| Started | Oct 14 09:07:24 PM UTC 24 |
| Finished | Oct 14 09:07:50 PM UTC 24 |
| Peak memory | 214844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=866365817 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.866365817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/36.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_smoke_zero_delays.4013859490 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 30865117 ps |
| CPU time | 2.52 seconds |
| Started | Oct 14 09:07:22 PM UTC 24 |
| Finished | Oct 14 09:07:26 PM UTC 24 |
| Peak memory | 214792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4013859490 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delays.4013859490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/36.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all.978348222 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 8782380756 ps |
| CPU time | 291.47 seconds |
| Started | Oct 14 09:07:32 PM UTC 24 |
| Finished | Oct 14 09:12:28 PM UTC 24 |
| Peak memory | 221148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=978348222 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.978348222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/36.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all_with_error.1768812216 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 2336142896 ps |
| CPU time | 92.3 seconds |
| Started | Oct 14 09:07:35 PM UTC 24 |
| Finished | Oct 14 09:09:10 PM UTC 24 |
| Peak memory | 216748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1768812216 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.1768812216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/36.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all_with_rand_reset.385709412 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 11252533790 ps |
| CPU time | 379.33 seconds |
| Started | Oct 14 09:07:34 PM UTC 24 |
| Finished | Oct 14 09:13:58 PM UTC 24 |
| Peak memory | 232908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=385709412 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_rand_reset.385709412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/36.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all_with_reset_error.3166403500 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 6440966048 ps |
| CPU time | 423.64 seconds |
| Started | Oct 14 09:07:37 PM UTC 24 |
| Finished | Oct 14 09:14:46 PM UTC 24 |
| Peak memory | 231740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3166403500 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_reset_error.3166403500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/36.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/36.xbar_unmapped_addr.1731268155 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 54859456 ps |
| CPU time | 9.98 seconds |
| Started | Oct 14 09:07:32 PM UTC 24 |
| Finished | Oct 14 09:07:43 PM UTC 24 |
| Peak memory | 216868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1731268155 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.1731268155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/36.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_access_same_device.1415536109 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 481227634 ps |
| CPU time | 43.13 seconds |
| Started | Oct 14 09:07:46 PM UTC 24 |
| Finished | Oct 14 09:08:31 PM UTC 24 |
| Peak memory | 216876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1415536109 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device.1415536109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/37.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_access_same_device_slow_rsp.3460424043 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 35211225132 ps |
| CPU time | 350.36 seconds |
| Started | Oct 14 09:07:46 PM UTC 24 |
| Finished | Oct 14 09:13:41 PM UTC 24 |
| Peak memory | 216740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3460424043 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device_slow_rsp.3460424043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/37.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_error_and_unmapped_addr.316151560 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 2241125772 ps |
| CPU time | 19.2 seconds |
| Started | Oct 14 09:07:52 PM UTC 24 |
| Finished | Oct 14 09:08:12 PM UTC 24 |
| Peak memory | 214696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=316151560 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_addr.316151560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/37.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_error_random.1740390617 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 119617893 ps |
| CPU time | 2.09 seconds |
| Started | Oct 14 09:07:49 PM UTC 24 |
| Finished | Oct 14 09:07:52 PM UTC 24 |
| Peak memory | 214600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1740390617 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.1740390617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/37.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_random.480398495 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 312175380 ps |
| CPU time | 14.75 seconds |
| Started | Oct 14 09:07:43 PM UTC 24 |
| Finished | Oct 14 09:07:59 PM UTC 24 |
| Peak memory | 214632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=480398495 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random.480398495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/37.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_random_large_delays.2416628501 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 20516750262 ps |
| CPU time | 120.99 seconds |
| Started | Oct 14 09:07:46 PM UTC 24 |
| Finished | Oct 14 09:09:49 PM UTC 24 |
| Peak memory | 214692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2416628501 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.2416628501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/37.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_random_slow_rsp.2487052121 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 9392878021 ps |
| CPU time | 68.45 seconds |
| Started | Oct 14 09:07:46 PM UTC 24 |
| Finished | Oct 14 09:08:56 PM UTC 24 |
| Peak memory | 214888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2487052121 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.2487052121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/37.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_random_zero_delays.91507564 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 699741252 ps |
| CPU time | 24.89 seconds |
| Started | Oct 14 09:07:46 PM UTC 24 |
| Finished | Oct 14 09:08:12 PM UTC 24 |
| Peak memory | 216676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=91507564 -assert nopostproc +UVM_TESTNAME=xbar_ base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/x bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_delays.91507564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/37.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_same_source.1789388329 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 324263310 ps |
| CPU time | 6.64 seconds |
| Started | Oct 14 09:07:48 PM UTC 24 |
| Finished | Oct 14 09:07:55 PM UTC 24 |
| Peak memory | 214620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1789388329 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.1789388329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/37.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_smoke.44581401 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 111287328 ps |
| CPU time | 4.29 seconds |
| Started | Oct 14 09:07:38 PM UTC 24 |
| Finished | Oct 14 09:07:43 PM UTC 24 |
| Peak memory | 214864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=44581401 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs /coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.44581401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/37.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_smoke_large_delays.1708636124 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 5112887969 ps |
| CPU time | 41.26 seconds |
| Started | Oct 14 09:07:41 PM UTC 24 |
| Finished | Oct 14 09:08:23 PM UTC 24 |
| Peak memory | 214680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1708636124 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.1708636124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/37.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_smoke_slow_rsp.2665986606 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 4339474366 ps |
| CPU time | 40.68 seconds |
| Started | Oct 14 09:07:42 PM UTC 24 |
| Finished | Oct 14 09:08:24 PM UTC 24 |
| Peak memory | 214656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2665986606 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.2665986606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/37.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_smoke_zero_delays.197555726 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 30887465 ps |
| CPU time | 3.31 seconds |
| Started | Oct 14 09:07:39 PM UTC 24 |
| Finished | Oct 14 09:07:44 PM UTC 24 |
| Peak memory | 214608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=197555726 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/x bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delays.197555726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/37.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all.1178798205 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 486358872 ps |
| CPU time | 35.25 seconds |
| Started | Oct 14 09:07:52 PM UTC 24 |
| Finished | Oct 14 09:08:29 PM UTC 24 |
| Peak memory | 216676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1178798205 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.1178798205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/37.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all_with_error.3679937671 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 1208873390 ps |
| CPU time | 37.38 seconds |
| Started | Oct 14 09:07:54 PM UTC 24 |
| Finished | Oct 14 09:08:33 PM UTC 24 |
| Peak memory | 214640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3679937671 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.3679937671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/37.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all_with_rand_reset.2838613457 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 304874437 ps |
| CPU time | 32.9 seconds |
| Started | Oct 14 09:07:54 PM UTC 24 |
| Finished | Oct 14 09:08:28 PM UTC 24 |
| Peak memory | 216676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2838613457 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_rand_reset.2838613457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/37.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all_with_reset_error.3031537943 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 202714295 ps |
| CPU time | 73.86 seconds |
| Started | Oct 14 09:07:56 PM UTC 24 |
| Finished | Oct 14 09:09:12 PM UTC 24 |
| Peak memory | 218732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3031537943 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_reset_error.3031537943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/37.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/37.xbar_unmapped_addr.2451537390 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 74475210 ps |
| CPU time | 6.61 seconds |
| Started | Oct 14 09:07:49 PM UTC 24 |
| Finished | Oct 14 09:07:57 PM UTC 24 |
| Peak memory | 216868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2451537390 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.2451537390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/37.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_access_same_device.3772187607 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 559624982 ps |
| CPU time | 48.84 seconds |
| Started | Oct 14 09:08:08 PM UTC 24 |
| Finished | Oct 14 09:08:59 PM UTC 24 |
| Peak memory | 218728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3772187607 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device.3772187607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/38.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.3621403623 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 31444268115 ps |
| CPU time | 222.45 seconds |
| Started | Oct 14 09:08:14 PM UTC 24 |
| Finished | Oct 14 09:12:00 PM UTC 24 |
| Peak memory | 216740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3621403623 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device_slow_rsp.3621403623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/38.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_error_and_unmapped_addr.3042028098 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 93081579 ps |
| CPU time | 14.89 seconds |
| Started | Oct 14 09:08:17 PM UTC 24 |
| Finished | Oct 14 09:08:34 PM UTC 24 |
| Peak memory | 214628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3042028098 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_addr.3042028098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/38.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_error_random.629877464 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 39636360 ps |
| CPU time | 5.66 seconds |
| Started | Oct 14 09:08:15 PM UTC 24 |
| Finished | Oct 14 09:08:22 PM UTC 24 |
| Peak memory | 214592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=629877464 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.629877464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/38.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_random.173465400 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 211144996 ps |
| CPU time | 23.24 seconds |
| Started | Oct 14 09:08:01 PM UTC 24 |
| Finished | Oct 14 09:08:25 PM UTC 24 |
| Peak memory | 214632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=173465400 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random.173465400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/38.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_random_large_delays.1748733249 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 11543872564 ps |
| CPU time | 74.33 seconds |
| Started | Oct 14 09:08:03 PM UTC 24 |
| Finished | Oct 14 09:09:19 PM UTC 24 |
| Peak memory | 214692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1748733249 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.1748733249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/38.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_random_slow_rsp.2981976309 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 12640309060 ps |
| CPU time | 90.51 seconds |
| Started | Oct 14 09:08:05 PM UTC 24 |
| Finished | Oct 14 09:09:37 PM UTC 24 |
| Peak memory | 214692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2981976309 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.2981976309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/38.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_random_zero_delays.2157462298 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 325821045 ps |
| CPU time | 23.31 seconds |
| Started | Oct 14 09:08:02 PM UTC 24 |
| Finished | Oct 14 09:08:27 PM UTC 24 |
| Peak memory | 214616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2157462298 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_delays.2157462298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/38.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_same_source.2498835976 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 3892206640 ps |
| CPU time | 30.23 seconds |
| Started | Oct 14 09:08:14 PM UTC 24 |
| Finished | Oct 14 09:08:46 PM UTC 24 |
| Peak memory | 214692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2498835976 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.2498835976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/38.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_smoke.1978275266 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 205650280 ps |
| CPU time | 5.3 seconds |
| Started | Oct 14 09:07:57 PM UTC 24 |
| Finished | Oct 14 09:08:03 PM UTC 24 |
| Peak memory | 214584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1978275266 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.1978275266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/38.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_smoke_large_delays.3301122894 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 4342279434 ps |
| CPU time | 38.48 seconds |
| Started | Oct 14 09:07:58 PM UTC 24 |
| Finished | Oct 14 09:08:38 PM UTC 24 |
| Peak memory | 214680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3301122894 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.3301122894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/38.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_smoke_slow_rsp.4005777228 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 14500403512 ps |
| CPU time | 42.6 seconds |
| Started | Oct 14 09:07:59 PM UTC 24 |
| Finished | Oct 14 09:08:43 PM UTC 24 |
| Peak memory | 214656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4005777228 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.4005777228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/38.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_smoke_zero_delays.1172305852 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 113434159 ps |
| CPU time | 3.41 seconds |
| Started | Oct 14 09:07:58 PM UTC 24 |
| Finished | Oct 14 09:08:03 PM UTC 24 |
| Peak memory | 214600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1172305852 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delays.1172305852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/38.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all.3035443228 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 1361190679 ps |
| CPU time | 131.02 seconds |
| Started | Oct 14 09:08:18 PM UTC 24 |
| Finished | Oct 14 09:10:31 PM UTC 24 |
| Peak memory | 218728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3035443228 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.3035443228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/38.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all_with_error.1601966159 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 3434956780 ps |
| CPU time | 124.23 seconds |
| Started | Oct 14 09:08:22 PM UTC 24 |
| Finished | Oct 14 09:10:28 PM UTC 24 |
| Peak memory | 216752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1601966159 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.1601966159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/38.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all_with_rand_reset.3134827710 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 182161697 ps |
| CPU time | 65.73 seconds |
| Started | Oct 14 09:08:19 PM UTC 24 |
| Finished | Oct 14 09:09:27 PM UTC 24 |
| Peak memory | 218916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3134827710 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_rand_reset.3134827710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/38.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all_with_reset_error.1945713378 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 4074489551 ps |
| CPU time | 194.42 seconds |
| Started | Oct 14 09:08:23 PM UTC 24 |
| Finished | Oct 14 09:11:41 PM UTC 24 |
| Peak memory | 220844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1945713378 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_reset_error.1945713378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/38.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/38.xbar_unmapped_addr.1237777133 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 1478399811 ps |
| CPU time | 31.04 seconds |
| Started | Oct 14 09:08:17 PM UTC 24 |
| Finished | Oct 14 09:08:50 PM UTC 24 |
| Peak memory | 214624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1237777133 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.1237777133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/38.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_access_same_device.2468940863 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 714946050 ps |
| CPU time | 15.29 seconds |
| Started | Oct 14 09:08:30 PM UTC 24 |
| Finished | Oct 14 09:08:47 PM UTC 24 |
| Peak memory | 214832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2468940863 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device.2468940863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/39.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_access_same_device_slow_rsp.1119110416 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 42768584373 ps |
| CPU time | 380.53 seconds |
| Started | Oct 14 09:08:31 PM UTC 24 |
| Finished | Oct 14 09:14:57 PM UTC 24 |
| Peak memory | 216744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1119110416 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device_slow_rsp.1119110416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/39.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_error_and_unmapped_addr.2476239010 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 1180061785 ps |
| CPU time | 12.8 seconds |
| Started | Oct 14 09:08:34 PM UTC 24 |
| Finished | Oct 14 09:08:48 PM UTC 24 |
| Peak memory | 214632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2476239010 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_addr.2476239010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/39.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_error_random.441934018 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 554975791 ps |
| CPU time | 23.19 seconds |
| Started | Oct 14 09:08:33 PM UTC 24 |
| Finished | Oct 14 09:08:57 PM UTC 24 |
| Peak memory | 214620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=441934018 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.441934018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/39.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_random.2281449455 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 977044552 ps |
| CPU time | 25.07 seconds |
| Started | Oct 14 09:08:27 PM UTC 24 |
| Finished | Oct 14 09:08:53 PM UTC 24 |
| Peak memory | 216808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2281449455 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random.2281449455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/39.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_random_large_delays.2867421897 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 48390319882 ps |
| CPU time | 87.63 seconds |
| Started | Oct 14 09:08:28 PM UTC 24 |
| Finished | Oct 14 09:09:58 PM UTC 24 |
| Peak memory | 214696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2867421897 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.2867421897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/39.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_random_slow_rsp.4182041923 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 20058573803 ps |
| CPU time | 91.79 seconds |
| Started | Oct 14 09:08:30 PM UTC 24 |
| Finished | Oct 14 09:10:04 PM UTC 24 |
| Peak memory | 217000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4182041923 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.4182041923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/39.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_random_zero_delays.3717328604 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 289682996 ps |
| CPU time | 19.31 seconds |
| Started | Oct 14 09:08:27 PM UTC 24 |
| Finished | Oct 14 09:08:47 PM UTC 24 |
| Peak memory | 216736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3717328604 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_delays.3717328604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/39.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_same_source.1844352643 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 49912656 ps |
| CPU time | 4.38 seconds |
| Started | Oct 14 09:08:32 PM UTC 24 |
| Finished | Oct 14 09:08:38 PM UTC 24 |
| Peak memory | 214624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1844352643 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.1844352643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/39.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_smoke.4219100520 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 160800901 ps |
| CPU time | 4.76 seconds |
| Started | Oct 14 09:08:24 PM UTC 24 |
| Finished | Oct 14 09:08:29 PM UTC 24 |
| Peak memory | 214588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4219100520 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.4219100520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/39.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_smoke_large_delays.884814631 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 4623060835 ps |
| CPU time | 29.2 seconds |
| Started | Oct 14 09:08:27 PM UTC 24 |
| Finished | Oct 14 09:08:57 PM UTC 24 |
| Peak memory | 214680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=884814631 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.884814631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/39.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_smoke_slow_rsp.1473076568 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 6931940649 ps |
| CPU time | 27.62 seconds |
| Started | Oct 14 09:08:27 PM UTC 24 |
| Finished | Oct 14 09:08:56 PM UTC 24 |
| Peak memory | 214656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1473076568 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.1473076568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/39.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_smoke_zero_delays.383330043 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 30799940 ps |
| CPU time | 3.18 seconds |
| Started | Oct 14 09:08:26 PM UTC 24 |
| Finished | Oct 14 09:08:31 PM UTC 24 |
| Peak memory | 214868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=383330043 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/x bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delays.383330043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/39.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all.2283151947 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 1061544498 ps |
| CPU time | 23.44 seconds |
| Started | Oct 14 09:08:34 PM UTC 24 |
| Finished | Oct 14 09:08:59 PM UTC 24 |
| Peak memory | 216680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2283151947 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.2283151947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/39.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all_with_error.1234028356 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 6144947857 ps |
| CPU time | 52.02 seconds |
| Started | Oct 14 09:08:40 PM UTC 24 |
| Finished | Oct 14 09:09:34 PM UTC 24 |
| Peak memory | 217008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1234028356 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.1234028356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/39.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all_with_rand_reset.447908647 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 239870328 ps |
| CPU time | 128.11 seconds |
| Started | Oct 14 09:08:40 PM UTC 24 |
| Finished | Oct 14 09:10:51 PM UTC 24 |
| Peak memory | 218720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=447908647 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_rand_reset.447908647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/39.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all_with_reset_error.2672720183 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 341016502 ps |
| CPU time | 104.54 seconds |
| Started | Oct 14 09:08:40 PM UTC 24 |
| Finished | Oct 14 09:10:27 PM UTC 24 |
| Peak memory | 220976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2672720183 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_reset_error.2672720183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/39.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/39.xbar_unmapped_addr.3896631761 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 280750841 ps |
| CPU time | 10.61 seconds |
| Started | Oct 14 09:08:33 PM UTC 24 |
| Finished | Oct 14 09:08:45 PM UTC 24 |
| Peak memory | 216676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3896631761 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.3896631761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/39.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_access_same_device.549725480 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 59916624 ps |
| CPU time | 5.71 seconds |
| Started | Oct 14 08:56:59 PM UTC 24 |
| Finished | Oct 14 08:57:07 PM UTC 24 |
| Peak memory | 214624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=549725480 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xba r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device.549725480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/4.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_access_same_device_slow_rsp.1810043254 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 6252873460 ps |
| CPU time | 64.86 seconds |
| Started | Oct 14 08:56:59 PM UTC 24 |
| Finished | Oct 14 08:58:06 PM UTC 24 |
| Peak memory | 214696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1810043254 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device_slow_rsp.1810043254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/4.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_error_and_unmapped_addr.2683182364 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 47942080 ps |
| CPU time | 2.24 seconds |
| Started | Oct 14 08:57:02 PM UTC 24 |
| Finished | Oct 14 08:57:05 PM UTC 24 |
| Peak memory | 214632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2683182364 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr.2683182364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/4.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_error_random.1377797673 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 4976782457 ps |
| CPU time | 37.95 seconds |
| Started | Oct 14 08:57:02 PM UTC 24 |
| Finished | Oct 14 08:57:41 PM UTC 24 |
| Peak memory | 214688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1377797673 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.1377797673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/4.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_random.624781888 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 105579450 ps |
| CPU time | 7.18 seconds |
| Started | Oct 14 08:56:55 PM UTC 24 |
| Finished | Oct 14 08:57:10 PM UTC 24 |
| Peak memory | 214628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=624781888 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random.624781888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/4.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_random_large_delays.3889568246 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 54678628629 ps |
| CPU time | 122.99 seconds |
| Started | Oct 14 08:56:57 PM UTC 24 |
| Finished | Oct 14 08:59:06 PM UTC 24 |
| Peak memory | 214700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3889568246 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.3889568246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/4.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_random_slow_rsp.3481664826 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 12591836690 ps |
| CPU time | 89.81 seconds |
| Started | Oct 14 08:56:57 PM UTC 24 |
| Finished | Oct 14 08:58:32 PM UTC 24 |
| Peak memory | 216740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3481664826 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.3481664826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/4.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_random_zero_delays.675360344 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 416497029 ps |
| CPU time | 24.21 seconds |
| Started | Oct 14 08:56:57 PM UTC 24 |
| Finished | Oct 14 08:57:26 PM UTC 24 |
| Peak memory | 214752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=675360344 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_delays.675360344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/4.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_same_source.3754273897 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 212568217 ps |
| CPU time | 10.32 seconds |
| Started | Oct 14 08:56:59 PM UTC 24 |
| Finished | Oct 14 08:57:11 PM UTC 24 |
| Peak memory | 214632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3754273897 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.3754273897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/4.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_smoke.848570668 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 34328947 ps |
| CPU time | 2.78 seconds |
| Started | Oct 14 08:56:53 PM UTC 24 |
| Finished | Oct 14 08:57:04 PM UTC 24 |
| Peak memory | 214608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=848570668 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.848570668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/4.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_smoke_large_delays.793993691 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 4905488340 ps |
| CPU time | 36.79 seconds |
| Started | Oct 14 08:56:53 PM UTC 24 |
| Finished | Oct 14 08:57:38 PM UTC 24 |
| Peak memory | 214680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=793993691 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.793993691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/4.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_smoke_slow_rsp.2284863832 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 4241979089 ps |
| CPU time | 41.58 seconds |
| Started | Oct 14 08:56:55 PM UTC 24 |
| Finished | Oct 14 08:57:45 PM UTC 24 |
| Peak memory | 214656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2284863832 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.2284863832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/4.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_smoke_zero_delays.1058898999 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 27923138 ps |
| CPU time | 2.51 seconds |
| Started | Oct 14 08:56:53 PM UTC 24 |
| Finished | Oct 14 08:57:03 PM UTC 24 |
| Peak memory | 214604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1058898999 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays.1058898999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/4.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_stress_all.2696591551 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 3163012894 ps |
| CPU time | 172.55 seconds |
| Started | Oct 14 08:57:04 PM UTC 24 |
| Finished | Oct 14 09:00:00 PM UTC 24 |
| Peak memory | 218796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2696591551 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.2696591551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/4.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_stress_all_with_rand_reset.518128765 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 3956670281 ps |
| CPU time | 433.37 seconds |
| Started | Oct 14 08:57:05 PM UTC 24 |
| Finished | Oct 14 09:04:24 PM UTC 24 |
| Peak memory | 231716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=518128765 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_rand_reset.518128765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/4.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_stress_all_with_reset_error.2748474737 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 465336709 ps |
| CPU time | 219.62 seconds |
| Started | Oct 14 08:57:05 PM UTC 24 |
| Finished | Oct 14 09:00:49 PM UTC 24 |
| Peak memory | 221092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2748474737 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_reset_error.2748474737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/4.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/4.xbar_unmapped_addr.3020097229 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 551914186 ps |
| CPU time | 23.35 seconds |
| Started | Oct 14 08:57:02 PM UTC 24 |
| Finished | Oct 14 08:57:26 PM UTC 24 |
| Peak memory | 214632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3020097229 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.3020097229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/4.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_access_same_device.508562049 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 548067174 ps |
| CPU time | 45.67 seconds |
| Started | Oct 14 09:08:50 PM UTC 24 |
| Finished | Oct 14 09:09:38 PM UTC 24 |
| Peak memory | 218724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=508562049 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xba r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device.508562049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/40.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_access_same_device_slow_rsp.2572883765 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 35927758438 ps |
| CPU time | 243.02 seconds |
| Started | Oct 14 09:08:50 PM UTC 24 |
| Finished | Oct 14 09:12:57 PM UTC 24 |
| Peak memory | 216936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2572883765 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device_slow_rsp.2572883765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/40.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_error_and_unmapped_addr.903104466 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 91466563 ps |
| CPU time | 11.28 seconds |
| Started | Oct 14 09:08:57 PM UTC 24 |
| Finished | Oct 14 09:09:09 PM UTC 24 |
| Peak memory | 214632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=903104466 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_addr.903104466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/40.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_error_random.2907996552 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 76245336 ps |
| CPU time | 3.26 seconds |
| Started | Oct 14 09:08:54 PM UTC 24 |
| Finished | Oct 14 09:08:58 PM UTC 24 |
| Peak memory | 214600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2907996552 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.2907996552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/40.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_random.3827792454 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 173706225 ps |
| CPU time | 20.4 seconds |
| Started | Oct 14 09:08:48 PM UTC 24 |
| Finished | Oct 14 09:09:09 PM UTC 24 |
| Peak memory | 214628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3827792454 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random.3827792454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/40.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_random_large_delays.2989378445 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 45156884898 ps |
| CPU time | 78.72 seconds |
| Started | Oct 14 09:08:50 PM UTC 24 |
| Finished | Oct 14 09:10:11 PM UTC 24 |
| Peak memory | 214696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2989378445 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.2989378445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/40.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_random_slow_rsp.2241340994 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 1701594707 ps |
| CPU time | 16.65 seconds |
| Started | Oct 14 09:08:50 PM UTC 24 |
| Finished | Oct 14 09:09:08 PM UTC 24 |
| Peak memory | 214600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2241340994 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.2241340994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/40.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_random_zero_delays.4181091116 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 138147557 ps |
| CPU time | 21 seconds |
| Started | Oct 14 09:08:48 PM UTC 24 |
| Finished | Oct 14 09:09:10 PM UTC 24 |
| Peak memory | 214812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4181091116 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_delays.4181091116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/40.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_same_source.3116938712 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 508803380 ps |
| CPU time | 13.09 seconds |
| Started | Oct 14 09:08:52 PM UTC 24 |
| Finished | Oct 14 09:09:07 PM UTC 24 |
| Peak memory | 214628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3116938712 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.3116938712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/40.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_smoke.1852279015 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 34369060 ps |
| CPU time | 2.71 seconds |
| Started | Oct 14 09:08:42 PM UTC 24 |
| Finished | Oct 14 09:08:46 PM UTC 24 |
| Peak memory | 214584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1852279015 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.1852279015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/40.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_smoke_large_delays.1496652991 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 7084234110 ps |
| CPU time | 54.39 seconds |
| Started | Oct 14 09:08:45 PM UTC 24 |
| Finished | Oct 14 09:09:41 PM UTC 24 |
| Peak memory | 214872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1496652991 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.1496652991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/40.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_smoke_slow_rsp.3255144943 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 3546970989 ps |
| CPU time | 24.61 seconds |
| Started | Oct 14 09:08:46 PM UTC 24 |
| Finished | Oct 14 09:09:12 PM UTC 24 |
| Peak memory | 214652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3255144943 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.3255144943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/40.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_smoke_zero_delays.698941403 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 42038647 ps |
| CPU time | 2.96 seconds |
| Started | Oct 14 09:08:45 PM UTC 24 |
| Finished | Oct 14 09:08:49 PM UTC 24 |
| Peak memory | 214868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=698941403 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/x bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delays.698941403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/40.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all.325912348 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 4995080600 ps |
| CPU time | 101.12 seconds |
| Started | Oct 14 09:09:00 PM UTC 24 |
| Finished | Oct 14 09:10:43 PM UTC 24 |
| Peak memory | 218788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=325912348 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.325912348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/40.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_error.2472816617 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 9042996546 ps |
| CPU time | 201.26 seconds |
| Started | Oct 14 09:09:00 PM UTC 24 |
| Finished | Oct 14 09:12:24 PM UTC 24 |
| Peak memory | 218864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2472816617 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.2472816617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/40.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_rand_reset.2239662300 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 6749765723 ps |
| CPU time | 178.39 seconds |
| Started | Oct 14 09:09:00 PM UTC 24 |
| Finished | Oct 14 09:12:01 PM UTC 24 |
| Peak memory | 220840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2239662300 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_rand_reset.2239662300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/40.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_reset_error.1382139209 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 507183807 ps |
| CPU time | 93.1 seconds |
| Started | Oct 14 09:09:00 PM UTC 24 |
| Finished | Oct 14 09:10:35 PM UTC 24 |
| Peak memory | 220780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1382139209 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_reset_error.1382139209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/40.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/40.xbar_unmapped_addr.2258142600 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 451579453 ps |
| CPU time | 20.97 seconds |
| Started | Oct 14 09:08:54 PM UTC 24 |
| Finished | Oct 14 09:09:16 PM UTC 24 |
| Peak memory | 214624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2258142600 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.2258142600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/40.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_access_same_device.169931835 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 1904477923 ps |
| CPU time | 57.17 seconds |
| Started | Oct 14 09:09:12 PM UTC 24 |
| Finished | Oct 14 09:10:10 PM UTC 24 |
| Peak memory | 216936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=169931835 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xba r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device.169931835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/41.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_access_same_device_slow_rsp.2884562169 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 28412134068 ps |
| CPU time | 235.97 seconds |
| Started | Oct 14 09:09:12 PM UTC 24 |
| Finished | Oct 14 09:13:11 PM UTC 24 |
| Peak memory | 216740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2884562169 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device_slow_rsp.2884562169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/41.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_error_and_unmapped_addr.1966767655 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 434591561 ps |
| CPU time | 10.17 seconds |
| Started | Oct 14 09:09:14 PM UTC 24 |
| Finished | Oct 14 09:09:25 PM UTC 24 |
| Peak memory | 214628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1966767655 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_addr.1966767655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/41.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_error_random.2148028831 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 167637971 ps |
| CPU time | 28.96 seconds |
| Started | Oct 14 09:09:12 PM UTC 24 |
| Finished | Oct 14 09:09:42 PM UTC 24 |
| Peak memory | 214596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2148028831 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.2148028831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/41.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_random.1768479400 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 124203863 ps |
| CPU time | 12.21 seconds |
| Started | Oct 14 09:09:05 PM UTC 24 |
| Finished | Oct 14 09:09:18 PM UTC 24 |
| Peak memory | 214632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1768479400 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random.1768479400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/41.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_random_large_delays.876227174 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 23106807262 ps |
| CPU time | 59.35 seconds |
| Started | Oct 14 09:09:09 PM UTC 24 |
| Finished | Oct 14 09:10:10 PM UTC 24 |
| Peak memory | 214688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=876227174 -assert nopostproc +UVM_ TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.876227174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/41.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_random_slow_rsp.2888634985 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 61552316550 ps |
| CPU time | 160.79 seconds |
| Started | Oct 14 09:09:09 PM UTC 24 |
| Finished | Oct 14 09:11:53 PM UTC 24 |
| Peak memory | 214692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2888634985 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.2888634985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/41.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_random_zero_delays.2494445383 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 42596148 ps |
| CPU time | 6.38 seconds |
| Started | Oct 14 09:09:07 PM UTC 24 |
| Finished | Oct 14 09:09:15 PM UTC 24 |
| Peak memory | 214616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2494445383 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_delays.2494445383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/41.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_same_source.1950629466 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 956262047 ps |
| CPU time | 24.09 seconds |
| Started | Oct 14 09:09:12 PM UTC 24 |
| Finished | Oct 14 09:09:37 PM UTC 24 |
| Peak memory | 214628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1950629466 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.1950629466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/41.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_smoke.3113686284 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 298939207 ps |
| CPU time | 5.56 seconds |
| Started | Oct 14 09:09:00 PM UTC 24 |
| Finished | Oct 14 09:09:06 PM UTC 24 |
| Peak memory | 214584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3113686284 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.3113686284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/41.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_smoke_large_delays.655158155 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 27076079709 ps |
| CPU time | 66.45 seconds |
| Started | Oct 14 09:09:01 PM UTC 24 |
| Finished | Oct 14 09:10:10 PM UTC 24 |
| Peak memory | 214684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=655158155 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.655158155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/41.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_smoke_slow_rsp.2364521764 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 7279927358 ps |
| CPU time | 30.77 seconds |
| Started | Oct 14 09:09:02 PM UTC 24 |
| Finished | Oct 14 09:09:34 PM UTC 24 |
| Peak memory | 214848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2364521764 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.2364521764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/41.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_smoke_zero_delays.728617323 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 33384903 ps |
| CPU time | 3.36 seconds |
| Started | Oct 14 09:09:00 PM UTC 24 |
| Finished | Oct 14 09:09:04 PM UTC 24 |
| Peak memory | 214608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=728617323 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/x bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delays.728617323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/41.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all.1919724234 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 2606333527 ps |
| CPU time | 200.42 seconds |
| Started | Oct 14 09:09:16 PM UTC 24 |
| Finished | Oct 14 09:12:39 PM UTC 24 |
| Peak memory | 220836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1919724234 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.1919724234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/41.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_error.3813831845 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 657955095 ps |
| CPU time | 28.61 seconds |
| Started | Oct 14 09:09:20 PM UTC 24 |
| Finished | Oct 14 09:09:50 PM UTC 24 |
| Peak memory | 214636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3813831845 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.3813831845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/41.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_rand_reset.1258938492 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 80966028 ps |
| CPU time | 31.71 seconds |
| Started | Oct 14 09:09:17 PM UTC 24 |
| Finished | Oct 14 09:09:50 PM UTC 24 |
| Peak memory | 216676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1258938492 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_rand_reset.1258938492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/41.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_reset_error.3519843900 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 1679704094 ps |
| CPU time | 169.29 seconds |
| Started | Oct 14 09:09:21 PM UTC 24 |
| Finished | Oct 14 09:12:13 PM UTC 24 |
| Peak memory | 220784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3519843900 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_reset_error.3519843900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/41.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/41.xbar_unmapped_addr.2605072791 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 204175900 ps |
| CPU time | 20.24 seconds |
| Started | Oct 14 09:09:14 PM UTC 24 |
| Finished | Oct 14 09:09:35 PM UTC 24 |
| Peak memory | 214820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2605072791 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.2605072791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/41.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_access_same_device.4270458024 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 466814531 ps |
| CPU time | 25.49 seconds |
| Started | Oct 14 09:09:36 PM UTC 24 |
| Finished | Oct 14 09:10:03 PM UTC 24 |
| Peak memory | 216684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4270458024 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device.4270458024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/42.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.2231531225 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 109507099845 ps |
| CPU time | 220.09 seconds |
| Started | Oct 14 09:09:36 PM UTC 24 |
| Finished | Oct 14 09:13:20 PM UTC 24 |
| Peak memory | 216936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2231531225 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device_slow_rsp.2231531225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/42.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_error_and_unmapped_addr.718182357 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 67612872 ps |
| CPU time | 7.17 seconds |
| Started | Oct 14 09:09:40 PM UTC 24 |
| Finished | Oct 14 09:09:49 PM UTC 24 |
| Peak memory | 214632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=718182357 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_addr.718182357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/42.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_error_random.1226617966 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 134697849 ps |
| CPU time | 10.02 seconds |
| Started | Oct 14 09:09:38 PM UTC 24 |
| Finished | Oct 14 09:09:49 PM UTC 24 |
| Peak memory | 214600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1226617966 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.1226617966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/42.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_random.1887440550 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 63839270 ps |
| CPU time | 3.73 seconds |
| Started | Oct 14 09:09:28 PM UTC 24 |
| Finished | Oct 14 09:09:33 PM UTC 24 |
| Peak memory | 214628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1887440550 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random.1887440550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/42.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_random_large_delays.2901916012 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 36566856525 ps |
| CPU time | 108.68 seconds |
| Started | Oct 14 09:09:34 PM UTC 24 |
| Finished | Oct 14 09:11:25 PM UTC 24 |
| Peak memory | 214696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2901916012 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.2901916012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/42.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_random_slow_rsp.2194085013 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 2161095359 ps |
| CPU time | 15.86 seconds |
| Started | Oct 14 09:09:36 PM UTC 24 |
| Finished | Oct 14 09:09:53 PM UTC 24 |
| Peak memory | 214692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2194085013 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.2194085013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/42.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_random_zero_delays.2935282048 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 1088386876 ps |
| CPU time | 21.62 seconds |
| Started | Oct 14 09:09:31 PM UTC 24 |
| Finished | Oct 14 09:09:54 PM UTC 24 |
| Peak memory | 214816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2935282048 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_delays.2935282048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/42.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_same_source.4054210191 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 4614869928 ps |
| CPU time | 32.63 seconds |
| Started | Oct 14 09:09:38 PM UTC 24 |
| Finished | Oct 14 09:10:12 PM UTC 24 |
| Peak memory | 214692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4054210191 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.4054210191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/42.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_smoke.2913777663 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 318363910 ps |
| CPU time | 2.94 seconds |
| Started | Oct 14 09:09:23 PM UTC 24 |
| Finished | Oct 14 09:09:27 PM UTC 24 |
| Peak memory | 214780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2913777663 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.2913777663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/42.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_smoke_large_delays.3057947371 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 20326480018 ps |
| CPU time | 43.34 seconds |
| Started | Oct 14 09:09:28 PM UTC 24 |
| Finished | Oct 14 09:10:13 PM UTC 24 |
| Peak memory | 214680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3057947371 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.3057947371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/42.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_smoke_slow_rsp.3416892547 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 5258415779 ps |
| CPU time | 33.71 seconds |
| Started | Oct 14 09:09:28 PM UTC 24 |
| Finished | Oct 14 09:10:03 PM UTC 24 |
| Peak memory | 214784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3416892547 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.3416892547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/42.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_smoke_zero_delays.2078612189 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 74686438 ps |
| CPU time | 3.06 seconds |
| Started | Oct 14 09:09:26 PM UTC 24 |
| Finished | Oct 14 09:09:30 PM UTC 24 |
| Peak memory | 214600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2078612189 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delays.2078612189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/42.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all.3731945023 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 1583132521 ps |
| CPU time | 205.13 seconds |
| Started | Oct 14 09:09:42 PM UTC 24 |
| Finished | Oct 14 09:13:10 PM UTC 24 |
| Peak memory | 218724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3731945023 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.3731945023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/42.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_error.3246604559 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 784548960 ps |
| CPU time | 55.62 seconds |
| Started | Oct 14 09:09:44 PM UTC 24 |
| Finished | Oct 14 09:10:41 PM UTC 24 |
| Peak memory | 216688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3246604559 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.3246604559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/42.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.2589054001 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 490817314 ps |
| CPU time | 142.73 seconds |
| Started | Oct 14 09:09:42 PM UTC 24 |
| Finished | Oct 14 09:12:07 PM UTC 24 |
| Peak memory | 218724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2589054001 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_rand_reset.2589054001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/42.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_reset_error.1638332397 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 63045137 ps |
| CPU time | 15.97 seconds |
| Started | Oct 14 09:09:44 PM UTC 24 |
| Finished | Oct 14 09:10:01 PM UTC 24 |
| Peak memory | 216680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1638332397 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_reset_error.1638332397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/42.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/42.xbar_unmapped_addr.3008295007 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 19792416 ps |
| CPU time | 4.04 seconds |
| Started | Oct 14 09:09:40 PM UTC 24 |
| Finished | Oct 14 09:09:45 PM UTC 24 |
| Peak memory | 214820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3008295007 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.3008295007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/42.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_access_same_device.4197022507 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 397423622 ps |
| CPU time | 13.92 seconds |
| Started | Oct 14 09:09:56 PM UTC 24 |
| Finished | Oct 14 09:10:12 PM UTC 24 |
| Peak memory | 214636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4197022507 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device.4197022507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/43.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.1653930910 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 87733314500 ps |
| CPU time | 321.71 seconds |
| Started | Oct 14 09:09:57 PM UTC 24 |
| Finished | Oct 14 09:15:23 PM UTC 24 |
| Peak memory | 217260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1653930910 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device_slow_rsp.1653930910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/43.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_error_and_unmapped_addr.99973930 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 97112723 ps |
| CPU time | 8.42 seconds |
| Started | Oct 14 09:10:00 PM UTC 24 |
| Finished | Oct 14 09:10:09 PM UTC 24 |
| Peak memory | 214824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=99973930 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_addr.99973930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/43.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_error_random.2752728353 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 1285254216 ps |
| CPU time | 28.08 seconds |
| Started | Oct 14 09:10:00 PM UTC 24 |
| Finished | Oct 14 09:10:29 PM UTC 24 |
| Peak memory | 214792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2752728353 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.2752728353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/43.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_random.2972836085 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 230761012 ps |
| CPU time | 29.35 seconds |
| Started | Oct 14 09:09:53 PM UTC 24 |
| Finished | Oct 14 09:10:24 PM UTC 24 |
| Peak memory | 216656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2972836085 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random.2972836085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/43.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_random_large_delays.1139870785 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 40939151574 ps |
| CPU time | 117.87 seconds |
| Started | Oct 14 09:09:56 PM UTC 24 |
| Finished | Oct 14 09:11:57 PM UTC 24 |
| Peak memory | 214888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1139870785 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.1139870785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/43.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_random_slow_rsp.3133339145 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 9528744409 ps |
| CPU time | 127.1 seconds |
| Started | Oct 14 09:09:56 PM UTC 24 |
| Finished | Oct 14 09:12:06 PM UTC 24 |
| Peak memory | 214948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3133339145 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.3133339145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/43.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_random_zero_delays.2581501703 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 252684721 ps |
| CPU time | 21.54 seconds |
| Started | Oct 14 09:09:53 PM UTC 24 |
| Finished | Oct 14 09:10:16 PM UTC 24 |
| Peak memory | 216664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2581501703 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_delays.2581501703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/43.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_same_source.3033153819 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 17940261 ps |
| CPU time | 2.5 seconds |
| Started | Oct 14 09:09:57 PM UTC 24 |
| Finished | Oct 14 09:10:00 PM UTC 24 |
| Peak memory | 214792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3033153819 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.3033153819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/43.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke.2344021859 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 156676993 ps |
| CPU time | 4.81 seconds |
| Started | Oct 14 09:09:46 PM UTC 24 |
| Finished | Oct 14 09:09:52 PM UTC 24 |
| Peak memory | 214588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2344021859 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.2344021859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/43.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke_large_delays.127622619 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 9560583294 ps |
| CPU time | 42.37 seconds |
| Started | Oct 14 09:09:50 PM UTC 24 |
| Finished | Oct 14 09:10:34 PM UTC 24 |
| Peak memory | 214876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=127622619 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.127622619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/43.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke_slow_rsp.1520310206 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 3162627720 ps |
| CPU time | 22.81 seconds |
| Started | Oct 14 09:09:53 PM UTC 24 |
| Finished | Oct 14 09:10:17 PM UTC 24 |
| Peak memory | 214632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1520310206 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.1520310206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/43.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke_zero_delays.1511208166 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 42602108 ps |
| CPU time | 2.75 seconds |
| Started | Oct 14 09:09:50 PM UTC 24 |
| Finished | Oct 14 09:09:54 PM UTC 24 |
| Peak memory | 214600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1511208166 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delays.1511208166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/43.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all.26185525 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 1552888836 ps |
| CPU time | 63.66 seconds |
| Started | Oct 14 09:10:02 PM UTC 24 |
| Finished | Oct 14 09:11:07 PM UTC 24 |
| Peak memory | 216680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26185525 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-si m-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.26185525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/43.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_error.3857373880 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 489354165 ps |
| CPU time | 41.27 seconds |
| Started | Oct 14 09:10:05 PM UTC 24 |
| Finished | Oct 14 09:10:47 PM UTC 24 |
| Peak memory | 214636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3857373880 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.3857373880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/43.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.559213543 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 752297967 ps |
| CPU time | 277.71 seconds |
| Started | Oct 14 09:10:05 PM UTC 24 |
| Finished | Oct 14 09:14:46 PM UTC 24 |
| Peak memory | 218724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=559213543 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_rand_reset.559213543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/43.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.3965864405 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 10914397351 ps |
| CPU time | 367.78 seconds |
| Started | Oct 14 09:10:05 PM UTC 24 |
| Finished | Oct 14 09:16:17 PM UTC 24 |
| Peak memory | 231720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3965864405 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_reset_error.3965864405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/43.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/43.xbar_unmapped_addr.1049068161 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 558960610 ps |
| CPU time | 23.06 seconds |
| Started | Oct 14 09:10:00 PM UTC 24 |
| Finished | Oct 14 09:10:24 PM UTC 24 |
| Peak memory | 216868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1049068161 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.1049068161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/43.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_access_same_device.3634671018 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 84814373 ps |
| CPU time | 6.06 seconds |
| Started | Oct 14 09:10:13 PM UTC 24 |
| Finished | Oct 14 09:10:20 PM UTC 24 |
| Peak memory | 214764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3634671018 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device.3634671018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/44.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.1087187134 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 21043799231 ps |
| CPU time | 165.75 seconds |
| Started | Oct 14 09:10:13 PM UTC 24 |
| Finished | Oct 14 09:13:02 PM UTC 24 |
| Peak memory | 216744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1087187134 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device_slow_rsp.1087187134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/44.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_error_and_unmapped_addr.1543326462 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 188898922 ps |
| CPU time | 21.31 seconds |
| Started | Oct 14 09:10:16 PM UTC 24 |
| Finished | Oct 14 09:10:39 PM UTC 24 |
| Peak memory | 214628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1543326462 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_addr.1543326462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/44.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_error_random.1637465345 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 1725998143 ps |
| CPU time | 30.7 seconds |
| Started | Oct 14 09:10:16 PM UTC 24 |
| Finished | Oct 14 09:10:48 PM UTC 24 |
| Peak memory | 214820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1637465345 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.1637465345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/44.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_random.2912834196 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 963202681 ps |
| CPU time | 34.12 seconds |
| Started | Oct 14 09:10:08 PM UTC 24 |
| Finished | Oct 14 09:10:44 PM UTC 24 |
| Peak memory | 214888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2912834196 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random.2912834196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/44.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_random_large_delays.2201808862 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 12930029234 ps |
| CPU time | 76.11 seconds |
| Started | Oct 14 09:10:13 PM UTC 24 |
| Finished | Oct 14 09:11:31 PM UTC 24 |
| Peak memory | 214696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2201808862 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.2201808862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/44.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_random_slow_rsp.970491945 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 17174429675 ps |
| CPU time | 105.29 seconds |
| Started | Oct 14 09:10:13 PM UTC 24 |
| Finished | Oct 14 09:12:00 PM UTC 24 |
| Peak memory | 216744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=970491945 -assert nopostproc +UVM_TEST NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.970491945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/44.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_random_zero_delays.770241133 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 98978901 ps |
| CPU time | 17.94 seconds |
| Started | Oct 14 09:10:13 PM UTC 24 |
| Finished | Oct 14 09:10:32 PM UTC 24 |
| Peak memory | 214688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=770241133 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_delays.770241133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/44.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_same_source.2255837744 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 3641358372 ps |
| CPU time | 27.95 seconds |
| Started | Oct 14 09:10:13 PM UTC 24 |
| Finished | Oct 14 09:10:43 PM UTC 24 |
| Peak memory | 214692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2255837744 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.2255837744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/44.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke.1758461968 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 106183670 ps |
| CPU time | 3.11 seconds |
| Started | Oct 14 09:10:05 PM UTC 24 |
| Finished | Oct 14 09:10:09 PM UTC 24 |
| Peak memory | 214584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1758461968 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.1758461968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/44.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_large_delays.164071484 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 20012153139 ps |
| CPU time | 38.95 seconds |
| Started | Oct 14 09:10:08 PM UTC 24 |
| Finished | Oct 14 09:10:49 PM UTC 24 |
| Peak memory | 214680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=164071484 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.164071484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/44.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_slow_rsp.2300123591 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 4916376978 ps |
| CPU time | 28.06 seconds |
| Started | Oct 14 09:10:08 PM UTC 24 |
| Finished | Oct 14 09:10:38 PM UTC 24 |
| Peak memory | 214652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2300123591 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.2300123591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/44.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_zero_delays.2771217053 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 53049822 ps |
| CPU time | 3.55 seconds |
| Started | Oct 14 09:10:05 PM UTC 24 |
| Finished | Oct 14 09:10:10 PM UTC 24 |
| Peak memory | 214600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2771217053 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delays.2771217053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/44.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all.1620082488 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 6520981603 ps |
| CPU time | 180.41 seconds |
| Started | Oct 14 09:10:16 PM UTC 24 |
| Finished | Oct 14 09:13:20 PM UTC 24 |
| Peak memory | 220972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1620082488 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.1620082488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/44.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_error.534701717 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 6187384183 ps |
| CPU time | 163.01 seconds |
| Started | Oct 14 09:10:17 PM UTC 24 |
| Finished | Oct 14 09:13:02 PM UTC 24 |
| Peak memory | 220844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=534701717 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.534701717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/44.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_rand_reset.1673045752 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 335662760 ps |
| CPU time | 125.82 seconds |
| Started | Oct 14 09:10:16 PM UTC 24 |
| Finished | Oct 14 09:12:25 PM UTC 24 |
| Peak memory | 218724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1673045752 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_rand_reset.1673045752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/44.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.1397159731 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 170691681 ps |
| CPU time | 27.24 seconds |
| Started | Oct 14 09:10:18 PM UTC 24 |
| Finished | Oct 14 09:10:47 PM UTC 24 |
| Peak memory | 216876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1397159731 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_reset_error.1397159731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/44.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/44.xbar_unmapped_addr.1633307016 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 2473565343 ps |
| CPU time | 28.65 seconds |
| Started | Oct 14 09:10:16 PM UTC 24 |
| Finished | Oct 14 09:10:46 PM UTC 24 |
| Peak memory | 216736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1633307016 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.1633307016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/44.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_access_same_device.1731077621 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 2788558854 ps |
| CPU time | 49.29 seconds |
| Started | Oct 14 09:10:28 PM UTC 24 |
| Finished | Oct 14 09:11:19 PM UTC 24 |
| Peak memory | 216744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1731077621 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device.1731077621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/45.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.1932900594 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 4723241319 ps |
| CPU time | 40.25 seconds |
| Started | Oct 14 09:10:30 PM UTC 24 |
| Finished | Oct 14 09:11:12 PM UTC 24 |
| Peak memory | 216740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1932900594 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device_slow_rsp.1932900594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/45.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_error_and_unmapped_addr.4085071582 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 168566371 ps |
| CPU time | 15.08 seconds |
| Started | Oct 14 09:10:34 PM UTC 24 |
| Finished | Oct 14 09:10:50 PM UTC 24 |
| Peak memory | 214628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4085071582 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_addr.4085071582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/45.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_error_random.3413485277 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 410575830 ps |
| CPU time | 10.91 seconds |
| Started | Oct 14 09:10:32 PM UTC 24 |
| Finished | Oct 14 09:10:44 PM UTC 24 |
| Peak memory | 214792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3413485277 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.3413485277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/45.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_random.1851601931 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 884156777 ps |
| CPU time | 25.9 seconds |
| Started | Oct 14 09:10:26 PM UTC 24 |
| Finished | Oct 14 09:10:54 PM UTC 24 |
| Peak memory | 214824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1851601931 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random.1851601931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/45.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_random_large_delays.1784763905 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 22872697849 ps |
| CPU time | 157.92 seconds |
| Started | Oct 14 09:10:26 PM UTC 24 |
| Finished | Oct 14 09:13:07 PM UTC 24 |
| Peak memory | 214700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1784763905 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.1784763905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/45.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_random_slow_rsp.3278643109 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 6377196315 ps |
| CPU time | 73.09 seconds |
| Started | Oct 14 09:10:28 PM UTC 24 |
| Finished | Oct 14 09:11:43 PM UTC 24 |
| Peak memory | 216740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3278643109 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.3278643109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/45.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_random_zero_delays.2542481337 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 69009326 ps |
| CPU time | 5.3 seconds |
| Started | Oct 14 09:10:26 PM UTC 24 |
| Finished | Oct 14 09:10:33 PM UTC 24 |
| Peak memory | 214620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2542481337 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_delays.2542481337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/45.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_same_source.4063719723 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 324021084 ps |
| CPU time | 18.14 seconds |
| Started | Oct 14 09:10:30 PM UTC 24 |
| Finished | Oct 14 09:10:50 PM UTC 24 |
| Peak memory | 214884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4063719723 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.4063719723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/45.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke.915120181 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 110213107 ps |
| CPU time | 4.55 seconds |
| Started | Oct 14 09:10:18 PM UTC 24 |
| Finished | Oct 14 09:10:24 PM UTC 24 |
| Peak memory | 214608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=915120181 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.915120181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/45.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_large_delays.2909345880 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 10031650211 ps |
| CPU time | 41.95 seconds |
| Started | Oct 14 09:10:23 PM UTC 24 |
| Finished | Oct 14 09:11:07 PM UTC 24 |
| Peak memory | 214680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2909345880 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.2909345880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/45.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_slow_rsp.1570434343 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 6137775404 ps |
| CPU time | 37.25 seconds |
| Started | Oct 14 09:10:26 PM UTC 24 |
| Finished | Oct 14 09:11:05 PM UTC 24 |
| Peak memory | 214652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1570434343 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.1570434343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/45.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_zero_delays.1424807473 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 35671636 ps |
| CPU time | 3.49 seconds |
| Started | Oct 14 09:10:21 PM UTC 24 |
| Finished | Oct 14 09:10:25 PM UTC 24 |
| Peak memory | 214600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1424807473 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delays.1424807473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/45.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all.28530638 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 291525173 ps |
| CPU time | 9.17 seconds |
| Started | Oct 14 09:10:36 PM UTC 24 |
| Finished | Oct 14 09:10:46 PM UTC 24 |
| Peak memory | 216680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=28530638 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-si m-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.28530638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/45.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_error.1326248720 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 390783017 ps |
| CPU time | 31.13 seconds |
| Started | Oct 14 09:10:36 PM UTC 24 |
| Finished | Oct 14 09:11:08 PM UTC 24 |
| Peak memory | 216688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1326248720 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.1326248720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/45.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.2109276908 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 3188626457 ps |
| CPU time | 462.03 seconds |
| Started | Oct 14 09:10:36 PM UTC 24 |
| Finished | Oct 14 09:18:24 PM UTC 24 |
| Peak memory | 222360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2109276908 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_rand_reset.2109276908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/45.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_reset_error.1938987034 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 9762873920 ps |
| CPU time | 172.76 seconds |
| Started | Oct 14 09:10:39 PM UTC 24 |
| Finished | Oct 14 09:13:34 PM UTC 24 |
| Peak memory | 221076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1938987034 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_reset_error.1938987034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/45.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/45.xbar_unmapped_addr.1001006554 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 636342197 ps |
| CPU time | 22.03 seconds |
| Started | Oct 14 09:10:34 PM UTC 24 |
| Finished | Oct 14 09:10:57 PM UTC 24 |
| Peak memory | 216672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1001006554 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.1001006554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/45.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_access_same_device.3416584546 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 1017199394 ps |
| CPU time | 19.35 seconds |
| Started | Oct 14 09:10:46 PM UTC 24 |
| Finished | Oct 14 09:11:06 PM UTC 24 |
| Peak memory | 214636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3416584546 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device.3416584546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/46.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.1493949401 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 52584794767 ps |
| CPU time | 281.8 seconds |
| Started | Oct 14 09:10:48 PM UTC 24 |
| Finished | Oct 14 09:15:34 PM UTC 24 |
| Peak memory | 216740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1493949401 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device_slow_rsp.1493949401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/46.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.2872909989 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 1439524377 ps |
| CPU time | 21.33 seconds |
| Started | Oct 14 09:10:51 PM UTC 24 |
| Finished | Oct 14 09:11:14 PM UTC 24 |
| Peak memory | 214824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2872909989 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_addr.2872909989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/46.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_error_random.1888178749 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 1430262401 ps |
| CPU time | 30.66 seconds |
| Started | Oct 14 09:10:49 PM UTC 24 |
| Finished | Oct 14 09:11:20 PM UTC 24 |
| Peak memory | 214628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1888178749 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.1888178749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/46.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_random.3529279342 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 33287752 ps |
| CPU time | 6.37 seconds |
| Started | Oct 14 09:10:45 PM UTC 24 |
| Finished | Oct 14 09:10:53 PM UTC 24 |
| Peak memory | 214628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3529279342 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random.3529279342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/46.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_random_large_delays.3297591269 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 19266172333 ps |
| CPU time | 67.42 seconds |
| Started | Oct 14 09:10:45 PM UTC 24 |
| Finished | Oct 14 09:11:55 PM UTC 24 |
| Peak memory | 214700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3297591269 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.3297591269 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/46.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_random_slow_rsp.1317365310 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 10778403595 ps |
| CPU time | 69.18 seconds |
| Started | Oct 14 09:10:46 PM UTC 24 |
| Finished | Oct 14 09:11:56 PM UTC 24 |
| Peak memory | 214952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1317365310 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.1317365310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/46.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_random_zero_delays.1549370231 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 149255881 ps |
| CPU time | 13.85 seconds |
| Started | Oct 14 09:10:45 PM UTC 24 |
| Finished | Oct 14 09:11:00 PM UTC 24 |
| Peak memory | 214624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1549370231 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_delays.1549370231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/46.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_same_source.1654011879 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 595165574 ps |
| CPU time | 23.42 seconds |
| Started | Oct 14 09:10:48 PM UTC 24 |
| Finished | Oct 14 09:11:13 PM UTC 24 |
| Peak memory | 214628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1654011879 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.1654011879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/46.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke.521958786 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 359310910 ps |
| CPU time | 3.75 seconds |
| Started | Oct 14 09:10:41 PM UTC 24 |
| Finished | Oct 14 09:10:46 PM UTC 24 |
| Peak memory | 214612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=521958786 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.521958786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/46.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_large_delays.1477860717 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 10321869124 ps |
| CPU time | 40.17 seconds |
| Started | Oct 14 09:10:43 PM UTC 24 |
| Finished | Oct 14 09:11:25 PM UTC 24 |
| Peak memory | 214872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1477860717 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.1477860717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/46.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.1595078495 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 4884315379 ps |
| CPU time | 28.61 seconds |
| Started | Oct 14 09:10:43 PM UTC 24 |
| Finished | Oct 14 09:11:13 PM UTC 24 |
| Peak memory | 214656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1595078495 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.1595078495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/46.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.2240731764 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 47870738 ps |
| CPU time | 2.47 seconds |
| Started | Oct 14 09:10:41 PM UTC 24 |
| Finished | Oct 14 09:10:45 PM UTC 24 |
| Peak memory | 214600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2240731764 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delays.2240731764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/46.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all.1227537842 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 169623748 ps |
| CPU time | 22.63 seconds |
| Started | Oct 14 09:10:51 PM UTC 24 |
| Finished | Oct 14 09:11:15 PM UTC 24 |
| Peak memory | 216676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1227537842 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.1227537842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/46.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_error.1804204645 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 1130362652 ps |
| CPU time | 50.8 seconds |
| Started | Oct 14 09:10:51 PM UTC 24 |
| Finished | Oct 14 09:11:44 PM UTC 24 |
| Peak memory | 218732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1804204645 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.1804204645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/46.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_rand_reset.2531261741 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 2515582805 ps |
| CPU time | 465.49 seconds |
| Started | Oct 14 09:10:51 PM UTC 24 |
| Finished | Oct 14 09:18:43 PM UTC 24 |
| Peak memory | 222356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2531261741 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_rand_reset.2531261741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/46.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_reset_error.273740451 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 161346813 ps |
| CPU time | 144.75 seconds |
| Started | Oct 14 09:10:51 PM UTC 24 |
| Finished | Oct 14 09:13:19 PM UTC 24 |
| Peak memory | 220780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=273740451 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_reset_error.273740451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/46.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/46.xbar_unmapped_addr.828266976 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 498131072 ps |
| CPU time | 28.83 seconds |
| Started | Oct 14 09:10:49 PM UTC 24 |
| Finished | Oct 14 09:11:19 PM UTC 24 |
| Peak memory | 216676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=828266976 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.828266976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/46.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_access_same_device.3419686164 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 20214236 ps |
| CPU time | 3.03 seconds |
| Started | Oct 14 09:11:08 PM UTC 24 |
| Finished | Oct 14 09:11:12 PM UTC 24 |
| Peak memory | 214624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3419686164 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device.3419686164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/47.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_access_same_device_slow_rsp.3866810230 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 69359995440 ps |
| CPU time | 321.63 seconds |
| Started | Oct 14 09:11:10 PM UTC 24 |
| Finished | Oct 14 09:16:36 PM UTC 24 |
| Peak memory | 216744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3866810230 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device_slow_rsp.3866810230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/47.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.30880994 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 1745462883 ps |
| CPU time | 18.31 seconds |
| Started | Oct 14 09:11:14 PM UTC 24 |
| Finished | Oct 14 09:11:34 PM UTC 24 |
| Peak memory | 214628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30880994 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_addr.30880994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/47.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_error_random.3004898982 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 3452363955 ps |
| CPU time | 21.32 seconds |
| Started | Oct 14 09:11:10 PM UTC 24 |
| Finished | Oct 14 09:11:33 PM UTC 24 |
| Peak memory | 214688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3004898982 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.3004898982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/47.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_random.3995735011 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 634732613 ps |
| CPU time | 13.31 seconds |
| Started | Oct 14 09:10:59 PM UTC 24 |
| Finished | Oct 14 09:11:14 PM UTC 24 |
| Peak memory | 214624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3995735011 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random.3995735011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/47.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_random_large_delays.950045609 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 14226708835 ps |
| CPU time | 71.8 seconds |
| Started | Oct 14 09:11:03 PM UTC 24 |
| Finished | Oct 14 09:12:16 PM UTC 24 |
| Peak memory | 214944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=950045609 -assert nopostproc +UVM_ TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.950045609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/47.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_random_slow_rsp.1918989067 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 33616539829 ps |
| CPU time | 150.93 seconds |
| Started | Oct 14 09:11:06 PM UTC 24 |
| Finished | Oct 14 09:13:40 PM UTC 24 |
| Peak memory | 214692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1918989067 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.1918989067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/47.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_random_zero_delays.865669415 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 52910848 ps |
| CPU time | 9.52 seconds |
| Started | Oct 14 09:11:01 PM UTC 24 |
| Finished | Oct 14 09:11:12 PM UTC 24 |
| Peak memory | 214624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=865669415 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_delays.865669415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/47.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_same_source.3031966097 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 320341455 ps |
| CPU time | 7.38 seconds |
| Started | Oct 14 09:11:10 PM UTC 24 |
| Finished | Oct 14 09:11:19 PM UTC 24 |
| Peak memory | 214632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3031966097 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.3031966097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/47.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke.1918481603 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 120665849 ps |
| CPU time | 5.32 seconds |
| Started | Oct 14 09:10:54 PM UTC 24 |
| Finished | Oct 14 09:11:00 PM UTC 24 |
| Peak memory | 214588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1918481603 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.1918481603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/47.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_large_delays.1900157971 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 6730880541 ps |
| CPU time | 26.05 seconds |
| Started | Oct 14 09:10:55 PM UTC 24 |
| Finished | Oct 14 09:11:23 PM UTC 24 |
| Peak memory | 214680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1900157971 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.1900157971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/47.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_slow_rsp.160375360 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 9930745394 ps |
| CPU time | 46.6 seconds |
| Started | Oct 14 09:10:58 PM UTC 24 |
| Finished | Oct 14 09:11:46 PM UTC 24 |
| Peak memory | 214648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=160375360 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.160375360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/47.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.3493274643 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 36695717 ps |
| CPU time | 3.71 seconds |
| Started | Oct 14 09:10:54 PM UTC 24 |
| Finished | Oct 14 09:10:58 PM UTC 24 |
| Peak memory | 214600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3493274643 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delays.3493274643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/47.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all.3541836394 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 525109348 ps |
| CPU time | 45.9 seconds |
| Started | Oct 14 09:11:14 PM UTC 24 |
| Finished | Oct 14 09:12:02 PM UTC 24 |
| Peak memory | 216676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3541836394 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.3541836394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/47.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_error.1634611694 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 1045047753 ps |
| CPU time | 111.4 seconds |
| Started | Oct 14 09:11:14 PM UTC 24 |
| Finished | Oct 14 09:13:08 PM UTC 24 |
| Peak memory | 218736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1634611694 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.1634611694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/47.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.2239949019 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 95663421 ps |
| CPU time | 15.19 seconds |
| Started | Oct 14 09:11:14 PM UTC 24 |
| Finished | Oct 14 09:11:31 PM UTC 24 |
| Peak memory | 216680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2239949019 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_rand_reset.2239949019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/47.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_reset_error.3408685112 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 537738703 ps |
| CPU time | 171.93 seconds |
| Started | Oct 14 09:11:14 PM UTC 24 |
| Finished | Oct 14 09:14:09 PM UTC 24 |
| Peak memory | 220780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3408685112 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_reset_error.3408685112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/47.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/47.xbar_unmapped_addr.1252761320 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 2159280075 ps |
| CPU time | 39.42 seconds |
| Started | Oct 14 09:11:14 PM UTC 24 |
| Finished | Oct 14 09:11:55 PM UTC 24 |
| Peak memory | 216992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1252761320 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.1252761320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/47.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_access_same_device.4204890097 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 296705086 ps |
| CPU time | 31.82 seconds |
| Started | Oct 14 09:11:25 PM UTC 24 |
| Finished | Oct 14 09:11:58 PM UTC 24 |
| Peak memory | 216684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4204890097 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device.4204890097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/48.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.2208216202 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 35373095038 ps |
| CPU time | 285.71 seconds |
| Started | Oct 14 09:11:25 PM UTC 24 |
| Finished | Oct 14 09:16:15 PM UTC 24 |
| Peak memory | 216740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2208216202 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device_slow_rsp.2208216202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/48.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.2160016230 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 727583772 ps |
| CPU time | 21.69 seconds |
| Started | Oct 14 09:11:33 PM UTC 24 |
| Finished | Oct 14 09:11:56 PM UTC 24 |
| Peak memory | 214824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2160016230 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_addr.2160016230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/48.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_error_random.1508735249 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 732982012 ps |
| CPU time | 22.32 seconds |
| Started | Oct 14 09:11:27 PM UTC 24 |
| Finished | Oct 14 09:11:51 PM UTC 24 |
| Peak memory | 214624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1508735249 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.1508735249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/48.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_random.3234554226 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 471360983 ps |
| CPU time | 13.1 seconds |
| Started | Oct 14 09:11:21 PM UTC 24 |
| Finished | Oct 14 09:11:35 PM UTC 24 |
| Peak memory | 214756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3234554226 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random.3234554226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/48.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_random_large_delays.2368808138 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 13490846045 ps |
| CPU time | 87.93 seconds |
| Started | Oct 14 09:11:23 PM UTC 24 |
| Finished | Oct 14 09:12:53 PM UTC 24 |
| Peak memory | 214692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2368808138 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.2368808138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/48.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_random_slow_rsp.874370204 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 16823818414 ps |
| CPU time | 45.02 seconds |
| Started | Oct 14 09:11:23 PM UTC 24 |
| Finished | Oct 14 09:12:09 PM UTC 24 |
| Peak memory | 214696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=874370204 -assert nopostproc +UVM_TEST NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.874370204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/48.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_random_zero_delays.1861656081 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 158509136 ps |
| CPU time | 18.21 seconds |
| Started | Oct 14 09:11:23 PM UTC 24 |
| Finished | Oct 14 09:11:42 PM UTC 24 |
| Peak memory | 216916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1861656081 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_delays.1861656081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/48.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_same_source.2387606145 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 530322718 ps |
| CPU time | 19.48 seconds |
| Started | Oct 14 09:11:27 PM UTC 24 |
| Finished | Oct 14 09:11:48 PM UTC 24 |
| Peak memory | 214628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2387606145 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.2387606145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/48.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke.3162442187 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 134496876 ps |
| CPU time | 5.23 seconds |
| Started | Oct 14 09:11:17 PM UTC 24 |
| Finished | Oct 14 09:11:23 PM UTC 24 |
| Peak memory | 214588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3162442187 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.3162442187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/48.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_large_delays.154175136 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 11610937991 ps |
| CPU time | 35.66 seconds |
| Started | Oct 14 09:11:17 PM UTC 24 |
| Finished | Oct 14 09:11:54 PM UTC 24 |
| Peak memory | 214812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=154175136 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.154175136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/48.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_slow_rsp.3088229870 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 11250200823 ps |
| CPU time | 34.7 seconds |
| Started | Oct 14 09:11:21 PM UTC 24 |
| Finished | Oct 14 09:11:57 PM UTC 24 |
| Peak memory | 214480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3088229870 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.3088229870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/48.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_zero_delays.557082934 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 29964874 ps |
| CPU time | 2.27 seconds |
| Started | Oct 14 09:11:17 PM UTC 24 |
| Finished | Oct 14 09:11:21 PM UTC 24 |
| Peak memory | 214612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=557082934 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/x bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delays.557082934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/48.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all.3796139690 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 1612945474 ps |
| CPU time | 52.6 seconds |
| Started | Oct 14 09:11:34 PM UTC 24 |
| Finished | Oct 14 09:12:29 PM UTC 24 |
| Peak memory | 216676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3796139690 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.3796139690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/48.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_error.3438761960 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 4855133101 ps |
| CPU time | 67.21 seconds |
| Started | Oct 14 09:11:36 PM UTC 24 |
| Finished | Oct 14 09:12:45 PM UTC 24 |
| Peak memory | 216748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3438761960 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.3438761960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/48.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.340396983 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 12043075625 ps |
| CPU time | 405.63 seconds |
| Started | Oct 14 09:11:36 PM UTC 24 |
| Finished | Oct 14 09:18:27 PM UTC 24 |
| Peak memory | 219112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=340396983 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_rand_reset.340396983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/48.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.269246825 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 81237284 ps |
| CPU time | 15.28 seconds |
| Started | Oct 14 09:11:43 PM UTC 24 |
| Finished | Oct 14 09:12:00 PM UTC 24 |
| Peak memory | 216840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=269246825 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_reset_error.269246825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/48.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/48.xbar_unmapped_addr.557704531 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 435631850 ps |
| CPU time | 17.15 seconds |
| Started | Oct 14 09:11:33 PM UTC 24 |
| Finished | Oct 14 09:11:52 PM UTC 24 |
| Peak memory | 214632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=557704531 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.557704531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/48.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_access_same_device.3858493770 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 735828794 ps |
| CPU time | 8.76 seconds |
| Started | Oct 14 09:11:53 PM UTC 24 |
| Finished | Oct 14 09:12:03 PM UTC 24 |
| Peak memory | 214636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3858493770 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device.3858493770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/49.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.3257082963 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 11539530212 ps |
| CPU time | 99.6 seconds |
| Started | Oct 14 09:11:53 PM UTC 24 |
| Finished | Oct 14 09:13:35 PM UTC 24 |
| Peak memory | 216740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3257082963 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device_slow_rsp.3257082963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/49.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.2085140940 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 467410294 ps |
| CPU time | 7.24 seconds |
| Started | Oct 14 09:11:57 PM UTC 24 |
| Finished | Oct 14 09:12:05 PM UTC 24 |
| Peak memory | 214628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2085140940 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_addr.2085140940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/49.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_error_random.845905400 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 118210200 ps |
| CPU time | 13.22 seconds |
| Started | Oct 14 09:11:57 PM UTC 24 |
| Finished | Oct 14 09:12:11 PM UTC 24 |
| Peak memory | 214856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=845905400 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.845905400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/49.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_random.3220773551 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 137552729 ps |
| CPU time | 3.45 seconds |
| Started | Oct 14 09:11:51 PM UTC 24 |
| Finished | Oct 14 09:11:56 PM UTC 24 |
| Peak memory | 214860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3220773551 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random.3220773551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/49.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_random_large_delays.2670494332 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 15364935788 ps |
| CPU time | 48.28 seconds |
| Started | Oct 14 09:11:51 PM UTC 24 |
| Finished | Oct 14 09:12:41 PM UTC 24 |
| Peak memory | 214696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2670494332 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.2670494332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/49.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_random_slow_rsp.2345080883 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 31174315154 ps |
| CPU time | 98.57 seconds |
| Started | Oct 14 09:11:51 PM UTC 24 |
| Finished | Oct 14 09:13:32 PM UTC 24 |
| Peak memory | 214692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2345080883 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.2345080883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/49.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_random_zero_delays.3814435915 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 83980873 ps |
| CPU time | 5.98 seconds |
| Started | Oct 14 09:11:51 PM UTC 24 |
| Finished | Oct 14 09:11:58 PM UTC 24 |
| Peak memory | 214616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3814435915 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_delays.3814435915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/49.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_same_source.290492856 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 1371324097 ps |
| CPU time | 31.49 seconds |
| Started | Oct 14 09:11:54 PM UTC 24 |
| Finished | Oct 14 09:12:27 PM UTC 24 |
| Peak memory | 214632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=290492856 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.290492856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/49.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke.1443190350 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 37650839 ps |
| CPU time | 3.4 seconds |
| Started | Oct 14 09:11:43 PM UTC 24 |
| Finished | Oct 14 09:11:48 PM UTC 24 |
| Peak memory | 214560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1443190350 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.1443190350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/49.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_large_delays.681293792 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 5700970306 ps |
| CPU time | 48.35 seconds |
| Started | Oct 14 09:11:45 PM UTC 24 |
| Finished | Oct 14 09:12:35 PM UTC 24 |
| Peak memory | 214680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=681293792 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.681293792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/49.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.657182623 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 4469858660 ps |
| CPU time | 32.18 seconds |
| Started | Oct 14 09:11:48 PM UTC 24 |
| Finished | Oct 14 09:12:22 PM UTC 24 |
| Peak memory | 214844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=657182623 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.657182623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/49.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.1404224938 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 87632147 ps |
| CPU time | 2.57 seconds |
| Started | Oct 14 09:11:45 PM UTC 24 |
| Finished | Oct 14 09:11:49 PM UTC 24 |
| Peak memory | 214600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1404224938 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delays.1404224938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/49.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all.3338161755 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 11449155243 ps |
| CPU time | 166.39 seconds |
| Started | Oct 14 09:11:57 PM UTC 24 |
| Finished | Oct 14 09:14:46 PM UTC 24 |
| Peak memory | 218792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3338161755 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.3338161755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/49.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_error.3239802694 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 2861184919 ps |
| CPU time | 43.25 seconds |
| Started | Oct 14 09:12:00 PM UTC 24 |
| Finished | Oct 14 09:12:45 PM UTC 24 |
| Peak memory | 216748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3239802694 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.3239802694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/49.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.3446637027 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 12334081013 ps |
| CPU time | 395.28 seconds |
| Started | Oct 14 09:12:00 PM UTC 24 |
| Finished | Oct 14 09:18:41 PM UTC 24 |
| Peak memory | 231392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3446637027 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_rand_reset.3446637027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/49.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_reset_error.2627928511 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 3919557712 ps |
| CPU time | 327.98 seconds |
| Started | Oct 14 09:12:00 PM UTC 24 |
| Finished | Oct 14 09:17:33 PM UTC 24 |
| Peak memory | 237540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2627928511 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_reset_error.2627928511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/49.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/49.xbar_unmapped_addr.2914973039 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 367262025 ps |
| CPU time | 12.94 seconds |
| Started | Oct 14 09:11:57 PM UTC 24 |
| Finished | Oct 14 09:12:11 PM UTC 24 |
| Peak memory | 216676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2914973039 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.2914973039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/49.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_access_same_device.3687431261 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 974309316 ps |
| CPU time | 44.19 seconds |
| Started | Oct 14 08:57:10 PM UTC 24 |
| Finished | Oct 14 08:57:56 PM UTC 24 |
| Peak memory | 216872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3687431261 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device.3687431261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/5.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_access_same_device_slow_rsp.1561707659 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 95087428188 ps |
| CPU time | 424.6 seconds |
| Started | Oct 14 08:57:10 PM UTC 24 |
| Finished | Oct 14 09:04:20 PM UTC 24 |
| Peak memory | 216740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1561707659 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device_slow_rsp.1561707659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/5.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_error_and_unmapped_addr.4213805444 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 152623500 ps |
| CPU time | 9.02 seconds |
| Started | Oct 14 08:57:12 PM UTC 24 |
| Finished | Oct 14 08:57:23 PM UTC 24 |
| Peak memory | 214640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4213805444 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr.4213805444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/5.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_error_random.751521160 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 689387061 ps |
| CPU time | 19.81 seconds |
| Started | Oct 14 08:57:10 PM UTC 24 |
| Finished | Oct 14 08:57:31 PM UTC 24 |
| Peak memory | 214632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=751521160 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.751521160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/5.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_random.4256243356 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 1405735212 ps |
| CPU time | 43.72 seconds |
| Started | Oct 14 08:57:08 PM UTC 24 |
| Finished | Oct 14 08:57:53 PM UTC 24 |
| Peak memory | 214628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4256243356 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random.4256243356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/5.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_random_large_delays.794621749 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 41503750605 ps |
| CPU time | 127.74 seconds |
| Started | Oct 14 08:57:10 PM UTC 24 |
| Finished | Oct 14 08:59:20 PM UTC 24 |
| Peak memory | 214884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=794621749 -assert nopostproc +UVM_ TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.794621749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/5.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_random_slow_rsp.2908187638 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 3411588695 ps |
| CPU time | 22.38 seconds |
| Started | Oct 14 08:57:10 PM UTC 24 |
| Finished | Oct 14 08:57:34 PM UTC 24 |
| Peak memory | 214692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2908187638 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.2908187638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/5.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_random_zero_delays.1922090354 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 84550042 ps |
| CPU time | 6.99 seconds |
| Started | Oct 14 08:57:08 PM UTC 24 |
| Finished | Oct 14 08:57:16 PM UTC 24 |
| Peak memory | 214616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1922090354 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_delays.1922090354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/5.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_same_source.2520465410 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 124209022 ps |
| CPU time | 2.9 seconds |
| Started | Oct 14 08:57:10 PM UTC 24 |
| Finished | Oct 14 08:57:14 PM UTC 24 |
| Peak memory | 214604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2520465410 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.2520465410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/5.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_smoke.2852168610 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 120907597 ps |
| CPU time | 4.54 seconds |
| Started | Oct 14 08:57:05 PM UTC 24 |
| Finished | Oct 14 08:57:11 PM UTC 24 |
| Peak memory | 214608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2852168610 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.2852168610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/5.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_smoke_large_delays.583008158 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 14969272824 ps |
| CPU time | 44.13 seconds |
| Started | Oct 14 08:57:05 PM UTC 24 |
| Finished | Oct 14 08:57:51 PM UTC 24 |
| Peak memory | 214684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=583008158 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.583008158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/5.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_smoke_slow_rsp.3178041097 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 7542312105 ps |
| CPU time | 22.86 seconds |
| Started | Oct 14 08:57:07 PM UTC 24 |
| Finished | Oct 14 08:57:32 PM UTC 24 |
| Peak memory | 214912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3178041097 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.3178041097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/5.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_smoke_zero_delays.4006982581 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 31037207 ps |
| CPU time | 2.63 seconds |
| Started | Oct 14 08:57:05 PM UTC 24 |
| Finished | Oct 14 08:57:09 PM UTC 24 |
| Peak memory | 214604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4006982581 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays.4006982581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/5.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_stress_all.1034297884 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 648558243 ps |
| CPU time | 25.16 seconds |
| Started | Oct 14 08:57:12 PM UTC 24 |
| Finished | Oct 14 08:57:39 PM UTC 24 |
| Peak memory | 216676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1034297884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.1034297884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/5.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_stress_all_with_error.2011484689 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 5027974264 ps |
| CPU time | 165.47 seconds |
| Started | Oct 14 08:57:13 PM UTC 24 |
| Finished | Oct 14 09:00:01 PM UTC 24 |
| Peak memory | 220840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2011484689 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.2011484689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/5.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_stress_all_with_reset_error.101064351 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 1214803335 ps |
| CPU time | 217.13 seconds |
| Started | Oct 14 08:57:13 PM UTC 24 |
| Finished | Oct 14 09:00:53 PM UTC 24 |
| Peak memory | 221092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=101064351 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_reset_error.101064351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/5.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/5.xbar_unmapped_addr.3076256602 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 139617091 ps |
| CPU time | 6.32 seconds |
| Started | Oct 14 08:57:10 PM UTC 24 |
| Finished | Oct 14 08:57:18 PM UTC 24 |
| Peak memory | 214760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3076256602 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.3076256602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/5.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_access_same_device.1572138150 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 1021728713 ps |
| CPU time | 28.85 seconds |
| Started | Oct 14 08:57:17 PM UTC 24 |
| Finished | Oct 14 08:57:48 PM UTC 24 |
| Peak memory | 214632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1572138150 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device.1572138150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/6.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_access_same_device_slow_rsp.1462275263 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 4147429287 ps |
| CPU time | 26.32 seconds |
| Started | Oct 14 08:57:17 PM UTC 24 |
| Finished | Oct 14 08:57:45 PM UTC 24 |
| Peak memory | 214692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1462275263 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device_slow_rsp.1462275263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/6.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_error_and_unmapped_addr.178061598 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 4748129500 ps |
| CPU time | 24.13 seconds |
| Started | Oct 14 08:57:22 PM UTC 24 |
| Finished | Oct 14 08:57:47 PM UTC 24 |
| Peak memory | 214696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=178061598 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr.178061598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/6.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_error_random.230701110 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 106816613 ps |
| CPU time | 13.21 seconds |
| Started | Oct 14 08:57:20 PM UTC 24 |
| Finished | Oct 14 08:57:34 PM UTC 24 |
| Peak memory | 214628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=230701110 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.230701110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/6.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_random.1919688801 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 826603404 ps |
| CPU time | 50.47 seconds |
| Started | Oct 14 08:57:15 PM UTC 24 |
| Finished | Oct 14 08:58:08 PM UTC 24 |
| Peak memory | 216684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1919688801 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random.1919688801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/6.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_random_large_delays.2277077530 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 19772861716 ps |
| CPU time | 99.28 seconds |
| Started | Oct 14 08:57:15 PM UTC 24 |
| Finished | Oct 14 08:58:56 PM UTC 24 |
| Peak memory | 214700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2277077530 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.2277077530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/6.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_random_slow_rsp.2047773763 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 16818620805 ps |
| CPU time | 66.47 seconds |
| Started | Oct 14 08:57:17 PM UTC 24 |
| Finished | Oct 14 08:58:25 PM UTC 24 |
| Peak memory | 214888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2047773763 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.2047773763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/6.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_random_zero_delays.2186412883 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 310915249 ps |
| CPU time | 22.34 seconds |
| Started | Oct 14 08:57:15 PM UTC 24 |
| Finished | Oct 14 08:57:39 PM UTC 24 |
| Peak memory | 214628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2186412883 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_delays.2186412883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/6.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_same_source.2280906258 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 254929450 ps |
| CPU time | 20.31 seconds |
| Started | Oct 14 08:57:17 PM UTC 24 |
| Finished | Oct 14 08:57:39 PM UTC 24 |
| Peak memory | 214628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2280906258 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.2280906258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/6.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_smoke.3768420371 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 236410645 ps |
| CPU time | 6.11 seconds |
| Started | Oct 14 08:57:13 PM UTC 24 |
| Finished | Oct 14 08:57:20 PM UTC 24 |
| Peak memory | 214868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3768420371 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.3768420371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/6.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_smoke_large_delays.4115745998 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 7221266295 ps |
| CPU time | 45.44 seconds |
| Started | Oct 14 08:57:13 PM UTC 24 |
| Finished | Oct 14 08:58:00 PM UTC 24 |
| Peak memory | 214872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4115745998 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.4115745998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/6.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_smoke_slow_rsp.367442640 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 3682380160 ps |
| CPU time | 37.5 seconds |
| Started | Oct 14 08:57:15 PM UTC 24 |
| Finished | Oct 14 08:57:54 PM UTC 24 |
| Peak memory | 214652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=367442640 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.367442640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/6.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_smoke_zero_delays.3722905628 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 33173858 ps |
| CPU time | 3.06 seconds |
| Started | Oct 14 08:57:13 PM UTC 24 |
| Finished | Oct 14 08:57:17 PM UTC 24 |
| Peak memory | 214604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3722905628 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays.3722905628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/6.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_stress_all.2577225300 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 2872118012 ps |
| CPU time | 51.98 seconds |
| Started | Oct 14 08:57:24 PM UTC 24 |
| Finished | Oct 14 08:58:18 PM UTC 24 |
| Peak memory | 216844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2577225300 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.2577225300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/6.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_stress_all_with_error.351514017 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 14881627407 ps |
| CPU time | 157.76 seconds |
| Started | Oct 14 08:57:24 PM UTC 24 |
| Finished | Oct 14 09:00:05 PM UTC 24 |
| Peak memory | 216940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=351514017 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.351514017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/6.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_stress_all_with_rand_reset.1648849550 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 1276746312 ps |
| CPU time | 149.43 seconds |
| Started | Oct 14 08:57:24 PM UTC 24 |
| Finished | Oct 14 08:59:56 PM UTC 24 |
| Peak memory | 218868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1648849550 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_rand_reset.1648849550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/6.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_stress_all_with_reset_error.1444690886 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 196784199 ps |
| CPU time | 79.57 seconds |
| Started | Oct 14 08:57:26 PM UTC 24 |
| Finished | Oct 14 08:58:48 PM UTC 24 |
| Peak memory | 218728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1444690886 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_reset_error.1444690886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/6.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/6.xbar_unmapped_addr.1718277956 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 766503501 ps |
| CPU time | 39.68 seconds |
| Started | Oct 14 08:57:22 PM UTC 24 |
| Finished | Oct 14 08:58:03 PM UTC 24 |
| Peak memory | 216684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1718277956 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.1718277956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/6.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_access_same_device.427917187 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 510366710 ps |
| CPU time | 13.39 seconds |
| Started | Oct 14 08:57:34 PM UTC 24 |
| Finished | Oct 14 08:57:48 PM UTC 24 |
| Peak memory | 216676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=427917187 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xba r_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device.427917187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/7.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_access_same_device_slow_rsp.3089535679 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 16258595369 ps |
| CPU time | 88.44 seconds |
| Started | Oct 14 08:57:35 PM UTC 24 |
| Finished | Oct 14 08:59:05 PM UTC 24 |
| Peak memory | 214756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3089535679 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device_slow_rsp.3089535679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/7.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_error_and_unmapped_addr.2544296592 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 6238378640 ps |
| CPU time | 26.33 seconds |
| Started | Oct 14 08:57:39 PM UTC 24 |
| Finished | Oct 14 08:58:07 PM UTC 24 |
| Peak memory | 214956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2544296592 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr.2544296592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/7.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_error_random.4066916182 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 3117392502 ps |
| CPU time | 15.99 seconds |
| Started | Oct 14 08:57:36 PM UTC 24 |
| Finished | Oct 14 08:57:53 PM UTC 24 |
| Peak memory | 214816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4066916182 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.4066916182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/7.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_random.2930932837 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 1015379273 ps |
| CPU time | 22.39 seconds |
| Started | Oct 14 08:57:32 PM UTC 24 |
| Finished | Oct 14 08:57:55 PM UTC 24 |
| Peak memory | 214828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2930932837 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random.2930932837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/7.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_random_large_delays.3638427338 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 35256217172 ps |
| CPU time | 119.67 seconds |
| Started | Oct 14 08:57:33 PM UTC 24 |
| Finished | Oct 14 08:59:35 PM UTC 24 |
| Peak memory | 214696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3638427338 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.3638427338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/7.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_random_zero_delays.3313593172 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 170874101 ps |
| CPU time | 6.19 seconds |
| Started | Oct 14 08:57:33 PM UTC 24 |
| Finished | Oct 14 08:57:40 PM UTC 24 |
| Peak memory | 214620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3313593172 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_delays.3313593172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/7.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_same_source.500816638 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 2013712456 ps |
| CPU time | 29.33 seconds |
| Started | Oct 14 08:57:35 PM UTC 24 |
| Finished | Oct 14 08:58:06 PM UTC 24 |
| Peak memory | 214624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=500816638 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.500816638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/7.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_smoke.732046645 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 173631396 ps |
| CPU time | 5.16 seconds |
| Started | Oct 14 08:57:27 PM UTC 24 |
| Finished | Oct 14 08:57:33 PM UTC 24 |
| Peak memory | 214604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=732046645 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.732046645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/7.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_smoke_large_delays.3717236527 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 8271717447 ps |
| CPU time | 45.49 seconds |
| Started | Oct 14 08:57:27 PM UTC 24 |
| Finished | Oct 14 08:58:14 PM UTC 24 |
| Peak memory | 214680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3717236527 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.3717236527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/7.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_smoke_slow_rsp.2105666638 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 16783967549 ps |
| CPU time | 41.52 seconds |
| Started | Oct 14 08:57:28 PM UTC 24 |
| Finished | Oct 14 08:58:11 PM UTC 24 |
| Peak memory | 214656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2105666638 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.2105666638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/7.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_smoke_zero_delays.520560762 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 79087968 ps |
| CPU time | 3.4 seconds |
| Started | Oct 14 08:57:27 PM UTC 24 |
| Finished | Oct 14 08:57:32 PM UTC 24 |
| Peak memory | 214580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=520560762 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/x bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays.520560762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/7.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_stress_all.1372499565 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 8945762165 ps |
| CPU time | 190.26 seconds |
| Started | Oct 14 08:57:39 PM UTC 24 |
| Finished | Oct 14 09:00:53 PM UTC 24 |
| Peak memory | 220840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1372499565 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.1372499565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/7.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_stress_all_with_error.3409619107 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 22840357400 ps |
| CPU time | 194.55 seconds |
| Started | Oct 14 08:57:40 PM UTC 24 |
| Finished | Oct 14 09:00:57 PM UTC 24 |
| Peak memory | 216744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3409619107 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.3409619107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/7.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_stress_all_with_rand_reset.3115940310 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 9347893765 ps |
| CPU time | 392.7 seconds |
| Started | Oct 14 08:57:40 PM UTC 24 |
| Finished | Oct 14 09:04:17 PM UTC 24 |
| Peak memory | 221152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3115940310 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_rand_reset.3115940310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/7.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_stress_all_with_reset_error.1179965433 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 267922913 ps |
| CPU time | 96.51 seconds |
| Started | Oct 14 08:57:41 PM UTC 24 |
| Finished | Oct 14 08:59:19 PM UTC 24 |
| Peak memory | 218928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1179965433 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_reset_error.1179965433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/7.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/7.xbar_unmapped_addr.324185571 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 109957891 ps |
| CPU time | 8.3 seconds |
| Started | Oct 14 08:57:36 PM UTC 24 |
| Finished | Oct 14 08:57:46 PM UTC 24 |
| Peak memory | 216676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=324185571 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_mai n-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.324185571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/7.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_access_same_device.1909984567 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 151809449 ps |
| CPU time | 27.79 seconds |
| Started | Oct 14 08:57:51 PM UTC 24 |
| Finished | Oct 14 08:58:20 PM UTC 24 |
| Peak memory | 214632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1909984567 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device.1909984567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/8.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_access_same_device_slow_rsp.553398943 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 11312254900 ps |
| CPU time | 98.11 seconds |
| Started | Oct 14 08:57:52 PM UTC 24 |
| Finished | Oct 14 08:59:32 PM UTC 24 |
| Peak memory | 216744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=553398943 -assert nopostproc +UVM_TEST NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device_slow_rsp.553398943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/8.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_error_and_unmapped_addr.1551761569 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 653612138 ps |
| CPU time | 21.35 seconds |
| Started | Oct 14 08:57:56 PM UTC 24 |
| Finished | Oct 14 08:58:19 PM UTC 24 |
| Peak memory | 214892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1551761569 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr.1551761569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/8.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_error_random.3519035047 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 342179349 ps |
| CPU time | 16.1 seconds |
| Started | Oct 14 08:57:54 PM UTC 24 |
| Finished | Oct 14 08:58:11 PM UTC 24 |
| Peak memory | 214624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3519035047 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.3519035047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/8.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_random.1595763373 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 6097627826 ps |
| CPU time | 40.66 seconds |
| Started | Oct 14 08:57:48 PM UTC 24 |
| Finished | Oct 14 08:58:30 PM UTC 24 |
| Peak memory | 214696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1595763373 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random.1595763373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/8.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_random_large_delays.3841467459 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 16943391427 ps |
| CPU time | 100.76 seconds |
| Started | Oct 14 08:57:48 PM UTC 24 |
| Finished | Oct 14 08:59:31 PM UTC 24 |
| Peak memory | 214764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3841467459 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.3841467459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/8.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_random_slow_rsp.3827704498 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 1078497037 ps |
| CPU time | 17.1 seconds |
| Started | Oct 14 08:57:50 PM UTC 24 |
| Finished | Oct 14 08:58:08 PM UTC 24 |
| Peak memory | 214796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3827704498 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.3827704498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/8.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_random_zero_delays.824225014 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 338614199 ps |
| CPU time | 23.57 seconds |
| Started | Oct 14 08:57:48 PM UTC 24 |
| Finished | Oct 14 08:58:13 PM UTC 24 |
| Peak memory | 214620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=824225014 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_delays.824225014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/8.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_same_source.1203988576 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 2995273744 ps |
| CPU time | 25.4 seconds |
| Started | Oct 14 08:57:54 PM UTC 24 |
| Finished | Oct 14 08:58:21 PM UTC 24 |
| Peak memory | 214696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1203988576 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.1203988576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/8.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_smoke.1108456214 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 149112033 ps |
| CPU time | 4.83 seconds |
| Started | Oct 14 08:57:42 PM UTC 24 |
| Finished | Oct 14 08:57:48 PM UTC 24 |
| Peak memory | 214608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1108456214 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.1108456214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/8.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_smoke_large_delays.3018904214 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 6036028835 ps |
| CPU time | 31.94 seconds |
| Started | Oct 14 08:57:46 PM UTC 24 |
| Finished | Oct 14 08:58:19 PM UTC 24 |
| Peak memory | 214872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3018904214 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.3018904214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/8.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_smoke_slow_rsp.1773794924 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 13106928671 ps |
| CPU time | 30.82 seconds |
| Started | Oct 14 08:57:47 PM UTC 24 |
| Finished | Oct 14 08:58:19 PM UTC 24 |
| Peak memory | 214656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1773794924 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.1773794924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/8.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_smoke_zero_delays.2138188797 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 37229467 ps |
| CPU time | 2.84 seconds |
| Started | Oct 14 08:57:46 PM UTC 24 |
| Finished | Oct 14 08:57:50 PM UTC 24 |
| Peak memory | 214796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2138188797 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays.2138188797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/8.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_stress_all.108382911 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 1362426436 ps |
| CPU time | 102.17 seconds |
| Started | Oct 14 08:57:56 PM UTC 24 |
| Finished | Oct 14 08:59:40 PM UTC 24 |
| Peak memory | 218728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=108382911 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.108382911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/8.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_stress_all_with_error.970171402 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 34444840392 ps |
| CPU time | 191.52 seconds |
| Started | Oct 14 08:58:01 PM UTC 24 |
| Finished | Oct 14 09:01:16 PM UTC 24 |
| Peak memory | 216744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=970171402 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.970171402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/8.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_stress_all_with_rand_reset.2055786954 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 7177961799 ps |
| CPU time | 353.83 seconds |
| Started | Oct 14 08:58:00 PM UTC 24 |
| Finished | Oct 14 09:03:59 PM UTC 24 |
| Peak memory | 220836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2055786954 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_rand_reset.2055786954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/8.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_stress_all_with_reset_error.1157472391 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 2485007730 ps |
| CPU time | 242.79 seconds |
| Started | Oct 14 08:58:04 PM UTC 24 |
| Finished | Oct 14 09:02:10 PM UTC 24 |
| Peak memory | 221156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1157472391 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_reset_error.1157472391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/8.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/8.xbar_unmapped_addr.2499629891 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 397209580 ps |
| CPU time | 15.38 seconds |
| Started | Oct 14 08:57:55 PM UTC 24 |
| Finished | Oct 14 08:58:12 PM UTC 24 |
| Peak memory | 216680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2499629891 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.2499629891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/8.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_access_same_device.4121283328 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 662326766 ps |
| CPU time | 21.89 seconds |
| Started | Oct 14 08:58:13 PM UTC 24 |
| Finished | Oct 14 08:58:36 PM UTC 24 |
| Peak memory | 216680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4121283328 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xb ar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device.4121283328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/9.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_access_same_device_slow_rsp.2550359528 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 12267085797 ps |
| CPU time | 97.33 seconds |
| Started | Oct 14 08:58:13 PM UTC 24 |
| Finished | Oct 14 08:59:52 PM UTC 24 |
| Peak memory | 216740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2550359528 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device_slow_rsp.2550359528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/9.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_error_and_unmapped_addr.3298986335 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 49911671 ps |
| CPU time | 5.72 seconds |
| Started | Oct 14 08:58:15 PM UTC 24 |
| Finished | Oct 14 08:58:22 PM UTC 24 |
| Peak memory | 214892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3298986335 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr.3298986335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/9.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_error_random.2893914552 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 1618787538 ps |
| CPU time | 32.25 seconds |
| Started | Oct 14 08:58:14 PM UTC 24 |
| Finished | Oct 14 08:58:47 PM UTC 24 |
| Peak memory | 214624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2893914552 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.2893914552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/9.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_random.1678437960 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 961980492 ps |
| CPU time | 31.85 seconds |
| Started | Oct 14 08:58:09 PM UTC 24 |
| Finished | Oct 14 08:58:43 PM UTC 24 |
| Peak memory | 214632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1678437960 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random.1678437960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/9.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_random_large_delays.1795387584 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 2248753486 ps |
| CPU time | 19.39 seconds |
| Started | Oct 14 08:58:12 PM UTC 24 |
| Finished | Oct 14 08:58:33 PM UTC 24 |
| Peak memory | 214888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1795387584 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.1795387584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/9.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_random_slow_rsp.3678096198 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 7597265671 ps |
| CPU time | 42.97 seconds |
| Started | Oct 14 08:58:12 PM UTC 24 |
| Finished | Oct 14 08:58:57 PM UTC 24 |
| Peak memory | 214692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3678096198 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.3678096198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/9.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_random_zero_delays.1083665620 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 135202998 ps |
| CPU time | 13.61 seconds |
| Started | Oct 14 08:58:09 PM UTC 24 |
| Finished | Oct 14 08:58:24 PM UTC 24 |
| Peak memory | 214620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1083665620 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_delays.1083665620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/9.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_same_source.134401229 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 3265463384 ps |
| CPU time | 38.16 seconds |
| Started | Oct 14 08:58:14 PM UTC 24 |
| Finished | Oct 14 08:58:53 PM UTC 24 |
| Peak memory | 214692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=134401229 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.134401229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/9.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_smoke.240858058 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 649861837 ps |
| CPU time | 5.53 seconds |
| Started | Oct 14 08:58:07 PM UTC 24 |
| Finished | Oct 14 08:58:13 PM UTC 24 |
| Peak memory | 214800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=240858058 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.240858058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/9.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_smoke_large_delays.256643743 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 9901102604 ps |
| CPU time | 34.47 seconds |
| Started | Oct 14 08:58:08 PM UTC 24 |
| Finished | Oct 14 08:58:44 PM UTC 24 |
| Peak memory | 214684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=256643743 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_m ain-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.256643743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/9.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_smoke_slow_rsp.202257739 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 3955803805 ps |
| CPU time | 38.48 seconds |
| Started | Oct 14 08:58:08 PM UTC 24 |
| Finished | Oct 14 08:58:48 PM UTC 24 |
| Peak memory | 214656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=202257739 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.202257739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/9.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_smoke_zero_delays.557788877 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 29717416 ps |
| CPU time | 3.11 seconds |
| Started | Oct 14 08:58:08 PM UTC 24 |
| Finished | Oct 14 08:58:12 PM UTC 24 |
| Peak memory | 214588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=557788877 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/x bar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays.557788877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/9.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_stress_all.1915680690 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 1784443185 ps |
| CPU time | 67.5 seconds |
| Started | Oct 14 08:58:15 PM UTC 24 |
| Finished | Oct 14 08:59:24 PM UTC 24 |
| Peak memory | 216676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1915680690 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.1915680690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/9.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_stress_all_with_error.157386293 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 3553492609 ps |
| CPU time | 147.22 seconds |
| Started | Oct 14 08:58:19 PM UTC 24 |
| Finished | Oct 14 09:00:50 PM UTC 24 |
| Peak memory | 214696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=157386293 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.157386293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/9.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_stress_all_with_rand_reset.3237902121 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 14450897050 ps |
| CPU time | 414.12 seconds |
| Started | Oct 14 08:58:18 PM UTC 24 |
| Finished | Oct 14 09:05:18 PM UTC 24 |
| Peak memory | 220308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3237902121 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_rand_reset.3237902121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/9.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_stress_all_with_reset_error.3689103670 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 486026020 ps |
| CPU time | 143.74 seconds |
| Started | Oct 14 08:58:20 PM UTC 24 |
| Finished | Oct 14 09:00:47 PM UTC 24 |
| Peak memory | 220776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3689103670 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_reset_error.3689103670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/9.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/coverage/xbar_build_mode/9.xbar_unmapped_addr.3732679653 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 132505806 ps |
| CPU time | 17.49 seconds |
| Started | Oct 14 08:58:14 PM UTC 24 |
| Finished | Oct 14 08:58:33 PM UTC 24 |
| Peak memory | 214632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3732679653 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ma in-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.3732679653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/9.xbar_unmapped_addr/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |