ALERT_HANDLER Simulation Results

Sunday December 24 2023 20:02:26 UTC

GitHub Revision: 671f2b57e2

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 96716765175854174075659971574604807242747408006700796360560480210023744343645

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.079m	2.017ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	8.730s	419.381us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	9.080s	120.900us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	7.307m	53.016ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	4.426m	4.618ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	7.070s	78.900us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	9.080s	120.900us	20	20	100.00
		alert_handler_csr_aliasing	4.426m	4.618ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	4.819m	5.145ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.086m	1.252ms	50	50	100.00
V2	entropy	alert_handler_entropy	53.064m	204.929ms	50	50	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.079m	2.191ms	50	50	100.00
V2	clk_skew	alert_handler_smoke	1.079m	2.017ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.220m	2.565ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.246m	4.689ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	11.460m	98.220ms	50	50	100.00
V2	lpg	alert_handler_lpg	57.140m	220.065ms	50	50	100.00
		alert_handler_lpg_stub_clk	46.218m	152.498ms	50	50	100.00
V2	stress_all	alert_handler_stress_all	1.193h	296.851ms	49	50	98.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	1.204m	3.306ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	3.970s	91.166us	20	20	100.00
V2	intr_test	alert_handler_intr_test	1.640s	9.320us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	18.840s	1.120ms	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	18.840s	1.120ms	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	8.730s	419.381us	5	5	100.00
		alert_handler_csr_rw	9.080s	120.900us	20	20	100.00
		alert_handler_csr_aliasing	4.426m	4.618ms	5	5	100.00
		alert_handler_same_csr_outstanding	38.160s	670.167us	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	8.730s	419.381us	5	5	100.00
		alert_handler_csr_rw	9.080s	120.900us	20	20	100.00
		alert_handler_csr_aliasing	4.426m	4.618ms	5	5	100.00
		alert_handler_same_csr_outstanding	38.160s	670.167us	20	20	100.00
V2		TOTAL			629	630	99.84
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	5.913m	22.926ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	5.913m	22.926ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	5.913m	22.926ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	5.913m	22.926ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	20.806m	34.692ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	2.079m	3.022ms	5	5	100.00
		alert_handler_tl_intg_err	1.289m	5.175ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.289m	5.175ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	5.913m	22.926ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.079m	2.017ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.079m	2.017ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.079m	2.017ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.079m	2.017ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.079m	2.191ms	50	50	100.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	57.140m	220.065ms	50	50	100.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.079m	2.191ms	50	50	100.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	53.064m	204.929ms	50	50	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	53.064m	204.929ms	50	50	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	2.079m	3.022ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	2.079m	3.022ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	2.079m	3.022ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	2.079m	3.022ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	2.079m	3.022ms	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	2.079m	3.022ms	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	2.079m	3.022ms	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	2.079m	3.022ms	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	2.079m	3.022ms	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	2.892h	242.850ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			848	850	99.76

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	14	93.33
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.69	99.99	98.72	100.00	100.00	100.00	99.38	99.72

Failure Buckets

• UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_d, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:

  • Test alert_handler_stress_all has 1 failures.

    • 6.alert_handler_stress_all.26247916229016884630886714193805569812995649230005638982969053526861504841089
      Line 285, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/6.alert_handler_stress_all/latest/run.log

        UVM_ERROR @ 9340556851 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_d, is_local_err 1, local_alert_type LocalEscIntFail
        UVM_INFO @ 9340556851 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_c, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:

  • Test alert_handler_stress_all_with_rand_reset has 1 failures.

    • 31.alert_handler_stress_all_with_rand_reset.675996949020073816102606688883461903667762797207343987514982377215696648638
      Line 1105, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/31.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 31153229980 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_c, is_local_err 1, local_alert_type LocalEscIntFail
        UVM_INFO @ 31153229980 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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