Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.72	100.00	93.62		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[1].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[0].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	99.56	100.00	97.78		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.56	100.00	97.78		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.63	100.00	97.78	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	44	93.62
Logical	47	44	93.62
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T5

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Covered	T19
1	1	1	Covered	T1,T3,T5

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T17,T18
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T17,T18,T7
1	1	1	Covered	T5,T17,T18

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T5,T17,T18
0	1	Covered	T7,T16,T20
1	0	Covered	T7,T16,T21

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T17,T18
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T7,T16,T21

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T17,T18
1	0	Covered	T22,T23,T24
1	1	Covered	T7,T16,T20

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T3,T4,T7

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T17,T7,T6

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T3,T17,T7

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T4,T17
1	Covered	T1,T5,T7

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T11,T12

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T3,T5

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T3,T5,T17

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T3,T17

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T3,T5

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T10,T11,T12
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T1,T3,T5
Phase1St	193	Covered	T1,T3,T5
Phase2St	210	Covered	T1,T3,T5
Phase3St	228	Covered	T1,T3,T5
TerminalSt	244	Covered	T1,T3,T5
TimeoutSt	154	Covered	T5,T17,T18

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	279	Covered	T10,T11,T12
IdleSt->Phase0St	147	Covered	T1,T3,T5
IdleSt->TimeoutSt	154	Covered	T5,T17,T18
Phase0St->FsmErrorSt	279	Not Covered
Phase0St->IdleSt	189	Covered	T16,T25,T26
Phase0St->Phase1St	193	Covered	T1,T3,T5
Phase1St->FsmErrorSt	279	Not Covered
Phase1St->IdleSt	206	Covered	T14,T27,T28
Phase1St->Phase2St	210	Covered	T1,T3,T5
Phase2St->FsmErrorSt	279	Not Covered
Phase2St->IdleSt	224	Covered	T7,T16,T29
Phase2St->Phase3St	228	Covered	T1,T3,T5
Phase3St->FsmErrorSt	279	Not Covered
Phase3St->IdleSt	240	Covered	T16,T30,T31
Phase3St->TerminalSt	244	Covered	T1,T3,T5
TerminalSt->FsmErrorSt	279	Not Covered
TerminalSt->IdleSt	256	Covered	T4,T17,T7
TimeoutSt->FsmErrorSt	279	Not Covered
TimeoutSt->IdleSt	176	Covered	T5,T17,T18
TimeoutSt->Phase0St	167	Covered	T7,T15,T16

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T5
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T17,T18
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T7,T15,T16
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T5,T17,T18
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T5,T17,T18
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T16,T25,T26
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T3,T5
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T3,T5
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T14,T27,T28
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T3,T5
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T3,T5
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T7,T16,T29
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T3,T5
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T3,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T16,T30,T31
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T3,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T3,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T4,T17,T7
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T3,T5
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	1181	0	0
CheckAccumTrig0_A	2147483647	2376	0	0
CheckAccumTrig1_A	2147483647	125	0	0
CheckClr_A	2147483647	1114	0	0
CheckEn_A	2147483647	1152747158	0	0
CheckPhase0_A	2147483647	2715	0	0
CheckPhase1_A	2147483647	2645	0	0
CheckPhase2_A	2147483647	2588	0	0
CheckPhase3_A	2147483647	2547	0	0
CheckTimeout0_A	2147483647	3832	0	0
CheckTimeoutSt1_A	2147483647	450779	0	0
CheckTimeoutSt2_A	2147483647	3433	0	0
CheckTimeoutStTrig_A	2147483647	267	0	0
ErrorStAllEscAsserted_A	2147483647	6458	0	0
ErrorStIsTerminal_A	2147483647	5378	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1181	0	0
T10	222496	244	0	0
T11	0	293	0	0
T12	0	267	0	0
T32	0	121	0	0
T33	0	256	0	0
T34	113408	0	0	0
T35	910304	0	0	0
T36	556632	0	0	0
T37	2191268	0	0	0
T38	294452	0	0	0
T39	497544	0	0	0
T40	660376	0	0	0
T41	566932	0	0	0
T42	173476	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2376	0	0
T1	509945	1	0	0
T2	30947	0	0	0
T3	702024	2	0	0
T4	948312	2	0	0
T5	60620	1	0	0
T6	881900	1	0	0
T7	656040	18	0	0
T8	239302	4	0	0
T13	431060	2	0	0
T14	1472469	10	0	0
T15	1621486	4	0	0
T16	0	15	0	0
T17	198808	3	0	0
T18	160408	0	0	0
T20	0	3	0	0
T21	0	8	0	0
T43	270906	1	0	0
T44	420698	3	0	0
T45	0	5	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	125	0	0
T6	440950	0	0	0
T7	328020	2	0	0
T8	358953	0	0	0
T9	747501	0	0	0
T13	215530	0	0	0
T14	981646	0	0	0
T15	2432229	0	0	0
T16	3830716	3	0	0
T20	82802	0	0	0
T21	307324	2	0	0
T27	462299	0	0	0
T28	0	1	0	0
T29	9530	0	0	0
T43	180604	0	0	0
T44	1262094	0	0	0
T45	779314	0	0	0
T46	0	3	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	3	0	0
T55	0	1	0	0
T56	0	3	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	2	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	148614	0	0	0
T64	2472	0	0	0
T65	122730	0	0	0
T66	41642	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1114	0	0
T4	316104	1	0	0
T6	661425	0	0	0
T7	492030	8	0	0
T8	478604	1	0	0
T13	323295	1	0	0
T14	1963292	7	0	0
T15	3242972	2	0	0
T16	1915358	9	0	0
T17	99404	1	0	0
T18	80204	0	0	0
T20	41401	1	0	0
T21	0	11	0	0
T22	0	4	0	0
T25	0	9	0	0
T27	0	11	0	0
T29	4765	2	0	0
T43	270906	0	0	0
T44	1262094	0	0	0
T45	389657	3	0	0
T63	99076	0	0	0
T64	1236	0	0	0
T66	0	1	0	0
T67	0	3	0	0
T68	0	6	0	0
T69	0	1	0	0
T70	0	1	0	0
T71	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1152747158	0	0
T1	2039780	1409146	0	0
T2	123788	59647	0	0
T3	1404048	725200	0	0
T4	1264416	959506	0	0
T5	121240	93653	0	0
T6	881900	667443	0	0
T7	656040	527353	0	0
T13	431060	325595	0	0
T17	198808	126232	0	0
T18	160408	65916	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2715	0	0
T1	509945	1	0	0
T2	30947	0	0	0
T3	702024	2	0	0
T4	948312	2	0	0
T5	60620	1	0	0
T6	881900	1	0	0
T7	656040	23	0	0
T8	239302	4	0	0
T13	431060	2	0	0
T14	1472469	10	0	0
T15	1621486	6	0	0
T16	0	19	0	0
T17	198808	3	0	0
T18	160408	0	0	0
T20	0	3	0	0
T21	0	7	0	0
T43	270906	1	0	0
T44	420698	3	0	0
T45	0	5	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2645	0	0
T1	509945	1	0	0
T2	30947	0	0	0
T3	702024	2	0	0
T4	948312	2	0	0
T5	60620	1	0	0
T6	881900	1	0	0
T7	656040	23	0	0
T8	239302	4	0	0
T13	431060	2	0	0
T14	1472469	9	0	0
T15	1621486	6	0	0
T16	0	19	0	0
T17	198808	3	0	0
T18	160408	0	0	0
T20	0	3	0	0
T21	0	7	0	0
T43	270906	1	0	0
T44	420698	3	0	0
T45	0	5	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2588	0	0
T1	509945	1	0	0
T2	30947	0	0	0
T3	702024	2	0	0
T4	948312	2	0	0
T5	60620	1	0	0
T6	881900	1	0	0
T7	656040	21	0	0
T8	239302	4	0	0
T13	431060	2	0	0
T14	1472469	9	0	0
T15	1621486	6	0	0
T16	0	18	0	0
T17	198808	3	0	0
T18	160408	0	0	0
T20	0	3	0	0
T21	0	7	0	0
T43	270906	1	0	0
T44	420698	3	0	0
T45	0	5	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2547	0	0
T1	509945	1	0	0
T2	30947	0	0	0
T3	702024	2	0	0
T4	948312	2	0	0
T5	60620	1	0	0
T6	881900	1	0	0
T7	656040	21	0	0
T8	239302	4	0	0
T13	431060	2	0	0
T14	1472469	9	0	0
T15	1621486	6	0	0
T16	0	17	0	0
T17	198808	3	0	0
T18	160408	0	0	0
T20	0	3	0	0
T21	0	7	0	0
T43	270906	1	0	0
T44	420698	3	0	0
T45	0	5	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3832	0	0
T4	316104	0	0	0
T5	30310	1	0	0
T6	881900	0	0	0
T7	656040	20	0	0
T8	358953	0	0	0
T13	431060	0	0	0
T14	1963292	0	0	0
T15	3242972	7	0	0
T16	0	30	0	0
T17	149106	2	0	0
T18	160408	20	0	0
T20	0	1	0	0
T21	0	6	0	0
T22	0	1	0	0
T23	0	7	0	0
T25	0	7	0	0
T27	0	16	0	0
T28	0	29	0	0
T43	361208	0	0	0
T44	1262094	0	0	0
T45	0	2	0	0
T46	0	4	0	0
T63	49538	0	0	0
T66	0	3	0	0
T72	0	3	0	0
T73	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	450779	0	0
T4	316104	0	0	0
T5	30310	224	0	0
T6	881900	0	0	0
T7	656040	2366	0	0
T8	358953	0	0	0
T13	431060	0	0	0
T14	1963292	0	0	0
T15	3242972	463	0	0
T16	0	6533	0	0
T17	149106	219	0	0
T18	160408	1327	0	0
T20	0	7	0	0
T21	0	639	0	0
T22	0	110	0	0
T23	0	1087	0	0
T25	0	1832	0	0
T27	0	2232	0	0
T28	0	3104	0	0
T43	361208	0	0	0
T44	1262094	0	0	0
T45	0	201	0	0
T46	0	1018	0	0
T63	49538	0	0	0
T66	0	171	0	0
T72	0	351	0	0
T73	0	178	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3433	0	0
T4	316104	0	0	0
T5	30310	1	0	0
T6	881900	0	0	0
T7	656040	15	0	0
T8	358953	0	0	0
T13	431060	0	0	0
T14	1963292	0	0	0
T15	3242972	5	0	0
T16	0	21	0	0
T17	149106	2	0	0
T18	160408	20	0	0
T21	0	4	0	0
T22	0	1	0	0
T23	0	5	0	0
T25	0	7	0	0
T27	0	14	0	0
T28	0	28	0	0
T43	361208	0	0	0
T44	1262094	0	0	0
T45	0	2	0	0
T46	0	2	0	0
T47	0	1	0	0
T63	49538	0	0	0
T66	0	3	0	0
T72	0	3	0	0
T73	0	7	0	0
T74	0	2	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	267	0	0
T6	440950	0	0	0
T7	328020	3	0	0
T8	239302	0	0	0
T13	215530	0	0	0
T14	981646	0	0	0
T15	1621486	0	0	0
T16	2873037	5	0	0
T20	0	1	0	0
T22	0	1	0	0
T23	0	5	0	0
T25	430616	0	0	0
T26	0	1	0	0
T27	924598	2	0	0
T28	0	1	0	0
T43	180604	0	0	0
T44	841396	0	0	0
T46	0	5	0	0
T47	0	3	0	0
T50	0	2	0	0
T52	0	1	0	0
T54	0	5	0	0
T63	99076	0	0	0
T64	1236	0	0	0
T67	435338	0	0	0
T68	136219	0	0	0
T69	80226	0	0	0
T73	0	1	0	0
T74	48493	0	0	0
T75	0	2	0	0
T76	0	1	0	0
T77	0	1	0	0
T78	0	1	0	0
T79	0	1	0	0
T80	0	4	0	0
T81	0	3	0	0
T82	75777	0	0	0
T83	45775	0	0	0
T84	393701	0	0	0
T85	59636	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6458	0	0
T10	222496	1453	0	0
T11	0	1406	0	0
T12	0	1432	0	0
T32	0	709	0	0
T33	0	1458	0	0
T34	113408	0	0	0
T35	910304	0	0	0
T36	556632	0	0	0
T37	2191268	0	0	0
T38	294452	0	0	0
T39	497544	0	0	0
T40	660376	0	0	0
T41	566932	0	0	0
T42	173476	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5378	0	0
T10	222496	1213	0	0
T11	0	1166	0	0
T12	0	1192	0	0
T32	0	589	0	0
T33	0	1218	0	0
T34	113408	0	0	0
T35	910304	0	0	0
T36	556632	0	0	0
T37	2191268	0	0	0
T38	294452	0	0	0
T39	497544	0	0	0
T40	660376	0	0	0
T41	566932	0	0	0
T42	173476	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2039780	2039436	0	0
T2	123788	123568	0	0
T3	1404048	1404016	0	0
T4	1264416	1264380	0	0
T5	121240	120896	0	0
T6	881900	881500	0	0
T7	656040	655724	0	0
T13	431060	431036	0	0
T17	198808	198408	0	0
T18	160408	160144	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T17,T18,T7
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T17,T18,T7

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T17,T7,T6

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T17,T18,T7
1	0	1	Covered	T2,T3,T7
1	1	0	Covered	T17,T18,T7
1	1	1	Covered	T18,T7,T16

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T18,T7,T16
0	1	Covered	T7,T16,T46
1	0	Covered	T7,T16,T48

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T18,T7,T16
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T7,T16,T48

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T18,T7,T16
1	0	Not Covered
1	1	Covered	T7,T16,T46

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T17,T7,T6
1	Covered	T7,T8,T20

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T7,T13,T14
1	Covered	T17,T7,T6

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T17,T7,T6
1	Covered	T7,T13,T27

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T17,T7,T6
1	Covered	T7,T14,T16

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T11,T12

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T17,T7,T15

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T7,T6,T15

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T17,T7,T6

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T17,T7,T13

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T10,T11,T12
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T17,T7,T6
Phase1St	193	Covered	T17,T7,T6
Phase2St	210	Covered	T17,T7,T6
Phase3St	228	Covered	T17,T7,T6
TerminalSt	244	Covered	T17,T7,T6
TimeoutSt	154	Covered	T18,T7,T16

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	279	Covered	T10,T11,T12
IdleSt->Phase0St	147	Covered	T17,T7,T6
IdleSt->TimeoutSt	154	Covered	T18,T7,T16
Phase0St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	189	Covered	T25,T86,T87
Phase0St->Phase1St	193	Covered	T17,T7,T6
Phase1St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	206	Covered	T27,T61,T88
Phase1St->Phase2St	210	Covered	T17,T7,T6
Phase2St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	224	Covered	T16,T27,T89
Phase2St->Phase3St	228	Covered	T17,T7,T6
Phase3St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	240	Covered	T16,T90,T91
Phase3St->TerminalSt	244	Covered	T17,T7,T6
TerminalSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	256	Covered	T17,T7,T14
TimeoutSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	176	Covered	T18,T7,T16
TimeoutSt->Phase0St	167	Covered	T7,T16,T46

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T17,T7,T6
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T18,T7,T16
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T7,T16,T46
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T18,T7,T16
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T18,T7,T16
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T25,T86,T87
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T17,T7,T6
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T17,T7,T6
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T27,T61,T88
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T17,T7,T6
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T17,T7,T6
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T16,T27,T89
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T17,T7,T6
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T17,T7,T6
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T16,T90,T91
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T17,T7,T6
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T17,T7,T6
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T17,T7,T14
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T17,T7,T6
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	697426547	277	0	0
CheckAccumTrig0_A	697426547	520	0	0
CheckAccumTrig1_A	697426547	25	0	0
CheckClr_A	697426547	234	0	0
CheckEn_A	697146246	300638882	0	0
CheckPhase0_A	697426547	596	0	0
CheckPhase1_A	697426547	588	0	0
CheckPhase2_A	697426547	576	0	0
CheckPhase3_A	697426547	569	0	0
CheckTimeout0_A	697426547	623	0	0
CheckTimeoutSt1_A	697426547	82320	0	0
CheckTimeoutSt2_A	697426547	537	0	0
CheckTimeoutStTrig_A	697426547	59	0	0
ErrorStAllEscAsserted_A	697426547	1625	0	0
ErrorStIsTerminal_A	697426547	1355	0	0
u_state_regs_A	697426547	697240114	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	697426547	277	0	0
T10	55624	51	0	0
T11	0	79	0	0
T12	0	53	0	0
T32	0	32	0	0
T33	0	62	0	0
T34	28352	0	0	0
T35	227576	0	0	0
T36	139158	0	0	0
T37	547817	0	0	0
T38	73613	0	0	0
T39	124386	0	0	0
T40	165094	0	0	0
T41	141733	0	0	0
T42	43369	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	697426547	520	0	0
T6	220475	1	0	0
T7	164010	6	0	0
T8	119651	1	0	0
T13	107765	1	0	0
T14	490823	1	0	0
T15	810743	1	0	0
T16	0	7	0	0
T17	49702	1	0	0
T18	40102	0	0	0
T20	0	2	0	0
T43	90302	0	0	0
T44	420698	0	0	0
T45	0	2	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	697426547	25	0	0
T6	220475	0	0	0
T7	164010	1	0	0
T8	119651	0	0	0
T13	107765	0	0	0
T14	490823	0	0	0
T15	810743	0	0	0
T16	957679	1	0	0
T43	90302	0	0	0
T44	420698	0	0	0
T48	0	1	0	0
T54	0	2	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	49538	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	697426547	234	0	0
T6	220475	0	0	0
T7	164010	3	0	0
T8	119651	0	0	0
T13	107765	0	0	0
T14	490823	1	0	0
T15	810743	0	0	0
T16	0	5	0	0
T17	49702	1	0	0
T18	40102	0	0	0
T20	0	1	0	0
T25	0	2	0	0
T27	0	5	0	0
T29	0	1	0	0
T43	90302	0	0	0
T44	420698	0	0	0
T45	0	1	0	0
T66	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	697146246	300638882	0	0
T1	509945	457716	0	0
T2	30947	11136	0	0
T3	351012	347979	0	0
T4	316104	315490	0	0
T5	30310	30223	0	0
T6	220475	9552	0	0
T7	164010	99349	0	0
T13	107765	3486	0	0
T17	49702	44317	0	0
T18	40102	27925	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	697426547	596	0	0
T6	220475	1	0	0
T7	164010	8	0	0
T8	119651	1	0	0
T13	107765	1	0	0
T14	490823	1	0	0
T15	810743	1	0	0
T16	0	9	0	0
T17	49702	1	0	0
T18	40102	0	0	0
T20	0	2	0	0
T43	90302	0	0	0
T44	420698	0	0	0
T45	0	2	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	697426547	588	0	0
T6	220475	1	0	0
T7	164010	8	0	0
T8	119651	1	0	0
T13	107765	1	0	0
T14	490823	1	0	0
T15	810743	1	0	0
T16	0	9	0	0
T17	49702	1	0	0
T18	40102	0	0	0
T20	0	2	0	0
T43	90302	0	0	0
T44	420698	0	0	0
T45	0	2	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	697426547	576	0	0
T6	220475	1	0	0
T7	164010	8	0	0
T8	119651	1	0	0
T13	107765	1	0	0
T14	490823	1	0	0
T15	810743	1	0	0
T16	0	8	0	0
T17	49702	1	0	0
T18	40102	0	0	0
T20	0	2	0	0
T43	90302	0	0	0
T44	420698	0	0	0
T45	0	2	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	697426547	569	0	0
T6	220475	1	0	0
T7	164010	8	0	0
T8	119651	1	0	0
T13	107765	1	0	0
T14	490823	1	0	0
T15	810743	1	0	0
T16	0	7	0	0
T17	49702	1	0	0
T18	40102	0	0	0
T20	0	2	0	0
T43	90302	0	0	0
T44	420698	0	0	0
T45	0	2	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	697426547	623	0	0
T6	220475	0	0	0
T7	164010	6	0	0
T8	119651	0	0	0
T13	107765	0	0	0
T14	490823	0	0	0
T15	810743	0	0	0
T16	0	4	0	0
T18	40102	3	0	0
T21	0	1	0	0
T23	0	7	0	0
T28	0	6	0	0
T43	90302	0	0	0
T44	420698	0	0	0
T45	0	1	0	0
T46	0	2	0	0
T63	49538	0	0	0
T72	0	3	0	0
T73	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	697426547	82320	0	0
T6	220475	0	0	0
T7	164010	682	0	0
T8	119651	0	0	0
T13	107765	0	0	0
T14	490823	0	0	0
T15	810743	0	0	0
T16	0	509	0	0
T18	40102	198	0	0
T21	0	59	0	0
T23	0	1087	0	0
T28	0	651	0	0
T43	90302	0	0	0
T44	420698	0	0	0
T45	0	149	0	0
T46	0	783	0	0
T63	49538	0	0	0
T72	0	351	0	0
T73	0	178	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	697426547	537	0	0
T6	220475	0	0	0
T7	164010	4	0	0
T8	119651	0	0	0
T13	107765	0	0	0
T14	490823	0	0	0
T15	810743	0	0	0
T16	0	2	0	0
T18	40102	3	0	0
T21	0	1	0	0
T23	0	5	0	0
T28	0	6	0	0
T43	90302	0	0	0
T44	420698	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T63	49538	0	0	0
T72	0	3	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	697426547	59	0	0
T6	220475	0	0	0
T7	164010	1	0	0
T8	119651	0	0	0
T13	107765	0	0	0
T14	490823	0	0	0
T15	810743	0	0	0
T16	957679	1	0	0
T23	0	2	0	0
T43	90302	0	0	0
T44	420698	0	0	0
T46	0	1	0	0
T47	0	1	0	0
T52	0	1	0	0
T54	0	1	0	0
T63	49538	0	0	0
T73	0	1	0	0
T77	0	1	0	0
T80	0	3	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	697426547	1625	0	0
T10	55624	366	0	0
T11	0	345	0	0
T12	0	344	0	0
T32	0	205	0	0
T33	0	365	0	0
T34	28352	0	0	0
T35	227576	0	0	0
T36	139158	0	0	0
T37	547817	0	0	0
T38	73613	0	0	0
T39	124386	0	0	0
T40	165094	0	0	0
T41	141733	0	0	0
T42	43369	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	697426547	1355	0	0
T10	55624	306	0	0
T11	0	285	0	0
T12	0	284	0	0
T32	0	175	0	0
T33	0	305	0	0
T34	28352	0	0	0
T35	227576	0	0	0
T36	139158	0	0	0
T37	547817	0	0	0
T38	73613	0	0	0
T39	124386	0	0	0
T40	165094	0	0	0
T41	141733	0	0	0
T42	43369	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	697426547	697240114	0	0
T1	509945	509859	0	0
T2	30947	30892	0	0
T3	351012	351004	0	0
T4	316104	316095	0	0
T5	30310	30224	0	0
T6	220475	220375	0	0
T7	164010	163931	0	0
T13	107765	107759	0	0
T17	49702	49602	0	0
T18	40102	40036	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T3,T5,T17
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T5,T17

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T3,T5,T17

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T17,T18
1	0	1	Covered	T2,T4,T7
1	1	0	Covered	T18,T7,T16
1	1	1	Covered	T5,T18,T7

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T5,T18,T7
0	1	Covered	T7,T16,T20
1	0	Covered	T7,T21,T28

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T5,T18,T7
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T7,T21,T28

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T18,T7
1	0	Covered	T22
1	1	Covered	T7,T16,T20

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T5,T17,T7
1	Covered	T3,T7,T43

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T5,T17
1	Covered	T7,T8,T21

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T5,T7
1	Covered	T17,T7,T15

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T17,T7
1	Covered	T5,T13,T14

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T11,T12

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T3,T5,T7

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T5,T17,T7

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T3,T17,T7

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T3,T5,T17

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T10,T11,T12
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T3,T5,T17
Phase1St	193	Covered	T3,T5,T17
Phase2St	210	Covered	T3,T5,T17
Phase3St	228	Covered	T3,T5,T17
TerminalSt	244	Covered	T3,T5,T17
TimeoutSt	154	Covered	T5,T18,T7

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	279	Covered	T10,T11,T12
IdleSt->Phase0St	147	Covered	T3,T5,T17
IdleSt->TimeoutSt	154	Covered	T5,T18,T7
Phase0St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	189	Covered	T26,T92,T78
Phase0St->Phase1St	193	Covered	T3,T5,T17
Phase1St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	206	Covered	T93,T86,T94
Phase1St->Phase2St	210	Covered	T3,T5,T17
Phase2St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	224	Covered	T7,T95,T80
Phase2St->Phase3St	228	Covered	T3,T5,T17
Phase3St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	240	Covered	T30,T31,T96
Phase3St->TerminalSt	244	Covered	T3,T5,T17
TerminalSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	256	Covered	T7,T13,T14
TimeoutSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	176	Covered	T5,T18,T7
TimeoutSt->Phase0St	167	Covered	T7,T16,T20

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T5,T17
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T18,T7
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T7,T16,T20
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T5,T18,T7
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T5,T18,T7
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T26,T92,T78
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T3,T5,T17
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T3,T5,T17
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T93,T86,T94
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T3,T5,T17
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T3,T5,T17
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T7,T95,T80
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T3,T5,T17
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T3,T5,T17
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T30,T31,T96
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T3,T5,T17
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T3,T5,T17
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T7,T13,T14
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T3,T5,T17
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	697426547	329	0	0
CheckAccumTrig0_A	697426547	832	0	0
CheckAccumTrig1_A	697426547	49	0	0
CheckClr_A	697426547	394	0	0
CheckEn_A	697146246	257086939	0	0
CheckPhase0_A	697426547	941	0	0
CheckPhase1_A	697426547	915	0	0
CheckPhase2_A	697426547	892	0	0
CheckPhase3_A	697426547	874	0	0
CheckTimeout0_A	697426547	863	0	0
CheckTimeoutSt1_A	697426547	106126	0	0
CheckTimeoutSt2_A	697426547	731	0	0
CheckTimeoutStTrig_A	697426547	82	0	0
ErrorStAllEscAsserted_A	697426547	1608	0	0
ErrorStIsTerminal_A	697426547	1338	0	0
u_state_regs_A	697426547	697240114	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	697426547	329	0	0
T10	55624	71	0	0
T11	0	80	0	0
T12	0	66	0	0
T32	0	40	0	0
T33	0	72	0	0
T34	28352	0	0	0
T35	227576	0	0	0
T36	139158	0	0	0
T37	547817	0	0	0
T38	73613	0	0	0
T39	124386	0	0	0
T40	165094	0	0	0
T41	141733	0	0	0
T42	43369	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	697426547	832	0	0
T3	351012	1	0	0
T4	316104	0	0	0
T5	30310	1	0	0
T6	220475	0	0	0
T7	164010	7	0	0
T8	0	2	0	0
T13	107765	1	0	0
T14	490823	2	0	0
T15	0	1	0	0
T17	49702	1	0	0
T18	40102	0	0	0
T43	90302	1	0	0
T44	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	697426547	49	0	0
T6	220475	0	0	0
T7	164010	1	0	0
T8	119651	0	0	0
T13	107765	0	0	0
T14	490823	0	0	0
T15	810743	0	0	0
T16	957679	0	0	0
T21	0	2	0	0
T28	0	1	0	0
T43	90302	0	0	0
T44	420698	0	0	0
T46	0	2	0	0
T47	0	1	0	0
T49	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T63	49538	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	697426547	394	0	0
T6	220475	0	0	0
T7	164010	4	0	0
T8	119651	1	0	0
T13	107765	1	0	0
T14	490823	1	0	0
T15	810743	0	0	0
T16	957679	1	0	0
T21	0	2	0	0
T25	0	4	0	0
T43	90302	0	0	0
T44	420698	0	0	0
T63	49538	0	0	0
T69	0	1	0	0
T70	0	1	0	0
T71	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	697146246	257086939	0	0
T1	509945	491278	0	0
T2	30947	2630	0	0
T3	351012	24276	0	0
T4	316104	312469	0	0
T5	30310	2984	0	0
T6	220475	220374	0	0
T7	164010	66391	0	0
T13	107765	107049	0	0
T17	49702	7427	0	0
T18	40102	30994	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	697426547	941	0	0
T3	351012	1	0	0
T4	316104	0	0	0
T5	30310	1	0	0
T6	220475	0	0	0
T7	164010	10	0	0
T8	0	2	0	0
T13	107765	1	0	0
T14	490823	2	0	0
T15	0	1	0	0
T17	49702	1	0	0
T18	40102	0	0	0
T43	90302	1	0	0
T44	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	697426547	915	0	0
T3	351012	1	0	0
T4	316104	0	0	0
T5	30310	1	0	0
T6	220475	0	0	0
T7	164010	10	0	0
T8	0	2	0	0
T13	107765	1	0	0
T14	490823	2	0	0
T15	0	1	0	0
T17	49702	1	0	0
T18	40102	0	0	0
T43	90302	1	0	0
T44	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	697426547	892	0	0
T3	351012	1	0	0
T4	316104	0	0	0
T5	30310	1	0	0
T6	220475	0	0	0
T7	164010	8	0	0
T8	0	2	0	0
T13	107765	1	0	0
T14	490823	2	0	0
T15	0	1	0	0
T17	49702	1	0	0
T18	40102	0	0	0
T43	90302	1	0	0
T44	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	697426547	874	0	0
T3	351012	1	0	0
T4	316104	0	0	0
T5	30310	1	0	0
T6	220475	0	0	0
T7	164010	8	0	0
T8	0	2	0	0
T13	107765	1	0	0
T14	490823	2	0	0
T15	0	1	0	0
T17	49702	1	0	0
T18	40102	0	0	0
T43	90302	1	0	0
T44	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	697426547	863	0	0
T4	316104	0	0	0
T5	30310	1	0	0
T6	220475	0	0	0
T7	164010	6	0	0
T13	107765	0	0	0
T14	490823	0	0	0
T15	810743	2	0	0
T16	0	5	0	0
T17	49702	0	0	0
T18	40102	1	0	0
T20	0	1	0	0
T21	0	3	0	0
T25	0	5	0	0
T27	0	2	0	0
T43	90302	0	0	0
T45	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	697426547	106126	0	0
T4	316104	0	0	0
T5	30310	224	0	0
T6	220475	0	0	0
T7	164010	1137	0	0
T13	107765	0	0	0
T14	490823	0	0	0
T15	810743	113	0	0
T16	0	1655	0	0
T17	49702	0	0	0
T18	40102	99	0	0
T20	0	7	0	0
T21	0	103	0	0
T25	0	1631	0	0
T27	0	170	0	0
T43	90302	0	0	0
T45	0	52	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	697426547	731	0	0
T4	316104	0	0	0
T5	30310	1	0	0
T6	220475	0	0	0
T7	164010	3	0	0
T13	107765	0	0	0
T14	490823	0	0	0
T15	810743	2	0	0
T16	0	2	0	0
T17	49702	0	0	0
T18	40102	1	0	0
T21	0	1	0	0
T25	0	5	0	0
T27	0	1	0	0
T43	90302	0	0	0
T45	0	1	0	0
T74	0	2	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	697426547	82	0	0
T6	220475	0	0	0
T7	164010	2	0	0
T8	119651	0	0	0
T13	107765	0	0	0
T14	490823	0	0	0
T15	810743	0	0	0
T16	957679	3	0	0
T20	0	1	0	0
T22	0	1	0	0
T23	0	1	0	0
T26	0	1	0	0
T27	0	1	0	0
T43	90302	0	0	0
T44	420698	0	0	0
T46	0	3	0	0
T47	0	1	0	0
T63	49538	0	0	0
T75	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	697426547	1608	0	0
T10	55624	378	0	0
T11	0	347	0	0
T12	0	353	0	0
T32	0	167	0	0
T33	0	363	0	0
T34	28352	0	0	0
T35	227576	0	0	0
T36	139158	0	0	0
T37	547817	0	0	0
T38	73613	0	0	0
T39	124386	0	0	0
T40	165094	0	0	0
T41	141733	0	0	0
T42	43369	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	697426547	1338	0	0
T10	55624	318	0	0
T11	0	287	0	0
T12	0	293	0	0
T32	0	137	0	0
T33	0	303	0	0
T34	28352	0	0	0
T35	227576	0	0	0
T36	139158	0	0	0
T37	547817	0	0	0
T38	73613	0	0	0
T39	124386	0	0	0
T40	165094	0	0	0
T41	141733	0	0	0
T42	43369	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	697426547	697240114	0	0
T1	509945	509859	0	0
T2	30947	30892	0	0
T3	351012	351004	0	0
T4	316104	316095	0	0
T5	30310	30224	0	0
T6	220475	220375	0	0
T7	164010	163931	0	0
T13	107765	107759	0	0
T17	49702	49602	0	0
T18	40102	40036	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T4,T17,T18
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T4,T17,T18
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T17,T18

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T4,T7,T14

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T17,T18,T7
1	0	1	Covered	T13,T8,T44
1	1	0	Covered	T17,T18,T7
1	1	1	Covered	T17,T18,T7

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T17,T18,T7
0	1	Covered	T16,T46,T23
1	0	Covered	T15,T22,T54

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T17,T18,T7
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T15,T22,T54

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T7
1	0	Covered	T23,T97
1	1	Covered	T16,T46,T23

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T4,T7,T14
1	Covered	T14,T15,T45

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T4,T14,T15
1	Covered	T7,T14,T16

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T7,T14,T15
1	Covered	T4,T15,T44

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T4,T7,T14
1	Covered	T14,T8,T20

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T11,T12

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T4,T14,T15

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T7,T14,T15

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T7,T14,T15

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T4,T7,T14

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T10,T11,T12
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T4,T7,T14
Phase1St	193	Covered	T4,T7,T14
Phase2St	210	Covered	T4,T7,T14
Phase3St	228	Covered	T4,T7,T14
TerminalSt	244	Covered	T4,T7,T14
TimeoutSt	154	Covered	T17,T18,T7

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	279	Covered	T10,T11,T12
IdleSt->Phase0St	147	Covered	T4,T7,T14
IdleSt->TimeoutSt	154	Covered	T17,T18,T7
Phase0St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	189	Covered	T21,T51,T98
Phase0St->Phase1St	193	Covered	T4,T7,T14
Phase1St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	206	Covered	T95,T58,T99
Phase1St->Phase2St	210	Covered	T4,T7,T14
Phase2St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	224	Covered	T57,T100,T101
Phase2St->Phase3St	228	Covered	T4,T7,T14
Phase3St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	240	Covered	T67,T25,T23
Phase3St->TerminalSt	244	Covered	T4,T7,T14
TerminalSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	256	Covered	T7,T14,T15
TimeoutSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	176	Covered	T17,T18,T7
TimeoutSt->Phase0St	167	Covered	T15,T16,T22

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T7,T14
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T17,T18,T7
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T15,T16,T22
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T17,T18,T7
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T17,T18,T7
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T21,T51,T98
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T4,T7,T14
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T4,T7,T14
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T95,T58,T99
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T4,T7,T14
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T4,T7,T14
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T57,T100,T101
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T4,T7,T14
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T4,T7,T14
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T67,T25,T23
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T4,T7,T14
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T4,T7,T14
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T14,T15,T45
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T4,T7,T14
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	697426547	302	0	0
CheckAccumTrig0_A	697426547	489	0	0
CheckAccumTrig1_A	697426547	27	0	0
CheckClr_A	697426547	231	0	0
CheckEn_A	697146246	303115397	0	0
CheckPhase0_A	697426547	563	0	0
CheckPhase1_A	697426547	543	0	0
CheckPhase2_A	697426547	535	0	0
CheckPhase3_A	697426547	526	0	0
CheckTimeout0_A	697426547	1000	0	0
CheckTimeoutSt1_A	697426547	104201	0	0
CheckTimeoutSt2_A	697426547	910	0	0
CheckTimeoutStTrig_A	697426547	62	0	0
ErrorStAllEscAsserted_A	697426547	1629	0	0
ErrorStIsTerminal_A	697426547	1359	0	0
u_state_regs_A	697426547	697240114	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	697426547	302	0	0
T10	55624	70	0	0
T11	0	63	0	0
T12	0	81	0	0
T32	0	23	0	0
T33	0	65	0	0
T34	28352	0	0	0
T35	227576	0	0	0
T36	139158	0	0	0
T37	547817	0	0	0
T38	73613	0	0	0
T39	124386	0	0	0
T40	165094	0	0	0
T41	141733	0	0	0
T42	43369	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	697426547	489	0	0
T4	316104	1	0	0
T6	220475	0	0	0
T7	164010	1	0	0
T8	119651	1	0	0
T13	107765	0	0	0
T14	490823	3	0	0
T15	810743	1	0	0
T16	0	3	0	0
T17	49702	0	0	0
T18	40102	0	0	0
T20	0	1	0	0
T21	0	8	0	0
T43	90302	0	0	0
T44	0	1	0	0
T45	0	2	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	697426547	27	0	0
T8	119651	0	0	0
T15	810743	2	0	0
T16	957679	0	0	0
T19	0	1	0	0
T20	41401	0	0	0
T21	153662	0	0	0
T22	0	1	0	0
T29	4765	0	0	0
T44	420698	0	0	0
T45	389657	0	0	0
T54	0	1	0	0
T57	0	1	0	0
T61	0	1	0	0
T63	49538	0	0	0
T64	1236	0	0	0
T102	0	1	0	0
T103	0	1	0	0
T104	0	1	0	0
T105	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	697426547	231	0	0
T8	119651	0	0	0
T14	490823	2	0	0
T15	810743	2	0	0
T16	957679	0	0	0
T20	41401	0	0	0
T21	0	5	0	0
T22	0	4	0	0
T23	0	1	0	0
T25	0	1	0	0
T27	0	1	0	0
T29	4765	0	0	0
T44	420698	0	0	0
T45	389657	1	0	0
T47	0	6	0	0
T63	49538	0	0	0
T64	1236	0	0	0
T67	0	3	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	697146246	303115397	0	0
T1	509945	280961	0	0
T2	30947	26346	0	0
T3	351012	350321	0	0
T4	316104	16823	0	0
T5	30310	30223	0	0
T6	220475	217143	0	0
T7	164010	138889	0	0
T13	107765	107469	0	0
T17	49702	44329	0	0
T18	40102	6407	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	697426547	563	0	0
T4	316104	1	0	0
T6	220475	0	0	0
T7	164010	1	0	0
T8	119651	1	0	0
T13	107765	0	0	0
T14	490823	3	0	0
T15	810743	3	0	0
T16	0	4	0	0
T17	49702	0	0	0
T18	40102	0	0	0
T20	0	1	0	0
T21	0	7	0	0
T43	90302	0	0	0
T44	0	1	0	0
T45	0	2	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	697426547	543	0	0
T4	316104	1	0	0
T6	220475	0	0	0
T7	164010	1	0	0
T8	119651	1	0	0
T13	107765	0	0	0
T14	490823	3	0	0
T15	810743	3	0	0
T16	0	4	0	0
T17	49702	0	0	0
T18	40102	0	0	0
T20	0	1	0	0
T21	0	7	0	0
T43	90302	0	0	0
T44	0	1	0	0
T45	0	2	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	697426547	535	0	0
T4	316104	1	0	0
T6	220475	0	0	0
T7	164010	1	0	0
T8	119651	1	0	0
T13	107765	0	0	0
T14	490823	3	0	0
T15	810743	3	0	0
T16	0	4	0	0
T17	49702	0	0	0
T18	40102	0	0	0
T20	0	1	0	0
T21	0	7	0	0
T43	90302	0	0	0
T44	0	1	0	0
T45	0	2	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	697426547	526	0	0
T4	316104	1	0	0
T6	220475	0	0	0
T7	164010	1	0	0
T8	119651	1	0	0
T13	107765	0	0	0
T14	490823	3	0	0
T15	810743	3	0	0
T16	0	4	0	0
T17	49702	0	0	0
T18	40102	0	0	0
T20	0	1	0	0
T21	0	7	0	0
T43	90302	0	0	0
T44	0	1	0	0
T45	0	2	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	697426547	1000	0	0
T6	220475	0	0	0
T7	164010	5	0	0
T8	119651	0	0	0
T13	107765	0	0	0
T14	490823	0	0	0
T15	810743	5	0	0
T16	0	3	0	0
T17	49702	1	0	0
T18	40102	7	0	0
T21	0	2	0	0
T25	0	1	0	0
T27	0	13	0	0
T28	0	15	0	0
T43	90302	0	0	0
T44	420698	0	0	0
T66	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	697426547	104201	0	0
T6	220475	0	0	0
T7	164010	356	0	0
T8	119651	0	0	0
T13	107765	0	0	0
T14	490823	0	0	0
T15	810743	350	0	0
T16	0	827	0	0
T17	49702	155	0	0
T18	40102	479	0	0
T21	0	477	0	0
T25	0	186	0	0
T27	0	1968	0	0
T28	0	1674	0	0
T43	90302	0	0	0
T44	420698	0	0	0
T66	0	54	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	697426547	910	0	0
T6	220475	0	0	0
T7	164010	5	0	0
T8	119651	0	0	0
T13	107765	0	0	0
T14	490823	0	0	0
T15	810743	3	0	0
T16	0	2	0	0
T17	49702	1	0	0
T18	40102	7	0	0
T21	0	2	0	0
T25	0	1	0	0
T27	0	13	0	0
T28	0	15	0	0
T43	90302	0	0	0
T44	420698	0	0	0
T66	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	697426547	62	0	0
T9	747501	0	0	0
T16	957679	1	0	0
T20	41401	0	0	0
T21	153662	0	0	0
T23	0	1	0	0
T27	462299	0	0	0
T29	4765	0	0	0
T45	389657	0	0	0
T46	0	1	0	0
T50	0	2	0	0
T54	0	1	0	0
T57	0	1	0	0
T64	1236	0	0	0
T65	122730	0	0	0
T66	41642	0	0	0
T80	0	1	0	0
T81	0	2	0	0
T106	0	4	0	0
T107	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	697426547	1629	0	0
T10	55624	364	0	0
T11	0	358	0	0
T12	0	365	0	0
T32	0	170	0	0
T33	0	372	0	0
T34	28352	0	0	0
T35	227576	0	0	0
T36	139158	0	0	0
T37	547817	0	0	0
T38	73613	0	0	0
T39	124386	0	0	0
T40	165094	0	0	0
T41	141733	0	0	0
T42	43369	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	697426547	1359	0	0
T10	55624	304	0	0
T11	0	298	0	0
T12	0	305	0	0
T32	0	140	0	0
T33	0	312	0	0
T34	28352	0	0	0
T35	227576	0	0	0
T36	139158	0	0	0
T37	547817	0	0	0
T38	73613	0	0	0
T39	124386	0	0	0
T40	165094	0	0	0
T41	141733	0	0	0
T42	43369	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	697426547	697240114	0	0
T1	509945	509859	0	0
T2	30947	30892	0	0
T3	351012	351004	0	0
T4	316104	316095	0	0
T5	30310	30224	0	0
T6	220475	220375	0	0
T7	164010	163931	0	0
T13	107765	107759	0	0
T17	49702	49602	0	0
T18	40102	40036	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	44	97.78
Logical	45	44	97.78
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Covered	T19
1	1	1	Covered	T1,T3,T4

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T17,T18,T7
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T17,T7,T16
1	1	1	Covered	T17,T18,T7

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T17,T18,T7
0	1	Covered	T27,T28,T23
1	0	Covered	T16,T46,T47

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T17,T18,T7
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T16,T46,T47

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T7
1	0	Covered	T24
1	1	Covered	T27,T28,T23

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T17
1	Covered	T4,T44,T16

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T7,T14,T16

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T7
1	Covered	T3,T17,T14

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T4,T17
1	Covered	T1,T7,T15

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T11,T12

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T3,T4

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T3,T17,T7

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T7,T14

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T3,T7

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T10,T11,T12
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T1,T3,T4
Phase1St	193	Covered	T1,T3,T4
Phase2St	210	Covered	T1,T3,T4
Phase3St	228	Covered	T1,T3,T4
TerminalSt	244	Covered	T1,T3,T4
TimeoutSt	154	Covered	T17,T18,T7

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	279	Covered	T10,T11,T12
IdleSt->Phase0St	147	Covered	T1,T3,T4
IdleSt->TimeoutSt	154	Covered	T17,T18,T7
Phase0St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	189	Covered	T16,T108,T109
Phase0St->Phase1St	193	Covered	T1,T3,T4
Phase1St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	206	Covered	T14,T28,T89
Phase1St->Phase2St	210	Covered	T1,T3,T4
Phase2St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	224	Covered	T29,T21,T27
Phase2St->Phase3St	228	Covered	T1,T3,T4
Phase3St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	240	Covered	T54,T110,T19
Phase3St->TerminalSt	244	Covered	T1,T3,T4
TerminalSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	256	Covered	T4,T7,T14
TimeoutSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	176	Covered	T17,T18,T7
TimeoutSt->Phase0St	167	Covered	T16,T27,T28

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T17,T18,T7
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T16,T27,T28
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T17,T18,T7
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T17,T18,T7
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T16,T108,T109
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T3,T4
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T3,T4
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T14,T28,T89
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T3,T4
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T3,T4
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T29,T21,T27
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T3,T4
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T3,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T54,T110,T19
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T3,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T3,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T4,T7,T14
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T3,T4
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	697426547	273	0	0
CheckAccumTrig0_A	697426547	535	0	0
CheckAccumTrig1_A	697426547	24	0	0
CheckClr_A	697426547	255	0	0
CheckEn_A	697146246	291905940	0	0
CheckPhase0_A	697426547	615	0	0
CheckPhase1_A	697426547	599	0	0
CheckPhase2_A	697426547	585	0	0
CheckPhase3_A	697426547	578	0	0
CheckTimeout0_A	697426547	1346	0	0
CheckTimeoutSt1_A	697426547	158132	0	0
CheckTimeoutSt2_A	697426547	1255	0	0
CheckTimeoutStTrig_A	697426547	64	0	0
ErrorStAllEscAsserted_A	697426547	1596	0	0
ErrorStIsTerminal_A	697426547	1326	0	0
u_state_regs_A	697426547	697240114	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	697426547	273	0	0
T10	55624	52	0	0
T11	0	71	0	0
T12	0	67	0	0
T32	0	26	0	0
T33	0	57	0	0
T34	28352	0	0	0
T35	227576	0	0	0
T36	139158	0	0	0
T37	547817	0	0	0
T38	73613	0	0	0
T39	124386	0	0	0
T40	165094	0	0	0
T41	141733	0	0	0
T42	43369	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	697426547	535	0	0
T1	509945	1	0	0
T2	30947	0	0	0
T3	351012	1	0	0
T4	316104	1	0	0
T5	30310	0	0	0
T6	220475	0	0	0
T7	164010	4	0	0
T13	107765	0	0	0
T14	0	4	0	0
T15	0	1	0	0
T16	0	5	0	0
T17	49702	1	0	0
T18	40102	0	0	0
T44	0	1	0	0
T45	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	697426547	24	0	0
T9	747501	0	0	0
T16	957679	2	0	0
T20	41401	0	0	0
T21	153662	0	0	0
T27	462299	0	0	0
T29	4765	0	0	0
T45	389657	0	0	0
T46	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T54	0	1	0	0
T56	0	2	0	0
T59	0	1	0	0
T64	1236	0	0	0
T65	122730	0	0	0
T66	41642	0	0	0
T89	0	1	0	0
T111	0	1	0	0
T112	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	697426547	255	0	0
T4	316104	1	0	0
T6	220475	0	0	0
T7	164010	1	0	0
T8	119651	0	0	0
T13	107765	0	0	0
T14	490823	3	0	0
T15	810743	0	0	0
T16	0	3	0	0
T17	49702	0	0	0
T18	40102	0	0	0
T21	0	4	0	0
T25	0	2	0	0
T27	0	5	0	0
T29	0	1	0	0
T43	90302	0	0	0
T45	0	1	0	0
T68	0	6	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	697146246	291905940	0	0
T1	509945	179191	0	0
T2	30947	19535	0	0
T3	351012	2624	0	0
T4	316104	314724	0	0
T5	30310	30223	0	0
T6	220475	220374	0	0
T7	164010	222724	0	0
T13	107765	107591	0	0
T17	49702	30159	0	0
T18	40102	590	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	697426547	615	0	0
T1	509945	1	0	0
T2	30947	0	0	0
T3	351012	1	0	0
T4	316104	1	0	0
T5	30310	0	0	0
T6	220475	0	0	0
T7	164010	4	0	0
T13	107765	0	0	0
T14	0	4	0	0
T15	0	1	0	0
T16	0	6	0	0
T17	49702	1	0	0
T18	40102	0	0	0
T44	0	1	0	0
T45	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	697426547	599	0	0
T1	509945	1	0	0
T2	30947	0	0	0
T3	351012	1	0	0
T4	316104	1	0	0
T5	30310	0	0	0
T6	220475	0	0	0
T7	164010	4	0	0
T13	107765	0	0	0
T14	0	3	0	0
T15	0	1	0	0
T16	0	6	0	0
T17	49702	1	0	0
T18	40102	0	0	0
T44	0	1	0	0
T45	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	697426547	585	0	0
T1	509945	1	0	0
T2	30947	0	0	0
T3	351012	1	0	0
T4	316104	1	0	0
T5	30310	0	0	0
T6	220475	0	0	0
T7	164010	4	0	0
T13	107765	0	0	0
T14	0	3	0	0
T15	0	1	0	0
T16	0	6	0	0
T17	49702	1	0	0
T18	40102	0	0	0
T44	0	1	0	0
T45	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	697426547	578	0	0
T1	509945	1	0	0
T2	30947	0	0	0
T3	351012	1	0	0
T4	316104	1	0	0
T5	30310	0	0	0
T6	220475	0	0	0
T7	164010	4	0	0
T13	107765	0	0	0
T14	0	3	0	0
T15	0	1	0	0
T16	0	6	0	0
T17	49702	1	0	0
T18	40102	0	0	0
T44	0	1	0	0
T45	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	697426547	1346	0	0
T6	220475	0	0	0
T7	164010	3	0	0
T8	119651	0	0	0
T13	107765	0	0	0
T14	490823	0	0	0
T15	810743	0	0	0
T16	0	18	0	0
T17	49702	1	0	0
T18	40102	9	0	0
T22	0	1	0	0
T25	0	1	0	0
T27	0	1	0	0
T28	0	8	0	0
T43	90302	0	0	0
T44	420698	0	0	0
T46	0	2	0	0
T66	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	697426547	158132	0	0
T6	220475	0	0	0
T7	164010	191	0	0
T8	119651	0	0	0
T13	107765	0	0	0
T14	490823	0	0	0
T15	810743	0	0	0
T16	0	3542	0	0
T17	49702	64	0	0
T18	40102	551	0	0
T22	0	110	0	0
T25	0	15	0	0
T27	0	94	0	0
T28	0	779	0	0
T43	90302	0	0	0
T44	420698	0	0	0
T46	0	235	0	0
T66	0	117	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	697426547	1255	0	0
T6	220475	0	0	0
T7	164010	3	0	0
T8	119651	0	0	0
T13	107765	0	0	0
T14	490823	0	0	0
T15	810743	0	0	0
T16	0	15	0	0
T17	49702	1	0	0
T18	40102	9	0	0
T22	0	1	0	0
T25	0	1	0	0
T28	0	7	0	0
T43	90302	0	0	0
T44	420698	0	0	0
T46	0	1	0	0
T66	0	2	0	0
T73	0	7	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	697426547	64	0	0
T23	0	1	0	0
T25	430616	0	0	0
T27	462299	1	0	0
T28	0	1	0	0
T47	0	1	0	0
T54	0	3	0	0
T67	435338	0	0	0
T68	136219	0	0	0
T69	80226	0	0	0
T74	48493	0	0	0
T75	0	1	0	0
T76	0	1	0	0
T78	0	1	0	0
T79	0	1	0	0
T81	0	1	0	0
T82	75777	0	0	0
T83	45775	0	0	0
T84	393701	0	0	0
T85	59636	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	697426547	1596	0	0
T10	55624	345	0	0
T11	0	356	0	0
T12	0	370	0	0
T32	0	167	0	0
T33	0	358	0	0
T34	28352	0	0	0
T35	227576	0	0	0
T36	139158	0	0	0
T37	547817	0	0	0
T38	73613	0	0	0
T39	124386	0	0	0
T40	165094	0	0	0
T41	141733	0	0	0
T42	43369	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	697426547	1326	0	0
T10	55624	285	0	0
T11	0	296	0	0
T12	0	310	0	0
T32	0	137	0	0
T33	0	298	0	0
T34	28352	0	0	0
T35	227576	0	0	0
T36	139158	0	0	0
T37	547817	0	0	0
T38	73613	0	0	0
T39	124386	0	0	0
T40	165094	0	0	0
T41	141733	0	0	0
T42	43369	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	697426547	697240114	0	0
T1	509945	509859	0	0
T2	30947	30892	0	0
T3	351012	351004	0	0
T4	316104	316095	0	0
T5	30310	30224	0	0
T6	220475	220375	0	0
T7	164010	163931	0	0
T13	107765	107759	0	0
T17	49702	49602	0	0
T18	40102	40036	0	0